Partitioning chaining for large-scale phased array systems.

Abstract

Aspects described herein include devices and methods using chain routing of signals for large-scale antenna arrays. In some aspects, an apparatus is provided that includes a first millimeter wave (mmW) transceiver having a first port, a second port, one or more antenna elements, multiple chain mmW transceiver ports, and a switching circuit. The switching circuit is controllable by control data to route a portion of the merged clock and data signals and the merged control and data signals between a first route between one or more antenna elements and the first port, a second route between one or more antenna elements and the second port, a third route between the first port and the multiple chain mmW transceiver ports, and a fourth route between the second port and the multiple chain mmW transceiver ports.

Description

[Technical field]

[0001] For example, aspects of the present disclosure relate to large scale phased array systems and routing used to provide signals to circuits related to large scale phased array antenna systems. [Background technology]

[0002] Wireless communication devices and technologies are becoming increasingly prevalent. Wireless communication devices generally transmit and receive communication signals. The communication signals are typically processed by a variety of different components and circuits. In some modern communication systems, phased array antennas are used to improve system operation through link budget, system capacity, beamforming, multiple-input multiple-output (MIMO) communications, and other such system operation improvements. Supporting such systems can involve complex system design choices and managing complex interactions between device elements and signals. Summary of the Invention

[0003] Various implementations of the systems, methods, and devices within the scope of the appended claims each have several aspects, no one of which is solely responsible for the desirable attributes described herein. Without limiting the scope of the appended claims, some prominent features are described herein.

[0004] Aspects described herein include devices, wireless communication devices, circuits, and modules that support millimeter wavelength (mmW) communication. mmW communication is part of a fifth generation communication system that uses electromagnetic waves from about 20 gigahertz (GHz) to 300 GHz. Furthermore, mmW communication can also be part of other systems, such as WiFi, radar, and / or sensing systems. Certain mmW networks use beamforming systems with large array sizes (e.g., hundreds or thousands of antenna elements). Such systems can be used to improve link budgets and system capacity while supporting various communication technologies. In conventional approaches, 1:2 diplexers or 1:4 diplexers are used in combination to provide signal routing from communication data sources to antenna elements in an array, with each antenna element having an independent circuit (e.g., phase shift circuit, etc.) to control the signal for the particular antenna element. The use of 1:2 or 1:4 splitters (e.g., or other such one-to-many splitters) creates significant design challenges, such as the need to manage control (CTRL) and clock (CLK) signals that can be combined with data signals. Aspects described herein include devices in which chain routing (e.g., daisy-chain configurations) are used instead of one-to-many splitters in configurations to provide combined control / data and combined clock / data signals from an intermediate frequency (IF) transceiver device to a series of millimeter wave (mmW) transceiver devices. Improvements to such devices can reduce or completely omit splitters for cost savings while also improving performance, while supporting large-scale phased array systems using commonly small transceivers with a limited number of ports. Furthermore, in some aspects, the daisy-chain mmW transceiver structure uses only four low-frequency routings and does not require a direct current (DC) chain power supply to address drop issues when large-scale phased arrays are operated simultaneously.

[0005] In some aspects, a wireless communication apparatus is provided that includes a first millimeter wave (mmW) transceiver including: a first port for communicating merged control and data signals; a second port for communicating merged clock and data signals associated with the merged control and data signals; one or more antenna elements; a plurality of chain mmW transceiver ports; and a switching circuit controllable by control data to route the merged clock and data signals and portions of the merged control and data signals between a first route between the one or more antenna elements and the first port, a second route between the one or more antenna elements and the second port, a third route between the first port and the plurality of chain mmW transceiver ports, and a fourth route between the second port and the plurality of chain mmW transceiver ports.

[0006] In some aspects, the wireless communications apparatus further comprises a second mmW transceiver including a first port coupled to a first data port of the plurality of chained mmW transceiver ports and a second port coupled to a second data port of the plurality of chained mmW transceiver ports.

[0007] In some aspects, the first data port is a chain control and data port coupled to a first multiplexing diplexer of the first mmW transceiver, and the second data port is a chain clock and data port coupled to a second multiplexing diplexer of the first mmW transceiver.

[0008] In some aspects, the second mmW transceiver further includes a second clock port coupled to the first clock port of the plurality of chain mmW transceiver ports as part of the chain clock path.

[0009] In some aspects, the second mmW transceiver further includes a second control port coupled to the first control port of the plurality of chain mmW transceiver ports as part of the chain control path.

[0010] In some aspects, the first mmW transceiver includes a first demultiplexing diplexer that couples a first port of the first mmW transceiver to a first data port and a first clock port to demultiplex the merged clock and data signals into separate clock and data signals.

[0011] In some aspects, the first mmW transceiver includes a second demultiplexing diplexer that couples a second port of the first mmW transceiver to a second data port and to the first control port for demultiplexing the merged control and data signals into separate control and data signals.

[0012] In some aspects, the first mmW transceiver further includes a first frequency conversion circuit in the first route configured to convert a first data signal associated with the merged control and data signal between an IF frequency and an mmW frequency, and a second frequency conversion circuit in the second route configured to convert a second data signal associated with the merged clock and data signal between the IF frequency and the mmW frequency.

[0013] In some aspects, the first mmW transceiver further includes a first frequency conversion circuit in the first route configured to convert a first data signal associated with the merged control and data signal between an IF frequency and an mmW frequency, and a second frequency conversion circuit in the second route configured to convert a second data signal associated with the merged clock and data signal between the IF frequency and the mmW frequency.

[0014] In some aspects, the second mmW transceiver further includes one or more second antenna elements and a second switching circuit controllable by control data to select between a fifth route coupling the first port to the one or more antenna elements as well as a sixth route coupling the second port to the one or more antenna elements, a seventh route coupling the first port to a first chain data port of the second mmW transceiver as well as an eighth route coupling the second port to a second chain data port of the second mmW transceiver.

[0015] In some aspects, the second mmW transceiver further includes a first frequency conversion circuit in a fifth route configured to convert a first data signal associated with the merged control and data signal between an IF frequency and an mmW frequency, and a second frequency conversion circuit in a sixth route configured to convert a second data signal associated with the merged clock and data signal between the IF frequency and the mmW frequency.

[0016] In some aspects, the wireless communications apparatus further comprises a third mmW transceiver including one or more third antenna elements, a first port coupled to the first chain data port, the first port configured to communicate a first data signal associated with the merged control and data signal with the second mmW transceiver, a second port coupled to the second chain data port, the second port configured to communicate a second data signal associated with the merged clock and data signal with the second mmW transceiver, a third port coupled to the chain control port of the second mmW transceiver, the third port configured to communicate a control signal associated with the merged control and data signal, and a fourth port coupled to the chain clock port of the second mmW transceiver, the fourth port configured to communicate a clock signal associated with the merged clock and data signal.

[0017] In some aspects, the wireless communications apparatus further comprises a processor and an intermediate frequency (IF) transceiver coupled to the processor, the IF transceiver including an IF merged clock and data port coupled to a first port of the first mmW transceiver as part of a merged clock and data path for merged clock and data signals, and an IF merged control and data port coupled to a second port of the first mmW transceiver as part of a merged control and data path for merged control and data signals.

[0018] In some aspects, the wireless communications device is configured to transmit the first data signal and the second data signal via one or more third antenna elements using the first data signal, the second data signal, a clock signal, and a control signal received from the IF transceiver via the first mmW transceiver and the second mmW transceiver.

[0019] In some aspects, the wireless communications device is configured to receive a first data signal, a second data signal, a clock signal, and a control signal at one or more third antennas; communicate the first data signal and the control signal via the second mmW transceiver and the first mmW transceiver to an IF merge control and data port of the IF transceiver; communicate the second data signal and the clock signal via the second mmW transceiver and the first mmW transceiver to an IF merge clock and data port of the IF transceiver; and process the data signals using the processor.

[0020] In some aspects, the first mmW transceiver is configured to merge the first data signal and the control signal into a merged control and data signal using a first diplexer, and the first mmW transceiver is configured to merge the second data signal and the control signal into a merged clock and data signal using a second diplexer.

[0021] In some aspects, the wireless communication device further comprises a display screen; and a control circuit coupled to the display screen and the first mmW transceiver and configured to transmit and receive data using daisy chain routing that includes the first mmW transceiver.

[0022] In some aspects, the first route includes a first transmit path variable gain amplifier (VGA), a first receive path VGA coupled between the first port and the one or more antenna elements, and a switching circuit for selecting between the first transmit path VGA and the first receive path VGA, and the second route includes a second transmit path VGA, a second receive path VGA coupled between the second port and the one or more antenna elements, and a switching circuit for selecting between the second transmit path VGA and the second receive path VGA.

[0023] In some aspects, the third route includes a first receive signal path VGA buffer, a first transmit signal path VGA buffer, and a switching circuit for selecting between the first receive signal path VGA buffer and the first transmit signal path VGA buffer, and the fourth route includes a second receive signal path VGA buffer, a second transmit signal path VGA buffer, and a switching circuit configured to select between the second receive signal path VGA buffer and the second transmit signal path VGA buffer.

[0024] In some aspects, a method is provided that includes generating a first analog data signal and a second analog data signal; generating control data and clock data for the first analog data signal and the second analog data signal; merging the control data and the first analog data signal by an intermediate frequency (IF) transceiver to generate a merged control and data signal; merging the clock data and the second analog data signal by the IF transceiver to generate a merged clock and data signal; and communicating the first analog data signal and the second analog data signal between the IF transceiver and a target mmW transceiver via daisy chain routing, the daisy chain routing including at least the first mmW transceiver in the daisy chain routing between the IF transceiver and the target mmW transceiver.

[0025] In some aspects, the method further includes splitting the merged control and data signals using a first diplexer of the first mmW transceiver between the IF transceiver and the target mmW transceiver, splitting the merged clock and data signals using a second diplexer of the first mmW transceiver between the IF transceiver and the target mmW transceiver, and routing, by the first mmW transceiver, the clock signal, the control signal, the first analog data signal, and the second analog data signal to the target mmW transceiver.

[0026] In some aspects, the method further includes receiving, at one or more antennas of the target mmW transceiver, a third analog data signal, a fourth analog data signal, a second control signal, and a second clock signal, and downconverting the third analog data signal and the fourth analog data signal from an mmW frequency to an IF frequency using frequency conversion circuitry of the target mmW transceiver.

[0027] In some aspects, the method further includes communicating a third analog data signal, a fourth analog data signal, a second control signal, and a second clock signal from the target mmW transceiver to the first mmW transceiver, merging the second control signal and the third analog data signal by a first diplexer of the first mmW transceiver to generate a second merged control and data signal, and merging the clock data and the second analog data signal by a second diplexer of the first mmW transceiver to generate a second merged clock and data signal.

[0028] In some aspects, the method further includes communicating a second merged control and data signal and a second merged clock and data signal from the first mmW transceiver to the IF transceiver, generating a second analog data signal by the IF transceiver using the second merged control and data signal and the second merged clock and data signal, converting the second analog data signal to a second digital data signal using an analog-to-digital converter coupled to the IF transceiver, and processing the second digital data signal using a processor coupled to the analog-to-digital converter.

[0029] In some aspects, another device is provided that includes a first millimeter wave (mmW) transceiver and a second mmW transceiver coupled to the first mmW transceiver via a daisy-chain routing path. In some aspects, the first mmW transceiver includes a plurality of intermediate frequency (IF) transceiver connection ports, one or more antenna elements, and a switching circuit configured to select between connecting the plurality of IF transceiver connection ports to the one or more antenna elements and connecting the plurality of IF transceiver connection ports to the second mmW transceiver via the daisy-chain routing path.

[0030] In some aspects, the first mmW transceiver further includes a first diplexer coupled to a first port of the multiple IF transceiver connection ports, to a first data port of the second mmW transceiver, and to a control port of the second mmW transceiver, the first diplexer configured for bidirectional operation to convert between merged control and data signals communicated with the IF transceiver via the first port and separate control signal and first data signals communicated with the second mmW transceiver via the control port and the first data port, and the daisy-chain routing path includes the control port and the first data port.

[0031] In some aspects, the first mmW transceiver further includes a second diplexer coupled to a second port of the multiple IF transceiver connection ports, to a second data port of the second mmW transceiver, and to a clock port of the second mmW transceiver, the second diplexer configured for bidirectional operation to convert between a merged clock and data signal communicated with the IF transceiver via the second port and separate clock and second data signals communicated with the second mmW transceiver via the control port and the second data port, and the daisy-chain routing path includes the clock port and the second data port.

[0032] In some aspects, the above-mentioned apparatus may include a mobile device having a camera for capturing one or more pictures. In some aspects, the above-mentioned apparatus may include a display screen for displaying one or more pictures. In some aspects, additional wireless communication circuitry (e.g., non-mmW communication circuitry) is provided. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used alone to determine the scope of the claimed subject matter. The subject matter should be understood by reference to appropriate portions of the entire specification, any or all drawings, and the claims.

[0033] The foregoing, together with other features and embodiments, will become more apparent with reference to the following specification, claims, and accompanying drawings.

[0034] In the figures, like reference numerals refer to like parts throughout the various figures unless otherwise indicated. For reference numerals having a letter designation, such as "102a" or "102b," the letter designation can distinguish between two similar parts or elements present in the same figure. If the reference numeral is intended to encompass all parts having the same reference numeral in all figures, the letter designation for the reference numeral can be omitted. [Brief description of the drawings]

[0035] [Figure 1] FIG. 1 illustrates a wireless communication system for communicating with a wireless device, which can be implemented in accordance with aspects described herein. [Figure 2A] FIG. 1 is a block diagram illustrating portions of a wireless device in which aspects of the present disclosure may be implemented. [Figure 2B] FIG. 1 is a block diagram illustrating portions of a wireless device in which aspects of the present disclosure may be implemented. [Figure 2C]1 is a block diagram illustrating aspects of a wireless device capable of implementing aspects of the present disclosure. [Figure 2D] 1 is a block diagram illustrating aspects of a wireless device capable of implementing aspects of the present disclosure. [Figure 3A] FIG. 1 illustrates aspects of an apparatus including chain signal routing for a large phased array, according to some aspects. [Figure 3B] FIG. 1 illustrates aspects of a mmW transceiver for use in chain signal routing for large scale phased arrays, according to some aspects. [Figure 4] FIG. 1 illustrates aspects of a transmit (Tx) path in an mmW transceiver for use in chain signal routing for a large phased array, in accordance with some aspects. [Diagram 5] FIG. 1 illustrates aspects of a receive (Rx) path in an mmW transceiver for use in chain signal routing for a large phased array, in accordance with some aspects. [Figure 6A] FIG. 1 illustrates aspects of an apparatus including chain signal routing for a large phased array, according to some aspects. [Figure 6B] FIG. 1 illustrates aspects of a mmW transceiver for use in chain signal routing for large scale phased arrays, according to some aspects. [Figure 6C] FIG. 1 illustrates aspects of a mmW transceiver for use in chain signal routing for large scale phased arrays, according to some aspects. [Figure 7A] FIG. 1 is a block diagram illustrating an mmW module according to aspects of the present disclosure. [Figure 7B] FIG. 1 is a block diagram illustrating an mmW module according to aspects of the present disclosure. [Figure 8] FIG. 1 is a flow diagram illustrating an example of a method of operation of a device including chain signal routing for a large phased array, in accordance with some aspects. [Figure 9]FIG. 1 is a functional block diagram of an apparatus including chain signal routing for a large phased array, in accordance with some aspects. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] The Detailed Description set forth below in connection with the accompanying drawings is intended as a description of exemplary implementations and is not intended to represent the only implementations in which the present invention may be practiced. As used herein, the term "exemplary" means "serving as an example, instance, or illustration" and should not necessarily be construed as preferred or advantageous over other exemplary implementations. The Detailed Description includes specific details intended to provide a thorough understanding of the exemplary implementations. In some instances, some devices are shown in block diagram form. Drawing elements that are common among the following figures may be identified using the same reference numerals.

[0037] Advances in wireless communications infrastructure, particularly for 3rd Generation Partnership Project (3GPP®) fifth generation (5G) millimeter-wavelength (mmW) systems, involve the use of antenna arrays with tens, hundreds, or thousands of elements. 5G systems have performance criteria where improved link budget and improved wireless coverage performance within devices are key design considerations. Signal delivery routing for antenna arrays with fewer antenna elements often uses one-to-many splitters, such as 1:2 or 1:4 splitters. Such splitters can introduce significant splitter losses in the signal path, increasing module area and cost, and can bring additional challenges associated with the use of merged control, clock, and data signals. For example, in some implementations, to accommodate 1:2 or 1:4 splitters, the IF transceiver requires a higher control / data or clock / data swing, which limits the total number of antenna array sizes with a given number of ports from intermediate frequency (IF) transceivers and mmW transceivers. Furthermore, some systems use DC chain power supplies and implement configurations to address voltage drop concerns when large phased arrays operate simultaneously. Some aspects described herein are limited to only four low frequency routings or other small number of low frequency routings (e.g., two, four, etc.). Such aspects can reduce or eliminate issues with DC chain power supplies used to address voltage drop concerns when large phased arrays in a single mmW device operate simultaneously.

[0038] According to described aspects, devices are described that include transceivers (e.g., intermediate frequency (IF) transceivers and mmW transceivers) that use chain signal paths instead of one-to-many (e.g., 1:2, 1:4, etc.) splitters to route data signals, control signals, and clock signals. Apparatus and devices according to such aspects can provide flexibility in signal routing and lower loss in paths for such routing in some implementations. Such characteristics improve device performance in the context of large arrays of antenna elements for beamforming systems and other such systems in communication devices. Such performance can be used to improve 5G user equipment or terminals (UE), customer premises equipment (CPE), small cells (FSM) of 5G wireless area networks, and base stations (CSM) of 5G wireless area networks. Further details regarding aspects of the present disclosure are described with respect to the figures.

[0039] FIG. 1 illustrates a wireless device 110 communicating with a wireless communication system 120. According to aspects described herein, the wireless device may include a transceiver configured for chain signal routing according to aspects described herein. The wireless communication system 120 may be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a Wireless Local Area Network (WLAN) system, a 5G New Radio (NR) system, or some other wireless system. The CDMA system may implement Wideband CDMA (WCDMA), CDMA 1X, Evolution Data Optimized (EVDO), Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. Communication elements of the wireless device 110 for implementing mmW and non-mmW communications according to any such communication standard may be supported by transceivers of various designs using chain signal routing. 1 shows wireless communications system 120 including two base stations 130 and 132, and one system controller 140. In general, a wireless communications system may include any number of base stations and any set of network entities.

[0040] The wireless device 110 may also be referred to as a user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, a station, etc. The wireless device 110 may be a cellular phone, a smartphone, a tablet, or other such mobile device (e.g., a device integrated with a display screen). Other examples of the wireless device 110 include a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smartbook, a netbook, a tablet, a cordless phone, a medical device, a device configured to connect to one or more other devices (e.g., via the Internet of Things), a wireless local loop (WLL) station, a Bluetooth device, etc. The wireless device 110 may communicate with the wireless communication system 120. The wireless device 110 may also receive signals from a broadcast station (e.g., a broadcast station 134) and / or from a satellite (e.g., a satellite 150 in one or more Global Navigation Satellite Systems (GNSS)). The wireless device 110 may support one or more radio technologies for wireless communication, such as LTE, WCDMA, CDMA 1X, EVDO, TD-SCDMA, GSM, 802.11, 5G, etc.

[0041] The wireless communication system 120 may also include a wireless device 160. In an exemplary embodiment, the wireless device 160 may be a wireless access point or another wireless communication device that constitutes or constitutes a part of a wireless local area network (WLAN). In an exemplary embodiment, the wireless device 110 may be configured as a customer premises equipment (CPE) capable of communicating with a base station 130 and another wireless device 110 or with other devices in the wireless communication system 120. In some embodiments, the CPE may be configured to communicate with the wireless device 160 using WAN signaling and interface with the base station 130 based on such communication, instead of the wireless device 160 communicating directly with the base station 130. In an exemplary embodiment in which the wireless device 160 is configured to communicate using WLAN signaling, the WLAN signals may include WiFi or other communication signals.

[0042] 2A is a block diagram illustrating a wireless device 200 capable of implementing aspects of the disclosure. The wireless device 200 may be, for example, an embodiment of a device (e.g., base station 130 or 132, wireless device 110 or 160, etc.) illustrated in FIG. 1. The described circuitry may be a circuitry that supports mmW or other such communication using a large array of antenna elements that is structured to receive signals via chain routing (e.g., rather than splitter-based routing). In some examples, the wireless device 200 (or any of the devices described and / or illustrated below) may be an embodiment of any of the devices illustrated in FIG. 1.

[0043] FIG. 2A illustrates an embodiment of a transceiver 220 having a transmitter 230 and a receiver 250. In general, the conditioning of the signals in the transmitter 230 and receiver 250 may be performed in one or more stages, such as amplifiers, filters, upconverters, downconverters, etc. These circuit blocks may also be arranged in a different manner than the configuration shown in FIG. 2A. Furthermore, other circuit blocks not shown in FIG. 2A may also be used to condition the signals in the transmitter 230 and receiver 250. Unless otherwise noted, any signal in FIG. 2A or any other figure in the drawings may be either single-ended or differential. Some circuit blocks in FIG. 2A may also be omitted.

[0044] In the embodiment shown in FIG. 2A, wireless device 200 generally comprises a transceiver 220 and a data processor 210. Data processor 210 may include a processor 296 operatively coupled to memory 298. Memory 298 may be configured to store data and program code and generally includes analog and / or digital processing components. Transceiver 220 includes a transmitter 230 and a receiver 250 supporting bidirectional communication. In general, wireless device 200 may include any number of transmitters and / or receivers for any number of communication systems and frequency bands. All or a portion of transceiver 220 may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc.

[0045] The transmitter or receiver can be implemented using a super-heterodyne architecture or a direct-conversion architecture. In a super-heterodyne architecture, a signal is frequency converted between radio frequency (RF) and baseband in multiple stages, e.g., for a receiver, from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct-conversion architecture, a signal is frequency converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and / or have different requirements. In the embodiment shown in FIG. 2A, the transmitter 230 and the receiver 250 are implemented using a direct-conversion architecture.

[0046] In the transmit path, the data processor 210 processes data to be transmitted and provides in-phase (I) and quadrature-phase (Q) analog output signals to the transmitter 230. In an exemplary embodiment, the data processor 210 includes digital-to-analog converters (DACs) 214a and 214b for converting digital signals generated by the data processor 210 into I and Q analog output signals, e.g., I and Q output currents, for further processing. In other embodiments, the DACs 214a and 214b are included within the transceiver 220, and the data processor 210 provides data (e.g., for I and Q) to the transceiver 220 digitally.

[0047] Within transmitter 230, baseband (e.g., low pass) filters 232a and 232b filter the I and Q analog transmit signals, respectively, to remove undesired images caused by previous digital-to-analog conversion. Amplifiers (Amp) 234a and 234b amplify signals from baseband filters 232a and 232b, respectively, to provide I and Q baseband signals. An upconverter 240, having upconversion mixers 241a and 241b, upconverts the I and Q baseband signals using I and Q TX LO signals from a transmit (TX) local oscillator (LO) 290 to provide upconverted signals. A filter 242 filters the upconverted signal to remove undesired images caused by frequency upconversion as well as noise in the receive frequency band. A power amplifier 244 amplifies the signal from filter 242 to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 246 and transmitted via an antenna 248. Although the embodiments discussed herein utilize I and Q signals, one skilled in the art will appreciate that the transceiver components may also be configured to utilize polar modulation.

[0048] In the receive path, an antenna 248 receives a communication signal and provides a receive RF signal that is routed through a duplexer or switch 246 and provided to a low noise amplifier (LNA) 252. The switch 246 is designed to operate using a specific RX to TX duplexer frequency separation such that the RX signal is separated from the TX signal. To obtain a desired RF input signal, the receive RF signal is amplified by the LNA 252 and filtered by a filter 254. Downconversion mixers 261a and 261b in the downconverter 260 mix the output of the filter 254 with I RX LO signals and Q RX LO signals (i.e., LO_I and LO_Q) from a receive (RX) LO signal generator 280 to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers 262a and 262b and further filtered by low pass filters 264a and 264b to obtain I and Q analog input signals that are provided to data processor 210. In the illustrated exemplary embodiment, data processor 210 includes analog-to-digital converters (ADCs) 216a and 216b for converting the analog input signals to digital signals that will be further processed by data processor 210. In some embodiments, ADCs 216a and 216b are included within transceiver 220 and provide data digitally to data processor 210.

[0049] In FIG. 2A, TX LO signal generator 290 generates I TX LO signal and Q TX LO signal used for frequency up-conversion, while RX LO signal generator 280 generates I RX LO signal and Q RX LO signal used for frequency down-conversion. Each LO signal is a periodic signal having a particular fundamental frequency. Phase-locked loop (PLL) 292 receives timing information from data processor 210 and generates control signals used to adjust the frequency and / or phase of the TX LO signal from LO signal generator 290. Similarly, PLL 282 receives timing information from data processor 210 and generates control signals used to adjust the frequency and / or phase of the RX LO signal from LO signal generator 280.

[0050] In an exemplary embodiment, the RX PLL 282, the TX PLL 292, the RX LO signal generator 280, and the TX LO signal generator 290 may alternatively be combined into a single LO generator circuit 295, which may include a common or shared LO signal generator circuit for providing the TX LO signal and the RX LO signal. Alternatively, separate LO generator circuits may be used to generate the TX LO signal and the RX LO signal.

[0051] Certain components of the transceiver 220 are illustrated in FIG. 2A with respect to their functionality, and the configuration depicted in this figure may or may not represent the physical device configuration in a particular implementation. For example, as discussed above, the transceiver 220 may be implemented in various integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc. In some embodiments, the transceiver 220 is implemented on a substrate or board, such as a printed circuit board (PCB) having various modules, chips, and / or components. For example, the power amplifier 244, the filter 242, and the switch 246 may be implemented in separate modules or as individual components, while the remaining components depicted in the transceiver 220 may be implemented in a single transceiver chip.

[0052] Power amplifier 244 may include one or more stages, including, for example, a driver stage, a power amplifier stage, or other components, that may be configured to amplify communication signals over one or more frequencies, in one or more frequency bands, and at one or more power levels. Depending on various factors, power amplifier 244 may be configured to operate with one or more driver stages, one or more power amplifier stages, one or more impedance matching networks, and may be configured to provide good linearity, efficiency, or a combination of good linearity and efficiency.

[0053] In an exemplary embodiment in a super-heterodyne architecture, power amplifier 244 and LNA 252 (and, in some embodiments, filter 242 and / or filter 254) may be implemented separately from other components in transmitter 230 and receiver 250 and may be implemented on a millimeter wave integrated circuit. An exemplary super-heterodyne architecture is shown in FIG. 2B.

[0054] Figure 2B is a block diagram illustrating a wireless device capable of implementing aspects of the present disclosure. Certain components of the wireless device 200a of Figure 2B, which may be indicated by the same reference numerals, may be configured similarly to the components in the wireless device 200 shown in Figure 2A, and descriptions of the same numbered items in Figure 2B will not be repeated.

[0055] Wireless device 200a is an example of a heterodyne (or superheterodyne) architecture in which upconverter 240 and downconverter 260 are configured to process communication signals between baseband and intermediate frequency (IF). For example, upconverter 240 may be configured to provide an IF signal to upconverter 275. In an exemplary embodiment, upconverter 275 may include a summing function 278 and an upconversion mixer 276. Summing function 278 combines the I and Q outputs of upconverter 240 to provide a non-quadrature signal to mixer 276. The non-quadrature signal may be single-ended or differential. Mixer 276 is configured to receive the IF signal from upconverter 240 and a TX RF LO signal from TX RF LO signal generator 277 and provide an upconverted mmW signal to phase shift circuit 281. Although PLL 292 is shown in FIG. 2B as being shared by signal generators 290, 277, a corresponding PLL for each signal generator may also be implemented.

[0056] In an exemplary embodiment, components within phase shift circuit 281 may include one or more adjustable or variably phased array elements and may receive one or more control signals from data processor 210 via connection 289 and operate the adjustable or variably phased array elements based on the received control signals.

[0057] In the exemplary embodiment, the phase shift circuit 281 includes a phase shifter 283 and a phased array element 287. For ease of explanation, three phase shifters 283 and three phased array elements 287 are shown, however, the phase shift circuit 281 may include more or fewer phase shifters 283 and phased array elements 287.

[0058] Each phase shifter 283 can be configured to receive the mmW transmit signal from the upconverter 275, change the phase by an amount, and provide the mmW signal to a corresponding phased array element 287. Each phased array element 287 can include transmit and / or receive circuitry, including one or more filters, amplifiers, driver amplifiers, and power amplifiers. In some embodiments, the phase shifter 283 can be incorporated within the corresponding phased array element 287.

[0059] The output of the phase shift circuit 281 is provided to the antenna 248. In an exemplary embodiment, the antenna 248 includes a number of antennas, typically corresponding to the number of phase shifters 283 and phased array elements 287, such that each antenna element is coupled to a corresponding phased array element 287. In an exemplary embodiment, the phase shift circuit 281 and the antenna 248 may be referred to as a phased array.

[0060] In the receive direction, the output of the phase shift circuit 281 is provided to the downconverter 285. In an exemplary embodiment, the downconverter 285 may include an I / Q generation function 291 and a downconversion mixer 286. In an exemplary embodiment, the mixer 286 downconverts the received mmW signal provided by the phase shift circuit 281 to an IF signal according to the RX mmW LO signal provided by the RX mmW LO signal generator 279. The I / Q generation function 291 receives the IF signal from the mixer 286 and generates I and Q signals for the downconverter 260, which downconverts the IF signal to baseband, as described above. The PLL 282 is shown in FIG. 2B as being shared by the signal generators 280, 279, although a corresponding PLL for each signal generator may also be implemented.

[0061] In some embodiments, the upconverter 275, the downconverter 285, and the phase shift circuit 281 are implemented on a common IC. In some embodiments, the summing function 278 and the I / Q generation function 291 are implemented separately from the mixers 276 and 286 such that the mixers 276, 286 and the phase shift circuit 281 are implemented on a common IC, but the summing function 278 and the I / Q generation function 291 are not implemented on the common IC (e.g., the summing function 278 and the I / Q generation function 291 are implemented in a separate IC that is coupled to the IC with the mixers 276, 286). In some embodiments, the LO signal generators 277, 279 are included in a common IC. In some embodiments, the phase shift circuitry is implemented on a common IC with 276, 286, 277, 278, 279, and / or 291, and in some embodiments, the common IC and antenna 248 are contained within a module that can be coupled to other components of transceiver 220 via a connector. In some embodiments, phase shift circuitry 281, e.g., the chip on which phase shift circuitry 281 is implemented, is coupled to antenna 248 by an interconnect. For example, the components of antenna 248 can be implemented on a substrate and coupled to an integrated circuit implementing phase shift circuitry 281 via a flexible printed circuit board or other such substrate.

[0062] In some embodiments, both the architectures shown in FIG. 2A and FIG. 2B are implemented in the same device. For example, wireless device 110 or wireless device 200 may be configured to communicate with signals having frequencies below about 20 GHz using the architecture shown in FIG. 2A and to communicate with signals having frequencies above about 20 GHz using the architecture shown in FIG. 2B. In a device in which both architectures are implemented, one or more components of FIG. 2A and FIG. 2B that are numbered the same may be shared between the two architectures. For example, both signals directly downconverted from mmW to baseband and signals downconverted from mmW to baseband via an IF stage may be filtered by the same baseband filters 264a, 264b. In other embodiments, a first version of filters 264a, 264b is included in the portion of the device implementing the architecture of FIG. 2A, and a second version of filters 264a, 264b is included in the portion of the device implementing the architecture of FIG. 2B.

[0063] As mentioned above, exemplary wireless devices can be configured with or without the use of intermediate frequencies (IFs). The aspects described below are discussed in the context of a system that merges IF signals with control and clock signals. In some other implementations, chain signals can be used in accordance with the description herein for systems that do not use IF signals or where control and clock signals are not merged with data signals.

[0064] FIG. 2C is a block diagram illustrating aspects of a wireless device capable of implementing aspects of the disclosure. The wireless device illustrated by FIG. 2C may structure the circuits of FIG. 2A, 2B above in an IF transceiver 201 (e.g., an IF integrated circuit (IFIC)) and an mmW transceiver 301 (e.g., 301-1, 301-M, 301-N, etc.). In some embodiments, the IF transceiver 201 is implemented in a chip separate from the mmW transceiver 301, and the signal path 204 and the signal path 207 may be implemented using cables. In some such embodiments, the IF IC is coupled to an IC that includes the mmW transceiver 301-1, which may or may not be included in a package or module. In other implementations, these transceivers may be implemented on a shared PCB, in a shared package, or in a single IC that may use other routing paths. Additional circuitry may be present in such elements and is not shown for simplicity or described below. In some embodiments, the mmW transceiver includes mixer 276 and mixer 286 and phase shift circuit 281, and IF transceiver 201 includes the remaining elements of transceiver 220.

[0065] The IF transceiver 201 includes two data sources, shown as data source 202 and data source 205. Each of the data source 202 and data source 205 can provide information to be transmitted over a channel in the mmW communication system. Similarly, circuitry for receiving information can also be included or alternatively included in place of the data source 202 and / or data source 205. In one exemplary embodiment, the data source 202 or data source 205 represents a DAC 214a and / or a DAC 214b integrated in the IF transceiver 201 to provide converted I analog data and / or Q analog data (e.g., I output current and Q output current) from the digital signal generated by the data processor 210. The IF transceiver can include data sources for multiple different signal paths for different signal routing for a large array of antenna elements. Each routing can provide a signal path for multiple mmW transceivers 301, and multiple signal paths using chain routing can exist in the device to support antenna elements in a large array. Each signal path includes analog components (e.g., H and V, various channels or frequencies, etc.) as described above. The components for a given signal path are combined with a control signal 203 or a clock signal 206 as shown in FIG. 2C using a diplexer 299 (e.g., or a splitter / combiner) as shown. Merging the data signal from the data source 202 with the control signal 203 creates a merged control / data signal that is communicated to the first mmW transceiver 301-1 in the daisy chain via merged control / signal path 204. Merging the clock signal 206 with the data signal from the data source 205 creates a merged clock / data signal that is communicated to the first mmW transceiver 301 in the daisy chain using merged clock / signal path 207.For example, data on path 204 may be for one polarization of an antenna or array of antennas, and data on path 207 may be for another polarization of an antenna or array of antennas. The data transmitted on the different polarizations may be the same (e.g., for diversity purposes) or different (e.g., for MIMO). In another embodiment, data on path 204 may be for a first antenna or array of antennas, and data on path 207 may be for a second antenna or array of antennas. The first antenna or array and the second antenna or array may be spaced apart, oriented in different directions, configured to communicate using different frequencies, configured as different types of antennas (e.g., one as a patch and the other as a dipole), etc. In some embodiments, additional paths containing additional data (e.g., for other or additional antennas) may be coupled between IF transceiver 201 and mmW transceiver 301-1 (and between mmW transceivers in the chain). In some such embodiments, the additional paths include data from multiple sources, which may be separated using a diplexer or other splitter, as described below with respect to paths 204 and 207.

[0066] The circuitry of the mmW transceiver 301-1 can use signals from the signal path 204 and the signal path 207 to transmit data on the antenna 248 of the mmW transceiver 301-1. Similarly, data received on the antenna 248 of the mmW transceiver 301-1 can be communicated to the IF transceiver 201 using the path 204 and the path 207. The chain path 209 can be used to communicate data between the IF transceiver 201 and the mmW transceiver 301N via the chain path 209 and the mmW transceiver 301-1. In such an implementation, the mmW transceiver 301-1 can be considered as a primary mmW transceiver, a master mmW transceiver, or a first mmW transceiver in the first signal routing for the device of FIG. 2C. The mmW transceiver 301N can be considered as a secondary mmW transceiver, a slave mmW transceiver, or a subsequent mmW transceiver in the first signal routing. Additional chain paths can be used to connect the mmW transceiver 301N to additional mmW transceivers 301 (e.g., 301-o, 301-p, 301-z, etc.) in the first signal routing. The control signal 203 can be used to manage the routing of signals to and from the antennas 248 of the various mmW transceivers in the first signal routing. The mmW transceiver 301N can therefore, in some aspects, receive signals from one mmW transceiver that are simply passed on to another mmW transceiver based on the control signal 203, without the signals interacting with antenna elements of a massive phased array integrated with the mmW transceiver 301N. Furthermore, the control signal 203 can facilitate controlling operations within the mmW transceiver, such as the signal beam (e.g., to select a codebook for beamforming), the gain of one or more amplifiers, etc.

[0067] In operation, the processor 296 (which may be one embodiment of the data processor 210, not shown in FIG. 2C) may manage the transmission of data from the memory 298 (not shown in FIG. 2C) or the reception of data for storage in the memory 298. During transmission, the control circuitry (e.g., the processor 296, or other such control circuitry) may generate control data that identifies one or more target mmW transceivers 301 that are to be used in transmitting or receiving the data. When the transmit data is merged with the clock data and the control data using a diplexer 299 (e.g., a splitter / combiner), the control data in the merged control and data signal may include information regarding the target mmW transceiver 301 that is being instructed to transmit the data. The transmit data is then communicated via daisy-chain routing to the target mmW transceiver (e.g., the mmW transceiver 301N, or any other mmW transceiver in the daisy-chain routing). The switching circuitry of the daisy chain routing then passes the transmit data through the routing to the appropriate mmW transceiver where it is then processed and transmitted to the target mmW transceiver's antenna 248. Examples of how signals are routed or used within particular transceivers of the daisy chain routing are described below in Figures 3A, 3B, 4, 5, and 6A-6C.

[0068] FIG. 2D is a block diagram illustrating aspects of a wireless device capable of implementing aspects of the disclosure. The wireless device of FIG. 2D illustrates how a daisy chain of multiple IF transceivers 201 and associated multiple mmW transceivers 201 can be combined to provide signal routing to any number of antenna elements to support a large-scale phased array according to aspects described herein. As shown, a processor 296 (e.g., or any control circuitry) can be combined with any number of transceivers 201 (e.g., as described above with respect to FIG. 2C). The example of FIG. 2D illustrates an IF transceiver 201-1, an IF transceiver 201-2, and an IF transceiver 201-M. Each of the IF transceivers 201 has an associated set of mmW transceivers. The IF transceiver 201-1 is associated with an mmW transceiver 301-1-1 and an mmW transceiver 301-1-N. The IF transceiver 201-2 is associated with mmW transceiver 301-2-1 and mmW transceiver 301-2-N. The IF transceiver 201-M is associated with mmW transceiver 301-M-1 and mmW transceiver 301-MN. If each mmW transceiver includes P antenna elements, the illustrated wireless device supports M×N×P antenna elements. Such a routing structure can support hundreds, thousands, or any number of antenna elements in a large antenna array. Such a structure improves the design of the device by reducing the routing complexity when compared to a multi-stage 1:N splitter tree. The reduced complexity can improve the link budget performance of the design and can support coverage to meet 5G performance standards for 5G customer terminal equipment, 5G wireless area networks for small cells, and 5G wireless area networks for base stations. Although each chain is shown in FIG. 2D as having the same number of mmW transceivers 301, the number of mmW transceivers in each chain may differ.

[0069] 3A illustrates aspects of an apparatus 300 including chain signal routing for a large phased array, according to some embodiments. FIG. 3B illustrates aspects of an mmW transceiver 301 for use with the apparatus 300 of FIG. 3A including chain signal routing for a large phased array, according to some embodiments.

[0070] FIG. 3A includes an IF transceiver, similar to FIG. 2C and FIG. 2D. The illustrated IF transceiver 310 has two paths (although, as described above, there may be more paths) connected to the chain routing for the mmW transceiver 301A, the mmW transceiver 301B, and the mmW transceiver 301C, or in a similar manner, more mmW transceivers. These two paths are a merge control path 381, similar to the merge control / signal path 204 of FIG. 2C, and a merge clock path 371, similar to the merge clock / signal path 207 of FIG. 2C. As described above, the two paths 204, 207 can be used for separate data, carriers, streams, channels, etc., to be communicated using the antennas supported by the IF transceiver 201 and the mmW transceiver 301 in the chain routing illustrated by FIG. 3A. Two paths 371 and 381 connect the IF transceiver 310 to a first (e.g., master or first) chained mmW transceiver 301A. The first chained mmW transceiver 301A includes circuitry to support both transmission and reception of signals using paths 371 and 381, as well as circuitry to support relaying of such signals between the IF transceiver 310 and mmW transceivers 301 further down the daisy chain away from the IF transceiver 310 (e.g., mmW transceivers 301B and 301C, which may be considered secondary or slave mmW transceivers relative to the primary or master mmW transceiver 301A). Although the apparatus 300 is shown with three mmW transceivers 301A, 301B, and 301C, additional numbers of mmW transceivers may be used in other configurations. Additionally, as discussed above, IF transceiver 310 may have other connections similar to paths 371 and 381 for connecting to additional chains of mmW transceivers.

[0071] In the embodiment of FIG. 3A, the routing path of the chained mmW transceiver 301 connects from path 381 through mmW transceiver 301A to separate signal path 383 and control path 382. In the embodiment of FIG. 3A, the merged signals from merged control path 381, including both data signals and control signals, are split inside mmW transceiver 301A, and separate paths are used for signals and control data communicated between mmW transceiver 301A and mmW transceiver 301B. The signal path carries data signals between mmW transceiver 301B and mmW transceiver 301A, and control path 382 carries control signals between mmW transceiver 301B and mmW transceiver 301A. Similarly, data from merged clock path 371 is separated inside chained mmW transceiver 301A. Data can be communicated to the chained mmW transceiver 301B using signal path 373 and clock path 372. Two separate data, clock, and control signals can be communicated separately down the daisy-chain routing into any number of subsequent chained transceivers after the first chained mmW transceiver 301 (e.g., using signal paths 385, 375, control path 384, clock path 374, and similar paths for any subsequent mmW transceivers in the daisy-chain routing away from the IF transceiver 310).

[0072] In addition to the daisy-chain connection to the IF transceiver 310, each mmW transceiver 301 in the chain of mmW transceivers can be associated with a separate power management integrated circuit (PMIC) 320. The PMIC 320 provides reference voltages and currents to support amplifiers and power for transmitting and receiving signals using the antenna for each individual mmW transceiver 301, as well as for compensating for losses in data, control, and clock signals as the signals are passed along the daisy-chain of chained mmW transceivers 301. Although the device 300 is shown with each mmW transceiver paired with a PMIC chip, it is also possible to pair one PMIC with two or more mmW transceivers to save costs, especially for large-scale phased array systems. For example, one or more reference voltages can be communicated through the chain of mmW transceivers, and the power management circuitry in each transceiver can convert the reference voltage to the voltage required by that transceiver.

[0073] 3B illustrates aspects of a mmW transceiver 301 (e.g., including chained mmW transceivers 301A, 301B, 301C) for use in the apparatus 300 of FIG. 3A, including chain signal routing for a large-scale phased array, according to some aspects. FIG. 3B illustrates the chained mmW transceiver 301B of FIG. 3A. The illustrated transceivers 301A, 301B, 301C are shown as duplicates, such that the following description of the chained mmW transceiver 301B can be applied to any transceiver in a daisy chain, including the first mmW transceiver in the chain (e.g., mmW transceiver 301A), even if some elements are not used due to a particular configuration.

[0074] 3B and also shown in FIG. 3A, the chained mmW transceiver 301B has connections to a preceding mmW transceiver and a following mmW transceiver in the daisy chain. The connection to the preceding mmW transceiver (e.g., mmW transceiver 301A) includes signal path 383, control path 382, ​​signal path 373, and clock path 372. The connection to the following mmW transceiver in the chain (e.g., mmW transceiver 301C) includes signal path 385, control path 384, signal path 375, and clock path 374. As a secondary (e.g., slave, following, etc.) mmW transceiver, signal path 383 will be used only for data signals, and control signals are received via control path 382. If transceiver 301B were the primary (e.g., first, master, etc.) transceiver, signal path 383 would include combined data and control signals that would be split by control / signal diplexer 389. Because the control and data signals for such a combination are at different frequencies, diplexer 389 could be a simple passive diplexer that splits the different frequency signals along separate paths. The path shown at the top is connected to the Tx and Rx paths for the antenna connected to mmW transceiver 301B. The path at the bottom is attached to control circuitry 380. When a control signal is received via control path 382 or control path 384, the signal is coupled directly to control circuitry 380 as shown. In an alternative embodiment, for receive path signals, control / signal diplexer 389 could similarly be used to combine the data and control signals into a combined control / data signal for communication to the IF transceiver if mmW transceiver 301B were the primary transceiver in the chain.Data signals communicated via signal path 383 may be connected to signal path 385 if the signal is to or from a subsequent mmW transceiver 301 further along the chain (e.g., mmW transceiver 301C), or may be connected to Rx path 311 or Tx path 312 for signals transmitted or received using an antenna element directly coupled to chain-connected mmW transceiver 301B.

[0075] Signal path 373 and clock path 372 are in turn connected to a clock / signal diplexer 379 and a clock circuit 370. Clock circuit 370 may be used to manage signals transmitted and received using an antenna directly coupled to transceiver 301B (e.g., for mixers such as mixers 276, 286) and may be used to refresh or otherwise manage and distribute clock signals up and down the daisy chain routing. Both data paths through the chained transceivers have three connections, namely, a signal path connection for conveying signals up and down the daisy chain routing (e.g., via signal path 385 or signal path 375), a receive path (e.g., Rx path 311 and Rx path 321) for signals received at antenna elements connected to the mmW transceiver 301B, and a transmit path (e.g., Tx path 312 and Tx path 322) for signals transmitted using antenna elements directly connected to the mmW transceiver 301B, which can be selectively coupled together via one or more switches or other means. Figure 4 below shows an example implementation of the Tx paths 312, 322. Figure 5 below shows an example implementation of the Rx paths 311, 321. The Tx path 312 and the Rx path 311 can be coupled to the same antenna or array of antennas. Similarly, the Tx path 322 and the Rx path 321 can be coupled to another antenna or array of antennas. Mixers, amplifiers, phase shifters, filters, splitters and / or combiners, transformers, and / or other components may be coupled between each of the Tx and Rx paths and its corresponding antenna or array. Figures 6B and 6C show certain of these components, although other configurations may be used.

[0076] FIG. 4 illustrates aspects of a transmit (Tx) path (e.g., Tx path 312 or Tx path 322) in an mmW transceiver for use in chain signal routing for a large-scale phased array, according to some aspects. As shown, the circuit of FIG. 4 illustrates the routing for signals from signal path 383 of FIG. 3A and FIG. 3B to Tx path 312 and signal path 385. Additional switching or isolation circuits may be present to manage signals along such paths, but are not shown for simplicity. As shown in FIG. 3A and FIG. 3B, a replica circuit or other circuit similar to the example circuit of FIG. 4 may be used for both data paths in any mmW transceiver 301.

[0077] As shown, this circuitry is connected to the signal path 383 and the control / signal diplexer 389 described above (paths for control data to and from the diplexer 389 are not shown in FIGS. 4 and 5 for ease of illustration). The data output of the control / signal diplexer 389 may be coupled to the circuitry for the Rx path 311, the Tx path 312, and the circuitry for the signal path 385. For transmit data to be transmitted using an antenna element coupled to the circuitry shown in FIG. 4, the transmit data will be received at the control / signal diplexer 389 and the switching for the Rx path 311 (not shown in FIG. 4 but shown in FIG. 5 for clarity) and the signal path 385 will be in the open / isolated position. The transmit data will be amplified by the Tx variable gain amplifier (VGA) 410 and then passed along the Tx path 312.

[0078] For transmit data that is instructed to be passed further along the daisy-chain routing, the Rx path switching 409 (e.g., switching for Rx path 311, see FIG. 4) and the Tx path switching 509 (see FIG. 5) for Tx VGA 410 will be opened / isolated, and the Tx buffer VGA 412 will be connected to the output of the control / signal diplexer 389. The Tx buffer VGA 412 is used to compensate for losses along the daisy-chain routing, and then passes the signal via switching to the signal path 385. The transmit data can be passed to the mmW transceiver 301 associated with the transmit data by the control data via multiple chains of such Tx buffers in the daisy-chain routing. The switching between the Tx buffer VGA 412 and the signal path 385 includes switching to connect the signal path 385 to both the Tx buffer VGA 412 and the Rx buffer VGA 512 for the receive signal transmitted up the daisy-chain routing as described in FIG. 5.

[0079] FIG. 5 illustrates aspects of the receive (Rx) path 311 in a mmW transceiver 301B for use in chain signal routing for a large phased array, according to some aspects. As mentioned above, both the Rx buffer VGA 514 and the Tx buffer VGA 412 can be connected to the signal path 385 via a switching circuit. This switching circuit allows the signal path 385 to connect to the Tx buffer VGA 412 when a signal is sent down the daisy chain routing to a mmW transceiver further down the chain, and to the Rx buffer VGA 514 via a matching circuit 502 when a receive signal is sent up the daisy chain to an IF transceiver. In the example circuit of FIG. 5, such receive signals sent up the daisy chain are input to the signal path 385 from another mmW transceiver (e.g., mmW transceiver 301C). Matching circuit 502 then provides a signal to Rx buffer VGA 514, which can compensate for signal loss from signal path 385 or other parts of the daisy chain routing. The received signal is then provided to control / signal diplexer 389 and passed further up the chain via signal path 383.

[0080] As described above in Figures 4 and 5, the Tx path 312 is connected to the Rx path, and switching circuitry (e.g., Rx path switching 409 and Tx path switching 509) can be used to isolate these paths depending on the path being used, or to isolate the Tx / Rx paths of these local antenna elements from the daisy chain routing if signals are passed up and down the daisy chain. When a signal is received at the antenna of a transceiver (e.g., mmW transceiver 301B) that includes the circuitry of Figure 5, the signal is processed through a circuit (e.g., transmitter circuitry 230 or receiver circuitry 250 described in Figure 2B, etc.) and then passed to the Rx VGA 512 via Rx path 311. The received signal is then passed to the control / signal diplexer 389 and passed towards the IF transceiver via path 383. As with the transmit path, an mmW transceiver such as chain mmW transceiver 301B may include two copies of the circuitry of Figure 4 and associated separate paths, one copy using control / signal diplexer 389 and the other copy using a clock diplexer (e.g., clock diplexer 379). In other embodiments, different circuits may be used to manage different data, clock and control signals to compensate for routing losses, signal integrity and provide signals going up and down the daisy chain with sufficient signal quality to be processed in a communications system.

[0081] FIG. 6A illustrates aspects of an apparatus including chain signal routing for a phased array (e.g., a large phased array) according to some aspects. In the implementations shown in FIGS. 3A, 3B, 4, and 5, the merged clock / data signal and the merged control / data signal are split at the primary mmW transceiver, and then the clock signal, the control signal, and the two data signals are passed separately up or down the daisy chain. FIG. 6A illustrates an implementation in which these signals are passed together, rather than being passed separately up or down the chain. Other aspects of the apparatus can operate as described above, with the merged signals provided to and from the IF transceiver in a merged format via the merged clock / signal path 602 and the merged control / signal path 604. The signal may then be passed upstream (e.g., Rx signals) or downstream (e.g., Tx signals) of the chain connecting the multiple mmW transceivers 601A-601N via chain path 622, chain path 624, second chain path 623, and second chain path 625. Signals received at antennas 695 of one or more mmW transceivers 601A-601N are passed up the chain to the IF transceiver 610, and signals to be transmitted using antennas 695 of one or more mmW transceivers are passed down the daisy chain from the mmW transceivers 601A-601N to their assigned mmW transceiver (e.g., mmW transceiver 601N) for transmission using the corresponding antenna 695 for the designated transceiver.

[0082] FIG. 6B illustrates aspects of a mmW transceiver for use in chain signal routing for a (large) phased array, according to some aspects. FIG. 6B illustrates an example implementation of a transceiver 601A that differs from the implementations described in FIG. 3B, FIG. 4, and FIG. 5. In the embodiment of FIG. 6B, the mmW transceiver 601A is configured to receive a combined transmit data signal in a merged clock / signal path 602 and a merged control / signal path 604. The corresponding merged transmit signals from each path are split in diplexers 630 and 631. In contrast to the above embodiment, if a signal is designated to be passed down the daisy chain rather than being transmitted through the antenna 695 for the mmW transceiver 601A (e.g., via phase shifter 650 and Tx / Rx amplifier 690), the signals are recombined in diplexers 640 and 641. The signals remerged in mmW transceiver 601A using diplexer 640 and diplexer 641 are then communicated down the daisy-chain routing via chain clock / signal path 622 and chain control / signal path 624. The receive signal follows the opposite path and the combined signal is received via chain control / signal path 624 and chain clock / signal path 622. The receive signal follows the inverse of the transmit signal and the signals are similarly split in mmW transceiver 601A and recombined before being passed up the daisy-chain routing to an IF transceiver such as IF transceiver 610.

[0083] In the mmW transceiver where the signal is transmitted, switching circuits coupled to diplexer 630 and diplexer 631 route the signal along a signal path, including from the data terminal of diplexer 630 and from the data terminal of diplexer 631 to antenna 695 using phase shifter 650 and amplifier 690. Although phase shifting of the signal paths is shown herein, one skilled in the art will appreciate that phase shifting can be achieved by shifting the LO signal and / or mixer signal instead (in this figure and other figures such as Figures 3A, 3B, 6C). A clock signal from merge clock / signal path 602 is coupled to the clock signal terminal and output from the clock terminal of diplexer 631 to be provided to circuitry for managing the timing of the data signal and / or conversion of the data signal between IF and RF (e.g., to a mixer in mmW transceiver 601A or to circuitry configured to generate an LO input for the mixer based on the clock signal). The control signal from merge control signal path 604 is provided to a control signal terminal of diplexer 631, which outputs from the control terminal of diplexer 631 to a control / wired interface 689 for managing the transmission of the data signal. For example, interface 689 may be configured to adjust phase shifter 650, set one or more switches in mmW transceiver 601A, set the gain of one or more amplifiers (e.g., any of amplifiers 690) in transceiver 601A, etc. For receive signals, antenna 695 receives the signals, which are amplified by amplifier 690. Additional circuitry then manages the data, clock, and control signals for propagation up the daisy chain via signal path 632 and signal path 633.

[0084] FIG. 6C illustrates aspects of a mmW transceiver for use in chain signal routing for a (large) phased array, according to some aspects. Similar to the device of FIG. 6B, the device of FIG. 6C communicates merged signals in merge signal path 602 and merge signal path 604 if the device is the first mmW transceiver. Diplexer 630 and diplexer 631 split any merged signals received up the daisy chain (e.g., towards the IF transceiver) and also merge any split signals that are to be sent directly to the IF transceiver. Signals communicated using antenna 695 are timed, for example, by a clock signal on clock path 685 and routed to phase shifter 650 and TX or RX amplifiers 690 based on control data from control / wired interface 689. Devices not connected to an IF transceiver (e.g., in the middle of a daisy chain) communicate data, control, and clock signals separately using paths 602, 604, 622A, 622B, 624A, and 624B. In contrast to the device of FIG. 6B, the device of FIG. 6C does not re-merge data and control or clock signals before communicating the signals up or down the daisy chain unless the signals are passed to an IF transceiver. Thus, if the device of FIG. 6C is the first mmW transceiver in the chain, the merged signals split at diplexer 630 and diplexer 631 are communicated separately down the daisy chain (e.g., away from the IF transceiver) using signal paths 622B, 624B and separate clock and control paths 622A and 624A. For example, if the device is a second mmW transceiver in a daisy chain or an additional mmW transceiver, the control signal is received as a stand-alone signal via chain control path 624A.For a first mmW transceiver in such a daisy chain, a data signal to be passed to a second mmW transceiver (e.g., away from the IF transceiver 610) is output from signal path 622B and signal path 624B of the first mmW transceiver and then input to corresponding signal path 622B and signal path 624B of the second mmW transceiver.

[0085] The daisy-chain routing architecture described herein can improve devices using such architectures by avoiding losses associated with splitters and by reducing the number of independent IF transceiver ICs, e.g., by a factor associated with the number of mmW transceivers in the daisy chain. For example, if two mmW transceivers are used in a daisy chain, the number of IF transceiver ICs can be reduced by half. For a 32×32 antenna array, reducing the number of IF transceiver ICs from 16 to 8 can reduce the space usage of the device and provide a corresponding improvement to the device associated with the reduced number of IF transceiver ICs. Furthermore, as described above, the use of multiplexing and demultiplexing diplexers on the mmW transceivers can reduce path losses (e.g., ∼4 dB from a 1:2 splitter) and provide a corresponding improvement in signal-to-noise ratio. Such an approach can further reduce the number of elements for a common RFIC design for UE and CPE that would otherwise incur area and current consumption penalties (e.g., due to 1:3 splitters used at the IF connection ports.) Furthermore, such aspects can improve the flexibility of device designs using daisy chains when compared to 1:2 splitter or 1:4 splitter configurations, for example, in environments where routing mm-wave signals beyond a few millimeters results in significant loss.

[0086] 7A and 7B are block diagrams collectively illustrating some aspects of a millimeter wave (mmW) module according to some aspects of the disclosure. The above circuits illustrate mmW elements that may be located within an mmW module (e.g., on an mmW PCB and / or within an mmW IC). These mmW module elements may include mmW transceivers as described in FIGS. 2D, 3A, 3B, 4, 5, and 6A-6C, as well as antenna elements used in large-scale antenna arrays as described throughout this specification. Such mmW elements may also include chain signal path routing as described herein.

[0087] FIG. 7A illustrates a side view of a millimeter-wave (mmW) module 700. The mmW module 700 may be one example of an mmW module used in conjunction with mmW transceivers, PMICs, and other such mmW elements described herein. In some aspects, the mmW module 700 may comprise a large-scale phased array fabricated on a substrate 703. Such a large-scale phased array module may include any number of antenna elements (e.g., 64 elements, 128 elements, 1024 elements, etc.). In some aspects, the mmW module 700 may comprise a mmWIC 710, a PMIC 715, a connector 717, and multiple antennas in the array. The side view of FIG. 7A illustrates an array of antennas 721, 722, 723, 724, 725, 726, 727, and 728, the mmWIC 710, the PMIC 715, and the connector 717 fabricated on the substrate 703. FIG. 7B is a top view of the mmW module 700 showing multiple antennas 721-1 to 721-N, antennas 722-1 to 722-N, antennas 723-1 to 723-N, antennas 724-1 to 724-N, antennas 725-1 to 725-N, antennas 726-1 to 726-N, antennas 727-1 to 727-N, and antennas 728-1 to 728-N on the substrate 703. In other embodiments, the mmW module 700 may have other numbers of antennas in other arrangements (e.g., 1×8, 16×16, 4×6, 8×16, etc.) other than the 8×8 grid shown in FIG. 7B. Other embodiments include devices where the mmW module may include an array of multiple antennas on a separate PCB that is attached to the main mmW PCB. In some embodiments, the antennas shown in FIG. 7B may be supported by multiple mmW transceivers. For example, each row of antennas may be supported by an IF transceiver and multiple chain mmW transceivers, each of which drives or receives from a subset of the antennas in the row.In another embodiment, one IF transceiver supports all of the antennas shown in FIG. 7B and is coupled to multiple daisy-chained mmW transceivers, each of which drives or receives from an antenna in a corresponding row.

[0088] 8 is a flow diagram illustrating an example of operations of a method 800 for operation of a device including chain signal routing for a large scale phased array, in accordance with some aspects. The blocks in the method 800 may be performed in the order shown, or out of the order shown, and in some embodiments may be performed at least partially in parallel.

[0089] Method 800 includes block 802, which involves generating a first analog data signal and a second analog data signal. These analog data signals may be generated by a digital-to-analog converter (e.g., DAC 214a and DAC 214b) from a first digital data signal and a second digital data signal received from a processor (e.g., processor 296) or memory (e.g., memory 298) of the device.

[0090] The method 800 includes block 804 with generating control data and clock data for the first analog data signal and the second analog data signal. The clock data may be generated by a clock circuit within the IF transceiver and the control data may be generated by control circuitry (e.g., the processor 296) for the wireless communication system.

[0091] The method 800 includes block 806, which involves merging the control data and the first analog data signal by an IF transceiver (eg, diplexer 299 of IF transceiver 201) to generate a merged control and data signal.

[0092] The method 800 includes block 808, which involves merging the clock data and the second analog data signal by an IF transceiver (eg, diplexer 299 of IF transceiver 201) to generate a merged clock and data signal.

[0093] The method 800 includes block 810, which involves communicating a first analog data signal and a second analog data signal between an IF transceiver and a target mmW transceiver via daisy chain routing, the daisy chain routing including at least a first mmW transceiver within the daisy chain routing between the IF transceiver and the target mmW transceiver.

[0094] In some aspects, the operations of block 810 may involve splitting the merged control and data signals using a first diplexer of the first mmW transceiver between the IF transceiver and the target mmW transceiver, splitting the merged clock and data signals using a second diplexer of the first mmW transceiver between the IF transceiver and the target mmW transceiver, and routing, by the first mmW transceiver, the clock signal, the control signal, the first analog data signal, and the second analog data signal to the target mmW transceiver.

[0095] Method 800 describes a transmit operation in a device including daisy-chain routing for mmW communications. Corresponding blocks for receive operations that can be performed by the same device will be apparent. In some aspects, a method for such receive operations may involve receiving a third analog data signal, a fourth analog data signal, a second control signal, and a second clock signal at one or more antennas of a target mmW transceiver, and downconverting the third analog data signal and the fourth analog data signal from mmW frequencies to IF frequencies using frequency conversion circuitry of the target mmW transceiver. Some such aspects further involve communicating a third analog data signal, a fourth analog data signal, a second control signal, and a second clock signal from the target mmW transceiver to the first mmW transceiver, merging the second control signal and the third analog data signal by a first diplexer of the first mmW transceiver to generate a second merged control and data signal, and merging the clock data and the fourth analog data signal by a second diplexer of the first mmW transceiver to generate a second merged clock and data signal. Some such embodiments further involve communicating a second merged control and data signal and a second merged clock and data signal from the first mmW transceiver to the IF transceiver, converting the third analog data signal and the fourth analog data signal to a third digital data signal and a fourth digital data signal using an analog-to-digital converter coupled to the IF transceiver, and processing the third digital data signal and the fourth digital data signal using a processor coupled to the analog-to-digital converter.

[0096] 9 is a functional block diagram of an apparatus including chain signal routing for a large scale phased array, according to some embodiments. The apparatus 900 comprises a means 902 for transmitting and / or receiving mmW signals. The apparatus 900 further comprises a means 904 for communicating data signals used to generate the mmW signals to and from the daisy-chain mmW transceivers. The daisy-chain mmW transceivers may be directly connected to the means 904 (e.g., via a communication port of the means 904 and routing to a communication port of the daisy-chain mmW transceivers) or may be connected via additional instances of the means 904 or a similar device that includes both a means for transmitting or receiving mmW signals and a means for routing data signals used to generate the mmW signals along a daisy-chain signal path.

[0097] The apparatus 900 may further include means for selecting between the means 902 and the means 904 (e.g., using the circuitry of FIG. 4 or FIG. 5). In some aspects, the apparatus 900 may further include means for duplicating signals and means for converting the IF data signal, or a portion of the IF data signal, between an IF frequency and an mmW frequency (e.g., to convert between an IF frequency data signal and an mmW signal transmitted or received via the antenna of the apparatus 900). In various aspects, the apparatus 900 may further include elements according to any description provided herein. In some aspects, the apparatus 900 may further include means for serial connection of merged chain clock and data signals and merged chain control and data signals to the mmW transceivers in the daisy chain, as described herein.

[0098] In various devices described herein, it is shown that an IF frequency is used to provide a signal to an mmW transceiver. In various embodiments, any structure can be used to convert a digital signal to an mmW signal. In some aspects, an IF frequency is provided to a separate mmW transceiver using the described daisy-chain structure, and the IF to mmW conversion is performed within the mmW transceiver. In other aspects, an mmW signal is generated in the transceiver, and the mmW signal is communicated up and down the daisy-chain, and the downconversion from the mmW frequency is performed outside the daisy-chain structure. Thus, in some aspects, the data path described in the above aspects can be configured as a routing path that is structured to carry an mmW frequency signal. In some such aspects, a baseband signal is converted to an mmW frequency using a direct conversion in a transceiver connected to a processor. Similarly, a received mmW signal can be converted to baseband via a direct conversion or using a low-IF or zero-IF configuration in a transceiver connected to a processor. In other aspects, a super-heterodyne architecture is used (eg, contained entirely within a single transceiver connected to a processor), but with mmW signals propagating between the mmW transceivers.

[0099] The devices, networks, systems, and specific means for transmitting or receiving signals described herein may be configured to communicate over one or more portions of the electromagnetic spectrum. The electromagnetic spectrum is often subdivided into various classes, bands, channels, etc. based on frequency or wavelength. In 5G NR, two initial operating bands have been identified as frequency range designations FR1 (410 MHz to 7.125 GHz) and FR2 (24.25 GHz to 52.6 GHz). Frequencies between FR1 and FR2 are often referred to as mid-band frequencies. Although a portion of FR1 is higher than 6 GHz, FR1 is often referred to (interchangeably) as the "sub-6 GHz" band in various documents and papers, and shall be referred to herein as "sub-7 GHz". Similar nomenclature issues can arise with respect to FR2, which is often referred to (interchangeably) as the "millimeter wave" (mmW) band in documents and papers, even though FR2 includes frequencies outside the extremely high frequency (EHF) band (30 GHz to 300 GHz) identified by the International Telecommunications Union (ITU) as the "mm wave" or mmW band.

[0100] With the above aspects in mind, it should be understood that unless otherwise specified, terms such as "sub-7 GHz," as used herein, may broadly refer to frequencies that may be below 7 GHz, frequencies that may be in the FR1 range, or frequencies that may include mid-band frequencies. Furthermore, it should be understood that unless otherwise specified, terms such as "mm-wave," mmW, etc., as used herein, may broadly refer to frequencies that may be in the FR2 range, or frequencies that may be in the EHF band.

[0101] The circuit architectures described herein may be implemented on one or more ICs, analog ICs, mmWICs, mixed signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The circuit architectures described herein may also be fabricated using a variety of IC process technologies, such as complementary metal oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon on insulator (SOI), etc.

[0102] An apparatus implementing the circuits described herein may be a standalone device or may be part of a larger device, which may be (i) a standalone IC, (ii) a set of one or more ICs, which may include a memory IC for storing data and / or instructions, (iii) an RFIC, such as an RF receiver (RFR) or an RF transmitter / receiver (RTR), or a corresponding mmW element, (iv) an ASIC, such as a mobile station modem (MSM), (v) a module that may be embedded within another device, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc.

[0103] While selected aspects have been illustrated and described in detail, it will be understood that various substitutions and changes can be made in those aspects without departing from the spirit and scope of the invention as defined by the following claims.

[0104] Exemplary aspects of the present disclosure include, but are not limited to, the following: Aspect 1. A wireless communications device comprising: a first millimeter wave (mmW) transceiver, the first mmW transceiver including: a first port for communicating merged control and data signals; a second port for communicating merged clock and data signals associated with the merged control and data signals; one or more antenna elements; a plurality of chain mmW transceiver ports; and a switching circuit controllable by control data to route the merged clock and data signals and portions of the merged control and data signals between a first route between the one or more antenna elements and the first port, a second route between the one or more antenna elements and the second port, a third route between the first port and the plurality of chain mmW transceiver ports, and a fourth route between the second port and the plurality of chain mmW transceiver ports.

[0105] Aspect 2. The wireless communications device of aspect 1, further comprising a second mmW transceiver, the second mmW transceiver including a first port coupled to a first data port of the plurality of chained mmW transceiver ports, and a second port coupled to a second data port of the plurality of chained mmW transceiver ports.

[0106] Aspect 3. The wireless communications device of aspect 2, wherein the first data port is a chain control and data port coupled to a first multiplexing diplexer of the first mmW transceiver, and the second data port is a chain clock and data port coupled to a second multiplexing diplexer of the first mmW transceiver.

[0107] Aspect 4. The wireless communications apparatus of aspect 2, wherein the second mmW transceiver further includes a second clock port coupled to the first clock port of the plurality of chain mmW transceiver ports as part of a chain clock path.

[0108] Aspect 5. The wireless communication device of aspect 4, wherein the second mmW transceiver further includes a second control port coupled to the first control port of the plurality of chain mmW transceiver ports as part of a chain control path.

[0109] Aspect 6. The wireless communication device of any of Aspects 2-5, wherein the first mmW transceiver includes a first demultiplexing diplexer that couples a first port of the first mmW transceiver to a first data port and a first clock port to demultiplex the merged clock and data signals into separate clock and data signals.

[0110] Aspect 7. The wireless communication device of aspect 6, wherein the first mmW transceiver includes a second demultiplexing diplexer that couples a second port of the first mmW transceiver to a second data port and the first control port for demultiplexing the merged control and data signals into separate control and data signals.

[0111] Aspect 8. The wireless communications device of any of Aspects 2-7, wherein the first mmW transceiver further includes a first frequency conversion circuit in a first route configured to convert a first data signal associated with the merged control and data signal between an IF frequency and an mmW frequency, and a second frequency conversion circuit in a second route configured to convert a second data signal associated with the merged clock and data signal between an IF frequency and an mmW frequency.

[0112] Aspect 9. The wireless communication device of any of Aspects 2-7, wherein the first mmW transceiver further includes a frequency conversion circuit in the first route configured to convert a data signal associated with the merged control and data signal between a baseband frequency and an mmW frequency.

[0113] Aspect 10. The wireless communication device of any of Aspects 2-9, wherein the second mmW transceiver further includes one or more second antenna elements and a second switching circuit, the second switching circuit controllable by control data to select between a fifth route coupling the first port to the one or more antenna elements and a sixth route coupling the second port to the one or more antenna elements, a seventh route coupling the first port to a first chain data port of the second mmW transceiver and an eighth route coupling the second port to a second chain data port of the second mmW transceiver.

[0114] Aspect 11. The wireless communication device of aspect 10, wherein the second mmW transceiver further includes a first frequency conversion circuit in a fifth route configured to convert a first data signal associated with the merged control and data signal between an IF frequency and an mmW frequency, and a second frequency conversion circuit in a sixth route configured to convert a second data signal associated with the merged clock and data signal between an IF frequency and an mmW frequency.

[0115] Aspect 12. The wireless communication device of Aspect 11, further comprising a third mmW transceiver, the third mmW transceiver including one or more third antenna elements, a first port coupled to the first chain data port, the first port configured to communicate a first data signal associated with the merged control and data signal with the second mmW transceiver, a second port coupled to the second chain data port, the second port configured to communicate a second data signal associated with the merged clock and data signal with the second mmW transceiver, a third port coupled to the chain control port of the second mmW transceiver, the third port configured to communicate a control signal associated with the merged control and data signal, and a fourth port coupled to the chain clock port of the second mmW transceiver, the fourth port configured to communicate a clock signal associated with the merged clock and data signal.

[0116] Aspect 13. The wireless communications device of aspect 12, further comprising a processor and an intermediate frequency (IF) transceiver coupled to the processor, the IF transceiver including an IF merged clock and data port coupled to a first port of the first mmW transceiver as part of a merged clock and data path for merged clock and data signals, and an IF merged control and data port coupled to a second port of the first mmW transceiver as part of a merged control and data path for merged control and data signals.

[0117] Aspect 14. The wireless communication device of aspect 13, wherein the wireless communication device is configured to transmit the first data signal and the second data signal via one or more third antenna elements using the first data signal, the second data signal, a clock signal, and a control signal received from the IF transceiver via the first mmW transceiver and the second mmW transceiver.

[0118] Aspect 15. The wireless communications device of aspect 13, wherein the wireless communications device is configured to receive a first data signal, a second data signal, a clock signal, and a control signal at one or more third antennas, communicate the first data signal and the control signal via the second mmW transceiver and the first mmW transceiver to an IF merge control and data port of the IF transceiver, communicate the second data signal and the clock signal via the second mmW transceiver and the first mmW transceiver to an IF merge clock and data port of the IF transceiver, and process the data signals using the processor.

[0119] Aspect 16. The wireless communication device of aspect 15, wherein the first mmW transceiver is configured to merge the first data signal and the control signal into a merged control and data signal using a first diplexer, and the first mmW transceiver is configured to merge the second data signal and the control signal into a merged clock and data signal using a second diplexer.

[0120] Aspect 17. The wireless communication device of any of aspects 1-16, further comprising: a display screen; and a control circuit coupled to the display screen and the first mmW transceiver and configured to transmit and receive data using daisy chain routing including the first mmW transceiver.

[0121] Aspect 18. The wireless communications device of any of aspects 1-17, wherein the first route includes a first transmit path variable gain amplifier (VGA), a first receive path VGA coupled between the first port and one or more antenna elements, and a switching circuit for selecting between the first transmit path VGA and the first receive path VGA, and the second route includes a second transmit path VGA, a second receive path VGA coupled between the second port and one or more antenna elements, and a switching circuit for selecting between the second transmit path VGA and the second receive path VGA.

[0122] Aspect 19. The wireless communications device of any of aspects 1-18, wherein the third route includes a first receive signal path VGA buffer, a first transmit signal path VGA buffer, and a switching circuit for selecting between the first receive signal path VGA buffer and the first transmit signal path VGA buffer, and the fourth route includes a second receive signal path VGA buffer, a second transmit signal path VGA buffer, and a switching circuit configured to select between the second receive signal path VGA buffer and the second transmit signal path VGA buffer.

[0123] Aspect 20. The wireless communication device of any of Aspects 1-7 or Aspects 17-19, wherein the wireless communication device is configured to convert a baseband signal to an mmW signal without using an intermediate frequency (IF) signal.

[0124] Aspect 21: The wireless communication device of aspect 1, wherein the first route, the second route, the third route, and the fourth route are configured for mmW signals.

[0125] Aspect 22. A first diplexer having a merge control signal terminal, a control terminal, and a first data terminal coupled to a first port; a second diplexer having a merge clock signal terminal, a clock terminal, and a second data terminal coupled to a second port; a third diplexer having a chain clock signal terminal coupled to a first port of the plurality of chain mmW transceiver ports, a third data terminal coupled to the first data terminal, and a second control terminal coupled to the control terminal; the fourth diplexer having a chain control signal terminal coupled to the first diplexer, a fourth data terminal coupled to the second data terminal, and a second clock terminal coupled to the clock terminal, wherein the first route includes a signal path between the one or more antenna elements and the first data terminal, the second route includes a signal path between the one or more antenna elements and the second data terminal, the third route includes a signal path between the first data terminal and the third data terminal, and the fourth route includes a signal path between the second data terminal and the fourth data terminal.

[0126] Aspect 23. The wireless communications device of aspect 1, further comprising: a first diplexer having a merge control signal terminal, a control terminal, and a first data terminal coupled to the first port, a first chain signal port coupled to the first data terminal, a chain control port coupled to the control terminal, a second diplexer having a merge clock signal terminal, a clock terminal, and a second data terminal coupled to the second port, a second chain signal port coupled to the second data terminal, and a clock port coupled to the clock terminal.

[0127] Aspect 24. A method comprising: generating a first analog data signal and a second analog data signal; generating control data and clock data for the first analog data signal and the second analog data signal; merging the control data and the first analog data signal by an intermediate frequency (IF) transceiver to generate a merged control and data signal; merging the clock data and the second analog data signal by the IF transceiver to generate a merged clock and data signal; and communicating the first analog data signal and the second analog data signal between the IF transceiver and a target mmW transceiver via daisy chain routing, the daisy chain routing including at least the first mmW transceiver in the daisy chain routing between the IF transceiver and the target mmW transceiver.

[0128] Aspect 25. The method of aspect 24, further comprising: splitting the merged control and data signals using a first diplexer of the first mmW transceiver between the IF transceiver and the target mmW transceiver; splitting the merged clock and data signals using a second diplexer of the first mmW transceiver between the IF transceiver and the target mmW transceiver; and routing, by the first mmW transceiver, the clock signal, the control signal, the first analog data signal, and the second analog data signal to the target mmW transceiver.

[0129] Aspect 26. The method of any of aspects 24 and 25, further comprising receiving a third analog data signal, a fourth analog data signal, a second control signal, and a second clock signal at one or more antennas of the target mmW transceiver, and downconverting the third analog data signal and the fourth analog data signal from an mmW frequency to an IF frequency using frequency conversion circuitry of the target mmW transceiver.

[0130] Aspect 27. The method of aspect 26, further comprising: communicating a third analog data signal, a fourth analog data signal, a second control signal, and a second clock signal from the target mmW transceiver to the first mmW transceiver; merging the second control signal and the third analog data signal by a first diplexer of the first mmW transceiver to generate a second merged control and data signal; and merging the clock data and the second analog data signal by a second diplexer of the first mmW transceiver to generate a second merged clock and data signal.

[0131] Example 28. The method of example 27, further comprising: communicating a second merged control and data signal and a second merged clock and data signal from the first mmW transceiver to the IF transceiver; generating a second analog data signal by the IF transceiver using the second merged control and data signal and the second merged clock and data signal; converting the second analog data signal to a second digital data signal using an analog-to-digital converter coupled to the IF transceiver; and processing the second digital data signal using a processor coupled to the analog-to-digital converter.

[0132] Aspect 29. A wireless communications device comprising: a first millimeter wave (mmW) transceiver; and a second mmW transceiver coupled to the first mmW transceiver via a daisy chain routing path, the first mmW transceiver including a plurality of intermediate frequency (IF) transceiver connection ports, one or more antenna elements, and a switching circuit configured to select between connecting the plurality of IF transceiver connection ports to the one or more antenna elements and connecting the plurality of IF transceiver connection ports to the second mmW transceiver via the daisy chain routing path.

[0133] Aspect 30. The wireless communication device of Aspect 29, wherein the first mmW transceiver further includes a first diplexer coupled to a first port of the multiple IF transceiver connection ports, a first data port of the second mmW transceiver, and a control port of the second mmW transceiver, wherein the first diplexer is configured for bidirectional operation to convert between merged control and data signals communicated with the IF transceiver via the first port and separate control signal and first data signals communicated with the second mmW transceiver via the control port and the first data port, and wherein the daisy chain routing path includes the control port and the first data port.

[0134] Aspect 31. The wireless communications device of any of Aspects 29 and 30, wherein the first mmW transceiver further includes a second diplexer coupled to a second port of the multiple IF transceiver connection ports, a second data port of the second mmW transceiver, and a clock port of the second mmW transceiver, wherein the second diplexer is configured for bidirectional operation to convert between a merged clock and data signal communicated with the IF transceiver via the second port and separate clock and second data signals communicated with the second mmW transceiver via the control port and the second data port, and wherein the daisy chain routing path includes the clock port and the second data port.

[0135] Aspect 32: A wireless communication device comprising means for transmitting or receiving an mmW signal and means for communicating an IF signal used to generate the mmW signal to and from an mmW transceiver via daisy chain routing.

[0136] Aspect 33: A wireless communication device comprising means for selecting between means for transmitting or receiving an mmW signal and means for communicating an IF signal used to generate the mmW signal to an mmW transceiver via daisy chain routing.

[0137] Aspect 34: An apparatus comprising means for performing the operations according to any of aspects 1 to 31 above.

[0138] Aspect 35: A non-transitory computer-readable storage medium having stored thereon instructions that, when executed by one or more processors, cause the one or more processors to perform operations according to any of aspects 1 to 31 above.

Claims

1. 1. A wireless communication device, comprising: a first millimeter wave (mmW) transceiver, the first mmW transceiver comprising: a first port for communicating merged control and data signals; a second port for communicating a merged clock and data signal associated with the merged control and data signal; one or more antenna elements; a plurality of chain mmW transceiver ports; a portion of the merged clock and data signal and the merged control and data signal; a first route between the one or more antenna elements and the first port, and a second route between the one or more antenna elements and the second port; and switching circuitry controllable by control data to route between a third route between the first port and the plurality of chained mmW transceiver ports and a fourth route between the second port and the plurality of chained mmW transceiver ports.

2. and a second mmW transceiver, the second mmW transceiver comprising: a first port coupled to a first data port of the plurality of chain mmW transceiver ports; a second port coupled to a second data port of the plurality of chain mmW transceiver ports; 10. The wireless communication device of claim 1.

3. the first data port is a chain control and data port coupled to a first multiplexing diplexer of the first mmW transceiver; 3. The wireless communication device of claim 2, wherein the second data port is a chain clock and data port coupled to a second multiplexing diplexer of the first mmW transceiver.

4. the second mmW transceiver further includes a second clock port coupled to a first clock port of the plurality of chain mmW transceiver ports as part of a chain clock path; the second mmW transceiver further includes a second control port coupled to a first control port of the plurality of chain mmW transceiver ports as part of a chain control path; the first mmW transceiver includes a first diplexer that couples the first port of the first mmW transceiver to the first data port and the first clock port to demultiplex the merged clock and data signals into separate clock and data signals; 3. The wireless communication device of claim 2, wherein the first mmW transceiver includes a second diplexer that couples the second port of the first mmW transceiver to the second data port and the first control port for demultiplexing the merged control and data signals into separate control and data signals.

5. the first mmW transceiver: a first frequency conversion circuit in the first route configured to convert a first data signal associated with the merged control and data signal between an IF frequency and a mmW frequency; 3. The wireless communication device of claim 2, further comprising: a second frequency conversion circuit in the second route configured to convert a second data signal associated with the merged clock and data signal between the IF frequency and the mmW frequency.

6. 3. The wireless communication device of claim 2, wherein the first mmW transceiver further includes frequency conversion circuitry in the first route configured to convert a data signal associated with the merged control and data signal between a baseband frequency and an mmW frequency.

7. the second mmW transceiver: one or more second antenna elements; a second switching circuit, a fifth route coupling the first port to the one or more antenna elements, and a sixth route coupling the second port to the one or more antenna elements; a second switching circuit controllable by the control data to select between a seventh route coupling the first port to a first chain data port of the second mmW transceiver and an eighth route coupling the second port to a second chain data port of the second mmW transceiver; the second mmW transceiver: a first frequency conversion circuit in the fifth route configured to convert a first data signal associated with the merged control and data signal between an IF frequency and a mmW frequency; 3. The wireless communication device of claim 2, further comprising: a second frequency conversion circuit in the sixth route configured to convert a second data signal associated with the merged clock and data signal between the IF frequency and the mmW frequency.

8. and a third mmW transceiver, the third mmW transceiver comprising: one or more third antenna elements; a first port coupled to the first chain data port, the first port configured to communicate the first data signal associated with the merged control and data signal with the second mmW transceiver; a second port coupled to the second chain data port, the second port configured to communicate the second data signal associated with the merged clock and data signal with the second mmW transceiver; a third port coupled to a chain control port of the second mmW transceiver, the third port configured to communicate control signals associated with the merged control and data signal; a fourth port coupled to a chain clock port of the second mmW transceiver, the fourth port configured to communicate a clock signal associated with the merged clock and data signal; a processor; an intermediate frequency (IF) transceiver coupled to the processor, the IF transceiver comprising: an IF merged clock and data port coupled to the first port of the first mmW transceiver as part of a merged clock and data path for the merged clock and data signals; an IF merged control and data port coupled to the second port of the first mmW transceiver as part of a merged control and data path for the merged control and data signals.

9. 10. The wireless communication device of claim 8, wherein the wireless communication device is configured to transmit the first data signal and the second data signal via the one or more third antenna elements using the first data signal, the second data signal, the clock signal, and the control signal received from the IF transceiver via the first mmW transceiver and the second mmW transceiver.

10. the wireless communication device: receiving the first data signal, the second data signal, the clock signal, and the control signal at the one or more third antenna elements; communicating the first data signal and the control signal via the second mmW transceiver and the first mmW transceiver to the IF merge control and data port of the IF transceiver; communicating the second data signal and the clock signal via the second mmW transceiver and the first mmW transceiver to the IF merged clock and data port of the IF transceiver; configured to process the first data signal and the second data signal using the processor; the first mmW transceiver is configured to merge the first data signal and the control signal into the merged control and data signal using a first diplexer; 10. The wireless communication device of claim 9, wherein the first mmW transceiver is configured to merge the second data signal and the control signal into the merged clock and data signal using a second diplexer.

11. A display screen; a control circuit coupled to the display screen and the first mmW transceiver, the control circuit configured to transmit and receive data using daisy-chain routing that includes the first mmW transceiver; The wireless communication device of claim 1 , further comprising:

12. the first route includes a first transmit path variable gain amplifier (VGA), a first receive path VGA coupled between the first port and the one or more antenna elements, and a switching circuit for selecting between the first transmit path VGA and the first receive path VGA; the second route includes a second transmit path VGA, a second receive path VGA coupled between the second port and the one or more antenna elements, and a switching circuit for selecting between the second transmit path VGA and the second receive path VGA; the third route includes a first receive signal path VGA buffer, a first transmit signal path VGA buffer, and a switching circuit for selecting between the first receive signal path VGA buffer and the first transmit signal path VGA buffer; 2. The wireless communications device of claim 1, wherein the fourth route includes a second receive signal path VGA buffer, a second transmit signal path VGA buffer, and a switching circuit configured to select between the second receive signal path VGA buffer and the second transmit signal path VGA buffer.

13. the wireless communication device is configured to convert a baseband signal to a mmW signal without using an intermediate frequency (IF) signal; 10. The wireless communication device of claim 1, wherein the first route, the second route, the third route, and the fourth route are configured for mmW signals.

14. a first diplexer having a merge control signal terminal, a control terminal, and a first data terminal coupled to the first port; a second diplexer having a merged clock signal terminal, a clock terminal, and a second data terminal coupled to the second port; a third diplexer having a chain clock signal terminal coupled to a first one of the plurality of chain mmW transceiver ports, a third data terminal coupled to the first data terminal, and a second control terminal coupled to the control terminal; a fourth diplexer having a chain control signal terminal coupled to a second one of the plurality of chain mmW transceiver ports, a fourth data terminal coupled to the second data terminal, and a second clock terminal coupled to the clock terminal; the first route includes a first signal path between the one or more antenna elements and the first data terminal, the second route includes a second signal path between the one or more antenna elements and the second data terminal, the third route includes a third signal path between the first data terminal and the third data terminal, and the fourth route includes a signal path between the second data terminal and the fourth data terminal; 10. The wireless communication device of claim 1.

15. a first diplexer having a merge control signal terminal, a control terminal, and a first data terminal coupled to the first port; a first chain signal port coupled to the first data terminal; a chain control port coupled to the control terminal; a second diplexer having a merged clock signal terminal, a clock terminal, and a second data terminal coupled to the second port; a second chain signal port coupled to the second data terminal; a clock port coupled to the clock terminal; The wireless communication device of claim 1 , further comprising:

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