Filter module and antenna module including same

Abstract

A filter module is disclosed, which includes a first ground layer, a second ground layer spaced apart from the first ground layer, a first conductive pattern layer disposed between the first ground layer and the second ground layer, a second conductive pattern layer disposed on one side of the first ground layer or the second ground layer, and a via connecting at least two of the first ground layer, the second ground layer, the first conductive pattern layer, and the second conductive pattern layer.

Description

[Technical field]

[0001] The embodiments relate to a filter module or an antenna module having a Wi-Fi and Bluetooth (registered trademark, the same applies below) antenna, and a high frequency module having the same. [Background technology]

[0002] A filter for filtering a signal of a desired frequency band is applicable to various devices or fields including antennas, etc. Such a bandpass filter requires an inductor and a capacitor.

[0003] If such a bandpass filter is implemented using lumped constant elements such as inductors and capacitors, various problems arise, such as large insertion loss, high signal distortion rate, and increased thickness or size, and research into this issue is currently being conducted.

[0004] A Bluetooth (registered trademark, hereinafter the same) module is a device that is made up of a series of chips and antennas and communicates in the 2.4 to 2.5 GHz band according to the Bluetooth wireless interface standard at a distance of about 10 to 100 meters.

[0005] A Wi-Fi (Wireless Fidelity) module is a device that communicates over short distances, for example, in the 2.4 to 2.5 GHz band or the 5 GHz band, and enables wireless Internet using radio waves or infrared transmission methods where a wireless access point (AP) is installed, or enables communication by directly connecting (Wi-Fi Direct) with other Wi-Fi modules as a P2P concept.

[0006] Conventionally, such Bluetooth and Wi-Fi modules were constructed as independent (separate) modules and installed in electronic products. Therefore, when it was necessary to install both BT and Wi-Fi modules in a certain electronic product, various problems could arise in terms of product miniaturization, system safety, etc.

[0007] Specifically, the Bluetooth and Wi-Fi modules are both devices that communicate via RF signals and have elements that can be included in common with each other, but when they are configured as independent modules, such elements are often used redundantly, which can hinder product miniaturization, cause social waste of electronic components, and cause system instability due to the redundant configuration of elements.

[0008] In addition, while Bluetooth uses channels that overlap with Wi-Fi channels, it does not use the 5-6 GHz band. Therefore, Bluetooth antennas require filters that can filter out the 5-6 GHz band, but if a circuit is configured using passive elements, the size becomes large, which can reduce price competitiveness. Summary of the Invention [Problem to be solved by the invention]

[0009] The embodiments provide a filter module with improved performance and structure.

[0010] The embodiment provides a new antenna module that can solve the above problems.

[0011] The embodiment provides an antenna module with a Bluetooth filter built into the substrate without using passive elements.

[0012] An embodiment provides an antenna module without passive components, with a low pass filter integrated into the substrate and coupled to a Bluetooth antenna. [Means for solving the problem]

[0013] A filter module according to one embodiment may include a first ground layer, a second ground layer spaced apart from the first ground layer, a first conductive pattern layer disposed between the first ground layer and the second ground layer, a second conductive pattern layer disposed on one side of the first ground layer or the second ground layer, and vias connecting at least two of the first ground layer, the second ground layer, the first conductive pattern layer, and the second conductive pattern layer.

[0014] In one example, the first conductive pattern layer may include a capacitance pattern formed to have capacitance facing at least one of the first ground layer or the second ground layer.

[0015] In one example, the first conductive pattern layer may include a first inductance pattern formed to have an inductance.

[0016] In one example, the second conductive pattern layer may include a second inductance pattern formed to have an inductance.

[0017] In one example, the width of the inductance pattern may be smaller than the width of the capacitance pattern.

[0018] In one example, the second conductive pattern layer may include a first opening in which the second inductance pattern is disposed, and the first ground layer may include a second opening vertically overlapping the first opening.

[0019] In one example, each of the first and second inductance patterns may include an inductance pattern having a planar shape that is folded at least once in a horizontal direction, and a maximum number of horizontal folds of the first inductance pattern may be greater than a maximum number of horizontal folds of the second inductance pattern.

[0020] In one example, the capacitance pattern may include a second capacitor pattern forming a second capacitor, a first capacitor pattern spaced apart from one side of the second capacitor pattern to form a first capacitor, and a third capacitor pattern spaced apart from the other side of the second capacitor pattern to form a third capacitor.

[0021] In one example, the second capacitor pattern may include a first stub, a second stub disposed on one side of the first stub, and a third stub disposed on an opposite side to the one side of the first stub.

[0022] In one example, the first inductance pattern may include a first inductor pattern arranged to connect a first via and a second via to form a first inductor, a second inductor pattern arranged to connect the first via and the first capacitor pattern to form a second inductor, a fifth inductor pattern arranged to connect a third via and the third capacitor pattern to form a fifth inductor, and a sixth inductor pattern arranged to connect the third via and a fourth via to form a sixth inductor.

[0023] In one example, the second inductance pattern may include a third inductor pattern arranged to connect the first via and the fifth via to each other and to connect the fifth via and a sixth via to form a third inductor, and a fourth inductor pattern arranged to connect the sixth via and the third via to form a fourth inductor, and the sixth via may be connected to the second capacitor pattern.

[0024] In one example, the line width of at least one of the first to sixth inductor patterns may be 250 μm or less.

[0025] In one example, at least one of the first and third capacitor patterns may have a line width of 300 μm or more.

[0026] In one example, the length of at least one of the first to sixth inductor patterns may be equal to or less than ⅛ wavelength of the fundamental frequency.

[0027] A filter module according to another embodiment may include a second ground layer, a first conductive pattern layer stacked on the second ground layer and having a pattern embodying an inductor and a capacitor, a first ground layer stacked on the first conductive pattern layer, a second conductive pattern layer stacked on the first ground layer and including a transmission line having a pattern embodying an inductor, and a via vertically connecting the inductor and the capacitor of the first conductive pattern layer to the inductor of the second conductive pattern part.

[0028] An antenna module according to an embodiment of the present disclosure may include a substrate to which a first antenna is coupled, a low-pass filter section embedded in a portion of the substrate, and a first transmission line connecting the first antenna and the low-pass filter section. The low-pass filter section may include first to fourth conductive layers, and first to third dielectric layers respectively disposed between the first to fourth conductive layers. The first conductive layer may include a first pattern having a first via, a second pattern connected between one end of the first pattern and a second via, and a third pattern connected to a third via. The second conductive layer may include a first pattern having a first via, a second pattern connected between one end of the first pattern and a second via, and a third pattern connected to a third via. The second conductive layer may include a first pattern having a first via, a second pattern connected to a second via, and a third pattern connected to a third via. BetweenThe third conductive layer may include a fourth pattern facing the first pattern, and a fifth pattern spaced apart from the fourth pattern and facing the second via and the third pattern. The fourth conductive layer may include a sixth pattern connected between an internal second via and a ground via, and a seventh pattern connected between the second via and the third via. The first and third patterns of the first conductive layer, the fourth and fifth patterns of the third conductive layer, and the first and second dielectric layers may form first and second capacitors. The second pattern, the sixth pattern, and the seventh pattern may have a line shape and form first to third inductors.

[0029] According to an embodiment of the present disclosure, the first and third patterns of the first conductive layer and the fourth and fifth patterns of the third conductive layer may have a polygonal plate shape.

[0030] According to an embodiment of the present disclosure, an area of ​​a top surface of the fifth pattern may be smaller than an area of ​​a top surface of the third pattern and larger than an area of ​​a top surface of the first pattern.

[0031] According to an embodiment of the present disclosure, an area of ​​a top surface of the third pattern may be smaller than an area of ​​a top surface of the first pattern.

[0032] According to an embodiment of the present disclosure, the first conductive layer includes a first input / output pattern connected to the other end of the first pattern and the first transmission line, and a second pattern and the low pass filter unit. placed to the side and a second input / output pattern coupled to the second transmission line.

[0033] According to an embodiment of the present disclosure, a length of the sixth pattern may be longer than a length of the second pattern.

[0034] According to an embodiment of the present disclosure, the sixth pattern may have a greater number of folds than the second and seventh patterns.

[0035] According to an embodiment of the present disclosure, the first capacitor may include a first capacitance due to the first dielectric layer between a first pattern of the first conductive layer and a first circular pattern connected to a first via of the second conductive layer, and a second capacitance due to the second dielectric layer between the first circular pattern and the fourth pattern.

[0036] According to an embodiment of the present disclosure, the second capacitor may be connected to a fifth pattern, a third circular pattern connected to a third via of the second conductive layer, and a third pattern of the first conductive layer through a third via connected to a seventh pattern of the fourth conductive layer. The second capacitor may include a third capacitance between the third circular pattern and a fourth pattern, and a fourth capacitance between the fifth pattern and the third circular pattern by a first dielectric layer.

[0037] According to an embodiment of the present disclosure, the second capacitor may include a fifth capacitance formed by a first dielectric layer between a first via of the first conductive layer and a second circular pattern connected to a second via of the second conductive layer, and a sixth capacitance formed by a second dielectric layer between the second circular pattern and a fourth circular pattern connected to a second via of the third conductive layer.

[0038] According to an embodiment of the present disclosure, the third and fifth capacitances may be connected in parallel to each other, and the fourth and sixth capacitances may be connected in parallel to each other.

[0039] According to an embodiment of the present disclosure, the wireless communication device may include a WiFi module connected to the low pass filter unit via a second transmission line, and a second antenna connected to the WiFi module. The first antenna may be a Bluetooth antenna, and the second antenna may be a WiFi antenna.

[0040] According to the embodiment of the present disclosure, the low-pass filter section can pass the 2402 to 2480 MHz band and filter out the 5 to 6 GHz band.

[0041] A radio frequency module according to an embodiment of the present disclosure may include a low-pass filter section in which a first input / output pattern is electrically connected to a Bluetooth antenna and a second input / output pattern is electrically connected to a Wi-Fi module. The low-pass filter section may include first to fourth conductive layers, a dielectric layer disposed between the first to fourth conductive layers, and a plurality of vias that are vertically disposed through the first to fourth conductive layers and the dielectric layer and selectively connect patterns of different conductive layers. One side pattern of the first to third conductive layers and a dielectric layer disposed between the one side patterns of the first to third conductive layers face each other, and may form a first capacitor that is connected in parallel to a first branch node connected to the first input / output pattern. The first line pattern of the first conductive layer may form a first inductor that is connected in series to the first branch node. The second line pattern of the fourth conductive layer may form a second inductor that is connected in parallel to a third branch node that is connected to the other end of the first inductor. The third line pattern of the fourth conductive layer may form a third inductor connected in parallel to a second branch node connected between the second input / output pattern and the third branch node. The other side patterns of the first to third conductive layers and a dielectric layer disposed between the other side patterns of the first to third conductive layers face each other to form a second capacitor connected in series to the third inductor. The other end of the first capacitor, the other end of the second inductor, and the other end of the second capacitor may be connected to a ground pattern.

[0042] According to the embodiment of the present disclosure, the low-pass filter section can pass the 2402 to 2480 MHz band and filter out the 5 to 6 GHz band.

[0043] According to an embodiment of the present disclosure, each of the first to third branch nodes may be formed by a via disposed in the low-pass filter portion. Effect of the Invention

[0044] As is apparent from the above description, according to the filter module of the present disclosure, since an inductor of sufficient length is secured in a limited space, it is possible to design an inductor having a desired inductance. In addition, it is possible to improve frequency components and improve insertion loss. Therefore, it is possible to improve antenna efficiency and increase transmission distance and transmission speed. In addition, it is possible to reduce signal distortion rate since delay is improved. In addition, it is possible to reduce the thickness of the filter compared to a filter module using passive elements.

[0045] In addition, the embodiment can reduce the size of the antenna module by incorporating a filter in the substrate without using inductor and capacitor components. Also, the manufacturing cost of the antenna module can be reduced. Also, the low pass filter (LPF) incorporated in the substrate of the antenna module can be connected to the Bluetooth antenna to filter the 5 to 6 GHz band. Also, the insertion loss characteristic in the 5 to 6 GHz band can be -3 dB or less.

[0046] The features, structures, effects, etc. described in the embodiments are included in at least one embodiment of the present disclosure, but are not necessarily limited to one embodiment. In addition, the features, structures, effects, etc. exemplified in each embodiment may be combined with other embodiments or modified by those skilled in the art. Therefore, the contents related to such combinations and modifications should be interpreted as belonging to the scope of the present disclosure.

[0047] Although the present disclosure has been specifically illustrated and described based on the exemplary embodiment, it will be apparent to those skilled in the art that the embodiment is merely for illustrative purposes, does not limit the present disclosure, and various modifications in form and details are possible within the scope of the essential characteristics of the embodiment disclosed herein. For example, each configuration disclosed in the embodiment can be modified and applied. Furthermore, such modifications and differences in application should be interpreted as belonging to the scope of the present disclosure defined by the appended claims. [Brief description of the drawings]

[0048] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The arrangement and embodiments will be described in detail with reference to the accompanying drawings, in which like reference numerals refer to like elements. [Figure 1] FIG. 2 is a conceptual diagram illustrating a filter module according to an embodiment. [Diagram 2] FIG. 2 is a circuit diagram illustrating an embodiment of the filter module shown in FIG. [Figure 3a] 2A and 2B are a perspective view and a plan view of the second conductive pattern layer shown in FIG. [Figure 3b] 2A and 2B are a perspective view and a plan view of the second conductive pattern layer shown in FIG. [Figure 4a] 2A and 2B are a perspective view and a plan view of the first ground plane shown in FIG. [Figure 4b] 2A and 2B are a perspective view and a plan view of the first ground plane shown in FIG. [Figure 5a] 2A and 2B are a perspective view and a plan view of the first conductive pattern layer shown in FIG. [Figure 5b] 2A and 2B are a perspective view and a plan view of the first conductive pattern layer shown in FIG. [Figure 6a] 2A and 2B are a perspective view and a plan view of the second ground plane shown in FIG. [Figure 6b] 2A and 2B are a perspective view and a plan view of the second ground plane shown in FIG. [Figure 7] 1 is a graph showing an insertion loss according to frequency of a filter module according to an embodiment. [Figure 8]11 is a graph showing inductance by frequency realized by first and sixth inductor patterns. [Figure 9] 11 is a graph showing the capacitance of a second capacitor pattern according to frequency. [Figure 10] 1 is a graph showing the insertion loss of a filter module according to a comparative example and the insertion loss of a filter module according to an embodiment. [Figure 11] 1A and 1B are diagrams illustrating a connection structure of a filter module according to an embodiment. [Figure 12] FIG. 2 is a block diagram of an antenna module according to an embodiment of the present disclosure. [Figure 13] 13 is a plan view showing a part of the antenna module of FIG. 12. [Figure 14] FIG. 14 is a perspective view showing a low-pass filter portion of FIG. 13. [Figure 15] FIG. 15 is a side view showing the low-pass filter portion of FIG. 14. [Figure 16] FIG. 2 is a diagram showing a circuit configuration of a low-pass filter according to the present disclosure. [Figure 17] FIG. 15 is an exploded perspective view of the low-pass filter portion of FIG. 14. [Figure 18] 18 is a diagram showing the pattern configuration of first to fourth conductive layers of the low-pass filter section of FIG. 17. FIG. [Figure 19] 15 is a cross-sectional view of the low-pass filter portion of FIG. 14 taken along line AA. [Figure 20] 15 is a cross-sectional view of the low-pass filter portion of FIG. 14 taken along line BB. [Figure 21] 11 is a graph showing the operating characteristics of a low-pass filter section of an antenna module according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0049] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0050] The technical ideas of the present disclosure are not limited to the described embodiments, but may be embodied in various different forms, and one or more of the components may be selectively combined or substituted within the scope of the technical ideas of the present disclosure.

[0051] Furthermore, unless otherwise clearly defined and described, terms (including technical and scientific terms) used in the embodiments of the present disclosure may be interpreted as having a meaning commonly understood by a person having ordinary knowledge in the technical field to which the present disclosure belongs, and commonly used terms, such as terms defined in a dictionary, may be interpreted in light of the contextual meaning of the relevant art.

[0052] In addition, the terms used in the embodiments of the present disclosure are intended to describe the embodiments and are not intended to limit the present disclosure. In this specification, the singular form can include the plural form unless otherwise specified in the phrase, and when it is described as "at least one (or more) of A, B, and C," it can include one or more of all combinations that can be combined with A, B, and C.

[0053] In addition, in describing components of the embodiments of the present disclosure, terms such as first, second, A, B, (a), (b), etc. may be used. Such terms are merely used to distinguish the components from other components, and do not limit the essence, order, or sequence of the components.

[0054] Furthermore, when a component is described as being "coupled," "coupled," or "connected" to another component, it can include not only the case where the component is directly coupled, coupled, or connected to the other component, but also the case where the component is "coupled," "coupled," or "connected" via yet another component between the component and the other component.

[0055] In addition, when described as being formed or disposed "above (upper side) or below (lower side)" each component, above (upper side) or below (lower side) includes not only the case where two components are in direct contact with each other, but also the case where one or more other components are formed or disposed between the two components. In addition, when described as "above (upper side) or below (lower side)," it can include not only the meaning above but also the meaning below one component.

[0056] Hereinafter, the filter modules 10 and 10A according to the embodiments will be described with reference to the accompanying drawings. For convenience, the filter modules 10 and 10A will be described using a Cartesian coordinate system (x-axis, y-axis, z-axis), but it goes without saying that they can also be described using other coordinate systems. In addition, in the Cartesian coordinate system, the x-axis, y-axis, and z-axis are mutually orthogonal, but the embodiments are not limited thereto. That is, the x-axis, y-axis, and z-axis can also intersect with each other.

[0057] FIG. 1 is a schematic diagram showing a filter module 10 according to an embodiment.

[0058] 1 may include a first ground (or earth or reference potential) layer GL1, a second ground layer GL2, a first conductive pattern layer TL1, a second conductive pattern layer TL2, and a via VA. Each layer may be expressed as a first layer to a fourth layer.

[0059] The first ground plane GL1 and the second ground plane GL2 are disposed apart from each other.

[0060] The first conductive pattern layer TL1 is disposed between the first ground plane GL1 and the second ground plane GL2.

[0061] The second conductive pattern layer TL2 may be disposed on one side of the first ground plane GL1 or the second ground plane GL2. For example, as shown in FIG. 1, the second conductive pattern layer TL2 may be disposed on the first ground plane GL1.

[0062] As shown in the figure, the filter module 10 according to the embodiment may include a second conductive pattern layer TL2, a first ground plane GL1, the first conductive pattern layer TL1, and a second ground plane GL2 stacked in a vertical direction (e.g., z-axis direction). That is, the second conductive pattern layer TL2 may be disposed on the top of the filter module 10, the second ground plane GL2 may be disposed on the bottom of the filter module 10, and the first ground plane GL1 and the first conductive pattern layer TL1 may be stacked and arranged between the second conductive pattern layer TL2 and the second ground plane GL2.

[0063] The vias VA may be disposed between the first ground plane GL1, the second ground plane GL2, the first conductive pattern layer TL1, and the second conductive pattern layer TL2, respectively. The vias may be formed in a groove or hole shape and may serve as connection paths for electrical signals between layers.

[0064] The first conductive pattern layer TL1 has a pattern realizing an inductor and a capacitor, and the second conductive pattern layer TL2 includes a transmission line having a pattern realizing an inductor. Here, the via VA serves to vertically connect the inductor and the capacitor of the first conductive pattern layer TL1 to the inductor of the second conductive pattern layer TL2. The via VA may also serve to vertically connect the first ground layer GL1, the second ground layer GL2, the first conductive pattern layer TL1, and the second conductive pattern layer TL2.

[0065] Filters (eg, band pass filters) having various circuits can be realized using the filter module 10 shown in FIG.

[0066] Hereinafter, the configuration and operation of a bandpass filter 10A according to an embodiment implemented by the filter module 10 shown in Fig. 1 will be described, but the embodiment is not limited thereto. That is, the filter module 10 shown in Fig. 1 may also implement a filter having a different configuration or function from the bandpass filter 10A shown in Fig. 2.

[0067] FIG. 2 is a circuit diagram illustrating an embodiment 10A of the filter module 10 shown in FIG.

[0068] The filter module 10A shown in FIG. 2 may include first, second and third capacitors C1, C2, C3 and first, second, third, fourth, fifth and sixth inductors L1, L2, L3, L4, L5, L6.

[0069] The first inductor L1 is coupled between the first port P1 and ground, and the sixth inductor L6 is coupled between the second port P2 and ground.

[0070] The second inductor L2 and the first capacitor C1 may be connected in series between the first port P1 and ground, and the fifth inductor L5 and the third capacitor C3 may be connected in series between the second port P2 and ground.

[0071] The third inductor L3 and the fourth inductor L4 are connected in series between the first port P1 and the second port P2. The second capacitor C2 may be connected between a node N between the third inductor L3 and the fourth inductor L4 and ground.

[0072] Hereinafter, a specific embodiment of the filter module 10 shown in Fig. 1 that embodies the bandpass filter shown in Fig. 2 will be described with reference to Figs. 3a to 6b, but the embodiment is not limited thereto. Also, the filter module 10 according to the embodiment will be described as being arranged by stacking the second ground layer GL2, the first conductive pattern layer TL1, the first ground layer GL1, and the second conductive pattern layer TL2 in this order from bottom to top as shown in Fig. 1, but the embodiment is not limited thereto.

[0073] 3a and 3b are oblique and plan views of the second conductive pattern layer TL2 shown in FIG. 1, FIGS. 4a and 4b are oblique and plan views of the first ground layer GL1 shown in FIG. 1, FIGS. 5a and 5b are oblique and plan views of the first conductive pattern layer TL1 shown in FIG. 1, and FIGS. 6a and 6b are oblique and plan views of the second ground layer GL2 shown in FIG. 1.

[0074] 3a and 3b, the second conductive pattern layer TL2 includes a first body B1 having a first opening OP1 and a second inductance pattern. The first body B1 may be connected to ground. In this specification, the opening is an area where a conductive material is not disposed by etching or the like, and the body may be a relatively large ground area.

[0075] The second inductance pattern may be disposed in the first opening OP1 and formed to have an inductance. That is, the second conductive pattern layer TL2 may form the inductances of the third and fourth inductors L3 and L4 shown in FIG. 2 using transmission lines. Here, if the width of the transmission lines is too thick, the overall length of the lines of the third and fourth inductors L3 and L4 may become long, which may increase the size of the product. Therefore, the width of the lines is made small. The specific line width will be described later.

[0076] For example, the second inductance pattern may include a third inductor pattern LP3 and a fourth inductor pattern LP4.

[0077] The third inductor pattern LP3 may include a 3-1 inductor pattern LP31 that is arranged to connect the first via VA1 and the fifth via VA5 to each other and forms a 3-1 inductor, and a 3-2 inductor pattern LP32 that is arranged to connect the fifth via VA5 and the sixth via VA6 to form a 3-2 inductor. The third inductor formed by the 3-1 inductor and the 3-2 inductor corresponds to the third inductor L3 shown in FIG.

[0078] The fourth inductor pattern LP4 may be disposed to connect the sixth via VA6 and the third via VA3 to form a fourth inductor. The fourth inductor formed by the fourth inductor pattern LP4 corresponds to the fourth inductor L4 shown in FIG.

[0079] The first, fifth, sixth and third vias VA1, VA5, VA6 and VA3 and the third and fourth inductor patterns LP3 and LP4 arranged in the first opening OP1 are spaced apart from the first body B1.

[0080] The first and second ports P1 and P2 shown in Fig. 3b correspond to the first and second ports P1 and P2 shown in Fig. 2. The first port P1 may be an input port Rx and the second port P2 may be an output port Tx, or the first port P1 may be an output port Tx and the second port P2 may be an input port Rx. For example, the first port P1 may be connected to an IC pad (not shown) and the second port P2 may be connected to a Bluetooth (BT) antenna (not shown), but may be connected in the opposite direction, and the embodiment is not limited thereto.

[0081] 4a and 4b, the first ground plane GL1 includes a second body B2 having a second opening OP2. The second body B2 is connected to a ground or reference potential. The second opening OP2 may be arranged to overlap the first opening OP1 in the z-axis direction, which is perpendicular to the first opening OP1. Thus, the first, fifth, sixth and third vias VA1, VA5, VA6 and VA3, which are arranged in the first opening OP1 and spaced apart from the first body B1, may be arranged spaced apart from the second body B2.

[0082] If the first ground layer GL1 does not have the second opening OP2 and is shielded by ground, the first conductive pattern layer TL1 can be patterned without interference, but the length required to realize the third and fourth inductor patterns LP3 and LP4 may increase. Therefore, as shown in Fig. 4b, the second opening OP2 is formed in the first ground layer GL1 to realize a single coplanar waveguide structure.

[0083] Referring to FIG. 5a and FIG. 5b, the first conductive pattern layer TL1 includes a capacitance pattern and a first inductance pattern.

[0084] The capacitance pattern is formed to have capacitance facing at least one of the first ground plane GL1 or the second ground plane GL2. In the embodiment, the capacitance pattern is formed to face both the first ground plane and the second ground plane in both directions at the same time.

[0085] The first inductance pattern is formed to have an inductance.

[0086] The capacitance pattern may include a first capacitor pattern CP1, a second capacitor pattern CP2, and a third capacitor pattern CP3.

[0087] The first, second and third capacitor patterns CP1, CP2 and CP3 form first, second and third capacitors, respectively, which may correspond to the first, second and third capacitors C1, C2 and C3 shown in FIG.

[0088] The first capacitor pattern CP1 may be spaced apart from one side of the second capacitor pattern CP2, and the third capacitor pattern CP3 may be spaced apart from the other side of the second capacitor pattern CP2. Although each of the first and third capacitor patterns CP1 and CP3 is illustrated as having a rectangular planar pattern, embodiments are not limited to a particular planar shape of the pattern.

[0089] According to the embodiment, the second capacitor pattern CP2 may include a plurality of stubs. For example, the second capacitor pattern CP2 may include first, second and third stubs CP21, CP22 and CP23. The first stub CP21 may be located at the center, and the second stub CP22 and the third stub CP23 may be located on both sides of the first stub CP21. That is, the second stub CP22 may be located on one side of the first stub CP21, and the third stub CP23 may be located on the other side opposite to the one side of the first stub CP21.

[0090] A sixth via VA6 connected between the third inductor pattern LP3 and the fourth inductor pattern LP4 may be vertically connected to the second capacitor pattern CP2.

[0091] The first inductance pattern can include a first inductor pattern LP1, a second inductor pattern LP2, a fifth inductor pattern LP5, and a sixth inductor pattern LP6.

[0092] The first inductor pattern LP1 may be disposed to connect the first via VA1 and the second via VA2 to form a first inductor, which corresponds to the first inductor L1 shown in FIG.

[0093] The second inductor pattern LP2 may be disposed to connect the first via VA1 and the first capacitor pattern CP1 to form a second inductor, which corresponds to the second inductor L2 shown in Fig. 2. The second inductor pattern LP2 may be connected to the third inductor pattern LP3 through the first via VA1.

[0094] The fifth inductor pattern LP5 may be disposed to connect the third via VA3 and the third capacitor pattern CP3 to form a fifth inductor, which corresponds to the fifth inductor L5 shown in FIG.

[0095] The sixth inductor pattern LP6 may be disposed to connect the third via VA3 and the fourth via VA4 to form a sixth inductor, which corresponds to the sixth inductor L6 shown in FIG.

[0096] The fifth inductor pattern LP5 and the sixth inductor pattern LP6 may be connected to the fourth inductor pattern LP4 through a third via VA3.

[0097] According to an embodiment, the first or second inductance pattern may have a planar shape folded at least once in the horizontal direction. For example, the first inductor pattern LP1 and the sixth inductor pattern LP6 shown in FIG. 5b may have a planar shape folded twice in the horizontal direction, and the second inductor pattern LP2 and the fifth inductor pattern LP5 may each have a planar shape folded once in the horizontal direction.

[0098] 6a and 6b, the second ground plane GL2 includes a third body B3, which may be connected to the ground.

[0099] The above-mentioned bodies B1, B2, and B3 shown in Figures 3b, 4b, and 6b may be made of a conductive material, and the capacitance pattern shown in Figure 5b and the first inductance pattern shown in Figure 3b and the second inductance pattern shown in Figure 3b may also be made of a conductive material.

[0100] Referring to Figures 4b and 6b, each of the body B2 of the first ground layer GL1 and the body B3 of the second ground layer GL2 may include a third opening OP3 into which a shield can is inserted, but the third opening OP3 may be omitted.

[0101] In addition, among the first to fifteenth vias VA1 to VA15, the vias excluding the first, third, fifth and sixth vias VA1, VA3, VA5 and VA6 can also play a role in vertically connecting the second conductive pattern layer TL2, the first ground plane GL1, the first conductive pattern layer TL1 and the second ground plane GL2 to each other.

[0102] The first to fifteenth vias VA1 to VA15 may be made of a conductive material. In each of Figures 3b, 4b, and 5b, the portions having a doughnut planar shape are conductive line regions corresponding to the vias.

[0103] The conductive material mentioned above may be copper (Cu), however embodiments are not limited to any particular material.

[0104] In addition, a dielectric material (or dielectric) (EM) may be filled in the areas indicated in white in Figures 3b, 4b, 5b and 6b and the first and second openings OP1, OP2, and a dielectric material may also be filled between the second conductive pattern layer TL2 and the first ground plane GL1, between the first ground plane GL1 and the first conductive pattern layer TL1, and between the first conductive pattern layer TL1 and the second ground plane GL2.

[0105] The smaller the line width of each of the first to sixth inductor patterns LP1, LP2, LP3, LP4, LP5, and LP6 described above, the shorter the length of each of the patterns can be designed. Considering this, according to the embodiment, if the line width of each of the first to sixth inductor patterns LP1, LP2, LP3, LP4, LP5, and LP6 is greater than 250 μm, the efficiency of the inductor may decrease. Therefore, the line width of each of the first to sixth inductor patterns LP1, LP2, LP3, LP4, LP5, and LP6 may be 250 μm or less, but the embodiment is not limited thereto.

[0106] Meanwhile, if the line width of the first and third capacitor patterns CP1 and CP3 is less than 300 μm, the efficiency of the capacitor may be reduced. Therefore, according to an embodiment, the line width of each of the first and third capacitor patterns CP1 and CP3 may be 300 μm or more, but the embodiment is not limited thereto.

[0107] The length of each of the first to sixth inductor patterns LP1, LP2, LP3, LP4, LP5, and LP6 may be equal to or less than one-eighth of the wavelength at a fundamental frequency (for example, 2.4 GHz), where the fundamental frequency means a frequency at which the insertion loss becomes zero.

[0108] For example, the length of each of the first to sixth inductor patterns LP1, LP2, LP3, LP4, LP5, and LP6 may be the length between the vias. For example, referring to FIG. 3b, the length of the 3-1 inductor pattern LP31 arranged between the first via VA1 and the fifth via VA5 may be equal to or less than one-eighth of the wavelength at a fundamental frequency, for example, 2.4 GHz, and the length of the 3-2 inductor pattern LP32 arranged between the fifth via VA5 and the sixth via VA6 may be equal to or less than one-eighth of the wavelength at a fundamental frequency, for example, 2.4 GHz. Also, the lengths of each of the first and third capacitor patterns CP1 and CP3 in the x-axis direction and the y-axis direction may be equal to or less than one-eighth of the wavelength at a fundamental frequency, for example, 2.4 GHz. For example, the lengths of each of the first to sixth inductor patterns LP1, LP2, LP3, LP4, LP5, and LP6 and the first and third capacitor patterns CP1 and CP3 may be equal to or less than 4.5 mm.

[0109] The areas of the first to sixth inductor patterns LP1 to LP6 and the first to third capacitor patterns CP1, CP2, CP3 depend on the lengths and line widths.

[0110] Hereinafter, the operation of the filter module 10, 10A according to the embodiment that serves as the bandpass filter shown in FIG. 2 with the configuration shown in FIGS. 3a to 6b will be described with reference to the accompanying drawings.

[0111] FIG. 7 is a graph showing the insertion loss of the filter module 10A according to the embodiment as a function of frequency, where the horizontal axis indicates frequency and the vertical axis indicates insertion loss.

[0112] FIG. 8 is a graph showing inductance for each frequency realized by the first and sixth inductor patterns LP1 and LP6, in which the horizontal axis represents frequency and the vertical axis represents inductance.

[0113] By adjusting the line width and length of each of the first and sixth inductor patterns LP1 and LP6, the self-resonance frequency (SRF) of the first inductor pattern LP1 can be designed to be f1 as shown in FIG. 7, which is the second harmonic frequency of the Bluetooth antenna or WIFI signal, and the self-resonance frequency (SRF) of the sixth inductor pattern LP6 can be designed to be f2 as shown in FIG. 8, which is the second harmonic frequency of the Bluetooth antenna or WIFI signal. Here, when the fundamental frequency is 2.4 GHz, the frequency f1 at which transmission is zero can be 4.8 GHz, and f2 can be 5 GHz or 5.5 GHz. The line width for this purpose can be 80 μm to 200 μm, and the length can be a quarter wavelength at 4.8 GHz. The point where the transfer function of the first inductor L1, the second inductor L2, and the first capacitor C1 becomes zero corresponds to f1 shown in Figures 7 and 8, and the point where the transfer function of the fifth inductor L5, the sixth inductor L6, and the third capacitor C3 becomes zero corresponds to f2 shown in Figures 7 and 8.

[0114] In addition, the first and sixth inductors L1 and L6 can also function to remove low-frequency noise such as DC components, and can also function to match impedance.

[0115] The second inductor L2 realized by the second inductor pattern LP2 and the first capacitor C1 realized by the first capacitor pattern CP1 generate a transmission zero at the resonance frequency. Similarly, the fifth inductor L5 realized by the fifth inductor pattern LP5 and the third capacitor C3 realized by the third capacitor pattern CP3 generate a transmission zero at the resonance frequency. The resonance frequency can be designed to be the second harmonic frequency of the Bluetooth antenna or the Wi-Fi antenna.

[0116] FIG. 9 is a graph showing the capacitance of the second capacitor pattern CP2 for each frequency, where the horizontal axis represents frequency and the vertical axis represents capacitance.

[0117] The third inductor L3 realized by the third inductor pattern LP3, the fourth inductor L4 realized by the fourth inductor pattern LP4, and the second capacitor C2 realized by the second capacitor pattern CP2 generate a transmission zero at a resonant frequency. The third inductor L3, the fourth inductor L4, and the second capacitor C2 may determine the bandwidth of the filter.

[0118] When the second capacitor C2 is designed as a parasitic component, there are two perfect matching points (poles) in the passband, and when the second capacitor C2 is designed as a resonator, there are three perfect matching points (poles) in the passband.

[0119] The second capacitor C2 may have a three band stub shape. Referring to Fig. 9, the second capacitor C2 may be realized to have a transmission zero at a frequency f3 by combining the 2-1 capacitor C21 realized by the first stub CP21, the 2-2 capacitor C22 realized by the second stub CP22, and the 2-3 capacitor C23 realized by the third stub CP23. In Fig. 9, the resonance point f4 of the 2-1 capacitor C21 may be 9.6 GHz, the resonance point f5 of the 2-3 capacitor C23 may be 12 GHz, the resonance point f6 of the 2-2 capacitor C22 may be 14.4 GHz, and the overall resonance point f3 of the second capacitor C2 may be 7.2 GHz.

[0120] The second capacitor C2 has a configuration in which three resonators are combined, and can be designed to have a self-resonant frequency at a harmonic frequency of 2.4 GHz to 2.5 GHz, and multiple resonators can be combined as necessary.

[0121] Hereinafter, a filter module according to a comparative example and a filter module according to an embodiment will be described with reference to the accompanying drawings.

[0122] FIG. 10 is a graph showing the insertion loss 200 of the filter module according to the comparative example and the insertion loss 210 of the filter module according to the embodiment, in which the horizontal axis represents frequency and the vertical axis represents insertion loss.

[0123] Referring to FIG. 10, the filter module 210 according to the embodiment has a passband of 2.4 GHz to 2.5 GHz, and a 3 dB bandwidth of 2.2 GHz to 3.2 GHz.

[0124] The filter module 200 of the comparative example uses a lumped element such as a capacitor or an inductor to form a bandpass filter. Referring to Fig. 10, it can be seen that the filter module 200 of the comparative example 200 has a superior blocking performance of at least -30 dB in the harmonic generation section after 4.8 GHz.

[0125] In the embodiment, each of the first, second, third, fifth and sixth inductor patterns LP1, LP2, LP3, LP5, and LP6 is formed by folding at least once in the horizontal direction, so that sufficient length is ensured in a limited space, and the inductance of each of the inductors L1, L2, L3, L5, and L6 can be designed as desired.

[0126] Furthermore, according to the filter modules 10 and 10A of the embodiment, it is possible to improve harmonic components other than the original signal due to an oscillator (not shown) and a mixer (not shown) inside the IC.

[0127] In addition, the filter modules 10 and 10A according to the embodiments can improve impedance matching and insertion loss compared to a transmission line by controlling pole points. That is, when an antenna or element is connected to the first port P1 and the second port P2, matching is improved, so that the efficiency of the antenna is improved, the transmission distance is increased, and the transmission speed is also improved.

[0128] In the filter module of the comparative example, a band pass filter is formed using a lumped element such as a capacitor or inductor, and a large insertion loss occurs because a transmission line is separately present. On the other hand, in the embodiment, a band pass filter is formed using inductors L3 and L4 embodied using the transmission line itself, so that the wavelength is shortened, group delay is improved, and signal distortion rate can be reduced.

[0129] As a result, in the filter module 10, 10A according to the embodiment, the second conductive pattern layer TL2 is designed to minimize signal distortion by coupling with the transmission line, and the structure for blocking harmonic components is shielded and positioned between the first ground layer GL1 and the second ground layer GL2, so noise is not radiated and can be easily removed via ground. That is, according to the embodiment, a signal having a main frequency of 2.4GHz to 2.5GHz is designed to be directly connected to the existing transmission line, improving impedance matching to reduce insertion loss and improving signal distortion, and the blocked signal can flow to the ground to prevent re-entry and radiation.

[0130] The filter module according to the embodiment may be modularized and applied to communication devices or filters inside communication devices, including, for example, televisions for organic light emitting diodes (OLEDs), WIFI / BT combo modules, multi-antenna systems, repeaters for LTE / WIFI 5G and 6G, etc.

[0131] 11 is a diagram showing an example of a connection structure of a filter module according to an embodiment, and is a diagram for aiding in understanding the present disclosure. Although it overlaps with the above content, it shows the connection structure of the conductive patterns and is added to aid in understanding the structure.

[0132] FIG. 12 is a block diagram of an antenna module according to an embodiment of the present disclosure, FIG. 13 is a plan view showing a portion of the antenna module of FIG. 12, FIG. 14 is an oblique view showing the low-pass filter section of FIG. 13, FIG. 15 is a side view of the low-pass filter section of FIG. 14, FIG. 16 is a diagram showing an example of a circuit configuration of a low-pass filter according to the present disclosure, FIG. 17 is an exploded oblique view of the low-pass filter section of FIG. 14, FIG. 18 is a diagram showing the pattern form of the first to fourth conductive layers of the low-pass filter section of FIG. 17, FIG. 19 is a cross-sectional view of the low-pass filter section of FIG. 14 along line AA, FIG. 20 is a cross-sectional view of the low-pass filter section of FIG. 14 along line BB, and FIG. 21 is a graph showing the operating characteristics of the low-pass filter section of an antenna module according to an embodiment of the present disclosure.

[0133] Referring to FIG. 12, the antenna module includes a first antenna 210 for transmitting and receiving a first high frequency signal, a low pass filter unit 100 connected to transmission lines 251, 252 of the first antenna 210, a second antenna 220 for transmitting and receiving a second high frequency signal, and a communication signal processing unit 200 for generating and processing transmission / reception signals of the first and second antennas 210, 220.

[0134] The first antenna 210 may be a Bluetooth antenna, the second antenna 220 may be a Wi-Fi antenna, and the communication signal processor 200 may be implemented by a Wi-Fi module.

[0135] The first high frequency signal includes a Bluetooth signal, for example, a band of 2402 to 2480 MHz. The second high frequency signal includes a Wi-Fi signal, for example, a band of 2400 to 2483 MHz and 5 to 6 GHz. Here, the first high frequency signal uses a channel that overlaps with the low frequency band (for example, 2402 to 2480 MHz) of the second high frequency signal, but does not use a channel that overlaps with the high frequency band (for example, 5 to 6 GHz).

[0136] 13 to 15, the low-pass filter unit 100 is connected to transmission lines 251 and 252 between the first antenna 210 and the communication signal processing unit 200, and can pass a low frequency band and filter a high frequency band. The low-pass filter unit 100 can be connected between a first transmission line 251 connected to the first antenna 210 and a second transmission line 252 connected to the communication signal processing unit 200. The first and second transmission lines 251 and 252 are feeder lines for feeding signals.

[0137] The low-pass filter unit 100 may form a resonant circuit using inductors and capacitors, and the inductors and capacitors may be implemented by conductive layer patterns and dielectric layers rather than passive components, thereby eliminating the need for passive components, thereby reducing costs and reducing the size of the low-pass filter unit 100.

[0138] The first and second antennas 210 and 220 may be coupled to the substrate 250. The first antenna 210 may be coupled to a coupling portion 255 of the substrate 250, and the coupling portion 255 may be a coupling hole to which a lower coupling protrusion of the first antenna 210 is fastened. Any one of the coupling portions 255 of the substrate 250 may be connected to the first transmission line 251. Also, the low pass filter unit 100 may be embedded in the substrate 250 of the communication signal processor 200. The substrate 250 may be a multi-layer substrate having a number of conductive layers.

[0139] 16, the circuit configuration of the low pass filter unit 100 is realized by a passive filter having a first input / output port and a second input / output port for transmitting and receiving a signal, a first capacitor C1 is connected in parallel to a first branch node N1 connected to the first input / output port, and the other end of the first capacitor C1 is grounded. One end of a first inductor L1 is connected in series to the first branch node N1, the other end of the first inductor L1 is connected to a third branch node N3, one end of a second inductor L2 is connected in parallel to the third branch node N3, and the other end of the second inductor L2 is grounded.

[0140] A third inductor L3 has one end connected in parallel to a second branch node N2 connected to the second input / output port, and a second capacitor C2 is connected in series to the other end of the third inductor L3, and the other end of the second capacitor C2 is connected to ground. The second branch node N2 is connected in series to the third branch node N3.

[0141] Here, the first input / output port may be connected to or formed integrally with the first transmission line 251. The second input / output port may be connected to or formed integrally with the second transmission line 252. The low pass filter unit 100 passes a first frequency band (e.g., 2400 to 2483 MHz) transmitted to the first and second input / output ports and filters a second frequency band (e.g., 5 to 6 GHz).

[0142] The first to third inductors L1, L2, and L3 may have inductances in the range of 0.5 to 4 nH, and may have different inductances from each other. For example, the first inductor L1 may have an inductance in the range of 1.3 nH ± 0.2 nH, the second inductor L2 may have an inductance in the range of 2.7 nH ± 0.2 nH, and the third inductor L3 may have an inductance in the range of 1.5 nH ± 0.2 nH. The first and second capacitors C1 and C2 may have inductances in the range of 0.3 to 2.5 pF, and may be different from each other. The first capacitor C1 may have an inductance in the range of 0.9 pF ± 0.05 pF, and the second capacitor C2 may have an inductance in the range of 0.5 pF ± 0.01 pF, for example.

[0143] 14, 15 and 17 to 20, the low pass filter unit 100 may be a part of the substrate 250 of FIG. 13 or may be a substrate region embedded within the substrate 250. As shown in FIG.

[0144] The low pass filter unit 100 may include a number of conductive layers 110, 120, 130, 140 and a number of dielectric layers 151, 152, 153 disposed between the conductive layers 110, 120, 130, 140, respectively. The conductive layers 110, 120, 130, 140 may be copper or may have at least one plating layer laminated on the surface of the copper. The plating layer may include at least one of nickel, gold, tin, lead, palladium, silver, and a mixture thereof.

[0145] The dielectric layers 151, 152, and 153 may include at least one of insulating materials such as FR-4, CEM-1, RF-35, Teflon, polyimide, and PTEE (Polytetrafluoroethylene). The dielectric layers 151, 152, and 153 may include capacitor dielectrics such as Ta2O5, BaO4SrTi, TiO2, BaO, Al2O3, PbO, CaO, or B2O3.

[0146] The plurality of conductive layers 110, 1201, 130, 140 include first to fourth conductive layers 110, 1201, 130, 140 stacked from the upper surface to the lower surface of the substrate 250, and the plurality of dielectric layers 151, 152, 153 may include first to third dielectric layers 151, 152, 153 disposed between the first to fourth conductive layers 110, 1201, 130, 140, respectively. The first and second dielectric layers 151, 152 may include the dielectric of the capacitor, and the thickness of the second dielectric layer 152 may be greater than the thickness of the first dielectric layer 151. For example, the thickness of the first and third dielectric layers 151, 153 may be formed to be 300 μm or less, for example, in the range of 100 to 300 μm, and the thickness of the second dielectric layer 152 may be formed to be 300 μm or more, for example, in the range of 300 to 500 μm.

[0147] The first dielectric layer 151 is disposed between the first conductive layer 110 and the second conductive layer 120, the second dielectric layer 152 is disposed between the second conductive layer 120 and the third conductive layer 130, and the third dielectric layer 153 is disposed between the third conductive layer 130 and the fourth conductive layer. The first conductive layer 110 may be exposed on an upper surface of the substrate, and the fourth conductive layer 140 may be exposed on a lower surface of the substrate.

[0148] As shown in FIG. 14 and FIG. 15, the low pass filter unit 100 may have a width between the first side S1 and the third side S3 smaller than a length between the second side S2 and the fourth side S4. Thus, a conductive pattern of an inductor having a long length in a first direction (longitudinal direction) from the second side S2 to the fourth side S4 may be arranged. Also, a conductive pattern of an inductor having a short length in a second direction (width direction) from the first side S1 to the third side S3 may be arranged. The first conductive layer 110 may be exposed to an upper surface of the substrate, and the fourth conductive layer 140 may be exposed to a lower surface of the substrate. As shown in FIG. 15, a part of the pattern 132 of the second conductive layer 140 may be exposed to the side S3.

[0149] As shown in Figures 15 and 17, the first conductive layer 110 includes a first pattern 111, a second pattern 112, and a third pattern 119, the second conductive layer 120 has a ground pattern 121, the third conductive layer 130 includes a fourth pattern 131 and a fifth pattern 132 spaced apart from each other, and the fourth conductive layer 140 includes a sixth pattern 141 and a seventh pattern 142 connected to a second via V2.

[0150] The first pattern 111 and the second pattern 112 of the first conductive layer 110 are connected to a first via V1 and a second via V2 spaced apart in a first direction, the first pattern 111 being a polygonal plate-shaped pattern, and the second pattern 112 being a line-shaped pattern having a width smaller than the plate-shaped pattern width. The first pattern 111 has a first via V1 therein and is connected to one end of the second pattern 112, and the other end of the second pattern 112 is connected to the second via V2. The second pattern 112 has a bent structure, for example, two or more or three or more bent structures. The second pattern 112 can increase or decrease the inductance value depending on the bent shape and length. The length L1 of the second pattern 112 may be in the range of 0.5 to 3 mm. Here, the length L1 of the second pattern 112 is the length extending from one end to the other end. The width L1 of the second pattern 112 may be in the range of 10 to 200 μm.

[0151] One end of the first pattern 111 is connected to a second pattern 112, and the other end is connected to a first input / output pattern 113, and the second pattern 112 and a second via V2 are connected to a second input / output pattern 114. The first and second input / output patterns 113 and 114 are first and second input / output ports. The second via V2 may have a circular pattern around it, and the diameter of the circular pattern may be greater than the width of the second pattern 112.

[0152] The third pattern 119 may be a plate-like pattern having a third via V3 and may be spatially separated from the first and second patterns 111 and 112. The third pattern 119 may have a polygonal shape. A hemispherical pattern may be formed around one side of the third via V3. The area of ​​a top surface of the third pattern 119 may be smaller than the area of ​​a top surface of the first pattern 111. The third via V3 may be disposed between the fifth via V5 and the seventh via V7 in the first direction and may be closer to the seventh via V7 than the fifth via V5.

[0153] Patterns 115, 116, 117, and 118 having fifth to eighth vias V5 to V8 are arranged at each corner of the first conductive layer 110, and these patterns are physically separated from the first to third patterns 111, 112, and 119. In the first conductive layer 110, the patterns 115, 116, 117, and 118 having the fifth to eighth vias V5 to V8 may have a polygonal shape.

[0154] As shown in Figures 17 and 18, the second conductive layer 120 is a ground pattern 121, and the ground pattern 121 includes a first circular pattern P1 connected to the first via V1, a second circular pattern P2 connected to the second via V2, and a third circular pattern P3 connected to the third via V3.

[0155] The first to third circular patterns P1, P2, and P3 may be spaced apart from the ground pattern 121 by predetermined gaps Q1, Q2, and Q3, respectively. The first to third circular patterns P1, P2, and P3 are not physically connected to the ground pattern 121, respectively.

[0156] The ground pattern 121 may be connected to the fifth to eighth vias V5 to V8, and may have an upper surface area larger than the upper surface area of ​​the pattern of the first conductive layer 110 or larger than the upper surface area of ​​the pattern of the third conductive layer 130.

[0157] The third conductive layer 130 includes a fourth pattern 131 connected to the first via V1 and a fifth pattern 132 connected to the second via V2 and the third via V3. The fourth pattern 131 and the first pattern 111 of the first conductive layer 110 face each other on both sides of the ground pattern 121. An area of ​​an upper surface of the fourth pattern 131 may be larger than an area of ​​an upper surface of the first pattern 111.

[0158] The second via V2 disposed in the fifth pattern 132 may include a fourth circular pattern P4 and may be spaced apart from the fifth pattern 132 by a predetermined gap Q4. The fourth circular pattern P4 is not physically connected to the fifth pattern 132. The inner side of the fifth pattern 132 may be connected to the third pattern 119. The fifth pattern 132 and the second and third patterns 111 and 112 face each other on both sides of the ground pattern 121.

[0159] The fourth pattern 131 and the fifth pattern 132 may be implemented as polygonal plate-shaped patterns. The area of ​​the top surface of the fourth pattern 131 may be larger than the area of ​​the top surface of the first pattern 111 and may be larger than the area of ​​the top surface of the fifth pattern 132. Also, the area of ​​the top surface of the fifth pattern 132 may be larger than the area of ​​the top surface of the first pattern 111. Here, the polygon may include a rectangle.

[0160] Fifth to eighth vias V5 to V8 may be disposed at each corner of the third conductive layer 130, and the fifth to eighth vias V5 to V8 of the third conductive layer 130 may have a circular pattern. The gaps Q1, Q2, Q3, and Q4 may be filled with the material of the dielectric layer, as shown in FIGS.

[0161] The fourth conductive layer 140 includes a sixth pattern 141 and a seventh pattern 142, and the sixth pattern 141 and the seventh pattern 142 are connected by a second via V2. The sixth pattern 141 is a line pattern, extends between the second via V2 and the sixth via V6, and has a line shape having two or more bends, for example, four or more bends.

[0162] The total length of the sixth pattern 141 may be greater than the total length of the second pattern 112. The number of bends of the sixth pattern 141 may be greater than the number of bends of the second pattern 112, for example, greater than two. The length (total length) of the sixth pattern 141 (L2) is 3 to 10 mm. The width of the sixth pattern 141 (L2) is 10 to 200 μm.

[0163] The seventh pattern 142 is a line pattern, and is connected between the second via V2 and the third via V3, and may be a line shape having one or more bent structures, for example, two or more bent structures. The seventh pattern 142 (L3) has a length (total length) of 0.5 to 3 mm. The seventh pattern 142 (L3) has a width of 10 to 200 μm.

[0164] Fifth to eighth vias V5 to V8 are disposed at each corner of the fourth conductive layer 140, and the fifth to eighth vias V5 to V8 of the fourth conductive layer 140 may have a circular pattern.

[0165] Here, the first capacitor C1 may include a first capacitance by a first dielectric layer 151 between the first pattern 111 of the first conductive layer 110 and the first circular pattern P1 of the second conductive layer 120, and a second capacitance by a second dielectric layer 152 between the first circular pattern P1 and the fourth pattern 131. The first pattern 111 of the first conductive layer 110 and the fourth pattern 131 of the third conductive layer 130 may function as both side electrode terminals of a first capacitor. The first and second capacitances may be connected in series.

[0166] Here, the first inductor L1 is implemented by a second pattern 112 connected between the first pattern 111 and the second via V2. The inductance value of the first inductor L1 may vary depending on the length and / or area of ​​the second pattern 112. Each of the second pattern 112, the sixth pattern 116, and the seventh pattern 117 may be a line pattern for an inductor.

[0167] The second inductor L2 is implemented by a line-shaped sixth pattern 141 connected between the second via V2 and the sixth via V6 of the fourth conductive layer 140, and an inductance value may vary depending on the length and / or area of ​​the sixth pattern 141. The second inductor L2 may be connected to the ground pattern 121 through the sixth via V6. The inductance value of the sixth pattern 141 may be greater than the inductance value of the second pattern 112.

[0168] The third inductor L3 is implemented by a line-shaped seventh pattern 142 connected between the second via V2 and the third via V3, and an inductance value may vary depending on the length and / or area of ​​the seventh pattern 142. The inductance value of the seventh pattern 142 may be greater than the inductance value of the second pattern 112.

[0169] The second capacitor C2 may be formed to be connected to the fifth pattern 132, the third circular pattern P3, and the third pattern 119 through a third via V3 connected to the seventh pattern 142. Here, the second capacitor C2 may have a third capacitance due to the first dielectric layer 151 between the third pattern 119 and the third circular pattern P3, and a fourth capacitance due to the second dielectric layer 152 between the third circular pattern P3 and the fifth pattern 132. In addition, the second capacitor C2 may have a fifth capacitance due to the first dielectric layer 151 between the second via V2 and the second circular pattern P2, and a sixth capacitance due to the second dielectric layer 152 between the second circular pattern P2 and the fourth circular pattern P4. The third and fourth capacitances may be connected in series, and the fifth and sixth capacitances may be connected in series. The third and fifth capacitances may be connected in parallel with each other, and the fourth and sixth capacitances may be connected in parallel with each other. Therefore, the second capacitor C2 may have third to sixth capacitances by the two side patterns of the first and second dielectric layers 151 and 152 and may be connected to the seventh pattern 142 in series.

[0170] Since the first pattern 111 is provided to be larger than the area of ​​the third pattern 119 and the fourth pattern 131 is provided to be larger than the area of ​​the fifth pattern 132, the capacitance of the second capacitor C2 may be smaller than the capacitance of the first capacitor C1.

[0171] As shown in FIG. 19, the first via V1 is connected to the first pattern 111, the first circular pattern P1, and the fourth pattern 131, and the second via V2 is connected to the second pattern 112, the second circular pattern P2, the fourth circular pattern P4, and the sixth pattern 141.

[0172] As shown in FIG. 20, the third via V3 is connected to the third pattern 119, the third circular pattern P3, the fifth pattern 132, and the seventh pattern 142. The fifth via V5 is connected to the ground pattern 121 and may be connected to the via patterns of the first, third, and fourth conductive layers 110, 130, and 140. The fifth via V5 may not be connected to the via patterns of the third and fourth conductive layers 130 and 140. That is, the fifth, seventh, and eighth vias V5, V7, and V8 of the third and fourth conductive layers may be patterns arranged to support between two dielectric layers. The seventh via V7 is connected to the ground pattern 121 and may be connected to the via patterns of the first, third, and fourth conductive layers 110, 130, and 140.

[0173] The first, second and third branch nodes N1, N2 and N3 may be formed by first, second and third vias V1, V2 and V3 arranged in the low-pass filter unit 100, respectively.

[0174] As another example of the present disclosure, the conductive layers / dielectric layers of FIG. 17 may be arranged in reverse. For example, the pattern of the first conductive layer 110 may be arranged in the pattern of the fourth conductive layer, the pattern of the second conductive layer 110 may be arranged in the pattern of the third conductive layer, the pattern of the third conductive layer 130 may be arranged in the pattern of the second conductive layer, and the pattern of the fourth conductive layer 140 may be arranged in the pattern of the first conductive layer. That is, the configuration shown in FIG. 17 may be embedded in a substrate upside down or rotated 180 degrees to realize the patterns of each layer. In this case, the input / output patterns may be arranged in the fourth conductive layer 140 and connected to the transmission lines 251 and 252 via the lower surface of the substrate 250.

[0175] As described above, the low-pass filter unit 100 embedded in the substrate may have frequency response characteristics as shown in FIG. 21. In the S-parameters, S21 indicates the insertion loss of the low-pass filter, which is obtained by comparing the magnitude of the signal at the first input / output port with the magnitude of the signal output to the second input / output port, and it can be seen that it satisfies -3 dB or less in the 5 to 6 GHz band. That is, it can be seen that the low-pass filter unit 100 has a high filtering effect in the 5 to 6 GHz band. The closer the insertion loss is to 0, the better the signal flows. In the S-parameters, S11 indicates the reflection coefficient or return loss at the first input / output port, and S22 indicates the reflection coefficient or return loss at the second input / output port. The frequencies of the transmission zeros (-22.41, -26.01) in the S11 and S22 curves can be adjusted, with the 4.25 GHz transmission zero adjusted lower than the 2.45 GHz transmission zero, and a portion of the input power can be transmitted in the 5 GHz and above band, thereby setting values ​​for bandwidth control and frequency suppression.

[0176] The antenna module according to the embodiment of the present disclosure is a WiFi module having Bluetooth and WiFi antennas, and can be applied to high frequency modules such as mobile phones, TVs and moving vehicles that receive high frequency signals.

[0177] [Mode of invention] Aspects of the invention have been described above in the Detailed Description of the Invention. [Industrial Applicability]

[0178] The filter module according to the embodiment can be used in fields such as Wi-Fi modules including Bluetooth antennas and Wi-Fi antennas, high frequency modules for mobile phones, TVs and automobiles for receiving high frequency signals, and the like.

Claims

1. The first ground level and A second ground layer is positioned at a distance from the first ground layer, A first conductive pattern layer is disposed between the first ground layer and the second ground layer, A second conductive pattern layer disposed on one side of the first ground layer or the second ground layer, A filter module comprising: a first ground layer, a second ground layer, a first conductive pattern layer, and vias connecting at least two of the second conductive pattern layers.

2. The filter module according to claim 1, wherein the first conductive pattern layer includes a capacitance pattern formed to have capacitance facing at least one of the first ground layer or the second ground layer.

3. The filter module according to claim 2, wherein the first conductive pattern layer includes a first inductance pattern formed to have inductance.

4. The filter module according to claim 3, wherein the second conductive pattern layer includes a second inductance pattern formed to have inductance.

5. The filter module according to claim 4, wherein the width of the second inductance pattern is smaller than the width of the capacitance pattern.

6. The second conductive pattern layer includes a first opening on which the second inductance pattern is arranged. The filter module according to claim 5, wherein the first ground layer includes a second opening that is superimposed perpendicularly to the first opening.

7. Each of the first and second inductance patterns includes an inductance pattern having a planar shape that is bent at least once in the horizontal direction. The filter module according to claim 5, wherein the maximum number of horizontal bends of the first inductance pattern is greater than the maximum number of bends of the second inductance pattern.

8. The capacitance pattern is, A second capacitor pattern that forms a second capacitor, A first capacitor pattern is arranged spaced apart from one side of the second capacitor pattern and forms the first capacitor, The filter module according to claim 5, comprising: a third capacitor pattern disposed at a distance from the other side of the second capacitor pattern and forming a third capacitor.

9. The second capacitor pattern is The first stub and, A second stub is positioned on one side of the first stub, The filter module according to claim 8, comprising a third stub disposed on the opposite side of the first stub.

10. The first inductance pattern is A first inductor pattern is arranged to connect a first via and a second via to form a first inductor, A second inductor pattern is arranged to connect the first via and the first capacitor pattern to form a second inductor, A fifth inductor pattern is arranged to connect the third via and the third capacitor pattern to form a fifth inductor, The filter module according to claim 8, further comprising: a sixth inductor pattern arranged to connect the third via and the fourth via to form a sixth inductor.

11. The second inductance pattern is, A third inductor pattern is arranged such that the first via and the fifth via are connected to each other, and the fifth via and the sixth via are connected to form a third inductor. The system includes a fourth inductor pattern arranged to connect the sixth via and the third via to form a fourth inductor, The filter module according to claim 10, wherein the sixth via is connected to the second capacitor pattern.

12. The filter module according to claim 11, wherein at least one of the first to sixth inductor patterns has a line width of 250 μm or less.

13. The filter module according to claim 8, wherein at least one of the first and third capacitor patterns has a line width of 300 μm or more.

14. The filter module according to claim 11, wherein the length of at least one of the first to sixth inductor patterns is less than or equal to one-eighth of a wavelength of the fundamental frequency.

15. The second ground level, A first conductive pattern layer is laminated on the second ground layer and has patterns that embody an inductor and a capacitor, A first ground layer laminated on the first conductive pattern layer, A second conductive pattern layer is laminated on the first ground layer and includes a transmission line having a pattern that embodies an inductor, A filter module including vias that vertically connect the inductor and capacitor of the first conductive pattern layer and the inductor of the second conductive pattern layer.

16. A substrate to which the first antenna is attached, A low-pass filter section embedded in a part of the aforementioned substrate, The system includes a first transmission line connecting the first antenna and the low-pass filter section, The low-pass filter section includes first to fourth conductive layers and first to third dielectric layers disposed between the first to fourth conductive layers, The first conductive layer includes a first pattern having a first via, a second pattern connected between one end of the first pattern and a second via, and a third pattern connected to a third via. The second conductive layer has a ground pattern with gaps between it and the first to third vias inside, The third conductive layer includes a fourth pattern facing the first pattern, and a fifth pattern separated from the fourth pattern and facing the second via and the third pattern. The fourth conductive layer includes a sixth pattern connected between the second via and the ground via inside, and a seventh pattern connected between the second via and the third via. The first and third patterns of the first conductive layer, the fourth and fifth patterns of the third conductive layer, and the first and second dielectric layers form the first and second capacitors. An antenna module in which the second pattern, the sixth pattern, and the seventh pattern have a linear shape and form the first to third inductors.

17. The antenna module according to claim 16, wherein the first pattern and the third pattern of the first conductive layer, and the fourth pattern and the fifth pattern of the third conductive layer have a polygonal plate shape.

18. The antenna module according to claim 16, wherein the area of ​​the upper surface of the fifth pattern is smaller than the area of ​​the upper surface of the third pattern and larger than the area of ​​the upper surface of the first pattern.

19. The antenna module according to claim 16, wherein the area of ​​the upper surface of the third pattern is smaller than the area of ​​the upper surface of the first pattern.

20. The first conductive layer is The other end of the first pattern and the first input / output pattern connected to the first transmission line, The antenna module according to claim 16, comprising the second pattern and a second input / output pattern connected to a second transmission line located on the other side of the low-pass filter section.

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