Indicates the substrate

Abstract

A display substrate is provided. The display substrate includes a display area (AA) and a peripheral area (NA), and includes a base substrate (101), a plurality of sub-pixels (SP) located on the base substrate (101), a first power signal line (VDD), a second power signal line (VSS), a first power signal bus (VDB), and a second power signal bus (VSB). The plurality of sub-pixels (SP) are located in the display area (AA). The first power signal line (VDD) and the second power signal line (VSS) are at least partially located in the display area (AA). The first power signal line (VDD) is configured to transmit a first power signal to at least some of the sub-pixels (SP). The second power signal line (VSS) is configured to transmit a second power signal to at least some of the sub-pixels (SP). The first power signal bus (VDB) and the second power signal bus (VSB) are located in the peripheral area (NA). The first power signal line (VDD) is electrically connected to the first power signal bus (VDB). The second power signal line (VSS) is electrically connected to the second power signal bus (VSB). The second power signal bus (VSB) includes a first portion (VSB1) provided on the side of the first power signal bus (VDB) close to the display area (AA) and a second portion (VSB2) provided on the side of the first power signal bus (VDB) away from the display area (AA), thereby at least partially surrounding the first power signal bus (VDB). The display substrate has a better display effect.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate.

Background Art

[0002] In the field of displays, organic light-emitting diode (OLED) display panels have characteristics such as self-emission, high contrast, low energy consumption, wide viewing angle, fast response speed, being applicable to flexible panels, wide operating temperature range, and easy manufacturing, and thus have promising future applications.

Summary of the Invention

[0003] At least one embodiment of the present disclosure is a display substrate, comprising a display area and a peripheral area at least partially surrounding the display area, and a base substrate, a plurality of sub-pixels provided on the base substrate and located in the display area, and a first power signal line and a second power signal line provided on the base substrate and at least partially located in the display area, wherein the first power signal line is configured to transmit a first power signal to at least a part of the plurality of sub-pixels, and the second power signal line is configured to transmit a second power signal different from the first power signal to at least a part of the plurality of sub-pixels, the first power signal line and the second power signal line, and a first power signal bus and a second power signal bus provided on the base substrate and located in the peripheral area, wherein the first power signal line is electrically connected to the first power signal bus, and the second power signal line is electrically connected to the second power signal bus, the first power signal bus and the second power signal bus, and the second power signal bus includes a first portion provided on a side of the first power signal bus close to the display area and a second portion provided on a side of the first power signal bus away from the display area, thereby at least partially surrounding the first power signal bus, providing a display substrate.

[0004] For example, the display substrate according to at least one embodiment of the present disclosure further includes a light-shielding layer provided on the base substrate, Each of the plurality of sub-pixels includes a light-emitting device and a pixel driving circuit for driving the light-emitting device, and the pixel driving circuit is provided on a side of the light-shielding layer away from the base substrate, The first power signal bus is provided in the same layer as the light-shielding layer.

[0005] For example, in the display substrate according to at least one embodiment of the present disclosure, the pixel driving circuit includes a thin-film transistor, and the thin-film transistor includes a gate provided on a side of the light-shielding layer away from the base substrate and a source-drain electrode provided on a side of the gate away from the base substrate, The first portion is provided in the same layer as the source-drain electrode.

[0006] For example, in the display substrate according to at least one embodiment of the present disclosure, the second portion is provided in the same layer as the gate.

[0007] For example, in the display substrate according to at least one embodiment of the present disclosure, the second power signal bus further includes a third portion and a fourth portion that electrically connect the first portion and the second portion, and the third portion and the fourth portion are located on opposite sides of the first power signal bus, The first portion, the second portion, the third portion, and the fourth portion jointly surround the first power signal bus.

[0008] For example, in the display substrate according to at least one embodiment of the present disclosure, the third portion and the fourth portion are provided in the same layer as the first portion and are integrally connected to the first portion.

[0009] For example, in the display substrate according to at least one embodiment of the present disclosure, the structures of the third portion and the fourth portion are symmetric.

[0010] For example, a display substrate according to at least one embodiment of the present disclosure is provided on the same layer as the first power signal bus, and further includes a first power connection line that electrically connects the first power signal bus and the first power signal line.

[0011] For example, in a display substrate according to at least one embodiment of the present disclosure, the first power signal line is provided on the same layer as the source-drain electrode and is electrically connected to the first power connection line via an adapter via.

[0012] For example, in a display substrate according to at least one embodiment of the present disclosure, the second power signal line is provided on the same layer as the source-drain electrode.

[0013] For example, in a display substrate according to at least one embodiment of the present disclosure, the second power signal line extends from the display area to the peripheral area and is electrically connected to the first portion.

[0014] For example, in a display substrate according to at least one embodiment of the present disclosure, the potential of the first power signal is higher than the potential of the second power signal.

[0015] For example, a display substrate according to at least one embodiment of the present disclosure is provided on a side of the source-drain electrode away from the base substrate, includes a planarization layer provided in the peripheral area and having a first via exposing the first portion and a second via provided in the display area and exposing the source-drain electrode, and a first electrode layer provided on a side of the planarization layer away from the base substrate, including a first electrode provided in the display area and a connection electrode provided in the peripheral area, the first electrode being electrically connected to the source-drain electrode via the second via, and the connection electrode being electrically connected to the first portion via the first via.

[0016] For example, a display substrate according to at least one embodiment of the present disclosure is provided on a side of the first electrode layer away from the base substrate, includes a connection opening provided in the peripheral region and a sub-pixel opening provided in the display region, the connection opening exposes the connection electrode, and the sub-pixel further includes a pixel definition layer that exposes the first electrode.

[0017] For example, a display substrate according to at least one embodiment of the present disclosure further includes a light-emitting material layer at least partially provided in the sub-pixel opening, a second electrode layer provided on a side of the light-emitting material layer away from the base substrate, extending from the display region to the peripheral region, and electrically connected to the connection electrode through the connection opening.

[0018] For example, in a display substrate according to at least one embodiment of the present disclosure, the second electrode layer ends at a side of the first power signal bus close to the display region and is spaced apart from the first power signal bus.

[0019] For example, in a display substrate according to at least one embodiment of the present disclosure, in a direction perpendicular to the base substrate, the first portion at least partially overlaps the first power connection line, and the first portion includes a first cutout portion that overlaps the first power connection line in a direction perpendicular to the base substrate.

[0020] For example, in a display substrate according to at least one embodiment of the present disclosure, the first portion includes a second cutout portion that does not overlap the first power connection line in a direction perpendicular to the base substrate.

[0021] For example, in a display substrate according to at least one embodiment of the present disclosure, in a direction perpendicular to the base substrate, at least one of the third portion and the fourth portion at least partially overlaps the first power connection line, and at least one of the third portion and the fourth portion includes a third cutout portion that overlaps the first power connection line in a direction perpendicular to the base substrate.

[0022] For example, in a display substrate according to at least one embodiment of the present disclosure, the first power connection line includes a first wiring portion extending along a first direction and a second wiring portion extending along a second direction, where the first direction is different from the second direction. In a direction perpendicular to the base substrate, the first wiring portion at least partially overlaps with the first portion and partially overlaps with the first cutout, and the second wiring portion overlaps with at least one of the third portion and the fourth portion and partially overlaps with the third cutout.

Brief Description of the Drawings

[0023] To more clearly explain the technical solution of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It is clear that the drawings in the following description are only related to some embodiments of the present disclosure and do not limit the present disclosure.

[0024]

Figure 1

Figure 2A

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Figure 8A

Figure 8B

Figure 9A

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Figure 10A

Figure 10B

Figure 11A

Figure 11B

Figure 12A

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Figure 13A

Figure 13B

Embodiments for Carrying Out the Invention

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings of the embodiments of the present disclosure. It is obvious that the described embodiments are only a part of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts shall be included in the protection scope of the present disclosure.

[0026] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those skilled in the art. The "first", "second", and similar words used in the present disclosure do not indicate order, quantity, or importance, but are only used to distinguish different components. Terms such as "include" or "contain" mean that the elements or things appearing before the term include, without excluding other elements or things, the elements or things listed after the term and their equivalents. The terms "connect" or "couple" or similar terms are not limited to physical or mechanical connections, and may include direct or indirect electrical connections. "Above", "below", "left", "right", etc. are used to express relative positional relationships, and when the absolute position of the described object changes, the relative positional relationships change accordingly.

[0027] As the display device increases in screen size and has a narrower bezel, it is necessary to minimize the layout space for structures such as the control circuit and power bus in the peripheral area of the display substrate. For this reason, if the circuit configuration is too compact, signal crosstalk and other problems are likely to occur. Therefore, how to rationally utilize the limited layout space to layout the above circuit structure becomes an important issue in optimizing the display substrate structure.

[0028] Among a plurality of sub-pixels of the display substrate, the pixel driving circuit is usually implemented with a structure such as 3T1C (three thin-film transistors and one storage capacitor), 7T1C (seven thin-film transistors and one storage capacitor), 8T1C (eight thin-film transistors and one storage capacitor), or 8T2C (eight thin-film transistors and two storage capacitors), and serves to drive the light-emitting device. For example, hereinafter, the pixel driving circuit with a 3T1C structure will be described as an example, but in the embodiments of the present disclosure, the specific structure of the pixel driving circuit is not limited.

[0029] For example, the pixel driving circuit with the 3T1C structure includes a driver circuit for driving the light-emitting device to emit light and a detector circuit for detecting the electrical characteristics of the sub-pixel to achieve external compensation. For example, FIG. 1 shows a schematic diagram of an example of a 3T1C pixel driving circuit according to at least one embodiment of the present disclosure.

[0030] Referring to FIG. 1, the pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst. The first transistor T1 is, for example, a driving transistor, and the second transistor T2 is, for example, a data writing transistor. The first source-drain electrode of the second transistor T2 is electrically connected to the first capacitive electrode Ca of the storage capacitor Cst and the gate of the first transistor T1. The second source-drain electrode of the second transistor T2 is configured to receive a data signal DT. The second transistor T2 is configured to write the data signal DT to the gate of the first transistor T1 and the storage capacitor Cst in response to a first control signal G1. The first source-drain electrode of the first transistor T1 is electrically connected to the second capacitive electrode Cb of the storage capacitor Cst and is configured to be electrically connected to the first electrode of the light-emitting device EM. The second source-drain electrode of the first transistor T1 is configured to receive a first power supply voltage V1 (for example, receive a high power supply voltage via a power signal line VDD). The first transistor T1 is configured to control a current for driving the light-emitting device under the control of the voltage of the gate of the first transistor T1. The first source-drain electrode of the third transistor T3 is electrically connected to the first source-drain electrode of the first transistor T1 and the second capacitive electrode Cb of the storage capacitor Cst. The second source-drain electrode of the third transistor T3 is configured to be connected to an external detection circuit by being connected to a detection line SEN. The third transistor T3 is configured to detect the electrical characteristics of the sub-pixel to which the detection of the second control signal G2 belongs and to achieve external compensation. The electrical characteristics include, for example, the threshold voltage and / or carrier mobility of the first transistor T1, or the threshold voltage and driving current of the light-emitting device EM, etc. The external detection circuit includes, for example, ordinary circuits such as a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC), and details thereof will not be described in detail in the embodiments of the present disclosure.

[0031] For example, the storage capacitor Cst shown in FIG. 1 further includes a third capacitive electrode Cc. The third capacitive electrode Cc is located on the side away from the second capacitive electrode Cb of the first capacitive electrode Ca and is electrically connected to the second capacitive electrode Cb to form a structure of a parallel capacitor, thereby increasing the capacitance value of the storage capacitor Cst. For example, the second electrode of the light-emitting device EM is electrically connected to the power signal line VSS and receives a low power supply voltage.

[0032] All the transistors used in the embodiments of the present disclosure may be thin-film transistors or other switching devices having the same characteristics. Since the source and drain of the transistors used herein may be structurally symmetric, the source and drain thereof may not be structurally distinguished. In the embodiments of the present disclosure, in order to distinguish the two electrodes other than the gate of the transistor, one of the electrodes is expressed as the first source-drain electrode and the other electrode is expressed as the second source-drain electrode. Further, depending on the characteristics of the transistor, the transistor may be classified into an N-type transistor and a P-type transistor. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other appropriate voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other appropriate voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V or other appropriate voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other appropriate voltages). In the following description, the case where the transistor in FIG. 1 is an N-type transistor is taken as an example for description, but such description does not limit the present disclosure.

[0033] Hereinafter, the operating principle of the pixel driving circuit shown in FIG. 1 will be described with reference to the signal timing diagrams shown in FIGS. 2A to 2C. FIG. 2A shows the signal timing diagram during the display of the pixel driving circuit, and FIGS. 2B and 2C show the signal timing diagrams during the detection of the pixel driving circuit.

[0034] For example, as shown in FIG. 2A, the display of an image for each frame includes a data writing and reset stage 1 and a light emitting stage 2. FIG. 2A shows the timing waveforms of the respective signals in each stage. As an example of the operation process of the 3T1C pixel driving circuit, in the data writing and reset stage 1, both the first control signal G1 and the second control signal G2 are on signals, the second transistor T2 and the third transistor T3 are conducting, the data signal DT is transmitted by the second transistor T2 to the gate of the first transistor T1, the first switch K1 is turned off, the analog-to-digital converter writes a reset signal to the first electrode (for example, the anode) of the light emitting device EM via the detection line SEN and the third transistor T3, the first transistor T1 conducts to drive a driving current to charge the first electrode of the light emitting device to an operating voltage, and in the light emitting stage 2, both the first control signal G1 and the second control signal G2 are off signals, due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst is held constant, the first transistor T1 operates in a saturated state and the current remains unchanged to drive the light emitting device to emit light, are included.

[0035] For example, FIG. 2B shows a signal timing diagram in the case of detecting the threshold voltage by the pixel driving circuit. As an example of the operation process of the 3T1C pixel driving circuit, both the first control signal G1 and the second control signal G2 are on signals, the second transistor T2 and the third transistor T3 are conducting, the data signal DT is transmitted by the second transistor T2 to the gate of the first transistor T1, the analog-to-digital converter writes a reset signal to the first electrode (node S) of the light emitting device EM via the detection line SEN and the third transistor T3, the first transistor T1 conducts to charge node S until the first transistor T1 is cut off, the digital-to-analog converter samples the voltage on the detection line SEN to obtain the threshold voltage of the first transistor T1, are included. This process may be performed, for example, when the display device is shut down.

[0036] For example, FIG. 2C shows a signal timing diagram in the case of detecting the carrier mobility by the pixel driving circuit. As an example of the operation process of the 3T1C pixel driving circuit, in the first stage, both the first control signal G1 and the second control signal G2 are on signals, the second transistor T2 and the third transistor T3 are conducting, and the data signal DT is transmitted to the gate of the first transistor T1 via the second transistor T2, and the analog-to-digital converter writes a reset signal to the first electrode (node S) of the light-emitting device EM via the detection line SEN and the third transistor T3. In the second stage, the first control signal G1 is an off signal, the second control signal G1 is an on signal, the second transistor T2 is cut off, the third transistor T3 is conducting, the detection line SEN is floated, and due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst is held constant, the first transistor T1 operates in a saturation state, and the current remains unchanged to drive the light-emitting device to emit light. Then, the digital-to-analog converter samples the voltage on the detection line SEN and calculates the carrier mobility in the first transistor T1 in combination with the magnitude and duration of the emission current. For example, this process may be performed during the blanking stage between display stages.

[0037] Through the above detection, the electrical characteristics of the first transistor T1 can be obtained, and the corresponding compensation algorithm can be realized.

[0038] For example, the peripheral region of the display substrate includes power buses that supply power signals to the power signal line VDD and the power signal line VSS, respectively. Since the power signal line VDD transmits a high-level signal, this high-level signal is likely to cause crosstalk with other signals transmitted on the display substrate. Therefore, optimization of the layout design of the power buses is required.

[0039] At least one embodiment of the present disclosure provides a display substrate, which includes a display area and a peripheral area at least partially surrounding the display area, and includes a base substrate, a plurality of sub-pixels provided on the base substrate and located in the display area, and a first power signal line and a second power signal line provided on the base substrate and at least a part of which is located in the display area. The first power signal line is configured to transmit a first power signal to at least a part of the plurality of sub-pixels, and the second power signal line is configured to transmit a second power signal different from the first power signal to at least a part of the plurality of sub-pixels. The first power signal line and the second power signal line, and a first power signal bus and a second power signal bus provided on the base substrate and located in the peripheral area. The first power signal line is electrically connected to the first power signal bus, and the second power signal line is electrically connected to the second power signal bus. The second power signal bus includes a first part provided on the side of the first power signal bus close to the display area and a second part provided on the side of the first power signal bus away from the display area, thereby at least partially surrounding the first power signal bus.

[0040] In the above display substrate according to the embodiment of the present disclosure, in the peripheral area, the second power signal bus at least partially surrounds the first power signal bus, thereby playing a role in blocking electromagnetic interference to the first power signal bus, making the signal transmission by the first power signal bus more accurate, and improving the display effect of the display substrate.

[0041] Hereinafter, the display substrate according to the embodiment of the present disclosure will be described in detail with several specific embodiments.

[0042] At least one embodiment of the present disclosure provides a display substrate. FIG. 3 shows a plane schematic diagram of the display substrate, FIG. 4 shows an enlarged schematic diagram of the display substrate in the dashed box area in FIG. 3, FIG. 5 shows an enlarged schematic diagram of the display substrate in the dashed box area in FIG. 4, and FIG. 6 shows a cross-sectional schematic diagram of a part of the sub-pixels of the display substrate.

[0043] As shown in FIG. 3, the display substrate includes a display area AA and a peripheral area NA that at least partially surrounds the display area AA. Referring to FIGS. 3 to 6, the display substrate further includes structures such as a base substrate 101, a plurality of sub-pixels SP, a first power signal line VDD, a second power signal line VSS, a first power signal bus VDB, and a second power signal bus VSB.

[0044] The plurality of sub-pixels SP are provided on the base substrate 101 and are located in the display area AA to achieve a display effect. The first power signal line VDD and the second power signal line VSS are provided on the base substrate 101, and at least a part of them is located in the display area AA. The first power signal line VDD is configured to transmit a first power signal to at least a part of the plurality of sub-pixels SP, and the second power signal line VSS is configured to transmit a second power signal different from the first power signal to at least a part of the plurality of sub-pixels SP.

[0045] For example, in some embodiments, the potential of the first power signal is higher than the potential of the second power signal. That is, the first power signal line VDD transmits a high power voltage, and the second power signal line VSS transmits a low power voltage. For example, in some embodiments, the second power signal bus VSB may be grounded.

[0046] The first power signal bus VDB and the second power signal bus VSB are provided on the base substrate 101 and are located in the peripheral area NA. The first power signal line VDD is electrically connected to the first power signal bus VDB and obtains the first power signal from the first power signal bus VDB. For example, in some embodiments, the first power signal line VDD may extend from the display area AA to the peripheral area NA and be electrically connected to the first power signal bus VDB. The second power signal line VSS is electrically connected to the second power signal bus VSV and obtains the second power signal from the second power signal bus VSB. For example, in some embodiments, the second power signal line VSS may extend from the display area AA to the peripheral area NA and be electrically connected to the second power signal bus VSV.

[0047] For example, as shown in FIGS. 4 and 5, the second power signal bus VSB may at least partially surround the first power signal bus VDB by including a first portion VSB1 provided on the side closer to the display area AA of the first power signal bus VDB (the lower side in the figure) and a second portion VSB2 provided on the side farther from the display area AA of the first power signal bus VDB (the upper side in the figure). Thereby, the second power signal bus VSB at least blocks electromagnetic interference to the first power signal bus VDB on both opposite sides (the upper side and the lower side in the figure), thereby making the signal transmission by the first power signal bus VDB more accurate and enhancing the display effect of the display substrate.

[0048] For example, in some embodiments, as shown in FIG. 6, the display substrate further includes a light-shielding layer SH provided on the base substrate 101. For example, each of a plurality of sub-pixels includes a light-emitting device EM and a pixel driving circuit for driving the light-emitting device, and the pixel driving circuit is provided on the side of the light-shielding layer SH away from the base substrate 101. For example, the pixel driving circuit includes structures such as a thin-film transistor (shown as a driving transistor in FIG. 6) and a storage capacitor. The thin-film transistor includes an active layer Ta provided on the side of the light-shielding layer SH away from the base substrate 101, a gate Tg provided on the side of the active layer Ta away from the base substrate 101, and source-drain electrodes Td and Ts provided on the side of the gate Tg away from the base substrate 101, and the source-drain electrodes Td and Ts are electrically connected to the active layer Ta via vias, respectively.

[0049] For example, in the direction perpendicular to the base substrate 101, that is, in the vertical direction in FIG. 6, the light-shielding layer SH at least partially overlaps with the active layer Ta to achieve a light-shielding effect on the active layer Ta, avoiding external light from irradiating the active layer Ta and adversely affecting the normal operation of the thin-film transistor.

[0050] For example, as shown in FIG. 6, the storage capacitor includes a first capacitive electrode Ca, a second capacitive electrode Cb, and a third capacitive electrode Cc. In a direction perpendicular to the base substrate 101, the first capacitive electrode Ca and the second capacitive electrode Cb overlap each other to form a first capacitor C1, the first capacitive electrode Ca and the third capacitive electrode Cc overlap each other to form a first capacitor C2, and the first capacitor C1 and the first capacitor C2 are connected in parallel, whereby the capacitance of the storage capacitor is increased.

[0051] For example, as shown in FIG. 6, the first capacitive electrode Ca is provided in the same layer as the active layer Ta, the second capacitive electrode Cb is provided in the same layer as the source-drain electrodes Td and Ts, and the third capacitive electrode Cc is provided in the same layer as the light-shielding layer SH. Thereby, the manufacturing process of the display substrate is simplified, and it is avoided that the thickness of the display substrate becomes large due to too many functional layers of the display substrate, which is advantageous for the design of thinning the display substrate.

[0052] In the embodiments of the present disclosure, "provided in the same layer" refers to the same layer in the stacked structure of the display substrate of two or more functional layers or structural layers, and refers to a layer formed of the same material. That is, in the manufacturing process, these two functional layers or structural layers may be formed of the same material layer, and a desired pattern or structure may be formed by the same patterning process, whereby the manufacturing process of the display substrate is simplified.

[0053] For example, in some embodiments, the first power signal bus VDB is provided in the same layer as the light-shielding layer SH. For example, the first portion VSB1 of the second power signal bus VSB is provided in the same layer as the source-drain electrodes Td and Ts. For example, the second portion VSB2 of the second power signal bus VSB is provided in the same layer as the gate Tg, thereby simplifying the manufacturing process of the display substrate, avoiding the display substrate having too many structural layers, and realizing a thinner display substrate. In addition, the first power signal bus VDB, the first portion VSB1, and the second portion VSB2 of the second power signal bus VSB are each made of different metal layers, thereby increasing the distance between the first power signal bus VDB and the second power signal bus VSB, and thus avoiding defects such as short circuits caused by signal lines being too close to each other.

[0054] For example, in some embodiments, as shown in Fig. 4, the second power signal bus VSB further includes a third part VSB3 and a fourth part VSB4 electrically connecting the first part VSB1 and the second part VSB3, and the third part VSB3 and the fourth part VSB4 are located on opposite sides of the first power signal bus VDS, for example, on the left and right sides in Fig. 4, in which case the first part VSB1, the second part VSB, the third part VSB3, and the fourth part VSB4 jointly surround the first power signal bus VDB. For example, as shown in Fig. 4, the first part VSB1, the second part VSB, the third part VSB3, and the fourth part VSB4 completely surround the first power signal bus VDB, thereby fully exerting the effect of preventing signal crosstalk of the first power signal bus VDB.

[0055] For example, in some embodiments, as shown in FIG. 4, the third portion VSB3 and the fourth portion VSB4 may be provided in the same layer as the first portion VSB1 and be integrally connected to the first portion VSB, and the third portion VSB3 and the fourth portion VSB4 are electrically connected to the second portion VSB2 through vias, whereby the first portion VSB1, the second portion VSB, the third portion VSB3, and the fourth portion VSB4 of the second power supply signal bus VSB are integrally formed and transmit the same low power supply signal, and can also reduce the voltage drop of the second power supply signal bus VSB.

[0056] For example, in some embodiments, as shown in FIG. 4, the third partial VSB3 and the fourth partial VSB4 are structurally symmetric, that is, they have the same shape, size, layout, etc., thereby making the signal transmission characteristics on the left and right sides of the display substrate substantially the same and improving the display uniformity of the display substrate.

[0057] For example, in some embodiments, as shown in FIG. 5, the display substrate further includes a first power connection line DL, and the first power connection line DL is provided on the same layer as the first power signal bus VDB, that is, it may be provided on the same layer as the light-shielding layer SH. The first power connection line DL electrically connects the first power signal bus VDB and the first power signal line VDD.

[0058] For example, in some embodiments, the first power connection line DL may be provided on the same layer as the first power signal bus VDB and integrally connected.

[0059] For example, as shown in FIG. 5, in some embodiments, the first power signal line VDD is provided on the same layer as the source-drain electrodes Td and Ts and may be electrically connected to the first power connection line DL via the adapter via V. For example, in some embodiments, the second power signal line VSS is provided on the same layer as the source-drain electrodes Td and Ts and is integrally connected to the first portion VSB1 of the second power signal bus VSB.

[0060] For example, as shown in FIG. 5, the second power signal line VSS extends from the display area AA to the peripheral area NA and is electrically connected to the first portion VSB1 of the second power signal bus VSB, for example, integrally connected.

[0061] For example, in some embodiments, as shown in FIG. 5, in a direction perpendicular to the base substrate 101, a first portion VSB1 of the second power signal bus VSB at least partially overlaps with the first power connection line DL, and the first portion VSB1 includes a first cutout portion H1 that overlaps with the first power connection line DL in a direction perpendicular to the base substrate 101. Thereby, the area of the first power connection line DL that overlaps with the first portion VSB1 can be reduced, and it is possible to avoid the first power connection line DL and the first portion VSB1 forming a structure such as a parasitic capacitor and adversely affecting the normal transmission of electrical signals.

[0062] For example, in some embodiments, as shown in FIG. 5, the first portion VSB1 of the second power signal bus VSB further includes a second cutout portion H2 that does not overlap with the first power connection line DL in a direction perpendicular to the base substrate 101. By providing the second cutout portion H2, the transparency of the region can be improved, the difference in etching of different regions of the first portion VSB1 provided over a large area can be reduced, and the etching uniformity of the first portion VSB1 provided over a large area can be improved.

[0063] For example, in some embodiments, as shown in FIGS. 4 and 5, in a direction perpendicular to the base substrate 101, at least one of the third portion VSB3 and the fourth portion VSB4 of the second power signal bus VSB (for example, both the third portion VSB3 and the fourth portion VSB4) at least partially overlaps with the first power connection line DL, and at least one of the third portion VSB3 and the fourth portion VSB4 (for example, both the third portion VSB3 and the fourth portion VSB4) includes a third cutout portion H3 that overlaps with the first power connection line DL in a direction perpendicular to the base substrate 101. Thereby, the overlapping area of the first power connection line DL with the third portion VSB3 and the fourth portion VSB4 can be reduced.

[0064] For example, in other embodiments, the third VSB portion VSB3 and the fourth VSB portion VSB4 may further include a cutout portion (not shown) that overlaps the first power connection line DL in a direction perpendicular to the base substrate 101, thereby improving the etching uniformity of the third VSB portion VSB3 and the fourth VSB portion VSB4.

[0065] For example, in some embodiments, as shown in FIG. 5, the first power connection line DL may include a first wiring portion DL1 extending along a first direction (the vertical direction in the figure) and a second wiring portion DL2 extending along a second direction (the horizontal direction in the figure), where the first direction is different from the second direction. For example, the first direction is perpendicular to the second direction. For example, referring to FIGS. 4 and 5, the first wiring portion DL1 includes a plurality of first wirings, and the plurality of first wirings are parallel to each other. The second wiring portion DL2 includes two second wirings arranged opposite to each other, and the two second wirings are provided on the same straight line. For example, a part of the first wiring is directly connected to the first power signal bus VDB, and another part is connected to the second wiring and electrically connected to the first power signal bus VDB through the second wiring.

[0066] For example, in a direction perpendicular to the base substrate 101, the first wiring portion DL1 at least partially overlaps the first portion VSB1 of the second power signal bus VSB and overlaps the first cutout portion H1, and the second wiring portion DL2 overlaps at least one of (for example, both) the third VSB portion VSB3 and the fourth VSB portion VSB4 of the second power signal bus VSB and overlaps the third cutout portion H3.

[0067] For example, in some embodiments, as shown in FIG. 6, the display substrate further includes a planarization layer PLN and a first electrode layer. The planarization layer PLN is provided on the side of the base substrate 101 away from the source-drain electrodes Td and Ts, thereby planarizing the pixel driving circuit, providing a flat surface, and facilitating the provision of the first electrode layer. Referring to FIGS. 4 and 6, the planarization layer PLN is provided in the peripheral region NA and includes a first via V1 that exposes a first portion VSB1 of the second power signal bus VSB, and a second via V2 that is provided in the display region AA and exposes the source-drain electrode Ts.

[0068] For example, as shown in FIG. 6, the first electrode layer is provided on the side of the planarization layer PLN away from the base substrate 101. Referring to FIGS. 5 and 6, the first electrode layer includes a first electrode E1 provided in the display region AA and a connection electrode EL provided in the peripheral region NA. The first electrode E1 is electrically connected to the source-drain electrode Ts via the second via V2, and the connection electrode EL is electrically connected to the first portion VSB1 of the second power signal bus VSB via the first via V1. For example, the first electrode E1 may function as the anode of the light-emitting device EM.

[0069] For example, in some embodiments, as shown in FIG. 6, the display substrate further includes a pixel definition layer PDL provided on the side of the first electrode layer away from the base substrate 101. Referring to FIGS. 5 and 6, the pixel definition layer PDL includes a connection opening PDL1 provided in the peripheral region NA and a sub-pixel opening PDL2 provided in the display region AA. The connection opening PDL1 exposes the connection electrode EL, and the sub-pixel opening PDL2 exposes the first electrode E1, thereby defining the effective light-emitting region of the light-emitting device EM.

[0070] For example, in some embodiments, as shown in FIG. 6, the display substrate further includes a light-emitting material layer E2 and a second electrode layer E3. At least a part of the light-emitting material layer E2 is provided in the sub-pixel opening PDL2, and thereby is driven by the first electrode E1 exposed through the sub-pixel opening PDL2 to emit light. The second electrode layer E3 is provided on the side away from the base substrate 101 of the light-emitting material layer E2. For example, the second electrode layer E3 may function as the cathode of the light-emitting device EM. For example, in some embodiments, the second electrode layer E3 is an electrode layer formed as a complete surface, that is, it is continuously provided in a sheet shape on the base substrate, and extends from the display area AA to the peripheral area NA. Further, it may be electrically connected to the connection electrode EL through the connection opening PLN1, whereby the second electrode layer E3 may be electrically connected to the first part VSB1 of the second power signal bus VSB and receive a low power signal.

[0071] For example, in some embodiments, as shown in FIG. 5, the second electrode layer E3 ends on the side close to the display area AA of the first power signal bus VDS. For example, the end boundary line of the second electrode layer E3 is E3D, whereby the second electrode layer E3 is spaced apart from the first power signal bus VDB, that is, the boundary line is E3D and is spaced apart from the first power signal bus VDB. For example, the spacing is greater than 1.0 μm, for example, 1.20 μm, 1.30 μm, 1.35 μm, 1.40 μm, 1.45 μm, or 1.50 μm, etc. Thereby, the risk of short circuit between the second electrode layer E3 and the first power signal bus VDB can be reduced, and the production yield of the display substrate can be increased.

[0072] For example, in some embodiments, the display substrate may further include structures such as a stop layer and a buffer layer (not shown) provided on the base substrate 101 so that impurities do not penetrate into each functional layer on the base substrate 101 from the base substrate 101. For example, as shown in FIG. 6, the display substrate may further include structures such as an insulating layer 102 provided on the light-shielding layer SH, a gate insulating layer GI provided on the active layer Ta, an interlayer insulating layer IDL provided on the gate Tg, a passivation layer PVX provided on the source-drain electrodes Td and Ts, and a sealing layer (not shown) provided on the second electrode layer.

[0073] For example, the passivation layer PVX includes a via PVX1 communicating with the second via V2 of the planarization layer PLN, whereby the first electrode E1 is electrically connected to the source-drain electrode Ts through the second via V2 and the via PVX1. For example, the passivation layer PVX may further include a via PVX2 (see FIG. 11A, described below) communicating with the first via V1, whereby the connection electrode EL is electrically connected to the first portion VSB1 of the second power signal bus VSB through the first via V1 and the via PVX2.

[0074] For example, in order to obtain an excellent sealing effect, the sealing layer may be a composite sealing layer in which a plurality of inorganic sealing layers and organic sealing layers are laminated, for example, a three-layer laminated structure of an inorganic sealing layer / organic sealing layer / inorganic sealing layer. For example, the display substrate may further include a structure such as a cover (for example, a glass transparent cover) provided on the sealing layer. In the embodiments of the present disclosure, other structures on the display substrate are not particularly limited.

[0075] For example, in the embodiments of the present disclosure, as the base substrate 101, a rigid substrate made of glass, quartz, etc., or a flexible substrate made of polyimide (PI), etc. may be used. The materials of the active layer Ta and the first capacitive electrode Ca include, but are not limited to, silicon-based materials (such as amorphous silicon a-Si, polysilicon p-Si, etc.), metal oxide semiconductors (such as IGZO, ZnO, AZO, IZTO, etc.), and organic materials (such as hexathiophene, polythiophene, etc.). During manufacturing, the semiconductor material of the first capacitive electrode Ca is made conductive to obtain good conductivity. The light-shielding layer SH, the third capacitive electrode Cc, and the first power signal bus VDD may use metal materials such as copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), titanium (Ti), tungsten (W), etc., or alloy materials. For example, the gate Tg and the second part VSB2 of the second power signal bus VSB may use metal materials such as copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), titanium (Ti), tungsten (W), etc., or alloy materials. For example, the gate Tg and the second part VSB2 of the second power signal bus VSB may have a single-layer structure or a multilayer structure, such as a laminated structure of a molybdenum-titanium alloy and copper, etc. For example, the source-drain electrodes Td and Ts, the second capacitive electrode Cb, and the first part VSB1, the third part VSB3, and the fourth part VSB4 of the second power signal bus VSB may use metal materials such as copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), titanium (Ti), tungsten (W), etc., or alloy materials, and may be formed, for example, as a single-layer or multilayer structure, such as a laminated structure of a molybdenum-titanium alloy and copper, etc.

[0076] For example, the insulating layer 102, the gate insulating layer GI, the interlayer insulating layer IDL, the passivation layer PVX, and the inorganic encapsulation layer may be made of an inorganic insulating material such as an inorganic insulating layer, for example, silicon oxide (SiOx), silicon nitride (SiNy), or silicon oxynitride (SiOxNy). For example, the planarization layer PLN, the pixel definition layer PDL, and the organic encapsulation layer may be made of an organic insulating material such as an organic insulating layer, for example, polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), etc.

[0077] For example, the first electrode E1 and the connection electrode EL may use a material having a high work function, such as a transparent metal oxide, for example, ITO, IZO, etc. For example, the first electrode E1 may also include a metal layer such as Ag, thereby forming a multilayer structure of a transparent metal oxide / metal layer. For example, the light-emitting material layer E2 may include an organic light-emitting material, whereby the light-emitting device EM becomes an organic light-emitting device (OLED). Alternatively, in some other embodiments, the light-emitting material layer E2 may include a quantum dot light-emitting material, whereby the light-emitting device EM becomes a quantum dot device (QLED). For example, the second electrode layer E3 may include a metal material or an alloy material such as magnesium (Mg), lithium (Li), aluminum (Al), silver (Ag), etc. In the embodiments of the present disclosure, the materials of each functional layer are not limited.

[0078] For example, FIGS. 7 to 13B show partial plan schematic views of some functional layers of the display substrate and partial plan schematic views of the sequentially stacked functional layers. Hereinafter, taking the structure shown in FIGS. 7 to 13B as an example, each functional layer of the display substrate and their positional relationships will be described.

[0079] For example, FIG. 7 shows a partial plan schematic view of the first conductive layer where the light-shielding layer SH exists. As shown in FIG. 7, the first conductive layer includes structures such as the light-shielding layer SH, the first power signal bus VDB, and the first power signal connection line DL.

[0080] For example, during manufacturing, the material of the first conductive layer is applied onto the base substrate 101 by a sputtering process, and the material of the first conductive layer is patterned by a photolithography process to obtain patterns of structures such as the light-shielding layer SH, the first power signal bus VDB, and the first power signal connection line DL.

[0081] For example, the photolithography process may include processes such as photoresist coating, exposure, development, and etching. Specifically, since related technologies can be referred to, it will not be described in detail here.

[0082] For example, referring to FIG. 6, an insulating layer 102 may be formed on the first conductive layer. During manufacturing, the material of the insulating layer 102 may be formed by a deposition process. The material of the insulating layer 102 may include one or more of SiNx, SiOx, or SiOxNy, and its thickness may include 150 nm to 500 nm, for example, 200 nm, 300 nm, or 400 nm, etc.

[0083] For example, during manufacturing, an amorphous oxide such as IGZO, ZnON, or ITZO is formed on the insulating layer 102 by a sputtering process to form a semiconductor material layer, and the semiconductor material layer is patterned by a photolithography process to form patterns of the active layer Ta and the first capacitive electrode Ca. For example, in order to obtain good conductivity, later, the pattern of the first capacitive electrode Ca and a part of the pattern of the active layer Ta may be made conductive, for example, by doping treatment.

[0084] For example, during manufacturing, the material of the gate insulating layer GI may be provided by a deposition process, and then the material of the second conductive layer may be provided on the material of the gate insulating layer GI by a sputtering process. The deposition thickness of the material of the second conductive layer may be 200 nm to 1000 nm, for example, 400 nm, 600 nm, or 800 nm, etc. As shown in FIG. 8A, the gate Tg and the second portion VSB2 of the second power signal bus VSB may be further formed by a photolithography process. For example, the photoresist pattern used in the above photolithography process may function as a mask without being peeled off. The material of the gate insulating layer GI is etched by a dry etching process to form a pattern of the gate insulating layer GI, and the semiconductor material layer exposed on the outer surface is made conductive by using a gas such as NH 3 , N 2 or H 2 etc., so as to impart good conductivity to the processed semiconductor material layer.

[0085] For example, FIG. 8B shows a partial plan schematic view of a stack of the second conductive layer and the first conductive layer. As shown in FIG. 8B, the second portion VSB2 of the second power signal bus VSB is located on the side away from the display area AA of the first power signal bus VDB.

[0086] For example, FIG. 9A shows a partial plan schematic view of the interlayer insulating layer IDL. As shown in FIG. 9, the interlayer insulating layer IDL further includes a via VS1 for electrically connecting the third portion VSB3 (and the fourth portion VSB4) of the second power signal bus VSB and the second portion VSB2, and a via VS2 for electrically connecting the source-drain electrodes Ts / Td and the active layer Ta.

[0087] For example, during manufacturing, the material of the interlayer insulating layer IDL may be deposited on the second conductive layer by a deposition process, and the vias VS1 and VS2 may be obtained by a dry etching process. For example, the material of the interlayer insulating layer IDL may be a single-layer or multi-layer structure formed of SiNx or SiOx.

[0088] For example, FIG. 9B shows a partial plan schematic view of a structure in which an interlayer insulating layer IDL, a second conductive layer, and a first conductive layer are stacked. As shown in FIG. 9B, via V S1 exposes the second portion V SB2 of the second power signal bus V SB, and via V S2 exposes the active layer Ta.

[0089] For example, during manufacturing, the material of the third conductive layer may be applied onto the interlayer insulating layer IDL by a sputtering process, and the deposition thickness of the material of the third conductive layer may be 200 nm to 1000 nm. As shown in FIG. 10A, further, by a photolithography process, source-drain electrodes T s / T d, a first power signal line V DD, a second power signal line V SS, a first portion V SB1, a third portion V SB3 (and a fourth portion V SB4) of the second power signal bus V SB may be formed. For example, the first portion V SB1 has a first cutout portion H1 and a second cutout portion H2, and the third portion V SB3 (and the fourth portion V SB4) has a third cutout portion H3.

[0090] For example, FIG. 10B shows a partial plan schematic view of a structure in which the third conductive layer, the interlayer insulating layer IDL, the second conductive layer, and the first conductive layer are stacked. As shown in FIG. 10B, the third portion V SB3 (and the fourth portion V SB4) of the second power signal bus V SB is electrically connected to the second portion V SB2 via via V S1, and the source-drain electrodes T s / T d are electrically connected to the active layer Ta via via V S2. Although not specifically shown in the figure, reference may be made to FIG. 6.

[0091] For example, FIG. 11A shows a partial plan schematic view of a passivation layer PVX and a planarization layer PLN. During manufacturing, the material of the passivation layer PVX, for example, SiO 2 is applied onto the third conductive layer by a deposition process, and a pattern of the passivation layer PVX may be further formed by a photolithography process. The passivation layer PVX includes via PVX1 located in the display area AA and exposing the source-drain electrode T s, and via PXV2 located in the peripheral area NA and exposing the first portion V SB1.

[0092] For example, a material of the planarization layer PLN, such as polyimide, is applied to the passivation layer PVX by coating, and post-baked at 230 °C to remove water and organic solvents in the material, thereby forming a planarization layer PLN with a thickness of about 2.0 μm to 3.5 μm. Then, through exposure and development, a first via V1 located in the peripheral region NA and communicating with the via PXV2, and a second via V2 located in the display region AA and communicating with the via PVX1 are formed.

[0093] For example, FIG. 11B shows a partial plan schematic view of a stack of the passivation layer PVX, the planarization layer PLN, the third conductive layer, the interlayer insulating layer IDL, the second conductive layer, and the first conductive layer. As shown in FIG. 11B, in the peripheral region NA, the first via V1 and the via PXV2 expose a first portion VSB1. In the display region AA, the second via V2 and the via PVX1 expose the source-drain electrode Ts, which is not shown in FIG. 11B and reference is made to FIG. 6.

[0094] For example, FIG. 12A shows a partial plan schematic view of a first electrode layer. As shown in FIG. 12A, the first electrode layer includes a first electrode E1 located in the display region AA and a connection electrode EL located in the peripheral region NA. During manufacturing, the material of the first electrode layer is applied onto the planarization layer PLN by a sputtering process, and the thickness of the material may be about 100 nm - 600 nm, such as 200 nm, 300 nm, 400 nm, or 500 nm, etc. Further, a photolithography process may be used to obtain the patterns of the first electrode E1 and the connection electrode EL.

[0095] For example, FIG. 12B shows a partial plan schematic view of a stack of the first electrode layer, the passivation layer PVX, the planarization layer PLN, the third conductive layer, the interlayer insulating layer IDL, the second conductive layer, and the first conductive layer. As shown in FIG. 12B, the connection electrode EL is electrically connected to the first portion VSB1 through vias in the peripheral region NA of the passivation layer PVX and the planarization layer PLN. The first electrode E1 is electrically connected to the source-drain electrode Ts through vias in the display region AA of the passivation layer PVX and the planarization layer PLN, which is not specifically shown in FIG. 12B and reference can be made to FIG. 6.

[0096] For example, FIG. 13A shows a partial plan view of the pixel definition layer PLN, and the shaded portion in the figure is the portion where the material of the pixel definition layer PLN has been removed. For example, as shown in FIG. 6, the pixel definition layer PLN includes a sub-pixel opening region PDL3, the sub-pixel opening region PDL3 includes sub-pixel openings PDL2 for a plurality of sub-pixels, and the sub-pixel openings PDL2 expose the first electrode E1. The pixel definition layer PLN further includes a connection opening PDL1, and the connection opening PDL1 exposes the connection electrode EL so that the second electrode layer E2 to be formed later is electrically connected to the connection electrode EL through the connection opening PDL1 and further electrically connected to the first portion VSB1 of the second power signal bus VSB.

[0097] For example, during manufacturing, the material of the pixel definition layer PLN is applied by a coating process, and patterns of the pixel definition layer PLN such as the connection opening PDL1 and the sub-pixel opening PDL2 are formed by pre-baking, exposure, development, etc. Then, post-baking is performed at 230° C. to remove water and organic solvents in the pixel definition layer PLN, and finally, a pixel definition layer PLN with a thickness of 1.8 μm to 2.0 μm may be formed.

[0098] For example, FIG. 13B shows a partial plan view of a stack of the pixel definition layer PLN, the first electrode layer, the passivation layer PVX, the planarization layer PLN, the third conductive layer, the interlayer insulation layer IDL, the second conductive layer, and the first conductive layer. As shown in FIG. 13B, the connection opening PDL1 exposes the connection electrode EL so that the second electrode layer E2 to be formed later is electrically connected to the connection electrode EL through the connection opening PDL1.

[0099] For example, the display substrate further has structures such as a light-emitting material layer E2 (formed by, for example, inkjet printing), a second electrode layer E3 (formed by, for example, sputtering), and a sealing layer. The formation methods and specific structures of these may refer to related technologies and the description of FIG. 6, etc., but will not be described in detail here.

[0100] In an embodiment of the present disclosure, both the second power signal line VSS and the first power signal line VDD in the display area AA are provided in the same layer as the source-drain electrodes Ts and Td, and the first power signal line VDD is connected to the first power signal bus VDB via a via. The first power signal bus VDB is provided in the same layer as the light-shielding layer SH, and each part of the second power signal bus VSB is provided in the same layer as the gate Tg, the source electrode, and the drain electrodes Ts / Td, respectively, thereby increasing the distance between the high and low power signal lines, and also, the first power signal bus VDB is separated from the second electrode layer E3. In this way, a short circuit between the first power signal bus VDB and the second electrode layer E3 is avoided, and the yield of the display substrate is improved. Each part of the second power signal bus VSB is provided on the side close to the display area AA and the side away from the display area AA, respectively, and at least partially surrounds the first power signal bus VDB, thereby being able to perform an electromagnetic shielding action on the first power signal bus VDB. The second electrode layer E3 is electrically connected to the second power signal bus VSB by using a connection electrode EL provided in the same layer as the first electrode E1 through a connection opening of the pixel definition layer PDL, which is advantageous for the butt joint between the second electrode layer E3 and the second power signal bus VSB. Also, a trench is designed at the overlapping part between the first power connection line DL electrically connected to the first power signal bus VDB and the second power signal bus VSB, that is, the second power signal bus VSB has a first cutout part and a third cutout part. In this way, the formation of parasitic capacitance can be avoided. The second power signal bus VSB provided in a large area further has a second cutout part, thereby enlarging the transparent area and reducing the difference in etching, and thus ensuring the yield of the display substrate and enhancing the display effect.

[0101] As described above, the display substrate according to the embodiment of the present disclosure has a good display effect and a high manufacturing yield while realizing a narrow bezel and a large screen.

[0102] The following points need to be explained. (1) The drawings of the embodiments of the present disclosure only include the structures related to the embodiments of the present disclosure, and other structures can refer to the common design. (2) For clarity, in the drawings used to illustrate the embodiments of the present disclosure, the thickness of layers or regions is enlarged or reduced. That is, these drawings are not drawn to actual scale. When an element such as a layer, film, region, or substrate is described as being "on" or "under" another element, it is understood that the element may be directly located "on" or "under" the other element, or there may be intermediate elements. (3) The features of the same and different embodiments of the present disclosure can be combined with each other without conflict. The above description is only an exemplary embodiment of the present disclosure and is not used to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Description of Reference Numerals

[0103] 101 Base Substrate AA Display Region NA Peripheral Region SP Sub-Pixel VDD First Power Signal Line VSS Second Power Signal Line VDB First Power Signal Bus VSB Second Power Signal Bus VSB1 First Portion VSB2 Second Portion

Claims

1. A display substrate, comprising: a display area and a peripheral area at least partially surrounding the display area, and a base substrate, a plurality of sub-pixels provided on the base substrate and located in the display area, a first power signal line and a second power signal line provided on the base substrate and at least partially located in the display area, wherein the first power signal line is configured to transmit a first power signal to at least a part of the plurality of sub-pixels, and the second power signal line is configured to transmit a second power signal different from the first power signal to at least a part of the plurality of sub-pixels, the first power signal line and the second power signal line, a first power signal bus and a second power signal bus provided on the base substrate and located in the peripheral area, wherein the first power signal line is electrically connected to the first power signal bus, and the second power signal line is electrically connected to the second power signal bus, the first power signal bus and the second power signal bus, The second power signal bus includes a first portion provided on a side of the first power signal bus close to the display area and a second portion provided on a side of the first power signal bus away from the display area, thereby at least partially surrounding the first power signal bus, the display substrate.

2. Further comprising a light-shielding layer provided on the base substrate, each of the plurality of sub-pixels includes a light-emitting device and a pixel driving circuit for driving the light-emitting device, and the pixel driving circuit is provided on a side of the light-shielding layer away from the base substrate, The first power signal bus is provided in the same layer as the light-shielding layer, the display substrate according to claim 1.

3. The pixel driving circuit includes a thin-film transistor, and the thin-film transistor includes a gate provided on a side of the light-shielding layer away from the base substrate and a source-drain electrode provided on a side of the gate away from the base substrate, The first portion is provided in the same layer as the source-drain electrode, the display substrate according to claim 2.

4. The second portion is provided in the same layer as the gate, the display substrate according to claim 3.

5. The second power signal bus further includes a third portion and a fourth portion for electrically connecting the first portion and the second portion, and the third portion and the fourth portion are located on opposite sides of the first power signal bus. The display substrate according to any one of claims 1 to 4, wherein the first part, the second part, the third part, and the fourth part jointly surround the first power signal bus.

6. The display substrate according to claim 5, wherein the third part and the fourth part are provided on the same layer as the first part and are integrally connected to the first part.

7. The display substrate according to claim 5 or 6, wherein the structures of the third part and the fourth part are symmetric.

8. The display substrate according to claim 3, further comprising a first power connection line provided on the same layer as the first power signal bus and electrically connecting the first power signal bus and the first power signal line.

9. The display substrate according to claim 8, wherein the first power signal line is provided on the same layer as the source-drain electrode and is electrically connected to the first power connection line via an adapter via.

10. The display substrate according to claim 3, wherein the second power signal line is provided on the same layer as the source-drain electrode.

11. The display substrate according to claim 10, wherein the second power signal line extends from the display area to the peripheral area and is electrically connected to the first part.

12. The display substrate according to any one of claims 1 to 11, wherein the potential of the first power signal is higher than the potential of the second power signal.

13. A planarization layer including a first via provided on a side of the source-drain electrode away from the base substrate, provided in the peripheral area, exposing the first part, and a second via provided in the display area, exposing the source-drain electrode; A first electrode layer provided on a side of the planarization layer away from the base substrate, including a first electrode provided in the display area and a connection electrode provided in the peripheral area, wherein the first electrode is electrically connected to the source-drain electrode via the second via, and the connection electrode is electrically connected to the first part via the first via, further comprising the display substrate according to claim 3 or 4.

14. A pixel definition layer provided on a side of the first electrode layer away from the base substrate, including a connection opening provided in the peripheral area and a sub-pixel opening provided in the display area, wherein the connection opening exposes the connection electrode, and the sub-pixel exposes the first electrode, further comprising the display substrate according to claim 13.

15. A light-emitting material layer at least partially provided in the sub-pixel opening; A second electrode layer provided on a side of the light-emitting material layer away from the base substrate, extending from the display region to the peripheral region, and electrically connected to the connection electrode through the connection opening. The display substrate according to claim 14 further includes the second electrode layer.

16. The second electrode layer ends at a side of the first power signal bus close to the display region and is spaced apart from the first power signal bus. The display substrate according to claim 15.

17. In a direction perpendicular to the base substrate, the first portion at least partially overlaps the first power connection line, and the first portion includes a first cutout portion that overlaps the first power connection line in a direction perpendicular to the base substrate. The display substrate according to claim 8 or 9.

18. The first portion includes a second cutout portion that does not overlap the first power connection line in a direction perpendicular to the base substrate. The display substrate according to claim 17.

19. In a direction perpendicular to the base substrate, at least one of the third portion and the fourth portion at least partially overlaps the first power connection line, and at least one of the third portion and the fourth portion includes a third cutout portion that overlaps the first power connection line in a direction perpendicular to the base substrate. The display substrate according to claim 17 or 18.

20. The first power connection line includes a first wiring portion extending along a first direction and a second wiring portion extending along a second direction, and the first direction is different from the second direction. In a direction perpendicular to the base substrate, the first wiring portion at least partially overlaps the first portion and partially overlaps the first cutout, the second wiring portion overlaps at least one of the third portion and the fourth portion, and partially overlaps the third cutout. The display substrate according to claim 19.

Images