PIXEL CIRCUIT, DISPLAY PANEL, DRIVING METHOD AND DISPLAY DEVICE

Abstract

The present disclosure provides a pixel circuit, a display panel, a driving method and a display device. The pixel circuit includes a light emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit and a writing control circuit, a first end of the first energy storage circuit is electrically connected to a control end of the driving circuit and a first end of the writing control circuit respectively, a second end of the first energy storage circuit is electrically connected to the first end of the driving circuit, a first end of the second energy storage circuit is electrically connected to the second end of the writing control circuit, and a second end of the second energy storage circuit is electrically connected to the writing end, the writing control circuit controls the first end of the first energy storage circuit and the first end of the second energy storage circuit to be connected or disconnected under the control of a first writing control signal, and the driving circuit generates a driving current for driving the light emitting element under the control of the potential of its control end. The present disclosure can provide a current type pixel circuit capable of self-compensating threshold voltage, which is applied to an organic light emitting diode display.

Description

[Technical field]

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit, a display panel, a driving method and a display device. [Background technology]

[0002] OLED (Organic Light Emitting Diode) display has become one of the hotspots in the current flat panel display research field, and pixel circuit design is the core technical content of OLED display. In the related art, it has been impossible to provide a current-type pixel circuit that can self-compensate the threshold voltage as a current-type pixel circuit applied to OLED display. Summary of the Invention

[0003] In a first aspect, an embodiment of the present disclosure provides a pixel circuit including a light emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, and a write control circuit, A first end of the first energy storage circuit is electrically connected to the control end of the driving circuit and the first end of the writing control circuit respectively, a second end of the first energy storage circuit is electrically connected to the first end of the driving circuit, a first end of the second energy storage circuit is electrically connected to the second end of the writing control circuit, and a second end of the second energy storage circuit is electrically connected to the writing end, the first energy storage circuit and the second energy storage circuit are used for storing electric energy; A control end of the write control circuit is electrically connected to a first write control end, and the write control circuit is used to control the first end of the first energy storage circuit and the first end of the second energy storage circuit to communicate or be cut off under the control of a first write control signal provided by the first write control end; A second end of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is used to generate a driving current for driving the light-emitting element under the control of the potential of its control end, providing a pixel circuit.

[0004] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a first control circuit; The first control circuit is electrically connected to a first control end, a first end of the second energy storage circuit, and a second end of the second energy storage circuit, respectively, and is used to control the communication between the first end of the second energy storage circuit and the second end of the second energy storage circuit to be established or cut off under the control of a first control signal provided by the first control end.

[0005] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a second control circuit; The second control circuit is electrically connected to a second control end, a power supply voltage end and a first end of the driving circuit, respectively, and is used to control communication or disconnection between the power supply voltage end and the first end of the driving circuit under the control of a second control signal supplied by the second control end.

[0006] Optionally, the second end of the driving circuit is electrically connected to the first pole of the light-emitting element, and the second pole of the light-emitting element is electrically connected to a first voltage end; The power supply voltage terminal is used to supply a power supply voltage, and the first voltage terminal is used to supply a first voltage signal; The absolute value of the voltage value of the power supply voltage is smaller than the absolute value of the voltage value of the first voltage signal.

[0007] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a third control circuit, and the second end of the driving circuit is electrically connected to the first pole of the light-emitting element, and the second pole of the light-emitting element is electrically connected to a first voltage end; The third control circuit is electrically connected to a third control terminal, a third voltage terminal and a first pole of the light-emitting element, respectively, and is used to control, under the control of a third control signal supplied by the third control terminal, the third voltage signal supplied by the third voltage terminal to be written to the first pole of the light-emitting element.

[0008] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a reference voltage writing circuit; the reference voltage write circuit is electrically connected to a second write control end, a reference voltage end and a write node respectively, and is used to write the reference voltage provided by the reference voltage end to the write node under the control of a second write control signal provided by the second write control end; The write node is electrically connected to a control end of the driving circuit, or the write node is electrically connected to a first end of the second energy storage circuit.

[0009] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a resistor circuit; A first end of the resistor circuit is electrically connected to a second end of the driving circuit, and the second end of the resistor circuit is electrically connected to a first electrode of the light-emitting element; The second pole of the light emitting device is electrically connected to a first voltage terminal.

[0010] Optionally, the first energy storage circuit includes a first capacitance and the second energy storage circuit includes a second capacitance; A first end of the first capacitance is electrically connected to a control end of the driving circuit and a first end of the write control circuit respectively, a second end of the first capacitance is electrically connected to the first end of the driving circuit, a first end of the second capacitance is electrically connected to the second end of the write control circuit, and a second end of the second capacitance is electrically connected to a write end; The capacitance value of the second capacitance is smaller than the capacitance value of the first capacitance.

[0011] Optionally, the write control circuitry includes a first transistor; A control pole of the first transistor is electrically connected to the first write control terminal, a first pole of the first transistor is electrically connected to a control terminal of the driving circuit, a second pole of the first transistor is electrically connected to a first terminal of the second energy storage circuit, and a back gate of the first transistor is electrically connected to a second voltage terminal.

[0012] Optionally, the first control circuit includes a second transistor; A control pole of the second transistor is electrically connected to the first control end, a first pole of the second transistor is electrically connected to a first end of the second energy storage circuit, a second pole of the second transistor is electrically connected to a second end of the second energy storage circuit, and a back gate of the second transistor is electrically connected to a second voltage end.

[0013] Optionally, the reference voltage writing circuit includes a third transistor; A control pole of the third transistor is electrically connected to the second write control terminal, a first pole of the third transistor is electrically connected to the reference voltage terminal, a second pole of the third transistor is electrically connected to the write node, and a back gate of the third transistor is electrically connected to a second voltage terminal.

[0014] Optionally, the second control circuit includes a fourth transistor and the drive circuit includes a drive transistor; a control electrode of the fourth transistor is electrically connected to the second control end, a first electrode of the fourth transistor is electrically connected to the power supply voltage end, a second electrode of the fourth transistor is electrically connected to the first end of the driving circuit, and a back gate of the fourth transistor is electrically connected to a second voltage end; The control pole of the driving transistor is the control end of the driving circuit, the first pole of the driving transistor is the first end of the driving circuit, the second pole of the driving transistor is the second end of the driving circuit, and the back gate of the driving transistor is electrically connected to a second voltage end.

[0015] Optionally, the third control circuit includes a fifth transistor; A control electrode of the fifth transistor is electrically connected to the third control terminal, a first electrode of the fifth transistor is electrically connected to the third voltage terminal, a second electrode of the fifth transistor is electrically connected to a first electrode of the light-emitting element, and a back gate of the fifth transistor is electrically connected to a fourth voltage terminal.

[0016] Optionally, the fifth transistor is an n-type transistor, and the fourth voltage end is a third voltage end; A deep n-well is provided between the back gate and the P-type base of the fifth transistor so as to isolate the back gate and the P-type base of the fifth transistor, and the back gate of the fifth transistor and a first electrode of the fifth transistor are both electrically connected to the third voltage terminal.

[0017] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes an n-well and a p-well; the doping concentration of the n-well is greater than the doping concentration of the deep n-well; the ratio of the thickness of the n-well to the thickness of the deep n-well is 0.4 to 0.6, The ratio of the thickness of the p-well to the thickness of the deep n-well is 0.4 to 0.6.

[0018] In a second aspect, an embodiment of the present disclosure provides a pixel circuit including a light emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, and a first control circuit, A first end of the first energy storage circuit is electrically connected to a control end of the driving circuit, a second end of the first energy storage circuit is electrically connected to a first end of the driving circuit, a first end of the second energy storage circuit is electrically connected to a control end of the driving circuit, and a second end of the second energy storage circuit is electrically connected to a writing end, and the first energy storage circuit and the second energy storage circuit are used to store electrical energy; The first control circuit and the second energy storage circuit are connected in parallel with each other, and the first control circuit is used to control the first end of the second energy storage circuit and the second end of the second energy storage circuit to communicate with each other or to be cut off under the control of a first control signal provided by a first control end; The second end of the driving circuit is electrically connected to the light-emitting element, and the driving circuit further provides a pixel circuit, which is used to generate a driving current for driving the light-emitting element under the control of the potential of its control end.

[0019] Optionally, a control end of the first control circuit is electrically connected to the first control end, a first end of the first control circuit is electrically connected to a first end of the second energy storage circuit, and a second end of the first control circuit is electrically connected to a second end of the second energy storage circuit.

[0020] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a write control circuit, the write control circuit being disposed between the first energy storage circuit and the second energy storage circuit; The control end of the write control circuit is electrically connected to a first write control end, the first end of the write control circuit is electrically connected to a first end of the first energy storage circuit, and the second end of the write control circuit is electrically connected to a first end of the second energy storage circuit, and the write control circuit is used to control the first end of the first energy storage circuit and the first end of the second energy storage circuit to be communicated or cut off under the control of a first write control signal provided by the first write control end.

[0021] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a second control circuit; The second control circuit is electrically connected to a second control end, a power supply voltage end and a first end of the driving circuit, respectively, and is used to control communication or disconnection between the power supply voltage end and the first end of the driving circuit under the control of a second control signal supplied by the second control end.

[0022] Optionally, the second end of the driving circuit is electrically connected to the first pole of the light-emitting element, and the second pole of the light-emitting element is electrically connected to a first voltage end; The power supply voltage terminal is used to supply a power supply voltage, and the first voltage terminal is used to supply a first voltage signal; The absolute value of the voltage value of the power supply voltage is smaller than the absolute value of the voltage value of the first voltage signal.

[0023] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a third control circuit, and the second end of the driving circuit is electrically connected to the first pole of the light-emitting element, and the second pole of the light-emitting element is electrically connected to a first voltage end; The third control circuit is electrically connected to a third control terminal, a third voltage terminal and a first pole of the light-emitting element, respectively, and is used to control, under the control of a third control signal supplied by the third control terminal, the third voltage signal supplied by the third voltage terminal to be written to the first pole of the light-emitting element.

[0024] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a reference voltage writing circuit; the reference voltage write circuit is electrically connected to a second write control end, a reference voltage end and a write node respectively, and is used to write the reference voltage provided by the reference voltage end to the write node under the control of a second write control signal provided by the second write control end; The write node is electrically connected to a control end of the driving circuit, or the write node is electrically connected to a first end of the second energy storage circuit.

[0025] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a resistor circuit; A first end of the resistor circuit is electrically connected to a second end of the driving circuit, and the second end of the resistor circuit is electrically connected to a first electrode of the light-emitting element; The second pole of the light emitting device is electrically connected to a first voltage terminal.

[0026] Optionally, the first energy storage circuit includes a first capacitance and the second energy storage circuit includes a second capacitance; A first end of the first capacitance is electrically connected to a control end of the driving circuit and a first end of the write control circuit respectively, a second end of the first capacitance is electrically connected to the first end of the driving circuit, a first end of the second capacitance is electrically connected to the second end of the write control circuit, and a second end of the second capacitance is electrically connected to a write end; The capacitance value of the second capacitance is smaller than the capacitance value of the first capacitance.

[0027] Optionally, the write control circuitry includes a first transistor; A control pole of the first transistor is electrically connected to the first write control terminal, a first pole of the first transistor is electrically connected to a control terminal of the driving circuit, a second pole of the first transistor is electrically connected to a first terminal of the second energy storage circuit, and a back gate of the first transistor is electrically connected to a second voltage terminal.

[0028] Optionally, the first control circuit includes a second transistor; A control pole of the second transistor is electrically connected to the first control end, a first pole of the second transistor is electrically connected to a first end of the second energy storage circuit, a second pole of the second transistor is electrically connected to a second end of the second energy storage circuit, and a back gate of the second transistor is electrically connected to a second voltage end.

[0029] Optionally, the reference voltage writing circuit includes a third transistor; A control pole of the third transistor is electrically connected to the second write control terminal, a first pole of the third transistor is electrically connected to the reference voltage terminal, a second pole of the third transistor is electrically connected to the write node, and a back gate of the third transistor is electrically connected to a second voltage terminal.

[0030] Optionally, the second control circuit includes a fourth transistor and the drive circuit includes a drive transistor; a control electrode of the fourth transistor is electrically connected to the second control end, a first electrode of the fourth transistor is electrically connected to the power supply voltage end, a second electrode of the fourth transistor is electrically connected to the first end of the driving circuit, and a back gate of the fourth transistor is electrically connected to a second voltage end; The control pole of the driving transistor is the control end of the driving circuit, the first pole of the driving transistor is the first end of the driving circuit, the second pole of the driving transistor is the second end of the driving circuit, and the back gate of the driving transistor is electrically connected to a second voltage end.

[0031] Optionally, the third control circuit includes a fifth transistor; A control electrode of the fifth transistor is electrically connected to the third control terminal, a first electrode of the fifth transistor is electrically connected to the third voltage terminal, a second electrode of the fifth transistor is electrically connected to a first electrode of the light-emitting element, and a back gate of the fifth transistor is electrically connected to a fourth voltage terminal.

[0032] Optionally, the fifth transistor is an n-type transistor, and the fourth voltage end is a third voltage end; A deep n-well is provided between the back gate and the P-type base of the fifth transistor so as to isolate the back gate and the P-type base of the fifth transistor, and the back gate of the fifth transistor and a first electrode of the fifth transistor are both electrically connected to the third voltage terminal.

[0033] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes an n-well and a p-well; the doping concentration of the n-well is greater than the doping concentration of the deep n-well; the ratio of the thickness of the n-well to the thickness of the deep n-well is 0.4 to 0.6, The ratio of the thickness of the p-well to the thickness of the deep n-well is 0.4 to 0.6.

[0034] In a third aspect, an embodiment of the present disclosure further provides a display panel including a plurality of rows and a plurality of columns of the pixel circuits described above.

[0035] Optionally, the display panel according to at least one embodiment of the present disclosure further includes a plurality of columns of data lines; The writing ends of the pixel circuits located in the same column are electrically connected to the data lines of the same column, and the second energy storage circuit includes a second capacitance; The second capacitance is a parasitic capacitance between the data line and a signal line provided in the same layer as the data line.

[0036] Optionally, the display panel includes an effective display area and a peripheral area, the peripheral area is disposed to surround the effective display area, and the pixel circuit includes a first control circuit; The first control circuit and the second energy storage circuit are provided in the peripheral region, and components included in the pixel circuit other than the first control circuit and the second energy storage circuit are provided in the effective display region.

[0037] Optionally, one column of pixel circuits included in the display panel shares one of the first control circuits and one of the second energy storage circuits; the display panel includes M rows and N columns of pixel circuits, where M and N are integers greater than 1; The display panel includes N shared units, and the nth shared unit includes an nth first control circuit and an nth second energy storage circuit; In an effective display area of ​​the display panel, a pixel circuit in the mth row and the nth column includes a light emitting element in the mth row and the nth column, a driving circuit in the mth row and the mth column, a first energy storage circuit in the mth row and the nth column, a writing control circuit in the mth row and the nth column, and a first control circuit in the mth row and the nth column; The nth first control circuit is electrically connected to a first control end, a first end of the nth second energy storage circuit, and a second end of the nth second energy storage circuit, respectively, and is used to control the first end of the nth second energy storage circuit and the second end of the nth second energy storage circuit to communicate with each other or to be cut off under the control of a first control signal provided by the first control end; The write control circuit in the mth row and the nth column is electrically connected to a first write control end, a control end of the driving circuit in the mth row and the nth column, and a first end of the nth second energy storage circuit, respectively, and is used to control the control end of the driving circuit in the mth row and the nth column to communicate with or be cut off from the first end of the nth second energy storage circuit under the control of a write control signal provided by the first write control end; A second end of the nth second energy storage circuit is electrically connected to the nth writing end, and the nth second energy storage circuit is used to store electrical energy; n is a positive integer equal to or less than N, and m is a positive integer equal to or less than M.

[0038] In a fourth aspect, an embodiment of the present disclosure is a driving method applied to the pixel circuit described above, the driving method comprising: A write control circuit controls, under the control of a first write control signal, to connect or disconnect a first end of the first energy storage circuit and a first end of the second energy storage circuit; The driving circuit generates a driving current for driving the light-emitting element under control of a potential at a control end thereof.

[0039] Alternatively, the display period of the pixel circuit includes an initialization step, a self-discharge step, a data preparation step, a potential control step, a data writing step, and a light emitting step, which are set in sequence, and the driving method includes: In the initialization step, the self-discharge step and the data writing step, the write control circuit controls, under the control of the first write control signal, to communicate between a first end of a first energy storage circuit and a first end of a second energy storage circuit; During the data preparation step, the potential control step and the light emission step, the write control circuit controls, under control of the first write control signal, to disconnect the first end of the first energy storage circuit from the first end of the second energy storage circuit.

[0040] Optionally, the pixel circuit further includes a first control circuit, and the driving method includes: In the initialization step, the self-discharge step, the data preparation step and the light-emitting step, the first control circuit controls, under the control of a first control signal, a first end of a second energy storage circuit and a second end of the second energy storage circuit to communicate with each other; During the potential control step and the data writing step, the first control circuit further includes controlling, under control of a first control signal, a first end of the second energy storage circuit to be disconnected from a second end of the second energy storage circuit.

[0041] In a fifth aspect, an embodiment of the present disclosure is a driving method applied to the pixel circuit described above, the driving method comprising: A first control circuit controls, under the control of a first control signal, to establish or block communication between a first end of the second energy storage circuit and a second end of the second energy storage circuit; The driving circuit generates a driving current for driving the light-emitting element under control of a potential at a control end thereof.

[0042] Alternatively, the display period of the pixel circuit includes an initialization step, a self-discharge step, a data preparation step, a potential control step, a data writing step, and a light emitting step, which are set in sequence, and the driving method includes: In the initialization step, the self-discharge step, the data preparation step and the light-emitting step, the first control circuit controls, under the control of a first control signal, a first end of a second energy storage circuit and a second end of the second energy storage circuit to communicate with each other; In the potential control step and the data writing step, the first control circuit controls, under control of a first control signal, so that a first end of the second energy storage circuit and a second end of the second energy storage circuit are disconnected from each other.

[0043] Optionally, the pixel circuit further includes a write control circuit, and the driving method includes: In the initialization step, the self-discharge step and the data writing step, the write control circuit controls, under the control of the first write control signal, to communicate between a first end of a first energy storage circuit and a first end of a second energy storage circuit; The method further includes, during the data preparation step, the potential control step and the light emission step, controlling the write control circuit to disconnect a first end of the first energy storage circuit and a first end of the second energy storage circuit under the control of the first write control signal.

[0044] In a sixth aspect, an embodiment of the present disclosure provides a display device including the above-mentioned display panel.

[0045] Optionally, the display panel includes a first silicon substrate, and a pixel circuit and a gate driving circuit disposed on the first silicon substrate; The display device includes a second silicon substrate and a display driver chip disposed on the second silicon substrate.

[0046] Optionally, the area of ​​the first silicon substrate is larger than the area of ​​the second silicon substrate; The minimum width of a signal line included in the display panel is greater than the width of a signal line included in the display driver chip. [Brief description of the drawings]

[0047] [Figure 1] FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Diagram 2] FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Diagram 3] FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 4] FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Diagram 5] FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 6] FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 7] FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 8] FIG. 2 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 9] 9 is an operation timing chart of at least one embodiment of the pixel circuit shown in FIG. 8 of the present disclosure. [Figure 10A] FIG. 9 is a schematic diagram of an operational state of at least one embodiment of a pixel circuit such as that shown in FIG. 8 of the present disclosure during an initialization stage S1. [Figure 10B] FIG. 9 is a schematic diagram of an operational state of at least one embodiment of a pixel circuit as shown in FIG. 8 of the present disclosure during a self-discharge phase S2. [Figure 10C] FIG. 9 is a schematic diagram of an operational state of at least one embodiment of a pixel circuit such as that shown in FIG. 8 of the present disclosure during a data preparation stage S3. [Figure 10D] FIG. 9 is a schematic diagram of an operating state in a potential control stage S4 of at least one embodiment of a pixel circuit as shown in FIG. 8 of the present disclosure. [Figure 10E]FIG. 9 is a schematic diagram of an operational state of at least one embodiment of a pixel circuit as shown in FIG. 8 of the present disclosure in a data writing phase S5. [Figure 10F] FIG. 9 is a schematic diagram of an operational state of at least one embodiment of a pixel circuit as shown in FIG. 8 of the present disclosure in a light-emitting stage S6. [Figure 11] 1 is a schematic diagram of an NMOS transistor structure and a PMOS structure in accordance with at least one embodiment of the present disclosure. [Figure 12] 1A and 1B are schematic diagrams illustrating a structure of an NMOS transistor and a structure of a PMOS transistor in the related art. [Figure 13] FIG. 2 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 14] FIG. 2 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 15] FIG. 2 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 16] FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 17] FIG. 2 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 18] 18 is an operation timing chart of at least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure. [Figure 19] FIG. 13 is a schematic diagram illustrating a second transistor and a second capacitor shared by pixel circuits in each column of a display panel according to at least one embodiment of the present disclosure. [Figure 20] FIG. 1 is a structural diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0048] Hereinafter, the technical aspects of the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, but it is obvious that the described embodiments are only some embodiments of the present disclosure, and are not all embodiments. Based on the embodiments of the present disclosure, other embodiments obtained by those skilled in the art without paying creative labor shall all be within the scope of protection of the present disclosure.

[0049] The transistors used in all the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with similar characteristics. In the embodiments of the present disclosure, in order to distinguish between the two poles of the transistor other than the gate, one pole is called a first electrode and the other pole is called a second electrode.

[0050] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be the drain and the second electrode may be the source, or the first electrode may be the source and the second electrode may be the drain.

[0051] The pixel circuit according to the embodiment of the present disclosure includes a light emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit and a writing control circuit; A first end of the first energy storage circuit is electrically connected to the control end of the driving circuit and the first end of the writing control circuit respectively, a second end of the first energy storage circuit is electrically connected to the first end of the driving circuit, a first end of the second energy storage circuit is electrically connected to the second end of the writing control circuit, and a second end of the second energy storage circuit is electrically connected to the writing end, the first energy storage circuit and the second energy storage circuit are used for storing electric energy; A control end of the write control circuit is electrically connected to a first write control end, and the write control circuit is used to control the first end of the first energy storage circuit and the first end of the second energy storage circuit to communicate or be cut off under the control of a first write control signal provided by the first write control end; A second end of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is used to generate a driving current for driving the light-emitting element under the control of the potential of its control end.

[0052] In the pixel circuit described in the embodiment of the present disclosure, the write control circuit is provided between the first energy storage circuit and the second energy storage circuit, and the write control circuit controls a first end of the first energy storage circuit to be connected or disconnected from a first end of the second energy storage circuit under control of a first write control signal, the first energy storage circuit and the second energy storage circuit are capable of controlling a potential of a control end of a driving circuit by voltage division, and the driving circuit generates a driving current for driving a light-emitting element under control of the potential of its control end.

[0053] During operation of the pixel circuit described in the embodiments of the present disclosure, by controlling to adjust the capacitance value of the first capacitance included in the first energy storage circuit and the capacitance value of the second capacitance included in the second energy storage circuit, the drive current of the drive circuit that drives the light-emitting element to emit light can be controlled to be independent of the threshold voltage of the drive transistor included in the drive circuit.

[0054] The embodiments of the present disclosure can provide a current-type pixel circuit that is simple in structure and capable of self-compensating the threshold voltage, for application in OLED (Organic Light Emitting Diode) displays.

[0055] As shown in FIG. 1, a pixel circuit according to at least one embodiment of the present disclosure includes a light emitting element E0, a driving circuit 11, a first energy storage circuit 12, a second energy storage circuit 13 and a writing control circuit 14; A first end of the first energy storage circuit 12 is electrically connected to the control end of the driving circuit 11 and a first end of the write control circuit 14 respectively, a second end of the first energy storage circuit 12 is electrically connected to the first end of the driving circuit 11, a first end of the second energy storage circuit 13 is electrically connected to the second end of the write control circuit 14, and a second end of the second energy storage circuit 13 is electrically connected to the write end DW, and the first energy storage circuit 12 and the second energy storage circuit 13 are used to store electrical energy; The control end of the write control circuit 14 is electrically connected to a first write control end WS1, and the write control circuit 14 is used to control the communication or disconnection between the first end of the first energy storage circuit 12 and the first end of the second energy storage circuit 13 under the control of a first write control signal provided by the first write control end WS1; A second end of the driving circuit 11 is electrically connected to the light emitting element E0, and the driving circuit 11 is used to generate a driving current for driving the light emitting element E0 under the control of the potential of its control end.

[0056] During operation of at least one embodiment of the pixel circuit as shown in FIG. 1 of the present disclosure, the write control circuit 14 controls the control end of the driving circuit 11 and the first end of the second energy storage circuit 13 to communicate or be cut off under the control of a first write control signal, and the writing of the data voltage is divided by the first energy storage circuit 12 and the second energy storage circuit 13, so that the dynamic range of the data voltage is expanded, which is advantageous for the design of the DAC (digital-to-analog converter) in the source driver and the uniformity of the output of the data line.

[0057] During operation of at least one embodiment of the pixel circuit as shown in FIG. 1 of the present disclosure, a display period of the pixel circuit may include an initialization stage, a self-discharge stage, a data preparation stage, a potential control stage, a data writing stage and a light emitting stage, which are set in sequence; In the initialization step, the self-discharge step and the data writing step, the write control circuit 13 controls the first end of the first energy storage circuit 12 to communicate with the first end of the second energy storage circuit 13 under the control of the first write control signal; In the data preparation stage, the potential control stage and the light emitting stage, the write control circuit 14 controls the first end of the first energy storage circuit 12 and the first end of the second energy storage circuit 13 to be disconnected under the control of the first write control signal.

[0058] As shown in FIG. 2 , in addition to at least one embodiment of the pixel circuit shown in FIG. 1 , the pixel circuit according to at least one embodiment of the present disclosure may further include a first control circuit 15; The first control circuit 15 is electrically connected to a first control end R0, a first end of the second energy storage circuit 13, and a second end of the second energy storage circuit 13, respectively, and is used to control the communication between the first end of the second energy storage circuit 13 and the second end of the second energy storage circuit 13 to be disconnected or connected under the control of a first control signal provided by the first control end R0.

[0059] In operation of at least one embodiment of the pixel circuit as shown in FIG. 2 of the present disclosure, a display cycle may include an initialization stage, a self-discharge stage, a data preparation stage, a potential control stage, a data writing stage and a light emitting stage, which are set in sequence; In the initialization stage, the first control circuit 15, under the control of the first control signal, controls the first end of the second energy storage circuit 13 to communicate with the second end of the second energy storage circuit 13, so that the second energy storage circuit 13 is reset; In the self-discharge stage and the data preparation stage, under the control of the first control signal, the first control circuit 15 controls the first end of the second energy storage circuit 13 to communicate with the second end of the second energy storage circuit 13, so that the charge stored in the second energy storage circuit 13 is cleared, thereby enabling the gate-source voltage of the drive transistor included in the drive circuit 11 to be controlled by the first energy storage circuit 12 to be maintained at the same level as in the self-discharge stage in the data preparation stage; In the potential control stage, the first control circuit 15 controls the first end of the second energy storage circuit 13 to be disconnected from the second end of the second energy storage circuit 13 under the control of the first control signal, but the write control circuit 14 controls the first end of the first energy storage circuit 12 to be disconnected from the first end of the second energy storage circuit 13 under the control of the first write control signal, so that no charge is stored in the second energy storage circuit 13, and the gate-source voltage of the drive transistor included in the drive circuit 11 is maintained by the first energy storage circuit 12 to be the same as in the data preparation stage. In a data writing stage, the first control circuit 15 controls the first end of the second energy storage circuit 13 to be disconnected from the second end of the second energy storage circuit 13 under the control of the first control signal, the write control circuit 14 controls the first end of the first energy storage circuit 12 to be connected to the first end of the second energy storage circuit 13 under the control of the first write control signal, and the first energy storage circuit 12 and the second energy storage circuit 13 redistribute charges to change the gate-source voltage of the driving transistor; In the light-emitting stage, the first control circuit 15, under the control of the first control signal, controls the first end of the second energy storage circuit 13 to be connected to the second end of the second energy storage circuit 13, the write control circuit 14, under the control of the first write control signal, controls the first end of the first energy storage circuit 12 to be disconnected from the first end of the second energy storage circuit 13, and the driving transistor drives the light-emitting element to emit light.

[0060] The pixel circuit according to at least one embodiment of the present disclosure may further include a second control circuit; The second control circuit is electrically connected to a second control end, a power supply voltage end and a first end of the driving circuit, respectively, and is used to control communication or disconnection between the power supply voltage end and the first end of the driving circuit under the control of a second control signal supplied by the second control end.

[0061] In a specific implementation, the second control circuit may control the communication or disconnection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the second control signal, thereby controlling the self-discharge threshold compensation process of the driving transistor included in the driving circuit.

[0062] In at least one embodiment of the present disclosure, the second end of the driving circuit is electrically connected to the first pole of the light-emitting element, and the second pole of the light-emitting element is electrically connected to a first voltage end; The power supply voltage terminal is used to supply a power supply voltage, and the first voltage terminal is used to supply a first voltage signal; The absolute value of the voltage value of the power supply voltage is smaller than the absolute value of the voltage value of the first voltage signal.

[0063] Alternatively, the voltage value range of the power supply voltage may be 1V or more and 3V or less, and the voltage value range of the first voltage signal may be, but is not limited to, -8V or more and -5V or less.

[0064] As shown in FIG. 3, in addition to at least one embodiment of the pixel circuit shown in FIG. 2, the pixel circuit according to at least one embodiment of the present disclosure further includes a second control circuit 10; the second control circuit 10 is electrically connected to a second control end DS, a power supply voltage end Vd, and a first end of the driving circuit 11, and is used to control the communication between the power supply voltage end Vd and the first end of the driving circuit 11 to be connected or disconnected under the control of a second control signal provided by the second control end DS; A second end of the driving circuit 11 is electrically connected to a first electrode of the light emitting element E0, and a second electrode of the light emitting element E0 is electrically connected to a first voltage end V1.

[0065] In at least one embodiment shown in FIG. 3, the first voltage end V1 may be, but is not limited to, a low voltage end.

[0066] In at least one embodiment of the present disclosure, the pixel circuit further includes a third control circuit, and a second end of the driving circuit is electrically connected to a first pole of the light-emitting element, and a second pole of the light-emitting element is electrically connected to a first voltage end; The third control circuit is electrically connected to a third control terminal, a third voltage terminal and a first pole of the light-emitting element, respectively, and is used to control, under the control of a second control signal supplied by the second control terminal, that the third voltage signal supplied by the third voltage terminal is written to the first pole of the light-emitting element.

[0067] In a specific implementation, the third control circuit is used to control the light-emitting element not to emit light by writing the third voltage signal to the first pole of the light-emitting element during a non-light-emitting stage under the control of the third control signal, so that the difference between the potential of the first pole of the light-emitting element and the potential of the second pole of the light-emitting element is smaller than the lighting voltage of the light-emitting element.

[0068] During operation of the pixel circuit according to at least one embodiment of the present disclosure, the third control circuit can reset the potential of the first electrode of the light-emitting element, and can also play a role of shunting current during the light-emitting stage, thereby improving the driving accuracy of the microcurrent of the silicon-based OLED (Organic Light-Emitting Diode).

[0069] Alternatively, the light emitting element may be an organic light emitting diode, the first pole of the light emitting element may be an anode of the organic light emitting diode, and the second pole of the light emitting element may be a cathode of the organic light emitting diode, but is not limited thereto.

[0070] As shown in FIG. 4, in addition to at least one embodiment of the pixel circuit shown in FIG. 3, the pixel circuit according to at least one embodiment of the present disclosure further includes a third control circuit 20; The third control circuit 20 is electrically connected to the third control end AZ, the third voltage end Vf and the first pole of the light-emitting element E0, respectively, and is used to control the third voltage signal supplied by the third voltage end Vf to be written to the first pole of the light-emitting element E0 under the control of the second control signal supplied by the third control end AZ.

[0071] During operation of at least one embodiment of a pixel circuit as shown in FIG. 4 of the present disclosure, the third control circuit 20 is used to control the light-emitting element E0 not to emit light by writing a third voltage signal supplied by a third voltage terminal Vf to the first pole of the light-emitting element E0 during a non-light-emitting stage under the control of a third control signal, so that the difference between the potential of the first pole of the light-emitting element E0 and the potential of the second pole of the light-emitting element E0 is smaller than the lighting voltage of the light-emitting element E0.

[0072] In at least one embodiment of the present disclosure, the first voltage end V1 may be, but is not limited to, a low voltage end.

[0073] Optionally, the pixel circuit according to at least one embodiment of the present disclosure may further include a reference voltage writing circuit; the reference voltage write circuit is electrically connected to a second write control end, a reference voltage end and a write node respectively, and is used to write the reference voltage provided by the reference voltage end to the write node under the control of a second write control signal provided by the second write control end to control the potential of the write node; The write node is electrically connected to a control end of the driving circuit, or the write node is electrically connected to a first end of the second energy storage circuit.

[0074] As shown in FIG. 5 , in addition to at least one embodiment of the pixel circuit shown in FIG. 4 , the pixel circuit according to at least one embodiment of the present disclosure may further include a reference voltage writing circuit 16; The reference voltage write circuit is electrically connected to the second write control terminal WS2, the reference voltage terminal R2 and the control terminal of the driving circuit 11, respectively, and is used to write the reference voltage Vref supplied by the reference voltage terminal R2 to the control terminal of the driving circuit 11 under the control of the second write control signal supplied by the second write control terminal WS2, to control the potential of the control terminal of the driving circuit 11.

[0075] As shown in FIG. 6 , in addition to at least one embodiment of the pixel circuit shown in FIG. 4 , the pixel circuit according to at least one embodiment of the present disclosure may further include a reference voltage writing circuit 16; The reference voltage write circuit 16 is electrically connected to the second write control terminal WS2, the reference voltage terminal R2 and the first terminal of the second energy storage circuit 13 respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal R2 to the first terminal of the second energy storage circuit 13 under the control of the second write control signal provided by the second write control terminal WS2, so as to control the potential of the first terminal of the second energy storage circuit 13.

[0076] Optionally, the pixel circuit according to at least one embodiment of the present disclosure may further include a resistor circuit; A first end of the resistor circuit is electrically connected to a second end of the driving circuit, and a second end of the resistor circuit is electrically connected to the first electrode of the light-emitting element, so as to prevent a short circuit between the first electrode of the light-emitting element and the second electrode of the light-emitting element; The second pole of the light emitting device is electrically connected to a first voltage terminal.

[0077] In at least one embodiment of the present disclosure, the resistance circuit may include, but is not limited to, a first resistor.

[0078] As shown in FIG. 7, in addition to at least one embodiment of the pixel circuit shown in FIG. 4, the pixel circuit according to at least one embodiment of the present disclosure may further include a resistor circuit 70; A first end of the resistance circuit 70 is electrically connected to a second end of the driving circuit 11, and a second end of the resistance circuit 70 is electrically connected to the first pole of the light-emitting element E0, so as to prevent a short circuit between the first pole of the light-emitting element E0 and the second pole of the light-emitting element E0.

[0079] Optionally, the first energy storage circuit includes a first capacitance, the second energy storage circuit includes a second capacitance, and the write control circuit includes a first transistor; A first end of the first capacitance is electrically connected to a control end of the driving circuit and a first end of the write control circuit, and a second end of the first capacitance is electrically connected to the first end of the driving circuit; A first end of the second capacitance is electrically connected to a second end of the write control circuit, and a second end of the second capacitance is electrically connected to a write end; The capacitance value of the second capacitance is smaller than the capacitance value of the first capacitance.

[0080] In at least one embodiment of the present disclosure, since the first capacitance needs to control the potential of the driving transistor in the driving circuit within one frame time, the capacitance value of the first capacitance needs to be set large, and the capacitance value of the first capacitance is set to be larger than the capacitance value of the second capacitance.

[0081] Optionally, the write control circuitry includes a first transistor; a control pole of the first transistor is electrically connected to the first write control terminal, a first pole of the first transistor is electrically connected to a control terminal of the driving circuit, a second pole of the first transistor is electrically connected to a first terminal of the second capacitance, and a back gate of the first transistor is electrically connected to a second voltage terminal; A second end of the second capacitor is electrically connected to the write end.

[0082] Optionally, the first control circuit includes a second transistor; A control pole of the second transistor is electrically connected to the first control end, a first pole of the second transistor is electrically connected to a first end of the second energy storage circuit, a second pole of the second transistor is electrically connected to a second end of the second energy storage circuit, and a back gate of the second transistor is electrically connected to a second voltage end.

[0083] Optionally, the reference voltage writing circuit includes a third transistor; A control pole of the third transistor is electrically connected to the second write control terminal, a first pole of the third transistor is electrically connected to the reference voltage terminal, a second pole of the third transistor is electrically connected to the write node, and a back gate of the third transistor is electrically connected to a second voltage terminal.

[0084] Optionally, the second control circuit includes a fourth transistor and the drive circuit includes a drive transistor; a control electrode of the fourth transistor is electrically connected to the second control end, a first electrode of the fourth transistor is electrically connected to the power supply voltage end, a second electrode of the fourth transistor is electrically connected to the first end of the driving circuit, and a back gate of the fourth transistor is electrically connected to a second voltage end; The control pole of the driving transistor is the control end of the driving circuit, the first pole of the driving transistor is the first end of the driving circuit, the second pole of the driving transistor is the second end of the driving circuit, and the back gate of the driving transistor is electrically connected to a second voltage end.

[0085] Optionally, the third control circuit includes a fifth transistor; A control electrode of the fifth transistor is electrically connected to the third control terminal, a first electrode of the fifth transistor is electrically connected to the third voltage terminal, a second electrode of the fifth transistor is electrically connected to a first electrode of the light-emitting element, and a back gate of the fifth transistor is electrically connected to a fourth voltage terminal.

[0086] In at least one embodiment of the present disclosure, the driving transistor, the first transistor, the second transistor, and the fourth transistor may all be PMOS (P-type metal oxide semiconductor) transistors, and the fifth transistor may be an NMOS (N-type metal oxide semiconductor) transistor, but is not limited thereto. In a specific implementation, the driving transistor, the first transistor, the second transistor, the fourth transistor, and the fifth transistor may all be PMOS transistors.

[0087] In at least one embodiment of the present disclosure, the back gate of each of the PMOS transistors is electrically connected to the second voltage end and is not electrically connected to the power supply voltage end, so that the n-well potential of the base of each PMOS transistor is isolated from the power supply voltage, which is beneficial to the base bias effect.

[0088] Optionally, the second voltage end may be, but is not limited to, a high voltage end.

[0089] As shown in FIG. 8, in addition to at least one embodiment of the pixel circuit shown in FIG. 4, the light emitting element is an organic light emitting diode O1; The first energy storage circuit 12 includes a first capacitance C1, the second energy storage circuit 13 includes a second capacitance C2, the write control circuit 14 includes a first transistor P1, and the driving circuit 11 includes a driving transistor P0; A first end of the first capacitance C1 is electrically connected to the gate of the driving transistor P0, and a second end of the first capacitance C1 is electrically connected to the source of the driving transistor P0; The gate of the first transistor P1 is electrically connected to the first write control end WS1, the source of the first transistor P1 is electrically connected to the gate of the driving transistor P0, the drain of the first transistor P1 is electrically connected to the first end of the second capacitor C2, and the back gate of the first transistor P1 is electrically connected to a high voltage end, which is used to supply a high voltage VDD; A second end of the second capacitance C2 is electrically connected to the write end DW; The first control circuit 15 includes a second transistor P2, The gate of the second transistor P2 is electrically connected to the first control end R0, the source of the second transistor P2 is electrically connected to the first end of the second capacitance C2, the drain of the second transistor P2 is electrically connected to the second end of the second capacitance C2, and the back gate of the second transistor P2 is electrically connected to a high voltage end, which is used to supply a high voltage VDD; The second control circuit 10 includes a fourth transistor P4, The gate of the fourth transistor P4 is electrically connected to the second control end DS, the source of the fourth transistor P4 is electrically connected to the power supply voltage end Vd, the second electrode of the fourth transistor P4 is electrically connected to the source of the driving transistor P0, and the back gate of the fourth transistor P4 is electrically connected to a high voltage end, which is used to supply a high voltage VDD; The back gate of the driving transistor P0 is electrically connected to the high voltage end, The third control circuit 20 includes a fifth transistor M5, The gate of the fifth transistor M5 is electrically connected to the third control end AZ, the source of the fifth transistor M5 is electrically connected to the third voltage end Vf, the drain of the fifth transistor M5 is electrically connected to the anode of the organic light emitting diode O1, and the back gate of the fifth transistor M5 is electrically connected to the third voltage end Vf; The cathode of the organic light emitting diode O1 is electrically connected to the low voltage terminal V0.

[0090] In at least one embodiment of the present disclosure, the fifth transistor is an n-type transistor, and the fourth voltage end is the third voltage end; or The fifth transistor is a p-type transistor, and the fourth voltage end is a second voltage end.

[0091] In at least one embodiment of the present disclosure, when the fifth transistor is an n-type transistor, a deep n-well is provided between a back gate and a P-type base of the fifth transistor so as to isolate the back gate and the P-type base of the fifth transistor, and the back gate of the fifth transistor and a first electrode of the fifth transistor are both electrically connected to the third voltage terminal.

[0092] Optionally, the pixel circuit according to at least one embodiment of the present disclosure may further include an n-well, and the doping concentration of the n-well is greater than the doping concentration of the deep n-well; The ratio of the thickness of the n-well to the thickness of the deep n-well is 0.4 to 0.6, but is not limited thereto.

[0093] For example, the thickness of the n-well may be 0.5 um, and the thickness of the deep n-well may be 1 um.

[0094] In a specific implementation, the pixel circuit described in at least one embodiment of the present disclosure may further include a p-well, and the ratio of the thickness of the p-well to the thickness of the deep n-well is greater than or equal to 0.4 and less than or equal to 0.6.

[0095] For example, the thickness of the p-well may be 0.5um and the thickness of the deep n-well may be 1um.

[0096] In at least one embodiment shown in FIG. 8, the fourth voltage terminal is the third voltage terminal Vf, but is not limited thereto.

[0097] In at least one embodiment shown in FIG. 8, in 0 gradation (grayscale), when the organic light emitting diode O1 emits light, the anode potential of the organic light emitting diode O1 may be -5V, and at this time, the third voltage signal may be a voltage signal of -5V, and the low voltage end V0 may supply a voltage signal of -9V, but is not limited thereto.

[0098] In at least one embodiment of the pixel circuit shown in FIG. 8, P0, P1, P2 and P4 are all PMOS transistors, and M5 is an NMOS transistor.

[0099] In at least one embodiment of the pixel circuit shown in FIG. 8, in order to facilitate realization of a narrow frame, the second transistor P2 and the second capacitor C2 may be located outside the effective display area, and the pixel circuits of each column may share one of the second transistors and one of the second capacitors, and within the effective display area, one pixel circuit includes only one capacitor, which can effectively reduce the requirements for circuit processing.

[0100] As shown in FIG. 9, during operation of at least one embodiment of the pixel circuit as shown in FIG. 8 of the present disclosure, a display cycle may include an initialization stage S1, a self-discharge stage S2, a data preparation stage S3, a potential control stage S4, a data writing stage S5 and a light emitting stage S6, which are set in sequence, In the initialization step S1, as shown in FIG. 10A, R0 supplies a low voltage signal, WS1 supplies a low voltage signal, DS supplies a low voltage signal, AZ supplies a high voltage signal, P1, P2, P4 and M5 are all turned on, the write end DW supplies an initial voltage Vofs to the second end of C2, and since P2 and P1 are turned on, the potential of the first end of C2 also becomes Vofs, and the gate voltage Vg of P0 becomes Vofs. At this time, the power supply voltage end Vd supplies the first power supply voltage ELVDD1, and the source voltage Vs of P0 becomes ELVDD1. Then, the gate-source voltage Vgs of P0 (Vgs is equal to Vg-Vs) becomes ELVDD1-Vofs, and ELVDD1-Vofs>|Vth|, and the next discharge is prepared, where Vth is the threshold voltage of the driving transistor P0 when there is no backgate effect; In the self-discharge stage S2, R0 supplies a low voltage signal, WS1 supplies a low voltage signal, DS supplies a high voltage signal, AZ supplies a high voltage signal, and the power supply voltage terminal Vd supplies the first power supply voltage ELVDD1. As shown in FIG. 10B, P1 and P2 are turned on and P4 is turned off to start discharging. The source voltage Vs of P0 decreases. As Vs decreases, the backgate effect occurs, and |Vth_ef| is equal to a×(VDD−Vs)+|Vth|, where Vth_ef is the threshold voltage of P0 when there is no backgate effect, and a is the coefficient of the backgate effect. As Vs decreases, Vgs also decreases at the same time. When |Vth_ef| increases to |Vgs|, P0 is turned off to stop discharging. At this time, a×(VDD−Vs)+|Vth|=|Vgs|.

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[0101] In the light emitting stage S6, the power supply voltage may be first increased from ELVDD2 to ELVDD1, and then M5 may be turned off.

[0102] In at least one embodiment of the present disclosure, when ELVDD1 ranges from 2V to 8V, the value of VDD may range from 2V to 8V, and the value of Vf may range from -6V to 0V, but is not limited thereto.

[0103] In at least one embodiment of the present disclosure, ELVDD1-Vofs may be, but is not limited to, 1.5V or greater.

[0104] In FIGS. 10A to 10F, transistors corresponding to the marks "o" are turned on, and transistors corresponding to the marks "x" are turned off.

[0105] In at least one embodiment of the pixel circuit as shown in FIG. 8 of the present disclosure, the driving transistor P0 is equivalent to a current source controlled by a gate voltage, thereby realizing direct control of the driving current flowing through O1 by the data voltage Vdata. Therefore, at least one embodiment of the pixel circuit as shown in FIG. 8 of the present disclosure uses a current-type pixel driving method, and the driving transistor included in the driving circuit in at least one embodiment of the pixel circuit as shown in FIG. 8 of the present disclosure is a PMOS transistor. If the anode of O1 and the cathode of O1 are shorted, no spot or line defect will occur due to the anode voltage of O1 being negative (if the anode voltage of O1 is negative, the drain voltage of the driving transistor P0 will also be negative. If the driving transistor is an NMOS transistor, the source voltage of the driving transistor will be negative. At this time, the parasitic diode between the base of the driving transistor and the source of the driving transistor will be forward conductive, causing a latch-up effect and resulting in a spot or line defect).

[0106] In at least one embodiment of the pixel circuit shown in FIG. 8 of the present disclosure, the driving transistor is a PMOS transistor, and compared with a pixel circuit in which the driving transistor is an NMOS transistor, at least one embodiment of the present disclosure can have a wider anode dynamic range, for the following reasons: In the case of a current-type pixel circuit in which the driving transistor is an NMOS transistor, when the voltage of the anode of the organic light-emitting diode O1 is set to a negative voltage, the negative voltage is input to the drain of the driving transistor, and if the driving transistor is an NMOS transistor, the presence of a forward-biased diode between the back gate of the driving transistor and the drain of the driving transistor will cause a latch-up effect, causing the pixel circuit to operate abnormally. Therefore, a current-type pixel circuit in which the driving transistor is a PMOS transistor has a wider anode dynamic range, and when the driving transistor in the current-type pixel circuit is a PMOS transistor, the potential of the anode of the organic light-emitting diode O1 may be a negative voltage.

[0107] At least one embodiment of the pixel circuit shown in FIG. 8 of the present disclosure can compensate for the self-discharge threshold voltage before writing the data voltage, and can improve the display uniformity of the pixel circuit.

[0108] During operation of at least one embodiment of a pixel circuit as shown in FIG. 8 of the present disclosure, the writing of a data voltage is divided by two capacitances, and the dynamic range of the data voltage is expanded, which is advantageous for the design of a DAC (digital-to-analog converter) in the source driver and the uniformity of the output of the data line.

[0109] In the related pixel circuit, P0 is an NMOS transistor, and the higher the potential of the gate of P0, the brighter the OLED becomes, so that when light leaks from the drain of P1 to the first capacitor C1 during the non-emitting stage, the potential of the gate of P0 rises, increasing the luminance of the OLED and causing a bright spot. In view of this, at least one embodiment of the present disclosure sets P0 as a PMOS transistor to solve the above problem.

[0110] At least one embodiment of the pixel circuit as shown in FIG. 8 of the present disclosure can prevent the occurrence of the low gradation bright spot phenomenon caused by leakage from the N-type base of the first transistor P1 for transmitting a data voltage to the first capacitor C1 toward the drain of the first transistor P1, and the cause of this phenomenon is as follows. In at least one embodiment of the pixel circuit as shown in FIG. 8 of the present disclosure, since P0 is a PMOS transistor, even if current leaks from the N-type base of the first transistor P1 toward the drain of the first transistor P1 to the first capacitance C1 during a non-light-emitting stage, causing the potential of the gate of P0 to increase, the light emission brightness of the organic light-emitting diode O1 is not increased and no bright spot is generated, since the driving transistor P0 is also a PMOS transistor.

[0111] At least one embodiment of the pixel circuit shown in FIG. 8 of the present disclosure is a current-type pixel circuit, which can compensate for the shortened life span caused by an increase in the internal resistance of the organic light-emitting diode O1; and in at least one embodiment of the pixel circuit shown in FIG. 8 of the present disclosure, a high voltage VDD is input to the back gate of each PMOS transistor, which is not electrically connected to the power supply voltage end, so that the n-well potential of the base of each PMOS transistor is isolated from the power supply voltage end, which is favorable for the base bias effect, and the base potential of the PMOS transistor is higher than the source potential of the PMOS transistor, and the back gate effect makes the PMOS transistor turn off more thoroughly, thereby improving the leakage current Ioff of the switch transistor.

[0112] In at least one embodiment of the pixel circuit shown in FIG. 8 of the present disclosure, the fifth transistor M5 is an NMOS transistor, and the back gate of the fifth transistor M5 and the source of the fifth transistor M5 are both electrically connected to a third voltage end Vf; A deep n-well is provided between the back gate and the P-type base of the fifth transistor M5 so as to isolate the back gate and the P-type base of the fifth transistor M5, and the back gate and the source of the fifth transistor M5 are both electrically connected to the third voltage terminal Vf.

[0113] In the related art, in a display panel, the back gate of the N-type transistor in a pixel circuit and the back gate of the N-type transistor in a drive circuit (the drive circuit is for supplying a drive signal to the pixel circuit) are both electrically connected to the P-type base, whereas in at least one embodiment of the present disclosure, the back gate of the fifth transistor M5 in the pixel circuit needs to be electrically connected to a third voltage terminal Vf, and a voltage signal of 0V is input to the P-type base, so that a deep n-well needs to be provided between the P-type base and the back gate of the fifth transistor M5 in order to isolate the P-type base and the back gate of the fifth transistor M5.

[0114] In at least one embodiment of the present disclosure, the dynamic range of the anode of the organic light emitting diode O1 needs to be expanded to negative voltage, and if the withstand voltage of each transistor is 8V and ELVDD1 is 3V, the minimum anode reset voltage can be -5V, so it is necessary to input a voltage signal of -5V to the back gate of the fifth transistor M5 (generally, the source of an NMOS transistor and the back gate of an NMOS transistor are electrically connected to the same voltage terminal). Therefore, it is necessary to isolate the P-type base from the back gate of the fifth transistor M5.

[0115] FIG. 11 is a structural diagram of an NMOS transistor and a PMOS transistor in accordance with at least one embodiment of the present disclosure.

[0116] In FIG. 11, reference numeral 60 denotes a P-type base, reference numeral 61 denotes a deep n-well, reference numeral 621 denotes a gate of an NMOS transistor, reference numeral 622 denotes a gate of a PMOS transistor, reference numeral 631 denotes a backgate of an NMOS transistor, reference numeral 632 denotes a source of an NMOS transistor, reference numeral 633 denotes a drain of an NMOS transistor, reference numeral 641 denotes a backgate of a PMOS transistor, reference numeral 642 denotes a source of a PMOS transistor, reference numeral 643 denotes a drain of a PMOS transistor, reference numeral 65 denotes an insulating structure, reference numerals 661 and 663 denote N-wells, and reference numeral 662 denotes a P-well.

[0117] In FIG. 11, the NMOS transistor may be the fifth transistor.

[0118] As shown in FIG. 11, a deep n-well 61 is provided between the back gate 631 of the NMOS transistor and the P-type base 60 so as to enable a voltage signal of −5 V to be input to the back gate of the NMOS transistor while a voltage signal of 0 V can be input to the P-type base 60.

[0119] In the related art, since a deep n-well is not provided between the back gate 631 and the P-type base 60 of the NMOS transistor, it is not possible to input different voltage signals to the back gate 631 and the P-type base 60 of the NMOS transistor.

[0120] FIG. 12 is a schematic diagram showing the structures of an NMOS transistor and a PMOS transistor in the related art.

[0121] FIG. 12 differs from FIG. 11 in that the deep n-well 61 is not provided.

[0122] As shown in FIG. 13, in addition to at least one embodiment of the pixel circuit shown in FIG. 8, the pixel circuit according to at least one embodiment of the present disclosure further includes a reference voltage writing circuit 16; The reference voltage write circuit 16 includes a third transistor P3, The gate of the third transistor P3 is electrically connected to the second write control end WS2, the source of the third transistor P3 is electrically connected to the reference voltage end R2, the drain of the third transistor P3 is electrically connected to the gate of the driving transistor P0, the back gate of the third transistor P3 is electrically connected to the high voltage end, the reference voltage end R2 is used to supply a reference voltage Vref, and the high voltage end is used to supply a high voltage VDD.

[0123] In at least one embodiment of the pixel circuit shown in FIG. 13, P3 is a PMOS transistor, but is not limited to such.

[0124] As shown in FIG. 14, in addition to at least one embodiment of the pixel circuit shown in FIG. 8, the pixel circuit according to at least one embodiment of the present disclosure further includes a reference voltage writing circuit 16; The reference voltage write circuit 16 includes a third transistor P3, The gate of the third transistor P3 is electrically connected to the second write control end WS2, the source of the third transistor P3 is electrically connected to the reference voltage end R2, the drain of the third transistor P3 is electrically connected to the first end of the second capacitance C2, the back gate of the third transistor P3 is electrically connected to the high voltage end, the reference voltage end R2 is used to supply a reference voltage Vref, and the high voltage end is used to supply a high voltage VDD.

[0125] In at least one embodiment of the pixel circuit shown in FIG. 14, P3 is a PMOS transistor, but is not limited to such.

[0126] As shown in FIG. 15, in addition to at least one embodiment of the pixel circuit shown in FIG. 8, the pixel circuit according to at least one embodiment of the present disclosure further includes a first resistor R01; The first resistor R01 is connected between the drain of the driving transistor P0 and the anode of the organic light emitting diode O1; A first end of the first resistor R01 is electrically connected to the drain of the driving transistor P0, and a second end of the first resistor R01 is electrically connected to the anode of the organic light emitting diode O1; The first resistor R01 can prevent a short circuit between the anode of the organic light emitting diode O1 and the cathode of the organic light emitting diode O1.

[0127] In at least one embodiment of the present disclosure, a pixel circuit includes a light emitting element, a driving circuit, a first energy storage circuit, a second energy storage circuit, and a first control circuit; A first end of the first energy storage circuit is electrically connected to a control end of the driving circuit, a second end of the first energy storage circuit is electrically connected to a first end of the driving circuit, a first end of the second energy storage circuit is electrically connected to a control end of the driving circuit, and a second end of the second energy storage circuit is electrically connected to a writing end, and the first energy storage circuit and the second energy storage circuit are used to store electrical energy; The first control circuit and the second energy storage circuit are connected in parallel with each other, and the first control circuit is used to control the first end of the second energy storage circuit and the second end of the second energy storage circuit to communicate with each other or to be cut off under the control of a first control signal provided by a first control end; A second end of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is used to generate a driving current for driving the light-emitting element under the control of the potential of its control end.

[0128] During operation of the pixel circuit described in at least one embodiment of the present disclosure, the first control circuit controls, under the control of the first control signal, to connect or disconnect the first end of the second energy storage circuit and the second end of the second energy storage circuit, and the writing of the data voltage is divided by the first energy storage circuit and the second energy storage circuit, so that the dynamic range of the data voltage is expanded, which is advantageous for the design of a DAC (digital-to-analog converter) in a source driver and the uniformity of the output of the data line.

[0129] In at least one embodiment of the present disclosure, a control end of the first control circuit is electrically connected to the first control end, a first end of the first control circuit is electrically connected to a first end of the second energy storage circuit, and a second end of the first control circuit is electrically connected to a second end of the second energy storage circuit.

[0130] As shown in FIG. 16 , a pixel circuit according to at least one embodiment of the present disclosure may include a light emitting element E0, a driving circuit 11, a first energy storage circuit 12, a second energy storage circuit 13, and a first control circuit 15; A first end of the first energy storage circuit 12 is electrically connected to a control end of the driving circuit 11, a second end of the first energy storage circuit 12 is electrically connected to a first end of the driving circuit 11, a first end of the second energy storage circuit 13 is electrically connected to a control end of the driving circuit 11, and a second end of the second energy storage circuit 13 is electrically connected to a writing end DW, and the first energy storage circuit 12 and the second energy storage circuit 13 are used to store electrical energy; The first control circuit 15 is electrically connected to a first control end R0, a first end of the second energy storage circuit 13, and a second end of the second energy storage circuit 13, respectively, and is used to control the first end of the second energy storage circuit 13 to communicate or be cut off from the second end of the second energy storage circuit 13 under the control of a first control signal provided by the first control end R0; A second end of the driving circuit 11 is electrically connected to the light emitting element E0, and the driving circuit 11 is used to generate a driving current for driving the light emitting element E0 under the control of the potential of its control end.

[0131] During operation of at least one embodiment of the pixel circuit as shown in FIG. 16 of the present disclosure, the first control circuit 15 controls the first end of the second energy storage circuit 13 to communicate or be cut off from the second end of the second energy storage circuit 13 under the control of the first control signal, and the writing of the data voltage is divided by the first energy storage circuit 12 and the second energy storage circuit 13, so that the dynamic range of the data voltage is expanded, which is advantageous for the design of a DAC (digital-to-analog converter) in a source driver and the uniformity of the output of the data line.

[0132] In operation of at least one embodiment of the pixel circuit as shown in FIG. 16 of the present disclosure, a display cycle may include an initialization stage, a self-discharge stage, a data preparation stage, a potential control stage, a data writing stage and a light emitting stage, which are set in sequence; In the initialization stage, the first control circuit 15, under the control of the first control signal, controls the first end of the second energy storage circuit 13 to communicate with the second end of the second energy storage circuit 13, so that the second energy storage circuit 13 is reset; In the self-discharge stage and the data preparation stage, under the control of the first control signal, the first control circuit 15 controls the first end of the second energy storage circuit 13 to communicate with the second end of the second energy storage circuit 13, so that the charge stored in the second energy storage circuit 13 is cleared, thereby enabling the gate-source voltage of the drive transistor included in the drive circuit 11 to be controlled by the first energy storage circuit 12 to be maintained at the same level as in the self-discharge stage in the data preparation stage; In a potential control stage, the first control circuit 15 controls the first terminal of the second energy storage circuit 13 to be disconnected from the second terminal of the second energy storage circuit 13 under the control of the first control signal; In a data writing stage, the first control circuit 15 controls the first end of the second energy storage circuit 13 to be disconnected from the second end of the second energy storage circuit 13 under the control of the first control signal, the write control circuit 14 controls the first end of the first energy storage circuit 12 to be connected to the first end of the second energy storage circuit 13 under the control of the first write control signal, and the first energy storage circuit 12 and the second energy storage circuit 13 redistribute charges to change the gate-source voltage of the driving transistor; In the light-emitting stage, the first control circuit 15, under the control of the first control signal, controls the first end of the second energy storage circuit 13 to be connected to the second end of the second energy storage circuit 13, the write control circuit 14, under the control of the first write control signal, controls the first end of the first energy storage circuit 12 to be disconnected from the first end of the second energy storage circuit 13, and the driving transistor drives the light-emitting element to emit light.

[0133] In at least one embodiment of the present disclosure, the pixel circuit may further include a write control circuit, the write control circuit being provided between the first energy storage circuit and the second energy storage circuit; The control end of the write control circuit is electrically connected to a first write control end, the first end of the write control circuit is electrically connected to a first end of the first energy storage circuit, and the second end of the write control circuit is electrically connected to a first end of the second energy storage circuit, and the write control circuit is used to control the first end of the first energy storage circuit and the first end of the second energy storage circuit to be communicated or cut off under the control of a first write control signal provided by the first write control end.

[0134] During the operation of the pixel circuit according to at least one embodiment of the present disclosure, in the initialization stage, the self-discharge stage and the data writing stage, the write control circuit controls the first end of the first energy storage circuit to communicate with the first end of the second energy storage circuit under the control of the first write control signal; In the data preparation step, the potential control step and the light emitting step, the write control circuit controls the first end of the first energy storage circuit to be disconnected from the first end of the second energy storage circuit under the control of the first write control signal.

[0135] The pixel circuit according to at least one embodiment of the present disclosure further includes a second control circuit, The second control circuit is electrically connected to a second control end, a power supply voltage end and a first end of the driving circuit, respectively, and is used to control communication or disconnection between the power supply voltage end and the first end of the driving circuit under the control of a second control signal supplied by the second control end.

[0136] In a specific implementation, the second control circuit may control the communication or disconnection between the power supply voltage terminal and the first terminal of the driving circuit under the control of the second control signal, thereby controlling the self-discharge threshold compensation process of the driving transistor included in the driving circuit.

[0137] Optionally, the second end of the driving circuit is electrically connected to the first pole of the light-emitting element, and the second pole of the light-emitting element is electrically connected to a first voltage end; The power supply voltage terminal is used to supply a power supply voltage, and the first voltage terminal is used to supply a first voltage signal; The absolute value of the voltage value of the power supply voltage is smaller than the absolute value of the voltage value of the first voltage signal.

[0138] In at least one embodiment of the present disclosure, the voltage value range of the power supply voltage may be 1V or more and 3V or less, and the voltage value range of the first voltage signal may be -8V or more and -5V or less, but is not limited thereto.

[0139] The pixel circuit according to at least one embodiment of the present disclosure may further include a third control circuit, wherein the second end of the driving circuit is electrically connected to the first pole of the light-emitting element, and the second pole of the light-emitting element is electrically connected to a first voltage end; The third control circuit is electrically connected to a third control terminal, a third voltage terminal and a first pole of the light-emitting element, respectively, and is used to control, under the control of a third control signal supplied by the third control terminal, the third voltage signal supplied by the third voltage terminal to be written to the first pole of the light-emitting element.

[0140] In a specific implementation, the third control circuit is used to control the light-emitting element not to emit light by writing a third voltage signal supplied by a third voltage terminal to the first pole of the light-emitting element in a non-light-emitting stage under the control of a third control signal, so that the difference between the potential of the first pole of the light-emitting element and the potential of the second pole of the light-emitting element is smaller than the lighting voltage of the light-emitting element.

[0141] During operation of the pixel circuit according to at least one embodiment of the present disclosure, the third control circuit can reset the potential of the first electrode of the light-emitting element, and can also play a role of shunting current during the light-emitting stage, thereby improving the driving accuracy of the microcurrent of the silicon-based OLED (Organic Light-Emitting Diode).

[0142] Optionally, the pixel circuit according to at least one embodiment of the present disclosure may further include a reference voltage writing circuit; the reference voltage write circuit is electrically connected to a second write control end, a reference voltage end and a write node respectively, and is used to write the reference voltage provided by the reference voltage end to the write node under the control of a second write control signal provided by the second write control end to control the potential of the write node; The write node is electrically connected to a control end of the driving circuit, or the write node is electrically connected to a first end of the second energy storage circuit.

[0143] In at least one embodiment of the present disclosure, the pixel circuit may further include a resistor circuit; A first end of the resistor circuit is electrically connected to a second end of the driving circuit, and a second end of the resistor circuit is electrically connected to the first pole of the light-emitting element, so as to prevent a short circuit between the first pole of the light-emitting element and the second pole of the light-emitting element; The second pole of the light emitting device is electrically connected to a first voltage terminal.

[0144] Optionally, the first energy storage circuit includes a first capacitance and the second energy storage circuit includes a second capacitance; A first end of the first capacitance is electrically connected to a control end of the driving circuit and a first end of the write control circuit respectively, a second end of the first capacitance is electrically connected to the first end of the driving circuit, a first end of the second capacitance is electrically connected to the second end of the write control circuit, and a second end of the second capacitance is electrically connected to a write end; The capacitance value of the second capacitance is smaller than the capacitance value of the first capacitance.

[0145] In at least one embodiment of the present disclosure, since the first capacitance needs to control the potential of the driving transistor in the driving circuit within one frame time, the capacitance value of the first capacitance needs to be set large, and the capacitance value of the first capacitance is set to be larger than the capacitance value of the second capacitance.

[0146] Optionally, the write control circuitry includes a first transistor; A control pole of the first transistor is electrically connected to the first write control terminal, a first pole of the first transistor is electrically connected to a control terminal of the driving circuit, a second pole of the first transistor is electrically connected to a first terminal of the second energy storage circuit, and a back gate of the first transistor is electrically connected to a second voltage terminal.

[0147] Optionally, the first control circuit includes a second transistor; A control pole of the second transistor is electrically connected to the first control end, a first pole of the second transistor is electrically connected to a first end of the second energy storage circuit, a second pole of the second transistor is electrically connected to a second end of the second energy storage circuit, and a back gate of the second transistor is electrically connected to a second voltage end.

[0148] Optionally, the reference voltage writing circuit includes a third transistor; A control pole of the third transistor is electrically connected to the second write control terminal, a first pole of the third transistor is electrically connected to the reference voltage terminal, a second pole of the third transistor is electrically connected to the write node, and a back gate of the third transistor is electrically connected to a second voltage terminal.

[0149] Optionally, the second control circuit includes a fourth transistor and the drive circuit includes a drive transistor; a control electrode of the fourth transistor is electrically connected to the second control end, a first electrode of the fourth transistor is electrically connected to the power supply voltage end, a second electrode of the fourth transistor is electrically connected to the first end of the driving circuit, and a back gate of the fourth transistor is electrically connected to a second voltage end; The control pole of the driving transistor is the control end of the driving circuit, the first pole of the driving transistor is the first end of the driving circuit, the second pole of the driving transistor is the second end of the driving circuit, and the back gate of the driving transistor is electrically connected to a second voltage end.

[0150] Optionally, the third control circuit includes a fifth transistor; A control electrode of the fifth transistor is electrically connected to the third control terminal, a first electrode of the fifth transistor is electrically connected to the third voltage terminal, a second electrode of the fifth transistor is electrically connected to a first electrode of the light-emitting element, and a back gate of the fifth transistor is electrically connected to a fourth voltage terminal.

[0151] In at least one embodiment of the present disclosure, the fifth transistor may be an n-type transistor, and the fourth voltage terminal is a third voltage terminal; A deep n-well is provided between the back gate and the P-type base of the fifth transistor so as to isolate the back gate and the P-type base of the fifth transistor, and the back gate of the fifth transistor and a first electrode of the fifth transistor are both electrically connected to the reset voltage terminal.

[0152] Optionally, the pixel circuit according to at least one embodiment of the present disclosure may further include an n-well, and the doping concentration of the n-well is greater than the doping concentration of the deep n-well; The ratio of the thickness of the n-well to the thickness of the deep n-well is 0.4 to 0.6, but is not limited thereto.

[0153] For example, the thickness of the n-well may be 0.5 um, and the thickness of the deep n-well may be 1 um.

[0154] In a specific implementation, the pixel circuit described in at least one embodiment of the present disclosure may further include a p-well, and the ratio of the thickness of the p-well to the thickness of the deep n-well is greater than or equal to 0.4 and less than or equal to 0.6.

[0155] For example, the thickness of the p-well may be 0.5um and the thickness of the deep n-well may be 1um.

[0156] As shown in FIG. 17, in addition to at least one embodiment of the pixel circuit as shown in FIG. 16 of the present disclosure, the pixel circuit according to at least one embodiment of the present disclosure further includes a write control circuit 14, a second control circuit 10, a third control circuit 20 and a reference voltage write circuit 16; the first energy storage circuit 12 includes a first capacitance C1, the second energy storage circuit 13 includes a second capacitance C2, the write control circuit 14 includes a first transistor P1, the driving circuit 11 includes a driving transistor P0, the first control circuit 15 includes a second transistor P2, the second control circuit 10 includes a fourth transistor P4, the third control circuit 20 includes a fifth transistor M5, the reference voltage write circuit 16 includes a third transistor P3, and the light emitting element is an organic light emitting diode O1; A first end of the first capacitance C1 is electrically connected to the gate of the driving transistor P0, and a second end of the first capacitance C1 is electrically connected to the source of the driving transistor P0; A first end of the second capacitor C2 is electrically connected to the gate of the driving transistor P0; The gate of the first transistor P1 is electrically connected to the first write control end WS1, the source of the first transistor P1 is electrically connected to the write end DW, the drain of the first transistor P1 is electrically connected to the second end of the second capacitor C2, and the back gate of the first transistor P1 is electrically connected to a high voltage end, which is used to supply a high voltage VDD; The gate of the third transistor P3 is electrically connected to the second write control end WS2, the source of the third transistor P3 is electrically connected to the reference voltage end R2, the drain of the third transistor P3 is electrically connected to the gate of the driving transistor P0, the back gate of the third transistor P3 is electrically connected to the high voltage end, and the reference voltage end R2 is used to supply a reference voltage Vref; The gate of the fourth transistor P4 is electrically connected to the first control end DS, the source of the fourth transistor P4 is electrically connected to the power supply voltage end Vd, the drain of the fourth transistor P4 is electrically connected to the source of the driving transistor P0, the back gate of the fourth transistor P4 is electrically connected to the high voltage end, and the power supply voltage end Vd is used to supply a power supply voltage ELVDD; The gate of the fifth transistor M5 is electrically connected to the second control end AZ, the source of the fifth transistor M5 is electrically connected to the ground end G1, the drain of the fifth transistor M5 is electrically connected to the anode of the organic light emitting diode O1, and the back gate of the fifth transistor M5 is electrically connected to the high voltage end; A common electrode voltage Vcom is applied to the cathode of the organic light emitting diode O1.

[0157] In at least one embodiment of the pixel circuit shown in FIG. 17, the fourth voltage end is the high voltage end, the first voltage end is supplied with a common electrode voltage Vcom, and the third voltage end is the ground end G1.

[0158] In at least one embodiment of the present disclosure, ELVDD-Vref is 1.5V or more, and the value of ELVDD may range from 2V or more to 8V or less, but is not limited thereto.

[0159] In at least one embodiment of the pixel circuit shown in FIG. 17, all transistors are PMOS transistors, but are not limited to such.

[0160] In at least one embodiment of a pixel circuit as shown in FIG. 17 of the present disclosure, the drive transistor P0 is equivalent to a current source controlled by a gate voltage, thereby realizing direct control of the drive current flowing through O1 by the data voltage Vdata, and therefore at least one embodiment of a pixel circuit as shown in FIG. 17 of the present disclosure is a current-type pixel circuit.

[0161] In at least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure, the data voltage Vdata is divided by C1 and C2 and written to the gate of the driving transistor P0, thereby widening the dynamic range of the data voltage Vdata, which is advantageous for the design of a DAC (digital-to-analog converter) in a source driver and the uniformity of the output of the data line.

[0162] As shown in FIG. 18, during operation of at least one embodiment of a pixel circuit as shown in FIG. 17 of the present disclosure, a display cycle includes an initialization stage S1, a self-discharge stage S2, a data preparation stage S3, a data writing stage S5 and a light-emitting stage S6, which are set in sequence; In the initialization stage S1, WS1 supplies a low voltage signal, WS2 supplies a low voltage signal, DS supplies a low voltage signal, AZ supplies a low voltage signal, R2 supplies a reference voltage Vref, DW supplies a reference voltage Vref, P1M5 is turned on, P1 is turned off, P4 is turned on, P3 is turned on, the power supply voltage ELVDD is applied to the source of P0, the reference voltage Vref is applied to the gate of P0, and the drain of P0 is connected to the ground terminal G1, and ELVDD-Vref is greater than |Vth|, so that P0 can be turned on at the beginning of the self-discharge stage S2, where Vth is the threshold voltage of P0 when there is no backgate effect; In the self-discharge stage S2, AZ supplies a low voltage signal, WS1 supplies a low voltage signal, WS2 supplies a low voltage signal, DS supplies a high voltage signal, R2 supplies a reference voltage Vref, DW supplies a reference voltage Vref, M5 is turned on to connect the drain of P0 to the ground terminal G1, P3 is turned on to input the reference voltage Vref to the gate of P0, P1 is turned on, and P4 is turned off; At the start of the self-discharge stage S2, P0 is turned on and discharged through P0 and M5, thereby lowering the source potential Vs of P0. As Vs lowers, the backgate effect occurs, and |Vth_ef| becomes equal to a×(VDD−Vs)+|Vth|, where Vth_ef is the threshold voltage of P0 when there is no backgate effect, and a is the coefficient of the backgate effect. As Vs lowers, Vgs also becomes smaller at the same time. When |Vth_ef| increases and becomes equal to |Vgs|, P0 is turned off and the discharge is stopped. At this time, a×(VDD−Vs)+|Vth|=Vg−Vs.

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[0163] As can be seen from the above operation process, during operation of at least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure, in the light emitting stage, the gate-source voltage of the driving transistor P0 can compensate for the threshold voltage of the driving transistor P0, so that the light emitting current of the organic light emitting diode O1 is independent of the threshold voltage Vth, and the display uniformity is improved.

[0164] At least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure is a current-type pixel circuit using all PMOS transistors, and has a wider anode dynamic range than a current-type pixel circuit constructed using NMOS transistors under a comparable process platform, for the following reasons. In the case of a current-type pixel circuit constructed using NMOS transistors, when the anode voltage of the organic light-emitting diode O1 is set to a negative voltage, the negative voltage is input to the source or drain of the transistor in the pixel circuit, and if the transistor is an n-type transistor, the presence of a forward-biased diode between the back gate and source of the transistor causes a latch-up effect, causing the pixel circuit to operate abnormally. Therefore, a current-type pixel circuit using PMOS transistors has a wider anode dynamic range, and if all the transistors in the current-type pixel circuit are PMOS transistors, the potential of the anode of the organic light-emitting diode O1 may be a negative voltage.

[0165] At least one embodiment of a pixel circuit as shown in FIG. 17 of the present disclosure uses a current-type pixel driving method, and a driving transistor included in a driving circuit in at least one embodiment of a pixel circuit as shown in FIG. 17 of the present disclosure is a PMOS transistor, so that even if the anode of O1 and the cathode of O1 are shorted, no spot or line defect occurs due to the anode voltage of O1 being negative.

[0166] At least one embodiment of the pixel circuit as shown in FIG. 17 of the present disclosure can prevent the occurrence of the low gradation bright spot phenomenon caused by leakage from the N-type base of the first transistor P1 for transmitting a data voltage to the first capacitor C1 toward the drain of the first transistor P1, and the cause of this phenomenon is as follows. The transistors used in at least one embodiment of the pixel circuit as shown in FIG. 17 of the present disclosure are PMOS transistors. Therefore, even if current leaks from the N-type base of the first transistor P1 toward the drain of the first transistor P1 to the first capacitor C1 during a non-light-emitting stage, causing the potential of the gate of P0 to increase, the light emission brightness of the organic light-emitting diode is not increased and no bright spot is generated, because the drive transistor P0 is also a PMOS transistor.

[0167] In the related art, P0 is an NMOS transistor, and the higher the potential of the gate of P0, the brighter the organic light-emitting diode becomes, so that when light leaks from the drain of P1 to the first capacitor C1 during the non-emitting stage, the potential of the gate of P0 rises, increasing the luminance of the organic light-emitting diode and causing a bright spot. In view of this, at least one embodiment of the present disclosure sets the transistor to a PMOS transistor in order to solve the above problem.

[0168] At least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure is a current-type pixel circuit, which can compensate for the reduction in lifetime due to an increase in the internal resistance of the organic light-emitting diode O1, and in at least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure, a high voltage VDD is applied to the back gate of each transistor, but ELVDD is not applied, so that the n-well potential of the base of each transistor is isolated from ELVDD, and as a result, ELVDD can be flexibly set within a range smaller than VDD.

[0169] At least one embodiment of the pixel circuit as shown in Figure 17 of the present disclosure may be, but is not limited to, a current-type pixel circuit applied to a silicon-based OLED (organic light-emitting diode) microdisplay chip. At least one embodiment of the present disclosure overcomes the space restriction of MOS transistors due to design rules in pixel circuits in which PMOS transistors and NMOS transistors are mixed, based on a specific semiconductor process platform, by designing a pixel circuit using only PMOS transistors, and can effectively reduce the area of ​​the pixel and improve the PPI (Pixels Per Inch).

[0170] A display panel according to an embodiment of the present disclosure includes multiple rows and multiple columns of the pixel circuits described above.

[0171] In at least one embodiment of the present disclosure, the display panel may further include a plurality of columns of data lines; The writing ends of the pixel circuits located in the same column are electrically connected to the data lines of the same column, and the second energy storage circuit includes a second capacitance; The second capacitance may be a parasitic capacitance between the data line and a signal line provided in the same layer, so as to save layout space.

[0172] In at least one embodiment of the present disclosure, the display panel includes an effective display area and a peripheral area, the peripheral area is arranged to surround the effective display area, and the pixel circuit includes a first control circuit; The first control circuit and the second energy storage circuit are provided in the peripheral region, and components included in the pixel circuit other than the first control circuit and the second energy storage circuit are provided in the effective display region.

[0173] In a specific implementation, in order to facilitate the realization of a narrow frame, the first control circuit and the second energy storage circuit may be located in the peripheral region, and the pixel circuits of each column may share one of the first control circuits and one of the second energy storage circuits, and within the effective display area, one pixel circuit includes only one capacitance, which can effectively reduce the requirements for circuit processing.

[0174] In at least one embodiment of the present disclosure, the pixel circuits in one column included in the display panel share one of the first control circuits and one of the second energy storage circuits; the display panel includes M rows and N columns of pixel circuits, where M and N are integers greater than 1; The display panel includes N shared units, and the nth shared unit includes an nth first control circuit and an nth second energy storage circuit; In an effective display area of ​​the display panel, a pixel circuit in the mth row and the nth column includes a light emitting element in the mth row and the nth column, a driving circuit in the mth row and the mth column, a first energy storage circuit in the mth row and the nth column, a writing control circuit in the mth row and the nth column, and a first control circuit in the mth row and the nth column; The nth first control circuit is electrically connected to a first control end, a first end of the nth second energy storage circuit, and a second end of the nth second energy storage circuit, respectively, and is used to control the first end of the nth second energy storage circuit and the second end of the nth second energy storage circuit to communicate with each other or to be cut off under the control of a first control signal provided by the first control end; The write control circuit in the mth row and the nth column is electrically connected to a first write control end, a control end of the driving circuit in the mth row and the nth column, and a first end of the nth second energy storage circuit, respectively, and is used to control the control end of the driving circuit in the mth row and the nth column to communicate with or be cut off from the first end of the nth second energy storage circuit under the control of a write control signal provided by the first write control end; A second end of the nth second energy storage circuit is electrically connected to the nth writing end, and the nth second energy storage circuit is used to store electrical energy; n is a positive integer equal to or less than N, and m is a positive integer equal to or less than M.

[0175] As shown in FIG. 19, reference symbol A0 denotes an effective display area, and devices included in pixel circuits arranged in multiple rows and multiple columns, other than the second transistor P2 and the second capacitor C2, are provided within the effective display area A0. The second transistor P2 and the second capacitor C2 are provided outside the effective display area A0, and the second transistor P2 and the second capacitor C2 are provided below the effective display area A0, One second transistor P2 and one second capacitor C2 are shared by the pixel circuits in one column.

[0176] A driving method according to at least one embodiment of the present disclosure is applied to the pixel circuit described above, and the driving method includes: A write control circuit controls, under the control of a first write control signal, to connect or disconnect a first end of the first energy storage circuit and a first end of the second energy storage circuit; The drive circuit generates a drive current for driving the light emitting element under control of the potential of the control end.

[0177] In at least one embodiment of the present disclosure, a display cycle of the pixel circuit includes an initialization stage, a self-discharge stage, a data preparation stage, a potential control stage, a data writing stage, and a light emitting stage, which are set in sequence, and the driving method includes: In the initialization step, the self-discharge step and the data writing step, the write control circuit controls, under the control of the first write control signal, to communicate between a first end of a first energy storage circuit and a first end of a second energy storage circuit; During the data preparation step, the potential control step and the light emission step, the write control circuit controls, under control of the first write control signal, to disconnect the first end of the first energy storage circuit from the first end of the second energy storage circuit.

[0178] In at least one embodiment of the present disclosure, the pixel circuit further includes a first control circuit, and the driving method includes: In the initialization step, the self-discharge step, the data preparation step and the light-emitting step, the first control circuit controls, under the control of a first control signal, a first end of a second energy storage circuit and a second end of the second energy storage circuit to communicate with each other; During the potential control step and the data writing step, the first control circuit further includes controlling, under control of a first control signal, a first end of the second energy storage circuit to be disconnected from a second end of the second energy storage circuit.

[0179] A driving method according to at least one embodiment of the present disclosure is applied to the pixel circuit described above, and the driving method includes: A first control circuit controls, under the control of a first control signal, to establish or block communication between a first end of the second energy storage circuit and a second end of the second energy storage circuit; The drive circuit generates a drive current for driving the light emitting element under control of the potential of the control end.

[0180] In at least one embodiment of the present disclosure, a display cycle of the pixel circuit includes an initialization stage, a self-discharge stage, a data preparation stage, a potential control stage, a data writing stage, and a light emitting stage, which are set in sequence, and the driving method includes: In the initialization step, the self-discharge step, the data preparation step and the light-emitting step, the first control circuit controls, under the control of a first control signal, a first end of a second energy storage circuit and a second end of the second energy storage circuit to communicate with each other; In the potential control step and the data writing step, the first control circuit controls, under control of a first control signal, so that a first end of the second energy storage circuit and a second end of the second energy storage circuit are disconnected from each other.

[0181] In at least one embodiment of the present disclosure, the pixel circuit further includes a write control circuit, and the driving method includes: In the initialization step, the self-discharge step and the data writing step, the write control circuit controls, under the control of the first write control signal, to communicate between a first end of a first energy storage circuit and a first end of a second energy storage circuit; The method further includes, during the data preparation step, the potential control step and the light emission step, controlling the write control circuit to disconnect a first end of the first energy storage circuit and a first end of the second energy storage circuit under the control of the first write control signal.

[0182] A display device according to an embodiment of the present disclosure includes the above-mentioned display panel.

[0183] In at least one embodiment of the present disclosure, the display panel includes a first silicon substrate, and a pixel circuit and a gate driving circuit disposed on the first silicon substrate; The display device further includes a second silicon substrate and a display driver chip disposed on the second silicon substrate.

[0184] In a specific implementation, the area of ​​the first silicon substrate is larger than the area of ​​the second silicon substrate; The minimum width of a signal line included in the display panel is greater than the width of a signal line included in the display driver chip.

[0185] As shown in FIG. 20, the display panel includes a first silicon substrate 201, and a pixel circuit and a gate driving circuit 202 provided on the first silicon substrate 201. In FIG. 20, the symbol A0 is an effective display area, and the pixel circuit is provided in the effective display area. The display device further includes a second silicon substrate 203 and a display driver chip disposed on the second silicon substrate 203 .

[0186] As shown in FIG. 20, the display driving chip may include, but is not limited to, a display driving integrated circuit 301, a source driver 302, a timing controller 303, a data processor 304, an input / output interface 305, a signal receiver 306, and a bias voltage and reference voltage supply circuit 307.

[0187] In at least one embodiment of the present disclosure, the area of ​​the first silicon substrate is larger than the area of ​​the second silicon substrate; The minimum width of a signal line included in the display panel is greater than the width of a signal line included in the display driver chip.

[0188] In at least one embodiment of the present disclosure, the display panel and the display driving chip may be manufactured using different process recipes, for example, the display panel may be manufactured using a 100 nm process and the display driving chip may be manufactured using a 28 nm process so that the line width of the signal lines included in the display driving chip is smaller than the line width of the signal lines included in the display panel and the spacing between the signal lines included in the display driving chip is smaller than the spacing between the signal lines included in the display panel.

[0189] The display device according to the embodiment of the present disclosure may be any product or part having a display function, such as a mobile phone, a tablet PC, a television, a display, a notebook PC, a digital photo frame, or a navigator.

[0190] The above is a preferred embodiment of the present disclosure, and it should be noted that those skilled in the art may further make some improvements and modifications without departing from the principles described in the present disclosure, and these improvements and modifications should also be considered to be within the scope of protection of the present disclosure.

Claims

1. A pixel circuit including a light emitting device, a driving circuit, a first energy storage circuit, a second energy storage circuit, and a write control circuit, A first end of the first energy storage circuit is electrically connected to the control end of the driving circuit and the first end of the writing control circuit respectively, a second end of the first energy storage circuit is electrically connected to the first end of the driving circuit, a first end of the second energy storage circuit is electrically connected to the second end of the writing control circuit, and a second end of the second energy storage circuit is electrically connected to the writing end, the first energy storage circuit and the second energy storage circuit are used for storing electric energy; A control end of the write control circuit is electrically connected to a first write control end, and the write control circuit is used to control the first end of the first energy storage circuit and the first end of the second energy storage circuit to communicate or be cut off under the control of a first write control signal provided by the first write control end; A pixel circuit, wherein a second end of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is used to generate a driving current for driving the light-emitting element under the control of the potential of its control end.

2. a first control circuit; 2. The pixel circuit according to claim 1, wherein the first control circuit is electrically connected to a first control end, a first end of the second energy storage circuit, and a second end of the second energy storage circuit, respectively, and is used to control the first end of the second energy storage circuit and the second end of the second energy storage circuit to communicate with each other or to be cut off under the control of a first control signal provided by the first control end.

3. Further comprising a second control circuit; 3. The pixel circuit according to claim 1, wherein the second control circuit is electrically connected to a second control end, a power supply voltage end and a first end of the driving circuit, respectively, and is used to control communication or disconnection between the power supply voltage end and the first end of the driving circuit under the control of a second control signal supplied by the second control end.

4. The second end of the driving circuit is electrically connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is electrically connected to a first voltage end; The power supply voltage terminal is used to supply a power supply voltage, and the first voltage terminal is used to supply a first voltage signal; The pixel circuit according to claim 3 , wherein an absolute value of the voltage value of the power supply voltage is smaller than an absolute value of the voltage value of the first voltage signal.

5. The light emitting device further includes a third control circuit, the second end of the driving circuit is electrically connected to the first pole of the light emitting device, and the second pole of the light emitting device is electrically connected to a first voltage end; 3. The pixel circuit according to claim 1 or 2, wherein the third control circuit is electrically connected to a third control terminal, a third voltage terminal and a first pole of the light-emitting element, respectively, and is used to control, under the control of a third control signal supplied by the third control terminal, that the third voltage signal supplied by the third voltage terminal is written to the first pole of the light-emitting element.

6. a reference voltage write circuit; the reference voltage write circuit is electrically connected to a second write control end, a reference voltage end and a write node respectively, and is used to write the reference voltage provided by the reference voltage end to the write node under the control of a second write control signal provided by the second write control end; 3. The pixel circuit according to claim 1, wherein the write node is electrically connected to a control end of the driving circuit, or the write node is electrically connected to a first end of the second energy storage circuit.

7. Further comprising a resistor circuit; A first end of the resistor circuit is electrically connected to a second end of the driving circuit, and the second end of the resistor circuit is electrically connected to a first electrode of the light-emitting element; The pixel circuit according to claim 1 , wherein the second electrode of the light-emitting element is electrically connected to a first voltage terminal.

8. the first energy storage circuit includes a first capacitance, and the second energy storage circuit includes a second capacitance; A first end of the first capacitance is electrically connected to a control end of the driving circuit and a first end of the write control circuit respectively, a second end of the first capacitance is electrically connected to the first end of the driving circuit, a first end of the second capacitance is electrically connected to the second end of the write control circuit, and a second end of the second capacitance is electrically connected to a write end; The pixel circuit according to claim 1 , wherein a capacitance value of the second capacitance is smaller than a capacitance value of the first capacitance.

9. the write control circuit includes a first transistor; 3. The pixel circuit according to claim 1, wherein a control pole of the first transistor is electrically connected to the first write control terminal, a first pole of the first transistor is electrically connected to a control terminal of the driving circuit, a second pole of the first transistor is electrically connected to a first terminal of the second energy storage circuit, and a back gate of the first transistor is electrically connected to a second voltage terminal.

10. the first control circuit includes a second transistor; 3. The pixel circuit of claim 2, wherein a control pole of the second transistor is electrically connected to the first control end, a first pole of the second transistor is electrically connected to a first end of the second energy storage circuit, a second pole of the second transistor is electrically connected to a second end of the second energy storage circuit, and a back gate of the second transistor is electrically connected to a second voltage end.

11. the reference voltage write circuit includes a third transistor; 7. The pixel circuit of claim 6, wherein a control electrode of the third transistor is electrically connected to the second write control terminal, a first electrode of the third transistor is electrically connected to the reference voltage terminal, a second electrode of the third transistor is electrically connected to the write node, and a back gate of the third transistor is electrically connected to a second voltage terminal.

12. the second control circuit includes a fourth transistor; and the drive circuit includes a drive transistor; a control electrode of the fourth transistor is electrically connected to the second control end, a first electrode of the fourth transistor is electrically connected to the power supply voltage end, a second electrode of the fourth transistor is electrically connected to the first end of the driving circuit, and a back gate of the fourth transistor is electrically connected to a second voltage end; 4. The pixel circuit of claim 3, wherein a control pole of the driving transistor is a control end of the driving circuit, a first pole of the driving transistor is a first end of the driving circuit, a second pole of the driving transistor is a second end of the driving circuit, and a back gate of the driving transistor is electrically connected to a second voltage end.

13. the third control circuit includes a fifth transistor; 6. The pixel circuit of claim 5, wherein a control electrode of the fifth transistor is electrically connected to the third control terminal, a first electrode of the fifth transistor is electrically connected to the third voltage terminal, a second electrode of the fifth transistor is electrically connected to a first electrode of the light-emitting element, and a back gate of the fifth transistor is electrically connected to a fourth voltage terminal.

14. the fifth transistor is an n-type transistor, the fourth voltage end is a third voltage end, 14. The pixel circuit of claim 13, wherein a deep n-well is provided between a back gate and a P-type base of the fifth transistor so as to isolate the back gate and the P-type base of the fifth transistor, and the back gate of the fifth transistor and a first electrode of the fifth transistor are both electrically connected to the third voltage terminal.

15. further comprising an n-well and a p-well, the doping concentration of the n-well is greater than the doping concentration of the deep n-well; the ratio of the thickness of the n-well to the thickness of the deep n-well is 0.4 to 0.6, 15. The pixel circuit of claim 14, wherein a ratio of a thickness of said p-well to a thickness of said deep n-well is 0.4 to 0.

6.

16. A pixel circuit including a light emitting device, a driving circuit, a first energy storage circuit, a second energy storage circuit, and a first control circuit, A first end of the first energy storage circuit is electrically connected to a control end of the driving circuit, a second end of the first energy storage circuit is electrically connected to a first end of the driving circuit, a first end of the second energy storage circuit is electrically connected to a control end of the driving circuit, and a second end of the second energy storage circuit is electrically connected to a writing end, and the first energy storage circuit and the second energy storage circuit are used to store electrical energy; The first control circuit and the second energy storage circuit are connected in parallel with each other, and the first control circuit is used to control the first end of the second energy storage circuit and the second end of the second energy storage circuit to communicate with each other or to be cut off under the control of a first control signal provided by a first control end; A pixel circuit, wherein a second end of the driving circuit is electrically connected to the light-emitting element, and the driving circuit is used to generate a driving current for driving the light-emitting element under the control of the potential of its control end.

17. 17. The pixel circuit of claim 16, wherein a control end of the first control circuit is electrically connected to the first control end, a first end of the first control circuit is electrically connected to a first end of the second energy storage circuit, and a second end of the first control circuit is electrically connected to a second end of the second energy storage circuit.

18. The write control circuit is provided between the first energy storage circuit and the second energy storage circuit, 17. The pixel circuit according to claim 16, wherein a control end of the write control circuit is electrically connected to a first write control end, a first end of the write control circuit is electrically connected to a first end of the first energy storage circuit, and a second end of the write control circuit is electrically connected to a first end of the second energy storage circuit, and the write control circuit is used to control the first end of the first energy storage circuit and the first end of the second energy storage circuit to be communicated or cut off under the control of a first write control signal provided by the first write control end.

19. Further comprising a second control circuit; The pixel circuit according to any one of claims 16 to 18, wherein the second control circuit is electrically connected to a second control end, a power supply voltage end, and a first end of the driving circuit, respectively, and is used to control communication between the power supply voltage end and the first end of the driving circuit to be interrupted or connected under the control of a second control signal supplied by the second control end.

20. The second end of the driving circuit is electrically connected to the first electrode of the light-emitting element, and the second electrode of the light-emitting element is electrically connected to a first voltage end; The power supply voltage terminal is used to supply a power supply voltage, and the first voltage terminal is used to supply a first voltage signal; The pixel circuit of claim 19 , wherein an absolute value of the voltage value of the power supply voltage is less than an absolute value of the voltage value of the first voltage signal.

21. The light emitting device further includes a third control circuit, the second end of the driving circuit is electrically connected to the first pole of the light emitting device, and the second pole of the light emitting device is electrically connected to a first voltage end; The pixel circuit according to any one of claims 16 to 18, wherein the third control circuit is electrically connected to a third control terminal, a third voltage terminal and a first pole of the light-emitting element, respectively, and is used to control, under the control of a third control signal supplied by the third control terminal, that the third voltage signal supplied by the third voltage terminal is written to the first pole of the light-emitting element.

22. a reference voltage write circuit; the reference voltage write circuit is electrically connected to a second write control end, a reference voltage end and a write node respectively, and is used to write the reference voltage provided by the reference voltage end to the write node under the control of a second write control signal provided by the second write control end; 19. The pixel circuit of claim 16, wherein the write node is electrically connected to a control end of the driving circuit, or the write node is electrically connected to a first end of the second energy storage circuit.

23. Further comprising a resistor circuit; A first end of the resistor circuit is electrically connected to a second end of the driving circuit, and the second end of the resistor circuit is electrically connected to a first electrode of the light-emitting element; 19. The pixel circuit according to claim 16, wherein a second electrode of the light-emitting element is electrically connected to a first voltage terminal.

24. the first energy storage circuit includes a first capacitance, and the second energy storage circuit includes a second capacitance; A first end of the first capacitance is electrically connected to a control end of the driving circuit and a first end of the write control circuit respectively, a second end of the first capacitance is electrically connected to the first end of the driving circuit, a first end of the second capacitance is electrically connected to the second end of the write control circuit, and a second end of the second capacitance is electrically connected to a write end; 19. The pixel circuit according to claim 16, wherein a capacitance value of the second capacitance is smaller than a capacitance value of the first capacitance.

25. the write control circuit includes a first transistor; 19. The pixel circuit of claim 18, wherein a control pole of the first transistor is electrically connected to the first write control end, a first pole of the first transistor is electrically connected to a control end of the driving circuit, a second pole of the first transistor is electrically connected to a first end of the second energy storage circuit, and a back gate of the first transistor is electrically connected to a second voltage end.

26. the first control circuit includes a second transistor; 19. The pixel circuit of claim 16, wherein a control electrode of the second transistor is electrically connected to the first control end, a first electrode of the second transistor is electrically connected to a first end of the second energy storage circuit, a second electrode of the second transistor is electrically connected to a second end of the second energy storage circuit, and a back gate of the second transistor is electrically connected to a second voltage end.

27. the reference voltage write circuit includes a third transistor; 23. The pixel circuit of claim 22, wherein a control pole of the third transistor is electrically connected to the second write control terminal, a first pole of the third transistor is electrically connected to the reference voltage terminal, a second pole of the third transistor is electrically connected to the write node, and a back gate of the third transistor is electrically connected to a second voltage terminal.

28. the second control circuit includes a fourth transistor; and the drive circuit includes a drive transistor; a control electrode of the fourth transistor is electrically connected to the second control end, a first electrode of the fourth transistor is electrically connected to the power supply voltage end, a second electrode of the fourth transistor is electrically connected to the first end of the driving circuit, and a back gate of the fourth transistor is electrically connected to a second voltage end; 20. The pixel circuit of claim 19, wherein a control pole of the driving transistor is a control end of the driving circuit, a first pole of the driving transistor is a first end of the driving circuit, a second pole of the driving transistor is a second end of the driving circuit, and a back gate of the driving transistor is electrically connected to a second voltage end.

29. the third control circuit includes a fifth transistor; 22. The pixel circuit of claim 21, wherein a control electrode of the fifth transistor is electrically connected to the third control terminal, a first electrode of the fifth transistor is electrically connected to the third voltage terminal, a second electrode of the fifth transistor is electrically connected to a first electrode of the light-emitting element, and a back gate of the fifth transistor is electrically connected to a fourth voltage terminal.

30. the fifth transistor is an n-type transistor, the fourth voltage end is a third voltage end, 30. The pixel circuit of claim 29, wherein a deep n-well is provided between a back gate and a P-type base of the fifth transistor so as to isolate the back gate and the P-type base of the fifth transistor, and the back gate of the fifth transistor and a first electrode of the fifth transistor are both electrically connected to the third voltage terminal.

31. further comprising an n-well and a p-well, the doping concentration of the n-well is greater than the doping concentration of the deep n-well; the ratio of the thickness of the n-well to the thickness of the deep n-well is 0.4 to 0.6, 31. The pixel circuit of claim 30, wherein a ratio of a thickness of said p-well to a thickness of said deep n-well is 0.4 to 0.

6.

32. A display panel comprising a plurality of rows and a plurality of columns of pixel circuits according to any one of the preceding claims.

33. further comprising a plurality of columns of data lines; The writing ends of the pixel circuits located in the same column are electrically connected to the data lines of the same column, and the second energy storage circuit includes a second capacitance; 33. The display panel according to claim 32, wherein the second capacitance is a parasitic capacitance between the data line and a signal line provided in the same layer as the data line.

34. the display panel includes an effective display area and a peripheral area, the peripheral area is provided to surround the effective display area, and the pixel circuit includes a first control circuit; 33. The display panel of claim 32, wherein the first control circuit and the second energy storage circuit are provided in the peripheral region, and components included in the pixel circuit other than the first control circuit and the second energy storage circuit are provided in the effective display region.

35. a pixel circuit in one column included in the display panel shares one of the first control circuits and one of the second energy storage circuits; the display panel includes M rows and N columns of pixel circuits, where M and N are integers greater than 1; The display panel includes N shared units, and the nth shared unit includes an nth first control circuit and an nth second energy storage circuit; In an effective display area of ​​the display panel, a pixel circuit in the mth row and the nth column includes a light emitting element in the mth row and the nth column, a driving circuit in the mth row and the mth column, a first energy storage circuit in the mth row and the nth column, a writing control circuit in the mth row and the nth column, and a first control circuit in the mth row and the nth column; The nth first control circuit is electrically connected to a first control end, a first end of the nth second energy storage circuit, and a second end of the nth second energy storage circuit, respectively, and is used to control the first end of the nth second energy storage circuit and the second end of the nth second energy storage circuit to communicate with each other or to be cut off under the control of a first control signal provided by the first control end; The mth row, nth column write control circuit is electrically connected to a first write control end, a control end of the mth row, nth column drive circuit, and a first end of the nth second energy storage circuit, respectively, and is used to control the communication between the control end of the mth row, nth column drive circuit and the first end of the nth second energy storage circuit to be disconnected or connected to each other under the control of a write control signal provided by the first write control end; A second end of the nth second energy storage circuit is electrically connected to the nth writing end, and the nth second energy storage circuit is used to store electrical energy; 35. The display panel of claim 34, wherein n is a positive integer equal to or less than N, and m is a positive integer equal to or less than M.

36. A driving method for a pixel circuit according to any one of claims 1 to 15, comprising the steps of: A write control circuit controls, under the control of a first write control signal, to connect or disconnect a first end of the first energy storage circuit and a first end of the second energy storage circuit; The driving circuit generates a driving current for driving the light-emitting element under control of a potential at a control end of the driving circuit.

37. The display cycle of the pixel circuit includes an initialization step, a self-discharge step, a data preparation step, a potential control step, a data writing step, and a light emitting step, which are set in sequence, and the driving method includes: In the initialization step, the self-discharge step and the data writing step, the write control circuit controls, under the control of the first write control signal, to communicate between a first end of a first energy storage circuit and a first end of a second energy storage circuit; The driving method according to claim 36, further comprising: controlling, under the control of the first write control signal, the write control circuit to disconnect a first end of the first energy storage circuit from a first end of the second energy storage circuit during the data preparation step, the potential control step and the light emission step.

38. The pixel circuit further includes a first control circuit, and the driving method includes: In the initialization step, the self-discharge step, the data preparation step and the light-emitting step, the first control circuit controls, under the control of a first control signal, a first end of a second energy storage circuit and a second end of the second energy storage circuit to communicate with each other; The driving method of claim 37, further comprising: in the potential control step and the data writing step, the first control circuit, under control of a first control signal, controlling a first end of the second energy storage circuit to be disconnected from a second end of the second energy storage circuit.

39. A driving method applied to a pixel circuit according to any one of claims 16 to 35, the driving method comprising: A first control circuit controls, under the control of a first control signal, to establish or block communication between a first end of the second energy storage circuit and a second end of the second energy storage circuit; The driving circuit generates a driving current for driving the light-emitting element under control of a potential at a control end of the driving circuit.

40. The display cycle of the pixel circuit includes an initialization step, a self-discharge step, a data preparation step, a potential control step, a data writing step, and a light emitting step, which are set in sequence, and the driving method includes: In the initialization step, the self-discharge step, the data preparation step and the light-emitting step, the first control circuit controls, under the control of a first control signal, a first end of a second energy storage circuit and a second end of the second energy storage circuit to communicate with each other; The driving method of claim 39, further comprising: in the potential control step and the data writing step, controlling the first control circuit to disconnect between the first end of the second energy storage circuit and the second end of the second energy storage circuit under the control of a first control signal.

41. The pixel circuit further includes a write control circuit, and the driving method includes: In the initialization step, the self-discharge step and the data writing step, the write control circuit controls, under the control of the first write control signal, to communicate between a first end of a first energy storage circuit and a first end of a second energy storage circuit; The driving method of claim 40, further comprising: in the data preparation step, the potential control step and the light emission step, the write control circuit controls, under the control of the first write control signal, to cut off a first end of the first energy storage circuit and a first end of the second energy storage circuit.

42. A display device comprising the display panel according to any one of claims 32 to 35.

43. The display panel includes a first silicon substrate, and a pixel circuit and a gate driving circuit disposed on the first silicon substrate; 43. The display device according to claim 42, wherein the display device includes a second silicon substrate and a display driver chip disposed on the second silicon substrate.

44. The area of ​​the first silicon substrate is larger than the area of ​​the second silicon substrate; 44. The display device according to claim 43, wherein a minimum width of a signal line included in said display panel is greater than a width of a signal line included in said display driver chip.

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