Method for determining a failure event on a lithography system and associated failure detection module - Patents.com

Abstract

A method for determining a failure event on a lithography system is disclosed, the method comprising decomposing at least one signal generated within the lithography system into a plurality of component signals, each component signal associated with a different respective frequency range, evaluating at least one of the component signals with respect to a nominal lithography system behavior, and identifying a deviation of at least one of the component signals from the nominal lithography system behavior as a failure event.

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims priority to European Application 22176549.8, filed May 31, 2022, which is incorporated herein by reference in its entirety.

[0002] [Technical field] The present invention relates to methods and apparatus usable, for example, in the manufacture of devices by lithographic techniques, and to methods of manufacturing devices using lithographic techniques, and more particularly to failure detection for such devices. [Background technology]

[0003] A lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate. Lithographic apparatus may be used, for example, in the manufacture of integrated circuits (ICs). In this case, a patterning device, also referred to as a mask or reticle, may be used to generate the circuit pattern to be formed on an individual layer of the IC. This pattern may be transferred onto a target portion (e.g. comprising part of, a die, or several dies) on the substrate (e.g. a silicon wafer). Transfer of the pattern is typically via imaging onto a layer of radiation-sensitive material (resist) provided on the substrate. In general, a single substrate will contain a network of adjacent target portions that are successively patterned. These target portions are commonly referred to as "fields".

[0004] In the manufacture of complex devices, typically many lithographic patterning steps are performed to form functional features in successive layers on a substrate. For this reason, an important aspect of the performance of a lithographic apparatus is the ability to accurately and precisely position an applied pattern relative to features deposited in a previous layer (by the same apparatus or a different lithographic apparatus). For this purpose, one or more sets of alignment marks are provided on the substrate. Each mark is a structure whose position can be measured later using a position sensor, typically an optical position sensor. The lithographic apparatus includes one or more alignment sensors that can accurately measure the position of the marks on the substrate. Different types of marks and different types of alignment sensors are known from different manufacturers and different products of the same manufacturer.

[0005] In other applications, metrology sensors are used to measure exposed structures on the substrate (in resist and / or after etching). A fast and non-invasive form of specialized inspection tool is the scatterometer, where a beam of radiation is directed onto a target on the surface of the substrate and properties of the scattered or reflected beam are measured. Examples of known scatterometers include angle resolved scatterometers of the type described in US2006033921A1 and US2010201963A1. In addition to measuring feature shapes by reconstruction, diffraction based overlay can be measured using such an apparatus, as described in published patent application US2006066855A1. Diffraction based overlay metrology using dark field imaging of the diffraction orders allows overlay measurements for smaller targets. Examples of dark field imaging metrology can be found in International Patent Applications WO2009 / 078708 and WO2009 / 106279, which are incorporated herein by reference in their entirety. Further developments in the technology are described in published patent applications US20110027704A, US20110043791A, US2011102753A1, US20120044470A, US20120123581A, US20130258310A, US20130271740A, and WO2013178422A1. These targets may be smaller than the illumination spot and may be surrounded by the product structures on the wafer. Using a composite grating target, multiple gratings may be measured in one image. The contents of all of these applications are also incorporated herein by reference. Summary of the Invention [Problem to be solved by the invention]

[0006] When a defect occurs in a lithography system, it is important to identify the cause of the defect as soon as possible. Traditionally, this is achieved by attempting to reproduce the problem. The trigger for defect detection is based on time domain signals.

[0007] Improved methods for detecting such failure events are desirable. [Means for solving the problem]

[0008] The invention in a first aspect provides a method for determining a failure event on a lithography system, the method comprising decomposing at least one signal generated within the lithography system into a plurality of component signals, each component signal associated with a different respective frequency range, evaluating at least one of the component signals with respect to a nominal lithography system behavior, and identifying a deviation of the at least one of the component signals from the nominal lithography system behavior as a failure event.

[0009] In a second aspect, the invention provides a signal deviation detection block capable of determining a failure event on a lithography system, the block comprising one or more filters capable of decomposing a signal generated in the lithography system into a plurality of component signals, each component signal associated with a different respective frequency range, and a processor capable of evaluating at least one of the component signals with respect to a nominal lithography system behavior and capable of identifying a deviation of at least one of the component signals from the nominal lithography system behavior as a failure event.

[0010] A computer program capable of carrying out the method of the first aspect is also disclosed.

[0011] These and other aspects of the invention will be understood from a consideration of the examples described below. [Brief description of the drawings]

[0012] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings in which: FIG. 1 depicts a lithographic apparatus. FIG. 2 illustrates diagrammatically the measurement and exposure process in the apparatus of FIG. FIG. 3 is a schematic diagram of a defect detection system including multiple defect detection modules according to one embodiment. FIG. 4 is a schematic diagram of a signal deviation detection block of the defect detection module according to the first embodiment. 5(a), 5(b), 5(c) and 5(d) form schematic diagrams of the signal decomposition block of the signal deviation detection block according to different embodiments. FIG. 6 is a schematic diagram of a signal deviation detection block of a defect detection module according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Before describing embodiments of the present invention in detail, an example of an environment in which embodiments of the present invention may be implemented is presented for reference.

[0014] Fig. 1 shows a schematic representation of a lithographic apparatus LA. The apparatus comprises an illumination system (illuminator) IL configured to condition a radiation beam B (e.g. UV or DUV radiation), a patterning device support or support structure (e.g. mask table) MT configured to support a patterning device (e.g. mask) MA and connected to a first positioner PM configured to accurately position the patterning device according to certain parameters, two substrate tables (e.g. wafer tables) WTa and WTb each configured to hold a substrate (e.g. resist-coated wafer) W and each connected to a second positioner PW configured to accurately position the substrate according to certain parameters, and a projection system (e.g. refractive projection lens system) PS configured to project a pattern formed in the radiation beam B by the patterning device MA onto a target portion C (e.g. comprising one or more dies) of the substrate W. A reference frame RF connects the various components and serves as a reference for setting and measuring the positions of the patterning device and the substrate, as well as the positions of features thereon.

[0015] Illumination systems may include various types of optical components, such as refractive, reflective, magnetic, electromagnetic, electrostatic or other types of optical components, or any combination thereof, for directing, shaping or controlling radiation.

[0016] The patterning device support MT holds the patterning device in a manner that depends on the orientation of the patterning device, the design of the lithographic apparatus, and other conditions, such as whether or not the patterning device is held in a vacuum environment. The patterning device support can use mechanical, vacuum, electrostatic or other clamping techniques to hold the patterning device. The patterning device support MT may be a frame or a table, for example, which may be fixed or movable as required. The patterning device support may ensure that the patterning device is at a desired position relative to the projection system etc.

[0017] The term "patterning device" as used herein should be broadly interpreted as referring to any device that can be used to generate a pattern in the cross-section of a radiation beam, for example to generate a pattern in a target portion of a substrate. It should be noted that the pattern generated in the radiation beam may not exactly correspond to the desired pattern in the target portion of the substrate, for example if the pattern includes phase-shifting features or so called assist features. Generally, the pattern generated in the radiation beam will correspond to a particular functional layer in a device being created in the target portion, such as an integrated circuit.

[0018] As here depicted, the apparatus is of a transmissive type (e.g. employing a transmissive patterning device). Alternatively, the apparatus may be of a reflective type (e.g. employing a programmable mirror array of the type described above, or a reflective mask). Examples of patterning devices include masks, programmable mirror arrays, and programmable LCD panels. Any use of the terms "reticle" or "mask" herein may be construed as synonymous with the more general term "patterning device." The term "patterning device" may also be interpreted as referring to a device that stores pattern information in digital form for use in controlling such a programmable patterning device.

[0019] The term "projection system" as used herein should be interpreted broadly to encompass any type of projection system, including refractive, reflective, catadioptric, magnetic, electromagnetic and electrostatic optical systems, or any combination thereof, appropriate for the exposure radiation used, or other factors such as the use of an immersion liquid or the use of a vacuum. Use of the term "projection lens" herein may be interpreted as synonymous with the more general term "projection system".

[0020] The lithographic apparatus may be of a type in which at least a part of the substrate may be covered by a liquid having a relatively high refractive index, such as water, to fill a space between the projection system and the substrate. Immersion liquids may also be applied to other spaces in the lithographic apparatus, for example between the mask and the projection system. Immersion techniques are well known techniques for increasing the numerical aperture of projection systems.

[0021] In operation, the illuminator IL receives a radiation beam from a radiation source SO. The source and the lithographic apparatus may be separate entities, for example when the source is an excimer laser. In such cases, the source is not to be construed as forming part of the lithographic apparatus, and the radiation beam is passed from the source SO to the illuminator IL by a beam delivery system BD, which may include, for example, suitable directing mirrors and / or beam expanders. In other cases, for example when the source is a mercury lamp, the source may be part of the lithographic apparatus. The source SO and the illuminator IL, together with the beam delivery system BD if required, may be referred to as a radiation system.

[0022] The illuminator IL may include, for example, an adjuster AD for adjusting the angular intensity distribution of the radiation beam, an integrator IN, and a condenser CO. The illuminator may be used to adjust the radiation beam so that it has a desired uniformity and intensity distribution in its cross-section.

[0023] The radiation beam B is incident on the patterning device MA, which is held on the patterning device support MT, and is patterned by the patterning device. Having passed through the patterning device (e.g. mask) MA, the radiation beam B passes through a projection system PS which focuses the beam on a target portion C of the substrate W. By means of the second positioner PW and a position sensor IF (e.g. an interferometer device, a linear encoder, a two-dimensional encoder or a capacitive sensor), the substrate table WTa or WTb can be accurately driven (e.g. to position different target portions C on the path of the radiation beam B). Similarly, the first positioner PM and other position sensors (not explicitly shown in FIG. 1 ) can be used to accurately position the patterning device (e.g. mask) MA with respect to the path of the radiation beam B (e.g. after mechanical retrieval from a mask library or during a scan).

[0024] The patterning device (e.g. mask) MA and substrate W may be aligned using mask alignment marks M1, M2 and substrate alignment marks P1, P2. Although the substrate alignment marks in the illustrated example occupy dedicated target portions, they may be located in spaces between the target portions (known as scribe-lane alignment marks). Similarly, in situations in which more than one die is provided on the patterning device (e.g. mask) MA, the mask alignment marks may be located between the dies. Small alignment marks may also be included among device features within a die. In this case it is desirable for the markers to be as small as possible and not require different imaging or process conditions than nearby features. Alignment systems for detecting alignment markers are described further below.

[0025] The depicted apparatus can be used in various modes. In scan mode, the patterning device support (e.g. mask table) MT and the substrate table WT are scanned simultaneously while a pattern formed in the radiation beam is projected onto a target portion C (i.e. a single dynamic exposure). The speed and direction of the substrate table WT relative to the patterning device support (e.g. mask table) MT may be determined by the magnification and image reversal characteristics of the projection system PS. In scan mode, the maximum size of the exposure field limits the width (in non-scanning direction) of the target portion in a single dynamic exposure, while the length of the scanning motion determines the height (in scanning direction) of the target portion. As is known, other types of lithographic apparatus and operation modes are also possible. A step mode is known for example. In so-called "maskless" lithography, a programmable patterning device is held stationary but the substrate table WT is driven or scanned with a changing pattern.

[0026] Combinations and / or variations on the above described modes of use or entirely different modes of use may also be employed.

[0027] The lithographic apparatus LA is of the so-called dual stage type, having two substrate tables WTa, WTb and two stations, namely an exposure station EXP and a measurement station MEA between which the substrate tables can be exchanged. While one substrate on one substrate table is being exposed in the exposure station, the other substrate is loaded on the other substrate table in the measurement station and various preparation steps can be performed. This allows a significant increase in the throughput of the apparatus. The preparation steps may include mapping the surface height profile of the substrate using the level sensor LS and measuring the position of an alignment marker on the substrate using the alignment sensor AS. If the position sensor IF is not able to measure the position of the substrate table while in the measurement station or the exposure station, a second position sensor may be provided in both stations to enable tracking the position of the substrate table relative to the reference frame RF. Other known arrangements can also be used instead of the dual stage arrangement shown. For example, other lithographic apparatuses are known in which a substrate table and a measurement table are provided. These are docked together when performing the preparation measurements and are undocked when the substrate table is exposed.

[0028] Figure 2 illustrates the steps for exposing a target portion (e.g. a die) on a substrate W in the dual stage apparatus of Figure 1. Inside the dashed box on the left are steps performed in the measurement station MEA, and on the right are steps performed in the exposure station EXP. As mentioned before, in operation, one of the substrate tables WTa, WTb is in the exposure station and the other is in the measurement station. For the purposes of this description, it is assumed that a substrate W is already loaded in the exposure station. In step 200, a new substrate W' is loaded into the apparatus by a mechanism not shown. These two substrates are processed in parallel to increase the throughput of the lithographic apparatus.

[0029] First, the newly loaded substrate W' may be a previously unprocessed substrate prepared with new photoresist for the first exposure in the tool. However, in general, the lithography process described is only one step in a series of exposure and processing steps, and the substrate W' may have already been through this and / or other lithography tools multiple times or may have undergone subsequent processing. In particular, for the task of improving overlay performance, the task is to ensure that the new pattern is applied at the correct location on a substrate that has already been through one or more cycles of patterning and processing. These processing steps progressively introduce distortions into the substrate that must be measured and corrected to achieve sufficient overlay performance.

[0030] The previous and / or subsequent patterning steps may be performed in other lithographic apparatus, as previously described, or in different types of lithographic apparatus. For example, some layers in a device manufacturing process that have very high demands on parameters such as resolution and overlay may be processed in more advanced lithography tools than other layers that have relatively lower demands. Thus, some layers may be exposed in an immersion type lithography tool and other layers in a "dry" tool. Some layers may be exposed in a tool operating at DUV wavelengths and other layers may be exposed using EUV wavelength radiation.

[0031] At 202, alignment measurements using substrate marks P1 etc. and an image sensor (not shown) are used to measure and record the alignment of the substrate relative to the substrate tables WTa / WTb. In addition, several alignment marks across the substrate W' are measured using alignment sensor AS. These measurements are used in one embodiment to establish a "wafer grid" that very accurately maps the distribution of marks across the substrate, including distortions relative to a reference rectangular grid.

[0032] In step 204, a map of wafer height (Z) versus XY position is measured using a level sensor LS as well. Typically, the height map is only used to achieve accurate focusing of the exposure pattern. It may also be used for other additional purposes.

[0033] When the substrate W' is loaded, recipe data 206 are received that define the characteristics of the wafer, the previously formed patterns, the patterns to be formed thereon, as well as the exposure to be performed. To these recipe data, measurements of the wafer position, the wafer grid and the height map obtained at 202, 204 can be added and a complete set of recipe and measurement data 208 can be passed to the exposure station EXP. The alignment data measurements include, for example, the X and Y positions of the alignment targets that are formed in a fixed or nominally fixed relationship to the product pattern that is the product of the lithography process. These alignment data, acquired immediately before exposure, are used to generate an alignment model with parameters that fit the model to the data. These parameters and the alignment model are used during the exposure operation to correct the position of the pattern applied in the current lithography step. The model in use interpolates the position deviations between the measured positions. Conventional alignment models may comprise four, five or six parameters that together define the translation, rotation and scaling of an "ideal" grid in different dimensions. Advanced models using more parameters are also known.

[0034] In 210, the wafers W' and W are swapped and the measured substrate W' becomes the substrate W and enters the exposure station EXP. In the example apparatus of FIG. 1, this is performed by exchanging the supports WTa and WTb in the apparatus, and the relative alignment between the substrate tables and the substrates themselves is maintained because the substrates W, W' remain held in the correct position on their respective supports. Thus, once the tables have been swapped, the measurement information 202, 204 can be used for the substrate W (formerly W') in controlling the exposure step, simply by determining the relative position between the projection system PS and the substrate table WTb (formerly WTa). In step 212, reticle alignment is performed using the mask alignment marks M1, M2. In steps 214, 216, 218, scanning movements and radiation pulses are applied at successive target positions across the substrate W to complete the exposure of multiple patterns.

[0035] By using the alignment data and height maps acquired by the metrology station during the exposure steps, these patterns are precisely aligned, specifically to their desired locations relative to previously placed features on the same substrate. The exposed substrate, labeled W", is removed from the apparatus in step 220 and etched or otherwise processed according to the exposed pattern.

[0036] Those skilled in the art will appreciate that the above description is a simplified overview of many very detailed steps that may be performed in one example of an actual manufacturing environment. For example, rather than measuring alignment in a single pass, there are often separate phases of coarse and fine measurements, using the same or different marks. The coarse and / or fine alignment measurement steps may be performed before or after, or in between, the height measurements.

[0037] In lithography systems, a key challenge that has a large impact on system uptime is the ability to quickly and efficiently detect and / or diagnose events or trends (e.g., defect events) that may indicate irregular or abnormal behavior. However, such systems are highly complex, with many different modules (e.g., including projection optics modules, wafer stage modules, reticle stage modules, reticle masking modules, among others), each generating large amounts of data. Complex challenges involving multiple modules are particularly challenging to diagnose due to a lack of data about failure events. Full context information (e.g., traces from all modules) at the moment of the defect is typically not available.

[0038] To address this, one current approach is to try to recreate the issue (failure event) to gather context information for diagnosis. This is very time consuming and results in long downtime, especially for intermittent (non-reproducible) issues. In addition, cross-module failure event triggers are not available. Even when recreating an issue, only single module information can be collected.

[0039] Furthermore, in current diagnostic methods, triggers for fault event detection are based on time domain signals. Triggers are typically generated when a particular signal crosses a predefined threshold. This is typically time domain anomaly detection based on sensor signal amplitude. Therefore, many faults that excite a particular frequency band are not caught. This can lead to a long time spent finding the root cause or failure to identify the root cause.

[0040] To address one or more of these challenges, a method is proposed for determining a failure event on a lithography system, the method comprising the steps of decomposing a signal generated in the lithography system into a plurality of component signals, each component signal associated with a different respective frequency range, evaluating each of the component signals with respect to a nominal lithography system behavior (e.g., comparing each of the component signals to an indicator of the nominal lithography system behavior), and identifying a deviation of at least one of the component signals from the nominal lithography system behavior as a failure event. The indicator may be, for example, a threshold value for the component signal or a reference signal.

[0041] 3 is a high-level diagram of a proposed defect event trigger architecture according to one embodiment. 1 ~MOD k Each defect detection module FD 1 ~FD k A lithography system module MOD is provided. 1 , and its defect detection module FD 1 is shown in more detail than the other modules. Each system module may generate a number of measurable signals. For example, the first lithography system module MOD 1 is the number of n measurable signals V 1 ~V n (Each lithography system module MOD 1 ~MOD k In one embodiment, each defect detection module FD 1 ~FD k However, each lithography system module MOD 1 ~MOD k In the illustrated example, the lithography system module MOD 1Each of the m signals of the small subset of n signals generated by 1 ~SDD m The subset of signals monitored (e.g., m) may comprise less than 30%, less than 10%, less than 5%, less than 2%, or less than 1% of the signals generated (e.g., n), and / or the number of signals monitored may be any suitable subset of the signals generated.

[0042] The subset of signals to be monitored may be selected for each module, for example, according to user or domain knowledge of the signals that are most important to the system dynamics for a particular module. Alternatively or additionally, the signals to be monitored may be selected based on a particular system state. For example, the monitoring described herein may be performed primarily or only during a particular predetermined system state. Signals that are important for an exposure state (e.g., when the system is performing an exposure) may be different from signals that are important for a "transmission image sensor (TIS) scan" state (where an aerial image of the projected (TIS) reticle mark is measured). Thus, the signals to be monitored may be selected based on the system state (those skilled in the art will recognize that there are more system states than the two particular examples provided herein). In this manner, the signals monitored by each defect detection module may be configurable, for example, based on a particular state or action being performed by the system.

[0043] Each signal deviation detection block SDD 1 ~SDD mmay comprise one or more suitable filters to define a plurality of component signals from the signal monitored by the signal deviation detection block, each component signal being associated with a respective frequency range or frequency bin. In this way, the monitoring of each monitored signal may be performed within a frequency bin. For example, if a deviation is detected within one or more frequency bins, an event trigger signal may be generated. Deviations may be detected by comparing a parameter of a signal component (e.g., signal energy) with a respective threshold value for the signal component. In this way, complex frequency analysis may be performed without complex computational implementation.

[0044] Signal deviation detection block SDD 1 ~SDD m The respective outputs of the signal deviation detection blocks are combined, for example via appropriate logical operators, into a single output. For example, one (or more) of the signal deviation detection blocks may be connected to the trigger TG SDD When generating a defect event trigger TG FD OR gates may be used to gate these outputs such that an OR is generated by the defect detection module. Using OR gates is just one example and other logic operations are possible. For example, two (or more) particular signal deviation detection blocks may be AND gated as appropriate for the respective signals. The output of the AND gate may then be OR gated (or otherwise combined) with the output of the other signal deviation detection block. This is just one particular example and one skilled in the art will recognize that any type, number and combination of logic operations may be used.

[0045] Similarly, the output of the fault detection modules is connected to an appropriate logic gate (e.g., if one of the fault detection modules detects a fault, the FD trigger TG FD If a system fault event trigger signal TG SY may be combined with an OR gate or a combination of logic operations / gates to generate

[0046] 4 is a schematic example of a signal deviation detection block according to an embodiment. At a high level, the signal deviation detection block may comprise a signal decomposition block SD, a signal comparison block SC and a logic block or health check logic block HCL.

[0047] The signal decomposition block SD divides the input signal S into several signal components S, each associated with a different frequency range or frequency bin. d1 ~S dp More specifically, an input time-domain signal S(t) is decomposed into multiple time-domain signals S(t) using a filter bank. i (t) (i = 1, , p). Each signal S i (t) (i=1, . . . , p) comprises information from the original signal S(t) in a particular frequency range. i (t) (i=1,...,p) may be obtained via a through path to monitor the complete input signal S(t).

[0048] The signal comparison block compares each signal component S d1 ~S dp , respectively, are compared to respective indicators, such as thresholds or references, of nominal lithography system behavior to determine whether the signal components (and, optionally, the complete signal) are within specification. c1 ~S cp is each signal component S d1 ~S dp is output to

[0049] The health check logic block checks the output signal S c1 ~S cp At least one of the signal components S d1 ~S dp Triggers when at least one of the following is out of specification: SDD To generate the comparison output signal S c1 ~S cpare combined according to one or more logical operations. As previously described, the logical operations may comprise a single logic gate, such as a single OR gate, or a more complex combination of logic gates.

[0050] Figure 5 shows four examples of a signal decomposition block SD that can be used in a signal deviation detection block as illustrated in Figure 4. Figure 5(a) shows an example of a signal decomposition block that uses a high-pass filter HPF and a low-pass filter LPF to obtain three signal components: a high-frequency component covering a higher frequency range of the input signal S(t) obtained directly by applying a high-pass filter HPF to the input signal, a low-frequency component covering a lower frequency range of the input signal S(t) obtained directly by applying a low-pass filter LPF to the input signal S(t), and a mid-frequency component covering a mid-frequency range obtained by removing the high- and low-frequency components of the input signal from the input signal S(t). Thus, three frequency bins are defined for signal monitoring. As mentioned before, an optional through-path is provided to monitor the complete input signal S(t).

[0051] Figure 5(b) shows a second example of a signal decomposition block and an example of a filter bank for implementing such a signal decomposition block. For some applications, it is necessary to define frequency ranges of variable length depending on the nature of the impairments or system behavior. The configuration shown here consists of one or more band-pass filters BPF 1 ~BPF p-1 to provide flexibility for defining such different frequency ranges. These bandpass filters may be implemented in combination with a lowpass filter LPF and a highpass filter HPF to define the highest and lowest frequency ranges and, if necessary, through passes as described above.

[0052] For time-invariant signals (e.g., S(t)=A sin(ωt+φ), where A is the amplitude, ω is 2πf, and φ is the phase), frequency domain analysis using Fast Fourier Transform (FFT) analysis is sufficient. In such cases, for time-invariant signals, the signal decomposition block in Figure 5(b) can generate the required triggers.

[0053] However, for time-varying signals (e.g., S(t)=Asin(ω(t)*t+φ): frequency constants change as a function of time), the signal decomposition block of FIG. 5(b) is insufficient. In this scenario, the examples shown in FIG. 5(c) and 5(d) or their variations may be used instead. This is similar to generating triggers based on wavelet coefficients. In FIG. 5(c), at each layer, the low-pass signal from the previous layer (or the input signal to the first layer) is split into two signals using a high-pass filter HPF and a low-pass filter LPF. The resulting frequency bin ranges (Fs is the sampling frequency) are shown in this figure. FIG. 5(d) shows an arrangement where each layer doubles the number of signal components, using a high-pass filter HPF and a low-pass filter LPF for each component of the previous layer. Of course, fewer or more layers than those shown in these figures may be used.

[0054] It will be appreciated that if a particular defect is better monitored at a particular frequency, this can be accomplished by using an appropriate configuration such as the Goertzel algorithm or a tuned bandpass filter (e.g., in combination with any of the examples disclosed herein and / or within the scope of the present disclosure).

[0055] Application of the filters may be accomplished in real time to allow for in-line diagnostics.

[0056] 6 is a specific implementation of a signal deviation detection block according to one embodiment. It shows a specific implementation of each of a signal decomposition block SD (e.g., as shown in FIG. 5(a)), a signal comparison block SC, and a health check logic block HCL. The specific implementation as shown here of each of these blocks may be implemented with different specific implementations of the blocks as disclosed herein and / or within the scope of the present disclosure. Thus, for example, the specific signal decomposition block SD shown here may be implemented with different instances of a signal comparison block and / or a health check logic block HCL, and the specific signal comparison block SC shown here may be implemented with different instances of a signal decomposition block SD and / or a health check logic block HCL.

[0057] In the signal comparison block SC, a monitoring metric calculation block ENG may be used to calculate a specific monitoring parameter for each signal component. For example, the monitoring parameter may be the signal energy E L , E M , E H , E T These energy values ​​E L , E M , E H , E T Each of these is, for example, an energy reference value Ref (for example, E iN,ref ) each reference value B L , B M , B H , B T may be compared with

[0058] More generally, the signal comparison block SC can be used to evaluate whether the decomposed signal Si(t) (i=1,...,p) has deviated with respect to a reference for nominal or healthy behavior (or a subset of the components of the decomposed signal).

[0059] The energy of the decomposed signal E iNis the signal S iN,avg (N is S i It may be calculated by the sum of squares error with respect to the offset / bias of (the sample of interest from the total measurement results of t).

number

[0060] The expected or reference energy E corresponding to a healthy machine of the decomposed signal iN,ref may be computed by collecting data from a healthy machine, which may be defined as the machine state when system performance (e.g., overall system performance) is within specifications.

[0061] Current measurement result E iN Reference E in iN,ref Deviation ΔE iN may be computed by:

number

[0062] Deviation in resolved signal energy ΔE iN Threshold B for i Reference E iN,ref may be defined below using

number

number

[0063] The decomposed signal S i Instead of comparing the energy of (t), the monitoring parameter is S between the N samples of interest. i (t) may have a maximum value.

[0064] Each signal deviation detection block may be understood to monitor the signal integrity of some signal in real time during system operation. For this reason, it is desirable to keep the computational demands from each signal deviation detection block as low as possible. In a particular example, each low-pass and high-pass signal component S LPF [l], S HPF A computationally efficient first order low-pass and high-pass filter that defines [l] may be described below.

number

[0065] In summary, a method is provided that provides signal deviation detection using frequency binning that can capture a large set of defects not captured by existing methods. The method also provides inter-module triggering to collect complete context information from all system modules.

[0066] The term "color" is used synonymously with wavelength throughout this text, and it should be understood that color may include those outside the visible band (eg, infrared or ultraviolet wavelengths).

[0067] While specific embodiments of the invention have been described above, it will be appreciated that the invention may be practiced otherwise than as described.

[0068] Although specific reference may be made to the use of embodiments of the invention in the context of optical lithography, it will be understood that the invention may be used in other applications such as imprint lithography and is not limited to optical lithography where the context permits. In imprint lithography, a topography in a patterning device defines the pattern to be created on a substrate. The topography of the patterning device may be pressed into a layer of resist supplied to the substrate and the resist is cured by applying electromagnetic radiation, heat, pressure or a combination thereof. The patterning device is then removed from the resist leaving a pattern behind after the resist has been cured.

[0069] As used herein, the terms "radiation" and "beam" encompass all types of electromagnetic radiation, including ultraviolet (UV) radiation (e.g., having a wavelength of about 365, 355, 248, 193, 157, or 126 nm), extreme ultraviolet (EUV) radiation (e.g., having a wavelength in the range of 1-100 nm), and particle beams such as ion beams or electron beams.

[0070] Where the context allows, the term "lens" may refer to any one or combination of various types of optical components, including refractive, reflective, magnetic, electromagnetic and electrostatic optical components. In devices operating in the UV and / or EUV range, reflective components are likely to be used.

[0071] The breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

[0072] Other aspects of the invention are presented in the following numbered paragraphs: Item 1: 1. A method for determining a failure event on a lithography system, comprising: Decomposing at least one signal generated within the lithography system into a plurality of component signals, each component signal associated with a different respective frequency range; evaluating at least one of the component signals with respect to a nominal lithography system behavior; identifying a deviation of at least one of the component signals from the nominal lithography system behavior as a failure event; A method for providing the above. Item 2: Item 10. The method of item 1, wherein the evaluating step comprises evaluating each of the component signals with respect to a nominal lithography system behavior. Item 3: 3. The method of claim 1 or 2, wherein the evaluating step comprises comparing each of the component signals to at least one indicator of nominal lithography system behavior. Item 4: 4. The method of claim 3, wherein the at least one indicator comprises a respective threshold or reference signal for each component signal. Item 5: 5. The method of claim 1, further comprising combining outputs of the evaluating and identifying steps associated with each component signal to generate a failure event trigger signal for the at least one signal based on the identification of a deviation of the at least one of the component signals. Item 6: performing the method individually for each signal of a plurality of signals associated with a lithography system module of the lithography system; combining a failure event trigger signal for each signal of the plurality of signals associated with the lithography system module to generate a failure event trigger signal for the lithography system module; 6. The method according to item 5, comprising: Item 7: Item 7. The method of item 6, wherein the plurality of signals comprises a subset of measurable signals generated by the lithography system module. Item 8: 8. The method of claim 7, comprising selecting the subset of measurable signals based on one or both of domain knowledge and system states of the lithography system. Item 9: performing the method individually for each lithography system module of a plurality of lithography system modules associated with the lithography system; combining the failure event trigger signals associated with each lithography system module to generate a failure event trigger signal for the lithography system; 9. The method according to item 6, 7 or 8, comprising: Item 10: 10. The method of any of items 5 to 9, wherein in one or more of the combining steps, the outputs are combined using one or more logical operators. Item 11: Item 11. The method of item 10, wherein the one or more logical operators comprise at least an OR operator. Item 12: Item 12. The method of any of items 1 to 11, wherein the decomposing step comprises applying one or more high-pass, low-pass and / or band-pass filters to the at least one signal. Item 13: Item 13. The method of item 12, wherein the decomposing step comprises applying one or more layers of at least low-pass and high-pass filters to the signal or to a signal of a previous layer. Item 14: The decomposing step includes: a low frequency component covering a lower frequency range of the at least one signal; a high frequency component covering a higher frequency range of the at least one signal; a mid-frequency component covering a mid-frequency range between the lower frequency range and the higher frequency range of the at least one signal; To generate at least three signal components: applying at least a low pass filter and a high pass filter to the at least one signal. Item 12. The method according to item 11. Item 15: Item 15. The method of any of items 1 to 14, wherein the decomposing step comprises applying at least one Goertzel algorithm or a bandpass filter to the at least one signal to generate signal components at specific frequencies or in specific frequency ranges. Item 16: evaluating the at least one unresolved signal with respect to a nominal lithography system behavior; identifying a deviation of the at least one signal from the nominal lithography system behavior as a failure event; 16. The method according to any of items 1 to 15, comprising: Item 17: Item 17. A method according to any preceding item, wherein the step of evaluating the component signals comprises evaluating signal energy of the component signals. Item 18: A signal deviation detection block capable of determining a failure event on a lithography system, comprising: one or more filters capable of decomposing a signal generated within the lithography system into a plurality of component signals, each component signal associated with a different respective frequency range; a processor capable of evaluating at least one of the component signals with respect to a nominal lithography system behavior and capable of identifying a deviation of at least one of the component signals from the nominal lithography system behavior as a failure event; A signal deviation detection block comprising: Item 19: 20. The signal deviation detection block of claim 18, wherein the processor is capable of evaluating each of the component signals with respect to a nominal lithography system behavior. Item 20: 20. The signal deviation detection block of item 18 or 19, wherein the processor is capable of comparing each of the component signals to at least one indicator of nominal lithography system behavior. Item 21: 21. The signal deviation detection block of claim 20, wherein the at least one indicator comprises a respective threshold or reference signal for each component signal. Item 22: 22. A signal deviation detection block according to any of items 18 to 21, comprising one or more logical operators capable of combining outputs of the evaluating and identifying steps relating to each component signal to generate a failure event trigger signal for said signal based on the identification of a deviation of at least one of the component signals. Item 23: 23. The signal deviation detection block of claim 22, wherein the one or more logical operators comprise at least an OR operator. Item 24: 24. The signal deviation detection block according to any of items 18 to 23, wherein the one or more filters comprise one or more high-pass, low-pass and / or band-pass filters. Item 25: 25. The signal deviation detection block of claim 24, wherein the one or more filters comprise one or more layers of at least low pass filters and high pass filters. Item 26: The one or more filters: a low frequency component covering a lower frequency range of said signal; a high frequency component covering a higher frequency range of said signal; a mid-frequency component covering a mid-frequency range between the lower and higher frequency ranges of the signal; and and a second signal component generating means for generating at least three signal components of said first signal component and said second signal component, Equipped with at least a low pass filter and a high pass filter, 21. A signal deviation detection block according to any one of items 18 to 20. Item 27: 27. A signal deviation detection block according to any of items 18 to 26, comprising a Goertzel algorithm or a tuned bandpass filter capable of generating signal components at a specific frequency or in a specific range of frequencies. Item 28: The processor further comprises: The unresolved signal can be evaluated with respect to nominal lithography system behavior; deviations of the signals from the nominal lithography system behavior can be identified as failure events. 28. A signal deviation detection block according to any of items 18 to 27. Item 29: 29. A signal deviation detection block according to any of items 18 to 28, wherein the processor is capable of evaluating signal energy of the component signals. Item 30: 1. A defect detection module capable of determining a failure event on a lithography system, comprising: 30. A plurality of signal deviation detection blocks according to any of items 18 to 29, each signal deviation detection block being capable of determining a failure event for a respective one of a plurality of signals associated with a lithography system module of the lithography system; at least one logical operator capable of combining the output of each signal deviation detection block to generate a failure event trigger signal for said lithography system module; A defect detection module comprising: Item 31: Item 31. The defect detection module of item 30, wherein the at least one logical operator capable of combining the outputs of each signal deviation detection block comprises at least an OR operator. Item 32: Item 32. The defect detection module of item 30 or 31, wherein the plurality of signals comprises a subset of measurable signals generated by the lithography system module. Item 33: 1. A defect detection system capable of determining a failure event on a lithography system, comprising: 33. A plurality of defect detection modules according to item 30, 31 or 32, each defect detection module being capable of determining a failure event for each of the lithography system modules of the lithography system; at least one logical operator capable of combining the output of each defect detection module to generate a failure event trigger signal for the lithography system; A defect detection system comprising: Item 34: Item 34. The defect detection system of item 33, wherein the one or more logical operators capable of combining the output of each defect detection module comprises at least an OR operator. Item 35: A computer program comprising program instructions which, when executed on a suitable device, is capable of carrying out the method according to any of items 1 to 15. Item 36: 36. A non-transitory computer program carrier comprising a computer program according to item 35. Item 37: A non-transitory computer program carrier according to item 36, a processor capable of executing said computer program provided on said non-transitory computer program carrier; A processing configuration comprising: Item 38: 35. A lithography system comprising the defect detection system according to item 33 or 34.

Claims

1. 1. A method for determining a failure event on a lithography system, comprising: Decomposing at least one signal generated within the lithography system into a plurality of component signals, each component signal associated with a different respective frequency range; evaluating at least one of the component signals with respect to a nominal lithography system behavior; identifying a deviation of at least one of the component signals from the nominal lithography system behavior as a failure event; A method for providing the above.

2. The method of claim 1 , wherein the evaluating step comprises evaluating each of the component signals with respect to a nominal lithography system behavior.

3. 3. The method of claim 1 or 2, comprising combining outputs of the evaluating and identifying steps associated with each component signal to generate a failure event trigger signal for the at least one signal based on the identification of a deviation of the at least one of the component signals.

4. performing the method individually for each signal of a plurality of signals associated with a lithography system module of the lithography system; combining a failure event trigger signal for each signal of the plurality of signals associated with the lithography system module to generate a failure event trigger signal for the lithography system module; The method of claim 3 comprising:

5. The method of claim 4 , wherein the plurality of signals comprises a subset of measurable signals generated by the lithography system module.

6. The method of claim 5 , comprising selecting the subset of measurable signals based on one or both of domain knowledge and system conditions of the lithography system.

7. performing the method individually for each lithography system module of a plurality of lithography system modules associated with the lithography system; combining the failure event trigger signals associated with each lithography system module to generate a failure event trigger signal for the lithography system; 7. The method of claim 4, 5 or 6, comprising:

8. 8. A method according to any of claims 4 to 7, wherein in one or more of the combining steps, the outputs are combined using one or more logical operators.

9. The method of claim 1 , wherein the decomposing step comprises applying one or more high-pass, low-pass and / or band-pass filters to the at least one signal.

10. 10. The method of claim 1, wherein the decomposing step comprises applying at least one of a Goertzel algorithm or a bandpass filter to the at least one signal to generate signal components at specific frequencies or in specific frequency ranges.

11. The method of claim 1 , wherein the step of evaluating the component signals comprises evaluating signal energy of the component signals.

12. A signal deviation detection block capable of determining a failure event on a lithography system, comprising: one or more filters capable of decomposing a signal generated within the lithography system into a plurality of component signals, each component signal associated with a different respective frequency range; a processor capable of evaluating at least one of the component signals with respect to a nominal lithography system behavior and capable of identifying a deviation of at least one of the component signals from the nominal lithography system behavior as a failure event; A signal deviation detection block comprising:

13. The signal deviation detection block of claim 12 , wherein the processor is capable of evaluating each of the component signals with respect to a nominal lithography system behavior.

14. 14. A signal deviation detection block as claimed in claim 12 or 13, comprising one or more logical operators capable of combining outputs of the evaluating and identifying steps relating to each component signal to generate a failure event trigger signal for said signal based on said identification of a deviation of at least one of said component signals.

15. 15. A signal deviation detection block according to any of claims 12 to 14, comprising a Goertzel algorithm or a tuned bandpass filter capable of generating signal components at a specific frequency or in a specific range of frequencies.

16. 16. A signal deviation detection block according to any of claims 12 to 15, wherein the processor is capable of evaluating signal energy of the component signals.

17. 1. A defect detection module capable of determining a failure event on a lithography system, comprising:

17. A plurality of signal deviation detection blocks according to claim 12, each of which is capable of determining a failure event for a respective one of a plurality of signals associated with a lithography system module of the lithography system; at least one logical operator capable of combining the output of each signal deviation detection block to generate a failure event trigger signal for said lithography system module; A defect detection module comprising:

18. 1. A defect detection system capable of determining a failure event on a lithography system, comprising:

20. The method of claim 17, wherein each defect detection module is capable of determining a failure event for a respective lithography system module of the lithography system; at least one logical operator capable of combining the output of each defect detection module to generate a failure event trigger signal for the lithography system; A defect detection system comprising:

19. A computer program comprising program instructions which, when executed on a suitable device, is capable of carrying out the method according to any of the claims 1 to 11.

20. 20. A non-transitory computer program carrier comprising a computer program according to claim 19.

21. A non-transitory computer program carrier according to claim 20; a processor capable of executing said computer program provided on said non-transitory computer program carrier; A processing configuration comprising:

22. A lithography system comprising the defect detection system of claim 18.

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