In a processor, selectively updating a branch predictor for a loop executed from a loop buffer

Abstract

This specification discloses selectively updating a branch predictor for loops executed from a loop buffer. In some aspects, a branch predictor update circuit of a processor is configured to detect a loop including a plurality of loop instructions in an instruction stream and determine that the loop is stored within a loop buffer circuit of the processor. The branch predictor update circuit is further configured to determine a count of potential history register updates to a history register for the plurality of loop instructions and determine whether the count of potential history register updates exceeds the size of the history register. The branch predictor update circuit is also configured to update a branch predictor of the branch predictor circuit based on the plurality of loop instructions in response to determining that the count of potential history register updates does not exceed the size of the history register.

Description

Technical Field

[0001] The technology of the present disclosure relates to the processing of instructions for execution in a microprocessor (the “processor”), and more particularly to branch prediction of branch instructions in a processor.

Background Art

[0002] A microprocessor, also referred to herein as a “processor,” executes computing tasks for various applications. A conventional processor includes a CPU that includes one or more processor cores, i.e., “central processing unit (CPU) cores.” The CPU executes computer program instructions (the “instructions” or “software instructions”), performs operations based on data, and generates results. The results can then be stored in memory, provided as output to an input / output (“I / O”) device, or made available (i.e., communicated) as input values to other instructions executed by the CPU, by way of non-limiting examples.

[0003] The processor can employ a processing technique known as an instruction pipeline, whereby the throughput of the computer instructions being executed can be improved by dividing the processing of each instruction into a series of steps that are executed within an execution pipeline composed of multiple stages. Optimal processor performance can be achieved when all stages within the execution pipeline can process instructions simultaneously and in order as the instructions are arranged within the execution pipeline. However, a situation called a structural hazard can occur, in which case the computational result associated with the execution of the next instruction must be incorrect. For example, as a result of the execution of a branch instruction, a control hazard may occur, and the path of instruction execution may be redirected based on the result evaluated when the branch instruction was executed. When encountering a branch instruction, the processor may need to stall the fetching of further instructions until the branch instruction has been executed, which can result in a decrease in processor performance and an increase in power consumption.

[0004] One way to maximize the performance of a processor is to use a branch predictor circuit to speculatively predict the path taken by a branch instruction (e.g., based on the results of previously executed branch instructions), and make the fetch of subsequent instructions based on the branch prediction. When the branch instruction reaches the execution stage of the instruction pipeline and is executed, the obtained target address of the branch instruction is verified by comparing it with the previously predicted target address when the branch instruction was fetched. If the predicted target address matches the actual target address (i.e., if the branch instruction was correct), the subsequent instructions at the target address have already been fetched and are present in the instruction pipeline, so instruction execution can proceed without delay. To correlate branch prediction with previously observed program behavior, the branch predictor circuit can use a finite-sized history register to track data related to, for example, global branch history, path history, etc.

[0005] Many conventional processors achieve further pipeline optimization and power savings by providing special handling for loops. As used herein, "loop" refers to a sequence of instructions in an instruction pipeline whose processing is sequentially repeated in a continuous operation. For example, a loop may result from a software loop structure that is compiled into a group of instructions that are sequentially processed repeatedly. FIG. 1 shows an example of an instruction stream 100 including an instruction including an exemplary loop 102. The loop 102 in the example of FIG. 1 is a "while" loop that begins with a while instruction 104 and, when processed, determines whether the specified condition is evaluated as true or false. If it is determined that the condition of the while instruction 104 is evaluated as true, the instructions 106-112 within the loop 102 are executed and continue to be executed as a loop as long as the condition of the while instruction 104 is evaluated as true. If it is determined that the condition of the while instruction 104 is evaluated as false, the while instruction 104 is considered an end branch instruction and the loop 102 branches to the next instruction 114 at the end target address.

[0006] When loops such as loop 102 in FIG. 1 can be detected within an instruction pipeline, the instructions that make up the loop can be captured and replayed the number of times the loop is processed before the loop ends, and there is no need for the instruction pipeline to re-fetch and re-decode these instructions. This is because each iteration following the first iteration of the loop necessarily contains the same instruction sequence that has already been fetched and decoded for the first iteration of the loop. In this regard, many conventional processors are provided with a loop buffer circuit for detecting, capturing, and replaying loop instructions. When loop instructions are replayed from the loop buffer, power savings may be achieved by deactivating or otherwise stalling the fetch stage and the decode stage of the instruction pipeline.

[0007] However, the use of a loop buffer circuit can cause problems with respect to updating the branch predictors (i.e., history registers and / or branch predictor table entries) used by the branch predictor circuit. In particular, there may be a problem as to whether the branch predictor should be updated for a branch instruction within a loop that is replayed from the loop buffer circuit. For example, in the case of a history register, in a conventional approach, the history register may be updated with new data each time a branch instruction is encountered, and the old data recorded in the history register is shifted. If the history register contains 64 bits and each encountered branch instruction inserts 1 bit into the history register, a loop with two branches per iteration will update the history register twice during each loop iteration. After 32 loop iterations, all the data stored in the history register from the instructions preceding the loop has been shifted by the updates executed during the loop, and as a result, the branch predictor can no longer correlate with the history preceding the loop. Moreover, since each update per loop iteration is (except perhaps for the last iteration) the same, there is no way to distinguish between different loops that exceed 32 iterations (i.e., the branch predictor cannot distinguish between a loop that is iterated 40 times and a loop that is iterated 100 times). In the case of branch predictor table entries, repeatedly updating the branch predictor table entries for each branch instruction encountered within a loop can lead to excessive power consumption without any corresponding benefit. SUMMARY OF THE INVENTION

[0008] Aspects disclosed herein include selectively updating a branch predictor for loops executed from a loop buffer in a processor. The processor provides a branch predictor update circuit configured to detect a loop including a plurality of loop instructions stored in a loop buffer circuit of the processor and to determine a count of potential history register updates to a history register for the plurality of loop instructions. In some aspects, the count of potential history register updates can be determined as a product of a predicted count of loop iterations, a count of one or more branch instructions within the plurality of loop instructions, and a count of bits of the history register that are updated for each of the one or more branch instructions. If the count of potential history register updates does not exceed the size of the history register, the branch predictor update circuit is configured to update the branch predictor (i.e., the history register and / or the branch predictor table entry of the branch predictor table of the processor's branch predictor circuit) based on the plurality of loop instructions. In aspects where the branch predictor to be updated is a history register, the branch predictor update circuit can "fast-forward" updates to the history register by performing all updates to the history register before starting execution of the loop from the loop buffer circuit. If the branch predictor update circuit determines that the count of potential history register updates exceeds the size of the history register, in some aspects, the branch predictor update circuit can start execution of the loop from the loop buffer circuit without updating the branch predictor of the loop.

[0009] In an aspect where the branch predictor circuit provides a plurality of branch predictor tables associated with corresponding history registers having different sizes, it may be desirable to update only the branch predictors of the branch predictor table associated with the larger history register, while leaving the branch predictors of the branch predictor table associated with the smaller history register unchanged. In this regard, such an aspect can provide that the branch predictor circuit is also configured to determine whether the size of the history register exceeds a history register size threshold and update the branch predictor only when the size of the history register exceeds the history register size threshold.

[0010] Some aspects can provide that the branch predictor update circuit performs updates to the branch predictor only for a subset of potential history register updates that occur during loop iterations (e.g., for long-running loops). In such an aspect, the branch predictor update circuit may be configured to determine whether the count of potential history register updates exceeds an update count threshold. If the threshold is exceeded, the branch predictor update circuit is configured to update the branch predictor of the branch predictor circuit only for a subset of potential history register updates. In some such aspects, the subset of potential history register updates may be determined by the equation x + log 10 n - log 10 x, where x is a non-zero integer representing the update count threshold and n is a non-zero integer representing the count of potential history register updates. Thus, for example, if the branch predictor being updated is a 100-bit history register, the update count threshold is 80, each loop iteration updates 1 bit in the history register, and the count of potential history register updates is between 100 and 999, the branch predictor will be updated 81 times.

[0011] In this regard, in one exemplary aspect, a processor is disclosed for selectively updating a branch predictor for loops executed from a loop buffer. The processor includes an instruction processing circuit configured to process an instruction stream including a plurality of instructions in an instruction pipeline, a branch predictor circuit including a history register, and a branch predictor update circuit. The branch predictor update circuit is configured to detect a loop including a plurality of loop instructions among the plurality of instructions in the instruction stream. The branch predictor update circuit is further configured to determine that the loop is stored within a loop buffer circuit of the processor. The branch predictor update circuit is also configured to determine a count of potential history register updates to the history register for the plurality of loop instructions. The branch predictor update circuit is further configured to determine whether the count of potential history register updates exceeds the size of the history register. The branch predictor update circuit is further configured to update the branch predictor of the branch predictor circuit based on the plurality of loop instructions in response to determining that the count of potential history register updates does not exceed the size of the history register.

[0012] In another exemplary aspect, a method is disclosed for selectively updating a branch predictor for loops executed from a loop buffer. The method includes detecting a loop including a plurality of loop instructions among the plurality of instructions in the instruction stream. The method further includes determining that the loop is stored within a loop buffer circuit. The method also includes determining a count of potential history register updates to the history register for the plurality of loop instructions. The method further includes determining whether the count of potential history register updates exceeds the size of the history register. The method further includes updating the branch predictor of the branch predictor circuit based on the plurality of loop instructions in response to determining that the count of potential history register updates does not exceed the size of the history register.

[0013] In another exemplary aspect, a non-transitory computer-readable medium is disclosed. The non-transitory computer-readable medium stores computer-executable instructions that, when executed, cause a processor to selectively update a branch predictor for a loop executed from a loop buffer by detecting a loop, including a plurality of loop instructions, among a plurality of instructions in an instruction stream. The computer-executable instructions further cause the processor to determine that the loop is stored within the processor's loop buffer circuit. The computer-executable instructions also cause the processor to determine a count of potential history register updates to a history register for the plurality of loop instructions. The computer-executable instructions additionally cause the processor to determine whether the count of potential history register updates exceeds the size of the history register. The computer-executable instructions further cause the processor to update the branch predictor of the branch predictor circuit based on the plurality of loop instructions in response to determining that the count of potential history register updates does not exceed the size of the history register.

[0014] Those skilled in the art will understand the scope of the present disclosure and its further aspects upon reading the following detailed description of the preferred embodiments in conjunction with the accompanying drawings. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate some aspects of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

Brief Description of the Drawings

[0015]

Figure 1

Figure 2

Figure 3

Figure 4A

Figure 4B

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Figure 7

[0016] Aspects disclosed herein include selectively updating a branch predictor for loops executed from a loop buffer in a processor. The processor detects a loop including a plurality of loop instructions stored in a loop buffer circuit of the processor and provides a branch predictor update circuit configured to determine a count of potential history register updates to a history register for the plurality of loop instructions. In some aspects, the count of potential history register updates can be determined as a product of a predicted count of loop iterations, a count of one or more branch instructions within the plurality of loop instructions, and a count of bits of the history register updated for each of the one or more branch instructions. If the count of potential history register updates does not exceed the size of the history register, the branch predictor update circuit is configured to update the branch predictor (i.e., the branch predictor table entry of the branch predictor table of the history register and / or the branch predictor circuit of the processor) based on the plurality of loop instructions. In aspects where the branch predictor to be updated is a history register, the branch predictor update circuit can "pre-fetch" updates to the history register by performing all updates to the history register before starting execution of the loop from the loop buffer circuit. If the branch predictor update circuit determines that the count of potential history register updates exceeds the size of the history register, in some aspects, the branch predictor update circuit can start execution of the loop from the loop buffer circuit without updating the branch predictor of the loop.

[0017] In aspects where the branch predictor circuit provides a plurality of branch predictor tables associated with corresponding history registers having different sizes, it may be desirable to update only the branch predictors of the branch predictor tables associated with the larger history registers and leave the branch predictors of the branch predictor tables associated with the smaller history registers unchanged. In this regard, such aspects can also be configured such that the branch predictor circuit determines whether the size of the history register exceeds a history register size threshold and updates the branch predictor only if the size of the history register exceeds the history register size threshold.

[0018] Some embodiments can provide that the branch predictor update circuit performs updates to the branch predictor only for a subset of potential history register updates that are executed during loop iterations (e.g., in the case of a long-running loop). In such an embodiment, the branch predictor update circuit may be configured to determine whether the count of potential history register updates exceeds an update count threshold. If the threshold is exceeded, the branch predictor update circuit is configured to update the branch predictor of the branch predictor circuit only for a subset of potential history register updates. In some such embodiments, the subset of potential history register updates may be determined by the equation x + log 10 n - log 10 x, where x is a non-zero integer representing the update count threshold and n is a non-zero integer representing the count of potential history register updates. Thus, for example, if the branch predictor being updated is a 100-bit history register, the update count threshold is 80, each loop iteration updates 1 bit in the history register, and the count of potential history register updates is between 100 and 999, the branch predictor will be updated 81 times.

[0019] In this regard, FIG. 2 is a diagram of an exemplary processor-based system 200 that includes a processor 202. The processor 202, which may also be referred to as a "processor core" or "central processing unit (CPU) core," may be an in-order processor or an out-of-order processor (OoP), and / or may be one of a plurality of processors 202 provided by the processor-based system 200. In the example of FIG. 2, the processor 202 includes one or more instruction pipelines I for processing instructions 206 fetched from an instruction memory (captioned "INSTR. MEMORY" in FIG. 2) 208 by a fetch circuit 210 for execution 0 ~I NIt includes an instruction processing circuit 204. The instruction memory 208 can be provided, as a non-limiting example, within the system memory in the processor-based system 200 or as part of the system memory. An instruction cache (captioned as "INSTR. cache" in FIG. 2) 212 is also provided in the processor 202 to cache the instructions 206 fetched from the instruction memory 208 and can reduce the latency of the fetch circuit 210.

[0020] In the example of FIG. 2, the fetch circuit 210 provides the fetched instruction 206 as the fetched instruction 206F to one or more instruction pipelines I within the instruction processing circuit 204 for preprocessing before the fetched instruction 206F reaches the execution circuit (captioned as "EXEC. circuit" in FIG. 2) 214 and is executed. 0 ~I N and is configured to preprocess it. The instruction pipelines I 0 ~I N are provided across various processing circuits or stages of the instruction processing circuit 204 to preprocess and process the fetched instruction 206F in a series of steps that can be executed simultaneously to improve throughput before the execution of the fetched instruction 206F by the execution circuit 214.

[0021] Continuing to refer to FIG. 2, the instruction processing circuit 204 includes a decode circuit 218 configured to decode the fetched instruction 206F fetched by the fetch circuit 210 into a decoded instruction 206D and determine the required instruction type and action. The required instruction type and action encoded in the decoded instruction 206D can also be used to determine the instruction pipeline I 0 ~I N in which the decoded instruction 206D is to be placed. In this example, the decoded instruction 206D is in the instruction pipeline I 0 ~I Nis arranged in one or more of them and is then provided to the rename circuit 220 in the instruction processing circuit 204. The rename circuit 220 is configured to determine whether the register names in the decoded instruction 206D should be renamed in order to break register dependencies that prevent parallel processing or out-of-order processing.

[0022] The instruction processing circuit 204 in the processor 202 of FIG. 2 also includes a register access circuit (captioned "RACC. circuit" in FIG. 2) 222. The register access circuit 222 accesses a physical register in a physical register file (PRF) (not shown) based on a mapping entry mapped to a logical register in a register mapping table (RMT) (not shown) of the source register operand of the decoded instruction 206D, and retrieves a value generated from the executed instruction 206E in the execution circuit 214. The register access circuit 222 is also configured to provide, as the source register operand of the decoded instruction 206D to be executed, the value retrieved and generated from the executed instruction 206E.

[0023] Also, in the instruction processing circuit 204, instruction pipeline I 0 ~I N is provided with a scheduler circuit (captioned "SCHED. circuit" in FIG. 2) 224, and is configured to store the decoded instruction 206D in a reservation entry until all source register operands of the decoded instruction 206D become available. The scheduler circuit 224 issues the decoded instruction 206D that is ready to be executed to the execution circuit 214. A write circuit 226 is also provided in the instruction processing circuit 204 to write back or commit the value generated from the executed instruction 206E to memory (such as PRF), cache memory, or system memory.

[0024] Continuing to refer to FIG. 2, the instruction processing circuit 204 also includes a branch predictor circuit 228. The branch predictor circuit 228 speculatively predicts the result of a fetched branch instruction that controls whether an instruction corresponding to a branched path or an instruction corresponding to a non-branched path within the instruction control flow path is fetched into instruction pipelines I 0 ~I N for execution. For example, the fetched branch instruction may be a branch instruction 230 that includes a condition to be resolved by the instruction processing circuit 204 to determine which instruction control flow path should be taken. In this way, in this example, the result of the branch instruction 230 need not be resolved during execution by the execution circuit 214 before the instruction processing circuit 204 can continue processing the fetched instruction 206F. The prediction made by the branch predictor circuit 228 is provided to the fetch circuit 210 as a branch prediction 232 and can be used to determine the next instruction 206 to fetch as the fetched instruction 206F.

[0025] The branch predictor circuit 228 generates branch predictions such as branch prediction 232 using a plurality of branch predictor tables 234(0) to 234(T). Although the branch predictor tables 234(0) to 234(T) are shown as separate elements from the branch predictor circuit 228 in FIG. 2, it should be understood that some embodiments may provide that the branch predictor tables 234(0) to 234(T) are implemented as components of the branch predictor circuit 228. Each of the branch predictor tables 234(0) to 234(T) stores a plurality of branch predictor table entries such as branch predictor table entries 236(0) to 236(C) and 238(0) to 238(C). The branch predictor table entries 236(0) to 236(C) and 238(0) to 238(C) are indexable entries (e.g., indexed by a hash of the program counter of a branch instruction, branch history, and / or path history) each including a saturating counter representing a branch prediction as a signed value. The branch predictor circuit 228 is configured to speculatively predict the result of a branch instruction such as branch instruction 230 by retrieving counters (e.g., as non-limiting examples, branch predictor table entries 236(0), 238(0)) from each of the plurality of tables of the branch predictor tables 234(0) to 234(T), optionally scaling each branch predictor table entry 236(0), 238(0) by a table-specific scaling factor (not shown), and then summing the retrieved branch predictor table entries 236(0), 238(0) using an adder circuit (not shown). The sign of the sum of the branch predictor table entries 236(0), 238(0) indicates the branch prediction 232.

[0026] To facilitate branch prediction by the branch predictor circuit 228, in the example of FIG. 2, the branch predictor tables 234(0) to 234(T) are associated with the corresponding history registers 240(0) to 240(T). The history registers 240(0) to 240(T) are used to capture the program behavior previously observed regarding previously encountered branches, such as global branch history, path history, etc. The branch predictor circuit 228 can correlate the branch behavior with the contents of the history registers 240(0) to 240(T) when performing branch prediction. In some aspects, each of the branch predictor tables 234(0) to 234(T) may be associated with a corresponding history register 240(0) to 240(T) with an increasing length. Thus, in such aspects, different registers of the history registers 240(0) to 240(T) can have different sizes.

[0027] Instruction 206 can include a "loop", which, as used herein, refers to a sequence of instructions 206 that are sequentially iterated in a continuous manner. When instruction 206 is being processed within one of instruction pipelines I 0 ~I N if an instruction 206 that is part of a loop can be detected, instruction 206 can be captured and replayed at the processing stage within instruction pipelines I 0 ~I N without the need to refetch and / or redecode instruction 206 for subsequent iterations of the loop. In this regard, in this example, the instruction processing circuit 204 includes a loop buffer circuit 242 for performing loop buffering. The loop buffer circuit 242 detects a loop in instruction 206, captures (i.e., loop buffers) the instructions 206 within the detected loop, and is configured to insert (i.e., replay) the captured loop instructions 206 into instruction pipelines I 0 ~I N for subsequent iterations of the loop. In this way, the loop buffer circuit 242 enables the instruction processing circuit to avoid or reduce the need to refetch instruction 206 within the detected loop.

[0028] The loop buffer circuit 242 in the instruction processing circuit 204 of the processor 202 includes a loop detection circuit 244 and a loop replay circuit 246. The loop detection circuit 244 is configured to detect a loop in the instruction 206 being executed. In this regard, in this example, the loop detection circuit 244 receives the decoded instruction 206D in the instruction pipeline I 0 ~I N and is communicatively coupled to the output of the decode circuit 218 in the instruction pipeline I 0 ~I N The loop detection circuit 244 is configured to receive the decoded instruction 206D, analyze the decoded instruction 206D, and determine whether there is a loop in the decoded instruction 206D. If the loop detection circuit 244 detects a loop in the decoded instruction 206D, the loop detection circuit 244 may provide the instruction 206D within the detected loop to the loop replay circuit 246, or store the captured decoded instruction 206D within the detected loop in a memory structure such as a loop capture memory 248 accessible, for example, by the loop replay circuit 246. The loop replay circuit 246, as a loop iteration prediction (not shown), is configured to predict the total number of complete iterations of the detected loop executed in the instruction pipeline I 0 ~I N and, as a loop termination branch prediction (not shown), is configured to predict the loop termination branch of the decoded instruction 206D of the detected loop that results in the detected loop ending in the instruction pipeline I 0 ~I N Next, the loop replay circuit 246 is configured to fully replay the detected loop within the instruction pipeline I

[0029] However, as described above, the use of the loop buffer circuit 242 may cause problems with respect to the update of the branch predictor (i.e., the history registers 240(0) to 240(T) and / or the branch predictor table entries 236(0) to 236(C), 238(0) to 238(C)) used by the branch predictor circuit 228 for the branch instructions within the loop that are replayed from the loop buffer circuit 242. Thus, in this regard, the branch predictor update circuit 250 of FIG. 2 is configured to selectively update the branch predictor for the loops executed from the loop buffer. When detecting a loop including a plurality of loop instructions stored in the loop buffer circuit 242, the branch predictor update circuit 250 determines a count of potential history register updates for the history register (e.g., the history register 240(0) of FIG. 2) for the plurality of loop instructions. If the count of potential history register updates does not exceed the size of the history register 240(0), the branch predictor update circuit 250 is configured to update the branch predictor (i.e., the history register 240(0) and / or the branch predictor table entries such as the branch predictor table entry 236(0) of FIG. 2) based on the plurality of loop instructions. If the branch predictor update circuit 250 determines that the count of potential history register updates exceeds the size of the history register 240(0), in some embodiments, the branch predictor update circuit 250 can start the execution of the loop from the loop buffer circuit 242 without updating the branch predictor for the loop. In this way, the program behavior of loops with short execution times can be used to update the branch predictor, while the program history stored by the branch predictor can be retained when encountering loops with long execution times.

[0030] To explain the exemplary elements of the branch predictor update circuit 250 of FIG. 2 and the operations performed thereby, FIG. 3 is provided. As seen in FIG. 3, an instruction stream 300 including a plurality of instructions 302(0) to 302(X) is being executed (e.g., by the instruction processing circuit 204 of FIG. 2). The plurality of instructions includes instructions 302(L) to 302(L') (also referred to herein as "loop instructions 302(L) to 302(L')") including a branch instruction 302(B) (also referred to herein as "branch instruction 302(B)"), which together form a loop 304. Also shown in FIG. 3 are the branch predictor update circuit 250 of FIG. 2, the branch predictor table 234(0) of FIG. 2 (including branch predictor table entries 236(0) to 236(C) (captioned "C counter" in FIG. 3)), and the corresponding history register 240(0) of FIG. 2 (including a plurality of bits 306(0) to 306(H)).

[0031] In the example of FIG. 3, the branch predictor update circuit 250 detects the loop 304 and determines that the loop 304 is stored in the loop buffer circuit 242 of FIG. 3 (e.g., by monitoring or querying the loop buffer circuit 242). When it is determined that the loop 304 is stored in the loop buffer circuit 242, the branch predictor update circuit 250 determines a count 308 of potential history register updates to the history register 240(0) for a plurality of loop instructions 302(L) to 302(L'). In some embodiments, the branch predictor update circuit 250 determines the count 308 of potential history register updates by first determining a predicted count 310 of loop iterations of the loop 304 (e.g., by examining the loop replay circuit 246 of FIG. 2). The branch predictor update circuit 250 further determines a count 312 of branch instructions (i.e., branch instruction 302(B)) within the plurality of loop instructions 302(L) to 302(L'). Additionally, the branch predictor update circuit 250 determines a count 314 of bits 306(0) to 306(H) of the history register 240(0) that are updated each time the branch instruction 302(B) is executed. Next, the branch predictor update circuit 250 can calculate the count 308 of potential history register updates as the product of the predicted count 310 of loop iterations, the count 312 of branch instructions 302(B) within the plurality of loop instructions 302(L) to 302(L'), and the count 314 of bits 306(0) to 306(H) of the history register 240(0) that are updated for the branch instruction 302(B). Thus, if it is predicted that there are 32 loop iterations, a single branch instruction 302(B), and 1 bit out of bits 306(0) to 306(H) of the history register 240(0) is updated each iteration of the branch instruction 302(B), the count 308 of potential history updates is calculated as 32×1×1, i.e., 32.

[0032] The branch predictor update circuit 250 then determines whether the count 308 of potential history register updates exceeds the size of the history register 240(0) (i.e., the number of bits 306(0) to 306(H) in FIG. 3, H). If the number of history registers is not exceeded, the branch predictor update circuit 250 updates the branch predictor of the branch predictor circuit 228 based on the plurality of loop instructions 302(L) to 302(L'). In some embodiments according to FIG. 3, the branch predictor may include a history register 240(0) associated with the branch predictor table 234(0). In such an embodiment, the branch predictor update circuit 250 may update the branch predictor by updating the history register 240(0) based on the branch instructions 302(B) within the plurality of loop instructions 302(L) to 302(L'). Each update to the history register 240(0) for each branch instruction 302(B) for each iteration of the loop 304 is the same, and since the count 308 of potential history updates is pre-computed, some embodiments of the branch predictor update circuit 250 may "pre-fetch" the updates to the history register 240(0) by performing all updates to the history register 240(0) before starting the execution of the loop 304 from the loop buffer circuit 242. Some embodiments according to FIG. 3 may provide that the branch predictor is a branch predictor table entry such as the branch predictor table entry 236(0). Thus, according to such an embodiment, the branch predictor update circuit 250 may update the branch predictor by updating the branch predictor table entry 236(0) based on the branch instructions 302(B) within the plurality of loop instructions 302(L) to 302(L').

[0033] In some embodiments, such as the example of FIG. 2, the branch predictor table 234(0) is one of a plurality of branch predictor tables 234(0) to 234(T), and the history register 240(0) is one of a plurality of corresponding history registers 240(0) to 240(T) with an increasing history length (i.e., number of bits). In such an embodiment, it may be desirable to update the branch predictor only for the branch predictor table associated with a history register longer than the history register size threshold 316 and avoid updating the branch predictor for the branch predictor table associated with a shorter history register. Thus, before updating the branch predictor, the branch predictor update circuit 250 can also determine whether the size of the history register 240(0) exceeds the history register size threshold 316. If the threshold is not exceeded, the branch predictor (e.g., as a non-limiting example, the history register 240(0) or the branch predictor table entry 236(0)) is updated as described above.

[0034] Some embodiments can provide that the branch predictor update circuit 250 performs an update to the branch predictor only for a subset of potential history register updates that are executed during loop iterations. In such an embodiment, the branch predictor update circuit 250 determines a count 308 of potential history register updates and also determines whether the count 308 of potential history register updates exceeds an update count threshold 318. If the threshold is exceeded, the branch predictor update circuit is configured to update the branch predictor of the branch predictor circuit 228 only for a subset of potential history register updates. The update count threshold 318 can be determined, for example, based on the number of history register updates executed per loop iteration and the length of the history register 240(0).

[0035] In some such embodiments, the subset of potential history register updates is given by the equation x + log 10 n - log 10It may be determined by x, where x is a non-zero integer representing the update count threshold 318, and n is a non-zero integer representing the count 308 of potential history register updates. With these aspects, the branch predictor update circuit 250 captures all branch predictor updates due to loop buffer-replayed branches for the first several iterations of the loop 304, while holding the history captured prior to the loop 304 and can also capture the approximate time at which the loop 304 has iterated. Among such aspects, there are also those that provide other mechanisms for determining the size of a subset of potential history register updates, such as dividing the count 308 of potential history register updates by a constant, or applying other logarithmic or exponential functions.

[0036] To illustrate the exemplary operations performed by the branch predictor update circuit 250 of FIGS. 2 and 3 according to some aspects, FIGS. 4A and 4B provide a flowchart 400. When describing FIGS. 4A and 4B, the elements of FIGS. 2 and 3 are referenced for clarity. It should be understood that some of the operations shown in FIGS. 4A and 4B may be performed in an order other than that shown herein and / or may be omitted in some aspects. The operation of FIG. 4A begins with a branch predictor update circuit, such as the branch predictor update circuit 250 of FIGS. 2 and 3, detecting a loop (e.g., loop 304 of FIG. 3) that includes a plurality of loop instructions (e.g., a plurality of loop instructions 302(L) - 302(L') among the plurality of instructions 302(0) - 302(X) of the instruction stream 300 of FIG. 3) among a plurality of instructions of an instruction stream (block 402). The branch predictor update circuit 250 determines that the loop 304 is stored within a loop buffer circuit, such as the loop buffer circuit 242 of FIG. 3 (block 404). The branch predictor update circuit 250 then determines a count (e.g., count 308 of FIG. 3) of potential history register updates to a history register (e.g., history register 240(0) of FIGS. 2 and 3) for the plurality of loop instructions 302(L) - 302(L') (block 406). Exemplary operations of block 406 for determining the count 308 of potential history register updates according to some aspects are discussed in further detail below with respect to FIG. 5.

[0037] In some embodiments, the branch predictor update circuit 250 can determine whether the size of the history register 240(0) exceeds a history register size threshold, such as the history register size threshold 316 of FIG. 3 (block 408). If the threshold is exceeded, the operation in such an embodiment continues at block 412. However, if the branch predictor update circuit 250 determines in decision block 408 that the size of the history register 240(0) does not exceed the history register size threshold 316, the branch predictor update circuit 250 starts execution of loop 304 from the loop buffer circuit 242 without updating the branch predictor (e.g., the history register 240(0) or the branch predictor table entry 236(0) of FIGS. 2 and 3) of the branch predictor circuit 228 for loop 304 (block 410).

[0038] Next, the branch predictor update circuit 250 determines whether the count of potential history register updates (e.g., count 308 of FIG. 3) exceeds the size of the history register 240(0) (block 412). If it is determined in decision block 412 that the count 308 of potential history register updates exceeds the size of the history register 240(0), the operation continues at block 410. Otherwise, the operation continues at block 414 of FIG. 4B.

[0039] Next, referring to FIG. 4B, when the branch predictor update circuit 250 determines in the determination block 412 that the count 308 of potential history register updates does not exceed the size of the history register 240(0), the branch predictor update circuit 250 updates the branch predictor (e.g., the history register 240(0) or the branch predictor table entry 236(0) of FIGS. 2 or 3) of the branch predictor circuit (e.g., the branch predictor circuit 228 of FIG. 2) based on a plurality of loop instructions 302(L) to 302(L') (block 414). In an aspect where the branch predictor is a history register such as the history register 240(0), the operation of block 414 to update the branch predictor can include updating the history register 240(0) based on one or more branch instructions 302(B) within the plurality of loop instructions 302(L) to 302(L') (block 416). Some such aspects can provide that the operation of block 416 to update the history register 240(0) includes performing all updates to the history register 240(0) before starting the execution of the loop 304 from the loop buffer circuit 242 (block 418). In an aspect where the branch predictor is a branch predictor table entry such as the branch predictor table entry 236(0), the operation of block 414 to update the branch predictor can include updating the branch predictor table entry 236(0) of the plurality of branch predictor table entries 236(0) to 236(C) of the branch predictor table 234(0) of the branch predictor circuit 228 based on one or more branch instructions 302(B) within the plurality of loop instructions 302(L) to 302(L') (block 420).

[0040] FIG. 5 provides a flowchart 500 for more particularly illustrating an exemplary operation of block 406 of FIG. 4A for determining a count 308 of potential history register updates according to some aspects. For clarity, elements of FIGS. 2 and 3 are referenced when describing FIG. 5. In FIG. 5, the operation begins with the branch predictor update circuit 250 determining a predicted count of loop iterations of loop 304 (e.g., predicted count 310 of FIG. 3) (block 502). The branch predictor update circuit 250 also determines a count (e.g., count 312 of FIG. 3) of one or more branch instructions 302(B) within the plurality of loop instructions 302(L) - 302(L’) (block 504). The branch predictor update circuit 250 also determines a count (e.g., count 314 of FIG. 3) of bits 306(0) - 306(H) of the history register 240(0) that are updated for each of the one or more branch instructions 302(B) (block 506). Finally, the branch predictor update circuit 250 determines the count 308 of potential history register updates as the product of the predicted count 310 of loop iterations, the count 312 of one or more branch instructions 302(B) within the plurality of loop instructions 302(L) - 302(L’), and the count 314 of bits 306(0) - 306(H) of the history register 240(0) that are updated for each of the one or more branch instructions 302(B) (block 508).

[0041] Some embodiments can provide for the branch predictor update circuit 250 to apply additional logic in determining how many updates should be made to the branch predictor before executing the operation of block 414 to update the branch predictor. In this regard, FIG. 6 provides a flowchart 600 for explaining an exemplary operation performed by the branch predictor update circuit 250. When explaining FIG. 6, the elements of FIGS. 2 and 3 are referenced for clarity. The operation of FIG. 6 begins after the branch predictor update circuit 250 determines a count of potential history register updates (e.g., count 308 of FIG. 3), by determining whether the count 308 of potential history register updates exceeds an update count threshold (e.g., update count threshold 318 of FIG. 3) (block 602). If the threshold is exceeded, the branch predictor update circuit 250 updates only the branch predictors 240(0), 236(0) of the branch predictor circuit 228 for a subset of the potential history register updates (block 604). However, if the branch predictor update circuit 250 determines in decision block 602 that the count 308 of potential history register updates does not exceed the update count threshold 318, the branch predictor update circuit 250 updates the branch predictors 240(0), 236(0) for each of the potential history register updates (block 606).

[0042] FIG. 7 is a block diagram of an exemplary processor-based system 700 that includes a processor 702 (e.g., a microprocessor) that includes an instruction processing circuit 704 that includes a branch predictor update circuit 706 (captioned "BPUC" in FIG. 7) that functionally corresponds to the branch predictor update circuit 250 of FIG. 2. The instruction processing circuit 704 can be, by way of example, the instruction processing circuit 204 within the processor 202 of FIG. 2. The processor-based system 700 can be, by way of example, the processor-based system 200 of FIG. 2. The processor-based system 700 can be one or more circuits included in an electronic substrate card such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or other device, and can represent, for example, a server or a user's computer.

[0043] In this example, the processor 702 represents one or more general-purpose processing circuits such as a microprocessor, a central processing unit. The processor 702 is configured to execute processing logic within instructions for performing the operations and steps discussed herein. In this example, the processor 702 includes an instruction cache 708 for temporary high-speed access memory storage of instructions accessible by the instruction processing circuit 704. Instructions fetched or prefetched from memory such as system memory 710 via the system bus 712 are stored in the instruction cache 708. The instruction processing circuit 704 is configured to process the instructions fetched into the instruction cache 708 and to process that instruction for execution.

[0044] The processor 702 and the system memory 710 are coupled to a system bus 712 and can interconnect peripheral devices included in the processor-based system 700. As is well known, the processor 702 communicates with these other devices by exchanging address, control, and data information via the system bus 712. For example, the processor 702 can communicate a burst transaction request to a memory controller 714 within the system memory 710 as an example of a slave device. Although not shown in FIG. 7, a plurality of system buses 712 may be provided where each system bus constitutes a different fabric. In this example, the memory controller 714 is configured to provide a memory access request to a memory array 716 within the system memory 710. The memory array 716 is composed of an array of memory bit cells for storing data. The system memory 710 may be, by way of non-limiting example, a read-only memory (ROM), a flash memory, a dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), and a static memory (e.g., a flash memory, a static random access memory (SRAM), etc.).

[0045] Other devices may be connected to the system bus 712. As shown in FIG. 7, these devices may include, by way of example, a system memory 710, one or more input devices 718, one or more output devices 720, a modem 722, and one or more display controllers 724. The input device 718 can include any type of input device including, but not limited to, input keys, switches, voice processors, etc. The output device 720 can include any type of output device including, but not limited to, voice, video, other visual indicators, etc. The modem 722 can be any device configured to enable data exchange with a network 726. The network 726 can be any type of network including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH (trademark) network, and the Internet. The modem 722 can be configured to support any desired type of communication protocol. The processor 702 may also be configured to access the display controller 724 via the system bus 712 and control the information transmitted to one or more displays 728. The display 728 can include any type of display including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0046] The processor-based system 700 of FIG. 7 can include a set of instructions 730 that are executed by a processor 702 for any desired application according to the instructions. The instructions 730 can be stored as an example of a non-transitory computer-readable medium 732 in the system memory 710, the processor 702, and / or the instruction cache 708. The instructions 730 can also exist, in whole or at least in part, within the system memory 710 and / or within the processor 702 during their execution. The instructions 730 can further be transmitted or received via the network 726 via the modem 722 such that the network 726 includes the computer-readable medium 732.

[0047] The computer-readable medium 732 is shown as a single medium in the exemplary embodiment, but the term "computer-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" should also be taken to include any medium that can store, encode, or carry a set of instructions for execution by a processing device and that can cause a processing device to execute any one or more of the methodologies of the embodiments disclosed herein. Thus, the term "computer-readable medium" should be taken to include, without limitation, solid-state memory, optical media, and magnetic media.

[0048] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be embodied as machine-executable instructions, such instructions being used to cause a general-purpose processor or a special-purpose processor programmed with the instructions to execute the steps. Alternatively, the steps may be executed by a combination of hardware and software.

[0049] Embodiments disclosed herein may be provided as a computer program product or software that includes a machine-readable medium (or computer-readable medium) storing instructions that may be used to program a computer system (or other electronic device) to perform a process according to embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes machine-readable storage media (e.g., ROM, random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.).

[0050] Unless specifically stated otherwise, and as will be apparent from the foregoing discussion, throughout this specification, discussions using terms such as “processing,” “computing,” “determining,” “displaying,” etc., refer to actions and processes of a computer system, or similar electronic computing device, that manipulate and transform data represented as physical (electronic) quantities within the registers of the computer system into other data similarly represented as physical quantities within the memory of the computer system or registers, or other such information storage devices, transmission devices, or display devices.

[0051] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The structure required for these various systems will be apparent from the above description. In addition, embodiments described herein are not described with reference to any particular programming language. It should be appreciated that various programming languages may be used to implement the teachings of the embodiments as described herein.

[0052] One of ordinary skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, instructions stored in memory or another computer-readable medium, instructions executed by a processor or other processing device, or any combination thereof. The components of the distributed antenna system described herein may, by way of example, be implemented in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in various ways for each particular application, but such implementation decisions should not be construed as causing a departure from the scope of the embodiments.

[0053] The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein can be implemented or executed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, a controller may be a processor. The processor may be a microprocessor, but in the alternative, may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0054] The embodiments disclosed herein may be embodied as hardware and instructions stored on hardware, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. An illustrative memory medium is coupled to the processor such that the processor can read information from, and write information to, the memory medium. In the alternative, the memory medium may be integral to the processor. The processor and the memory medium may reside within an ASIC. The ASIC may reside within a remote station. In the alternative, the processor and the memory medium may reside as discrete components in a remote station, base station, or server.

[0055] Note that the operation steps described in any of the exemplary embodiments in this specification are explained for the purpose of providing examples and discussions. The operations described can be performed in many different orders other than the order shown. Furthermore, the operations described as a single operation step may actually be executed in a plurality of different steps. In addition, one or more operation steps discussed in the exemplary embodiments may be combined. Also, those skilled in the art will understand that information and signals can be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields, or particles, optical fields or particles, or any combination thereof.

[0056] Unless explicitly stated otherwise, it is never intended that any method described in this specification be construed as requiring that its steps be performed in a particular order. Thus, when a method claim does not actually recite the order in which its steps should be followed, or when the steps are not specifically recited in the claim or the specification as being limited to a particular order, it is never intended that a particular order be inferred.

[0057] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit and scope of the invention. Since modifications, combinations, sub - combinations, and variations of the disclosed embodiments incorporating the spirit and substance of the invention can be conceived by those skilled in the art, the invention should be construed to include all within the scope of the appended claims and their equivalents.

Claims

1. It is a processor, The instruction processing circuit includes an instruction processing circuit configured to process an instruction stream containing multiple instructions in an instruction pipeline, and the instruction processing circuit is configured A branch predictor circuit including a history register, The branch predictor update circuit includes, and the branch predictor update circuit is To detect loops that include multiple loop instructions among the multiple instructions in the instruction stream, Determining that the loop is stored in the loop buffer circuit of the processor, Determining the count of potential history register updates for the history registers for the plurality of loop instructions, Determining whether the count of potential history register updates exceeds the size of the history register, In response to determining that the count of potential history register updates does not exceed the size of the history register, the branch predictor of the branch predictor circuit is updated based on the plurality of loop instructions. Configured to perform, Processor.

2. The processor according to claim 1, wherein the branch predictor update circuit is To determine the predicted count of loop iterations of the aforementioned loop, Determining the count of one or more branch instructions within the aforementioned plurality of loop instructions, Determine the count of the bits in the history register that are updated for each of the one or more branch instructions. The count of potential history register updates is determined as the product of the predicted count of loop iterations, the count of one or more branch instructions within the plurality of loop instructions, and the count of the bits of the history register that are updated for each of the one or more branch instructions. A processor configured to determine the count of potential history register updates by being configured to perform the following:

3. The processor according to claim 1, The branch predictor includes the history register, The branch predictor update circuit is configured to update the branch predictor by updating the history register based on one or more branch instructions within the plurality of loop instructions. Processor.

4. A processor according to claim 3, wherein the branch predictor update circuit is configured to update the history register based on one or more branch instructions in the plurality of loop instructions, by performing all updates to the history register before the loop execution starts from the loop buffer circuit.

5. The processor according to claim 1, The branch predictor includes a branch predictor table entry from among a plurality of branch predictor table entries in the branch predictor table of the branch predictor circuit, The branch predictor update circuit is configured to update the branch predictor by updating the branch predictor table entries based on one or more branch instructions within the plurality of loop instructions. Processor.

6. The processor according to claim 1, The branch predictor circuit includes a plurality of branch predictor tables and a plurality of corresponding history registers, including the history registers. The branch predictor update circuit is further configured to determine whether the size of the history register exceeds the history register size threshold. The branch predictor update circuit is configured to update the branch predictor of the branch predictor circuit based on the plurality of loop instructions in response to determining that the size of the history register exceeds the history register size threshold. Processor.

7. The processor according to claim 1, The branch predictor update circuit is further configured to determine whether the count of potential history register updates exceeds an update count threshold. The branch predictor update circuit is configured to update the branch predictor of the branch predictor circuit based on the plurality of loop instructions, by further determining that the count of potential history register updates exceeds the update count threshold, and updating the branch predictor of the branch predictor circuit only for a subset of the potential history register updates. Processor.

8. A processor according to claim 7, wherein the subset of potential history register updates is determined by the equation x + log 10n - log 10x, where x is a non-zero integer representing the update count threshold and n is a non-zero integer representing the count of potential history register updates.

9. A processor according to claim 1, wherein the branch predictor update circuit is further configured to initiate execution of the loop from the loop buffer circuit without updating the branch predictor of the branch predictor circuit for the loop, in response to determining that the count of potential history register updates exceeds the size of the history register.

10. A step of detecting a loop that contains multiple loop instructions among multiple instructions in an instruction stream, The steps include determining that the aforementioned loop is stored in the loop buffer circuit, The steps include determining the count of potential history register updates for the history registers for the plurality of loop instructions, A step of determining whether the count of potential history register updates exceeds the size of the history register, A step of updating the branch predictor of the branch predictor circuit based on the plurality of loop instructions in response to determining that the count of potential history register updates does not exceed the size of the history register. A method that includes this.

11. A method according to claim 10, wherein the step of determining the count of potential history register updates is The steps include determining the predicted count of loop iterations of the aforementioned loop, The steps include determining the count of one or more branch instructions within the plurality of loop instructions, The steps include determining the count of bits in the history register that are updated for each of the one or more branch instructions, The step includes determining the count of potential history register updates as the product of the predicted count of loop iterations, the count of one or more branch instructions within the plurality of loop instructions, and the count of the bits of the history register that are updated for each of the one or more branch instructions, method.

12. The method according to claim 10, The branch predictor includes the history register, The step of updating the branch predictor includes updating the history register based on one or more branch instructions within the plurality of loop instructions. method.

13. A method according to claim 12, wherein the step of updating the history register based on one or more branch instructions in the plurality of loop instructions includes the step of performing all updates to the history register before the execution of the loop from the loop buffer circuit begins.

14. A method according to claim 10, wherein the step of updating the branch predictor includes updating a branch predictor table entry among a plurality of branch predictor table entries in the branch predictor table of the branch predictor circuit based on one or more branch instructions in the plurality of loop instructions.

15. A method according to claim 10, further comprising the step of determining whether the size of the history register exceeds a history register size threshold, The step of updating the branch predictor of the branch predictor circuit based on the plurality of loop instructions further responds to determining that the size of the history register exceeds the history register size threshold. method.

16. The method according to claim 10, The step of determining whether the count of potential history register updates exceeds the update count threshold is Furthermore, The step of updating the branch predictor of the branch predictor circuit based on the plurality of loop instructions further includes the step of updating the branch predictor of the branch predictor circuit for only a subset of the potential history register updates in response to determining that the count of potential history register updates exceeds the update count threshold, method.

17. The method according to claim 16, wherein the subset of potential history register updates is determined by the equation x + log 10n - log 10x, where x is a non-zero integer representing the update count threshold and n is a non-zero integer representing the count of potential history register updates. method.

18. A non-temporary computer-readable medium storing computer-executable instructions, wherein, when the computer-executable instructions are executed, the processor... Detecting loops containing multiple loop instructions among multiple instructions in an instruction stream, Determining that the loop is stored in the loop buffer circuit of the processor, To determine the count of potential history register updates for the history registers for the aforementioned multiple loop instructions, Determining whether the count of potential history register updates exceeds the size of the history register, In response to determining that the count of potential history register updates does not exceed the size of the history register, the branch predictor of the branch predictor circuit is updated based on the plurality of loop instructions, To have them do it, A non-temporary computer-readable medium.

19. A non-temporary computer-readable medium according to claim 18, wherein the computer-executable instruction is transmitted to the processor, To determine the predicted count of loop iterations of the aforementioned loop, Determining the count of one or more branch instructions within the aforementioned plurality of loop instructions, Determine the count of the bits in the history register that are updated for each of the one or more branch instructions. The count of potential history register updates is determined as the product of the predicted count of loop iterations, the count of one or more branch instructions within the plurality of loop instructions, and the count of the bits of the history register that are updated for each of the one or more branch instructions. By causing the processor to perform this action, the processor is made to determine the count of potential history register updates. A non-temporary computer-readable medium.

20. A non-temporary computer-readable medium according to claim 18, wherein the computer-executable instruction further causes the processor to initiate execution of the loop from the loop buffer circuit without updating the branch predictor of the branch predictor circuit for the loop, in response to determining that the count of potential history register updates exceeds the size of the history register. A non-temporary computer-readable medium.

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