Semiconductor Package

Abstract

The semiconductor package according to the embodiment includes an insulating layer, a protective layer disposed on the insulating layer, a through electrode penetrating the insulating layer, and a bump portion disposed on the through electrode and penetrating the protective layer. The bump portion includes a first portion connected to the through electrode and a second portion disposed on the first portion and protruding above the protective layer. The horizontal width of the first portion is the same as the horizontal width of the second portion.

Description

Technical Field

[0001] Embodiments relate to a circuit board and a semiconductor package including the same.

Background Art

[0002] A semiconductor package has a structure in which a semiconductor chip is attached to a circuit board. The semiconductor package can provide a combination of a plurality of packages to which different elements are attached. Such a semiconductor package has an advantage in that high-speed signal transmission is possible through a short path because a plurality of elements are realized in one package. Accordingly, semiconductor packages are widely applied to mobile devices and the like.

[0003] On the other hand, when attaching an electronic element such as a semiconductor chip to a circuit board, a wire is applied to form a semiconductor package. A semiconductor package having a wire structure has a problem of increased volume. Accordingly, recently, semiconductor packages have been manufactured by flip chip packaging. Flip chip packaging is a method of bonding and packaging a semiconductor chip and a circuit board by fusing solder bumps to connection patterns of the semiconductor chip and the circuit board without using an additional connecting member such as a wire when attaching an electronic element such as a semiconductor chip to the circuit board.

[0004] Recently, due to the demand for high-speed and large-capacity data processing and the trend toward thinner, lighter, and more compact electronic products, the bump pitch of electronic elements has been gradually decreasing. Along with such a trend, the reliability of bump connection between a circuit board and a semiconductor chip in flip chip packaging has been decreasing. In order to prevent such a decrease in reliability, Korean Patent Publication No. 10-2013-0027870 proposes a structure including a bump portion with improved reliability.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The embodiments provide a circuit board with a new structure and a semiconductor package including the same.

[0006] Also, the embodiments provide a circuit board capable of reducing the pitch between a plurality of bump portions and a semiconductor package including the same.

[0007] Also, the embodiments provide a circuit board capable of improving circuit integration and a semiconductor package including the same.

[0008] Also, the present embodiment provides a circuit board with improved connection reliability between the pad portion and the bump portion of the bump portion and a semiconductor package including the same.

[0009] Also, the embodiments provide a circuit board capable of minimizing the degree of concavity of a recess formed on a side surface of a lower region of the bump portion and a semiconductor package including the same.

[0010] Furthermore, the embodiments provide a circuit board capable of minimizing the thickness deviation of a plurality of bump portions and a semiconductor package including the same.

[0011] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those having ordinary knowledge in the technical field to which the proposed embodiments belong from the following description.

Means for Solving the Problems

[0012] The semiconductor package according to the embodiments includes an insulating layer, a protective layer disposed on the insulating layer, a through electrode penetrating the insulating layer, and a bump portion disposed on the through electrode and penetrating the protective layer. The bump portion includes a first portion connected to the through electrode and a second portion disposed on the first portion and protruding above the protective layer. The horizontal width of the first portion is the same as the horizontal width of the second portion.

[0013] In addition, the horizontal width of the first part is larger than the width of the upper surface of the through electrode.

[0014] In addition, the bump part is integrally formed with the first part and the second part.

[0015] In addition, the first part and the second part of the bump part are integrally formed with the through electrode.

[0016] In addition, the bump part includes a plurality of metal layers, and the width of at least one of the plurality of metal layers is different from the width of at least one other metal layer.

[0017] In addition, the plurality of metal layers include a first metal layer disposed on the insulating layer, a second metal layer disposed on the first metal layer, and a third metal layer disposed on the second metal layer, and the width of the first metal layer is larger than the width of the third metal layer.

[0018] In addition, the width of the second metal layer is larger than the width of the first metal layer.

[0019] In addition, the width of the third metal layer is larger than the width of the second metal layer.

[0020] In addition, the first metal layer is a chemical copper plating layer, the second metal layer is a first electrolytic plating layer, and the third metal layer is a second electrolytic plating layer.

[0021] In addition, the bump part further includes a fourth metal layer provided between the insulating layer and the first metal layer, and the width of the third metal layer is larger than the width of the fourth metal layer.

[0022] In addition, the fourth metal layer is a copper foil layer.

[0023] Further, the first metal layer has a first thickness in the range of 0.5 μm to 1.5 μm, the second metal layer has a second thickness in the range of 3 μm to 5 μm, the third metal layer has a third thickness in the range of 100 μm to 220 μm, and the fourth metal layer has a fourth thickness in the range of 0.8 μm to 2 μm.

[0024] Further, the semiconductor package is disposed on the insulating layer and further includes a pad portion horizontally spaced from the bump portion, and the pad portion horizontally overlaps a first portion of the bump portion.

[0025] The pad portion includes first to third metal layers corresponding to the first to third metal layers of the bump portion.

[0026] Further, the thickness of the third metal layer of the pad portion is smaller than the thickness of the third metal layer of the bump portion.

[0027] Further, the semiconductor package is disposed on the insulating layer and further includes a trace horizontally spaced from the bump portion, and the trace horizontally overlaps the first portion of the bump portion.

[0028] Further, the trace includes first to third metal layers corresponding to the first to third metal layers of the bump portion.

[0029] Further, the thickness of the third metal layer of the trace is smaller than the thickness of the third metal layer of the bump portion.

Advantages of the Invention

[0030] The circuit board of the embodiment includes an insulating layer, a through electrode penetrating the insulating layer, and a first circuit layer disposed on the insulating layer. At this time, the first circuit layer includes a bump portion. The bump portion is provided to protrude through a protective layer disposed on the insulating layer and onto the protective layer.

[0031] The bump portion includes a first portion disposed on the insulating layer and the through electrode, and a second portion on the first portion. There is no interface between the first portion and the second portion of the bump portion. In other words, the first portion and the second portion are integrally formed with each other. Further, the through electrode is integrally formed with the first portion and the second portion of the bump portion. In other words, there is also no interface between the through electrode and the bump portion.

[0032] Therefore, in the bump portion of the embodiment, no additional layer is disposed between the first portion and the second portion. Specifically, there is no seed layer between the first portion and the second portion of the bump portion. Through this, the embodiment can improve the physical and electrical connectivity between the first portion and the second portion of the bump portion. Further, the bump portion of the embodiment is also integrally formed with the through electrode, thereby further improving the electrical and physical reliability.

[0033] At this time, in the comparative example, the pad portion and the bump portion are formed by another plating process in which they are separated from each other. Therefore, the comparative example has problems such as a decrease in the electrical and physical connectivity between them and an increase in signal transmission loss. Further, the comparative example has a structure in which a seed layer is further disposed between the pad portion and the bump portion, and has a problem that the overall reliability of the bump portion is reduced due to the problem of the physical reliability of the seed layer.

[0034] In contrast, the embodiment has a structure in which the through electrode, the first portion of the bump portion, and the second portion of the bump portion are integrally formed with each other. Thereby, the embodiment can improve the electrical and physical connectivity between the through electrode and the bump portion. Thereby, the embodiment can improve the physical and electrical reliability of the circuit board.

[0035] Also, the bump portion of the embodiment includes a first metal layer, a second metal layer, and a third metal layer. The second metal layer is a first electrolytic plating layer electrolytically plated using the first metal layer as a seed layer, and the third metal layer is a second electrolytic plating layer electrolytically plated using the first metal layer and the second metal layer as seed layers.

[0036] Therefore, the embodiment can minimize the depth of the recesses generated in the etching process of the seed layer performed after the formation of the circuit layer. That is, the second metal layer can have higher strength than the first metal layer as an electrolytic plating layer. Therefore, the second metal layer can function as a barrier layer that minimizes the depth of the recesses generated on the side surface of the first metal layer in the etching process. Furthermore, the second metal layer can function to prevent the third metal layer from being deformed in the etching process. Therefore, the embodiment can minimize the depth of the recesses formed on the lower side surface of the bump portion by further including the second metal layer in the bump portion. Therefore, the embodiment can improve the physical reliability and electrical reliability of the bump portion.

[0037] Also, the third metal layer of the bump portion is electrolytically plated using not only the first metal layer but also the second metal layer as a seed layer. Thereby, the embodiment can minimize the thickness deviation between the plurality of bump portions included in the circuit board.

[0038] Specifically, looking at the circuit board of the comparative example, the plating of the bump portion is performed using only the electroless copper plating layer as a seed layer. At this time, the bump portion has a thickness of 100 μm or more. Thus, when plating a metal layer having a thickness of 100 μm or more, it is difficult to perform a plating process having a uniform thickness in the entire region with only the electroless copper plating layer. Therefore, in the circuit board of the comparative example, the thickness deviation of each bump portion exceeded 30% compared to the average value of the thicknesses of the plurality of bump portions. For example, when the average value was 100 μm, the thickness of at least one of the plurality of bump portions was less than 70 μm or exceeded 130 μm. Thereby, the circuit board of the comparative example performs the plating process so as to have a thickness larger than the target thickness in order to match the thicknesses of the respective bump portions. As a result, the comparative example had the problem that a polishing process had to be essentially included for thickness uniformity while finally matching the thickness of the bump portion to the target thickness, and the polishing process time increased.

[0039] In contrast, in the embodiment, not only the first metal layer of the bump portion but also the second metal layer is used as a seed layer to perform electrolytic plating of the third metal layer of the bump portion. Thereby, the embodiment can minimize the thickness deviation between the plurality of bump portions. Thereby, in the embodiment, the plating process can be performed on the condition that the bump portion has a thickness corresponding to the target thickness. Thereby, the embodiment can omit the polishing process or significantly shorten the polishing process time.

Brief Description of the Drawings

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Mode for Carrying Out the Invention

[0041] Hereinafter, with reference to the accompanying drawings, the preferred embodiments of this specification will be described in detail. However, the technical idea of the present invention is not limited to the partial embodiments described, and can be realized in various different forms. As long as it is within the scope of the technical idea of the present invention, one or more of the components can be selectively combined and replaced between the embodiments for use.

[0042] Also, the terms (including technical and scientific terms) used in the embodiments of the present invention are, unless clearly defined and described otherwise, construed to have a meaning generally understood by those having ordinary knowledge in the technical field to which the present invention pertains. Terms generally used like those defined in a dictionary can be interpreted in consideration of the meaning in the context of the related art.

[0043] Also, the terms used in the embodiments of the present invention are for the purpose of explaining the embodiments and are not intended to limit the present invention. In this specification, the singular form can also include the plural form unless otherwise particularly stated in the text, and when described as "at least one (or one or more) of A and (or) B, C", it can include one or more of all combinations that can be combined with A, B, and C.

[0044] Also, when explaining the components of the embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. can be used. Such terms are only for distinguishing the components from other components, and the essence, order, or procedure of the components are not determined by such terms.

[0045] And when a component is described as being "connected", "coupled", or "joined" to another component, that component can include not only the case where it is directly connected, coupled, or joined to the other component, but also the case where it is "connected", "coupled", or "joined" by one or more other components intervening between that component and the other component.

[0046] Also, when described as being formed or arranged "above or below" each component, above or below includes not only the case where two components are in direct contact with each other, but also the case where one or more other components are formed or arranged between the two components.

[0047] Also, when expressed as "above or below", it can include not only the upward direction but also the downward direction with respect to one component.

[0048] - Comparative Example -

[0049] FIG. 1 is a cross-sectional view showing a circuit board according to a comparative example.

[0050] Referring to FIG. 1, the circuit board includes an insulating layer 10.

[0051] And on the upper surface of the insulating layer 10, a first circuit pattern 20 is disposed, and on the lower surface of the insulating layer 10, a second circuit pattern 30 is disposed. The first circuit pattern 20 includes pads.

[0052] Also, the circuit board of the comparative example includes a through electrode that penetrates the insulating layer 10.

[0053] On the upper surface of the insulating layer 10, a protective layer 50 having an opening that overlaps in the vertical direction with the upper surface of the pad of the first circuit pattern 20 is disposed.

[0054] And on the pad of the first circuit pattern 20, a bump 70 is disposed.

[0055] The bump 70 has a certain height or thickness and protrudes on the pad of the first circuit pattern 20. Therefore, it is difficult to form the bump 70 by electroless plating.

[0056] Thereby, a seed layer 60 is disposed between the bump 70 and the pad of the first circuit pattern 20. The seed layer 60 is an electroless copper plating layer.

[0057] The seed layer 60 is disposed on the upper surface of the pad of the first circuit pattern 20 and the inner wall of the protective layer 50, respectively.

[0058] That is, the comparative example has a structure in which a seed layer 60 is disposed between the bump 70 and the pad of the first circuit pattern 20. Thereby, the comparative example has a problem that the step of forming the seed layer 60 should be further performed, which complicates the manufacturing process or increases the manufacturing time.

[0059] In addition, in the circuit board of the comparative example, a whitening phenomenon of the protective layer 50 occurs due to the solution used in the desmear process of the seed layer 60 formed by electroless plating. Also, the circuit board of the comparative example has a structure in which the seed layer 60 is disposed between the pad and the bump 70, and thus the bump layer has a porous fine structure. At this time, the porous structure has a low metal density, and thus there is a problem that cracks occur in the porous seed layer 60 due to external impact or other physical forces. And due to the occurrence of the cracks, the bump 70 is destroyed, resulting in a problem that the product reliability and durability are rapidly reduced.

[0060] Furthermore, the comparative example has a problem that the connection reliability between the pad and the bump 70 is reduced due to the structure in which the seed layer 60 is disposed.

[0061] Also, in the comparative example, a problem occurs in that the seed layer 60 is etched in the pretreatment process for the surface treatment of the bump 70, resulting in a problem that the bump 70 cannot function normally.

[0062] Also, the bump 70 of the comparative example is disposed on the pad with a width smaller than the width of the pad. Thereby, the pitch between the plurality of bumps corresponds to the pitch between the plurality of pads respectively connected to the plurality of bumps. And the pitch between the plurality of pads corresponds to the pitch between the plurality of through electrodes connected thereto.

[0063] At this time, the comparative example determines the pitch between the through electrodes, the pitch between the pads, and the pitch between the bumps in consideration of all of the tolerance in the process of forming the bump 70, the tolerance in the process of forming the pads of the first circuit pattern 20, and the tolerance in the process of forming the through holes of the through electrodes 40. Thereby, the comparative example has a limit in reducing the pitch between the plurality of bumps.

[0064] In the comparative example, plating of the bumps 70 is performed by a seed layer 60 separately disposed on the pads of the first circuit pattern 20. As a result, in the comparative example, there is a problem that the thickness deviation between the plurality of bumps 70 is large. Therefore, the comparative example has a problem that a polishing process for making the thicknesses of the plurality of bumps uniform should be essentially performed.

[0065] An embodiment provides a circuit board and a semiconductor package including the same, which can reduce the pitch between a plurality of bump posts to improve the integration degree of a circuit, improve the connection reliability between the pad portion and the bump portion of the bump posts, minimize the degree of concavity of recesses formed on the side surfaces of the lower regions, and minimize the thickness deviation of the plurality of bump posts.

[0066] - Electronic device -

[0067] Prior to the description of the embodiment, an electronic device including the semiconductor package of the embodiment will be briefly described. The electronic device includes a main board (not shown). The main board can be physically and / or electrically connected to various components. For example, the main board can be connected to the semiconductor package of the embodiment. Various elements can be mounted on the semiconductor package. Mainly, the semiconductor package can include various elements or chips. The elements or chips can include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, and application processor chips such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, and logic chips such as an analog-to-digital converter, an ASIC (application-specific IC), and the like.

[0068] Also, the elements or chips can include active elements and passive elements.

[0069] The active element means an element that actively utilizes the non-linear part of signal characteristics. And the passive element means an element that does not utilize non-linear signal characteristics even if both linear and non-linear signal characteristics exist. For example, the active element can include transistors, IC semiconductor elements, etc., and the passive element can include capacitors, resistors, inductors, etc. The passive element can increase the signal processing speed of the semiconductor chip that is the active element or perform a filtering function, etc. Also, the chip can be a wireless communication chip usable for Wi-Fi, 5G communication, etc.

[0070] On the other hand, the product group to which the semiconductor package of the embodiment is applied can be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0071] At this time, the electronic device can be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an Automotive, etc. However, it is needless to say that it is not limited thereto and can be any other electronic device that processes data in addition to these.

[0072] FIG. 2 is a cross-sectional view showing a circuit board according to an embodiment.

[0073] Hereinafter, with reference to FIG. 2, the overall configuration of the circuit board according to the embodiment will be described.

[0074] Referring to FIG. 2, the circuit board 100 allows at least one chip to be attached. Also, the circuit board 100 of the embodiment can be attached to the main board of the electronic device. The main board means the motherboard of the electronic device.

[0075] Also, the number of chips mounted on the circuit board 100 may be one, or alternatively, may be two or more. For example, one processor chip may be mounted on the circuit board 100. For example, at least two processor chips performing different functions from each other may be mounted on the circuit board 100. For example, one memory chip may be mounted on the circuit board 100 together with one processor chip. For example, at least two processor chips performing different functions from each other and at least one memory chip may be mounted on the circuit board 100.

[0076] The circuit board 100 includes an insulating layer 110.

[0077] At this time, the circuit board 100 of the embodiment may be a core board. For example, the circuit board 100 may include a second insulating layer 112 of the core layer.

[0078] For example, the circuit board 100 may have a structure in which a plurality of insulating layers having a mutually symmetric structure are laminated on the upper and lower portions thereof with the second insulating layer 112 as the center. However, the embodiment is not limited thereto. For example, a plurality of insulating layers having an asymmetric structure with respect to each other may be arranged on the upper and lower portions with the second insulating layer 112 as the center.

[0079] Hereinafter, it will be described assuming that the circuit board 100 of the embodiment is a core board, and thus the second insulating layer 112 is a core layer. However, the embodiment is not limited thereto. For example, the circuit board 100 of the embodiment may be a coreless board that does not include a core layer. The structural features of the circuit board 100 in the embodiment are in the outermost circuit layer of the circuit board 100. And hereinafter, the structure of the outermost circuit layer of the circuit board 100 of the embodiment will be mainly described.

[0080] As a result, the structure of the outermost circuit layer 120 of the circuit board 100 described below can be applied to a core board, and differently, can be applied to a coreless board. Furthermore, the structure of the outermost circuit layer 120 can be applied not only to the laminated structure of a general circuit board but also to a circuit board with an ETS (Embedded Trace Substrate) structure.

[0081] The circuit board 100 of the embodiment includes an insulating layer 110.

[0082] The insulating layer 110 can include a first insulating layer 111, a second insulating layer 112, and a third insulating layer 113 from the upper side.

[0083] The second insulating layer 112 can mean an inner insulating layer disposed in the inner layer among the plurality of insulating layers of the circuit board 100. The second insulating layer 112 can include a prepreg.

[0084] At this time, in the drawing, the first insulating layer 111 is shown as having a single-layer structure, but it is not limited thereto. For example, the first insulating layer 111 can have a multilayer structure. For example, the circuit board 100 can have a layer structure of four or more layers. And the first insulating layer 111 corresponding to the inner insulating layer of the circuit board 100 can have a plurality of layer structures based on the total number of layers of the circuit board 100.

[0085] The first insulating layer 111 can be disposed on the second insulating layer 112. For example, the first insulating layer 111 can be disposed on the upper surface of the second insulating layer 112.

[0086] The first insulating layer 111 can mean the outermost insulating layer in the insulating layer 110 of the circuit board 100. For example, the first insulating layer 111 can indicate the insulating layer disposed on the uppermost side in the insulating layer 110 of the circuit board 100. The first insulating layer 111 can provide a mounting area where chips are mounted or a bonding area where an external substrate such as a main board of an electronic device is bonded.

[0087] The third insulating layer 113 can be disposed on the lower surface of the second insulating layer 112. The third insulating layer 113 can mean the second outermost insulating layer in the insulating layer 110 of the circuit board 100. For example, the third insulating layer 113 can indicate the insulating layer disposed on the lowermost side in the insulating layer 110 of the circuit board 100.

[0088] The first insulating layer 111 and the third insulating layer 113 can be rigid or flexible. For example, the first insulating layer 111 and the third insulating layer 113 can include glass or plastic. Specifically, the first insulating layer 111 and the third insulating layer 113 can include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. Alternatively, the first insulating layer 111 and the third insulating layer 113 can include reinforced or ductile plastics such as polyimide PI (Polyimide), polyethylene terephthalate PET (Polyethylene terephthalate), propylene glycol PPG (Propylene glycol) polycarbonate PC, etc. Alternatively, the first insulating layer 111 and the third insulating layer 113 can include sapphire.

[0089] Also, the first insulating layer 111 and the third insulating layer 113 can include an optical isotropic film. As an example, the first insulating layer 111 and the third insulating layer 113 can include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate PC (Polycarbonate), or optically isotropic polymethyl methacrylate PMMA, etc.

[0090] Also, the first insulating layer 111 and the third insulating layer 113 can be formed of a material containing an inorganic filler and an insulating resin. For example, the first insulating layer 111 and the third insulating layer 113 can include a structure in which inorganic fillers such as silica and alumina are dispersed in a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide. For example, the first insulating layer 111 and the third insulating layer 113 can include ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imagable Dielectric resin), BT, etc.

[0091] Also, the first insulating layer 111 and the third insulating layer 113 can be bent while having a partially curved surface. That is, the first insulating layer 111 and the third insulating layer 113 can have a partially flat surface and can be bent while having a partially curved surface. More specifically, the first insulating layer 111 and the third insulating layer 113 can be bent while having a curved surface at the end or can be bent or flexed while having a surface with a random curvature.

[0092] Also, the first insulating layer 111 and the third insulating layer 113 can be a flexible substrate having flexible characteristics. Also, the first insulating layer 111 and the third insulating layer 113 can be a curved or bended substrate.

[0093] Each of the first insulating layer 111 and the third insulating layer 113 can have a thickness in the range of 10 μm to 60 μm. Preferably, each of the first insulating layer 111 and the third insulating layer 113 can have a thickness in the range of 12 μm to 50 μm. More preferably, each of the first insulating layer 111 and the third insulating layer 113 can have a thickness of 15 μm to 40 μm.

[0094] If the thickness of the first insulating layer 111 or the third insulating layer 113 is less than 10 μm, the circuit layers included in the circuit board 100 may not be stably protected.

[0095] In addition, when the thickness of the first insulating layer 111 or the third insulating layer 113 exceeds 60 μm, the thickness of the circuit board 100 can be increased, and thereby the thickness of the semiconductor package can be increased. Further, when the thickness of the first insulating layer 111 or the third insulating layer 113 exceeds 60 μm, correspondingly, the thickness of the circuit layer and the thickness of the through electrode can be increased. And when the thickness of the circuit layer and the thickness of the through electrode increase, it is difficult to implement miniaturization, so the integration degree of the circuit may decrease, and the signal transmission distance increases and the signal transmission loss can increase.

[0096] The circuit board 100 of the embodiment includes a circuit layer disposed in the insulating layer 110.

[0097] For example, the circuit board 100 may include a first circuit layer 120 disposed on the upper surface of the first insulating layer 111.

[0098] For example, the circuit board 100 may include a second circuit layer 130 disposed between the lower surface of the first insulating layer 111 and the upper surface of the second insulating layer 112.

[0099] For example, the circuit board 100 may include a third circuit layer 140 disposed between the lower surface of the second insulating layer 112 and the upper surface of the third insulating layer 113.

[0100] For example, the circuit board 100 may include a fourth circuit layer 150 disposed on the lower surface of the third insulating layer 113.

[0101] The first circuit layer 120, the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 are possible by an additive process, a subtractive process, an MSAP (Modified Semi Additive Process), an SAP (Semi Additive Process) method, etc., which are the manufacturing processes of a normal circuit board, and detailed descriptions are omitted here.

[0102] The first circuit layer 120 can mean a circuit layer disposed on the first outermost layer of the circuit board 100. And the fourth circuit layer 140 can mean a circuit layer disposed on the second outermost layer of the circuit board 100.

[0103] The first circuit layer 120 can have a structure protruding on the upper surface of the first insulating layer 111. Also, the fourth circuit layer 140 can have a structure protruding below the lower surface of the third insulating layer 113. However, the embodiments are not limited thereto. For example, when the circuit board 100 of the embodiment has an ETS structure, either one of the first circuit layer 120 and the fourth circuit layer 140 (preferably, the fourth circuit layer) can have a structure embedded in the surface of the insulating layer.

[0104] The first circuit layer 120 can be divided into a plurality of circuit patterns according to functions.

[0105] For example, the first circuit layer 120 can include a first circuit pattern 121, a second circuit pattern 122, and a third circuit pattern 123.

[0106] The first circuit pattern 121 functions as a metal bump portion for coupling an external substrate (for example, the main board of an electronic device) onto the circuit board 100. Thus, the first circuit pattern 121 can also be referred to as a "bump portion". Hereinafter, the first circuit pattern 121 will be described as a "bump portion".

[0107] The second circuit pattern 122 functions as a mounting pad for mounting a chip onto the circuit board 100. Thus, the second circuit pattern 122 can also be referred to as a "pad". Hereinafter, the second circuit pattern 122 will be described as a "pad".

[0108] The third circuit pattern 123 is connected to at least one of the first circuit pattern 121 and the second circuit pattern 122 and functions as a trace that performs a wiring function. Thus, the third circuit pattern 123 can also be referred to as a "trace". Hereinafter, the third circuit pattern 123 will be described as a "trace".

[0109] The bump portion 121 can have a thickness different from that of the pad 122 and the trace 123. Preferably, the bump portion 121 may be larger than the thicknesses of the pad 122 and the trace 123. And the pad 122 and the trace 123 can have the same thickness as each other. Here, having the same thickness as each other can mean that the thickness difference between the pad 122 and the trace 123 is 5 μm or less, 4 μm or less, 3 μm or less, 2 μm or less, or 1 μm or less.

[0110] The thickness of the bump portion 121 may be 3 times or more the thickness of the pad 122 or the trace 123. For example, the thickness of the bump portion 121 may be 5 times or more the thickness of the pad 122 or the trace 123. For example, the thickness of the bump portion 121 may be 7 times the thickness of the pad 122 or the trace 123. For example, the thickness of the bump portion 121 may be 10 times or more the thickness of the pad 122 or the trace 123.

[0111] At this time, the fact that the thickness of the bump portion 121 is larger than the thickness of the pad 122 or the trace 123 does not mean that the number of metal layers constituting the bump portion 121 is larger than the number of metal layers constituting the pad 122 or the trace 123. In other words, the number of metal layers constituting the bump portion 121 is the same as the number of metal layers constituting the pad 122 or the trace 123. That is, the layer structure of the bump portion 121 is the same as the layer structure of the pad 122 or the trace 123. However, the thickness of any one of the metal layers constituting the bump portion 121 is larger than the thickness of the corresponding metal layer of the pad 122 or the trace 123.

[0112] Thereby, the thickness of the bump portion 121 is larger than the thickness of the pad 122 or the trace 123.

[0113] The bump portion 121 can be divided into a plurality of parts. The bump portion 121 can be divided into a first part 121P and a second part 121B with respect to the thickness direction. At this time, the division of the first part 121P and the second part 121B does not mean layer division. Specifically, the first part 121P and the second part 121B are a single structure formed integrally with each other, provided that this can be divided based on the pad 122 or the trace 123.

[0114] The first part 121P of the bump portion 121 can mean the pad portion of the bump portion 121. The first part 121P of the bump portion 121 can have a thickness corresponding to the thickness of the pad 122 or the trace 123.

[0115] The second part 121B of the bump portion 121 is disposed on the first part 121P of the bump portion 121. The second part 121B of the bump portion 121 can be said to be the bump portion of the bump portion 121.

[0116] Thereby, the bump portion 121 may be larger than the thickness of the pad 122 or the trace 123 by the thickness of the second part 121B.

[0117] For this reason, the bump portion 121 can be formed through a plating process different from that of the pad 122 or the trace 123. However, the embodiment is not limited thereto. The first part 121P of the bump portion 121 may be formed in the plating process of the pad 122 or the trace 123, or an additional plating process may be performed to form the second part 121B of the bump portion 121 integral with the first part 121P.

[0118] Through this, in the bump portion 121 of the embodiment, no additional layer is disposed between the first portion 121P and the second portion 121B. Specifically, there is no seed layer between the first portion 121P and the second portion 121B of the bump portion 121. Through this, the embodiment can improve the physical and electrical connectivity between the first portion 121P and the second portion 121B of the bump portion 121. Also, the widths of the first portion 121P and the second portion 121B of the bump portion 121 can correspond to each other. Here, the width of the first portion 121P can mean the width at a position that does not horizontally overlap with the recess (121U in FIG. 22) included in the lower region of the first portion 121P. Thereby, the embodiment can determine the pitch between a plurality of bump portions 121a and 121b based on the pitch of the second portion 121B of the bump portion 121.

[0119] The detailed structures of the bump portion 121, the pad 122, and the trace 123 of the first circuit layer 120 will be described in more detail below.

[0120] The second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 can have a layer structure different from that of the first circuit layer 120. For example, the number of metal layers of the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 can be different from the number of metal layers of the first circuit layer 120. For example, the number of metal layers of the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 may be less than the number of metal layers of the first circuit layer 120.

[0121] Specifically, the first circuit layer 120, the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 each include a metal layer corresponding to the seed layer. And the number of seed layers of the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 may be less than the number of seed layers of the first circuit layer 120.

[0122] However, the fourth circuit layer 150 is the second outermost circuit layer of the circuit board and can be formed together with the first circuit layer 120 during the formation of the first circuit layer 120. Thus, in order to improve processability, the embodiment can have the fourth circuit layer 150 with a layer structure corresponding to that of the first circuit layer 120.

[0123] The first circuit layer 120, the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 can be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Also, the first circuit layer 120, the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 can be formed of a paste or a solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) having excellent bonding force. Preferably, the first circuit layer 120, the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 can be formed of copper (Cu) which is relatively inexpensive.

[0124] The second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 can have a thickness in the range of 5 μm to 20 μm. For example, the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 can have a thickness in the range of 6 μm to 17 μm. The second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 can have a thickness in the range of 7 μm to 13 μm. When the thickness of the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 is less than 5 μm, the resistance can increase. When the thickness of the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150 exceeds 20 μm, it is difficult to miniaturize the circuit, and the circuit integration degree may decrease accordingly.

[0125] On the other hand, the pads 122 and the traces 123 of the first circuit layer 120 can have a thickness corresponding to the thicknesses of the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150.

[0126] And the bump portion 121 of the first circuit layer 120 may be larger than the thicknesses of the pad 122, the trace 123, the second circuit layer 130, the third circuit layer 140, and the fourth circuit layer 150.

[0127] The thickness of the bump portion 121 of the first circuit layer 120 can exceed 100 μm. The thickness of the bump portion 121 of the first circuit layer 120 can exceed 120 μm. The thickness of the bump portion 121 of the first circuit layer 120 can exceed 140 μm. The thickness of the bump portion 121 of the first circuit layer 120 can exceed 160 μm. The thickness of the bump portion 121 of the first circuit layer 120 can exceed 200 μm.

[0128] The thickness of the bump portion 121 of the first circuit layer 120 can satisfy the range of 100 μm to 220 μm. Preferably, the thickness of the bump portion 121 of the first circuit layer 120 can satisfy the range of 110 μm to 215 μm. More preferably, the thickness of the bump portion 121 of the first circuit layer 120 can satisfy the range of 115 μm to 210 μm.

[0129] If the thickness of the bump portion 121 of the first circuit layer 120 is less than 100 μm, an external substrate (for example, the main board of an electronic device) may not be stably bonded onto the first bump portion 121. For example, if the thickness of the bump portion 121 of the first circuit layer 120 exceeds 220 μm, the rigidity of the bump portion 121 may decrease, and as a result, reliability problems such as collapse may occur when the external substrate is bonded. Also, if the thickness of the bump portion 121 of the first circuit layer 120 exceeds 220 μm, the thickness deviation between a plurality of bump portions becomes large, and thereby the time for the polishing process can increase. Further, if the thickness of the bump portion 121 of the first circuit layer 120 exceeds 220 μm, the thickness of the circuit board 100 and the thickness of the semiconductor package can increase.

[0130] The circuit board of the embodiment can include a through electrode.

[0131] Specifically, the through electrodes can penetrate the insulating layer 110. Preferably, the through electrodes include a first through electrode 160 that penetrates the first insulating layer 111. Also, the through electrodes include a second through electrode 170 that penetrates the second insulating layer 112. Also, the through electrodes include a third through electrode 180 that penetrates the third insulating layer 113.

[0132] The first through electrode 160, the second through electrode 170, and the third through electrode 180 can be disposed in through holes that penetrate their respective insulating layers. For example, the first through electrode 160, the second through electrode 170, and the third through electrode 180 can be formed by filling the through holes with a conductive material.

[0133] The through holes can be formed by any one of machining methods such as mechanical, laser, and chemical machining. The through holes can be formed by machining methods such as milling, drill, and routing. Also, UV or CO2 laser methods can be used for the through holes. Also, for the first through hole, a chemical machining method using chemicals such as aminosilane and ketones can be used.

[0134] When the through holes are formed, the inside of the through holes can be filled with any one metal material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd) to form the first through electrode 160, the second through electrode 170, and the third through electrode 180. At this time, for the filling of the conductive material, any one or a combination of methods such as electroless plating, electroplating, screen printing, sputtering, evaporation method, inkjetting, and dispensing can be used.

[0135] On the other hand, a plurality of first through electrodes 160 can be formed horizontally spaced apart within the first insulating layer 111.

[0136] At this time, the first through electrode 160 can overlap with the first circuit layer 120 in the vertical direction. And the first through electrode 160 can include a first-1 through electrode 160a that overlaps with the bump portion 121 of the first circuit layer 120 in the vertical direction. Also, the first through electrode 160 can include a first-2 through electrode 160b that overlaps with the pad 122 of the first circuit layer 120 in the vertical direction.

[0137] At this time, the first through electrode 160 is formed integrally with the first circuit layer 120. This is because the filling inside the through hole penetrating the first insulating layer 111 and the plating process for forming the circuit layer on the first insulating layer 111 are performed simultaneously.

[0138] Therefore, the pad 122 can be formed integrally with the first-2 through electrode 160b. Here, being formed integrally means that at least one metal layer constituting the pad 122 and at least one metal layer constituting the first-2 through electrode are plating layers formed by one plating process.

[0139] Furthermore, the bump portion 121 can be formed integrally with the first-1 through electrode 160a. For example, the second portion 121B corresponding to the bump portion of the bump portion 121 is formed integrally with the first portion 121P corresponding to the pad portion of the bump portion 121. And the first portion 121P of the bump portion 121 is formed integrally with the first-1 through electrode 160a. Therefore, the second portion 121B of the bump portion 121 is formed integrally with the first-1 through electrode 160a.

[0140] At this time, in the comparative example, the through electrode and the pad of the bump portion are formed integrally with each other, but the through electrode and the bump of the bump portion are metal layers separated by a separate process. As a result, in the comparative example, there was a problem that the electrical and physical connectivity between them decreased and the signal transmission loss increased.

[0141] In contrast, the embodiment has a structure in which the first-through electrode 160a, the first portion 121P of the bump portion 121, and the second portion 121B of the bump portion 121 are integrally formed with each other. Thereby, the embodiment can improve the electrical and physical connectivity between the first-through electrode 160a and the bump portion 121. Thereby, the embodiment can improve the physical reliability and electrical reliability of the circuit board.

[0142] The circuit board 100 of the embodiment includes a protective layer.

[0143] Specifically, a first protective layer 195 is disposed on the upper surface of the first insulating layer 111. The first protective layer 195 includes at least one opening. Specifically, the first protective layer 195 includes an opening that overlaps the bump portion 121 of the first circuit layer 120 in the vertical direction. At this time, the width of the opening of the first protective layer 195 may be the same as the width of the bump portion 121.

[0144] Here, in the comparative example, the width of the opening of the first protective layer was larger or smaller than the width of the bump portion. This is because it is difficult to substantially equalize the width of the opening of the first protective layer and the width of the bump portion due to the tolerance in the exposure and development processes of the first protective layer. Thereby, in the comparative example, the width of the opening of the first protective layer was increased or the width of the bump portion was increased in consideration of the tolerance. Thereby, in the comparative example, there was a limit to reducing the pitch between the plurality of bump portions.

[0145] In contrast, the embodiment forms the first protective layer 195 after forming the bump portion 121 with a certain thickness. Thereby, the embodiment can make the width of the bump portion 121 and the width of the opening of the first protective layer 195 substantially equal. Through this, the embodiment can further reduce the pitch between the plurality of bump portions. Thereby, the embodiment can improve the circuit integration degree of the circuit board.

[0146] On the other hand, the circuit board 100 can further include a second protective layer 195 disposed on the lower surface of the third insulating layer 113.

[0147] The first protective layer 195 and the second protective layer 195 can contain an insulating material. The first protective layer 195 and the second protective layer 195 can contain various materials that can be heated and cured after being applied to protect the surfaces of the insulating layer and the circuit layer.

[0148] The first protective layer 195 and the second protective layer 195 can be solder resist layers containing organic polymer materials. As an example, the first protective layer 195 and the second protective layer 195 can contain epoxy acrylate-based resins. Specifically, the first protective layer 195 and the second protective layer 195 can contain resins, curing agents, photoinitiators, pigments, solvents, fillers, additives, acrylic monomers, etc. However, the embodiments are not limited thereto, and it goes without saying that the first protective layer 195 and the second protective layer 195 can be any one of a photosolder resist layer, a cover-lay, and a polymer material.

[0149] The thickness of the first protective layer 195 and the second protective layer 195 can be 1 μm to 20 μm. The thickness of the first protective layer 195 and the second protective layer 195 can be 1 μm to 15 μm. For example, the thickness of the first protective layer 195 and the second protective layer 195 can be 5 μm to 20 μm. When the thickness of the first protective layer 195 and the second protective layer 195 exceeds 20 μm, the overall thickness of the circuit board and the semiconductor package can increase.

[0150] On the other hand, in the drawings, the circuit board is shown as including the first protective layer 195 and the second protective layer 195, but it is not limited thereto.

[0151] For example, at least one of the first protective layer 195 and the second protective layer 195 can be omitted.

[0152] Preferably, in the circuit board 100 of FIG. 2, the first protective layer 195 may be omitted. As a result, the upper surface and the upper and side surfaces of the first circuit layer 120 of the first insulating layer 111 may be exposed to the outside of the circuit board 100. Then, at least a part of the upper surface and the upper and side surfaces of the first insulating layer 111 and the first circuit layer 120 may be covered by a molding layer in the semiconductor packaging process.

[0153] On the other hand, although not shown in the drawings, a surface treatment layer may be disposed on the first circuit layer 120 of the circuit board 100. For example, the surface treatment layer may be disposed on at least one of the upper surfaces of the bump portions 121 and the pads 122 of the first circuit layer 120. The surface treatment layer may be formed to enhance solderability while preventing corrosion and oxidation of the circuit layer.

[0154] The surface treatment layer may be an OSP (Organic Solderability Preservative) layer. Preferably, the surface treatment layer may be an organic layer formed of an organic substance such as benzimidazole coated on the circuit layer.

[0155] Alternatively, the surface treatment layer may be a plating layer. For example, the surface treatment layer may include an electrolessly plated gold (Au) plating layer. For example, the surface treatment layer may include an electrolessly plated nickel (Ni) plating layer and an electrolessly plated gold (Au) plating layer on the nickel plating layer. For example, the surface treatment layer may include an electrolessly plated nickel (Ni) plating layer, an electrolessly plated palladium (Pd) plating layer on the nickel plating layer, and an electrolessly plated gold (Au) plating layer on the palladium plating layer.

[0156] Hereinafter, the circuit layers included in the circuit board of the embodiment will be described more specifically.

[0157] FIG. 3 is a cross-sectional view showing the layer structure of the bump portion of the first circuit layer of the first embodiment, FIG. 4 is a cross-sectional view showing the layer structure of the pad of the first circuit layer of the first embodiment, FIG. 5 is a cross-sectional view showing the layer structure of the trace of the first circuit layer of the first embodiment, FIG. 6 is a cross-sectional view showing the layer structure of the second circuit layer of the embodiment, and FIG. 7 is a cross-sectional view showing the layer structure of the bump portion of the first circuit layer of the second embodiment.

[0158] Referring back to FIG. 2 for a moment, the first circuit layer 120 includes a bump portion 121, a pad 122, and a trace 123. The first circuit layer 120, the bump portion 121, and the pad 122 have the same layer structure as each other, while at least one has a thickness different from that of at least one other.

[0159] On the other hand, the second circuit layer 130 has a layer structure different from that of the first circuit layer 120. For example, the second circuit layer 130 has a smaller number of layers than the first circuit layer 120. For example, the number of seed layer of the second circuit layer 130 is less than the number of seed layer of the first circuit layer 120.

[0160] On the other hand, the first circuit layer 120 of the embodiment can have different layer structures depending on the manufacturing method. For example, when the first circuit layer 120 is manufactured by the SAP method, the first circuit layer 120 includes only the first to third metal layers 121-1, 121-2, 121-3 that do not include the fourth metal layer 121-4 corresponding to the copper foil layer. And when the first circuit layer 120 is manufactured by the MSAP method, the first circuit layer 120 can include the first to fourth metal layers 121-1, 121-2, 121-3, 121-4 including the copper foil layer.

[0161] Referring to FIG. 3, the circuit board 100 includes a first-1 through electrode 160a that penetrates the first insulating layer 111 and a bump portion 121 of the first circuit layer 120 disposed on the first-1 through electrode 160a.

[0162] At this time, the first-1 through electrode 160a and the bump portion 121 are integrally formed.

[0163] The bump portion 121 includes a plurality of metal layers. And the first through electrode 160a also includes a plurality of metal layers corresponding to the plurality of metal layers of the bump portion 121. And each of the plurality of metal layers of the bump portion 121 is integrally formed with the corresponding metal layer among the plurality of metal layers of the first through electrode 160a. Being integrally formed can mean that any one of the plurality of metal layers constituting the bump portion 121 and any one of the plurality of metal layers constituting the first through electrode 160a are formed of one layer.

[0164] The bump portion 121 includes a first metal layer 121-1. The first metal layer 121-1 is disposed on the upper surface of the first insulating layer 111 in the circuit board of the first embodiment.

[0165] The first metal layer 121-1 of the bump portion 121 can be an electroless plating layer. For example, the first metal layer 121-1 of the bump portion 121 can be a chemical copper plating layer.

[0166] For example, the first metal layer 121-1 of the bump portion 121 can be formed by a chemical copper plating method performed in the order of a degreasing process, a soft etching process, a pre-catalyst treatment process, a catalyst treatment process, an activation process, an electroless plating process, and an antioxidant treatment process.

[0167] The first metal layer 121-1 of the bump portion 121 can have a first thickness. The first thickness of the first metal layer 121-1 of the bump portion 121 can satisfy the range of 0.5 μm to 1.5 μm. Preferably, the first thickness of the first metal layer 121-1 of the bump portion 121 can satisfy the range of 0.7 μm to 1.3 μm. More preferably, the first thickness of the first metal layer 121-1 of the bump portion 121 can satisfy the range of 0.8 μm to 1.2 μm. If the first thickness of the first metal layer 121-1 of the bump portion 121 is less than 0.5 μm, the first metal layer 121-1 may not function properly as a seed layer. If the first thickness of the first metal layer 121-1 of the bump portion 121 is greater than 1.5 μm, the reliability of the bump portion 121 may decrease. For example, if the first thickness of the first metal layer 121-1 of the bump portion 121 is greater than 1.5 μm, in the etching process of the first metal layer 121-1 performed after the formation of the bump portion 121, the depth of the recess (or undercut) can increase. Also, if the first thickness of the first metal layer 121-1 of the bump portion 121 is greater than 1.5 μm, the etching process time can increase. Further, if the first thickness of the first metal layer 121-1 of the bump portion 121 is greater than 1.5 μm, deformation of the third metal layer 123 of the bump portion 121 may occur in the etching process of the first metal layer 121-1.

[0168] The bump portion 121 can include a second metal layer 121-2 disposed on the first metal layer 121-1. The second metal layer 121-2 of the bump portion 121 can be an electrolytic plating layer. For example, the second metal layer 121-2 of the bump portion 121 can be a first electrolytic plating layer formed by electrolytically plating using the first metal layer 121-1 of the bump portion 121 as a seed layer.

[0169] The second metal layer 121-2 of the bump portion 121 can have a second thickness greater than the first thickness of the first metal layer 121-1 of the bump portion 121. For example, the second thickness of the second metal layer 121-2 of the bump portion 121 may be 1.3 times or more the first thickness of the first metal layer 121-1 of the bump portion 121. For example, the second thickness of the second metal layer 121-2 of the bump portion 121 may be 1.5 times or more the first thickness of the first metal layer 121-1 of the bump portion 121. For example, the second thickness of the second metal layer 121-2 of the bump portion 121 may be 2 times or more the first thickness of the first metal layer 121-1 of the bump portion 121.

[0170] The second thickness of the second metal layer 121-2 of the bump portion 121 can satisfy the range of 3 μm to 5 μm. For example, the second thickness of the second metal layer 121-2 of the bump portion 121 can satisfy the range of 3.2 μm to 4.8 μm. For example, the second thickness of the second metal layer 121-2 of the bump portion 121 can satisfy the range of 3.5 μm to 4.5 μm.

[0171] If the second thickness of the second metal layer 121-2 of the bump portion 121 is less than 3 μm, the effect manifested by the formation of the second metal layer 121-2 may be insufficient. For example, the second metal layer 121-2 of the bump portion 121 can function to reduce the depth of the recess in the etching process of the first metal layer 121-1 while improving the processability in the plating process of the bump portion 121. For example, the second metal layer 121-2 of the bump portion 121 can function to reduce the thickness deviation between a plurality of bump portions. And if the second thickness of the second metal layer 121-2 of the bump portion 121 is less than 3 μm, the effect by the second metal layer 121-2 may be insufficient. If the second thickness of the second metal layer 121-2 of the bump portion 121 exceeds 5 μm, the process time in the process of etching the second metal layer 121-2 can increase.

[0172] The first metal layer 121-1 and the second metal layer 121-2 of the bump portion 121 function as a seed layer for forming the third metal layer 121-3 by electrolytic plating. The metal layer 121-1 functions as a seed layer for forming the second metal layer 121-2 by electrolytic plating. And the first metal layer 121-1 and the second metal layer 121-2 function as a seed layer for forming the third metal layer 121-3 by electrolytic plating.

[0173] That is, the bump portion 121 includes a third metal layer 121-3 disposed on the second metal layer 121-2 of the bump portion 121. The third metal layer 121-3 is an electrolytic plating layer formed by electrolytically plating the first metal layer 121-1 and the second metal layer 121-2 as seed layers. For example, the third metal layer 121-3 of the bump portion 121 can also be referred to as the second electrolytic plating layer of the bump portion 121.

[0174] The third thickness of the third metal layer 121-3 of the bump portion 121 can exceed 95 μm. For example, the third thickness of the third metal layer 121-3 of the bump portion 121 can exceed 115 μm. The third thickness of the third metal layer 121-3 of the bump portion 121 can exceed 135 μm. The third thickness of the third metal layer 121-3 of the bump portion 121 can exceed 155 μm. The third thickness of the third metal layer 121-3 of the bump portion 121 can exceed 195 μm.

[0175] That is, the bump portion 121 includes the first metal layer 121-1, the second metal layer 121-2, and the third metal layer 121-3. And the thickness T1 of the bump portion 121 including the first metal layer 121-1, the second metal layer 121-2, and the third metal layer 121-3 can satisfy the range of 100 μm to 220 μm. Preferably, the thickness T1 of the bump portion 121 can satisfy the range of 110 μm to 215 μm. More preferably, the thickness T1 of the bump portion 121 can satisfy the range of 115 μm to 210 μm.

[0176] If the thickness T1 of the bump portion 121 is less than 100 μm, the external substrate (for example, the main board of an electronic device) may not be stably bonded onto the first bump portion 121. For example, if the thickness T1 of the bump portion 121 exceeds 220 μm, the rigidity of the bump portion 121 may decrease, and reliability problems such as collapse may occur when the external substrate is bonded. Also, if the thickness T1 of the bump portion 121 exceeds 220 μm, the thickness deviation between a plurality of bump portions becomes large, which may increase the time of the polishing process. Further, if the thickness T1 of the bump portion 121 exceeds 220 μm, the thickness of the circuit board 100 and the thickness of the semiconductor package may increase.

[0177] In the embodiment, the bump portion 121 includes a first metal layer 121-1, a second metal layer 121-2, and a third metal layer 121-3. The second metal layer 121-2 is a first electrolytic plating layer electrolytically plated using the first metal layer 121-1 as a seed layer, and the third metal layer 121-3 is a second electrolytic plating layer electrolytically plated using the first metal layer 121-1 and the second metal layer 121-2 as seed layers.

[0178] Therefore, the embodiment can minimize the depth of the recesses generated in the etching process of the seed layer performed after the formation of the circuit layer. That is, the second metal layer 121-2 can have a higher metal density than the first metal layer 121-1 as an electrolytic plating layer. Therefore, the second metal layer 121-2 can function as a barrier layer that minimizes the depth of the recesses generated on the side surface of the first metal layer 121-1 in the etching process. Further, the second metal layer 121-2 can function to prevent the third metal layer 121-3 from being deformed in the etching process. Therefore, the embodiment can minimize the depth of the recesses formed on the side surface of the lower part of the bump portion 121 by further including the second metal layer 121-2 in the bump portion 121. Therefore, the embodiment can improve the physical reliability and electrical reliability of the bump portion 121.

[0179] Further, the third metal layer 121-3 of the bump portion 121 is electrolytically plated using not only the first metal layer 121-1 but also the second metal layer 121-2 as a seed layer. Thereby, the embodiment can minimize the thickness deviation between a plurality of bump portions included in the circuit board 100.

[0180] Specifically, looking at the circuit board of the comparative example, the plating of the bump portion is performed using only the electroless copper plating layer as a seed layer. At this time, the bump portion has a thickness of 100 μm or more. Thus, when plating a metal layer having a thickness of 100 μm or more, it is difficult to perform a plating process having a uniform thickness in all regions with only the electroless copper plating layer. Therefore, in the circuit board of the comparative example, the thickness deviation of each bump portion exceeded 30% compared to the average value of the thicknesses of the plurality of bump portions. For example, when the average value is 100 μm, the thickness of at least one of the plurality of bump portions is less than 70 μm or exceeds 130 μm. Thereby, the circuit board of the comparative example performs the plating process so as to have a thickness larger than the target thickness in order to match the thicknesses of the respective bump portions. As a result, the comparative example finally has a problem that a polishing process must be included for thickness uniformity while matching the thickness of the bump portion to the target thickness, and the polishing process time increases.

[0181] In contrast, in the embodiment, electrolytic plating of the third metal layer 121-3 of the bump portion 121 is performed using not only the first metal layer 121-1 but also the second metal layer 121-2 as a seed layer. Thereby, the embodiment can minimize the thickness deviation between a plurality of bump portions. Thereby, in the embodiment, the plating process can be performed under the condition that the bump portion 121 has a thickness corresponding to the target thickness. Thereby, the embodiment can omit the polishing process or significantly shorten the polishing process time.

[0182] Specifically, the circuit board 100 of the embodiment includes a plurality of bump portions 121a and 121b that are horizontally spaced apart from each other. And in the embodiment, based on the average value of the thicknesses of the plurality of bump portions 121a and 121b, the thickness deviation of each bump portion 121a and 121b can be adjusted to be 20% or less. For example, in the embodiment, based on the average value of the thicknesses of the plurality of bump portions 121a and 121b, the thickness deviation of each bump portion 121a and 121b can be adjusted to be 15% or less. For example, in the embodiment, based on the average value of the thicknesses of the plurality of bump portions 121a and 121b, the thickness deviation of each bump portion 121a and 121b can be adjusted to be 10% or less.

[0183] On the other hand, the first through electrode 160 of the circuit board of the embodiment includes a first-1 through electrode 160a that overlaps the bump portion 121 in the vertical direction. And the first-1 through electrode 160a can have a layer structure corresponding to the bump portion 121.

[0184] For example, the first-1 through electrode 160a can include a first metal layer 161, a second metal layer 162, and a third metal layer 163 of the first-1 through electrode 160a corresponding to the first metal layer 121-1, the second metal layer 121-2, and the third metal layer 121-3 of the bump portion 121.

[0185] The first metal layer 161 of the first-1 through electrode 160a can correspond to the first metal layer 121-1 of the bump portion 121. In other words, the first metal layer 161 of the first-1 through electrode 160a can be formed integrally with the first metal layer 121-1 of the bump portion 121.

[0186] Also, the second metal layer 162 of the first-1 through electrode 160a can correspond to the second metal layer 121-2 of the bump portion 121. In other words, the second metal layer 162 of the first-1 through electrode 160a can be formed integrally with the second metal layer 121-2 of the bump portion 121.

[0187] Further, the third metal layer 163 of the first-through electrode 160a can correspond to the third metal layer 121-3 of the bump portion 121. That is, the third metal layer 163 of the first-through electrode 160a can be formed integrally with the third metal layer 121-3 of the bump portion 121.

[0188] Thereby, the bump portion 121 of the embodiment can have a structure formed integrally with the first-through electrode 160 and the first-through electrode 160a.

[0189] On the other hand, referring to FIG. 4, the first circuit layer 120 includes a pad 122. At this time, the thickness T2 of the pad 122 is smaller than the thickness T1 of the bump portion 121.

[0190] At this time, the pad 122 includes first to third metal layers 122-1, 122-2, and 122-3.

[0191] The first and second metal layers 122-1 and 122-2 of the pad 122 correspond to the first metal layer 121-1 and the second metal layer 121-2 of the bump portion 121.

[0192] At this time, the third metal layer 122-3 of the pad 122 is the same as the third metal layer 121-3 of the bump portion 121 in that the first and second metal layers 122-1 and 122-2 of the pad 122 are used as seed layers for electrolytic plating.

[0193] However, the thickness of the third metal layer 122-3 of the pad 122 is smaller than the thickness of the third metal layer 121-3 of the bump portion 121. In other words, the thickness of the third metal layer 122-3 of the pad 122 can be determined based on the total thickness T2 of the pad 122.

[0194] The circuit board 100 also includes a first-through electrode 160b that overlaps the pad 122 in the vertical direction.

[0195] The first-through electrode 160b can have a layer structure corresponding to the layer structure of the pad 122.

[0196] For example, the first-through second via electrode 160b can include a first metal layer 161 of the first-through second via electrode 160b corresponding to the first metal layer 122-1 of the pad 122. The first metal layer 161 of the first-through second via electrode 160b can be formed integrally with the first metal layer 122-1 of the pad 122.

[0197] For example, the first-through second via electrode 160b can include a second metal layer 162 of the first-through second via electrode 160b corresponding to the second metal layer 122-2 of the pad 122. The second metal layer 162 of the first-through second via electrode 160b can be formed integrally with the second metal layer 122-2 of the pad 122.

[0198] For example, the first-through second via electrode 160b can include a third metal layer 163 of the first-through second via electrode 160b corresponding to the third metal layer 122-3 of the pad 122. The third metal layer 163 of the first-through second via electrode 160b can be formed integrally with the third metal layer 122-3 of the pad 122.

[0199] On the other hand, referring to FIG. 5, the trace 123 of the first circuit layer 120 can include first to third metal layers 123-1, 123-2, and 123-3.

[0200] At this time, the first to third metal layers 123-1, 123-2, and 123-3 of the trace 123 can correspond to the first to third metal layers 122-1, 122-2, and 122-3 of the pad 122. And the thickness T3 of the trace 123 can correspond to the thickness T2 of the pad 122.

[0201] Accordingly, specific descriptions of the first to third metal layers 123-1, 123-2, and 123-3 of the trace 123 are omitted.

[0202] On the other hand, referring to FIG. 6, the second circuit layer 130 of the circuit board 100 can have a layer structure different from that of the first circuit layer 120. For example, the number of layers of the second circuit layer 130 can be different from the number of layers of the first circuit layer 120. For example, the number of metal layers of the second circuit layer 130 can be less than the number of metal layers of the first circuit layer 120.

[0203] Correspondingly, the second through electrode 170 penetrating the second insulating layer 112 of the circuit board 100 can have a layer structure different from that of the first through electrode 160. For example, the second through electrode 170 can include a metal layer having a smaller number of layers than the number of metal layers of the first through electrode 160.

[0204] For example, the second circuit layer 130 includes a first metal layer 130-1 corresponding to the first metal layer 122-1 or 123-1 of the pad 122 or trace 123 of the first circuit layer 120. Further, the second circuit layer 130 includes a third metal layer 130-2 corresponding to the third metal layer 122-3 or 123-3 of the pad 122 or trace 123 of the first circuit layer 120. In other words, the second circuit layer 130 can have a structure that does not include the second metal layer 122-2 or 123-2 of the pad 122 or trace 123 as compared with the pad 122 or trace 123 of the first circuit layer 120.

[0205] Also, the second through electrode 170 includes a first metal layer 171 corresponding to the first metal layer 160-1 of the first-1 through electrode 160a or the first-2 through electrode 160b. Further, the second through electrode 170 includes a second metal layer 172 corresponding to the third metal layer of the first-1 through electrode 160a or the first-2 through electrode 160b. In other words, the second through electrode 170 can have a structure that does not include the second metal layer 160-2 of the first-1 through electrode 160a or the first-2 through electrode 160b as compared with the first-1 through electrode 160a or the first-2 through electrode 160b.

[0206] On the other hand, referring to FIG. 7, the circuit board 100 of the embodiment can be manufactured through an MSAP process.

[0207] Specifically, the first circuit layer 120 can further include a fourth metal layer as compared with FIGS. 3 to 5. In other words, each of the bump portion 121, the pad 122, and the trace 123 of the first circuit layer 120 can further include a fourth metal layer disposed between the upper surface of the first insulating layer 111 and the first metal layer. In contrast, the first through electrode 160 can include the first to third metal layers 161, 162, 163 as described with reference to FIGS. 3 to 5.

[0208] At this time, the bump portion 121, the pad 122, and the trace 123 of the first circuit layer 120 each include the same fourth metal layer. Accordingly, hereinafter, the description will be centered on the fourth metal layer 121-4 of the bump portion 121.

[0209] The bump portion 121 of the first circuit layer 120 further includes a fourth metal layer 121-4. The fourth metal layer 121-4 is disposed between the first metal layer 121-1 of the bump portion 121 and the upper surface of the first insulating layer 111. The fourth metal layer 121-4 can be a copper foil layer. Specifically, the fourth metal layer 121-4 can be a copper foil that adhered to the upper surface of the first insulating layer 111 during the process of laminating the first insulating layer 111.

[0210] Then, the circuit board 100 of the second embodiment is manufactured by the MSAP process, and thereby, the circuit layer forming process is performed without removing the fourth metal layer 121-4, which is a copper foil layer disposed on the upper surface of the first insulating layer 111.

[0211] The fourth metal layer 121-4 can have a fourth thickness. For example, the fourth thickness of the fourth metal layer 121-4 can satisfy the range of 0.8 μm to 2 μm. The fourth thickness of the fourth metal layer 121-4 can satisfy the range of 1.0 μm to 1.8 μm. The fourth thickness of the fourth metal layer 121-4 can satisfy the range of 1.2 μm to 1.6 μm. If the fourth thickness of the fourth metal layer 121-4 is less than 0.8 μm, reliability problems such as a decrease in flatness in the process of laminating the first insulating layer 111 may occur. If the fourth thickness of the fourth metal layer 121-4 exceeds 2 μm, the processability in the process of etching the fourth metal layer 121-4 (for example, the etching process of the seed layer or the through-hole forming process) may decrease.

[0212] Accordingly, the thickness T5 of the bump portion 121 of the second embodiment may be larger than the thickness T1 of the bump portion 121 of the first embodiment by the fourth thickness of the fourth metal layer 121-4.

[0213] Hereinafter, the recess formed in the lower region of the bump portion 121 of the embodiment will be described.

[0214] FIG. 8 is an enlarged view of the A region of FIG. 7 according to the first embodiment, and FIG. 9 is an enlarged view of the A region of FIG. 7 according to the second embodiment.

[0215] Referring to FIGS. 8 and 9, the first circuit layer 120 of the embodiment can include a recess formed in a lower region adjacent to the upper surface of the first insulating layer 111. The recess can also be said to be an undercut. The recess can be formed in the lower regions of the bump portion 121, the pad 122, and the trace 123 of the first circuit layer 120, respectively.

[0216] Specifically, referring to FIG. 7, the recess can be formed in the first metal layer and the fourth metal layer of each of the bump portion 121, the pad 122, and the trace 123.

[0217] In contrast, referring to FIG. 8, the recess can be formed in the first, second, and fourth metal layers.

[0218] Hereinafter, the description will focus on the recess formed in the bump portion 121. And, corresponding to the recess formed in the bump portion 121, recesses may also be formed in the pad 122 and the trace 123 of the first circuit layer 120.

[0219] At this time, there is no interface between the bump portion 121 and the first through electrode 160a. That is, the absence of an interface can mean that the bump portion 121 and the first through electrode 160a are integrally formed with each other.

[0220] Referring to FIG. 7, the recess in the bump portion 121 may be formed in the first metal layer 121-1 and the fourth metal layer 121-4 of the bump portion 121. And when the bump portion 121 is formed by the SAP process, the recess of the bump portion 121 may be formed only in the first metal layer 121-1 of the bump portion 121.

[0221] Thereby, the bump portion 121 can include a portion where the width changes in the thickness direction.

[0222] For example, the width of the bump portion 121 in the region where the first metal layer 121-1 is disposed may be smaller than the width in the region where the third metal layer 121-3 is disposed. Also, the width of the bump portion 121 in the region where the fourth metal layer 121-4 is disposed may be smaller than the width in the region where the third metal layer 121-3 is disposed.

[0223] And the width of the bump portion 121 in the region where the first metal layer 121-1 is disposed may be smaller than the width in the region where the second metal layer 121-2 is disposed. Also, the width of the bump portion 121 in the region where the second metal layer 121-2 is disposed may be larger than the width in the region where the fourth metal layer 121-4 is disposed.

[0224] And the width of the region where the second metal layer 121-2 of the bump portion 121 is disposed may be the same as the width of the region where the third metal layer 121-3 is disposed.

[0225] At this time, in the embodiment, a second metal layer 121-2 is further formed on the first metal layer 121-1, and the formed second metal layer 121-2 is used as an additional seed layer to form a third metal layer 121-3. Then, after forming the third metal layer 121-3, in the process of etching the seed layer, it is possible to prevent the first metal layer 121-1 from being over-etched by the second metal layer 121-2. Thereby, the embodiment can minimize the depth of the recess (specifically, the horizontal width of the recess).

[0226] Also, referring to FIG. 8, the recess in the bump portion 121 can be formed in the first metal layer 121-1, the second metal layer 121-2, and the fourth metal layer 121-4 of the bump portion 121. And when the bump portion 121 is formed by the SAP process, the recess in the bump portion 121 can be formed in the first metal layer 121-1 and the second metal layer 121-2 of the bump portion 121.

[0227] Thereby, the bump portion 121 can include a portion where the width changes in the thickness direction.

[0228] For example, the width of the bump portion 121 in the region where the first metal layer 121-1 is disposed may be smaller than the width in the region where the third metal layer 121-3 is disposed. Also, the width of the bump portion 121 in the region where the fourth metal layer 121-4 is disposed may be smaller than the width in the region where the third metal layer 121-3 is disposed. Also, the width of the bump portion 121 in the region where the second metal layer 121-2 is disposed may be smaller than the width in the region where the third metal layer 121-3 is disposed.

[0229] At this time, in the embodiment, a part of the recess may also be formed in the second metal layer 121-2. However, the depth of the recess in the second metal layer 121-2 is smaller than the depth of the recess in the first metal layer 121-1.

[0230] For example, in the bump portion 121, at least a part of the region where the second metal layer 121-2 is disposed has a width larger than that of the region where the first metal layer 121-1 is disposed. And in the embodiment, although a recess can be formed in the second metal layer 121-2 of the bump portion 121, its depth can be minimized, and further, the depth of the recesses formed in the first metal layer 121-1 and the fourth metal layer 121-4 by the second metal layer 121-2 can also be minimized.

[0231] The circuit board of the embodiment includes an insulating layer, a through electrode penetrating the insulating layer, and a first circuit layer disposed on the insulating layer. At this time, the first circuit layer includes a bump portion. The bump portion penetrates a protective layer disposed on the insulating layer and protrudes on the protective layer.

[0232] The bump portion includes a first portion disposed on the insulating layer and the through electrode and a second portion on the first portion. There is no interface between the first portion and the second portion of the bump portion. In other words, the first portion and the second portion are integrally formed with each other. Further, the through electrode is integrally formed with the first portion and the second portion of the bump portion. In other words, there is no interface between the through electrode and the bump portion.

[0233] Therefore, no additional layer is disposed between the first portion and the second portion of the bump portion of the embodiment. Specifically, there is no seed layer between the first portion and the second portion of the bump portion. Through this, the embodiment can improve the physical and electrical connectivity between the first portion and the second portion of the bump portion. Further, the bump portion of the embodiment is also integrally formed with the through electrode, and thereby the electrical and physical reliability can be further improved.

[0234] At this time, in the comparative example, the pad portion and the bump portion are formed through another plating process in which they are separated from each other. Therefore, the comparative example has a problem that the electrical and physical connectivity between them decreases and the signal transmission loss increases. Further, the comparative example has a structure in which a seed layer is further disposed between the bump portions of the pad portion, and has a problem that the overall reliability of the bump portion decreases due to the problem of the physical reliability of the seed layer.

[0235] On the other hand, the embodiment has a structure in which the through electrode, the first part of the bump portion, and the second part of the bump portion are integrally formed with each other. Thereby, the embodiment can improve the physical reliability and electrical reliability between the through electrode and the bump portion. Thereby, the embodiment can improve the physical reliability and electrical reliability of the circuit board.

[0236] Also, the bump portion of the embodiment includes a first metal layer, a second metal layer, and a third metal layer. The second metal layer is a first electrolytic plating layer electrolytically plated using the first metal layer as a seed layer, and the third metal layer is a second electrolytic plating layer electrolytically plated using the first metal layer and the second metal layer as seed layers.

[0237] Therefore, the embodiment can minimize the depth of the recesses generated in the etching process of the seed layer performed after the formation of the circuit layer. That is, the second metal layer can have higher strength than the first metal layer as an electrolytic plating layer. Therefore, the second metal layer can function as a barrier layer that minimizes the depth of the recesses generated on the side surface of the first metal layer in the etching process. Further, the second metal layer can function to prevent the third metal layer from being deformed in the etching process. Therefore, the embodiment can minimize the depth of the recesses formed on the side surface of the lower part of the bump portion by further including the second metal layer in the bump portion. Therefore, the embodiment can improve the physical reliability and electrical reliability of the bump portion.

[0238] Further, the third metal layer of the bump portion is electrolytically plated using not only the first metal layer but also the second metal layer as a seed layer. Thereby, the embodiment can minimize the thickness deviation between a plurality of bump portions included in the circuit board.

[0239] Specifically, looking at the circuit board of the comparative example, the plating of the bump portion is performed using only the electroless copper plating layer as a seed layer. At this time, the bump portion has a thickness of 100 μm or more. Thus, when plating a metal layer having a thickness of 100 μm or more, it is difficult to perform a plating process having a uniform thickness over the entire region with only the electroless copper plating layer. Therefore, in the circuit board of the comparative example, the thickness deviation of each bump portion exceeded 30% compared to the average value of the thicknesses of the plurality of bump portions. For example, when the average value was 100 μm, the thickness of at least one of the plurality of bump portions was less than 70 μm or exceeded 130 μm. Thereby, the circuit board of the comparative example performs the plating process so as to have a thickness greater than the target thickness in order to match the thicknesses of the respective bump portions. As a result, the comparative example finally has a problem that a polishing process must be included essentially for thickness uniformity while matching the thickness of the bump portion to the target thickness, and the polishing process time increases.

[0240] In contrast, the embodiment electrolytically plates the third metal layer of the bump portion using not only the first metal layer but also the second metal layer as a seed layer. Thereby, the embodiment can minimize the thickness deviation between a plurality of bump portions. Thereby, in the embodiment, the plating process can be performed under the condition that the bump portion has a thickness corresponding to the target thickness. Thereby, the embodiment can omit the polishing process or significantly shorten the polishing process time.

[0241] Specifically, looking at the circuit board of the comparative example, the plating of the bump portion is performed using only the electroless copper plating layer as the seed layer. At this time, the bump portion has a thickness of 100 μm or more. Thus, when plating a metal layer having a thickness of 100 μm or more, it is difficult to perform a plating process with a uniform thickness in all regions using only the electroless copper plating layer. Therefore, in the circuit board of the comparative example, the thickness deviation of each bump portion exceeded 30% compared to the average value of the thicknesses of the plurality of bump portions. For example, when the average value was 100 μm, the thickness of at least one of the plurality of bump portions was less than 70 μm or exceeded 130 μm. As a result, in the circuit board of the comparative example, the plating process is performed so that each bump portion has a thickness greater than the target thickness in order to match the thicknesses of the respective bump portions. As a result, the comparative example finally has a problem that a polishing process must be included to equalize the thickness while matching the thickness of the bump portion to the target thickness, and the polishing process time increases.

[0242] In contrast, in the example, electrolytic plating of the third metal layer of the bump portion is performed using not only the first metal layer of the bump portion but also the second metal layer as the seed layer. Thereby, the example can minimize the thickness deviation between the plurality of bump portions. Thereby, in the example, the plating process can be performed under the condition that the bump portion has a thickness corresponding to the target thickness. Thereby, the example can omit the polishing process or significantly shorten the polishing process time.

[0243] FIG. 10 is a diagram showing a semiconductor package according to an example.

[0244] Referring to FIG. 10, the semiconductor package of the example can have a structure in which a plurality of chips and an external substrate are arranged on the circuit board of FIG. 2.

[0245] For this purpose, the circuit board includes the bump portion 121 and the pad 122 of the first circuit layer 120.

[0246] The semiconductor package can include a first adhesive portion 210 disposed on the pad 122 of the circuit board. The semiconductor package can also include a second adhesive portion 240 disposed on the bump portion 121.

[0247] The first adhesive portion 210 and the second adhesive portion 240 can have the same shape as each other, or, alternatively, can have different shapes from each other.

[0248] For example, the first adhesive portion 210 and the second adhesive portion 240 can have a hexahedron shape. For example, the cross-section of the first adhesive portion 210 and the second adhesive portion 240 can include a rectangular shape. The cross-section of the first adhesive portion 210 and the second adhesive portion 240 can include a rectangular shape or a square shape. For example, the first adhesive portion 210 and the second adhesive portion 240 can include a spherical shape. For example, the cross-section of the first adhesive portion 210 and the second adhesive portion 240 can include a circular shape or a semi-circular shape. For example, the cross-section of the first adhesive portion 210 and the second adhesive portion 240 can include a partially or wholly rounded shape. The cross-sectional shape of the first adhesive portion 210 and the second adhesive portion 240 can be planar on one side and curved on the other side. The first adhesive portion 210 and the second adhesive portion 240 can be solder balls, but are not limited thereto.

[0249] The embodiment can include a chip 220 disposed on the first adhesive portion 210. The chip 220 can be a first processor chip. For example, the chip 220 can be an application processor (AP) chip among a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. The terminals 225 of the chip 220 can be electrically connected to the pad 122 via the first adhesive portion 210.

[0250] The embodiment can also include an external substrate 250 coupled to the second adhesive portion 240. The external substrate 250 can include a terminal portion 255 that is electrically connected to the second adhesive portion 240 on the lower surface.

[0251] The external substrate 250 can be a main board. For example, the external substrate 250 can be the main board of an electronic device.

[0252] Alternatively, the external substrate 250 can be an interposer. For example, the external substrate 250 can be an interposer that connects between the semiconductor package of the embodiment and other packages (e.g., memory packages).

[0253] Alternatively, the external substrate 250 can be a memory substrate or a memory package on which memory chips are mounted.

[0254] The semiconductor package can include a molding layer 230. The molding layer 230 can be disposed to cover the chip 220 and the bump portion 121.

[0255] When the first protective layer 195 is omitted from the circuit board, the molding layer 230 can be disposed to cover the configuration disposed on the uppermost side of the circuit board.

[0256] The molding layer 230 can be, but is not limited to, an EMC (Epoxy Mold Compound) formed to protect the mounted chip 220.

[0257] At this time, the molding layer 230 can have a low dielectric constant to enhance heat dissipation characteristics. For example, the dielectric constant (Dk) of the molding layer 230 can be 0.2 to 10. For example, the dielectric constant (Dk) of the molding layer 230 can be 0.5 to 8. For example, the dielectric constant (Dk) of the molding layer 230 can be 0.8 to 5. Thereby, the embodiment can enhance the heat dissipation characteristics of the heat generated by the chip 220 by making the molding layer 230 have a low dielectric constant.

[0258] On the other hand, the semiconductor package can include a third adhesive portion 260 disposed on the lowermost side of the circuit board. The third adhesive portion 260 can be disposed on the lower surface of the fourth circuit layer 150 exposed through the opening of the second protective layer 195.

[0259] Hereinafter, a method for manufacturing a circuit board according to an embodiment will be described.

[0260] FIGS. 11 to 22 are cross-sectional views showing the method for manufacturing the circuit board shown in FIG. 2 in the order of steps.

[0261] Referring to FIG. 11, the embodiment can perform a step of manufacturing an inner layer of the circuit board 100. For this purpose, the embodiment prepares a second insulating layer 112. Then, the embodiment forms a through hole in the second insulating layer 112. Thereafter, the embodiment can perform a step of forming a second circuit layer 130 disposed on the upper surface and a third circuit layer 140 disposed on the lower surface of the second insulating layer 112 together with a second through electrode 170 filling the through hole of the second insulating layer 112.

[0262] On the other hand, when the circuit board 100 of the embodiment is not a core board, the step of manufacturing the inner layer can be performed using a carrier board.

[0263] Further, when the circuit board 100 has a multilayer structure of four or more layers, the step of manufacturing the inner layer can be repeated a plurality of times.

[0264] Next, referring to FIG. 12, the embodiment can perform a step of manufacturing an outer layer on the manufactured inner layer.

[0265] For this purpose, the embodiment can perform a step of laminating a first insulating layer 111 on the second insulating layer 112. At this time, a structure in which a copper foil layer M1 is laminated can be provided on the first insulating layer 111. And the copper foil layer M1 may not be removed in the SAP process and can constitute a part of the first circuit layer 120 in the MSAP process.

[0266] Correspondingly, the embodiment can perform a step of laminating a third insulating layer 113 under the second insulating layer 112. At this time, under the third insulating layer 113, a structure in which a copper foil layer M2 is laminated can be provided. And the copper foil layer M2 may not be removed in the SAP process and can form a part of the fourth circuit layer 150 in the MSAP process.

[0267] Next, referring to FIG. 13, the embodiment can perform a step of processing the first insulating layer 111 and the third insulating layer 113 to form a through hole. For example, the embodiment can perform a step of processing the first insulating layer 111 and the copper foil layer M1 to form a first through hole VH1.

[0268] Also, the embodiment can perform a step of processing the third insulating layer 113 and the copper foil layer M2 to form a second through hole VH2.

[0269] On the other hand, in the following embodiment, a step of forming the first circuit layer 120 and the first through electrode 160 in the first insulating layer 111 and a step of forming the fourth circuit layer 150 and the third through electrode 180 in the third insulating layer 113 can be performed.

[0270] Hereinafter, the manufacturing process of the first circuit layer 120 and the first through electrode 160 formed in the first insulating layer 111 will be described as a reference. Correspondingly, a step of forming the fourth circuit layer 150 and the third through electrode 180 in the third insulating layer 113 can be performed.

[0271] Referring to FIG. 14, after the first through hole VH1 is formed, the embodiment can perform a step of forming an electroless plating layer M2 on the inner wall of the copper foil layer M1 and the first through hole VH1. At this time, the electroless plating layer M2 can mean an electroless copper plating layer.

[0272] The electroless plating layer M2 can also be disposed on the upper surface of the second circuit layer 120 overlapping in the vertical direction with the first through hole VH1. The electroless plating layer M2 constitutes the first metal layer of the bump portion 121, the pad 122, and the trace 123 of the first circuit layer 120 on the circuit board.

[0273] Referring to FIG. 15, the embodiment can perform a step of forming a first electrolytic plating layer M3 on the electroless plating layer M2. The first electrolytic plating layer M3 can be formed by performing primary electrolytic plating using the electroless plating layer M2 as a seed layer. Then, the first electrolytic plating layer M3 constitutes the second metal layer of each of the bump portion 121, the pad 122, and the trace 123 of the first circuit layer 120 on the circuit board. The first electrolytic plating layer M3 can be formed corresponding to the profile of the surface of the electroless plating layer M2.

[0274] Referring to FIG. 16, the embodiment can perform a step of forming a first mask DF1 on the first electrolytic plating layer M3. At this time, the first mask DF1 includes a first open region OR1 and a second open region OR2. Preferably, the first mask DF1 can have the first open region OR1 formed corresponding to the region where the pad 122 of the first circuit layer 120 and the first through electrode 160 are disposed in the upper region of the first electrolytic plating layer M3. Also, the first mask DF1 can have the second open region OR2 formed corresponding to the region where the trace 123 of the first circuit layer 120 is disposed in the upper region of the first electrolytic plating layer M3. At this time, the first mask DF1 is disposed to cover the region where the bump portion 121 is disposed in the upper region of the first electrolytic plating layer M3.

[0275] Referring to FIG. 17, the embodiment performs electrolytic plating using the electroless plating layer M2 and the first electrolytic plating layer M3 as seed layers to form a second electrolytic plating layer M4. Thereby, the second electrolytic plating layer M4 can be formed corresponding to the first open region OR1 and the second open region OR2 of the first mask DF1. The second electrolytic plating layer M4 can constitute the first-2 through electrode 160b of the first through electrode 160, the pad 122 of the first circuit layer 120, and the third metal layer of the trace 123.

[0276] Next, referring to FIG. 18, the embodiment can perform a step of removing the first mask DF1 disposed on the first electrolytic plating layer M3.

[0277] Next, referring to FIG. 19, the embodiment can perform a step of forming a second mask DF2 on the first electrolytic plating layer M3 and the second electrolytic plating layer M4. The second mask DF2 can include a third open region OR3. The third open region OR3 can be formed corresponding to the region where the first-1 through electrode 160a of the first through electrode 160 and the bump portion 121 are disposed in the upper region of the first electrolytic plating layer M3.

[0278] Next, referring to FIG. 20, the embodiment can perform electrolytic plating using the electroless plating layer M2 and the first electrolytic plating layer M3 as seed layers to form a third electrolytic plating layer M5 that fills the third open region OR3 of the second mask DF2. At this time, the third electrolytic plating layer M5 can constitute the third metal layer of each of the first-1 through electrode 160a and the bump portion 121.

[0279] Next, referring to FIG. 21, the embodiment can perform a step of removing the second mask DF2.

[0280] Next, referring to FIG. 22, the embodiment can perform an etching step of removing the copper foil layer M1, the electroless plating layer M2, and the first electrolytic plating layer M3 in a region that does not vertically overlap with the second electrolytic plating layer M4 and the third electrolytic plating layer M5.

[0281] Through this, the embodiment can form a first circuit layer 120 including the first to fourth metal layers, and including a bump portion 121, a pad 122, and a trace 123 integrally formed with the first through electrode. At this time, in the etching step, a first recess 121U can be formed on the side surface of the lower region of the bump portion 121. Also, in the etching step, a second recess 122U can be formed on the side surface of the lower region of the pad 122. Also, in the etching step, a third pile portion 123U can be formed on the side surface of the lower region of the trace 123.

[0282] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified and implemented in other embodiments by those with ordinary knowledge in the field to which the embodiment belongs. Therefore, the content related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0283] Also, although the description has centered around the embodiments above, this is merely an illustration and does not limit the embodiments. Those with ordinary knowledge in the field to which the embodiments belong will understand that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present embodiments. For example, each component specifically shown in the embodiments can be implemented with modifications. And the differences related to such modifications and applications should be construed as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. An insulating layer, a protective layer disposed on the insulating layer, a through electrode penetrating the insulating layer, and a bump portion disposed on the through electrode and penetrating the protective layer, wherein the bump portion includes a first portion connected to the through electrode and a second portion disposed on the first portion and protruding on the protective layer, wherein a horizontal width of the first portion is the same as a horizontal width of the second portion, a semiconductor package.

2. wherein the horizontal width of the first portion is larger than a width of an upper surface of the through electrode, the semiconductor package according to Claim 1.

3. wherein the first portion and the second portion of the bump portion are integrally formed, the semiconductor package according to Claim 1.

4. wherein the first portion and the second portion of the bump portion are integrally formed with the through electrode, the semiconductor package according to Claim 1.

5. wherein the bump portion includes a plurality of metal layers, wherein a width of at least one of the plurality of metal layers is different from a width of at least one other of them, the semiconductor package according to Claim 1.

6. wherein the plurality of metal layers include a first metal layer disposed on the insulating layer, a second metal layer disposed on the first metal layer, and a third metal layer disposed on the second metal layer, wherein a width of the first metal layer is smaller than a width of the third metal layer, the semiconductor package according to Claim 5.

7. wherein a width in the second metal layer is larger than a width of the first metal layer, the semiconductor package according to Claim 6.

8. wherein a width of the third metal layer is larger than a width of the second metal layer, the semiconductor package according to Claim 6.

9. wherein the first metal layer is a chemical copper plating layer, wherein the second metal layer is a first electrolytic plating layer, wherein the third metal layer is a second electrolytic plating layer, the semiconductor package according to Claim 6.

10. wherein the bump portion further includes a fourth metal layer provided between the insulating layer and the first metal layer, wherein a width of the third metal layer is larger than a width of the fourth metal layer, the semiconductor package according to Claim 6.

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