Inter-die Connectivity Monitoring Using a Clock Receiver

Abstract

It is to estimate and monitor connection quality. 【Solution means】 A programmable delay line, the following inputs, namely (a) a data signal that also functions as an input to a reference clock receiver configured to sample the data signal received from the interconnection lane between two integrated circuits (ICs) of a multi-IC module, and (b) a delayed clock signal received from the programmable delay line, which is a delayed version of the clock signal that clocks the reference clock receiver. A delay sampling device having a delayed clock signal, a comparison circuit configured to compare the data signal output of the delay sampling device with the data signal output of the reference clock receiver, and based on the comparison result of the comparison circuit and the amount of delay that caused the result, an I / O sensor comprising a controller configured to estimate the connection quality between two ICs via an interconnection lane.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims the priority of U.S. Provisional Patent Application No. 63 / 349,863, entitled "Die - To - Die Connectivity Monitoring Using a Clocked Receiver", filed on June 7, 2022, and claims the priority of U.S. Patent Application No. 18 / 089,541, entitled "Die - To - Die Connectivity Monitoring Using a Clocked Receiver", filed on December 27, 2022. The contents of both applications are incorporated herein by reference.

Background Art

[0002]

[0002] A semiconductor integrated circuit (IC) typically includes analog and digital electronic circuits on a flat semiconductor substrate such as a silicon wafer. Using photolithography technology, tiny transistors are printed on the substrate to create a complex circuit of billions of transistors in a very small area, realizing the latest electronic circuit designs using ICs at both low cost and high performance. ICs are manufactured on an assembly line in a factory called a foundry, where the manufacturing of ICs such as complementary metal - oxide - semiconductor (CMOS) ICs is shared.

[0003]

[0003] ICs are typically manufactured in large batches on a single wafer of electronic - grade silicon (EGS) or other semiconductors (such as GaAs). The wafer is cut (diced) into many pieces, each of which contains one copy of the circuit. Each of these pieces is called a "die".

[0004]

[0004] Digital ICs are typically packaged in a casing of metal, plastic, glass, or ceramic. The casing, or "package", is connected to a circuit board, such as by using solder. Types of packages include lead frames (through-hole, surface mount, chip carrier, etc.), pin grid arrays, chip scale packages, ball grid arrays, etc. for connecting between the IC pads and the circuit board.

[0005]

[0005] Some of the latest ICs are actually modules composed of multiple interconnected ICs (sometimes referred to as "chips" or "chiplets") configured to cooperate. A typical example is a logic IC interconnected with a memory IC, but there are many other types. There are also many inter-die (i.e., between-IC) connection technologies. As an example, for instance, wafer-level integration featuring high-density connectivity based on redistribution layers (RDL) and through-integrated via (TIV) sold by Taiwan Semiconductor Manufacturing Company (TSMC), Limited can be mentioned. Another example is system-level integration featuring individual chips bonded via microbumps on a silicon interposer, such as Chip on Wafer on Substrate (CoWoS) technology sold by TSMC Limited and Embedded Interconnect Bridge (EMIB) technology sold by Intel Corporation. Both enable high-bandwidth memory (HBM) subsystems. A third example is 3D chip stacking technology based on through-silicon vias (TSV), such as Chip on Wafer (CoW) and Wafer on Wafer (WoW) technologies sold by TSMC Limited.

[0006]

[0006] The foregoing examples of related art and the limitations related thereto are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those skilled in the art upon reading this specification and examining the figures.

Summary of the Invention

[0007]

[0007] The following embodiments and aspects thereof are described and illustrated in connection with a system, tool, and method that are not intended to be limiting, but rather illustrative and exemplary.

[0008]

[0008] One embodiment is directed to an I / O sensor comprising a programmable delay line, a data signal that also functions as an input to a reference clocked receiver configured to sample a data signal received from an interconnect lane between two integrated circuits (ICs) of a multi-IC module, and a delayed clock signal received from the programmable delay line, the delayed clock signal being a delayed version of a clock signal that clocks the reference clocked receiver, a comparison circuit configured to compare the data signal output of the delayed sampling device and the data signal output of the reference clocked receiver, and a controller configured to (a) gradually adjust the amount of delay introduced by the programmable delay line, (b) receive a comparison result from the comparison circuit after each gradual adjustment of the delay, and (c) estimate the connection quality between two ICs via the interconnect lane based on at least one of the results and the amount of delay that caused the result.

[0009]

[0009] In some embodiments, the programmable delay line includes a coarse delay line and a fine delay line connected in series, each delay step of the coarse delay line is longer than each delay step of the fine delay line, the length of each delay step of the coarse delay line is configured to bring the rising edge of the delay clock signal close to a place where the comparison result is likely to invert from "pass" to "fail" or vice versa, and the length of each delay step of the fine delay line is configured to detect an exact point where the comparison result is likely to invert from "pass" to "fail" or vice versa.

[0010]

[0010] In some embodiments, the estimation of the connection quality includes calculating the eye pattern parameters of the data signal.

[0011]

[0011] In some embodiments, the eye pattern parameters include the eye width calculated based on the time distance between the inversion points of the comparison results on the left and right sides of the unit interval (UI) of the data signal.

[0012]

[0012] In some embodiments, the controller is configured to operate the programmable delay line to scan the eye in one direction to detect the inversion point of the comparison result.

[0013]

[0013] In some embodiments, the controller is configured to select from two eye scan modes, namely, a first eye scan mode for scanning the first side of the eye by increasing or decreasing the amount of delay introduced by the programmable delay line, and a second eye scan mode for scanning the second opposite side of the eye by increasing or decreasing the amount of delay introduced by the programmable delay line.

[0014]

[0014] In some embodiments, the clock signal that clocks the reference clock receiver is a multi-phase clock signal. In the first ice scan mode, one of the phases of the multi-phase clock signal is affected by an increase or decrease in the amount of delay introduced by the programmable delay line. In the second ice scan mode, another one of the phases of the multi-phase clock signal is affected by an increase or decrease in the amount of delay introduced by the programmable delay line. In both the first and second ice scan modes, another one of the phases of the multi-phase clock signal is used to clock the reference clock receiver.

[0015]

[0015] In some embodiments, the delay sampling device is a clock receiver that has a reference voltage as an additional input that also functions as an input to the reference clock receiver. In some such embodiments, the reference voltage is a variable reference voltage, the eye pattern parameter further includes an eye height, and the controller is further configured to measure the eye height by gradually adjusting the variable reference voltage between each of the first and second ice scan modes, thereby measuring the eye width at different voltage levels.

[0016]

[0016] In some embodiments, the clock signal that clocks the reference clock receiver is a multi-phase clock signal, and the controller is further configured to detect duty cycle distortion of the multi-phase clock signal based on only one of the two ice scan modes.

[0017]

[0017] In some embodiments, the clock signal that clocks the reference clock receiver is a multi-phase clock signal having a duty cycle of approximately 50%. In the calculation of the eye width, the delayed clock signal received from the programmable delay line is only one phase of the multi-phase clock signal.

[0018]

[0018] In some embodiments, the I / O sensor further includes a compensation delay element configured to apply a certain amount of delay to the clock signal to compensate for the true delay of the programmable delay line.

[0019]

[0019] In some embodiments, the I / O sensor further comprises a compensation delay element configured to apply a certain amount of delay to the data signal in order to compensate for the true delay of the programmable delay line.

[0020]

[0020] In some embodiments, the I / O sensor further comprises a compensation delay element configured to apply a certain amount of delay to at least one of the data signal and the clock signal in order to compensate for the distance between the reference clock receiver and the I / O sensor.

[0021]

[0021] In some embodiments, the delay sampling device is a flip-flop.

[0022]

[0022] In some embodiments, the I / O sensor further comprises a timing measurement circuit configured to measure the delay provided by the programmable delay line. In some embodiments, the timing measurement circuit comprises a ring oscillator circuit configured to selectively incorporate the programmable delay line.

[0023]

[0023] Another embodiment is directed to a method for estimating the connection quality between two ICs interconnected by an interconnect lane, the method including operating various elements of the I / O sensor as described above.

[0024]

[0024] Another embodiment is directed to a computer-readable encoding of the I / O sensor, the computer-readable encoding of the I / O sensor including various elements of the I / O sensor described above (or elsewhere in this specification). The computer-readable encoding may be stored on a (non-transitory) computer-readable medium.

[0025]

[0025] In addition to the exemplary aspects and embodiments described above, further aspects and embodiments will become apparent by referring to the drawings and considering the following detailed description.

Brief Description of the Drawings

[0026]

[0026] Exemplary embodiments are shown in the reference figures. The dimensions of the components and features shown in the figures are generally selected for the convenience of display and clarity, and are not necessarily shown to scale. The figures are described below.

[0027]

Figure 1

[0027] An exemplary die interconnect using a clock receiver is shown.

Figure 2

[0028] An exemplary first version of an I / O sensor based on a clock receiver is shown.

Figure 3

[0029] It is a timing diagram showing a search mechanism for detecting / measuring the eye width (EW) of an input signal using the I / O sensor of FIG. 2.

Figure 4

[0030] An exemplary die interconnect configuration using a multi-phase clock is shown.

Figure 5

[0031] It is a timing diagram showing the timing of the clock phase of FIG. 4.

Figure 6

[0032] An example of the I / O sensor of FIG. 2 having the multi-phase clock configuration of FIG. 4 is shown.

Figure 7

[0033] An exemplary second version of an I / O sensor based on a clock receiver is shown.

Figure 8

[0034] An exemplary third version of an I / O sensor based on a clock receiver is shown.

Figure 9A

[0035] An exemplary fourth version of an I / O sensor based on a clock receiver is shown.

Figure 9B

[0036] A modification of an exemplary fourth version of an I / O sensor based on flip-flop-based sampling is shown.

Figure 9C

[0037] Shows a measurement circuit of a programmable delay line for precise EW measurement using an I / O sensor.

Figure 10

[0038] Shows a timing diagram of a search mechanism for detecting / measuring the eye width (EW) of an input data signal using the I / O sensor of FIG. 7, FIG. 8, FIG. 9A or 9B.

Figure 11

[0039] Shows an exemplary die interconnection configuration using the I / O sensors of FIGS. 7 and 8.

Figure 12A

[0040] Shows another exemplary die interconnection configuration using the I / O sensor of FIG. 9A.

Figure 12B

[0041] Shows a similar exemplary die interconnection configuration using the I / O sensor of FIG. 9B.

Figure 13A

[0042] Shows another exemplary die interconnection configuration using the I / O sensors of FIGS. 2 and 7 - 9B with the function of measuring the eye height (EH) added.

Figure 13B

[0043] Shows a method of measuring the eye height using the configuration of FIG. 13A.

Figure 14

[0044] Shows another exemplary die interconnection configuration using the I / O sensors of FIGS. 2 and 7 - 9B with the function of using a single I / O sensor for multiple clock receivers added.

Figure 15A-15B

[0045] Shows the timing diagrams of a normal polyphase clock duty cycle and an abnormal (distorted) polyphase clock duty cycle, respectively.

Best Mode for Carrying Out the Invention

[0028]

[0046] This specification discloses circuits, devices, systems, and methods (collectively, generally referred to as "I / O sensors" or "I / O sensing") for estimating and monitoring the connection quality between integrated circuits in a multi-IC module (sometimes referred to as a "multi-chip module") via interconnect lanes. Estimation includes, for example, measuring eye pattern parameters (such as eye width and / or eye height) of signals received at one end of an interconnect lane, and estimating the degradation of connection quality over time. Optionally, if the connection quality is insufficient, one or more actions may be taken, such as replacing a defective interconnect lane with a spare interconnect lane, reducing the transfer rate (also referred to as the "data rate") over a defective interconnect lane, or replacing a defective IC with a new IC (if the degradation of connection quality is due to a defective IC rather than a defective interconnect lane).

[0029]

[0047] The term "multi-IC module" as referred to in this specification may describe a group of interconnected integrated circuits (sometimes referred to as "chiplets" or "dies") that are integrated and packaged together and configured to cooperate through this interconnect to achieve a specific bonding function. The ICs in the module may communicate with each other, for example, via an interconnect bus. Their physical integration may be horizontal, vertical, or both.

[0030]

[0048] The term "eye pattern" as referred to in this specification may describe a graph in which a digital signal from a receiver is repeatedly sampled and applied to a vertical input, while the data rate triggers a horizontal sweep. The eye pattern is useful for evaluating signal transmission quality, such as various phenomena that cause channel noise and distortion of the digital signal. From a mathematical perspective, the eye pattern is a visualization of the probability density function (PDF) of the signal with the unit interval (UI) as the norm. In other words, it shows the probability that the signal is at each possible voltage over the duration of the UI. The generally measured parameters of the eye pattern are the eye width (EW) and the eye height (EH).

[0031]

[0049] The multi-IC modules to which the present disclosure relates may be constructed by known or later-introduced integration techniques that provide either direct connections between the ICs or indirect connections via mediators such as certain interposers, substrates, circuit boards, etc. In multi-IC modules, it is also possible to use both direct and indirect connections between various integrated IC pairs. Examples of today's multi-IC module integration techniques include Chip on Wafer on Substrate (CoWoS), Wafer On Wafer (WoW), Chip On Wafer (CoW), and 3D IC. However, embodiments of the present invention are certainly beneficial to other types of multi-IC modules characterized by die-to-die (IC-to-IC) connectivity.

[0032]

[0050] The disclosed I / O sensing includes die-to-die connectivity monitoring, particularly determining the connection quality of high-speed die-to-die interconnects. Such interconnects may implement wide buses and / or low power (picojoules / bit). Quality issues can cause open circuits, short circuits, bridge shorts (between signals), receiver-side microbump resistance degradation, and / or transmitter-side microbump resistance degradation. In this case, the timing of the signals at the receiver is expected to change, and that change may be detected by the disclosed monitoring techniques. The timing effect and power effect of this monitoring are minimal even when they cannot be ignored.

[0033]

[0051] Embodiments of the present disclosure may be useful, for example, in die-to-die connection schemes that use a clocked receiver (also referred to as a "clocked comparator" or "switch comparator"). This is prevalent in today's high-speed die-to-die connections that provide transfer data rates of 4 to 32 GT / s (gigatransfers per second) or higher.

[0034]

[0052] Refer to FIG. 1, which shows an exemplary die - to - die connection between a left - hand transmitter (belonging to the first IC of a multi - IC module) and a right - hand receiver (belonging to the second IC of the multi - IC module) according to the prior art. The two ICs are interconnected using interconnect lanes, and the physical connection between each IC and the lanes is made via pads (typically micro - bumps, pins, etc.). This receiver is based on a clocked - receiver configuration (shown in the enlarged portion of the figure) in which input data is compared with a reference voltage (V REF ) at the rising or falling edge of the clock using a comparator.

[0035]

[0053] At the clock edge, when the voltage difference (V in - V REF ) is greater than a specific value (e.g., 1 - 20 mV depending on the implementation and design of the comparator), the output D0 will resolve to V DD . Otherwise, D0 will resolve to V ss .

[0036]

[0054] According to the principles of the present disclosure, when monitoring the connection quality of an interconnect lane that uses a clocked - receiver as a sampler, the monitoring circuit needs to implement the same type of receiver in order to generate a reliable diagnosis. That is, by using a monitoring circuit (referred to herein as an "I / O sensor") that is a replica of the circuit being monitored, it is generally guaranteed that the detected anomalies are real and not caused by the monitoring itself.

[0037]

[0055] Thus, the disclosed I / O sensor used to monitor and characterize lanes based on a clocked - receiver sampler also implements a clocked - receiver sampler. In the various I / O sensor versions described below, in principle, a delayed clocked - receiver is used in parallel with a reference clocked - receiver (the latter is essentially the same as the clocked - receiver used in the IC even in the absence of an I / O sensor). Both of these clocked - receivers receive the same data signal (D in) receives the same reference voltage (V REF ), but the clock method is different. That is, the reference clock receiver is directly clocked by the original clock signal, while the delayed clock receiver is clocked by a delayed version of the original clock signal. By comparing the data output (D_s_d) of the delayed clock receiver with the data output (D_s) of the reference clock receiver, for example, the eye width of the data signal (D in ) can be measured to evaluate the interconnect quality of the lane. The evaluation / measurement may be performed by a controller included in the I / O sensor that controls the amount of delay, receives the result of the comparison, and also selects the input clock signal as necessary. The controller may further track the eye width over time (e.g., over days, weeks, months, years) to detect lane degradation, and a decrease in the eye width indicates degradation. The controller may further determine whether the eye width is less than a preset threshold and, accordingly, trigger the replacement of a defective lane with another spare lane.

[0038]

[0056] In particular, in all I / O sensor versions described below, the estimation of interconnect quality and the measurement of eye pattern parameters have the advantage that they can be performed in "mission mode" while the lane is transferring actual data. The I / O sensor operates in parallel with the sampling element (clock receiver) of the lane and does not interfere with the operation of that sampling element, so it is not necessary to stop the normal operation of the lane to perform the evaluation and measurement.

[0039]

[0057] FIG. 2 shows a first version of an exemplary I / O sensor based on a clock receiver. The data input (D in ) drives two clock receivers (the two Rx elements shown) where one port is connected to the connecting lane. The lower Rx ("reference clock receiver") may be something that has existed from the front in the IC design, and the upper Rx ("delayed clock receiver") is added for monitoring purposes.

[0040]

[0058] Voltage reference V REF is connected to the other port of each clock receiver and is used as a comparison level with D in .

[0041]

[0059] The clock signal (clk) directly drives the lower clock receiver.

[0042]

[0060] The inverted delay version of the clock signal (clk_d_b) is generated by a programmable delay line. The delayed clock version (clk_b_d) is used to clock the upper clock receiver.

[0043]

[0061] Therefore, the two clock receivers sample data (D in ) at different times and generate two outputs D_s and D_s_d.

[0044]

[0062] Next, these two outputs are sampled by the two flip-flops (memory elements, denoted as FF1 and FF2) shown in the figure and compared by a comparison circuit such as the XOR gate shown in the figure. FF1 and FF2 are clocked by the inverted clock signal Clk_b. When D_s_d is equal to D_s, the XOR output (X0) becomes the logical value 0 (indicating "pass"), and when D_s_d is different from D_s, the XOR output becomes the logical value 1 (indicating "fail").

[0045]

[0063] The last flip-flop (memory element, denoted as FF3) may be used to store the XOR value at the first time point when the XOR value changes to the logical value 1 according to the following configuration. FF3 is clocked by Clk_b, the data input to FF3 is from an OR gate, the first input of the OR gate is X0, and the second input is the output of FF3. The last flip-flop is also optionally regarded as part of the comparison circuit to store the last change of the comparison result.

[0046]

[0064] A controller (not shown in this figure) embedded in the IC may control the amount of incremental delay introduced by the programmable delay line and may also receive the output of FF3. Therefore, the controller recognizes the specific delay amount that caused the first "fail" of X0 and may utilize this knowledge to calculate the eye width of D in .

[0047]

[0065] The operation of the I / O sensor in FIG. 2 may be better understood by referring to FIG. 3, which is a timing diagram showing a search mechanism (method) for detecting / measuring the eye width of the input signal at D in .

[0048]

[0066] In the figure, the clock signal (clk) that clocks the lower clocked receiver samples the value of D1 data at the center of the unit interval (UI) during communication (data transfer).

[0049]

[0067] Clk_b_d generated by the programmable delay line is used to scan the eye from left to right or right to left by clocking the upper clocked receiver at various delay levels (indicated by the dotted lines of the rising clock edges) compared to the clk signal.

[0050]

[0068] The outputs of the two clocked receivers are sampled by two flip-flops (FF1 and FF2) at the falling edge of the clk signal and then compared by XOR.

[0051]

[0069] When the flip-flops happen to sample different values, the XOR output will be set to the logical value 1. The last flip-flop (FF2) stores this fault indication until it is reset by the controller in a subsequent scan sequence. The controller may of course be configured to store a record of all past fault indications on the IC in non-volatile memory along with the time at which each fault was indicated.

[0052]

[0070] The scan sequence (method) may be as follows.

[0053]

[0071] Starting from the minimum delay of the programmable delay line, clk_b_d samples the value of D0 data. The clk signal samples D0.

[0054]

[0072] Since D0 is not equal to D1, a failure is expected (displayed as the letter F).

[0055]

[0073] Thereafter, the programmable delay line gradually increases the delay, and at the point (position of the delay line) where the two clock receivers are sampling the same value, the detection switches (inverts) to a pass (indicated by the letter P).

[0056]

[0074] Thereafter, the delay line continues to increase its delay value until the two clock receivers sample different values again. At that time, the comparison indicates a failure (displayed as the letter F).

[0057]

[0075] The eye width may be measured as follows.

[0058]

[0076] 1. Record the position of the programmable delay line at the transition from the first fail to pass (F→P).

[0059]

[0077] 2. Record the position of the programmable delay line at the transition from the first pass to fail (P→F).

[0060]

[0078] 3. Calculate the delay line increment (K) between the first fail to pass and the first pass to fail.

[0061]

[0079] 4. Convert K to the time (e.g., in picoseconds) of each increment step that the delay line is programmed to execute by multiplying K by the delay line "tick" (d).

[0062]

[0080] The disclosed I / O sensor may be used in an inter-die connection configuration that utilizes a multi-phase clock to increase data transmission bandwidth. In such a configuration, a particular sampling clock frequency (e.g., 2.4 GHz) may span multiple clock phases (e.g., eight phases) to obtain a larger bandwidth (e.g., 2.4 × 8 = 19.2 GT / s).

[0063]

[0081] Such an exemplary configuration is shown in FIG. 4, which has eight clock receivers each clocked at a different clock phase (from Φ0 to Φ7), generating eight different data outputs (from D0 to D7). Such a configuration may include from 2 to 32 phases or more different numbers of clock phases.

[0064]

[0082] And FIG. 5 is a timing diagram showing the timing of the eight clock phases and eight data outputs of the clock receivers in FIG. 4.

[0065]

[0083] Referring to FIG. 6, which shows an embodiment of the disclosed I / O sensor with a multi-phase clock configuration (such as that in FIG. 4). In this embodiment, the I / O sensor may be configured to include the following changes compared to FIG. 2.

[0066]

[0084] 1. One representative receiver is used for every eight receivers.

[0085] 2. The reference data (D_in) is generated by the lane receiver (D0).

[0086] 3. The delayed clock version (clko) is generated by the I / O sensor to drive an external clock receiver and generate the delayed data D0_D (however, it is also possible to include this clock receiver within the I / O sensor itself).

[0067]

[0087] Instead of coupling the I / O sensor to just one representative clock receiver in a polyphase clock configuration, it is possible to couple the I / O sensor to multiple clock receivers using a multiplexer that selects a different clock receiver each time. This alternative configuration is not shown in the figure.

[0068]

[0088] Refer to FIG. 7 showing a second version of the I / O sensor based on a clock receiver and FIG. 10 showing a timing diagram of a search mechanism for measuring the eye width of an input signal using the I / O sensor of FIG. 7. The second version of the I / O sensor operates in the same manner as the first version, but has several differences as shown below and in FIG. 7.

[0069]

[0089] The second I / O sensor version enables measurement of the eye width by performing two measurements in separate scan operation modes, each selectable by a multiplexer.

[0070]

[0090] In the first measurement mode (M1, mode 1), the rising edge of the clk signal is used as a reference for measuring the timing shift on the right side of EW. This is done by shifting the clk signal with a delay line (adjusting the delay of the clk signal) to find the lowest fail indication (assuming the delay line delay is shifting from the maximum value to the minimum value) or the highest pass indication (assuming the delay line is shifting from the minimum value to the maximum value).

[0071]

[0091] In the second measurement (M2, mode 2), while using the rising edge of the clk signal as a reference, the rising edge of the clk_b signal (the inversion of clk) is delayed with a delay line to measure the timing shift on the left side of EW. This is done by shifting the clk_b signal with a delay line to find the highest fail indication (assuming the delay line is shifting from the minimum value to the maximum value) or the lowest pass indication (assuming the delay line is shifting from the maximum value to the minimum value).

[0072]

[0092] And the minimum EW is calculated as follows: minimum EW = UI + M1 - M2. UI represents the data unit interval, i.e., 1 / data rate (GT / s). Each of M1 and M2 represents the delay provided by the delay line when FF3 first indicates "fail" in each mode.

[0073]

[0093] The delay line may be composed of two parts, a coarse delay line and a fine delay line connected in series, and the combination of their delays provides the overall delay of the delay line. Each step of the coarse delay line may increase the delay by a value between 1 / 2 and 6 / 8 of the UI length, while each step of the fine delay line may increase the delay by a value between 1 / 8 and 1 / 4 of the UI length. Generally, the ratio of the step delay lengths between the coarse delay line and the fine delay line may be 2:1 or more.

[0074]

[0094] The coarse delay line is a controlled delay element that enables the I / O sensor to operate at multiple / wide ranges of data rates (clock frequencies) while using the same variable (fine) delay line. The coarse delay line is configured to bring the edge of the scan clock into the fail region (i.e., near the location where the transition from "fail" to "pass" result, or vice versa, is likely to be detected) based on the data rate. And the fine delay line is used for a finer scan to detect the exact point of the transition from pass to fail, or vice versa.

[0075]

[0095] Both the coarse delay line and the fine delay line can be controlled by the same controller (not shown in the figure) embedded in the IC and optionally part of the I / O sensor, and this controller also receives the output of FF3 and controls the multiplexer.

[0076]

[0096] Refer to FIG. 8 showing the third version of the I / O sensor based on a clock receiver, and FIG. 10 showing the timing diagram of the search mechanism for detecting / measuring the eye width of the input signal using the I / O sensor of FIG. 8 (this timing diagram is the same as that of the I / O sensor of FIG. 7).

[0077]

[0097] The third version of the I / O sensor can operate at a very high data rate (frequency) of 32 GT / s or higher by using a delay line and two inverted-phase input clocks (clk_phase_0 and clk_phase_1) that directly clock a reference clock receiver that generates a D_s output. Due to these high data rates, this version of the I / O sensor may include two optional compensation delay elements, namely, a phase shifter that applies a fixed delay to D in and a compensation delay buffer that applies a fixed delay to the clk_phase_0 signal. It is also possible to include only one of these. The fixed delay may be 3 to 12 picoseconds (or more as required), which is approximately equivalent to the true delay of the programmable delay line. This true delay is the delay introduced by the programmable delay line even when it is not set to apply a delay, and just the presence of this delay line in a specific signal path causes the signal passing through it to be slightly delayed. By slightly delaying D in it is possible to ensure that each data signal arrives at both clock receivers almost simultaneously (the maximum dispersion is, for example, 3 picoseconds or less). Similarly, by slightly delaying the clk_phase_0 signal, it is possible to ensure that when the delay line is set to introduce a specific delay, the clk_phase_0 signal arrives at the delayed clock receiver with approximately the set delay (the maximum dispersion is, for example, 3 picoseconds or less) without being significantly delayed compared to that. In short, these compensation delay elements help to ensure that like is compared with like, that is, the outputs of the two clock receivers are compared under the same starting conditions.

[0078]

[0098] The third I / O sensor version enables the measurement of the eye width by performing two measurements in two selectable separate scan modes using a multiplexer (similar to the second version). EW is extracted in the same way as described above. Clk_phase_0 is used as the reference clock for both the M1 and M2 measurements, clk_phase_0 is the delayed clock in the M1 measurement, and clk_phase_1 is the delayed clock in the M2 measurement.

[0079]

[0099] In the first measurement (M1, mode 1), the rising edge of the clk_phase_0 signal is used as a reference to measure the timing shift on the right side of the EW. This is done by shifting the clk_phase_0 signal with a delay line to find the lowest failure indication (assuming the delay line is shifted from the maximum value to the minimum value), or the highest pass indication (assuming the delay line is shifted from the minimum value to the maximum value).

[0080]

[0100] In the second measurement mode (M2, mode 2), the rising edge of the clk_phase_0 signal is used as a reference to measure the timing shift on the left side of the EW. This is done by shifting the clk_phase_1 signal with a delay line to find the highest fail indication (assuming the delay line is shifted from the minimum value to the maximum value), or the lowest pass indication (assuming the delay line is shifted from the maximum value to the minimum value).

[0081]

[0101] And the minimum EW is calculated as follows: minimum EW = UI + M1 - M2.

[0082]

[0102] clk_phase_0 and clk_phase_1 represent two adjacent clock phases within a multi-clock phase system, where clk_phase_0 is the lead clock phase and clk_phase_1 is the clock phase delayed by only the UI. A third I / O sensor version may be used to measure the EW of each data index (more than two) within a multi-clock phase system by connecting any two adjacent clock phases to the I / O sensor. For example, in a 4-clock phase system, the following clock phase pairs [lead, lag], i.e., [clk_phase_1, clk_phase_0], [clk_phase_2, clk_phase_1], [clk_phase_3, clk_phase_2] can be measured. This can be implemented, as would be readily understood by those skilled in the art, by adding an input selector (multiplexer).

[0083]

[0103] Refer to FIG. 9A showing a fourth version of the I / O sensor based on a clock receiver, FIG. 9B showing a fourth version of the I / O sensor based on flip-flop sampling (which also measures quadrature phase clocks), and FIG. 10 showing a timing diagram of a search mechanism for detecting / measuring the eye width of an input signal using the I / O sensor of FIG. 9A or 9B (this timing diagram is the same for the I / O sensors of FIGS. 7 and 8).

[0084]

[0104] The fourth version of the I / O sensor can measure the eye width for each clock phase in a multi-phase clock system with a wide frequency range. For example, such a system utilizes a multi-phase clock to sample wide data rate transmission (e.g., from 4 GT / s to 3.2 GT / s) at multiple clock phases (e.g., two or four). The I / O sensor of FIG. 9A can measure the EW for each of the clock phases clke and clko. The I / O sensor of FIG. 9B can measure the EW for each of the clock phases clk_phase_1, clk_phase_2, clk_phase_3, and clk_phase_4.

[0085]

[0105] The main difference between FIGS. 9A and 9B is that in FIG. 9A, data is sampled using a clocked receiver, whereas in FIG. 9B, data is sampled using flip-flops (registers). Specifically, in FIG. 9B, the first flip-flop (FF1) and the second flip-flop (FF2) are used to sample data using a delayed version of the reference clock and a non-delayed version of the reference clock, respectively. The other flip-flops within the I / O sensor are basically the same. The use of sampling flip-flops may have the advantage of being easier to manufacture or fabricate compared to a clocked receiver. Also, in this configuration, since it is not necessary to provide VREF to the I / O sensor, the efficiency of signal routing may be improved.

[0086]

[0106] FIG. 9A shows two clock phases, clock even (clke) and clock odd (clko). The phase between clke and clko is 180 degrees, and clke samples data at the even positions of the data stream, and clko samples data at the odd positions of the data stream (in the case of double data rate (DDR) operation). Other configurations contemplated herein may include a different number of clock phases. As shown in FIG. 9B, there may be four clock phases with a 90-degree interval between each clock phase and the other two clock phases (in the case of quad or quadrature data rate (QDR) operation). Even more clock phases can be used, and those skilled in the art will understand the adaptation to these examples necessary to facilitate that number of clock phases.

[0087]

[0107] The fourth version of the I / O sensor implements two input multiplexers, mux1 and mux2, to select each of the clock phases in the system used as the reference clock (clke or clko in FIG. 9A, or clk_phase_1, clk_phase_2, clk_phase_3, and clk_phase_4 in FIG. 9B). The I / O sensor will measure EW for each clock phase selected by the multi-mode measurement technique as described above.

[0088]

[0108] In the case of FIG. 9A, to measure EW for clke, in mode 1, both mux1 and mux2 select clke. In mode 2, mux1 selects clko and mux2 selects clke. To measure EW for clko, in mode 1, both mux1 and mux2 select clko. In mode 2, mux1 selects clke and mux2 selects clko.

[0089]

[0109] Referring to FIG. 9B, the input multiplexer is used to select two clock phases for each measurement, as described below.

[0090]

[0110] To measure EW in DDR mode (when only two clock phases are used), the two clock phases need to be selected in the following order. Eye-1 is measured by selecting clk_phase_1, clk_phase_2 (clk_f1, clk_f2). Eye-2 is measured by selecting clk_phase_2, clk_phase_1 (clk_f2, clk_f1). This is achieved by selecting mux2 (controlled by the prtn_io_sensor_cfg[10:9] signal) and mux1 (controlled by the prtn_io_sensor_cfg[12:11] signal) as follows.

[0091]

[0111] To measure eye-1 in DDR mode, the following clock pairs are selected: prtn_io_sensor_cfg[10:9]=[0,0], prtn_io_sensor_cfg[12:11]=[0,0] → M1 prtn_io_sensor_cfg[10:9]=[0,0], prtn_io_sensor_cfg[12:11]=[0,1] → M2

[0092]

[0112] To measure Eye-2 in DDR mode, the following clock pairs are selected: prtn_io_sensor_cfg[10:9]=[0,1], prtn_io_sensor_cfg[12:11]=[0,1] → M1 prtn_io_sensor_cfg[10:9]=[0,1], prtn_io_sensor_cfg[12:11]=[0,0] → M2

[0093]

[0113] To measure each EW in QDR mode, two of the four clock phases need to be selected in the following order. Eye-1 is measured by selecting clk_phase_1, clk_phase_4 (clk_f1, clk_f4). Eye-2 is measured by selecting clk_phase_2, clk_phase_1 (clk_f2, clk_f1). Eye-3 is measured by selecting clk_phase_3, clk_phase_2 (clk_f3, clk_f2). Eye-4 is measured by selecting clk_phase_4, clk_phase_3 (clk_f4, clk_f3). This is achieved by selecting mux2 (controlled by the prtn_io_sensor_cfg[10:9] signal) and mux1 (controlled by the prtn_io_sensor_cfg[12:11] signal) as follows.

[0094]

[0114] To measure Eye-1 in QDR mode, the following clock pairs are selected: prtn_io_sensor_cfg[10:9]=[0,0], prtn_io_sensor_cfg[12:11]=[0,0] → M1 prtn_io_sensor_cfg[10:9]=[0,0], prtn_io_sensor_cfg[12:11]=[1,1] → M2

[0095]

[0115] To measure Eye-2 in QDR mode, the following clock pairs are selected: prtn_io_sensor_cfg[10:9]=[0,1], prtn_io_sensor_cfg[12:11]=[0,1] → M1 prtn_io_sensor_cfg[10:9]=[0,1], prtn_io_sensor_cfg[12:11]=[0,0] → M2

[0096]

[0116] To measure Eye-3 in QDR mode, the following clock pairs are selected: prtn_io_sensor_cfg[10:9]=[1,0], prtn_io_sensor_cfg[12:11]=[1,0] → M1 prtn_io_sensor_cfg[10:9]=[1,0], prtn_io_sensor_cfg[12:11]=[0,1] → M2

[0097]

[0117] To measure Eye-4 in QDR mode, the following clock pair is selected: prtn_io_sensor_cfg[10:9]=[1,1], prtn_io_sensor_cfg[12:11]=[1,1] → M1 prtn_io_sensor_cfg[10:9]=[1,1], prtn_io_sensor_cfg[12:11]=[1,0] → M2

[0098]

[0118] Referring to FIG. 9C, a measurement circuit of a programmable or adjustable delay line for precise EW measurement using an I / O sensor is shown. This circuit can be interconnected, for example, by coupling the I / O sensor of FIG. 9A or FIG. 9B with the shown input multiplexer and programmable delay line.

[0099]

[0119] In this design, a ring oscillator (ROSC) circuit is used to measure the delay. The ROSC circuit consists of an extended delay line (EDL) and a ROSC inverter. The ROSC circuit is controlled by a ROSC pass gate and a ROSC selector, both of which are enabled by the ROSC enable signal osc_en. When osc_en = [1], the ROSC pass gate and the ROSC selector are enabled, and when osc_en = [0], the ROSC pass gate and the ROSC selector are disabled.

[0100]

[0120] The output of the ROSC selector is controlled by the mode signal osc_mode. The ROSC circuit can operate in two modes. In the first mode (osc_mode = [1]), the ROSC circuit consists of only the extended delay line and the ROSC inverter. In the second mode (osc_mode = [0]), the ROSC circuit consists of the programmable delay line of the I / O sensor, the extended delay line, and the ROSC inverter. The output of the ROSC selector is provided to a frequency divider including a divider flip-flop (FF) and an inverter. The output of the ROSC selector is provided as a clock input to the divider flip-flop (FF), and the inverter is coupled between the divider flip-flop (FF) data output and the divider flip-flop (FF) data input. As a result, the signal at the divider flip-flop (FF) data output is half the frequency of the output of the ROSC selector.

[0101]

[0121] The output of the frequency divider is supplied to a buffer, which provides an oscillator output signal osc_out. Advantageously, the oscillator output signal may be multiplexed with the measurement output of an I / O sensor (not shown). It is advantageous to disable normal I / O sensor measurements when the programmable delay line is being measured. For this purpose, the ROSC enable signal osc_en is also provided to the inverted control input (labeled Input_dis) of a multiplexer (mux) (e.g., mux2 in FIGS. 9A and 9B) that provides an input to the delay line. Thereby, the inverted control input disables the multiplexer when osc_en = [1]. Thus, the programmable delay line can be used for normal (EW) measurements or for delay line measurements. In the latter case, the normal (EW) measurement mode is disabled.

[0102]

[0122] The programmable delay line circuit generates a linear delay in fine steps. The delay provided by the programmable delay line (D) can be expressed by the following formula:

Number

[0103] where D0 is the true delay of the delay line, d is the delay step of the fine step, and n is the number obtained by subtracting 1 from the number of steps (since the initial value of k is 0), and may be, for example, 16.

[0104]

[0123] The ROSC circuit enables measurement of fine delay line steps in picosecond units. As described above, the ROSC circuit can operate in two configuration modes. The first mode (osc_mode = [1]) is also called the fine delay line bypass mode. In this configuration, the ROSC consists of an EDL and a ROSC inverter. And the oscillation frequency of the ROSC is based on the EDL delay. The oscillation period Tosc is twice the delay of the EDL. The second mode (osc_mode = [0]) is also called the fine delay line non-bypass mode. In this configuration, the ROSC consists of an EDL and a programmable delay line. The oscillation frequency of the ROSC in this mode corresponds to the delay of the EDL and the delay of the programmable fine delay line. The oscillation period Tosc in this case is twice the sum of the EDL delay and the programmable delay line delay.

[0105]

[0124] In a specific example (for illustrative purposes only), the EDL delay may have a value of 0.5 ns, and the expected frequency of the ROSC in the first mode is approximately 1 GHz (1 / (2×0.5 [ns])).

[0106] The frequency divider (including the divider flip-flop FF) divides the ROSC frequency by 2, so in this case the oscillator output signal osc_out is approximately 500 MHz.

[0107]

[0125] During operation, the first mode of the ROSC circuit is used to generate a baseline frequency (FB) that is 500 MHz in the above specific example. Next, the cycle time can be extracted: T B =(2 / F B ). In this specific example, T B is 4 ns. Next, the second mode of the ROSC circuit is used with k = 0. This corresponds to measuring the frequency (F D ) corresponding to the sum of the EDL delay and the true delay (D0) of the programmable delay line, and from this extracting the corresponding cycle time (TD).

[0108]

[0126]

Number

[0109]

[0127] Finally, the second mode of the ROSC circuit is used by setting k to each of 1 to n (n = 15 in the specific example considered in this specification), and F D (k) is measured, and the fine delay line step duration d(k) is extracted according to the following formula.

[0110]

[0128]

Equation

[0111]

[0129] The value of a typical example of d(k) may be from 1 ps to 5 ps depending on the configuration of the delay line. The timing measurement values determined in this way can be used for precise EW measurement.

[0112]

[0130] Generally, this circuit may be considered a timing measurement circuit configured to measure the delay provided by a programmable delay line. The timing measurement circuit may include a ring oscillator circuit configured to selectively incorporate a programmable delay line. In this way, the comparison between the output frequency of a ring oscillator circuit without a programmable delay line and the output frequency of a ring oscillator circuit with a programmable delay line may indicate the delay introduced by the programmable delay line. This may enable precise EW measurement (up to the order of picoseconds).

[0113]

[0131] Refer to FIG. 11 showing an exemplary die interconnection configuration using any of the first, second, or third versions of the I / O sensor. This I / O sensor is located near a lane sampling element and a reference clock receiver (Rx). The I / O sensor input signal is connected to the lane to receive D in and the Rx clock is also used to clock the I / O sensor. Rx V REFis also used as the reference voltage for the (delay) clock receiver of the I / O sensor itself.

[0114]

[0132] Refer to FIGS. 12A and 12B, which show exemplary die interconnect configurations using a fourth I / O sensor version. FIG. 12A uses a fourth I / O sensor version based on a clock receiver having two clock phases, as shown in FIG. 9A for example, and FIG. 12B uses a fourth I / O sensor version based on a sampling flip-flop (or similar) having four clock phases, as shown in FIG. 9B for example. In both cases, the I / O sensor is located near the lane sampling element and the clock receiver (Rx). The I / O sensor input signal is connected to the lane to receive D in and the two clock phases of each Rx element are also used to clock the I / O sensor. In FIG. 12A, Rx V REF is used as the reference voltage for the (delay) clock receiver of the I / O sensor itself. As shown in FIG. 12B, when a sampling flip-flop is used in the I / O sensor, it is not necessary to provide Rx V REF as the reference voltage to the I / O sensor.

[0115]

[0133] Refer to FIG. 13A, which shows an exemplary die interconnect configuration with the added function of measuring the eye height (EH) using a variable V REF using any of the above-described I / O sensor versions. To measure the eye height, as shown in FIG. 13B, M1 and M2 measurements are taken for different V REF values, and the eye width is calculated for each different V REF point. The eye height can be calculated for each defined minimum eye width (e.g., V REF + / -2dV).

[0116]

[0134] Refer to FIG. 14, which shows an exemplary inter-die connection configuration where one I / O sensor can be used for each of a plurality of reference clock receivers (Rx) (e.g., two) using any of the above-described I / O sensor versions. In this configuration, each of the reference clock receivers is connected to the I / O sensor such that the clock-to-data delay difference does not substantially change regardless of the distance between the clock receivers. The delay inherent to that distance (i.e., the signal propagation time proportional to the distance of the path) may be compensated by an illustrated compensation delay buffer that applies a fixed amount of delay pre-calculated according to the relevant distance. By keeping the delay difference between the data signal and the clock signal the same at the input of the I / O sensor, it becomes possible to measure EW and EH in a reliable manner based on the M1+M2 measurement. That is, the measured EW and EH are equal to the EW and EH of the reference clock receiver itself. The two multiplexers mux1 and mux2 shown in this figure can be implemented outside the I / O sensor or as part of the I / O sensor.

[0117]

[0135] In the third and fourth I / O sensor versions where a multi-phase clock is used, such clock duty cycle distortion may have been detected and / or measured using the following techniques. Such distortion is indicated by different mismatched periods of different clock phases. Refer to FIGS. 15A and 15B, which show the timing diagrams of a normal multi-phase clock duty cycle and an abnormal (distorted) multi-phase clock duty cycle, respectively. The normal multi-phase clock shows a 50% duty cycle, the UI is consistent, and the distance between the rising edges of each clock phase signal clko and clke is equal. On the other hand, in the abnormal multi-phase clock, there is no consistent UI. For clko, its "phase low" (PL) period is longer than its "phase high" (PH) period, and the reverse phenomenon may be observed for clke. The distances between the rising edges of these respective clock phase signals are not equal. Generally, in a multi-phase clock receiver, a duty cycle other than 50% is not desirable.

[0118]

[0136] To detect such duty cycle distortion and optionally to measure the distorted duty cycle, two measurements may be performed, namely, a measurement in mode 1 using clke (M1e) and a measurement in mode 1 using clko (M1o). In this case, the distortion is given by M1e - M1o. As an alternative, the two measurements may include a measurement in mode 2 using clke (M2e) and a measurement in mode 2 using clko (M2o). In this case, the distortion is given by M2e - M2o.

[0119]

[0137] In connection with I / O sensor versions (second, third, and fourth versions) where a polyphase clock is used, various methods for measuring the eye width (Min EW) have been described above. In these methods, it was necessary to operate two scan modes. However, if it is known that the duty cycle of the polyphase clock is not distorted (either by measuring the distortion as described above or by knowing that no distortion is expected from other tests), a simpler method for measuring the eye width may be used. In this method, only one scan mode is required in which the lowest fail and the highest fail are determined for one of the clock phases (since the duty cycle is assumed to be 50%, there is no need to measure other clock phases). At this time, the eye width is given as UI + lowest fail - highest fail. That is, during the period of UI, the delay required to reach the lowest fail is added and the delay required to reach the highest fail is subtracted.

[0120]

[0138] Thus, if it is known in advance that the multiphase reference clock receiver has a normal (50%) duty cycle (or close thereto, e.g., 47 - 53% duty cycle), the third and fourth I / O sensor versions may be implemented without the multiplexer used for mode selection, and instead, only one of the clock phases may be used for connection quality estimation and eye width measurement. Similarly, the second I / O sensor version may be implemented without a clock phase inverter and the subsequent multiplexer, and the connection quality estimation and eye width measurement are performed based only on the original clock signal.

[0121]

[0139] Further, a method for calculating eye width jitter is provided herein. This may include using the second, third, or fourth I / O sensor version to perform a number of (e.g., 10,000 or more) M1 or M2 measurements and calculating a statistical measure of the distribution of the measurement values. An alternative method for calculating eye width jitter is to distribute these M1 or M2 measurements across a plurality of interconnect lanes (i.e., when the associated I / O sensors are connected to the reference clock receivers of a plurality of different lanes) such that the calculated eye width jitter represents the jitter occurring in all of these lanes.

[0122]

[0140] Generally, for all versions of the I / O sensor, it will be understood that the I / O sensor may include the controller briefly described above. The controller may be configured to control a programmable delay line by appropriate circuitry included therein, i.e., to gradually adjust the amount of delay introduced by the delay line according to the delay increments (or "steps") incorporated in the delay line. This gradual adjustment may follow the scan method described above.

[0123]

[0141] The controller may further be configured to control any of the aforementioned multiplexers to perform various measurement modes.

[0124]

[0142] The controller may further be configured to receive the comparison result (a "pass" or "fail" represented as 0 or 1) from the comparison circuit (e.g., an XOR gate) only immediately after each comparison is made or after the value of the last flip-flop (e.g., FF3 in FIG. 7 and equivalent flip-flops in other figures) changes from one value to another (e.g., from "pass" to "fail" or vice versa).

[0125]

[0143] Furthermore, the controller may be configured to estimate the connection quality between ICs connected via an interconnect lane based on the comparison result and the amount of delay that caused the result. That is, in response to a certain amount of delay introduced by a delay line, if the comparison result converts (inverts) from a previous "pass" to "fail", the controller may infer that the connection quality is related to that certain amount of delay. Generally, the longer the delay, the better the connection quality, and vice versa. Quality estimation may comprise, for example, measuring eye pattern parameters of a signal received via an interconnect lane, such as eye width and / or eye height. To measure the eye height, the controller may further be configured to control a variable V REF to gradually adjust V REF to different levels as necessary to obtain an eye height measurement value.

[0126]

[0144] Quality estimation by the controller may also take the form of longer-term monitoring, during which the tendency of "fail" at various amounts of delay (and for respective eye pattern parameters) is detected and optionally addressed. Whether the estimation is instantaneous or long-term, the controller may execute or trigger one or more actions as discussed above if the connection quality is insufficient (e.g., below a threshold or if the degradation tendency exceeds a certain slope).

[0127]

[0145] The controller may further be configured to perform the aforementioned duty cycle distortion detection / measurement and the aforementioned eye width jitter measurement.

[0128]

[0146] The controller may further be configured to send a quality estimate value (e.g., a measured eye pattern parameter) to a computing device in which the multi-IC module is installed, and optionally from there to a computer-controlled server via a communication network. The quality estimate value may further be analyzed by the computing device or the computer-controlled server, each of which may issue an instruction to the user regarding the quality estimate and / or the result of its further analysis.

[0129]

[0147] More generally, for all versions of the I / O sensor, the I / O sensor may include one or more compensation delay elements configured to compensate for the true delay of the I / O sensor elements and / or a longer signal propagation distance required by the position of the I / O sensor as needed. The compensation delay buffer and phase shifter of FIG. 8 are examples of such compensation delay elements, where the first element delays the clock signal and the second element delays the data signal. Further examples regarding the distance to the I / O sensor requiring timing compensation are shown in FIG. 14. The importance of such compensation delay elements in the I / O sensor generally increases as the data rate of the monitored interconnect lane increases. At high data rates, it is necessary to precisely adjust the timing of sampling of the data signal, and if there are uncompensated delays associated with the I / O sensor (its elements and / or its position), the reliability of the quality estimate may be reduced, for example, by generating inaccurate measurements of eye pattern parameters.

[0130]

[0148] Advantages of the disclosed I / O sensor and I / O sensing method include - Complete data lane coverage - Complete coverage of driver and receiver (comparator, level shifter) circuits - Minimal impact on area and power - Use during test and in mission - Data analysis capabilities may be mentioned.

[0131]

[0149] The disclosed I / O sensors and I / O sensing methods may be useful, for example, in characterizing IC designs prior to fabrication. - Characterization of lane performance (eye width and jitter) in various PVT (process voltage temperature) ranges. - Characterization of inter-lane skew and crosstalk. - Verification of substrate design topology.

[0132]

[0150] The disclosed I / O sensors and I / O sensing methods may also be useful, for example, after the IC has been manufactured. - Detection of outliers in assembled multi-IC modules. - Operation of spare lanes (if such lanes are available). - Yield monitoring and early warning of yield degradation.

[0133]

[0151] The disclosed I / O sensors and I / O sensing methods may also be useful, for example, in monitoring the reliability of multi-IC modules operating in the field where inter-die lanes may degrade over time. Predictive maintenance such as operation of spare lanes and module replacement may be performed when the following faults are detected.

[0134]

[0152] Another option is to perform I / O sensing on each IC before each IC is ultimately packaged with a different IC, avoiding packaging together ICs with significant performance differences, e.g., receivers with significantly different delays. To this end, embodiments include a test device (a "tester") configured to send data to an IC connected to the tester, the IC including the disclosed I / O sensor. The tester has sent the data completely and is assumed not to be the cause of lane delay (which is not a significant delay in any case), so the delay may be due to the IC being tested. By testing every IC manufactured in this way, "fast" ICs (those with low lane delay) may be interconnected and packaged together, and the same applies to "slow" ICs. This prevents fast and slow ICs from being packaged together, resulting in die-to-die connections that are as slow as the slowest IC ("weakest link").

[0135]

[0153] This specification describes various circuit designs and circuit diagrams. It will be understood that these circuit designs may be embodied in an electronic (also referred to as "digital") representation (also referred to as "encoding"). The electronic representation may be stored, in particular, on a non-transitory computer-readable medium. Suitable electronic representations may include representations of electronic computer-aided design (ECAD) software, also referred to as electronic design automation (EDA) software. In this case, part of the representation may be stored across multiple electronic documents or files, which may include one or more libraries of ECAD software that provide details of the components of the circuit. The ECAD representation may provide instructions suitable for manufacturing (also referred to as "fabricating") the circuit represented in the design. According to the present disclosure, such electronic representations may be provided. As part of manufacturing an electronic circuit, a method of using an electronic representation of such an electronic circuit is further contemplated.

[0136]

[0154] The flowcharts, circuits, and block diagrams in the figures illustrate the architecture, functionality, and operation of possible examples of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, which includes one or more executable instructions for implementing the specified logical function. It should also be noted that each block in the block diagrams and / or flowchart diagrams, as well as combinations of blocks in the block diagrams and / or flowchart diagrams, can be implemented by a system based on dedicated hardware that performs the specified function or action, or a combination of dedicated hardware and computer instructions.

[0137]

[0155] In this specification and the claims, each of the terms "substantially", "essentially", and their forms, when representing a numerical value, means a deviation of up to 20% from that numerical value (i.e., ±20%). Similarly, when such terms represent a numerical range, they mean a range that is 20% wider (10% above and 10% below the explicit range).

[0138]

[0156] In this specification, any numerical range should be considered to specifically disclose not only the individual numerical values within that range but also all possible sub-ranges, and such sub-ranges and individual numerical values each constitute an embodiment of the present invention. This applies regardless of the width of the range. For example, a description of an integer range from 1 to 6 should be considered to specifically disclose sub-ranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and the individual numerical values within that range, such as 1, 4, 6. Similarly, for example, a description of a fractional range from 0.6 to 1.1 should be considered to specifically disclose sub-ranges such as from 0.6 to 0.9, from 0.7 to 1.1, from 0.9 to 1, from 0.8 to 0.9, from 0.6 to 1.1, from 1 to 1.1, etc., and the individual numbers within that range, such as 0.7, 1, and 1.1.

[0139]

[0157] The descriptions of various embodiments of the present invention are presented for illustrative purposes and are not intended to be exhaustive or limited to explicit descriptions. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein are chosen to best explain the principles of the embodiments, the practical application, or the technical improvements in the art found in the marketplace, or to enable those skilled in the art to understand the embodiments disclosed herein.

[0140]

[0158] In the description and claims of this application, the words "comprise", "include", and "have", and their forms, are not necessarily limited to the members in the list to which the word may be associated.

Claims

1. A programmable delay line, and A delay sampling device having the following inputs, A data signal that also functions as an input to a reference clock receiver configured to sample a data signal received from an interconnect lane between two integrated circuits (ICs) of a multi-IC module, and A delayed clock signal received from the programmable delay line, which is a delayed version of the clock signal that clocks the reference clock receiver A delay sampling device having, A comparison circuit configured to compare the data signal output of the delay sampling device with the data signal output of the reference clock receiver, A controller, Gradually adjust the amount of delay introduced by the programmable delay line, After each gradual adjustment of the delay, receive the result of the comparison from the comparison circuit, Estimate the connection quality between the two ICs via the interconnect lane based on at least one of the results and the amount of delay that caused the result A controller configured as such, and An I / O sensor comprising.

2. The programmable delay line includes a coarse delay line and a fine delay line connected in series, Each delay step of the coarse delay line is longer than each delay step of the fine delay line, The length of each delay step of the coarse delay line is configured to bring the rising edge of the delayed clock signal close to a place where the result of the comparison is likely to invert from "pass" to "fail", or vice versa, The length of each delay step of the fine delay line is configured to detect an exact point where the result of the comparison is likely to invert from "pass" to "fail", or vice versa. The I / O sensor of Claim 1.

3. The I / O sensor of Claim 1 or Claim 2, wherein the estimation of the connection quality includes calculation of eye pattern parameters of the data signal.

4. The I / O sensor of Claim 3, wherein the eye pattern parameter includes an eye width calculated based on the time distance between the inversion points of the comparison results on the left and right sides of the unit interval (UI) of the data signal.

5. The I / O sensor according to claim 4, wherein the controller is configured to operate the programmable delay line to scan the eye in one direction in order to detect the inversion point of the comparison result.

6. The controller is configured to select from two eye scan modes, wherein the two eye scan modes are a first eye scan mode for scanning a first side of the eye by increasing or decreasing the amount of delay introduced by the programmable delay line, and a second eye scan mode for scanning a second opposite side of the eye by increasing or decreasing the amount of delay introduced by the programmable delay line of the I / O sensor according to claim 4.

7. The clock signal for clocking the reference clock receiver is a multi-phase clock signal, in the first eye scan mode, one of the phases of the multi-phase clock signal is affected by the increase or decrease of the amount of delay introduced by the programmable delay line, in the second eye scan mode, another one of the phases of the multi-phase clock signal is affected by the increase or decrease of the amount of delay introduced by the programmable delay line, in both the first and second eye scan modes, the other one of the phases of the multi-phase clock signal is used to clock the reference clock receiver, of the I / O sensor according to claim 6.

8. The delay sampling device is a clock receiver having a reference voltage as an additional input that also functions as an input to the reference clock receiver, the reference voltage is a variable reference voltage, the eye pattern parameter further includes an eye height, the controller is further configured to measure the eye height by gradually adjusting the variable reference voltage between each of the first and second eye scan modes, thereby measuring the eye width at different voltage levels, of the I / O sensor according to claim 6 or claim 7.

9. The clock signal for clocking the reference clock receiver is a multi-phase clock signal, The I / O sensor according to any one of claims 6 to 8, wherein the controller is further configured to detect a duty cycle distortion of the polyphase clock signal based on only one of the two ice scan modes.

10. The clock signal for clocking the reference clock receiver is a polyphase clock signal having a duty cycle of about 50%, The I / O sensor according to any one of claims 4 to 9, wherein in the calculation of the eye width, the delayed clock signal received from the programmable delay line is only one phase of the polyphase clock signal.

11. The I / O sensor according to any one of claims 1 to 10, further comprising a compensation delay element configured to apply a certain amount of delay to the clock signal in order to compensate for the true delay of the programmable delay line.

12. The I / O sensor according to any one of claims 1 to 11, further comprising a compensation delay element configured to apply a certain amount of delay to the data signal in order to compensate for the true delay of the programmable delay line.

13. The I / O sensor according to any one of claims 1 to 12, further comprising a compensation delay element configured to apply a certain amount of delay to at least one of the data signal and the clock signal in order to compensate for the distance between the reference clock receiver and the I / O sensor.

14. The I / O sensor according to any one of claims 1 to 13, wherein the delay sampling device is a clock receiver having a reference voltage as an additional input that also functions as an input to the reference clock receiver.

15. The I / O sensor according to any one of claims 1 to 13, wherein the delay sampling device is a flip-flop.

16. The I / O sensor according to any one of claims 1 to 15, further comprising a timing measurement circuit configured to measure the delay provided by the programmable delay line.

17. The I / O sensor according to claim 16, wherein the timing measurement circuit comprises a ring oscillator circuit configured to selectively incorporate the programmable delay line.

18. A non-transitory computer-readable medium storing a computer-readable encoding of an I / O sensor, wherein the computer-readable encoding of the I / O sensor comprises a programmable delay line, A delay sampling device having the following inputs, A data signal that also functions as an input to a reference clock receiver configured to sample a data signal received from an interconnect lane between two integrated circuits (ICs) of a multi-IC module, and A delayed clock signal received from the programmable delay line, the delayed clock signal being a delayed version of the clock signal that clocks the reference clock receiver A delay sampling device having; A comparison circuit configured to compare the data signal output of the delay sampling device with the data signal output of the reference clock receiver; A controller, Gradually adjusting the amount of delay introduced by the programmable delay line, After each gradual adjustment of the delay, receiving the result of the comparison from the comparison circuit, Estimating the connection quality between the two ICs via the interconnect lane based on at least one of the results and the amount of delay that caused the result A controller configured as such, A non-transitory computer-readable medium comprising. **Claim 19** The computer-readable encoding of the I / O sensor further comprises any of the elements of any one of claims 2 to 17, the non-transitory computer-readable medium of claim 18.

Images