Integrated circuit package having an internal circuit for detecting external component parameters and parasitics

Abstract

Apparatus and techniques for an integrated circuit (IC) package to automatically detect external component parameters and parasitics via input / output pins. An exemplary IC package generally includes pins for coupling to components external to the IC package and at least one of a resistor detector, an inductor detector, or a capacitor detector coupled to the pins and configured to respectively detect at least one of resistance, inductance, or capacitance of a lumped parameter model for components external to the IC package. The resistor detector, inductor detector, or capacitor detector can also be configured to detect parasitics associated with at least one of a component, a pin, or a connection between a component and a pin.

Description

Technical Field

[0001] (Cross - Reference to Related Applications)

[0001] This application claims priority to U.S. Patent Application No. 17 / 808,357, filed on June 23, 2022, which is incorporated herein by reference.

[0002]

[0002] Certain aspects of the present disclosure generally relate to electronic circuits, and more particularly, to integrated circuit packages having one or more off - chip components and on - chip detection schemes related to parasitics.

Background Art

[0003]

[0003] In recent years, electronic devices such as computers, wireless communication devices (e.g., mobile phones and Wi - Fi access points), and wearable devices have become widespread. Electronic devices typically include one or more integrated circuits (ICs). These ICs are typically implemented as one or more semiconductor dies that can be coupled to other electronic components, and all of them can be included within an IC package for assembly on a printed circuit board (PCB) in order to include them all within an electronic device.

[0004]

[0004] By packaging integrated circuit dies and other components together within a module (also referred to herein as a "packaged assembly"), an electronic device can have a smaller form factor compared to known electronic devices while providing improved signal performance (e.g., reduction of transient overshoot and undershoot), electrical performance (e.g., reduction of power consumption), and thermal performance (e.g., reduction of heat generation). For example, a mobile phone can have improved battery life due to the reduction of power consumption by a transceiver module in which dies and other components are assembled within a packaged assembly.

Summary of the Invention

[0005]

[0005] The systems, methods, and devices of the present disclosure each have several aspects, and none of those aspects alone contribute to their desirable attributes. Without limiting the scope of the present disclosure as expressed by the following claims, some features will now be briefly discussed. After considering this discussion, and particularly after reading the section entitled "Detailed Description of the Invention," the advantages described herein will be understood as to how the features of the present disclosure provide them.

[0006]

[0006] Certain aspects of the present disclosure generally relate to apparatuses and techniques for an integrated circuit (IC) package to detect external component parameters and parasitics.

[0007]

[0007] Certain aspects of the present disclosure are directed to an integrated circuit (IC) package. The IC package generally includes pins for coupling to components external to the IC package, and at least one of a resistor detector, an inductor detector, or a capacitor detector configured to detect at least one of a resistance, an inductance, or a capacitance of a lumped parameter model associated with at least one of an external component of the IC package, a parasitic associated with the component, the pin, or a connection between the component and the pin.

[0008]

[0008] Certain aspects of the present disclosure are directed to a method for parameter determination. The method generally includes coupling at least one of a resistor detector, an inductor detector, or a capacitor detector inside an integrated circuit (IC) package to a pin of the IC package, the pin being coupled to a component external to the IC package. The method also includes using at least one of a resistor detector, an inductor detector, or a capacitor detector inside the IC package to detect at least one of a resistance, an inductance, or a capacitance of a lumped parameter model related to a component external to the IC package and related to a parasitic associated with at least one of the component, the pin, or a connection between the component and the pin.

[0009]

[0009] Certain aspects of the present disclosure are directed to an integrated circuit (IC) package. The IC package generally includes a pin for coupling to a component external to the IC package and at least one of means for detecting a resistance, means for detecting an inductance, or means for detecting a capacitance of a lumped parameter model related to a component external to the IC package and related to a parasitic associated with at least one of the component, the pin, or a connection between the component and the pin.

[0010]

[0010] To achieve the above and related objects, one or more aspects include features that are hereinafter fully described and particularly pointed out in the claims. The following description and the accompanying drawings detail specific exemplary features of one or more aspects. However, these features are only a small part of the various ways in which the principles of the various aspects can be employed.

Brief Description of the Drawings

[0011]

[0011] To obtain a more specific description, briefly summarized above, reference is made to the aspects, some of which are shown in the accompanying drawings, so that the above-described features of the present disclosure can be understood in detail. However, it should be noted that the accompanying drawings show only specific exemplary aspects of the present disclosure and should not be regarded as limiting the scope of the present disclosure, because the present description may admit other equally effective aspects.

Figure 1

[0012] A block diagram of an exemplary device capable of implementing aspects of the present disclosure is shown.

Figure 2

[0013] A block diagram of an exemplary circuit comprising an integrated circuit (IC) package and one or more external components according to a particular aspect of the present disclosure.

Figure 3

[0014] An exemplary implementation of an inductance detector according to a particular aspect of the present disclosure is shown.

Figure 4

[0015] An exemplary implementation of an exemplary peak detector according to a particular aspect of the present disclosure is shown.

Figure 5

[0016] An exemplary implementation of a resistance detector according to a particular aspect of the present disclosure is shown.

Figure 6

[0017] An exemplary implementation of a capacitance detector according to a particular aspect of the present disclosure is shown.

Figure 7

[0018] A flowchart of an exemplary operation for parameter determination according to a particular aspect of the present disclosure.

[0012]

[0019] For ease of understanding, the same reference numbers are used to designate the same elements common to the figures, where possible. It is contemplated that elements disclosed in one aspect can be beneficially utilized in other aspects without specific recitation.

DETAILED DESCRIPTION OF THE INVENTION

[0013]

[0020] Certain aspects of the present disclosure provide circuits and techniques for an integrated circuit (IC) package to automatically detect external component parameters and parasitics, and such circuits are present inside the IC package. Such circuits and techniques may enable the design parameters of the IC package to be adaptively changed based on the detected external parameters and parasitics.

[0014]

[0021] Hereinafter, various aspects of the present disclosure will be more fully described with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout the present disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art should understand that the scope of the present disclosure is intended to include any and all aspects of the present disclosure disclosed herein, regardless of whether the present disclosure is implemented independently of any other aspect of the present disclosure or in combination with any other aspect of the present disclosure. For example, an apparatus can be implemented or a method can be practiced using any number of the aspects described herein. Furthermore, the scope of the present disclosure is intended to include such apparatus or methods practiced using other structures, functions, or a combination of structures and functions in addition to, or other than, the various aspects of the present disclosure described herein. It should be understood that any aspect of the present disclosure disclosed herein can be embodied by one or more elements of the claims.

[0015]

[0022] As used herein, the term "connected to" in various tenses of the verb "connect" can mean that element A is directly connected to element B, or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B). In the case of electrical components, the term "connected to" can also be used herein to mean electrically connecting element A and element B (and any components electrically connected therebetween) using wires, traces, or other conductive materials.

[0016] Exemplary Device

[0023] FIG. 1 shows an exemplary device 100 capable of implementing aspects of the present disclosure. The device 100 can be a battery-operated device such as a mobile phone, a personal digital assistant (PDA), a handheld device, a wireless device, a laptop computer, a tablet, a smartphone, a wearable device, etc.

[0017]

[0024] The device 100 may include a processor 104 that controls the operation of the device 100. The processor 104 may also be referred to as a central processing unit (CPU). The memory 106 can include both a read-only memory (ROM) and a random access memory (RAM), and provides instructions and data to the processor 104. A portion of the memory 106 may also include a non-volatile random access memory (NVRAM). The processor 104 typically performs logical and arithmetic operations based on program instructions stored in the memory 106.

[0018]

[0025] In certain embodiments, device 100 may also include a housing 108 that can include a transmitter 110 and a receiver 112 to enable the transmission and reception of data between device 100 and a remote location. For certain embodiments, the transmitter 110 and the receiver 112 can be combined into a transceiver 114. One or more antennas 116 can be attached to or otherwise coupled to housing 108 and electrically connected to transceiver 114. Device 100 may also include multiple transmitters, multiple receivers, and / or multiple transceivers (not shown).

[0019]

[0026] Device 100 may also include a signal detector 118 that can be used for the purpose of detecting and quantifying the level of signals received by transceiver 114. Signal detector 118 can detect such signal parameters as, among other things, total energy, energy per subcarrier per symbol, and power spectral density. Device 100 may also include a digital signal processor (DSP) 120 for use in processing signals.

[0020]

[0027] Device 100 may further include a battery 122 that is used to power the various components of device 100. Device 100 may also include a power management integrated circuit (power management IC or PMIC) 124 for managing the power from the battery to the various components of device 100. PMIC 124 can perform various functions related to the device, such as DC-DC conversion, battery charging, power source selection, voltage scaling, power sequencing, etc. In certain embodiments, PMIC 124 can include at least a portion of a power supply circuit that can include a switched-mode power supply (SMPS), or a linear voltage regulator such as a low dropout (LDO) regulator 125.

[0021]

[0028] Device 100 may further include one or more speakers (not shown) for converting an electrical signal into an audio signal. In this case, device 100 may include one or more amplifiers for driving the speakers, and these amplifiers may be powered by one or more power circuits that may be part of the PMIC or that can receive a power supply voltage rail generated by the PMIC.

[0022]

[0029] The various components of device 100 can be integrally coupled by a bus system 126, which may include a power bus, a control signal bus, and / or a status signal bus in addition to a data bus.

[0023] Exemplary IC package supporting detection of internal inductance, capacitance, and / or resistance of external components

[0030] FIG. 2 is a block diagram of an exemplary circuit 200 including an integrated circuit (IC) package 205 capable of implementing aspects of the present disclosure. IC package 205 may have pins 250 (e.g., input / output (I / O) pins) for coupling IC package 205 to one or more external components 270 (i.e., components external to the IC package).

[0024]

[0031] Many circuits (such as circuit 200) include pins (such as pin 250) for coupling an IC package to external components (such as external component 270), rather than being entirely on-chip (e.g., inside a single IC package such as IC package 205). The entire circuit can be implemented on a printed circuit board (PCB). In some cases, external components and parasitics (e.g., of the pins, PCB, and / or the external components themselves) can introduce additional variables to consider during circuit design. Thus, in a single circuit design, it may not be possible to achieve optimized performance for all conditions under which the circuit can operate. Therefore, automatic detection, determination, and / or measurement of component parameters and parasitics are desirable to enable automatic configuration of IC packages.

[0025]

[0032] Some aspects of circuit design can also be adaptively configured using programmable components. However, some components within a circuit may or may not be programmable, but adding programmable components generally involves performing additional circuit testing and circuit tuning. Furthermore, although frequency domain measurement tools exist, frequency domain measurement of parasitics and component parameters is generally complex and consumes additional power and area, making such implementations impractical or infeasible.

[0026]

[0033] One approach for detecting external parasitics and component parameters involves using sensors within an IC package that are coupled to external components via one or more sense pins separate from the input / output pins of the IC package. However, this design can be costly and difficult to integrate due to the additional pin and wiring resources. Furthermore, such sensors may not actually be designed to measure external passive component parameters and parasitics, and thus may be unreliable for such applications.

[0027]

[0034] Therefore, certain aspects of the present disclosure provide techniques and internal circuitry for detecting external parasitic and component parameters via the input / output pins of an IC package without using any additional sense pins or sensor interfaces. This detection scheme can be automatically executed for certain aspects (e.g., during power-up of the IC package or during other idle times of the operation of the IC package).

[0028]

[0035] Accordingly, as shown in FIG. 2, the IC package 205 may also include an internal detection circuit 210 for detecting external component parameters and parasitics via the pin 250. The detection circuit 210 may include one or more of an inductance detector 220, a resistance detector 230, and a capacitance detector 240. The IC package 205 may optionally include a switch network 215 including one or more switches coupled between the pin 250 and at least one of the inductance detector 220, the resistance detector 230, or the capacitance detector 240. These switches may enable connecting the detector to the pin 250 when a particular detector is used and disconnecting the detector from the pin 250 during the mission mode of the IC package circuitry normally associated with the pin 250.

[0029]

[0036] The inductance detector 220, the resistance detector 230, and / or the capacitance detector 240 can be configured to detect at least one of the inductance, resistance, or capacitance of a lumped parameter model (e.g., the lumped parameter model 328 shown in FIGS. 3, 5, and 6, also known as a "lumped element model") for an external component 270, respectively. The inductance detector 220, the resistance detector 230, and / or the capacitance detector 240 can be configured to detect a parasitic 260 associated with at least one of the external component 270, the pin 250, or a connection 265 (e.g., a wiring) between the external component 270 and the pin 250 (e.g., by a PCB structure, a via, and / or a trace wiring).

[0030]

[0037] Based on the detected inductance, resistance, and / or capacitance of the lumped parameter model, one or more parameters (e.g., adjustments or settings for adjustable components in an IC package and / or other circuits) can be selected, and based on those selected parameters (i.e., adaptive parameter selection), one or more components can be adjusted. Such detection and selection can save the costs of testing, debugging, and / or calibration time and non-recurring engineering (NRE) costs. Furthermore, by understanding the inductance, resistance, and / or capacitance when looking out from the pin 250 and selecting parameters accordingly, various performance specifications can be improved, the stability margin can be increased, and overdesign can be avoided.

[0031]

[0038] The inductance detector 220, the resistance detector 230, or the capacitance detector 240 is shown as a separate detector, but one of ordinary skill in the art will understand that some components in one of these detectors may be used by one or more of the other detectors to perform the corresponding detection process described in more detail below. For example, the resistance detector 230 and the capacitance detector 240 can be combined and share components in some cases.

[0032]

[0039] In some aspects, at least one of the inductance detector 220, the resistance detector 230, or the capacitance detector 240 can be configured to operate in the time domain. For example, in some aspects, at least one of the detectors can be configured to output a time-domain drive signal (e.g., to an external component 270) and sense a time-domain response signal (e.g., from the external component 270). These drive and response signals can be used to determine at least one of the inductance, resistance, or capacitance of a lumped parameter model regarding the external component 270, as described in more detail below.

[0033] Exemplary inductance detection circuit

[0040] FIG. 3 shows an exemplary implementation of the inductance detector 220 according to a particular aspect of the present disclosure. As shown, the external component 270 can be represented using a lumped parameter model 328 that includes a series resistor 330 having a resistance R p a series inductor 335 having an inductance L p and a shunt capacitor 340 having a capacitance C L The inductance detector 220 can be configured to determine the inductance L p of the inductor 335 within the lumped parameter model.

[0034]

[0041] The inductance detector 220 may include a pulse generator 302, a switch driver 304, and a switch 306. The switch 306 can be coupled between the power rail 308 and the pin 250, and the switch driver 304 can be coupled between the output of the pulse generator 302 and the control input of the switch 306 (e.g., the gate of the transistor implementing the switch 306).

[0035]

[0042] In some embodiments, the switch driver 304 can be configured to drive the switch 306 at multiple different slew rates (wherein, in this case, "slew rate" generally refers to the change in voltage or current per unit time). Therefore, in some embodiments, the switch driver 304 is coupled between the output of the pulse generator 302 and the control input of the switch 306 through a switch 320 (labeled "D0, D1,..., D M-1 " and also representing the digital control signals for those switches) and may include a plurality of drive circuits 322 that are selectively coupled. In some embodiments, at least one of the plurality of drive circuits 322 can be implemented as a plurality of serially connected inverters, a plurality of serially connected buffers, or a combination thereof as shown in the figure. The paths associated with each drive circuit 322 may be individually referred to as "switch driver paths" or collectively as "switch driver paths". Each drive circuit 322 may have different delays, which can be implemented by having different numbers of inverters and / or buffers within each drive circuit. By having different drive strengths in each of the drive circuits 322, different switch driver paths can be configured to drive the switch 306 using control signals (e.g., pulses from the pulse generator 302) having different slew rates.

[0036]

[0043] According to certain aspects, the inductance detector 220 may further include a peak detector 310, a comparator 314, an N-bit successive approximation register (SAR) 316, and digital logic 318. The peak detector 310 may have an input coupled to the pin 250 and the switch 306. As shown, the comparator 314 may have a first input coupled to the output of the peak detector 310 and a second input coupled to the reference voltage node 313. For certain aspects, the reference voltage node 313 may be coupled to a reference voltage generator 312 capable of generating a reference voltage (labeled as "V th ") using any of various suitable techniques. The output of the comparator 314 can be coupled to the input of the SAR 316, and the output of the SAR 316 can be coupled to the logic 318. For the N-bit SAR 316, N is the number of cycles passing through the inductance detector 220 and represents the inductance resolution.

[0037]

[0044] The inductance detector 220 can use an SAR-based charging scheme according to an equation related to the instantaneous voltage L across the inductor to determine the inductance V p of the inductor 335. Therefore, inductance detection can be based on introducing currents with different slew rates to the pin 250 and detecting the peak voltage (V L ) across the inductor 335 resulting therefrom using the peak detector 310. The voltage V e can be represented by the following equation, L which is as follows:

[0038]

Equation

[0039] wherein,

[0040]

Equation

[0041] is the change over time (through-rate) of the current flowing through the inductor. In the case of a higher frequency through-rate, the DC component (resistance) and capacitance of the lumped parameter model 328 may be negligible, so the sensed voltage represents the inductance of the lumped parameter model 328.

[0042]

[0045] Using this equation,

[0043]

Equation

[0044] By setting it to an extremely large value (for example, using a fast rise time for the pulse received at the control input of switch 306), even when the inductance L p is extremely small, based on the measured voltage V e it is possible to detect the inductance L p For example, in some cases, the inductance L p can be in the range of nanohenries (nH). Different through-rates from different switched driver paths make it possible to vary the time (dt) for which current is driven through inductor 335 depending on which switched driver path is selected.

[0045]

[0046] The inductance detector 220 can function by sequentially using different switched driver paths to achieve different peak voltages at pin 250 based on the values stored in SAR 316 and the encoding of the logic 318 for selecting the next switched driver path. The peak detector 310 can be configured to detect the peak voltage, and the comparator 314 compares those peak voltages with a reference voltage generated by the reference voltage generator 312 (also referred to as the "threshold voltage" and thus "V thIt can be configured to compare with (e.g., something labeled with 」). In some embodiments, the reference voltage can be designed to be equal to half of the voltage of the pulse from the pulse generator 302 (e.g., the midpoint of the highest possible peak voltage value). The comparator 314 is configured to compare the peak voltage with the reference voltage in each iteration (each cycle). When the comparator 314 determines that the peak voltage is lower than the threshold voltage, the comparator will output a logic 「0」. When the comparator 314 determines that the peak voltage is greater than the threshold voltage, the comparator will output a logic 「1」.

[0046]

[0047] SAR316 can be configured to store (and shift) the 1-bit value from the comparator 314 based on each of the N comparisons performed. The logic 318 can have one or more outputs coupled to the control inputs of the switches 320 within the switch driver 304. The logic 318 can be configured to control the selection of the switch driver path based on the digital value within the SAR316. Specifically, the logic 318 can serve to control the switch 320 based on the mapping of the bits of the SAR316 to the switch 320.

[0047]

[0048] At the end of the N cycles passing through the inductance detector 220, the selected switch driver path should result in the peak voltage on pin 250 approximating the reference voltage, indicating that the SAR-based quantization of the external inductance has been successfully completed. After the N cycles, the N-bit value stored in the SAR316 can be used to determine the inductance based on the mapping of the inductance to the digital code, as shown in graph 350 for example with N = 4 cycles. For example, an SAR output of 0101b can indicate an inductance of approximately 5 nH. The drive strength in the drive circuit 322 can be designed to provide a linear mapping of the inductance to the digital code, such as the linear relationship shown in graph 350.

[0048]

[0049] FIG. 4 shows an exemplary implementation of the peak detector 310 according to a particular aspect of the present disclosure. In the case of the detection scheme described above, the voltage across the inductor 335 can be made to occur as a very short pulse in each cycle. The peak detector 310 can be configured to capture and hold the peak voltage of this short pulse.

[0049]

[0050] The peak detector 310 may include a first transistor 402 having a drain coupled to pin 250 and a first capacitive element C. The first capacitive element C can be coupled between the source of the first transistor 402 and the reference potential node (e.g., electrical ground) of the peak detector 310. When the gate and drain of the first transistor 402 are integrally connected, the first transistor becomes a diode-connected transistor, and thus this peak detector effectively includes a series diode coupled to a shunt capacitor (e.g., the first capacitive element C). The output of this peak detector becomes the cathode of the diode (e.g., the source of the first transistor 402). Therefore, the first capacitive element C can be configured to charge when the voltage at pin 250 is greater than the voltage across the first capacitive element C, and can be configured to stop charging when the voltage at pin 250 is less than the voltage across the first capacitive element C. In this way, the first capacitive element C can be configured to detect and hold the peak voltage value at pin 250 during the detection window.

[0050]

[0051] According to a particular aspect, the peak detector 310 can be implemented as an AC-coupled diode peak detector as shown. In this case, the peak detector 310 may include a second capacitive element C coupled between the drain and gate of the first transistor 402 C and may include. The second capacitive element C CReverse leakage can be prevented by coupling a DC signal to pin 250. The peak detector 310 may also include a resistive element R coupled between the gate of the first transistor 402 and the reference potential node. C It may also include.

[0051]

[0052] In some embodiments, the peak detector 310 may also include a second transistor 404 having a drain coupled to the source of the first transistor 402. The source of the second transistor 404 can be coupled to the first capacitive element C and to the first input of the comparator 314 (e.g., at the node labeled "V e "). The second transistor 404 can function as an isolation switch configured to isolate supply ripple and leakage from pin 250.

[0052]

[0053] The peak detector 310 may also include control logic circuitry 414 for the second transistor 404, which may include a third transistor 406, a fourth transistor 408, a current source 410, and a switch capacitor array (also referred to as a "capacitor bank"). The switch capacitor array can be implemented by M parallel paths, each path including a switch 412 coupled in series with a capacitive element (labeled "C-Bank <0:M-1> "). For a particular embodiment, M = 2 N . The source of the third transistor 406 can be coupled to the gate of the second transistor 404. The current source 410 can be coupled between the power rail 308 and the drain of the third transistor 406. The fourth transistor 408 can have a drain coupled to the gate of the second transistor 404 and the source of the third transistor 406, and can have a source coupled to the reference potential node of the peak detector 310. In some embodiments, the control input signals ("V drv " and

[0053]

Number

[0054] Those labeled as such can be complementary signals. The control logic circuit 414 can be configured to activate the second transistor 404 at the start of the detection window and deactivate the second transistor 404 at the end of the detection window. In some embodiments, the detection window can start when a new switched driver path is selected and a new pulse is generated.

[0055]

[0054] In some aspects, the switch capacitor array can be coupled between the gate of the second transistor 404 and the reference potential node of the peak detector 310. The switch capacitor array can be used to control the timing of turning off the second transistor 404. The capacitive element C-Bank within the switch capacitor array <0:M-1> can be selected using a control signal (labeled as "CTRL" <0:M-1> ") for the switch 412 based on the selected switched driver path (and the corresponding slew rate). For example, the faster the slew rate of the selected switched driver path, the shorter the time to turn on the peak detector 310. In that case, the switch capacitor array can be selected to have a smaller capacitance. This can help minimize (or at least reduce) the impact of the supply ripple on the voltage held on the peak detector 310.

[0056]

[0055] Graphs 420 and 430 respectively show an exemplary input signal and output signal of peak detector 310. The input signal of peak detector 310 (represented by the y-axis and labeled "Vin" in Graph 420) can be the return signal received at pin 250 from an external component, and the output signal of peak detector 310 (represented by the y-axis and labeled "V e " in Graph 430) can indicate the peak voltage of the input signal detected during the detection window. In the illustrated embodiment, at time 435 during the detection window, the input signal rapidly rises to a peak value (labeled "Peak"), and peak detector 310 detects that peak value and holds that value (e.g., as "Stored Peak"). As shown at time 440 in Graph 420, even if a ripple voltage occurs at the input of peak detector 310, the output of peak detector 310 does not change. Furthermore, at time 445 outside the frame of the detection window, even if the input signal exceeds the peak voltage, peak detector 310 will hold the stored peak value detected during the detection window (e.g., will not overwrite it).

[0057] Exemplary Resistance Detection Circuit

[0056] FIG. 5 shows an exemplary resistor detector 230 according to a particular aspect of the present disclosure. Resistor detector 230 can be configured to determine the resistance R of resistor 330 in lumped parameter model 328. p to be determined.

[0058]

[0057] The resistance detector 230 may include a control logic 502, a first current source 504 configured to supply a first current (labeled as "I1"), a first switch 508 coupled between the first current source 504 and the pin 250, a second current source 506 configured to supply a second current (labeled as "I2"), and a second switch 510 coupled between the second current source 506 and the pin 250. The second current should be different from the first current. The first current source 504 can be coupled between a power rail (e.g., power rail 308) and the first switch 508, and the second current source 506 can be coupled between the power rail and the second switch 510. The first current source 504, the second current source 506, the first switch 508, and / or the second switch 510 can each be implemented by, for example, one or more transistors. The resistance detector 230 may further include a first sample-and-hold (S&H) circuit 512 having an input coupled to the pin 250, a second S&H circuit 514 having an input coupled to the pin 250, and an analog-to-digital converter (ADC) 518 having one or more inputs coupled to the output of the first S&H circuit 512 and the output of the second S&H circuit 514.

[0059]

[0058] The resistance detector 230 (and, more specifically, the control logic 502) can be configured to close the first switch 508 at the start of a first period for supplying a first current from the first current source 504 to the pin 250. The first period can have a time duration t1. By supplying the first current to the pin 250, a resistor voltage can be generated across one or more external resistance elements (represented by the resistor 330), and one or more external capacitive elements (e.g., those represented by the capacitor 340) can be charged to generate a capacitor voltage. This charging can be performed at a low frequency such that the DC component and the capacitive element are dominant and the inductive element in the lumped parameter model 328 has a negligible effect (e.g., there is little or no voltage drop across the inductive element). During the first period, the first S&H circuit 512 can be configured to sample the first voltage (labeled as "V1") of the pin 250. At the end of the first period, the resistance detector 230 can further be configured to open the first switch 508, and the first S&H circuit 512 can be configured to hold the sampled first voltage. After the first period, the external capacitive element can be discharged.

[0060]

[0059] The resistance detector 230 (and, more specifically, the control logic 502) can further be configured to close the second switch 510 at the start of a second period for supplying a second current from the second current source 506 to the pin 250, thereby generating a voltage across the external resistance element and the external capacitive element as described above. The second period can have a time duration t2. During the second period, the second S&H circuit 514 can be configured to sample the second voltage (labeled as "V2") of the pin 250. At the end of the second period, the resistance detector 230 can further be configured to open the second switch 510, and the second S&H circuit 514 can be configured to hold the sampled second voltage. After the second period, the external capacitive element can be discharged.

[0061]

[0060] The time allocated to discharge the external capacitive element can be determined based on the known value of the resistance of the pull-down network used to discharge the capacitive element and the estimated range of the capacitance C of the capacitor 340 in the lumped parameter model. Based on these values, a resistance-capacitance (RC) time constant can be estimated, and the resistance detector 230 can be configured to wait for a corresponding amount of time to ensure that the external capacitive element is actually discharged (e.g., substantially discharged such that it has a negligible impact for the purpose of resistance detection). L Based on these values, a resistance-capacitance (RC) time constant can be estimated, and the resistance detector 230 can be configured to wait for a corresponding amount of time to ensure that the external capacitive element is actually discharged (e.g., substantially discharged such that it has a negligible impact for the purpose of resistance detection).

[0062]

[0061] Based on the above sequence, the voltage difference (e.g., "ΔVout") between the held first voltage and the held second voltage at pin 250 can be expressed as follows.

[0063]

Equation

[0064] Therefore, the first product of the value of the first current and the duration of the first period (t1) can be configured to be equal to the second product of the value of the second current and the duration of the second period (t2). That is, the current and the period can be set such that I1 * t1 = I2 * t2. Thus, since I1 * t1 = I2 * t2, the capacitance C of the capacitor 340 in the lumped parameter model L becomes negligible. That is, the voltage difference between the held first voltage and the held second voltage at pin 250 can instead be approximated as follows. ΔVout = (I1 - I2) * R p

[0065]

[0062] The resistance detector 230 may further use an ADC 518 to quantize the voltage difference between the held first voltage and the held second voltage, and based on the reconstructed equation, the resistance R of the resistor 330 in the lumped parameter model p can be configured to be determined.

[0066]

Number

[0067]

[0063] According to a particular aspect, the resistance detector 230 may further include an amplifier 516 having a first input coupled to the output of the first S&H circuit 512, a second input coupled to the output of the second S&H circuit 514, and an output coupled to one or more inputs of the ADC 518. The amplifier 516 can be configured to amplify the voltage difference between the held first voltage and the held second voltage. In this case, the resistance detector 230 uses the ADC 518 to quantize the amplified voltage difference, and based on the value of the first current, the value of the second current, and the amplified and quantized voltage difference, the resistance R of the resistor 330 in the lumped parameter model p can be configured to be determined.

[0068] Exemplary capacitance detection circuit

[0064] FIG. 6 shows an exemplary capacitance detector 240 according to a particular aspect of the present disclosure. The capacitance detector 240 can be configured to determine the capacitance C of the capacitor 340 in the lumped parameter model 328 L can be configured to be determined.

[0069]

[0065] The capacitance detector 240 may include control logic 602, a current source 604, a switch 606, a sample-and-hold (S&H) circuit 608, and an analog-to-digital converter (ADC) 610. As shown, the current source 604 can be coupled between a power supply rail (e.g., power supply rail 308) and the switch 606, the switch 606 can be coupled between the current source 604 and pin 250, and the S&H circuit 608 can be coupled between pin 250 and the ADC 610. The current source 604 and / or the switch can each be implemented, for example, by one or more transistors. The control logic 602 may have an output coupled to a control input of the switch 606.

[0070]

[0066] The capacitance detector 240 (and, more specifically, the control logic 602) can be configured to close the switch 606 at the start of a period for charging one or more capacitive elements external to the IC package, represented by the capacitor 340, with current from the current source 604. This charging can be performed at a low frequency such that the capacitive elements are dominant and the resistive and inductive elements in the lumped parameter model 328 have a negligible effect. The capacitance detector 240 can further be configured to use the S&H circuit 608 to sample the voltage at pin 250 during the period, hold the sampled voltage at the end of the period, and open the switch 606 at the end of the period.

[0071]

[0067] The capacitance detector 240 (and, more specifically, the control logic 602) can also use the ADC 610 to quantize the held voltage and determine the capacitance C of the capacitor 340 in the lumped parameter model 328 based on the value of the current, the duration of the period, and the quantized voltage. L For example, the capacitance detector 240 can be configured to determine the capacitance C of the capacitor 340 in the lumped parameter model using the following equation: L and can be configured to determine the capacitance C of the capacitor 340 in the lumped parameter model,

[0072]

Equation

[0073] Wherein, I is the current from the current source 604, t is the length of time of the period, and V C is the voltage sampled by the S&H circuit 608.

[0074]

[0068] FIG. 6 also includes plots 630 and 640 showing the input voltage and output voltage of the capacitance detector 240 at times before, during, and after the detection period, respectively. As shown in plot 630, the switch 606 can be closed by changing the control input to the switch 606 from logic low to logic high. While the switch 606 is closed, one or more capacitive elements external to the IC package, represented by the capacitor 340, are charged by the current from the current source 604. The switch 606 remains closed for a length of time t during which the voltage at pin 250 (represented by the y-axis and labeled "output" in graph 640) increases and is sampled by the S&H circuit 608. At the end of this period, the switch 606 can be opened (as indicated by changing the control input to the switch 606 to logic low), and the S&H circuit 608 can hold the sampled voltage. The held voltage can then be quantized (e.g., by the ADC 610), and the quantized value can be used to calculate the capacitance C of the capacitor 340 in the lumped parameter model based on the above equation. L can be used.

[0075] Exemplary Operations for Parameter Determination

[0069] FIG. 7 is a flowchart of an exemplary operation 700 for determining the parasitic and component parameters external to an IC package (such as the IC package 205) according to a particular aspect of the present disclosure. The operation 700 can be performed using a detection circuit within the IC package, such as the detection circuit 210 within the IC package 205 of FIG. 2.

[0076]

[0070] Operation 700 can start by coupling at least one of an inductance detector (e.g., inductance detector 220), a resistance detector (e.g., resistance detector 230), or a capacitance detector (e.g., capacitance detector 240) inside the IC package to a pin (e.g., pin 250) of the IC package in block 702. This pin can be coupled to an external component (e.g., external component 270) outside the IC package. In block 704, operation 70 can further include detecting at least one of the resistance, inductance, or capacitance of a lumped parameter model (e.g., lumped parameter model 328) related to an external component of the IC package and related to a parasitics (e.g., parasitics 260) associated with at least one of that component, the pin, or the connection (e.g., connection 265) between that component and the pin, using at least one of a resistance detector, an inductance detector, or a capacitance detector inside the IC package.

[0077]

[0071] According to a particular aspect, coupling in block 702 can involve closing one or more switches (e.g., switches within switch network 215) coupled between the pin and at least one of a resistance detector, an inductance detector, or a capacitance detector.

[0078]

[0072] According to certain aspects, detecting at block 704 can involve operating at least one of a resistance detector, an inductance detector, or a capacitance detector in the time domain. In certain aspects, detecting at block 704 can involve generating a drive signal (e.g., via switch driver 304) within the IC package, outputting the drive signal to a component via a pin of the IC package, and receiving a response signal from the component and parasitics via a pin of the IC package. In this case, the drive signal can be a time domain drive signal, and the response signal can be a time domain response signal.

[0079]

[0073] According to certain aspects, detecting capacitance at block 704 involves closing a switch (e.g., switch 606) coupled between a current source (e.g., current source 604) and a pin at the start of a period for charging a capacitive element (e.g., capacitor C L ) in a lumped parameter model with current from the current source, and opening the switch at the end of the period. In this case, detecting capacitance can further involve sampling the voltage of the pin during the period using a sample and hold (S&H) circuit (e.g., S&H circuit 608), and holding the sampled voltage at the end of the period using the S&H circuit. In certain aspects, detecting capacitance can further involve quantizing the held voltage using an analog to digital converter (ADC) (e.g., ADC 610), and determining the capacitance of the capacitive element in the lumped parameter model based on the value of the current, the duration of the period, and the quantized voltage.

[0080]

[0074] According to certain aspects, detecting the resistance at block 704 may involve closing a first switch (e.g., first switch 508) coupled between the first current source and the pin at the start of a first period to supply a first current (e.g., I1) from the first current source (e.g., first current source 504) to the pin, and opening the first switch at the end of the first period. In certain aspects, detecting the resistance may further involve sampling a first voltage of the pin during the first period using a first S&H circuit (e.g., S&H circuit 512), and holding the sampled first voltage at the end of the first period. Detecting the resistance may also involve closing a second switch (e.g., second switch 510) coupled between the second current source and the pin at the start of a second period to supply a second current (e.g., I2) from the second current source (e.g., second current source 506) to the pin, and opening the second switch at the end of the second period. In certain aspects, detecting the resistance may further involve sampling a second voltage of the pin during the second period using a second S&H circuit (e.g., S&H circuit 514), and holding the sampled second voltage at the end of the second period. Detecting the resistance may further involve quantizing the voltage difference between the held first voltage and the held second voltage using an analog-to-digital converter (ADC) (e.g., ADC518), and determining the resistance of a resistor element (e.g., resistor R p ) in the lumped parameter model based on the value of the first current, the value of the second current, and the quantized voltage difference. In this case, the first product of the value of the first current and the duration of the first period can be made substantially equal to the second product of the value of the second current and the duration of the second period so that the capacitance of the lumped parameter model can be ignored.

[0081]

[0075] In some embodiments, detecting the resistance may further involve amplifying the voltage difference between the held first voltage and the held second voltage (e.g., using amplifier 516). In this case, quantizing the voltage difference between the held first voltage and the held second voltage may involve quantizing the amplified voltage difference.

[0082]

[0076] According to certain embodiments, detecting the inductance at block 704 may involve using a successive approximation register (SAR)-based charging scheme (e.g., using SAR 316) to charge the component through the pin over several cycles. In certain embodiments, detecting the inductance may involve generating a pulse using a pulse generator (e.g., pulse generator 302), selecting a path from among a plurality of paths (e.g., a plurality of drive circuits 322) within a switched driver (e.g., switched driver 304), modifying the slew rate of the pulse (e.g., via logic 318) using the selected path within the switched driver, and driving a switch (e.g., switch 306) coupled between a power rail (e.g., power rail 308) and the pin using the pulse having the modified slew rate. In certain embodiments, detecting the inductance may further involve detecting the peak of the voltage signal received from the pin (e.g., via peak detector 310) and comparing the detected peak of the voltage signal to a reference voltage (generated, e.g., using reference voltage generator 312) using a comparator (e.g., comparator 314). In this case, detecting the inductance may involve storing the digital value output from the comparator into a successive approximation register (SAR) (e.g., SAR 316). The plurality of digital values stored in the SAR may represent the inductance after several cycles of driving the switch at different slew rates. In some embodiments, selecting a path within the switched driver involves selecting a path from among a plurality of paths within the switched driver based on the plurality of digital values within the SAR.

[0083] According to a particular aspect, operation 700 may further include selecting one or more parameters regarding the IC package based on at least one of the detected resistance, inductance, or capacitance of the lumped parameter model, and adjusting the operation of one or more circuit components of the IC package based on the selected one or more parameters.

[0084] Exemplary aspects In addition to the various aspects described above, certain combinations of aspects are within the scope of the present disclosure, and some of them are detailed below.

[0085] Aspect 1: An integrated circuit (IC) package comprising at least one of a resistor detector, an inductor detector, or a capacitor detector configured to detect at least one of the resistance, inductance, or capacitance of a lumped parameter model associated with at least one of a component external to the IC package, a pin coupled to the component external to the IC package, and a parasitics associated with the component, the pin, or a connection between the component and the pin.

[0086] Aspect 2: The IC package of Aspect 1, wherein at least one of the resistor detector, the inductor detector, or the capacitor detector is configured to operate in the time domain.

[0087] Aspect 3: The IC package of Aspect 1 or 2, wherein at least one of the resistor detector, the inductor detector, or the capacitor detector is configured to output a time domain drive signal and sense a time domain response signal.

[0088]

[0082] Aspect 4: Any of the previous aspects of the IC package, further comprising one or more switches coupled between the pin and at least one of a resistance detector, an inductance detector, or a capacitance detector.

[0089]

[0083] Aspect 5: Any of the previous aspects of the IC package, wherein the capacitance detector includes a current source, a switch coupled between the current source and the pin, an analog-to-digital converter (ADC), and a sample-and-hold circuit coupled between the pin and the ADC.

[0090]

[0084] Aspect 6: The IC package of Aspect 5, wherein the capacitance detector closes the switch at the start of a period for charging the capacitive element in the lumped parameter model with the current from the current source, opens the switch at the end of the period, uses the sample-and-hold circuit to sample the voltage of the pin during the period, holds the sampled voltage at the end of the period, uses the ADC to quantize the held voltage, and is configured to determine the capacitance of the capacitive element in the lumped parameter model based on the value of the current, the duration of the period, and the quantized voltage.

[0091]

[0085] Aspect 7: Any of the previous aspects of the IC package, wherein the resistance detector includes a first current source configured to supply a first current, a first switch coupled between the first current source and the pin, a second current source configured to supply a second current, the second current being different from the first current, a second switch coupled between the second current source and the pin, a first sample-and-hold circuit having an input coupled to the pin, a second sample-and-hold circuit having an input coupled to the pin, and an ADC having one or more inputs coupled to the output of the first sample-and-hold circuit and the output of the second sample-and-hold circuit.

[0092]

[0086] Aspect 8: At the start of a first period for supplying a first current to the pin, the first switch is closed; at the end of the first period, the first switch is opened. Using the first sample-and-hold circuit, during the first period, the first voltage of the pin is sampled, and at the end of the first period, the sampled first voltage is held. At the start of a second period for supplying a second current to the pin, the second switch is closed; at the end of the second period, the second switch is opened. Using the second sample-and-hold circuit, during the second period, the second voltage of the pin is sampled, and at the end of the second period, the sampled second voltage is held. Using an ADC, the voltage difference between the held first voltage and the held second voltage is quantized, and based on the value of the first current, the value of the second current, and the quantized voltage difference, the resistance of the resistance element in the lumped parameter model is determined. The IC package of Aspect 7 is configured as such.

[0093]

[0087] Aspect 9: The IC package of Aspect 8 is configured such that a first product of the value of the first current and the time duration of the first period is equal to a second product of the value of the second current and the time duration of the second period (such that the capacitance of the lumped parameter model can be ignored).

[0094]

[0088] Aspect 10: The resistance detector has a first input coupled to the output of the first sample-and-hold circuit, a second input coupled to the output of the second sample-and-hold circuit, and an output coupled to one or more inputs of the ADC. The IC package of any one of Aspects 7 to 9 further includes an amplifier.

[0095] Aspect 11: At the start of a first period for supplying a first current to the pin, the resistance detector closes the first switch, and at the end of the first period, opens the first switch. Using a first sample-and-hold circuit, during the first period, it samples the first voltage of the pin, and at the end of the first period, holds the sampled first voltage. At the start of a second period for supplying a second current to the pin, it closes the second switch, and at the end of the second period, opens the second switch. Using a second sample-and-hold circuit, during the second period, it samples the second voltage of the pin, and at the end of the second period, holds the sampled second voltage. Using an amplifier, it amplifies the voltage difference between the held first voltage and the held second voltage, and using an ADC, it quantizes the amplified voltage difference. Based on the value of the first current, the value of the second current, and the quantized voltage difference, it is configured to determine the resistance of a resistance element within a lumped parameter model, the IC package of Aspect 10.

[0096] Aspect 12: The inductance detector includes a pulse generator, a switch coupled between a power rail and the pin, and a switch driver coupled between the output of the pulse generator and the control input of the switch, the switch driver being configured to drive the switch at a plurality of different slew rates, the IC package of any of the preceding aspects.

[0097] Aspect 13: The inductance detector further includes a peak detector having an input coupled to the pin, a comparator having a first input coupled to the output of the peak detector and a second input coupled to a reference voltage node, and a successive approximation register having an input coupled to the output of the comparator, the IC package of Aspect 12.

[0098] Aspect 14: The peak detector includes an AC-coupled diode peak detector, the IC package of Aspect 13.

[0099] Aspect 15: The IC package of Aspect 13 or 14, wherein the peak detector includes a first transistor having a drain coupled to a pin, a first capacitor coupled between the drain and the gate of the first transistor, and a second capacitor coupled between the source of the first transistor and the reference potential node of the peak detector.

[0100] Aspect 16: The IC package of Aspect 15, wherein the peak detector further includes a second transistor having a drain coupled to the source of the first transistor and a source coupled to the second capacitor and the first input of the comparator, a third transistor having a source coupled to the gate of the second transistor, a current source coupled between the power rail and the drain of the third transistor, and a fourth transistor having a drain coupled to the gate of the second transistor and the source of the third transistor and a source coupled to the reference potential node of the peak detector.

[0101] Aspect 17: The IC package of Aspect 16, wherein the peak detector further includes a switch capacitor array coupled between the gate of the second transistor and the reference potential node of the peak detector.

[0102] Aspect 18: The IC package of any one of Aspects 13 to 17, wherein the switch driver includes a plurality of drive circuits selectively coupled between the output of the pulse generator and the control input of the switch.

[0103] Aspect 19: The IC package of Aspect 18, further comprising logic having an input coupled to the output of the successive approximation register and an output coupled to the control input of the switch in the switch driver, the logic being configured to control the selection of the drive circuit based on the digital value in the successive approximation register.

[0104] Aspect 20: The IC package of Aspect 18 or 19, wherein at least one of the plurality of drive circuits includes a plurality of series-connected inverters.

[0105]

[0099] Aspect 21: A method for determining parameters, comprising coupling at least one of a resistance detector, an inductance detector, or a capacitance detector inside the IC package to a pin of the IC package, wherein this pin is coupled to a component outside the IC package, and using at least one of a resistance detector, an inductance detector, or a capacitance detector inside the IC package to detect at least one of the resistance, inductance, or capacitance of a lumped parameter model regarding a component outside the IC package and regarding a parasitic associated with at least one of the component, the pin, or the connection between the component and the pin.

[0106]

[0100] Aspect 22: The method of Aspect 21, wherein detecting comprises operating at least one of a resistance detector, an inductance detector, or a capacitance detector in the time domain.

[0107]

[0101] Aspect 23: The method of Aspect 21 or 22, wherein detecting comprises generating a drive signal within the IC package, outputting the drive signal to a component via a pin of the IC package, and receiving a response signal from the component and the parasitic via a pin of the IC package.

[0108]

[0102] Aspect 24: The method of Aspect 23, wherein the drive signal is a time-domain drive signal and the response signal is a time-domain response signal.

[0109]

[0103] Aspect 25: The method according to any one of Aspects 21 to 24, wherein coupling comprises closing one or more switches coupled between the pin and at least one of a resistance detector, an inductance detector, or a capacitance detector.

[0110] Aspect 26: Detecting capacitance includes closing a switch coupled between a current source and a pin at the start of a period for charging a capacitive element in a lumped parameter model with current from the current source, opening the switch at the end of the period, sampling the voltage of the pin during the period using a sample and hold circuit, holding the sampled voltage at the end of the period using a sample and hold circuit, quantizing the held voltage using an ADC, and determining the capacitance of the capacitive element in the lumped parameter model based on the value of the current, the duration of the period, and the quantized voltage. The method is any one of Aspects 21 - 25.

[0111] Aspect 27: Detecting resistance includes closing a first switch coupled between a first current source and a pin at the start of a first period for supplying a first current to the pin, opening the first switch at the end of the first period, sampling the first voltage of the pin during the first period using a first sample and hold circuit and holding the sampled first voltage at the end of the first period, closing a second switch coupled between a second current source and the pin at the start of a second period for supplying a second current to the pin, opening the second switch at the end of the second period, sampling the second voltage of the pin during the second period using a second sample and hold circuit and holding the sampled second voltage at the end of the second period, quantizing the voltage difference between the held first voltage and the held second voltage using an ADC, and determining the resistance of the resistive element in the lumped parameter model based on the value of the first current, the value of the second current, and the quantized voltage difference. The method is any one of Aspects 21 - 26.

[0112] Aspect 28: The method of Aspect 27, wherein a first product of a value of a first current and a duration of a first period is substantially equal to a second product of a value of a second current and a duration of a second period such that the capacitance of the lumped parameter model can be ignored.

[0113] Aspect 29: The method of Aspect 27 or 28, wherein detecting a resistance further includes amplifying a voltage difference between a held first voltage and a held second voltage, and quantizing includes quantizing the amplified voltage difference.

[0114] Aspect 30: The method according to any one of Aspects 21 to 29, wherein detecting an inductance includes using a SAR-based charging scheme to charge a component via a pin over several cycles.

[0115] Aspect 31: The method according to any one of Aspects 21 to 30, wherein detecting an inductance includes generating a pulse using a pulse generator, selecting a path from a plurality of paths in a switch driver, modifying a slew rate of the pulse using the selected path in the switch driver, and driving a switch coupled between a power rail and a pin using the pulse having the modified slew rate.

[0116] Aspect 32: The method of Aspect 31, wherein detecting an inductance further includes detecting a peak of a voltage signal received from a pin, comparing the detected peak of the voltage signal with a reference voltage using a comparator, and storing a digital value output from the comparator in a successive approximation register, wherein the plurality of digital values stored in the successive approximation register represent the inductance after several cycles of driving the switch at different slew rates.

[0117] Aspect 33: The method of Aspect 32, wherein the selection includes selecting a path from a plurality of paths in a switch driver based on a plurality of digital values in a sequential comparison register.

[0118] Aspect 34: The method according to any one of Aspects 21 to 33, further comprising selecting one or more parameters regarding the IC package based on at least one of the resistance, inductance, or capacitance of the detected lumped parameter model, and adjusting the operation of one or more circuit components of the IC package based on the selected one or more parameters.

[0119] Aspect 35: An IC package, comprising pins for coupling to components external to the IC package, and means for detecting the resistance of a lumped parameter model, means for detecting inductance, or means for detecting capacitance, which is related to at least one of the components external to the IC package, and the parasitics associated with at least one of the components, pins, or connections between the components and pins.

[0120] Aspect 36: The IC package of Aspect 35, further comprising means for selectively coupling at least one of the means for detecting resistance, means for detecting inductance, or means for detecting capacitance to a pin of the IC package.

[0121] Aspect 37: The IC package of Aspect 35 or 36, wherein at least one of the means for detecting resistance, means for detecting inductance, or means for detecting capacitance is configured to output a time-domain drive signal and sense a time-domain response signal.

[0122] Additional Considerations

[0116] The various operations of the above method can be performed by any suitable means capable of performing the corresponding functions. Those means can include, but are not limited to, various hardware components and / or software components, and / or various hardware modules and / or software modules, including circuits, application-specific integrated circuits (ASICs), or processors. Generally, when operations are shown in the figures, those operations can have corresponding equivalent means-plus-function components with similar numbers.

[0123]

[0117] For example, the means for detecting a resistance can include a resistance detector such as the resistance detector 230 shown in FIGS. 2 and 5. The means for detecting an inductance can include an inductance detector such as the inductance detector 220 shown in FIGS. 2 and 3. The means for detecting a capacitance can include a capacitance detector such as the capacitance detector 240 shown in FIGS. 2 and 6. The means for selectively coupling can include one or more switches such as the switch network 215 shown in FIG. 2.

[0124]

[0118] As used herein, the term "determining" encompasses a wide variety of actions. For example, "determining" can include calculating, computing, processing, deriving, investigating, searching (e.g., searching in a table, database, or another data structure), ascertaining, etc. Also, "determining" can include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), etc. Further, "determining" can include resolving, selecting, choosing, establishing, etc.

[0125] As used herein, the phrase referring to a list of items "at least one of" refers to any combination of those items, including a single member. By way of example, "at least one of a, b, or c" includes a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination having multiple identical elements (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c, or any other arrangement of a, b, and c).

[0126]

[0120] The methods disclosed herein include one or more steps or actions for achieving the described methods. The steps and / or actions of those methods can be interchanged with each other without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order of the specific steps and / or actions, and / or the use of those steps and / or actions, can be modified without departing from the scope of the claims.

[0127]

[0121] It should be understood that the claims are not limited to the exact configurations and components illustrated above. Various modifications, changes, and variations can be made to the configurations, operations, and details of the above-described methods and apparatuses without departing from the scope of the claims.

Claims

1. An integrated circuit (IC) package, Pins for coupling to external components of the IC package, A resistance detector, an inductance detector, or a capacitance detector, each coupled to the aforementioned pin and configured to detect at least one of the resistance, inductance, or capacitance of a lumped parameter model relating to the aforementioned component outside the IC package and to a parasite associated with at least one of the aforementioned component, the aforementioned pin, or the connection between the aforementioned component and the aforementioned pin, The inductance detector is equipped with, pulse generator, A switch coupled between the power rail and the aforementioned pin, A switch driver coupled between the output of the pulse generator and the control input of the switch, configured to drive the switch at a plurality of different slew rates, The inductance detector is equipped with, A peak detector having an input coupled to the aforementioned pin, A comparator having a first input coupled to the output of the peak detector and a second input coupled to a reference voltage node, A successive comparison register having an input coupled to the output of the comparator, An IC package that further includes the following.

2. At least one of the resistance detector, the inductance detector, or the capacitance detector is configured to operate in the time domain, or At least one of the resistance detector, the inductance detector, or the capacitance detector is configured to output a time-domain drive signal and sense a time-domain response signal, or The IC package according to claim 1, further comprising one or more switches coupled between the pin and at least one of the resistance detector, the inductance detector, or the capacitance detector.

3. The capacitance detector, A current source and A switch coupled between the current source and the pin, Analog-to-digital converter (ADC), A sample-and-hold circuit coupled between the aforementioned pin and the ADC, Equipped with, The capacitance detector, At the start of the period for charging the capacitive element in the aforementioned concentrated parameter model with the current from the current source, the switch is closed. At the end of the aforementioned period, open the switch, Using the sample-and-hold circuit, the voltage of the pin is sampled during the period, and the sampled voltage is held at the end of the period. Using the ADC, the held voltage is quantized. The IC package according to claim 1, configured to determine the capacitance of the capacitive element in the lumped parameter model based on the value of the current, the duration of the period, and the quantized voltage.

4. The aforementioned resistive detector A first current source configured to supply a first current, A first switch coupled between the first current source and the pin, A second current source configured to supply a second current, wherein the second current is different from the first current, A second switch coupled between the second current source and the pin, A first sample-and-hold circuit having an input connected to the aforementioned pin, A second sample-and-hold circuit having an input connected to the aforementioned pin, The IC package according to claim 1, comprising: an analog-to-digital converter (ADC) having one or more inputs coupled to the output of the first sample-and-hold circuit and the output of the second sample-and-hold circuit.

5. The aforementioned resistive detector At the start of the first period for supplying the first current to the pin, the first switch is closed. At the end of the first period, the first switch is opened. Using the first sample-and-hold circuit, a first voltage of the pin is sampled during the first period, and the sampled first voltage is held at the end of the first period. At the start of the second period for supplying the second current to the pin, the second switch is closed. At the end of the second period, the second switch is opened. Using the second sample-and-hold circuit, a second voltage of the pin is sampled during the second period, and the sampled second voltage is held at the end of the second period. Using the ADC, the voltage difference between the held first voltage and the held second voltage is quantized. The system is configured to determine the resistance of the resistive element in the lumped parameter model based on the value of the first current, the value of the second current, and the quantized voltage difference. The IC package according to claim 4, configured such that the first product of the value of the first current and the time length of the first period is equal to the second product of the value of the second current and the time length of the second period.

6. The resistance detector further comprises an amplifier having a first input coupled to the output of the first sample-and-hold circuit, a second input coupled to the output of the second sample-and-hold circuit, and an output coupled to one or more inputs of the ADC. The aforementioned resistive detector At the start of the first period for supplying the first current to the pin, the first switch is closed. At the end of the first period, the first switch is opened. Using the first sample-and-hold circuit, a first voltage of the pin is sampled during the first period, and the sampled first voltage is held at the end of the first period. At the start of the second period for supplying the second current to the pin, the second switch is closed. At the end of the second period, the second switch is opened. Using the second sample-and-hold circuit, during the second period, the second voltage of the pin is sampled, and at the end of the second period, the sampled second voltage is held. Using the amplifier, the voltage difference between the held first voltage and the held second voltage is amplified. Using the ADC, the amplified voltage difference is quantized. The IC package according to claim 4, configured to determine the resistance of a resistive element in the lumped parameter model based on the value of the first current, the value of the second current, and the quantized voltage difference.

7. The peak detector includes an AC-coupled diode peak detector, or The aforementioned peak detector A first transistor having a drain connected to the aforementioned pin, A first capacitor coupled between the drain and gate of the first transistor, A second capacitor is coupled between the source of the first transistor and the reference potential node of the peak detector, The peak detector is equipped with A second transistor having a drain coupled to the source of the first transistor and a source coupled to the second capacitor and the first input of the comparator, A third transistor having a source coupled to the gate of the second transistor, A current source coupled between the power rail and the drain of the third transistor, A fourth transistor having a drain coupled to the gate of the second transistor and the source of the third transistor, and a source coupled to the reference potential node of the peak detector, The IC package according to claim 1, further comprising a switched capacitor array in which the peak detector is coupled between the gate of the second transistor and the reference potential node of the peak detector.

8. The switch driver comprises a plurality of drive circuits that are selectively coupled between the output of the pulse generator and the control input of the switch, The logic further comprises having an input coupled to the output of the successive approximation register and an output coupled to the control input of a switch in the switch driver, wherein the logic is configured to control the selection of the drive circuit based on the digital value in the successive approximation register, or The IC package according to claim 1, wherein at least one of the plurality of drive circuits includes a plurality of series-connected inverters.

9. A method for determining parameters, The method involves coupling at least one of a resistance detector, inductance detector, or capacitance detector inside an integrated circuit (IC) package to a pin of the IC package, wherein the pin is coupled to an external component of the IC package. Using at least one of the resistance detector, inductance detector, or capacitance detector located inside the IC package, the resistance, inductance, or capacitance of a lumped parameter model relating to the component located outside the IC package, and to a parasite associated with at least one of the component, the pin, or the connection between the component and the pin, respectively. Including the detection of the inductance, Generating pulses using a pulse generator, Selecting a path from among multiple paths within the switch driver, Using the selected path within the switch driver, the slew rate of the pulse is modified. Using the pulse having the modified slew rate, a switch coupled between the power rail and the pin is driven. Including the detection of the inductance, To detect the peak of the voltage signal received from the aforementioned pin, Using a comparator, the peak of the detected voltage signal is compared with a reference voltage, The digital value output from the comparator is stored in a successive comparison register, wherein the multiple digital values ​​stored in the successive comparison register represent the inductance after several cycles of driving the switch at different slew rates. Methods that further include the above.

10. The detection includes operating at least one of the resistance detector, the inductance detector, or the capacitance detector in the time domain, or The above detection is The IC package generates a drive signal, The drive signal is output to the component via the pins of the IC package, The IC package receives response signals from the components and the parasites via the pins of the IC package, The method according to claim 9, wherein the drive signal is a time-domain drive signal and the response signal is a time-domain response signal.

11. The method according to claim 9, wherein the coupling includes closing one or more switches coupled between the pin and at least one of the resistance detector, the inductance detector, or the capacitance detector.

12. Detecting the capacitance is At the start of the period for charging the capacitive element in the aforementioned lumped parameter model with current from the current source, the switch coupled between the current source and the pin is closed. At the end of the aforementioned period, the switch is opened, Using a sample-and-hold circuit, the voltage of the pin is sampled during the aforementioned period, Using the sample-and-hold circuit, the sampled voltage is held at the end of the period, The held voltage is quantized using an analog-to-digital converter (ADC), The method according to claim 9, comprising determining the capacitance of the capacitive element in the lumped parameter model based on the value of the current, the duration of the period, and the quantized voltage.

13. Detecting the aforementioned resistance At the start of a first period for supplying a first current from the first current source to the pin, a first switch coupled between the first current source and the pin is closed. At the end of the first period, the first switch is opened, Using a first sample-and-hold circuit, a first voltage of the pin is sampled during the first period, and the sampled first voltage is held at the end of the first period. Closing a second switch coupled between the second current source and the pin at the start of a second period for supplying a second current from the second current source to the pin, At the end of the second period, the second switch is opened, A second sample-and-hold circuit is used to sample the second voltage of the pin during the second period, and to hold the sampled second voltage at the end of the second period. Using an analog-to-digital converter (ADC), the voltage difference between the held first voltage and the held second voltage is quantized, The resistance of the resistive element in the lumped parameter model is determined based on the value of the first current, the value of the second current, and the quantized voltage difference. The first product of the value of the first current and the time length of the first period is substantially equal to the second product of the value of the second current and the time length of the second period, such that the capacitance of the lumped parameter model becomes negligible, or The method according to claim 9, wherein detecting the resistance further includes amplifying the voltage difference between the held first voltage and the held second voltage, and quantizing includes quantizing the amplified voltage difference.

14. Detecting the inductance involves using a successive approximation register (SAR)-based charging scheme to charge the component via the pin over several cycles, or The method according to claim 9, wherein the selection includes selecting the path from among the plurality of paths in the switch driver based on the plurality of digital values ​​in the successive comparison register.

15. Selecting one or more parameters relating to the IC package based on at least one of the resistance, inductance, or capacitance of the detected lumped parameter model, Adjusting the operation of one or more circuit components of the IC package based on the selected one or more parameters, The method according to claim 9, further comprising:

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