Method, apparatus, and electronic device for generating hardware interface signals

Abstract

This application discloses a method, apparatus, and electronic device for generating a hardware interface signal. Here, the method includes: obtaining a request instruction by a first system; determining a plurality of logical bit information corresponding to the request instruction; and generating a hardware interface signal corresponding to the request instruction based on the plurality of logical bit information and a timer. This application solves the technical problem that the design cost of a chip is high because in the prior art, it is necessary for the chip itself to have the hardware logic design of a controller.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and more specifically, to a method, apparatus, and electronic device for generating a hardware interface signal.

Background Art

[0002] Currently, in the prior art, in order for a chip to communicate with an external device using a hardware interface signal, it is necessary for the chip itself to have the hardware logic design of a related controller, where the related controller is used to specifically process the hardware interface signal. However, the introduction of the related controller increases the design cost and manufacturing cost of the chip. Therefore, it has become urgent to seek new solutions to reduce the design complexity of the chip and the manufacturing cost of the chip.

Summary of the Invention

Problems to be Solved by the Invention

[0003] This application provides a method, apparatus, and electronic device for generating a hardware interface signal.

Means for Solving the Problems

[0004] According to one aspect of this application, a method for generating a hardware interface signal is provided, including steps of obtaining a request instruction by a first system, determining a plurality of logical bit information corresponding to the request instruction, and generating a hardware interface signal corresponding to the request instruction based on the plurality of logical bit information and a timer. In one embodiment of this application, the method for generating a hardware interface signal further includes steps of determining a reload value and a first match value corresponding to the timer based on the plurality of logical bit information, and generating a hardware interface signal corresponding to the request instruction based on the reload value and the first match value.

[0005] In one embodiment of the present application, the method for generating a hardware interface signal further includes: obtaining an operation time corresponding to each piece of logical bit information; determining a reload value based on the operation time; determining a first match value corresponding to a timer based on the logical bit of each piece of logical bit information, and obtaining a plurality of first match values corresponding to the timer, wherein the first match value corresponding to each piece of logical bit information is used to control the logical bit of the logical bit information to 0 or 1 by controlling the time when the logical bit information is at a high level.

[0006] In one embodiment of the present application, the method for generating a hardware interface signal further includes: sequentially generating a hardware interface sub-signal corresponding to each piece of logical bit information based on the reload value and the first match value corresponding to each piece of logical bit information according to the order before and after among a plurality of pieces of logical bit information corresponding to a request instruction, and obtaining a hardware interface signal.

[0007] In one embodiment of the present application, the method for generating a hardware interface signal includes: performing a decrement operation on the reload value corresponding to each piece of logical bit information based on a timer; outputting, by a first system, a first signal corresponding to the logical bit information before the reload value corresponding to each piece of logical bit information is decremented to the first match value corresponding to the logical bit information, where the first signal is a high-level signal; and after the reload value corresponding to each piece of logical bit information is decremented to the first match value corresponding to the logical bit information, outputting, by the first system, a second signal corresponding to the logical bit information. Second signala step of being a low-level signal, and when the reload value corresponding to each logical bit information is decremented to 0, determining the generation of a hardware interface sub-signal corresponding to the logical bit information, and obtaining a hardware interface sub-signal corresponding to each logical bit information, wherein the hardware interface sub-signal corresponding to each logical bit information is composed of a first signal and a second signal corresponding to the logical bit information; and further includes.

[0008] In one embodiment of the present application, the method for generating a hardware interface signal includes: when the reload value corresponding to each logical bit information is decremented to the initial match value corresponding to the logical bit information, triggering a first interrupt corresponding to the logical bit information; and when the reload value corresponding to each logical bit information is decremented to 0, triggering a second interrupt corresponding to the logical bit information; and further includes.

[0009] In one embodiment of the present application, the method for generating a hardware interface signal includes: in the process of sequentially generating a hardware interface sub-signal corresponding to each logical bit information based on the reload value and the initial match value corresponding to each logical bit information, each time a first interrupt or a second interrupt is triggered, performing an interrupt count once; and determining a field in which the current signal conversion process in the request instruction is being performed based on the interrupt count, wherein the signal conversion process is used to generate a hardware interface sub-signal corresponding to the logical bit information corresponding to each field in the request instruction; and further includes.

[0010] In one embodiment of the present application, the method for generating a hardware interface signal further includes: obtaining the number of bytes corresponding to each field in the request instruction; determining the number of logical bit information corresponding to the request instruction based on the number of bytes, where each byte corresponding to the request instruction corresponds to one piece of logical bit information; determining the number of interrupts corresponding to the request instruction based on the number of logical bit information, where the number of interrupts corresponding to the request instruction is twice the number of logical bit information; and determining the field in the request instruction where the current signal conversion process is being performed based on the number of interrupts and the interrupt count.

[0011] In one embodiment of the present application, the method for generating a hardware interface signal further includes: determining the logical bit information that is currently being converted into a hardware interface sub-signal based on the number of interrupts and the interrupt count; determining the byte corresponding to the logical bit information that is currently being converted into a hardware interface sub-signal as the target byte; and determining the field corresponding to the target byte as the field in the request instruction where the current signal conversion process is being performed.

[0012] In one embodiment of the present application, the data structure of the request data corresponding to the request instruction is the first data structure, where the first data structure includes at least a device address, a write length, a read length, an instruction code, and request parameters. The device address is used to characterize the address of the target device, and the target device is a device that generates response data based on the hardware interface signal. The instruction code is used to distinguish different request instructions. The write length is used to characterize the number of bytes from the instruction code to the request data. The read length is used to characterize the number of bytes including the completion code and the read data in the request data. The request parameters are used to characterize the parameters of the request instruction.

[0013] In one embodiment of the present application, the method for generating a hardware interface signal includes, when a first request triggered by a second system is detected by a first system, the step of obtaining request data, where the first system and the second system operate on the same processor, the request data is generated by the second system, and the service response speed of the second system is slower than that of the first system, and further includes the step of analyzing the request data to obtain a request instruction.

[0014] In one embodiment of the present application, the method for generating a hardware interface signal includes, before obtaining the request data, the step of storing the request data in a target memory by the second system, and after the storage of the request data is completed, the step of triggering a first request by the second system, where the first request is used to notify the first system to read the request data from the target memory, and the target memory is a memory accessible by both the first system and the second system.

[0015] In one embodiment of the present application, the method for generating a hardware interface signal further includes, after generating a hardware interface signal corresponding to the request instruction based on logical bit information and a timer, the step of converting the voltage of the hardware interface signal to obtain a target hardware interface signal. In one embodiment of the present application, the method for generating a hardware interface signal further includes the step of inputting the hardware interface signal into a voltage conversion device and obtaining the target hardware interface signal output from the voltage conversion device.

[0016] In one embodiment of the present application, the method for generating a hardware interface signal includes generating a hardware interface signal corresponding to a request command based on logical bit information and a timer, and then receiving, by a first system, response data corresponding to the hardware interface signal, where the transmission format of the response data is the same as that of the hardware interface signal, and further includes adjusting the data structure of the response data to a second data structure.

[0017] In one embodiment of the present application, the second data structure includes at least a first calibration value, a second calibration value, and response valid data. Here, the first calibration value is used to characterize the calibration value in the request data, the second calibration value is used to characterize the calibration value in the response data, and the response valid data is used to characterize the completion code in the response data and data for explaining the state of the target device. The target device is a device that generates response data based on the hardware interface signal.

[0018] In one embodiment of the present application, the method for generating a hardware interface signal further includes, after adjusting the data structure of the response data to the second data structure, triggering a second request by the first system, where the second request is used to notify the second system to read the response data. In one embodiment of the present application, the hardware interface signal is any one of a PECI signal, an HDMI (registered trademark) signal, an SGMII signal, an RGMII signal, a GPIO signal, and an SPI signal.

[0019] According to another aspect of the embodiment of the present application, there is provided a generating device for a hardware interface signal, including an acquisition module used by the first system to acquire a request command, a determination module used to determine a plurality of logical bit information corresponding to the request command, and a generation module used to generate a hardware interface signal corresponding to the request command based on the plurality of logical bit information and a timer.

[0020] In one embodiment of the present application, the generation module includes a first determination unit and a second generation unit. Here, the first determination unit is used to determine the reload value and the first match value corresponding to the timer based on a plurality of logical bit information, and the second generation unit is used to generate the hardware interface signal corresponding to the request instruction based on the reload value and the first match value.

[0021] In one embodiment of the present application, the first determination unit further includes a first acquisition subunit, a first determination subunit, and a second determination subunit. Here, the first acquisition subunit is used to acquire the operation time corresponding to each logical bit information, the first determination subunit is used to determine the reload value based on the operation time, and the second determination subunit is used to determine one first match value corresponding to the timer based on the logical bit of each logical bit information, and is used to obtain a plurality of first match values corresponding to the timer. Here, the first match value corresponding to each logical bit information is used to control the logical bit of the logical bit information to 0 or 1 by controlling the time when the logical bit information is at a high level.

[0022] In one embodiment of the present application, the second generation unit further includes a first generation subunit that sequentially generates the hardware interface sub-signals corresponding to each logical bit information based on the reload value and the first match value corresponding to each logical bit information according to the order before and after among the plurality of logical bit information corresponding to the request instruction, and is used to obtain the hardware interface signal.

[0023] In one embodiment of the present application, the first generation subunit further includes a decrement submodule, a first signal output submodule, a second signal output submodule, and a first determination submodule. Here, the decrement submodule is used to perform a decrement operation on the reload value corresponding to each logical bit information based on a timer. The first signal output submodule is used to output a first signal corresponding to the logical bit information by the first system before the reload value corresponding to each logical bit information is decremented to the initial match value corresponding to the logical bit information. Here, the first signal is a high-level signal. The second signal output submodule is used to output a second signal corresponding to the logical bit information by the first system after the reload value corresponding to each logical bit information is decremented to the initial match value corresponding to the logical bit information. Here, Second signal is a low-level signal. The first determination submodule determines the generation of the hardware interface sub-signal corresponding to the logical bit information when the reload value corresponding to each logical bit information is decremented to 0, and is used to obtain the hardware interface sub-signal corresponding to each logical bit information. Here, the hardware interface sub-signal corresponding to each logical bit information is composed of the first signal and the second signal corresponding to the logical bit information.

[0024] In one embodiment of the present application, the generation device of the hardware interface signal further includes a first interrupt trigger module and a second interrupt trigger module. Here, the first interrupt trigger module is used to trigger a first interrupt corresponding to the logical bit information when the reload value corresponding to each logical bit information is decremented to the initial match value corresponding to the logical bit information. The second interrupt trigger module is used to trigger a second interrupt corresponding to the logical bit information when the reload value corresponding to each logical bit information is decremented to 0.

[0025] In one embodiment of the present application, the apparatus for generating a hardware interface signal further includes an interrupt counting module and a field determination module. Here, each time the interrupt counting module triggers a first interrupt or a second interrupt, it is used to perform an interrupt count once, and the field determination module is used to determine the field in which the current signal conversion process in the request instruction is being performed based on the interrupt count. Here, the signal conversion process is used to generate a hardware interface sub-signal corresponding to the logical bit information corresponding to each field in the request instruction.

[0026] In one embodiment of the present application, the field determination module further includes a second acquisition unit, a second determination unit, a third determination unit, and a fourth determination unit. Here, the second acquisition unit is used to acquire the number of bytes corresponding to each field in the request instruction, the second determination unit is used to determine the number of logical bit information corresponding to the request instruction based on the number of bytes. Here, each byte corresponding to the request instruction corresponds to one piece of logical bit information. The third determination unit is used to determine the number of interrupts corresponding to the request instruction based on the number of logical bit information. Here, the number of interrupts corresponding to the request instruction is twice the number of logical bit information. The fourth determination unit is used to determine the field in which the current signal conversion process in the request instruction is being performed based on the number of interrupts and the interrupt count.

[0027] In one embodiment of the present application, the fourth determination unit further includes a third determination sub-unit, a fourth determination sub-unit, and a fifth determination sub-unit. Here, the third determination sub-unit is used to determine the logical bit information that is currently being converted into a hardware interface sub-signal based on the number of interrupts and the interrupt count. The fourth determination sub-unit is used to determine the byte corresponding to the logical bit information that is currently being converted into a hardware interface sub-signal as the target byte. The fifth determination sub-unit is used to determine the field corresponding to the target byte as the field in which the current signal conversion process in the request instruction is being performed.

[0028] In one embodiment of the present application, the acquisition module further includes a request data acquisition unit and a request data analysis unit. Here, the request data acquisition unit is used to acquire request data when the first request triggered by the second system is detected by the first system. Here, the first system and the second system operate on the same processor, the request data is generated by the second system, the service response speed of the second system is smaller than that of the first system, and the request data analysis unit analyzes the request data and is used to obtain a request instruction.

[0029] In one embodiment of the present application, the device for generating a hardware interface signal is a request data storage module used to store request data in a target memory by the second system and trigger the first request by the second system after the storage of the request data is completed. The first request is used to notify the first system to read the request data from the target memory, and the target memory further includes a request data storage module that is a memory accessible by both the first system and the second system.

[0030] In one embodiment of the present application, the device for generating a hardware interface signal further includes a voltage conversion module used to convert the voltage of the hardware interface signal to obtain a target hardware interface signal. In one embodiment of the present application, the device for generating a hardware interface signal further includes a signal input unit used to input the hardware interface signal into a voltage conversion device and obtain the target hardware interface signal output from the voltage conversion device.

[0031] In one embodiment of the present application, the apparatus for generating a hardware interface signal further includes a response data receiving module and a data structure adjusting module. Here, the response data receiving module is used to receive response data corresponding to the hardware interface signal by a first system. Here, the transmission format of the response data is the same as that of the hardware interface signal. The data structure adjusting module is used to adjust the data structure of the response data to a second data structure.

[0032] In one embodiment of the present application, the apparatus for generating a hardware interface signal is a second request triggering module used to trigger a second request by a first system, and the second request is used to notify a second system to read response data. The apparatus for generating a hardware interface signal further includes a second request triggering module.

[0033] To achieve the above object, according to another embodiment of the present disclosure, there is further provided a computer-readable storage medium storing a computer program, where the computer program is configured to execute the steps in any of the embodiments of the above method during operation.

[0034] To achieve the above object, according to another embodiment of the present disclosure, there is further provided an electronic device including a storage storing a computer program and a processor configured to execute the steps in any of the above method embodiments when executing the computer program. To achieve the above object, according to another aspect of the present application, there is further provided an embedded system including a first system and a processor, where the first system operates on the processor. The first system acquires a request instruction, determines a plurality of logical bit information corresponding to the request instruction, and is used to generate a hardware interface signal corresponding to the request instruction based on the plurality of logical bit information and a timer.

[0035] In one embodiment of the present application, the first system is used to determine a reload value and an initial match value corresponding to a timer based on a plurality of logical bit information, and the second system is used to generate a hardware interface signal corresponding to a request instruction based on the reload value and the initial match value. In one embodiment of the present application, the first system is used to obtain an operation time corresponding to each logical bit information, the first system is used to determine a reload value based on the operation time, the first system determines one initial match value corresponding to the timer based on the logical bits of each logical bit information, and is used to obtain a plurality of initial match values corresponding to the timer, where the initial match value corresponding to each logical bit information is used to control the logical bit of the logical bit information to 0 or 1 by controlling the time when the logical bit information is at a high level.

[0036] In one embodiment of the present application, the first system sequentially generates a hardware interface sub-signal corresponding to each logical bit information based on the reload value and the initial match value corresponding to each logical bit information according to the order before and after among the plurality of logical bit information corresponding to the request instruction, and is used to obtain a hardware interface signal.

[0037] In one embodiment of the present application, the first system is used to perform a decrement operation on the reload value corresponding to each logical bit information based on a timer. Before the reload value corresponding to each logical bit information is decremented to the initial match value corresponding to the logical bit information, the first system is used to output a first signal corresponding to the logical bit information by the first system. Here, the first signal is a high-level signal. After the reload value corresponding to each logical bit information is decremented to the initial match value corresponding to the logical bit information, the first system is used to output a second signal corresponding to the logical bit information by the first system. The second signal is a low-level signal. When the reload value corresponding to each logical bit information is decremented to 0, the first system determines the generation of the hardware interface sub-signal corresponding to the logical bit information and is used to obtain the hardware interface sub-signal corresponding to each logical bit information. Here, the hardware interface sub-signal corresponding to each logical bit information is composed of the first signal and the second signal corresponding to the logical bit information.

[0038] In one embodiment of the present application, when the reload value corresponding to each logical bit information is decremented to the initial match value corresponding to the logical bit information, the first system is used to trigger a first interrupt corresponding to the logical bit information. When the reload value corresponding to each logical bit information is decremented to 0, the first system is used to trigger a second interrupt corresponding to the logical bit information.

[0039] In one embodiment of the present application, each time the first system triggers one of the first interrupt or the second interrupt, it is used to perform an interrupt count once. The first system is used to determine the field in which the current signal conversion process in the request command is being performed based on the interrupt count. Here, the signal conversion process is used to generate the hardware interface sub-signal corresponding to the logical bit information corresponding to each field in the request command.

[0040] In one embodiment of the present application, the first system is used to obtain the number of bytes corresponding to each field in the request command, the first system is used to determine the number of logical bit information corresponding to the request command based on the number of bytes, where each byte corresponding to the request command corresponds to one piece of logical bit information, the first system is used to determine the number of interrupts corresponding to the request command based on the number of logical bit information, where the number of interrupts corresponding to the request command is twice the number of logical bit information, and the first system is used to determine the field in the request command where the current signal conversion process is being performed based on the number of interrupts and the interrupt count.

[0041] In one embodiment of the present application, the first system is used to determine the logical bit information that is currently being converted into the hardware interface sub-signal based on the number of interrupts and the interrupt count, the first system is used to determine the byte corresponding to the logical bit information that is currently being converted into the hardware interface sub-signal as the target byte, and the first system is used to determine the field corresponding to the target byte as the field in the request command where the current signal conversion process is being performed.

[0042] In one embodiment of the present application, the embedded system further includes a second system, where both the second system and the first system operate on a processor, the second system is used to generate request data, and the first system is used to obtain the request data when detecting the first request triggered by the second system, where the service response speed of the second system is smaller than that of the first system, and the first system is used to analyze the request data to obtain the request command.

[0043] In one embodiment of the present application, the second system stores the request data in the target memory and, after the storage of the request data is completed, is used to trigger a first request, where the first request is used to notify the first system to read the request data from the target memory, and the target memory is a memory accessible by both the first system and the second system.

[0044] In one embodiment of the present application, the first system is used to convert the voltage of the hardware interface signal to obtain a target hardware interface signal. In one embodiment of the present application, the first system inputs the hardware interface signal into a voltage conversion device and is used to obtain the target hardware interface signal output from the voltage conversion device.

[0045] In one embodiment of the present application, the first system is used to receive response data corresponding to the hardware interface signal, where the transmission format of the response data is the same as the transmission format of the hardware interface signal, and the first system is used to adjust the data structure of the response data to a second data structure. In one embodiment of the present application, the first system is used to trigger a second request, where the second request is used to notify the second system to read the response data.

[0046] According to another aspect of the present application, there is further provided a chip including at least one of a programmable logic circuit and executable instructions, which operates in an electronic device and is used to execute the steps in any of the embodiments of the above method. According to another aspect of the present application, there is further provided a BMC chip including a storage unit and a processing unit connected to the storage unit, where the storage unit is used to store a program, and the processing unit is used to execute the program to execute the steps in any of the embodiments of the above method.

[0047] According to another aspect of the present application, there is provided a motherboard including at least one processor and at least one storage used for storing at least one program, wherein when the at least one program is executed by the at least one processor, the at least one processor is caused to execute the steps in any of the embodiments of the above method.

[0048] According to another aspect of the present application, there is provided a server including a processor, a communication interface, a storage, and a communication bus, wherein the processor, the communication interface, and the storage realize communication with each other via the communication bus, the storage is used for storing a computer program, and when the processor executes the program stored in the storage, the server is used for realizing the steps in any of the embodiments of the above method.

Advantages of the Invention

[0049] In this application, a method is adopted in which a first system generates a hardware interface signal corresponding to a request instruction. First, the first system acquires the request instruction. Subsequently, a plurality of logical bit information corresponding to the request instruction is determined. Finally, a hardware interface signal corresponding to the request instruction is generated based on the plurality of logical bit information and a timer. As can be seen from the above, this application generates a hardware interface signal corresponding to a request instruction by means of a first system, thereby realizing the technical effect of analogously generating a hardware interface signal using a software method. Furthermore, the chip itself does not need to have a hardware logic design for the relevant hardware interface signal, achieving the purpose of not only reducing the design complexity of the chip but also further reducing the design cost of the chip. This application achieves the purpose of generating a hardware interface signal using a software system without the need to perform a hardware logic design for the hardware interface signal on the chip, thereby reducing the design complexity of the chip. Moreover, it solves the technical problem that the design cost of the chip is high because in the prior art, the chip itself needs to have a hardware logic design for the controller.

Brief Description of the Drawings

[0050] The drawings described herein are provided to further understand this application, form a part of this application, and the exemplary embodiments and their descriptions of this application are used to interpret this application and do not unduly limit this application.

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Embodiments for Carrying Out the Invention

[0051] The following clearly and completely describes the technical solution in the embodiments of the present application with reference to the drawings in the embodiments of the present application so that those skilled in the art can better understand the solution means of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments that can be obtained by those skilled in the art without creative efforts should belong to the scope protected by the present application.

[0052] Note that terms such as "first" and "second" in the specification, claims and the above drawings of the present application are used to distinguish similar objects and are not for explaining a specific order or sequence. It should be understood that such data can be mutually exchanged when appropriate so that the embodiments of the present application described in this specification can be implemented in an order other than the order illustrated or described in this specification. Furthermore, the terms "include" and "have", and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not necessarily limited to the clearly listed steps or units, and may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0053] Note that the user information related to the present application (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, electronic medical records, etc.) are all information and data permitted by the user or fully permitted by each party. When collecting, using and processing related data, relevant laws, regulations and standards of relevant countries and regions should be complied with, and it is necessary to provide corresponding operation entrances to allow the user to select permission or rejection.

[0054] According to the embodiments of the present application, a method for generating a hardware interface signal is provided. The steps shown in the flowchart of the drawings can be executed, for example, in a computer system of a group of computer-executable instructions. Although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that in this specification.

[0055] Embodiments of the method provided in the present application can be executed on a mobile terminal, a computer terminal, or a similar computing device. FIG. 1 shows a block diagram of the hardware structure of a computer terminal (or mobile device) for implementing the method for generating a hardware interface signal. As shown in FIG. 1, the computer terminal (or mobile device) 10 may include a processor 102 (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA, and the processor 102 may also include a set of processors shown as 102a, 102b,..., 102n in FIG. 1), a storage 104 used for storing data, and a transmission module 106 used for communication functions. In addition, it may further include a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of the BUS bus), a network interface, a power supply, and / or a camera. As can be understood by those skilled in the art, the structure shown in FIG. 1 is merely exemplary and does not limit the structure of the above electronic device. For example, the computer terminal 10 may include more or fewer components than those shown in FIG. 1, or may have an arrangement different from that shown in FIG. 1.

[0056] Note that in this specification, the one or more processors 102 and / or other data processing circuits described above may generally be referred to as "data processing circuits". All or part of the data processing circuits may be embodied as software, hardware, firmware, or any other combination. Also, the data processing circuits may be a single independent processing module, or all or part of them may be incorporated into any of the other elements in the computer terminal 10 (or mobile device).

[0057] The storage 104 includes, for example, a program instruction / data storage device corresponding to the method for generating a hardware interface signal in the embodiments of the present application, and can be used to store software programs and modules of application software. The processor 102 can execute the software programs and modules stored in the storage 104 to execute various functional applications and data processing, that is, to implement the method for generating the hardware interface signal. The storage 104 may include a high-speed random access memory, and may further include non-volatile memory such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some embodiments, the storage 104 may further include storage remotely installed with respect to the processor 102, and these remote storages can be connected to the computer terminal 10 via a network. Examples of the above network include, but are not limited to, the Internet, enterprise intranets, local area networks, mobile communication networks, and combinations thereof.

[0058] The transmission device 106 is used to receive or transmit data via a network. Specific examples of the above network may include a wireless network provided by a communication carrier of the computer terminal 10. In one example, the transmission device 106 includes one network adapter (Network Interface Controller, NIC) that can communicate with the Internet by connecting to other network devices via a base station. In one example, the transmission device 106 may be a radio frequency (RF) module for communicating with the Internet in a wireless manner.

[0059] The display may be, for example, a touch screen type liquid crystal display (LCD), and the liquid crystal display enables a user to interact with the user interface of the computer terminal 10 (or mobile device). In the above operating environment, the present application provides a method for generating a hardware interface signal as shown in FIG. 2. As shown in FIG. 2, the method includes the following steps S201 to S203.

[0060] In step S201, a request command is obtained by a first system. In step S201, the first system may be, for example, an RTOS (Real-time system) system, which may be a software system arranged on a chip. The request command may be a command for generating a hardware interface signal. For example, if the hardware interface signal is a PECI (platform environment control interface) signal, the request command is a PECI request command based on the PECI protocol.

[0061] In addition, the above chip may be a BMC (baseboard management controller, a server platform management control chip that can realize functions such as health status monitoring of the server, remote on / off, temperature (voltage) collection, and fault diagnosis), or may be other types of chips. The present application does not particularly limit the type of the chip.

[0062] Optionally, the hardware interface signal may be, for example, an HDMI (high definition multimedia interface) signal, an RGMII (reduced gigabit media independent interface) signal, an SGMII (serial gigabit media independent interface) signal, a GPIO (general-purpose input / output) signal, and an SPI (serial peripheral interface) signal, etc., or may be a hardware interface signal of other protocol types. In addition, the request command may be a request command of other protocol types. For example, when the hardware interface signal is a GPIO signal, the request command is a GPIO request command. The present application does not particularly limit the specific types of the request command and the hardware interface signal.

[0063] Also, it should be noted that in addition to the RTOS system, the first system may be, for example, a Linux (registered trademark) system or other software systems developed for self-driving vehicles, or may be other software systems. The present application only needs to ensure that the first system can continuously generate and output the hardware interface signal. In step S202, determine a plurality of logical bit information corresponding to the request command.

[0064] In step S202, after the first system obtains a request command, it can analyze and obtain a plurality of logical bit information corresponding to the request command. Here, there is a sequential order among the plurality of logical bit information, and the first system can generate a waveform signal (i.e., a hardware interface signal) corresponding to the request command based on the plurality of logical bit information corresponding to the request command, thereby transmitting the information included in the request command to other devices through the hardware interface signal.

[0065] Optionally, the request command includes at least one field, and each field can be represented by a logical bit 0 or 1. In addition, the corresponding conversion relationship between each field and the logical bit 1 or 0 is the logical bit information corresponding to the field. When the request command corresponds to a plurality of fields, the request command corresponds to a plurality of logical bit information. Also, each logical bit can be represented by combining a high-level signal and a low-level signal. For example, for logical bit 0, it can be represented by a combination of a high-level signal with a first preset time length and a low-level signal with a second preset time length. For logical bit 1, it can be represented by a combination of a high-level signal with a second preset time length and a low-level signal with a first preset time length. Here, the first preset time length and the second preset time length are different. In addition, since each logical bit includes both a high-level signal and a low-level signal, actually, each logical bit is represented by a section of waveform signal (the conversion between the high-level signal and the low-level signal forms one waveform). The request command corresponds to a plurality of logical bit information, that is, corresponds to a plurality of logical bits. Therefore, the hardware interface signal corresponding to the request command is one waveform signal obtained by combining the waveform signals corresponding to each logical bit information.

[0066] In step S203, a hardware interface signal corresponding to the request command is generated based on the plurality of logical bit information and a timer. Optionally, the timer in step S203 may be a timing program in the first system, or the timer may be a register in the chip where the first system is located. Here, the timer can provide at least a timing function and a counting function. The present application uses the timing function and the counting function of the timer to generate a hardware interface signal corresponding to the request command according to a plurality of logical bit information.

[0067] It should be noted that taking the example that the chip is a BMC chip and the hardware interface signal is a PECI signal, in the prior art, in order to realize the communication between the BMC chip and devices such as a CPU (central processing unit), the prior art requires that the BMC chip itself has the hardware logic design of a PECI controller, which causes the problem of high design cost of the BMC chip. In other words, in the prior art, in order to generate a PECI signal on the BMC chip, the hardware logic design of the PECI controller must be realized in advance on the BMC chip. However, in the present application, only the first system can generate a PECI signal on the BMC chip, and it is not necessary to realize the hardware logic design of the PECI controller on the BMC chip, thereby reducing the design difficulty and design cost of the BMC chip.

[0068] As can be seen from the content of steps S201 to S203, in the present application, a method of generating a hardware interface signal corresponding to a request command by the first system is adopted. First, the first system obtains the request command, then determines a plurality of logical bit information corresponding to the request command, and finally generates a hardware interface signal corresponding to the request command based on the plurality of logical bit information and the timer.

[0069] As can be seen from the above content, the present application generates a hardware interface signal corresponding to a request command by means of a first system, thereby realizing the technical effect of analogously generating a hardware interface signal using a software method. Furthermore, the present application achieves the objective that the chip itself does not need to have a hardware logic design of the relevant hardware interface signal, which can not only reduce the design complexity of the chip, but also further reduce the design cost of the chip.

[0070] Thereby, the present application achieves the objective of generating a hardware interface signal using a software system without the need to perform a hardware logic design of the hardware interface signal for the chip, thereby reducing the design complexity of the chip. Furthermore, in the prior art, since the chip itself needs to have a hardware logic design of a controller, the technical problem of high design cost of the chip is solved.

[0071] In an alternative embodiment, in order to generate a hardware interface signal corresponding to a request command based on a plurality of logical bit information and a timer, the first system first determines a reload value and an initial match value corresponding to the timer based on the plurality of logical bit information, and then generates a hardware interface signal corresponding to the request command based on the reload value and the initial match value.

[0072] Optionally, the reload value may be understood as the count period of the timer. For example, assuming that the reload value is 100 ms, the timer restarts counting every 100 ms of counting. The initial match value is used to control the logical bits corresponding to each logical bit information to be 0 or 1. Optionally, in the process of determining the reload value and the first match value corresponding to the timer based on a plurality of logical bit information, the first system first obtains the operation time corresponding to each logical bit information, and then determines the reload value based on the operation time. In addition, the first system determines one first match value corresponding to the timer based on the logical bits of each logical bit information, and obtains a plurality of first match values corresponding to the timer. Here, the first match value corresponding to each logical bit information is used to control the logical bit of the logical bit information to 0 or 1 by controlling the time when the logical bit information is at a high level.

[0073] In general, in the signal transmission protocol, the operation time corresponding to each logical bit information among a plurality of logical bit information is the same. For example, assuming that the operation time corresponding to each logical bit information is tBIT, the reload value corresponding to the timer is a numerical value obtained by converting tBIT based on the timing unit of the timer. For example, if the operation time tBIT is 100 seconds and the timing unit of the timer is seconds, the reload value is 100.

[0074] In addition, the first match value corresponding to each logical bit information is related to the logical bit corresponding to the logical bit information. As shown in FIG. 3, tBIT is the operation time corresponding to one logical bit information. When the logical bit of one logical bit information is 0, the signal corresponding to the logical bit information is a waveform with a duty ratio of about 1 / 4. Here, the holding time of the high level satisfies 0.2 to 0.4tBIT. Also, as shown in FIG. 4, when the logical bit of one logical bit information is 1, the signal corresponding to the logical bit information is a waveform with a duty ratio of 3 / 4. Here, the holding time of the high level satisfies 0.6 to 0.8tBIT.

[0075] As can be seen from the above content, in order to simulate a hardware interface signal in a software manner, it is essential to realize waveform conversion (there is waveform conversion between high level and low level whether it is logic 0 or logic 1). Therefore, the present application realizes waveform conversion by the reload value Reload Value and the first match value First Match Value of the timer. Optionally, while the present application realizes the control of the operation time of logical bits, that is, the operation time of one waveform signal, by the reload value, it realizes the identification of different logical bits by the first match value. That is, the waveform signals corresponding to different logical bits have different duty ratios.

[0076] Optionally, the first system needs to sequentially generate hardware interface sub-signals corresponding to each logical bit information based on the reload value and the first match value corresponding to each logical bit information according to the order before and after among a plurality of logical bit information corresponding to a request command, and obtain a hardware interface signal. For example, assuming that the request command corresponds to logical bit information 1, logical bit information 2, logical bit information 3... logical bit information i... logical bit information N, the first system sequentially generates hardware interface sub-signals corresponding to each logical bit information, that is, hardware interface sub-signal 1, hardware interface sub-signal 2, hardware interface sub-signal 3... hardware interface sub-signal i... hardware interface sub-signal N. Finally, hardware interface sub-signal 1, hardware interface sub-signal 2, hardware interface sub-signal 3... hardware interface sub-signal i... hardware interface sub-signal N are spliced to form a hardware interface signal.

[0077] Optionally, the generation process of the hardware interface sub-signal corresponding to each logical bit information is as shown in FIG. 5. In step S501, a decrement operation is performed on the reload value corresponding to each logical bit information based on the timer.

[0078] In step S502, before the reload value corresponding to each logical bit information is decremented to the first match value corresponding to the logical bit information, the first system outputs a first signal corresponding to the logical bit information, where the first signal is a high-level signal. In step S503, after the reload value corresponding to each logical bit information is decremented to the first match value corresponding to the logical bit information, the first system outputs a second signal corresponding to the logical bit information, where the second signal is a low-level signal.

[0079] In step S504, when the reload value corresponding to each logical bit information is decremented to 0, it is determined to generate a hardware interface sub-signal corresponding to the logical bit information, and the hardware interface sub-signal corresponding to each logical bit information is obtained, where the hardware interface sub-signal corresponding to each logical bit information is composed of the first signal and the second signal corresponding to the logical bit information.

[0080] Optionally, based on the operating principle of the timer, one down-counter is included inside the timer. The down-counter triggers a timer interrupt when it counts down to 0 with the system clock, automatically loads the reload value, and then resumes decrement counting. Also, when the down-count value is equal to the first match value, it triggers an interrupt. Here, the interrupt may be understood as an identifier. Therefore, the interrupt is called an interrupt identifier, the first interrupt is called the first interrupt identifier, and the second interrupt may be called the second interrupt identifier. In order to realize the waveforms of logical bit 0 and logical bit 1 in this application, the reload value of the timer is set to the operating time tBIT corresponding to the logical bit information, the first match value is set to 3×tBIT / 4 to represent logical 0, and the first match value is set to 1×tBIT / 4 to represent logical 1.

[0081] The following describes the software implementation process of the hardware interface sub-signal corresponding to each logical bit information, taking a transmission rate of 10 kbps as an example. Set the reload value Reload Value of the timer to 100 ms, Set the high-level output (it is necessary to pull the signal to the high level every time a signal is generated), If the logical bit of one logical bit information is 0, set the value of the first match value First Match Value corresponding to the logical bit information to 75 ms, If the logical bit of one logical bit information is 1, set the value of the first match value First Match Value corresponding to the logical bit information to 25 ms, When the down-count value of the timer matches the first match value, the first system outputs a low level, When the reload value of the timer is decremented by 0, determine the generation of the hardware interface sub-signal corresponding to the logical bit, and the first system pulls the low level to the high level and continues to generate the hardware interface sub-signal corresponding to the next logical bit information.

[0082] As can be seen from the above content, the present application realizes the waveform conversion of the signal by the reload value Reload Value and the first match value First Match Value of the timer, thereby simulating and generating the hardware interface signal. In an alternative embodiment, when the reload value corresponding to each logical bit information is decremented to the first match value corresponding to the logical bit information, the first system also triggers the first interrupt corresponding to the logical bit information, and when the reload value corresponding to each logical bit information is decremented to 0, the first system also triggers the second interrupt corresponding to the logical bit information.

[0083] Note that this application realizes an interrupt count by recording a first interrupt and a second interrupt triggered corresponding to each logical bit information, and further can determine which field in a request command is a field for performing current signal conversion based on the interrupt count. Optionally, each time one of the first interrupt or the second interrupt is triggered, the first system performs an interrupt count once, determines the field in which the current signal conversion process in the request command is being performed based on the interrupt count, where the signal conversion process is used to generate a hardware interface sub-signal corresponding to the logical bit information corresponding to each field in the request command.

[0084] Optionally, the first system may obtain the number of bytes corresponding to each field in the request command, and subsequently determine the number of logical bit information corresponding to the request command based on the number of bytes, where each byte corresponding to the request command corresponds to one logical bit information. Subsequently, the first system determines the number of interrupts corresponding to the request command based on the number of logical bit information, where the number of interrupts corresponding to the request command is twice the number of logical bit information. Finally, the first system determines the field in which the current signal conversion process in the request command is being performed based on the number of interrupts and the interrupt count.

[0085] For example, as shown in FIG. 6, one request command includes four fields: an address rate negotiation bit, a target address addr, a message rate negotiation bit, and a write length. Here, the number of bytes corresponding to the address rate negotiation bit is 2, that is, the address rate negotiation bit is composed of 2 bits; the number of bytes corresponding to the target address addr is 8; the number of bytes corresponding to the message rate negotiation bit is 1; and the number of bytes corresponding to the write length is 8. Thus, the request command in FIG. 6 corresponds to a total of 19 bytes. Since each byte corresponds to one logical bit of information, the request command corresponds to 19 logical bits of information. Also, since each logical bit of information corresponds to two interrupts, the request command corresponds to a total of 38 interrupts, that is, the number of interrupts of the request command is 38. In addition, through the interrupt count, the first system can determine that the 2 bits of the address rate negotiation bit are processed by 4 interrupts from interrupt 0 to interrupt 3, and the field of the write length is processed by 16 interrupts from interrupt 22 to interrupt 37.

[0086] Optionally, the first system determines the logical bit information that is currently being converted into the hardware interface sub-signal based on the number of interrupts and the interrupt count, determines the byte corresponding to the logical bit information that is currently being converted into the hardware interface sub-signal as the target byte, and thereby the first system determines the field corresponding to the target byte as the field in the request command where the current signal conversion process is being performed.

[0087] For example, still taking the request command in FIG. 6 above as an example, assuming that the current interrupt count is 4, it can be determined that the logical bit information currently undergoing signal conversion is the second logical bit information among 19 pieces of logical bit information, and the target byte is the second byte among 19 bytes. Since the field corresponding to the second byte is the address rate negotiation bit, the first system can determine that the field in the request command where the current signal conversion process is being performed is the address rate negotiation bit.

[0088] In addition to being able to determine the field where the signal conversion process is being performed using the interrupt count method, the present application can further determine the field where the signal conversion process is being performed by recording the number of times the reload value decreases to the first match value and the number of times the reload value decreases to 0, or determine the field where the signal conversion process has already been completed, or determine the field where the signal conversion process has not yet been completed.

[0089] Optionally, the present application may separately record the fields where the signal conversion process has already been completed. Compared with determining the field where the signal conversion process is being performed by recording the number of times the reload value decreases to the first match value and the number of times the reload value decreases to 0, separately recording the fields where the signal conversion process has already been completed and determining the fields where the signal conversion process is being performed using the interrupt count can reduce the computational load of the first system, thereby realizing the technical effect of more simply and efficiently determining the fields.

[0090] In an alternative embodiment, the first system may further transmit to the display screen the fields where the current signal conversion process is being performed, the fields where the signal conversion process has already been completed, and the fields where the signal conversion process has not been completed yet. Thereby, in the event of a failure in signal conversion, the operator can directly check the progress of signal conversion from the display screen, which further helps the operator quickly resume the signal conversion operation. For example, the operator may send a control command to the first system to request the first system to resume signal conversion from the field where the signal conversion process was being performed when the failure occurred in signal conversion. There is no need to repeat signal conversion for the fields where the signal conversion process has already been completed, thereby improving the signal conversion efficiency and avoiding waste of the system's computing resources.

[0091] Hereinafter, in order to better explain the generation process of the hardware interface signal in the present application, taking the case where the hardware interface signal is a PECI signal as an example, the description will be made with reference to the drawings. As shown in FIG. 7, first, the first system calls an initialization function. Here, the main function of the initialization function is to complete the initialization function before the transmission of the request command. Based on the signal transmission protocol specification, the default level state is the low level. Therefore, the initialization function is used to control the level of the signal generation port to the low level. Here, the signal generation port may be a GPIO port. Subsequently, the first system proceeds to the transfer function processing process, and the specific steps are as shown in FIG. 8.

[0092] In step 1, first, the first system extracts request parameters, and such request parameters include the target address addr, write length wl, read length rl, instruction code cmd, and parameter para in the request command. In step 2, the first system calculates the number of interrupts required for this transmission. Here, two interrupts are required to complete the transmission of each logical bit information (one interrupt occurs when the downcount value becomes 0, and one interrupt occurs when the downcount value is equal to the first match value). The reload value is used to define the start of the logical bit information, and the first match value is used to control the logical bit corresponding to the logical bit information to be output to 0 or 1. In step 3, the first system sets the reload value Reload Value of the timer to one logical bit time tBIT. In step 4, the first system sets the first match value First Match Value of the timer to 3×tBIT / 4 hours (corresponding to logical 0, because each transmission starts from logical 0). In step 5, the first system turns on the timer interrupt and starts the timer. In step 6, when the timer interrupt processing is completed, this transmission is terminated.

[0093] Optionally, FIG. 9 shows a flowchart of the processing of the timer interrupt function according to an embodiment of the present application. As shown in FIG. 9, each time after adding 1 to the variable of the interrupt count, the first system compares the obtained interrupt count with the number of interrupts required for this transmission calculated previously. If the interrupt count is greater than the number of interrupts, the timer is turned off, and it is determined that the hardware interface signal corresponding to the request command has already been generated. If the interrupt count is less than or equal to the number of interrupts, the field to be processed currently is determined based on the interrupt count and the number of interrupts, and it is determined whether the logical bit of the logical bit information that needs to perform the next signal conversion is 1. If not, the first match value is updated to 3×tBIT / 4, and if it is 1, the first match value is updated to tBIT / 4, thereby realizing the control of the level change of the signal generation port.

[0094] In an alternative embodiment, the hardware interface system in the present application can be implemented by a dual system. Optionally, when a first request triggered by a second system is detected by a first system, request data is acquired, where the first system and the second system operate on the same processor, the request data is generated by the second system, and the service response speed of the second system is slower than that of the first system. Finally, the first system analyzes the request data to obtain a request instruction.

[0095] Optionally, the second system can be, for example, a Linux system and can be various types of software systems, and the present application does not particularly limit the type of the second system. Also, in order to continuously and smoothly generate a hardware interface signal, the available computing resources of the first system are greater than those of the second system. In other words, the present application selects a system with more available resources to generate a hardware interface signal, thereby avoiding the problem that the hardware interface signal cannot be continuously generated due to insufficient system resources.

[0096] In another alternative embodiment, the available computing resources of the first system can be set to be greater than a preset threshold, and the preset threshold is used to characterize the maximum computing resource value required when continuously generating a hardware interface signal. Optionally, before acquiring the request data, the present application stores the request data in a target memory by the second system. After the storage of the request data is completed, the second system triggers a first request, where the first request is used to notify the first system to read the request data from the target memory, and the target memory is a memory accessible by both the first system and the second system.

[0097] As shown in FIG. 10, taking as an example that the first system is an RTOS system, the second system is a Linux system, and the hardware interface signal is a PECI signal. The present application divides the software processing flow of the PECI communication protocol in the chip into two processes: instruction request and instruction response, and the following will explain these two processes in detail respectively.

[0098] As shown in FIG. 10, for the instruction request process, first, the upper-layer application related to the PECI service in the Linux system (such as fault diagnosis, CPU temperature acquisition, etc.) actively starts the PECI request instructions as needed. These request instructions include, but are not limited to, basic Ping() instructions, CPU temperature acquisition instructions, MSR register information reading instructions, etc. The codes of different PECI request instructions are realized by corresponding interface functions.

[0099] Optionally, the Linux system uses the instruction parameter structuring module in FIG. 10 to write the request data such as the target address, read / write length, instruction code, para parameter, etc. of each request instruction into the target memory according to the PECI protocol specification. When all the request data is written into the target memory, the Linux system generates a first request by the interrupt event generation and detection function module in FIG. 10 and notifies the RTOS system. Here, the first request may be an SGI interrupt request (software generated interrupt, communication interrupt request between processor cores).

[0100] It should be noted that in the process of storing the requested data in the target memory by the second system, the second system stores the requested data in the target memory in the form of a first data structure. Here, the first data structure includes at least a device address, a write length, a read length, an instruction code, and request parameters. The device address is used to characterize the address of the target device, and the target device is a device that generates response data based on the hardware interface signal. The instruction code is used to distinguish different request instructions. The write length is used to characterize the number of bytes from the instruction code to the requested data. The read length is used to characterize the number of bytes including the completion code and the read data in the requested data. The request parameters are used to characterize the parameters of the request instruction.

[0101] As shown in Table 1, Table 1 shows an example of the data structure of the selectable requested data (corresponding to the first data structure).

[0102]

Table 1

[0103] Optionally, as shown in FIG. 10, after detecting the first request triggered by the Linux system, the RTOS system reads the requested data in the target memory, and then completes the data analysis process by the instruction analysis and parameter extraction function module in FIG. 10. Subsequently, the PECI instruction and parameter matching function module determines the corresponding PECI request instruction and instruction parameters based on the analyzed data, and finally transmits the PECI signal from the GPIO port of the BMC by the PECI waveform generation and transmission module in FIG. 10.

[0104] In an alternative embodiment, the first system can also receive response data corresponding to the hardware interface signal, where the transmission format of the response data is the same as that of the hardware interface signal. Next, the first system adjusts the data structure of the response data to a second data structure. Also, after adjusting the data structure of the response data to the second data structure, the present application triggers a second request by the first system, where the second request is used to notify the second system to read the response data.

[0105] Optionally, still taking the hardware interface signal being a PECI signal as an example, FIG. 10 further shows the instruction response process. As shown in FIG. 10, first, the RTOS system receives the response data transmitted from the PECI bus, and then the PECI instruction parsing and parameter extraction function module in FIG. 10 completes the data parsing, converting the signal format of the response data from the format of the hardware interface signal to the format of the software signal. For example, by identifying the waveform change between the high-level signal and the low-level signal in the hardware interface signal, the corresponding logical bit information is obtained, and the software signal data is obtained based on the logical bit information. The parsed response data is adjusted by the instruction parameter structuring module and written into the target memory. After all the parsed response data is written, the interrupt event generation and detection module of the RTOS system triggers a second request and notifies the Linux system. When the Linux system detects the second request, it actively reads the parsed response data stored in the target memory, processes the data by the instruction parsing and parameter extraction module, and then returns it to the upper-layer application. Here, the second request is also an SGI interrupt request.

[0106] It should be noted that the shared memory in FIG. 10 is the target memory in the present application. In the present application, the target memory may be other memories in addition to the shared memory, such as, for example, a random access memory (abbreviated as RAM), a flash memory (Flash), etc. In an alternative embodiment, in view of the fact that both the above first request and the second request are interrupt requests (for example, SGI interrupt requests), the interrupt requests will be described below.

[0107] Optionally, preempting and releasing processing resources between different operating systems can be completed by an inter-core interrupt, for example, an SGI interrupt request. One operating system can send a resource preemption request (for example, a core preemption request) or a resource release request (for example, a core release request) to another operating system by IPI (Inter-Processor Interrupt) to request preemption or release of processing resources. Taking the Linux system as an example, in the Linux system, inter-core communication can be realized based on a custom interrupt vector table and interrupt events between different operating systems. Here, IPI is an interrupt triggered between multiple cores within a SOC (System on Chip, also called a system-on-chip). Different from a general external interrupt, therefore, a core can reserve some interrupt numbers specifically for IPI. In the ARM 64 architecture (CPU architecture), there are 16 interrupt numbers from 0 to 15. In one exemplary embodiment, a first interaction request of a first operating system (which may correspond to the above first system) can be transmitted to a second operating system through an inter-core communication interface, and the processing method includes at least one of the following.

[0108] The core - to - core communication interface transmits a first preemption request with an interrupt number being the first interrupt number to a second operating system (which may correspond to the second system), where the first preemption request is used to preempt the processing resources of the second operating system. The core - to - core communication interface transmits a resource release request with an interrupt number being the second interrupt number to the second operating system, where the resource release request is used to request the release of the processing resources occupied by the first operating system to the second operating system.

[0109] In this embodiment, the preemption and release of processing resources between different operating systems can be completed by core - to - core interrupts. Different interrupt events can be defined to correspond to different resource exchange types, and different interrupt events can correspond to different interrupt numbers. Here, the interrupt number assigned to the first interrupt event in which the first operating system applies for preemption of the processing resources of the second operating system is the first interrupt number, and the interrupt number assigned to the second interrupt event in which the first operating system actively releases the processing resources to the second operating system is the second interrupt number. As an alternative embodiment, the first exchange request may be a first preemption request, that is, a request used to request preemption of the processing resources of the second operating system. The first operating system transmits a first preemption request with an interrupt number being the first interrupt number to the second operating system through the core - to - core communication interface. That is, the trigger source of the core - to - core communication interrupt with an interrupt number being the first interrupt number is the first operating system, and the response source is the second operating system. The meaning of this core - to - core communication interrupt is that the first operating system preempts the processing resources of the second operating system.

[0110] As another alternative embodiment, the first interaction request may be a resource release request, that is, it is used to request the release of processing resources occupied by the first operating system to the second operating system. The first operating system can send a resource release request with an interrupt number being the second interrupt number to the second operating system through the inter-core communication interface. That is, the trigger source of the inter-core communication interrupt with the interrupt number being the second interrupt number is the first operating system, and the response source is the second operating system. The meaning of this inter-core communication interrupt is that the first operating system actively releases the processing resources to the second operating system.

[0111] According to this embodiment, by allocating interrupt numbers for preemption and active release of processing resources between different operating systems, resource scheduling between operating systems is performed in the way of inter-core communication interrupt, improving the accuracy of resource scheduling. In one exemplary embodiment, transmitting the second interaction request of the second operating system to the first operating system through the inter-core communication interface includes transmitting, by the inter-core communication interface, a second preemption request with an interrupt number being the third interrupt number from the second operating system, where the second preemption request is used to request preemption of the processing resources of the first operating system.

[0112] In this embodiment, similar to the previous embodiment, the preemption and release of processing resources between different operating systems can be completed by inter-core interrupts. It can be defined that different interrupt events correspond to different resource transaction types, and different interrupt events correspond to different interrupt numbers. Here, the interrupt number assigned to the third interrupt event for the second operating system to apply to the first operating system for preemption of processing resources is the third interrupt number.

[0113] Optionally, the second transaction request may be a second preemption request, that is, a request used to request preemption of the processing resources of the first operating system. The second operating system can transmit a second preemption request with an interrupt number of the third interrupt number to the first operating system through the inter-core communication interface. That is, the trigger source of the inter-core communication interrupt with an interrupt number of the third interrupt number is the second operating system, and the response source is the first operating system. The meaning of this inter-core communication interrupt is that the second operating system preempts the processing resources of the first operating system.

[0114] According to this embodiment, by allocating interrupt numbers for preemption of processing resources between different operating systems, resource scheduling between operating systems is performed in the manner of inter-core communication interrupts, improving the accuracy of resource scheduling. In one exemplary embodiment, the second operating system can obtain a second transaction response returned in response to the second transaction request through the inter-core communication interface, including at least one of the following.

[0115] The core - to - core communication interface transmits a resource release permission response with an interrupt number being the fourth interrupt number to the second operating system, where the resource release permission response is used to instruct the first operating system to permit the second operating system to preempt the processing resources of the first operating system. The core - to - core communication interface transmits a resource release rejection response with an interrupt number being the fifth interrupt number to the second operating system, where the resource release rejection response is used to instruct the first operating system to reject the second operating system from preempting the processing resources of the first operating system.

[0116] In this embodiment, similar to the previous embodiment, the preemption and release of processing resources between different operating systems can be completed by core - to - core interrupts. Different interrupt events can be defined to correspond to different resource exchange types, and different interrupt events can correspond to different interrupt numbers. Here, the interrupt numbers assigned to the fourth interrupt event and the fifth interrupt event for which the second operating system applies to the first operating system to return a resource preemption response are the fifth interrupt number. Here, the fourth interrupt event is an interrupt event that permits resource preemption, and the fifth interrupt event is an interrupt event that rejects resource preemption.

[0117] As an alternative embodiment, if the first operating system determines to permit the second operating system to occupy at least some of its processing resources, the first operating system can send a resource release permission response with an interrupt number being the fourth interrupt number to the second operating system through the inter-core communication interface. That is, the trigger source of the inter-core communication interrupt with the interrupt number being the fourth interrupt number is the first operating system, and the response source is the second operating system. The meaning of this inter-core communication interrupt is that the first operating system passively releases the processing resources to the second operating system.

[0118] As another alternative embodiment, if the first operating system determines to reject the second operating system's occupation of its processing resources, the first operating system can send a resource release rejection response with an interrupt number being the fifth interrupt number to the second operating system through the inter-core communication interface. That is, the trigger source of the inter-core communication interrupt with the interrupt number being the fifth interrupt number is the first operating system, and the response source is the second operating system. The meaning of this inter-core communication interrupt is that the first operating system rejects releasing the processing resources to the second operating system.

[0119] According to this embodiment, by permitting preemption of processing resources between different operating systems and allocating interrupt numbers used to reject preemption of processing resources, resource scheduling between operating systems is performed in the way of inter-core communication interrupt, improving the accuracy of resource scheduling. As selectable examples, the inter-core communication interrupt will be described below by taking the RTOS system and the Linux system as examples. In the Linux system, inter-core communication can be realized based on a custom interrupt vector table and interrupt events between heterogeneous operating systems. The Linux operating system makes full use of bit numbers not defined by SGI to realize the customization of terminal signals and reduce the cost of inter-core communication. The undefined bit numbers may be numbers 8 to 15. In a heterogeneous multi-core operating system, in order to best support the current resource allocation method, numbers 8 to 15 (a total of 8 interrupts) are used to characterize the inter-core interrupt vector table, and the executable allocation methods of the vector table are as shown in Table 2.

[0120]

Table 2

[0121] Here, the first interrupt number corresponds to interrupt number 12, the second interrupt number corresponds to interrupt number 8, the third interrupt number corresponds to interrupt number 9, the fourth interrupt number corresponds to interrupt number 10, and the fifth interrupt number corresponds to interrupt number 11. As shown in Table 2, active release means that when there is no traffic scheduling in the RTOS system (i.e., in the idle state), an SGI interrupt with interrupt number 8 is sent to the Linux system. At this time, the core resources of the RTOS are taken over by the Linux system, and the RTOS system enters the sleep state. Passive release means that when the traffic load of the Linux system increases rapidly, an SGI interrupt with interrupt number 9 is sent to the RTOS system. At this time, if the process being executed by the RTOS system is allowed to be interrupted (processes in the RTOS system have priorities and can be arranged according to the actual situation. If the priority is higher than interrupt 9, it cannot be interrupted; if it is lower, it can be interrupted), the RTOS system sends an SGI interrupt with interrupt number 10 to the Linux system, and the CPU core resources it occupies are passively released and used for Linux system scheduling. Then, the RTOS system enters the sleep state. At this time, if the RTOS system does not allow itself to be interrupted, an SGI interrupt with interrupt number 11 is sent to the Linux system to notify the Linux system that the core resources of the RTOS cannot be released at this time. At this time, the Linux system continues to execute according to the current operation policy and does not change.

[0122] Note that the inter-core communication vector table is not unique and is not limited to the inter-core communication vector table shown in Table 2 above. Optionally, the second data structure includes at least a first calibration value, a second calibration value, and response valid data. Here, the first calibration value is used to characterize the calibration value in the request data, the second calibration value is used to characterize the calibration value in the response data, and the response valid data is used to characterize the data for explaining the completion code and the state of the target device in the response data. The target device is a device that generates response data based on the hardware interface signal.

[0123] As shown in Table 3, Table 3 shows an example of the data structure of selectable response data (corresponding to the second data structure).

[0124]

Table 3

[0125] Optionally, Table 4 shows examples of the first requirement and the second requirement.

[0126]

Table 4

[0127] In an optional example, after generating a hardware interface signal corresponding to a request instruction based on logical bit information and a timer, the first system converts the voltage of the hardware interface signal to obtain a target hardware interface signal. Optionally, the first system can input the hardware interface signal into a voltage conversion device and obtain the target hardware interface signal output from the voltage conversion device.

[0128] Optionally, the voltage conversion device may be a CPLD (Complex Programmable Logic Device), and the CPLD can be connected to a target device, where the target device may be a CPU in a server. Taking the example that the hardware interface signal is a PECI signal and the chip is a BMC chip, FIG. 11 shows a hardware topology architecture diagram for simulating and generating a PECI signal according to the present application. As shown in FIG. 11, two software systems, namely a Linux system and an RTOS system (the two systems can be executed on different BMC cores), are executed on a BMC chip (corresponding to the BMC device in FIG. 11). Here, the Linux system is used to process general management services and PECI services of the BMC. The PECI service of the proposed method is executed as an upper-layer application in the Linux system. When service data exchange is required (for example, the BMC starts collecting fault register information), the Linux system communicates with the RTOS system, further activates the GPIO port in the RTOS, and the RTOS system simulates a PECI software module to generate a PECI signal.

[0129] It should be noted that the PECI signal transmitted from the GPIO port of the BMC at this time may not be able to meet the electrical characteristic requirements of the PECI protocol. For example, the operating voltage of the CPU is 5V, but the voltage of the signal output from the GPIO port of the BMC is 3.3V. Considering the generality of implementation, the present application may input the generated PECI signal into a GPIO port of the CPLD, and then perform voltage conversion by the internal logic of the CPLD. The converted PECI waveform meets the PECI protocol requirements and also meets the voltage requirements corresponding to the target device (for example, the voltage of the converted PECI signal is 3.3V). Finally, the PECI signal is output by another GPIO of the CPLD, and this GPIO port is physically connected to the standard PECI interface on the CPU side.

[0130] It should be noted that the solution in the present application can be applied not only to generating PECI signals instead of the PECI interface, but also to other hardware interfaces. In one selectable embodiment, Table 5 shows multiple types of hardware interfaces supported by the embodiments of the present application.

[0131]

Table 5

[0132] In a selectable embodiment, FIG. 12 shows an interaction diagram between a selectable first system and a second system according to the embodiment of the present application. As shown in FIG. 12, the specific steps of the interaction between the Linux system (corresponding to the second system) and the RTOS system (corresponding to the first system) are as follows.

[0133] In step 1, as the requester and user of the request command, before triggering the request command, the Linux system first stores the request data in the target memory. In step 2, the Linux system triggers the first request and notifies the RTOS system of the completion of the preparation of the PECI request data. In step 3, after receiving the first request, the RTOS system reads the request data from the target memory and generates a hardware interface signal based on the request data. In step 4, the RTOS system receives the response data corresponding to the hardware interface signal. In step 5, the RTOS system stores the received response data in the target memory. In step 6, the RTOS triggers the second request and notifies the Linux system of the completion of the preparation of the response data. In step 7, the Linux system obtains and analyzes the response data from the target memory.

[0134] As can be seen from the above content, this application integrates the first system and the second system of the embedded system, realizes the data exchange in the embedded system by means of core interrupt and memory sharing, constructs a waveform generator function module for required instructions in the RTOS system, and realizes the communication of the hardware interface signal between the embedded system and external devices by means of software simulation. In addition, this application makes full use of the high real-time feature of the RTOS system, ensures the accuracy of the sequence when simulating the required instruction waveform, and has the characteristics of flexibility and efficiency. By means of the solution of this application, the design difficulty of the chip can be significantly reduced. Since the hardware interface signal is generated by using software simulation, more possibilities are provided for the optimization design between the communication function and other service functions in the embedded system. In addition, since the controller specially used to realize the hardware interface signal communication in the chip is omitted, the design cost and manufacturing cost of the chip can be reduced.

[0135] In one selectable embodiment, this application further provides a startup control process of the operating system, and this process includes the following steps. In step A, the first operating system running on the first processor core of the processor controls the hardware controller of the target device through the first bus to control the operating state of the target device.

[0136] For example, for devices such as servers, personal computers, and industrial computers, specific devices for executing operations related to the operation of the devices may be arranged. In the related art, usually, when the system is powered on, these specific devices start to operate. After the system is powered on, the operating system running on the processor can take over the specific device normally only after a certain period of time and control the operating state of the specific device. During the startup of the operating system, the specific device is uncontrollable. For example, when the system is powered on, the fan starts to operate. After the system is powered on, the operating system running on the CPU takes a certain amount of time to properly take over the fan and can set the rotation speed of the fan. Therefore, the fan cannot be controlled during the startup of the operating system.

[0137] For example, in order to realize the ability to control the fan during the startup of the operating system, the server uses a control method by combining the BMC and the CPLD, the personal computer uses a control method by the EC chip (the function that the EC chip adjusts the rotation speed of the fan according to the temperature), and the industrial computer uses a control method by a custom chip. Thus, during the startup of the operating systems of the server, personal computer, and industrial computer, the CPLD, EC chip, and custom chip are involved in controlling the rotation speed of the fan. When the operating system is fully started, the control right of the fan is passed to the application program in the operating system for control.

[0138] To at least partially solve the above technical problems, a startup control method of a multi-core multi-system (for example, a multi-core dual-system) is used. Different operating systems of the embedded system can be executed on different processor cores of the processor. Since the response speeds of different operating systems are different, when the second operating system fails to start, restarts, or cannot control the operating state of a specific device in other cases, the operating state of the specific device can be controlled by the first operating system with a response speed higher than that of the second operating system, reducing the situation where the operating state of the specific device cannot be controlled. Also, since there is no need to add extra costs, it further has good scalability.

[0139] In this embodiment, when the second operating system fails to start, restarts, or cannot control the operating state of a specific device in other cases, the first operating system controls the hardware controller of the target device via the first bus to control the operating state of the target device. The target device here may be a fan or other device that needs to operate when the system starts. For a fan, the corresponding hardware controller is a fan controller, for example, a PWM (Pulse Width Modulation) controller or a FanTach (fan rotation speed) controller. Here, if the first operating system (for example, an RTOS system) is used instead of the conventional CPLD, EC chip, or custom chip, while saving hardware costs, device control is realized by software, so the scalability is high.

[0140] For example, a dual-system, RTOS system, and Linux system are realized based on the BMC dual-core, a fan is realized based on the multi-core dual-system, and using the high real-time property of the RTOS system, during the startup of the Linux system, the fan is controlled by the RTOS system instead of the CPLD, EC chip, or custom chip, that is, the control right of the fan is taken over, and the operating state of the fan can be controlled at a sufficiently fast speed.

[0141] In step B, the startup of the second operating system on the second processor core of the processor is booted. When power is supplied to the system or when the second operating system is restarted, the startup of the second operating system on the second processor core of the processor is booted, and the second operating system can be operated on the second processor core. Here, the startup of the second operating system on the second processor core means scheduling the second processor core to the second operating system, and the system file or ISO file of the operating system may be stored on the chip where the processor is located or in a memory outside the chip, for example, in an external RAM (Random Access Memory).

[0142] In step C, after the second operating system is started, the hardware controller is taken over via the first bus by the second operating system, and the control right of the target device is taken over. After the startup of the second operating system is completed, the operation state of the target device can always be controlled by the first operating system. In order to operate multiple operating systems on a multi-core processor, it is necessary to exchange data between the multiple operating systems. Also, considering the ease of overall control of the device by one operating system, the second operating system may take over the control right of the target device. For example, the second operating system may take over the hardware controller via the first bus. The method by which the second operating system takes over the control right of the target device may be as follows. After the startup of the second operating system, a device handover request is sent from the second operating system to the first operating system. For example, an interrupt request is sent via the second bus to request taking over the hardware controller of the target device. The first operating system receives the device handover request sent from the second operating system and may pass the control right of the target device to the second operating system. Furthermore, operations related to the handover of the control right of the target device may be executed. For example, the execution of a service (process) for controlling the operation state of the target device may be stopped.

[0143] For example, when the Linux system is fully started, the RTOS system passes the control right of the fan to the Linux system, and the Linux system controls the fan. The above process may be executed after the system is powered on. That is, using the startup method of a multi-core dual system, first start the RTOS system, which is advantageous for getting involved in the control of the fan earlier. When the Linux system is fully started, the RTOS system passes the control right of the fan to the Linux system for control.

[0144] In one exemplary embodiment, before the first operating system running on the first processor core of the processor controls the hardware controller of the target device via the first bus, further, after powering on the chip where the processor is located, the step of waking up the first processor core by the processor and the step of executing the bootloader program of the first operating system by the first processor core to boot the startup of the first operating system on the first processor core are included.

[0145] The entire system may be divided into two stages, an initial startup stage and a real-time operation stage, according to the operation period, and the startup control method in this embodiment may be executed in the initial startup stage or the real-time operation stage. Regarding the initial startup stage, the initial startup stage starts from powering on the system, that is, powering on the chip where the processor is located. When the system is powered on, one core is woken up to execute the boot operation of the operating system, and the remaining cores are temporarily in the sleep state. The woken-up core may be the first processor core.

[0146] Optionally, after being powered on, the system first executes a preset core scheduling policy (startup boot policy), that is, executes the core scheduling policy by one processor core of the processor. The core scheduling policy may be stored in the RAM or Norflash (non-volatile flash memory) on the SOC. The scheduling policy can be flexibly arranged according to different design requirements. Its main function includes specifying the initial processing resources (processor cores) required for different operating systems to operate and determining the boot process of heterogeneous operating systems. Powering on the chip can refer to powering on at the SOC chip level.

[0147] After the first processor core is woken up, the bootloader program can boot the operation of the first operating system on the first processor core, that is, the first processor core can boot the startup of the first operating system on the first processor core by the bootloader program. The bootloader program can be located in a computer or other computer applications, which refers to a program used to boot the loading of the operating system. For example, it includes the specific program in the BootRom. The specific program refers to the code that boots the startup of the operating system, belongs to the BootLoader program, and the BootRom is a small mask ROM (Read-Only Memory) or write-protected flash memory incorporated in the processor chip on the CPU chip.

[0148] In the initial startup stage, if the bootloader boots the startup of the corresponding processor core of the operating system, the success rate of the operating system startup can be increased, so as to prepare for the real-time operation stage. In addition, for the embodiments of each method described above, for the sake of simplicity, they are all represented as a combination of a series of operations. However, as can be understood by those skilled in the art, the present application is not limited to the order of the described operations. Based on the present application, any steps can be performed in other orders or simultaneously. Next, as can be understood by those skilled in the art, the embodiments described in the specification all belong to the preferred embodiments, and such operations and modules are not necessarily required for the present application.

[0149] As can be clearly understood by those skilled in the art from the description of the above embodiments, the method according to the above embodiments can be realized by a method of adding necessary general-purpose hardware platforms to software. Of course, it can also be realized by hardware, but the former is often a more preferred embodiment. Based on such an understanding, the technical solution of the present application can be essentially or the part contributing to the prior art can be embodied in the form of a software product. The computer software product can be stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a plurality of instructions for causing a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the method of each embodiment of the present application.

[0150] According to an embodiment of the present application, there is further provided a hardware interface signal generation device for implementing the above hardware interface signal generation method. As shown in FIG. 13, the hardware interface signal generation device includes an acquisition module 1301, a determination module 1302, and a generation module 1303. Optionally, the acquisition module 1301 is used to acquire a request instruction by a first system, the determination module 1302 is used to determine a plurality of logical bit information corresponding to the request instruction, and the generation module 1303 is used to generate a hardware interface signal corresponding to the request instruction based on the plurality of logical bit information and a timer. In the hardware interface signal generation device provided by the embodiment of the present application, the generation module includes a first determination unit and a second generation unit. Here, the first determination unit is used to determine a reload value and an initial match value corresponding to the timer based on the plurality of logical bit information, and the second generation unit is used to generate a hardware interface signal corresponding to the request instruction based on the reload value and the initial match value. In the apparatus for generating a hardware interface signal provided in the embodiment of the present application, the first determination unit further includes a first acquisition subunit, a first determination subunit, and a second determination subunit. Here, the first acquisition subunit is used to acquire the operation time corresponding to each logical bit information, the first determination subunit is used to determine a reload value based on the operation time, and the second determination subunit is used to determine one initial match value corresponding to the timer based on the logical bit of each logical bit information, and is used to obtain a plurality of initial match values corresponding to the timer. Here, the initial match value corresponding to each logical bit information is used to control the logical bit of the logical bit information to 0 or 1 by controlling the time when the logical bit information is at a high level.

[0151] In the apparatus for generating a hardware interface signal provided in the embodiment of the present application, the second generation unit further includes a first generation subunit that is used to obtain a hardware interface signal, and sequentially generates a hardware interface sub-signal corresponding to each logical bit information based on the reload value and the initial match value corresponding to each logical bit information according to the order before and after among the plurality of logical bit information corresponding to the request command.

[0152] In the hardware interface signal generation device provided in the embodiment of the present application, the first generation subunit further includes a decrement sub-module, a first signal output sub-module, a second signal output sub-module, and a first determination sub-module. Here, the decrement sub-module is used to perform a decrement operation on the reload value corresponding to each logical bit information based on a timer. The first signal output sub-module is used to output a first signal corresponding to the logical bit information by a first system before the reload value corresponding to each logical bit information is decremented to the initial match value corresponding to the logical bit information. Here, the first signal is a high-level signal. The second signal output sub-module is used to output a second signal corresponding to the logical bit information by a first system after the reload value corresponding to each logical bit information is decremented to the initial match value corresponding to the logical bit information. Here, Second signal is a low-level signal. The first determination sub-module determines the generation of a hardware interface sub-signal corresponding to the logical bit information when the reload value corresponding to each logical bit information is decremented to 0, and is used to obtain the hardware interface sub-signal corresponding to each logical bit information. Here, the hardware interface sub-signal corresponding to each logical bit information is composed of the first signal and the second signal corresponding to the logical bit information.

[0153] In the hardware interface signal generation device provided in the embodiment of the present application, the hardware interface signal generation device further includes a first interrupt trigger module and a second interrupt trigger module. Here, the first interrupt trigger module is used to trigger a first interrupt corresponding to the logical bit information when the reload value corresponding to each logical bit information is decremented to the initial match value corresponding to the logical bit information. The second interrupt trigger module is used to trigger a second interrupt corresponding to the logical bit information when the reload value corresponding to each logical bit information is decremented to 0.

[0154] In the hardware interface signal generation device provided in the embodiments of the present application, the hardware interface signal generation device further includes an interrupt count module and a field determination module. Here, each time the interrupt count module triggers a first interrupt or a second interrupt, it is used to perform an interrupt count once, and the field determination module is used to determine the field in which the current signal conversion process in the request instruction is being performed based on the interrupt count. Here, the signal conversion process is used to generate a hardware interface sub-signal corresponding to the logical bit information corresponding to each field in the request instruction.

[0155] In the hardware interface signal generation device provided in the embodiments of the present application, the field determination module further includes a second acquisition unit, a second determination unit, a third determination unit, and a fourth determination unit. Here, the second acquisition unit is used to acquire the number of bytes corresponding to each field in the request instruction, the second determination unit is used to determine the number of logical bit information corresponding to the request instruction based on the number of bytes. Here, each byte corresponding to the request instruction corresponds to one piece of logical bit information. The third determination unit is used to determine the number of interrupts corresponding to the request instruction based on the number of logical bit information. Here, the number of interrupts corresponding to the request instruction is twice the number of logical bit information. The fourth determination unit is used to determine the field in which the current signal conversion process in the request instruction is being performed based on the number of interrupts and the interrupt count.

[0156] In the apparatus for generating a hardware interface signal provided in the embodiment of the present application, the fourth determination unit further includes a third determination subunit, a fourth determination subunit, and a fifth determination subunit. Here, the third determination subunit is used to determine the logical bit information that is being converted into the current hardware interface sub-signal based on the number of interrupts and the interrupt count. The fourth determination subunit is used to determine the byte corresponding to the logical bit information that is being converted into the current hardware interface sub-signal as the target byte. The fifth determination subunit is used to determine the field corresponding to the target byte as the field in which the current signal conversion process in the request instruction is being performed.

[0157] In the apparatus for generating a hardware interface signal provided in the embodiment of the present application, the data structure of the request data corresponding to the request instruction is the first data structure. Here, the first data structure includes at least a device address, a write length, a read length, an instruction code, and request parameters. The device address is used to characterize the address of the target device, and the target device is a device that generates response data based on the hardware interface signal. The instruction code is used to distinguish different request instructions. The write length is used to characterize the number of bytes from the instruction code to the request data. The read length is used to characterize the number of bytes including the completion code and the read data in the request data. The request parameters are used to characterize the parameters of the request instruction.

[0158] In the apparatus for generating a hardware interface signal provided in the embodiment of the present application, the acquisition module further includes a request data acquisition unit and a request data analysis unit. Here, the request data acquisition unit is used to acquire request data when a first request triggered by a second system is detected by the first system. Here, the first system and the second system operate on the same processor, the request data is generated by the second system, the service response speed of the second system is smaller than that of the first system, and the request data analysis unit is used to analyze the request data and obtain a request instruction.

[0159] In the apparatus for generating a hardware interface signal provided in the embodiment of the present application, the apparatus for generating a hardware interface signal is a request data storage module used to store request data in a target memory by a second system and trigger a first request by the second system after the storage of the request data is completed. The first request is used to notify the first system to read request data from the target memory, and the target memory is a memory accessible by both the first system and the second system. The apparatus for generating a hardware interface signal further includes the request data storage module.

[0160] In the apparatus for generating a hardware interface signal provided in the embodiment of the present application, the apparatus for generating a hardware interface signal further includes a voltage conversion module used to convert the voltage of the hardware interface signal to obtain a target hardware interface signal. In the apparatus for generating a hardware interface signal provided in the embodiment of the present application, the apparatus for generating a hardware interface signal further includes a signal input unit used to input the hardware interface signal to a voltage conversion device and obtain a target hardware interface signal output from the voltage conversion device.

[0161] In the apparatus for generating a hardware interface signal provided in an embodiment of the present application, the apparatus for generating a hardware interface signal further includes a response data receiving module and a data structure adjusting module. Here, the response data receiving module is used to receive response data corresponding to the hardware interface signal by a first system. Here, the transmission format of the response data is the same as the transmission format of the hardware interface signal, and the data structure adjusting module is used to adjust the data structure of the response data to a second data structure.

[0162] In the apparatus for generating a hardware interface signal provided in an embodiment of the present application, the second data structure includes at least a first calibration value, a second calibration value, and response valid data. Here, the first calibration value is used to characterize the calibration value in the request data, the second calibration value is used to characterize the calibration value in the response data, and the response valid data is used to characterize the completion code in the response data and the data for explaining the state of the target device. The target device is a device that generates response data based on the hardware interface signal.

[0163] In the apparatus for generating a hardware interface signal provided in an embodiment of the present application, the apparatus for generating a hardware interface signal is a second request trigger module used to trigger a second request by a first system. The second request further includes a second request trigger module used to notify the second system to read response data.

[0164] In the apparatus for generating a hardware interface signal provided in an embodiment of the present application, the hardware interface signal is any one of a PECI signal, an HDMI signal, an SGMII signal, an RGMII signal, a GPIO signal, and an SPI signal. The embodiments of the present application further provide a computer-readable storage medium. Optionally, in this embodiment, the storage medium can be used to store program codes executed by the above-provided method for generating a hardware interface signal.

[0165] Optionally, in this embodiment, the storage medium can be located in any computer terminal among a group of computer terminals in a computer network or in any mobile terminal among a group of mobile terminals. The embodiments of the present application further provide an electronic device including a storage in which a computer program is stored, and a processor installed to execute the method for generating the above-provided hardware interface signal by executing the computer program.

[0166] The embodiments of the present application can provide a computer terminal that can be any computer terminal device among a group of computer terminals. Optionally, in this embodiment, the computer terminal may be replaced with a terminal device such as a mobile terminal. Optionally, in this embodiment, the computer terminal can be located in at least one network device among a plurality of network devices of a computer network.

[0167] In this embodiment, the computer terminal can execute program codes of steps including obtaining a request instruction by a first system in the method for generating a hardware interface signal, determining a plurality of logical bit information corresponding to the request instruction, and generating a hardware interface signal corresponding to the request instruction based on the plurality of logical bit information and a timer.

[0168] The above computer terminal can execute program codes including: a step of determining a reload value and an initial match value corresponding to a timer based on a plurality of logical bit information in a method for generating a hardware interface signal; and a step of generating a hardware interface signal corresponding to a request command based on the reload value and the initial match value. The above computer terminal can execute program codes including: a step of obtaining an operation time corresponding to each logical bit information in a method for generating a hardware interface signal; a step of determining a reload value based on the operation time; and a step of determining one initial match value corresponding to a timer based on the logical bit of each logical bit information, and obtaining a plurality of initial match values corresponding to the timer, wherein the initial match value corresponding to each logical bit information is used to control the logical bit of the logical bit information to 0 or 1 by controlling the time when the logical bit information is at a high level.

[0169] The above computer terminal can execute program codes including: a step of sequentially generating hardware interface sub-signals corresponding to each logical bit information based on the reload value and the initial match value corresponding to each logical bit information according to the order before and after among the plurality of logical bit information corresponding to a request command, and obtaining a hardware interface signal.

[0170] The above computer terminal can execute program codes including: a step of performing a decrement operation on the reload value corresponding to each logical bit information based on a timer; a step of outputting a first signal corresponding to the logical bit information by a first system before the reload value corresponding to each logical bit information is decremented to the initial match value corresponding to the logical bit information, wherein the first signal is a high-level signal; and a step of outputting a second signal corresponding to the logical bit information by the first system after the reload value corresponding to each logical bit information is decremented to the initial match value corresponding to the logical bit information.Second signal a step of a low-level signal, and when the reload value corresponding to each logical bit information is decremented to 0, determining the generation of a hardware interface sub-signal corresponding to the logical bit information, and obtaining a hardware interface sub-signal corresponding to each logical bit information, wherein the hardware interface sub-signal corresponding to each logical bit information is composed of a first signal and a second signal corresponding to the logical bit information; the program code of the step can be executed.

[0171] The computer terminal can execute program codes of a step of triggering a first interrupt corresponding to the logical bit information when the reload value corresponding to each logical bit information in the method for generating a hardware interface signal is decremented to the initial match value corresponding to the logical bit information, and a step of triggering a second interrupt corresponding to the logical bit information when the reload value corresponding to each logical bit information is decremented to 0.

[0172] In the process of sequentially generating a hardware interface sub-signal corresponding to each logical bit information based on the reload value and the initial match value corresponding to each logical bit information in the method for generating a hardware interface signal by the computer terminal, each time a first interrupt or a second interrupt is triggered, a step of performing an interrupt count once, and a step of determining a field in which the current signal conversion process in the request instruction is being performed based on the interrupt count, wherein the signal conversion process is used to generate a hardware interface sub-signal corresponding to the logical bit information corresponding to each field in the request instruction; the program code of the step can be executed.

[0173] The above computer terminal can execute program codes including steps of: obtaining the number of bytes corresponding to each field in a request command in a method for generating a hardware interface signal; determining the number of logical bit information corresponding to the request command based on the number of bytes, where each byte corresponding to the request command corresponds to one piece of logical bit information; determining the number of interrupts corresponding to the request command based on the number of logical bit information, where the number of interrupts corresponding to the request command is twice the number of logical bit information; and determining the field in the request command where the current signal conversion process is being performed based on the number of interrupts and the interrupt count.

[0174] The above computer terminal can execute program codes including steps of: determining the logical bit information that is currently being converted into a hardware interface sub-signal based on the number of interrupts and the interrupt count in a method for generating a hardware interface signal; determining the byte corresponding to the logical bit information that is currently being converted into a hardware interface sub-signal as a target byte; and determining the field corresponding to the target byte as the field in the request command where the current signal conversion process is being performed.

[0175] Also, the data structure of the request data corresponding to the request command is a first data structure. Here, the first data structure includes at least a device address, a write length, a read length, an instruction code, and request parameters. The device address is used to characterize the address of the target device, where the target device is a device that generates response data based on the hardware interface signal. The instruction code is used to distinguish different request commands. The write length is used to characterize the number of bytes from the instruction code to the request data. The read length is used to characterize the number of bytes including the completion code and the read data in the request data. The request parameters are used to characterize the parameters of the request command.

[0176] When the computer terminal in the method for generating a hardware interface signal detects a first request triggered by a second system by a first system, the step of obtaining request data, where the first system and the second system operate on the same processor, the request data is generated by the second system, and the service response speed of the second system is slower than that of the first system, and the step of analyzing the request data to obtain a request instruction, can execute the program code thereof.

[0177] Before obtaining the request data, the computer terminal in the method for generating a hardware interface signal stores the request data in a target memory by a second system, and after the storage of the request data is completed, the second system triggers a first request, where the first request is used to notify the first system to read the request data from the target memory, and the target memory is a memory accessible by both the first system and the second system, and can execute the program code of this step.

[0178] After generating a hardware interface signal corresponding to a request instruction based on logical bit information and a timer in the method for generating a hardware interface signal, the computer terminal can execute the program code of the step of converting the voltage of the hardware interface signal to obtain a target hardware interface signal. The computer terminal in the method for generating a hardware interface signal can execute the program code of the step of inputting the hardware interface signal into a voltage conversion device and obtaining the target hardware interface signal output from the voltage conversion device.

[0179] After generating a hardware interface signal corresponding to a request command based on logical bit information and a timer in the method for generating a hardware interface signal, the computer terminal receives response data corresponding to the hardware interface signal by a first system, where the transmission format of the response data is the same as that of the hardware interface signal, and executes program code for adjusting the data structure of the response data to a second data structure.

[0180] Optionally, the second data structure includes at least a first calibration value, a second calibration value, and response valid data, where the first calibration value is used to characterize the calibration value in the request data, the second calibration value is used to characterize the calibration value in the response data, and the response valid data is used to characterize the completion code in the response data and data for explaining the state of the target device, and the target device is a device that generates response data based on the hardware interface signal.

[0181] After adjusting the data structure of the response data to a second data structure in the method for generating a hardware interface signal, the computer terminal executes program code for triggering a second request by a first system, where the second request is used to notify the second system to read the response data.

[0182] Also, the hardware interface signal is any one of a PECI signal, an HDMI signal, an SGMII signal, an RGMII signal, a GPIO signal, and an SPI signal. Optionally, FIG. 14 is a block diagram of the structure of a computer terminal according to an embodiment of the present application. As shown in FIG. 14, the computer terminal 10 may include one or more (only one is shown in FIG. 14) processors 102 and a storage 104. The computer terminal 10 may further include a memory controller that controls and manages the storage 104, and the computer terminal 10 may further include an external interface that is connected to a radio frequency module, an audio module, a display screen, etc.

[0183] Here, the storage can be used to store software programs and modules such as, for example, program instructions / modules corresponding to the method and apparatus for generating a hardware interface signal in the embodiments of the present application. The processor executes the software programs and modules stored in the storage to execute various functional applications and data processing, that is, to implement the above method for generating a hardware interface signal. The storage may include high-speed random access memory, and may further include non-volatile memory such as, for example, one or more magnetic storage devices, flash memory, or other non-volatile solid-state memories. In some examples, the storage may further include storage that is remotely installed with respect to the processor, and these remote storages can be connected to the computer terminal 10 via a network. Examples of the above network include, but are not limited to, the Internet, a corporate intranet, a local area network, a mobile communication network, and combinations thereof.

[0184] The processor calls the information and application program stored in the storage by the transmission device, and detects whether to receive a serial port switching instruction by a first system in a first processor core, where the serial port switching instruction has information to be switched to a target serial port; when receiving the serial port switching instruction, the first system transmits the serial port switching instruction to a second system in a second processor core, where the service response speed of the second system is slower than that of the first system; and the second system executes serial port switching according to the serial port switching instruction.

[0185] As can be understood by those skilled in the art, the structure shown in FIG. 14 is only schematic, and the computer terminal may be a smart phone (such as an Android mobile phone, an iOS mobile phone, etc.), a tablet computer, a palmtop computer, a Mobile Internet Devices (MID), a PAD, or other terminal devices. FIG. 14 does not limit the structure of the above electronic device. For example, the computer terminal 10 may include more or fewer components (such as a network interface, a display device, etc.) than those shown in FIG. 14, or may have an arrangement different from that shown in FIG. 14.

[0186] Embodiments of the present application further provide an embedded system. As shown in FIG. 15, the embedded system may include a chip and at least two operating systems. Here, the chip includes a processor 1502, a hardware controller 1504, a first bus 1506, and a second bus 1508. Here, the bandwidth of the first bus 1506 is higher than that of the second bus 1508, and the first bus 1506 is arranged in a multi-master multi-slave mode, and the second bus 1508 is arranged in a single-master multi-slave mode. At least two operating systems operate based on the processor 1502. At least two operating systems communicate via the first bus 1506. At least two operating systems realize control over the hardware controller through the second bus 1508.

[0187] Here, the chip may be a BMC chip, the processor may be a multi-core processor, the hardware controller may be used to control external devices connected to corresponding external interfaces, the first bus is arranged in a multi-master multi-slave mode, and it may be a bus used for communication between multiple processor cores of the processor. For example, AHB (Advanced High Performance Bus) may be mentioned. The second bus is arranged in a single-master multi-slave mode, and it may be a bus used for control between hardware controllers by the processor. For example, APB (Advanced Peripheral Bus) may be mentioned. The bandwidth of the first bus is higher than that of the second bus.

[0188] The embedded system may include at least two operating systems. The at least two operating systems operate based on a processor, and the processing resources of the processor are dynamically allocated to the at least two operating systems. The processing resources of the processor include processor cores. The at least two operating systems communicate via a first bus, and the at least two operating systems realize control over a hardware controller through a second bus.

[0189] Optionally, the hardware controller may include one or more types, and may include, but is not limited to, controllers corresponding to at least one of the following chip peripheral devices: I2C, USB (Universal Serial Bus), UART, ADC (Analog to Digital Converter), JTAG (Joint Test Action Group), RTC (Real_Time Clock), GPIO (General Purpose Input / Output), WDT (Watch Dog Timer), Virtual UART, Super I / O, SGPIO (Serial General Purpose Input / Output), PWM (Pulse Width Modulation), FanTach (fan speed adjustment), Timer (clock), PECI (Platform Environment Control Interface), MailBox. Furthermore, other types of controllers may also be included. The external interface may include one or more types, and may include, but is not limited to, external interfaces corresponding to any of the above controllers.

[0190] The first bus mentioned above is arranged in a multi-master multi-slave mode, which may be a bus used for communication between multiple processor cores of a processor. For example, AHB (Advanced High Performance Bus) may be mentioned. The second bus is arranged in a single-master multi-slave mode, which may be a bus used for control between hardware controllers by a processor. For example, APB (Advanced Peripheral Bus) may be mentioned. The bandwidth of the first bus is higher than that of the second bus. This will be described below. The first bus is already defined in AMBA2. The first bus is mainly used as a system high-speed bus at first, is applicable to a high-performance and low-power consumption system design, and is mainly used for connection between high-performance modules (such as CPU, DMA, and DSP, etc.), and is used as the system-on-chip bus of the SoC. In the AMBA protocol, AHB is mainly for system-level high-bandwidth high-performance system interconnection design. It includes several characteristics such as single clock edge operation, non-tri-state implementation method, support for burst transfer, support for hierarchical transfer, an interconnection mode that supports multi-master and multi-slave, the bus width can be set from 32 bits to 128 bits, and support for byte, nibble, and word transfer. The AHB system is composed of three parts: a master module, a slave module, and an infrastructure. All transmissions in the entire first bus are sent by the master module, and the slave module is responsible for the response. The infrastructure is composed of an arbiter, a multiplexer from the master module to the slave module, a multiplexer from the slave module to the master module, a decoder, a dummy slave module, and a dummy master module.

[0191] APB is mainly used for connections between low-bandwidth peripheral devices. Examples include UART, 1284, etc. Its bus architecture is different from AHB that supports multiple master modules. The only master module in APB is the APB bridge. Its features include the following.

[0192] (1) It can operate at high frequencies. (2) It has a simple protocol without complex sequences. (3) It is a synchronous bus, and all transactions (read and write operations) on the bus depend on the rising edge of the clock. (4) It is a single master multi-slave. Generally, APB is applied to the first bus system, and the transaction is converted between the first bus systems through the AHB-APB Bridge. At this time, the Bridgre is the master of APB, and all other peripheral devices are slaves. (5) It has a simple interface. Compared with AXI and AHB, the interface is relatively simple. (6) It has low power consumption. (7) It can be connected to multiple types of peripheral devices such as I2C, SPI, Timer, Keypad, and UART.

[0193] In one selectable embodiment, in the multi-master multi-slave mode of AHB, the Master first sends a message transmission request to the arbiter. The arbiter determines the appropriate permission for the master to obtain bus access. After the master obtains the permission, it sends data and control signals to the arbiter. The arbiter determines the corresponding slave path through address parsing and then sends the request to the corresponding destination. Similarly, the response data is parsed by the Decoder and then returned to the corresponding master. Through such a multiplexing mechanism, multiple-to-multiple access is realized.

[0194] In one selectable embodiment, in the single-master multi-slave mode of the APB, generally, the APB is applied to the first bus system, and the transaction is converted between the first bus systems via the AHB-APB Bridge. At this time, the Bridgre is the master of the APB, and all other peripheral devices are slaves. The data request can only be sent from the Master to the slave. After receiving the request, the slave returns the corresponding response data to the master. This process can achieve a one-to-multiple access, and the access is not related to the arbiter and decoder parsing operations on the first bus.

[0195] In addition, the first bus further has high-bandwidth characteristics and is used for the interconnection between high-performance modules (such as CPU, DMA, etc.) in the system. The APB bus has a relatively low bandwidth and is used for the connection between peripheral devices (such as UART, I2C, etc.) in the system. The logic circuit and bus protocol of the first bus are complex, while the bus interface circuit and bus protocol are relatively simple.

[0196] Optionally, when the RTOS occupies the CPU resources when waking up from sleep, after the RTOS goes to sleep, it does not completely occupy the CPU resources. When it wakes up (for example, an interrupt occurs in a peripheral device or wake-up timer to trigger the wake-up operation), it reacquires the control right of core 0 through an inter-core interrupt. During the period from the above sleep state to the reacquisition of core control right, the participation of the core is not required in the RTOS system.

[0197] Here, in this embodiment, the provided embedded system can be used to realize the generation of hardware interface signals. The two operating systems included in the embedded system may be the first system and the second system. In this embodiment, the first system obtains a request instruction, determines a plurality of logical bit information corresponding to the request instruction, and is also used to generate a hardware interface signal corresponding to the request instruction based on the plurality of logical bit information and the timer.

[0198] Optionally, the first system is used to determine a reload value and an initial match value corresponding to a timer based on a plurality of logical bit information, and the second system is used to generate a hardware interface signal corresponding to a request command based on the reload value and the initial match value. Optionally, the first system is used to obtain an operation time corresponding to each logical bit information, the first system is used to determine a reload value based on the operation time, the first system determines one initial match value corresponding to the timer based on the logical bit of each logical bit information, and is used to obtain a plurality of initial match values corresponding to the timer, where the initial match value corresponding to each logical bit information is used to control the logical bit of the logical bit information to 0 or 1 by controlling the time when the logical bit information is at a high level.

[0199] Optionally, the first system sequentially generates hardware interface sub-signals corresponding to each logical bit information based on the reload value and the initial match value corresponding to each logical bit information according to the order before and after among the plurality of logical bit information corresponding to the request command, and is used to obtain the hardware interface signal. Optionally, the first system is used to perform a decrement operation on the reload value corresponding to each logical bit information based on a timer. Before the reload value corresponding to each logical bit information is decremented to the initial match value corresponding to the logical bit information, the first system is used to output a first signal corresponding to the logical bit information. Here, the first signal is a high-level signal. After the reload value corresponding to each logical bit information is decremented to the initial match value corresponding to the logical bit information, the first system is used to output a second signal corresponding to the logical bit information. The second signal is a low-level signal. When the reload value corresponding to each logical bit information is decremented to 0, the first system determines the generation of the hardware interface sub-signal corresponding to the logical bit information and is used to obtain the hardware interface sub-signal corresponding to each logical bit information. Here, the hardware interface sub-signal corresponding to each logical bit information is composed of the first signal and the second signal corresponding to the logical bit information.

[0200] Optionally, when the reload value corresponding to each logical bit information is decremented to the initial match value corresponding to the logical bit information, the first system is used to trigger a first interrupt corresponding to the logical bit information. When the reload value corresponding to each logical bit information is decremented to 0, the first system is used to trigger a second interrupt corresponding to the logical bit information.

[0201] Optionally, each time the first system triggers one of the first interrupt or the second interrupt, it is used to perform an interrupt count once. The first system is used to determine the field in which the current signal conversion process in the request command is being performed based on the interrupt count. Here, the signal conversion process is used to generate the hardware interface sub-signal corresponding to the logical bit information corresponding to each field in the request command.

[0202] Optionally, the first system is used to obtain the number of bytes corresponding to each field in the request instruction, and the first system is used to determine the number of logical bit information corresponding to the request instruction based on the number of bytes. Here, each byte corresponding to the request instruction corresponds to one piece of logical bit information. The first system is used to determine the number of interrupts corresponding to the request instruction based on the number of logical bit information. Here, the number of interrupts corresponding to the request instruction is twice the number of logical bit information. The first system is used to determine the field in the request instruction where the current signal conversion process is being performed based on the number of interrupts and the interrupt count.

[0203] Optionally, the first system is used to determine the logical bit information that is currently being converted into the hardware interface sub-signal based on the number of interrupts and the interrupt count. The first system is used to determine the byte corresponding to the logical bit information that is currently being converted into the hardware interface sub-signal as the target byte. The first system is used to determine the field corresponding to the target byte as the field in the request instruction where the current signal conversion process is being performed.

[0204] Optionally, the data structure of the request data corresponding to the request instruction is the first data structure. Here, the first data structure includes at least a device address, a write length, a read length, an instruction code, and request parameters. The device address is used to characterize the address of the target device. The target device is a device that generates response data based on the hardware interface signal. The instruction code is used to distinguish different request instructions. The write length is used to characterize the number of bytes from the instruction code to the request data. The read length is used to characterize the number of bytes including the completion code and the read data in the request data. The request parameters are used to characterize the parameters of the request instruction.

[0205] Optionally, the embedded system further includes a second system, where both the second system and the first system operate on a processor. The second system is used to generate request data, and the first system is used to obtain the request data when it detects a first request triggered by the second system. Here, the service response speed of the second system is smaller than that of the first system, and the first system analyzes the request data and is used to obtain a request instruction.

[0206] Optionally, the second system stores the request data in a target memory and is used to trigger the first request after the storage of the request data is completed. Here, the first request is used to notify the first system to read the request data from the target memory, and the target memory is a memory accessible by both the first system and the second system.

[0207] Optionally, the first system is used to convert the voltage of a hardware interface signal and obtain a target hardware interface signal. Optionally, the first system inputs the hardware interface signal into a voltage conversion device and is used to obtain the target hardware interface signal output from the voltage conversion device.

[0208] Optionally, the first system is used to receive response data corresponding to the hardware interface signal. Here, the transmission format of the response data is the same as that of the hardware interface signal, and the first system is used to adjust the data structure of the response data to a second data structure. Optionally, the second data structure includes at least a first calibration value, a second calibration value, and response valid data, where the first calibration value is used to characterize the calibration value in the request data, the second calibration value is used to characterize the calibration value in the response data, and the response valid data is used to characterize the data for explaining the completion code and the state of the target device in the response data, and the target device is a device that generates response data based on the hardware interface signal.

[0209] Optionally, the first system is used to trigger a second request, where the second request is used to notify the second system to read the response data. Optionally, the hardware interface signal is any one of a PECI signal, an HDMI signal, an SGMII signal, an RGMII signal, a GPIO signal, and an SPI signal.

[0210] In an alternative embodiment, the first system and the second system described above can operate on different processor cores of the processor. Therefore, the communication between the first system and the second system is in the form of inter-core communication. As shown in FIG. 16, an inter-core communication method is provided and implemented by the embedded system of the above embodiment. Here, the first operating system in FIG. 16 may correspond to the first system, and the second operating system may correspond to the second system, and includes the following steps S1602 to S1606.

[0211] In step S1602, the first operating system transmits the target data to the target virtual channel in the processor memory, where the first operating system and the second operating system operate on the processor. Specifically, the first operating system and the second operating system may be real-time operating systems or non-real-time operating systems. The first operating system and the second operating system may be single-core operating systems or multi-core operating systems. The target data is the data to be transmitted, and the target virtual channel is the free storage space in the memory. The first operating system transmitting the target data to the target virtual channel in the processor memory refers to the CPU core of the first operating system writing the data to be transmitted to the target virtual channel.

[0212] In step S1604, an interrupt notification message is sent to the second operating system. Specifically, the CPU core of the first operating system sends an interrupt notification message to the CPU core of the second operating system. The interrupt notification message can carry the address of the target virtual channel and is used to notify the second operating system to obtain the target data from the target virtual channel. The interrupt notification message may be a software trigger or a hardware trigger.

[0213] In step S1606, the second operating system responds to the interrupt notification message and obtains the target data from the target virtual channel in the memory. Specifically, the CPU core of the second operating system responds to the interrupt notification message, analyzes the address of the target virtual channel from the interrupt notification message, further locates the target virtual channel in the memory based on the analyzed address, obtains the target data from the target virtual channel, and realizes the data exchange between the first operating system and the second operating system.

[0214] In the above steps, when multiple operating systems running on a processor need to transmit data to each other, the first operating system that transmits data sends the target data to a target virtual channel in the processor memory, and sends an interrupt notification message to the second operating system. The second operating system that receives the data responds to the interrupt notification message and acquires the target data from the target virtual channel, thereby solving the problems of resource waste and high dependence on the operating system during the inter-core communication process, and achieving the effect of reducing resource waste and dependence on the operating system during the inter-core communication process.

[0215] Also, FIG. 17 is a flowchart 1 of a selectable communication method according to an embodiment of the present application. As shown in FIG. 17, specifically, it is a process in which a non-real-time operating system transmits data to a real-time operating system. First, the application layer of the non-real-time operating system fills the data to be transmitted in a corresponding format, and then generates a device file ipidev at the / dev path of the system. When the application layer needs to read and write data from the driver layer, it first turns on the device / dev / ipidev using the open function attached to the system, and uses the write function to transmit the data to be transmitted from the application layer of the non-real-time operating system to the driver layer. The driver layer of the non-real-time operating system places the data in the shared memory, and then triggers a software interrupt to notify another core's real-time operating system to read the data.

[0216] Specifically, the shared memory area is divided into multiple memory channels, each memory channel corresponds to one channel structure (IpiHeader), and the structure data is used to record the relevant information of the memory channel. The driver layer of the non-real-time operating system first uses the interface GetEmptyChannel based on the size of the data to be sent to find, in all channels, a memory channel that meets two conditions: one is that the empty flag Flag in the channel structure IpiHeader is not equal to 0xA5A5A5A5, and the other is that the channel size ChannelSize in the channel structure IpiHeader is larger than the size of the data to be sent. After finding an empty channel that meets the requirements, the channel is set to not empty, that is, the empty flag in the channel structure IpiHeader is set to 0xA5A5A5A5. Subsequently, the data to be sent is copied to the empty channel, and then a software interrupt is triggered to notify the real-time operating system of other cores.

[0217] In one exemplary embodiment, the real-time operating system receives an interrupt, triggers the corresponding interrupt processing function, the interrupt processing function sends a task notification to wake up the corresponding task, and the task reads and analyzes the data from the shared memory. Specifically, the task first uses the interface GetNoEmptyChannel to find, in all channels, a channel that meets three conditions: one is that the empty flag in the channel structure IpiHeader is equal to 0xA5A5A5A5, the second is that the TargetId in the channel structure is equal to the ID of the current CPU, and the third is that the TargetId in the channel structure is not equal to the SrcId. After finding a non-empty channel that meets the requirements, the data of the non-empty channel is analyzed, and the specific function is completed based on NetFn and Cmd in the channel structure IpiHeader. Finally, the channel is set to empty, that is, the empty flag in the channel structure is set to 0.

[0218] FIG. 18 is a flowchart 2 of a selectable communication method according to an embodiment of the present application. As shown in FIG. 18, specifically, it is a process in which a real-time operating system transmits data to a non-real-time operating system. First, if there is data to be transmitted on the real-time operating system side, it finds an empty channel from the shared sub-memory. When it finds an empty channel, it sets this channel as empty, copies the data to be transmitted to the found empty channel, then generates a software interrupt and notifies the non-real-time operating system side. The non-real-time operating system side calls the corresponding interrupt processing function. The interrupt processing function scans the IpiHeader structures of all channels, determines which application layer program to send a signal to based on the NetFn and Cmd fields in the structure, and sends the corresponding channel ID to the application program. It should be noted that when the system is initialized, the application layer program for inter-core communication needs to register the NetFn, Cmd, and the PID corresponding to the application layer program with the driver. After receiving the signal, the application layer calls the corresponding processing function, turns on the device / dev / ipidev to read the data. The driver finds the corresponding data in the shared memory based on the channel ID, returns the data and the data length to the application layer, and sets this channel as empty, that is, sets the empty flag in the channel structure to 0.

[0219] The present invention provides a method for inter-core communication in the multi-core multi-operating system of this embodiment. For data exchange at the physical layer, the shared memory method is used. In addition, virtual channels are added to manage the shared memory. When the transmitting CPU core places the data to be transmitted in the shared memory in a pre-agreed protocol format, a software interrupt is triggered to notify the receiving CPU core to read the data. Subsequently, the data is analyzed in the pre-agreed protocol format. After the receiving CPU core reads the data, it supports the option of whether to return a response to the transmitting CPU core or not. Inter-core communication realizes inter-core communication in the multi-core multi-operating system by using the shared memory and software interrupt methods. The method of using virtual channels to manage the shared memory and the format of the virtual channel structure are used. Without using additional components, the development is simple, system resources are saved, and only general-purpose functions such as operating system tasks and semaphores are used, greatly reducing the dependence on the operating system.

[0220] As can be clearly understood by those skilled in the art from the description of the above embodiments, the method according to the above embodiments can be realized by adding a general-purpose hardware platform required for software. Of course, it can also be realized by hardware, but the former is often a more preferred embodiment. Based on such an understanding, the technical solution of the present application can be embodied in the form of a software product in essence or in the part that contributes to the prior art. The computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a plurality of instructions for causing a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the method of each embodiment of the present application.

[0221] To achieve the above object, according to another aspect of the present application, there is further provided a chip including at least one of a programmable logic circuit and executable instructions, which operates in an electronic device and is used to execute the steps in any of the embodiments of the above method. Embodiments of the present application further provide a BMC chip, where the BMC chip includes a memory unit and a processing unit connected to the memory unit. The memory unit is used to store a program, and the processing unit is used to execute the steps in any of the embodiments of the above method by executing the program.

[0222] For example, an example of the BMC chip may be as shown in FIG. 19. The hardware of the BMC chip may include, but is not limited to, an SOC sub-module and a BMC out-of-band sub-module. The SOC sub-module mainly includes an ARM core (ARM Core 1, ARM Core 2... ARM Core X), which may include, but is not limited to, a DDR (Double Data Rate) 4 controller (memory controller), a MAC (Media Access Control Address) controller (network controller), an SD (Secure Digital) / eMMC (Embedded Multi Media Card) controller (memory controller), a PCIe RC (Root Complex) controller, an SRAM (Static Random-Access Memory), and an SPI controller.

[0223] The above core and each controller are interconnected via a first bus to realize the interaction between the core and each controller. Also, the ARM cores are connected to the first bus (for example, they may be connected via an AXI (Advanced eXtensible Interface) bridge), and communication between the cores is realized by the first bus. Also, the interconnection and exchange between the first bus and the second bus are realized in the SOC sub-module (for example, realized by the conversion of an APB bridge), thus providing a physical channel for the SOC sub-module to access the peripheral devices on the second bus.

[0224] The DDR4 controller can be connected to other components or devices via a DDR4 PHY (Physical Layer) interface, the MAC controller is connected to other components or devices via an RGMII (Reduced Gigabit Media Independent Interface), the SD card eMMC controller is connected to other components or devices via an SD interface, and the PCIe RC controller is connected to other components or devices via a PCIe PHY interface.

[0225] The BMC outband sub-module mainly includes controllers corresponding to peripheral devices of the chip such as PWM, GPIO, FanTech (fan speed adjustment), mailbox, etc. These controllers can realize outband management functions such as PECI communication with the BMC (for example, simulating PECI using GPIO) and fan adjustment control. As can be seen from FIG. 19, the BMC outband sub-module can realize the interaction with the SOC sub-module via the second bus, but is not limited thereto.

[0226] The BMC chip realizes the interconnection between the ARM core, memory unit, and controller hardware resources within the chip through the AHB and a second bus. The dynamic equalization scheduling of the processor resources mainly concerns the scheduling of the ARM core resources of the BMC chip, and the inter-core communication refers to the communication carried out between the ARM cores. Taking the example of the Linux system preempting the RTOS system core, the Linux system first sends an inter-core interrupt (interrupt number 9) from a core with cores 2 to N to core 1 via the first bus on the chip. If the RTOS system is in the idle state and permits preemption at this time, core 1 returns an inter-core interrupt (interrupt number 10) via the first bus, releases the external controller resources (such as PWM / PECI) currently mapped to core 1, the Linux system receives the inter-core interrupt 10, starts the preemption flow, adds core 1 to the Linux SMP scheduling, and can obtain the control right of the PWM / PECI peripheral device and control it via the second bus.

[0227] On the one hand, at least two operating systems include a first operating system and a second operating system. Here, the chip loads a communication value onto the first bus, and the first bus transmits a communication signal with the communication value to a communication register corresponding to the second operating system to realize the communication between the first operating system and the second operating system. Here, the communication value is used to indicate the communication content between the first operating system and the second operating system.

[0228] On the other hand, the chip loads a control value onto the second bus, and the second bus transmits a control signal with the control value to a register corresponding to the hardware controller to realize the control of the hardware controller by the operating system. Here, the control value is used to indicate the control content of the hardware controller by the operating system.

[0229] The first bus mentioned above is arranged in a multi-master multi-slave mode, which may be a bus used for communication between multiple processor cores of a processor. For example, an AHB (Advanced High Performance Bus) may be mentioned. The second bus is arranged in a single-master multi-slave mode, which may be a bus used for control between hardware controllers by a processor. For example, an APB (Advanced Peripheral Bus) may be mentioned. The bandwidth of the first bus is higher than that of the second bus. This will be described below.

[0230] The AHB bus has already been defined in AMBA2. The AHB bus is mainly used as a system high-speed bus at first, and is applicable to a high-performance and low-power consumption system design. It is mainly used for the connection between high-performance modules (such as CPU, DMA, and DSP, etc.), and is used as the system-on-chip bus of the SoC. In the AMBA protocol, the AHB is mainly for the system-level high-bandwidth high-performance system interconnection design. It includes several characteristics such as single clock edge operation, non-tri-state implementation method, support for burst transfer, support for hierarchical transfer, an interconnection mode that supports multi-master and multi-slave, a configurable bus width of 32 bits to 128 bits, and support for byte, nibble, and word transfer. The AHB system is composed of three parts: a master module, a slave module, and an infrastructure. All transmissions in the entire AHB bus are sent by the master module, and the slave module is responsible for the response. The infrastructure is composed of an arbiter, a multiplexer from the master module to the slave module, a multiplexer from the slave module to the master module, a decoder, a dummy slave module, and a dummy master module.

[0231] APB is mainly used for connections between low-bandwidth peripheral devices. For example, UART, 1284, etc. are included. Its bus architecture is different from AHB that supports multiple master modules. The only master module in APB is the APB bridge. Its features include the following.

[0232] (1) It can operate at high frequencies. (2) It has a simple protocol without complex sequences. (3) It is a synchronous bus, and all transactions (read and write operations) on the bus depend on the rising edge of the clock. (4) It is a single-master multi-slave. Generally, APB is connected to the AHB bus system, and the transaction is converted between the AHB bus systems through the AHB-APB Bridge. At this time, the Bridgre is the master of APB, and all other peripheral devices are slaves. (5) It has a simple interface, and the interface is relatively simple compared to AXI and AHB. (6) It has low power consumption. (7) It can be connected to multiple types of peripheral devices such as I2C, SPI, Timer, Keypad, and UART.

[0233] In one selectable embodiment, in the multi-master multi-slave mode of AHB, the Master first sends a message transmission request to the arbiter. The arbiter determines the appropriate authority for the master to obtain bus access. After the master obtains the authority, it sends data and control signals to the arbiter. The arbiter determines the corresponding slave path through address parsing and then sends the request to the corresponding destination. Similarly, the response data is parsed by the Decoder and then returned to the corresponding master. Through such a multiplexing mechanism, multiple-to-multiple access is realized.

[0234] In one selectable embodiment, in the single-master multi-slave mode of the APB, generally, the APB is applied to the AHB bus system, and the transaction is converted between the AHB bus systems through the AHB-APB Bridge. At this time, the Bridgre is the master of the APB, and all other peripheral devices are slaves. The data request can only be sent from the Master to the slave. After receiving the request, the slave returns the corresponding response data to the master. This process can realize a one-to-multiple access, and the access is not related to the arbiter and decoder parsing operations in the AHB bus.

[0235] In addition, the AHB bus further has high-bandwidth characteristics and is used for the interconnection between high-performance modules (such as CPU, DMA, etc.) in the system. The APB bus has a relatively low bandwidth and is used for the connection between peripheral devices (such as UART, I2C, etc.) in the system. The AHB bus logic circuit and bus protocol are complex, while the bus interface circuit and bus protocol are relatively simple.

[0236] The operating system controls the hardware controller by accessing (e.g., performing read and write operations) the registers of each hardware controller. The way the operating system accesses the registers of the hardware controller may be, but is not limited to, reading or writing the register addresses of each hardware controller. The addresses of these registers may or may not be unique and determined during chip design. For example, when the operating system writes a specific value (i.e., the above communication value or control value) to a specific address (i.e., the above communication register or the register corresponding to the hardware controller), a specific function (e.g., the communication function between the above operating systems or the control function of the operating system on the hardware controller) can be realized. That is, different functions correspond to different control values, and the correspondence between the functions of the hardware controller and the control values is maintained in the chip. For example, control value 00 represents accelerating the air conditioner by one level, and control value 01 represents decelerating the air conditioner by one level, etc.

[0237] Interactions such as communication and control between each operating system and between the operating system and the hardware controller may be carried out via a bus, but are not limited to this. The read and write operations of the operating system on the registers of each hardware controller are ultimately converted into control signals for the hardware controller by the first bus (or the second bus). The conversion operation of this part and the control process of the hardware controller by the first bus (or the second bus) may or may not be automatically realized by the hardware inside the chip. The realization process follows the bus specification. Here, in the operation process of the first bus (or the second bus), physical signals related to the bus protocol can be transmitted and controlled, while valid data can be transmitted to each hardware controller via its physical data channel.

[0238] With the above-mentioned embedded system, the first operating system and the second operating system operate based on a processor, and communication between the operating systems and control of the hardware controller are realized by buses with different functions. Since both the first operating system and the second operating system operate based on the same processor, an increase and arrangement of hardware devices are avoided, the system cost is reduced, the processor resources are rationally utilized to support the operation between systems, and thus, the technical problem of low operating efficiency of the operating system can be solved, and the technical effect of improving the operating efficiency of the operating system can be achieved.

[0239] The embodiment of the present application further provides a motherboard, where the motherboard includes at least one processor and at least one storage used for storing at least one program. When the at least one program is executed by the at least one processor, the at least one processor is caused to execute the steps in any of the embodiments of the above method.

[0240] The embodiment of the present application further provides a server including a processor, a communication interface, a storage, and a communication bus. Here, the processor, the communication interface, and the storage realize communication with each other via the communication bus. The storage is used for storing a computer program. When the processor executes the program stored in the storage, the steps in any of the embodiments of the above method are realized and used to achieve the same technical effect.

[0241] The communication bus of the above server may be a PCI (Peripheral Component Interconnect) bus, an EISA (Extended Industry Standard Architecture) bus, or the like. The communication bus can be divided into an address bus, a data bus, a control bus, and the like. The communication interface is used for communication between the above server and other devices.

[0242] The storage may include a RAM (Random Access Memory), and may include, for example, an NVM (Non-Volatile Memory) such as at least one magnetic disk memory. Optionally, the storage may be at least one storage device located away from the processor. The above processor may be a general-purpose processor, including a CPU (Central Processing Unit), an NP (Network Processor), etc., and may be a DSP (Digital Signal Processing), an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or other programmable logic devices, discrete gates, or transistor logic devices, discrete hardware components.

[0243] Regarding the server, the server has at least the characteristics of high extensibility and high stability. Here, since it is impossible for the enterprise network not to change over a long period of time, in today's network informatization, without a certain degree of extensibility in the server, it may affect the future development of the enterprise. Therefore, extensibility becomes one of the most basic characteristics of the server. Extensibility includes not only hardware extensibility but also software extensibility. Since the functions of the server are very complex compared to computers, not only the hardware configuration but also the software configuration is important. To achieve more functions, comprehensive software support is essential. In addition, since the server needs to process a large amount of data to support the continuous operation of the service, the server has an important feature of high stability. If the data transmission of the server cannot operate stably, it will surely have a great impact on the implementation of the service.

[0244] The solution of the present application utilizes the characteristic of high expandability of the server, introduces a dual software system of a first system and a second system to generate a hardware interface signal, adjusts the transmission voltage of the hardware interface signal respectively, and introduces hardware devices such as GPLD and BMC chips to monitor the operating state of other devices inside the server. In addition, in the present application, a method of generating a hardware interface signal corresponding to a request command by the first system is adopted. First, the first system obtains the request command, then determines a plurality of logical bit information corresponding to the request command, and finally generates a hardware interface signal corresponding to the request command based on the plurality of logical bit information and a timer. As can be seen from the above content, the present application generates a hardware interface signal corresponding to a request command by the first system, thereby realizing the technical effect of simulating and generating a hardware interface signal using a software method, and further achieving the purpose that the chip itself does not need to have a hardware logic design of the related hardware interface signal, which can not only reduce the design difficulty of the chip, but also further reduce the design cost of the chip. The present application achieves the purpose of generating a hardware interface signal using a software system without the need to perform a hardware logic design of the hardware interface signal for the chip, thereby reducing the design difficulty of the chip, and further solving the technical problem that the design cost of the chip is high because the chip itself needs to have a hardware logic design of the controller in the prior art.

[0245] In addition, when introducing a dual software system of a first system and a second system, the stability of the server can be ensured. Since the service response speed of the second system is slower than that of the first system, when generating a hardware interface signal using the first system with a faster service response speed, it can be guaranteed that the generation of the hardware interface signal is not interrupted, thereby ensuring that the hardware interface signal can be continuously and stably output.

[0246] As can be understood by those skilled in the art, all or part of the steps in the various methods of the above embodiments may be completed by instructing the hardware related to the terminal device by a program, and the program may be stored in a computer-readable storage medium. The storage medium may include a flash memory disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc.

[0247] The numbers of the above embodiments of the present application are only for the purpose of illustration and do not represent the superiority or inferiority of the embodiments. In the above embodiments of the present application, the descriptions of each embodiment have their respective focuses. For parts not detailed in a certain embodiment, reference may be made to the related descriptions of other embodiments.

[0248] In some embodiments provided in this application, it should be understood that the disclosed technical content may be implemented in other ways. Here, the embodiments of the devices described above are merely exemplary. For example, the division of units is merely a division of logical functions, and when actually implemented, other division methods may be used. For example, a plurality of units or components may be combined, integrated into another system, or some features may be ignored or not executed. On the other hand, the couplings, direct couplings, or communicable connections shown or discussed may be indirect couplings or communicable connections through some interfaces, units, or modules, and may be electrical or other forms.

[0249] The units described as separation members may or may not be physically separated, and the members shown as units may or may not be physical units, that is, they may be located in one place or distributed among a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution means of this embodiment. In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, each unit may exist physically alone, or two or more units may be integrated into one unit. The above integrated units may be implemented in the form of hardware or in the form of software functional units.

[0250] When the integrated unit is realized in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method of each embodiment of the present application. The above-mentioned storage medium includes various media capable of storing program codes, such as a USB disk, a read-only memory (ROM), a random access memory (RAM), a portable hard disk, a magnetic disk, or an optical disk.

[0251] The above are only preferred embodiments of the present application, and it should be pointed out that those skilled in the art can make some improvements and modifications without departing from the principle of the present application, and these improvements and modifications should also be regarded as within the protection scope of the present application.

Claims

1. The step of obtaining a request command by a first system; The step of determining a plurality of logical bit information corresponding to the request command; A method for generating a hardware interface signal, comprising: generating a hardware interface signal corresponding to the request command based on the plurality of logical bit information and a timer.

2. The step of generating a hardware interface signal corresponding to the request command based on the plurality of logical bit information and a timer includes: The step of determining a reload value and a first match value corresponding to the timer based on the plurality of logical bit information; The method according to claim 1, further comprising: generating a hardware interface signal corresponding to the request command based on the reload value and the first match value.

3. The step of determining a reload value and a first match value corresponding to a timer based on the plurality of logical bit information includes: The step of obtaining an operation time corresponding to each logical bit information; The step of determining the reload value based on the operation time; The step of determining one first match value corresponding to the timer based on the logical bits of each logical bit information, and obtaining a plurality of first match values corresponding to the timer, wherein the first match value corresponding to each logical bit information is used to control the logical bit of the logical bit information to 0 or 1 by controlling the time when the logical bit information is at a high level. The method according to claim 2.

4. The step of generating a hardware interface signal corresponding to the request command based on the reload value and the first match value includes: Sequentially generating a hardware interface sub-signal corresponding to each logical bit information based on the reload value and the first match value corresponding to each logical bit information according to the order before and after among the plurality of logical bit information corresponding to the request command, and obtaining the hardware interface signal. The method according to claim 3.

5. The step of sequentially generating a hardware interface sub-signal corresponding to each logical bit information based on the reload value and the first match value corresponding to each logical bit information includes: The step of performing a decrement operation on the reload value corresponding to each logical bit information based on the timer; Before the reload value corresponding to each piece of the logical bit information is decremented to the initial match value corresponding to the logical bit information, a step of outputting, by the first system, a first signal corresponding to the logical bit information, wherein the first signal is a high-level signal, After the reload value corresponding to each piece of the logical bit information is decremented to the initial match value corresponding to the logical bit information, a step of outputting, by the first system, a second signal corresponding to the logical bit information, wherein the second signal is a low-level signal, When the reload value corresponding to each piece of the logical bit information is decremented to 0, determining generation of a hardware interface sub-signal corresponding to the logical bit information and obtaining the hardware interface sub-signal corresponding to each piece of the logical bit information, wherein the hardware interface sub-signal corresponding to each piece of the logical bit information is constituted by the first signal and the second signal corresponding to the logical bit information, the method according to claim 4 comprising the steps.

6. When the reload value corresponding to each piece of the logical bit information is decremented to the initial match value corresponding to the logical bit information, triggering a first interrupt corresponding to the logical bit information, When the reload value corresponding to each piece of the logical bit information is decremented to 0, triggering a second interrupt corresponding to the logical bit information, the method according to claim 5 further comprising the steps.

7. In a process of sequentially generating a hardware interface sub-signal corresponding to each piece of the logical bit information based on the reload value and the initial match value corresponding to each piece of the logical bit information, Each time one of the first interrupt or the second interrupt is triggered, performing an interrupt count once, Determining, based on the interrupt count, a field in which the current signal conversion process in the request command is being performed, wherein the signal conversion process is used to generate a hardware interface sub-signal corresponding to the logical bit information corresponding to each field in the request command, the method according to claim 6 further comprising the steps.

8. The step of determining, based on the interrupt count, a field in which the current signal conversion process in the request command is being performed is, The step of obtaining the number of bytes corresponding to each field in the request command; The step of determining the number of logical bit information corresponding to the request command based on the number of bytes, wherein each byte corresponding to the request command corresponds to one logical bit information; The step of determining the number of interrupts corresponding to the request command based on the number of logical bit information, wherein the number of interrupts corresponding to the request command is twice the number of logical bit information; The method according to claim 7, further comprising the step of determining a field in the request command that is currently performing signal conversion processing based on the number of interrupts and the interrupt count.

9. The step of determining a field in the request command that is currently performing signal conversion processing based on the number of interrupts and the interrupt count includes: The step of determining logical bit information that is currently being converted into the hardware interface sub-signal based on the number of interrupts and the interrupt count; The step of determining a byte corresponding to the logical bit information that is currently being converted into the hardware interface sub-signal as a target byte; The method according to claim 8, further comprising the step of determining a field corresponding to the target byte as a field in the request command that is currently performing signal conversion processing.

10. The data structure of the request data corresponding to the request command is a first data structure, where the first data structure includes at least a device address, a write length, a read length, an instruction code, and request parameters. The device address is used to characterize the address of the target device, and the target device is a device that generates response data based on the hardware interface signal. The instruction code is used to distinguish different request commands. The write length is used to characterize the number of bytes from the instruction code to the request data. The read length is used to characterize the number of bytes including the completion code and the read data in the request data. The request parameters are used to characterize the parameters of the request command. The method according to claim 1.

11. The step of obtaining a request command by a first system is: When the first system detects the first request triggered by the second system, the step of obtaining the request data, wherein the first system and the second system operate on the same processor, the request data is generated by the second system, and the service response speed of the second system is slower than that of the first system; The method according to claim 10, further comprising the step of analyzing the request data to obtain the request instruction. **Claim 12** Before obtaining the request data, The step of storing the request data in a target memory by the second system and triggering the first request by the second system after the storage of the request data is completed, wherein the first request is used to notify the first system to read the request data from the target memory, and the target memory is a memory accessible by both the first system and the second system. The method according to claim 11. **Claim 13** After generating the hardware interface signal corresponding to the request instruction based on the logical bit information and the timer, The method according to claim 1, further comprising the step of converting the voltage of the hardware interface signal to obtain a target hardware interface signal. **Claim 14** The step of converting the voltage of the hardware interface signal to obtain a target hardware interface signal comprises The method according to claim 13, comprising the step of inputting the hardware interface signal into a voltage conversion device and obtaining the target hardware interface signal output from the voltage conversion device. **Claim 15** The step of receiving, by the first system, response data corresponding to the hardware interface signal, wherein the transmission format of the response data is the same as that of the hardware interface signal; The method according to claim 1, further comprising the step of adjusting the data structure of the response data to a second data structure. **Claim 16** The method according to claim 15, wherein the second data structure includes at least a first calibration value, a second calibration value, and response valid data, where the first calibration value is used to characterize the calibration value in the request data, the second calibration value is used to characterize the calibration value in the response data, the response valid data is used to characterize data for explaining the completion code and the state of the target device in the response data, and the target device is a device that generates the response data based on the hardware interface signal.

17. After adjusting the data structure of the response data to a second data structure, The method according to claim 16, further comprising the step of triggering a second request by the first system, wherein the second request is used to notify the second system to read the response data.

18. The method according to claim 1, wherein the hardware interface signal is any one of a PECI signal, an HDMI signal, an SGMII signal, an RGMII signal, a GPIO signal, and an SPI signal.

19. An embedded system including a first system and a processor, wherein the first system operates on the processor, The first system obtains a request instruction, determines a plurality of logical bit information corresponding to the request instruction, and is used to generate a hardware interface signal corresponding to the request instruction based on the plurality of logical bit information and a timer.

20. The first system is used to determine a reload value and a first match value corresponding to the timer based on the plurality of logical bit information, The embedded system according to claim 19, wherein the first system is used to generate a hardware interface signal corresponding to the request instruction based on the reload value and the first match value.

21. The first system is used to obtain an operation time corresponding to each logical bit information, The first system is used to determine the reload value based on the operation time. The first system determines one initial match value corresponding to the timer based on the logical bits of the respective logical bit information, and is used to obtain a plurality of initial match values corresponding to the timer. Here, the initial match value corresponding to each logical bit information is used to control the logical bit of the logical bit information to 0 or 1 by controlling the time when the logical bit information is at a high level. The embedded system according to claim 20.

22. The first system sequentially generates hardware interface sub-signals corresponding to the respective logical bit information based on the reload value and the initial match value corresponding to each logical bit information according to the order before and after among the plurality of logical bit information corresponding to the request command, and is used to obtain the hardware interface signal. The embedded system according to claim 21.

23. The first system is used to perform a decrement operation on the reload value corresponding to each logical bit information based on the timer. Before the reload value corresponding to each logical bit information is decremented to the initial match value corresponding to the logical bit information, the first system is used to output a first signal corresponding to the logical bit information. Here, the first signal is a high-level signal. After the reload value corresponding to each logical bit information is decremented to the initial match value corresponding to the logical bit information, the first system is used to output a second signal corresponding to the logical bit information. The second signal is a low-level signal. When the reload value corresponding to each logical bit information is decremented to 0, the first system determines the generation of the hardware interface sub-signal corresponding to the logical bit information, and is used to obtain the hardware interface sub-signal corresponding to each logical bit information. Here, the hardware interface sub-signal corresponding to each logical bit information is composed of the first signal and the second signal corresponding to the logical bit information. The embedded system according to claim 22.

24. The first system is used to trigger a first interrupt corresponding to the logical bit information when the reload value corresponding to each logical bit information is decremented to the initial match value corresponding to the logical bit information. The first system according to claim 23, which is used to trigger a second interrupt corresponding to the logical bit information when the reload value corresponding to each logical bit information is decremented to 0. **Claim 25** Each time the first system triggers one of the first interrupt or the second interrupt, it is used to perform an interrupt count once. The first system is used to determine the field in which the current signal conversion process in the request command is being performed based on the interrupt count. Here, the signal conversion process is used to generate a hardware interface sub-signal corresponding to the logical bit information corresponding to each field in the request command. The embedded system according to claim 24. **Claim 26** The first system is used to obtain the number of bytes corresponding to each field in the request command. The first system is used to determine the number of logical bit information corresponding to the request command based on the number of bytes. Here, each byte corresponding to the request command corresponds to one piece of the logical bit information. The first system is used to determine the number of interrupts corresponding to the request command based on the number of logical bit information. Here, the number of interrupts corresponding to the request command is twice the number of logical bit information. The first system according to claim 25, which is used to determine the field in which the current signal conversion process in the request command is being performed based on the number of interrupts and the interrupt count. **Claim 27** The first system is used to determine the logical bit information that is currently being converted into the hardware interface sub-signal based on the number of interrupts and the interrupt count. The first system is used to determine the byte corresponding to the logical bit information that is currently being converted into the hardware interface sub-signal as the target byte. The integrated system according to claim 26, wherein the first system is used to determine a field corresponding to the target byte as a field in which the current signal conversion process in the request instruction is being performed.

28. The data structure of the request data corresponding to the request instruction is a first data structure, where the first data structure includes at least a device address, a write length, a read length, an instruction code, and request parameters. The device address is used to characterize the address of the target device, and the target device is a device that generates response data based on the hardware interface signal. The instruction code is used to distinguish different request instructions. The write length is used to characterize the number of bytes from the instruction code to the request data. The read length is used to characterize the number of bytes including the completion code and the read data in the request data. The request parameters are used to characterize the parameters of the request instruction. The integrated system according to claim 19.

29. The integrated system further includes a second system, where both the second system and the first system operate on the processor. The second system is used to generate the request data. The first system is used to obtain the request data when detecting a first request triggered by the second system. Here, the service response speed of the second system is slower than that of the first system. The first system is used to analyze the request data and obtain the request instruction. The integrated system according to claim 28.

30. The second system stores the request data in the target memory and, after the storage of the request data is completed, uses it to trigger the first request. Here, the first request is used to notify the first system to read the request data from the target memory. The target memory is a memory accessible by both the first system and the second system. The integrated system according to claim 29.

31. The embedded system according to claim 19, wherein the first system is used to convert the voltage of the hardware interface signal to obtain a target hardware interface signal.

32. The embedded system according to claim 31, wherein the first system inputs the hardware interface signal into a voltage conversion device and is used to obtain a target hardware interface signal output from the voltage conversion device.

33. The first system is used to receive response data corresponding to the hardware interface signal, wherein the transmission format of the response data is the same as the transmission format of the hardware interface signal. The embedded system according to claim 19, wherein the first system is used to adjust the data structure of the response data to a second data structure.

34. The second data structure includes at least a first calibration value, a second calibration value, and response valid data, wherein the first calibration value is used to characterize the calibration value in the request data, the second calibration value is used to characterize the calibration value in the response data, and the response valid data is used to characterize data for explaining the completion code in the response data and the state of the target device, and the target device is a device that generates the response data based on the hardware interface signal. The embedded system according to claim 33.

35. The first system is used to trigger a second request, wherein the second request is used to notify the second system to read the response data. The embedded system according to claim 34.

36. The embedded system according to claim 19, wherein the hardware interface signal is any one of a PECI signal, an HDMI signal, an SGMII signal, an RGMII signal, a GPIO signal, and an SPI signal.

37. An acquisition module used to obtain a request command by a first system, A determination module used to determine a plurality of logical bit information corresponding to the request command, A generation module used to generate a hardware interface signal corresponding to the request command based on the plurality of logical bit information and a timer, and a generation device for the hardware interface signal.

38. A chip including at least one of a programmable logic circuit and executable instructions, operating in an electronic device, and used to implement the method for generating a hardware interface signal according to any one of claims 1 to 18.

39. A BMC chip including a memory unit and a processing unit connected to the memory unit, where the memory unit is used to store a program, and the processing unit is used to execute the program to implement the method for generating a hardware interface signal according to any one of claims 1 to 18.

40. A motherboard including at least one processor and at least one storage used to store at least one program, where when the at least one program is executed by the at least one processor, the at least one processor is caused to implement the method for generating a hardware interface signal according to any one of claims 1 to 18.

41. A server including a processor, a communication interface, a storage, and a communication bus, where the processor, the communication interface, and the storage realize communication with each other via the communication bus, the storage is used to store a computer program, and the processor is used to implement the method for generating a hardware interface signal according to any one of claims 1 to 18 when executing the program stored in the storage.

42. A computer-readable storage medium storing a computer program, where when the computer program is executed by a processor, the steps of the method for generating a hardware interface signal according to any one of claims 1 to 18 are implemented.

43. An electronic device including a storage, a processor, and a computer program stored in the storage and executable by the processor, where the processor realizes the steps of the method for generating a hardware interface signal according to any one of claims 1 to 18 when executing the computer program. ​ ​ ​ ​

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