Method and apparatus for collecting high-frequency power supply signals

Abstract

The present application discloses and provides a method and apparatus for collecting high-frequency power supply signals. The method includes determining a rising edge section and a falling edge section within a current pulse period, and setting data bits corresponding to the rising edge section and the falling edge section in a sampling array to 0, a low level of the signal, or a null signal. In the prior art, a collection board continuously collects voltage and current signals without interruption and continuously outputs the signals. Even during the switching of the switch and in the PULSE mode, the signals are still collected and output without interruption during the ramp generation stage, resulting in the problem of inaccurate data being output.

Description

Technical Field

[0001] The present invention relates to the technical field of high-frequency power supply signal collection, and specifically, to a method and apparatus for collecting high-frequency power supply signals.

Background Art

[0002] A typical data collection system collects signals generated from the surrounding environment and various test target devices by various sensors. Generally, since these signals are randomly generated, the data collection system needs to continuously sample so as not to miss important signals. In a high-frequency power supply, the current collection board collects voltage and current signals by continuous sampling. In the prior art, the collection board continuously collects voltage and current signals without interruption and continuously outputs the signals. Even when the switch is switched and in the PULSE mode, signals are still collected and output without interruption during the lamp generation stage, which causes the problem that inaccurate data is output.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Therefore, the technical problem to be solved by the present invention is to provide a method and apparatus for collecting high-frequency power supply signals in order to solve the problem in the conventional high-frequency power supply technology that inaccurate data is output because the collection board continuously collects voltage and current signals without interruption and continuously outputs the signals, and still collects and outputs the signals without interruption during the lamp generation stage even when the switch is switched and in the PULSE mode.

Means for Solving the Problems

[0004] To solve the above technical problems, the disclosed embodiments of the present invention provide at least a method and apparatus for collecting high-frequency power supply signals.

[0005] In a first aspect, the disclosed embodiments of the present invention are Determining a rising edge section and a falling edge section within a current pulse period; Setting data bits corresponding to the rising edge section and the falling edge section in a sampling array to 0, a low level of a signal, or a null signal, and providing a method for collecting a high-frequency power supply signal.

[0006] Optionally, the step of setting data bits corresponding to the rising edge section and the falling edge section in the sampling array to 0, a low level of a signal, or a null signal is a step of setting data bits corresponding to the rising edge section and the falling edge section in the sampling array to 0, a low level of a signal, or a null signal by sampling delay or resetting an output of sampling data.

[0007] Optionally, the step of setting data bits corresponding to the rising edge section and the falling edge section in the sampling array to 0, a low level of a signal, or a null signal by sampling delay or resetting an output of sampling data includes: in a rising edge section, at the time of data sampling, delaying a sampling time to set a data bit corresponding to the rising edge section in the sampling array to 0, a low level of a signal, or a null signal, or at the time of outputting sampling data, setting a data bit corresponding to the rising edge section in the sampling array to 0, a low level of a signal, or a null signal; and in a falling edge section, at the time of data sampling, delaying a sampling time to set a data bit corresponding to the falling edge section in the sampling array to 0, a low level of a signal, or a null signal, or at the time of outputting sampling data, setting a data bit corresponding to the falling edge section or the falling edge section in the sampling array to 0, a low level of a signal, or a null signal.

[0008] Optionally, by delaying the sampling time, the step of setting the data bit corresponding to the rising edge section in the sampling array to 0, a low level signal of the signal, or a null signal includes starting a first sampling delay from the rising edge start point within the current pulse period, and setting the data bit corresponding to the first sampling delay in the sampling array to 0, a low level signal of the signal, or a null signal. By delaying the sampling time, the step of setting the data bit corresponding to the falling edge section in the sampling array to 0, a low level signal of the signal, or a null signal includes starting a second sampling delay from the falling edge start point within the current pulse period, and setting the data bit corresponding to the second sampling delay in the sampling array to 0, a low level signal of the signal, or a null signal.

[0009] Optionally, the step of setting the data bit corresponding to the rising edge section in the sampling array to 0, a low level signal of the signal, or a null signal includes, simultaneously with the completion of signal sampling for the rising edge end point within the current pulse period, determining first abnormal data that is data within a first predetermined length before the data bit corresponding to the rising edge end point in the sampling array, resetting the first abnormal data to a low level signal of the signal or a null signal, and the first predetermined length being the array length corresponding to the rising edge section. The step of setting the data bit corresponding to the falling edge section in the sampling array to 0, a low level signal of the signal, or a null signal includes, simultaneously with the completion of signal sampling for the falling edge end point within the current pulse period, determining second abnormal data that is data within a second predetermined length before the data bit corresponding to the falling edge end point in the sampling array, resetting the second abnormal data to a low level signal of the signal or a null signal, and the second predetermined length being the array length corresponding to the falling edge section.

[0010] Optionally, the step of setting the data bit corresponding to the first sampling delay in the sampling array to 0, a low level of the signal, or a null signal is to set the data bit corresponding to the first predetermined sampling time in the sampling array to 0, a low level of the signal, or a null signal to end the delay, and the step of setting the data bit corresponding to the second sampling delay in the sampling array to 0, a low level of the signal, or a null signal is to set the data bit corresponding to the second predetermined sampling time in the sampling array to 0, a low level of the signal, or a null signal to end the delay.

[0011] Optionally, the step of setting the data bit corresponding to the first sampling delay in the sampling array to 0, a low level of the signal, or a null signal is to set the data bit corresponding to the first predetermined array length in the sampling array to 0, a low level of the signal, or a null signal to end the delay, and the step of setting the data bit corresponding to the second sampling delay in the sampling array to 0, a low level of the signal, or a null signal is to set the data bit corresponding to the second predetermined array length in the sampling array to 0, a low level of the signal, or a null signal to end the delay.

[0012] Optionally, the step of determining the rising edge section and the falling edge section within the current pulse period is determining the rising edge section and the falling edge section within the current pulse period according to a reference threshold for representing the low level of the signal, a rising edge time, and a falling edge time, or determining the rising edge section and the falling edge section within the current pulse period according to the reference threshold and a peak threshold for representing the high level of the signal, or including determining the rising edge section and the falling edge section within the current pulse period according to the power change of the sampling point.

[0013] Optionally, the first predetermined sampling time is equal to the rising edge time, and the second predetermined sampling time is equal to the falling edge time.

[0014] Optionally, the first predetermined array length and the second predetermined array length are determined based on a predetermined arithmetic relationship from the rising edge time or the falling edge time and the sampling period.

[0015] Optionally, the first predetermined array length is equal to the rising edge time / sampling period, the second predetermined array length is equal to the falling edge time / sampling period, or the first predetermined array length, the second predetermined array length, and the rising edge time / sampling period are equal, or the first predetermined array length, the second predetermined array length, and the falling edge time / sampling period are equal.

[0016] Optionally, the step of determining the rising edge section and the falling edge section within the current pulse period according to the power change of the sampling point includes obtaining a rising edge start point which is a sampling point at which the power first becomes greater than the rising edge reference threshold within the current pulse period, and obtaining a falling edge start point which is a sampling point at which the power first becomes less than the falling edge reference threshold within the current pulse period.

[0017] Optionally, the method further includes a step of sequentially outputting the sampling data read by the sampling array outside the rising edge section and the falling edge section.

[0018] Optionally, when the first predetermined array length, the second predetermined array length, and the rising edge time / sampling period are equal, and the rising edge time is greater than the falling edge time, the step of setting the data bits corresponding to the rising edge section and the falling edge section in the sampling array to 0, a low level of the signal, or a null signal by sampling delay or resetting the output of the sampling data is, at the time of output of the sampling data, simultaneously with the completion of signal sampling for the falling edge end point within the current pulse period, calculate the time of a third delay, which is the difference value between the rising edge time and the falling edge time, start the third delay, at the end of the third delay, determine third abnormal data, which is the data within a third predetermined length before the data bit corresponding to the third delay end point in the sampling array, reset the third abnormal data to a low level of the signal or a null signal, and the step that the third predetermined length is the array length corresponding to the falling edge section.

[0019] Optionally, the step of determining the rising edge section and the falling edge section within the current pulse period is including the step of respectively determining the rising edge section and the falling edge section within the current pulse period based on a predetermined power rising threshold, a predetermined power falling threshold, the number of padding data of the predetermined rising edge, and the number of padding data of the predetermined falling edge.

[0020] Optionally, before the step of determining the rising edge section and the falling edge section within the current pulse period, the method is further including the step of obtaining the predetermined power rising threshold, the predetermined power falling threshold, the number of padding data of the predetermined rising edge, and the number of padding data of the predetermined falling edge by continuous sampling tests.

[0021] Optionally, in the step of obtaining the predetermined power rise threshold, the predetermined power fall threshold, the number of padding data for a predetermined rising edge, and the number of padding data for a predetermined falling edge by continuous sampling tests, continuously collecting a first high-frequency power signal including a first voltage V and a first current I for each of a plurality of sampling points; determining the predetermined power rise threshold, the predetermined power fall threshold, the number of padding data for a predetermined rising edge, and the number of padding data for a predetermined falling edge based on the first voltage V and the first current I.

[0022] Optionally, in the step of determining a rising edge section and a falling edge section within a current pulse period respectively based on the predetermined power rise threshold, the predetermined power fall threshold, the number of padding data for a predetermined rising edge, and the number of padding data for a predetermined falling edge, continuously collecting a second high-frequency power signal including a second voltage V and a second current I for each of a plurality of sampling points; determining the power of each sampling point based on the second voltage V and the second current I; determining a start point of the rising edge section and the number of padding data for the predetermined rising edge based on the power of each sampling point, the power rise threshold, and the number of padding data for the rising edge; determining a start point of the falling edge section and the number of padding data for the predetermined falling edge based on the power of each sampling point, the power fall threshold, and the number of padding data for the falling edge.

[0023] Optionally, in the step of determining the predetermined power rise threshold, the predetermined power fall threshold, the number of padding data for a predetermined rising edge, and the number of padding data for a predetermined falling edge based on the first voltage V and the first current I, Calculate the power value at each sampling point according to P = VI, obtain the first specific power value Pr after the zero potential and the power value Pd that is not Pe after the power average value Pe at the peak potential, and include the step of using Pr as the predetermined power rising threshold and Pd as the predetermined power falling threshold.

[0024] Optionally, the step of determining the predetermined power rising threshold, the predetermined power falling threshold, the number of padding data for the predetermined rising edge, and the number of padding data for the predetermined falling edge based on the first voltage V and the first current I includes: Determine the number of padding data for the predetermined rising edge in the rising edge based on Tr / T, determine the number of padding data for the predetermined falling edge in the falling edge based on Td / T, where Td is the falling edge time, Tr is the rising edge time, and T is the sampling period, and further include this step.

[0025] In a second aspect, the disclosed embodiment of the present invention An abnormal data interval determination module for determining a rising edge interval and a falling edge interval within the current pulse period, and A sampling data reset module for setting the data bits corresponding to the rising edge interval and the falling edge interval in the sampling array to 0, a low level of the signal, or a null signal, and further provides a high-frequency power source signal collection device.

[0026] In a third aspect, the disclosed embodiment of the present invention includes a processor, a memory, and a bus. The memory stores computer-readable commands executable by the processor. When the computer device operates, the processor communicates with the memory via the bus. When the computer-readable commands are executed by the processor, the steps in the above first aspect or any possible implementation form of the first aspect are implemented, and further provides a computer device.

[0027] In a fourth aspect, the disclosed embodiment of the present invention further provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in any possible embodiment of the first aspect or the first aspect above.

Advantages of the Invention

[0028] The technical solution provided by the embodiments of the present invention may have the following beneficial effects.

[0029] Determine the rising edge section and the falling edge section within the current pulse period, set the data bits corresponding to the rising edge section and the falling edge section in the sampling array to 0, a low-level signal of the signal, or a null signal, mask the data of the abnormal segment by resetting the FIFO (First Input First Output) sampling array, that is, output the data of the switch switching time and the lamp segment in the PULSE mode to 0, and output power only in the correct time zone other than the lamp.

[0030] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the present invention.

[0031] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly describes the drawings necessary for the description of the specific embodiments or the prior art. Naturally, the drawings in the following description are only a part of the embodiments of the present invention, and those skilled in the art can conceive other drawings from these drawings without creative efforts.

Brief Description of the Drawings

[0032]

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Embodiments for Carrying Out the Invention

[0033] Here, exemplary embodiments will be described in detail and the examples will be shown in the drawings. In the following, when referring to the description with reference to the drawings, unless otherwise specified, the same numerals in different drawings represent the same elements or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments that are consistent with the present invention. On the contrary, they are merely examples of devices and methods that are consistent with some aspects of the present invention detailed in the appended claims.

[0034] Example 1 As shown in FIG. 1, which is a flowchart of a method for collecting high-frequency power supply signals provided by the disclosed embodiments of the present invention, the method includes: Step S11 of determining the rising edge section and the falling edge section within the current pulse period; S12 of setting the data bits corresponding to the rising edge section and the falling edge section in the sampling array to 0, the low level of the signal, or a null signal; S13 of sequentially outputting the sampling data read by the sampling array outside the rising edge section and the falling edge section.

[0035] It can be understood that the technical solution provided by this embodiment determines the rising edge section and the falling edge section within the current pulse period, sets the data bits corresponding to the rising edge section and the falling edge section in the sampling array to 0, the low level of the signal, or a null signal, masks the data of the abnormal segment by resetting the FIFO (First Input First Output) sampling array, that is, outputs the data of the lamp segment at the time of switch switching and in the PULSE mode to 0, and outputs power only in the correct time zone other than the lamp.

[0036] Example 2 As shown in FIG. 2, which is a flowchart of another method for collecting high-frequency power supply signals provided by the disclosed embodiments of the present invention, referring to FIG. 3, the method masks the abnormal data generated in the lamp stage within the pulse period, and the method includes: Step S21 of determining the rising edge section and the falling edge section within the current pulse period; S22 of setting the data bits corresponding to the rising edge section and the falling edge section in the sampling array to 0, the low level of the signal, or a null signal; S23 of sequentially outputting the sampling data read by the sampling array outside the rising edge section and the falling edge section. It includes the following steps.

[0037] In some embodiments, S22 of setting the data bits corresponding to the rising edge section and the falling edge section in the sampling array to 0, the low level of the signal, or a null signal may be performed by sampling delay or resetting the output of the sampling data, so as to set the data bits corresponding to the rising edge section and the falling edge section in the sampling array to 0, the low level of the signal, or a null signal.

[0038] In some embodiments, S22 may include the following S221 and S222.

[0039] In S221, within the rising edge section, different data processing methods may be used according to the data determination pattern. The data determination pattern includes the following methods (A), (B), and (C).

[0040] (A) It is determined by a reference threshold whether the input signal transitions from the low level of the signal to the rising edge section. That is, when the signal data is below the reference threshold, it is regarded as the low level of the signal (or the signal zero point output, or 0 output), and when the signal data is greater than the reference threshold, it is regarded as the signal rising towards the high level, and the rising process is regarded as the rising edge section.

[0041] When reading sampling data, if the sampling data that has been read once and is planned to be introduced into the sampling array exceeds the reference threshold value, the signal is considered to have entered the rising edge, and in this case, the sampling delay is started. When the sampling delay ends, the normal sampling data reading operation is resumed. In some embodiments, the time of the sampling delay is the time of the rising edge section. Here, according to the length of the corresponding collection array, the corresponding data processing method is adopted and will be described as follows.

[0042] (A-1) When the time corresponding to the data bit of the collection array is equal to or longer than the time of the rising edge section, (A-11) The method of first setting the sampling data read during the sampling delay period to 0, the low level of the signal or the null signal, and then padding the sampling array, (A-12) The method of marking the sampling data read during the sampling delay period and introduced into the sampling array, and when outputting the sampling data, setting the data bit corresponding to the rising edge section in the sampling array to 0, the low level of the signal or the null signal, (A-13) During the period when the sampling time delay is started, no matter what sampling data is read, the entire data of the sampling array still maintains the FIFO operation. When the sampling time delay ends, all the data fields in the sampling array are set to 0, the low level of the signal or the null signal, and at the same time, the normal data sampling operation is performed. It is processed by any one of the above methods.

[0043] (A-2) When the time corresponding to the data bit of the collection array is less than the time of the rising edge section, the data read by the method of (A-11) or (A-12) is processed.

[0044] (B) Determine whether the input signal has transitioned from the low level of the signal to the rising edge section based on a reference threshold value, and also determine whether the input signal has transitioned from the rising edge section to the high level of the signal based on a peak threshold value.

[0045] When reading sampling data, if the sampling data that has been read and is planned to be introduced into the sampling array exceeds the reference threshold value, it is considered that the signal has entered the rising edge, and in this case, start the sampling delay. If the sampling data that has been read and is planned to be introduced into the sampling array exceeds the peak threshold value, it is considered that the signal has entered the high level of the signal from the rising edge. In this case, end the sampling delay and resume the normal sampling data reading operation and the padding operation to the sampling array.

[0046] In some embodiments, when the time of the rising edge section is known, according to the length of the corresponding collection array, adopt the corresponding data processing method as in (A-1) and (A-2) above.

[0047] In some embodiments, the time of the sampling delay needs to be determined by the time when the read sampling value is between the reference threshold value and the peak threshold value, that is, the actual time of the rising edge section. That is, it means that only the reference threshold value and the peak threshold value are used to determine the low level, rising edge and high level of the signal. The data processing method is as in (A-1) and (A-2) above.

[0048] (C) By comparing the sampling values read before and after, based on the change in data size, determine whether the input signal has transitioned from the low level of the signal to the rising edge section, and also whether it has transitioned from the rising edge section to the high level of the signal.

[0049] When reading sampling data, when a plurality of consecutive sampling data to be introduced into the sampling array, once read, rises from a certain low-level data to rising data (the data before being read is lower than the data behind), the signal is regarded as entering the rising edge, and in this case, the sampling delay is started. When a plurality of consecutive sampling data to be introduced into the sampling array, once read, becomes a certain high-level data from the rising data (the data before being read is equal to the data behind), the signal is regarded as entering the high level of the signal from the rising edge, and in this case, the sampling delay is terminated, and the normal sampling data reading operation and the padding operation to the sampling array are resumed.

[0050] In some embodiments, when the time of the rising edge section is known, according to the length of the corresponding collection array, the corresponding data processing method as described in (A-1) and (A-2) above is adopted.

[0051] In some embodiments, the time of the sampling delay needs to be determined by the time when the read sampling value is between the reference threshold and the peak threshold, that is, the actual time of the rising edge section. That is, it means that the low level, rising edge and high level of the signal can be determined by the conversion between a certain data and rising data without considering the time of the rising edge section. The data processing method is as described in (A-11) and (A-12) above.

[0052] In S222, within the falling edge section, different data processing methods may be used according to the data determination pattern. The data determination pattern includes the following methods (D), (E), (F), (G).

[0053] (D) It is determined by a reference threshold whether the input signal has reached the falling edge section and transitioned to the low level of the signal, that is, it means whether the signal has reached the end of the falling edge section. Furthermore, it can be considered that the signal transitions to the low level, zero point, or no output.

[0054] When reading sampling data, if the sampling data that has been read and is planned to be introduced into the sampling array is below the reference threshold, it is considered that the signal has passed the falling edge end, and further, the signal has reached the low level, zero point, or no output. In this case, the sampling delay is started. When the sampling delay ends, the normal sampling data reading operation is resumed.

[0055] In some embodiments, the time of the sampling delay is the total data sampling time corresponding to the data bits of the collection array - the falling edge time. Here, the total data sampling time corresponding to the data bits of the collection array is greater than or equal to the falling edge time. On the other hand, the method of performing delay processing according to the length of the corresponding collection array is as follows in (D-1) and (D-2).

[0056] (D-1) When the total data sampling time corresponding to the data bits of the collection array is equal to the falling edge time, the time of the sampling delay is 0, that is, the sampling delay is not started, and the subsequent data processing is directly performed.

[0057] (D-2) When the total data sampling time corresponding to the data bits of the collection array is greater than the falling edge time, the time of the sampling delay is the difference between the two, and after the delay ends, the subsequent data processing is performed.

[0058] In some embodiments, during the period when the sampling delay is started (the above D-2), no matter what sampling data is read, the entire data of the sampling array still maintains the FIFO operation. When the sampling delay time ends (or the sampling delay is not started as in the above D-1), all the data fields in the sampling array are set to 0, the low level of the signal or the null signal, and at the same time, normal data sampling operations are performed.

[0059] (E) It is determined by the peak threshold whether the input signal has transitioned to the falling edge section from the high level of the signal, that is, if the signal data is greater than the peak threshold, it is regarded as the high level of the signal, and if the signal data is below the peak threshold, the signal is regarded as having dropped to the low level, and the dropping process is regarded as the falling edge section.

[0060] When reading sampling data, if the sampling data to be introduced into the sampling array, once read, is below the peak threshold, the signal is regarded as entering the falling edge, and in this case, the sampling delay is started. When the sampling delay ends, the normal sampling data reading operation is resumed.

[0061] In some embodiments, the time of the sampling delay uses the longer one of the time of the falling edge section and the total data sampling time corresponding to the data bits of the collection array. If both are the same, either one can be selected. Therefore, after the delay ends, the collected data read is at the low level of the signal.

[0062] Here, according to the length of the corresponding collection array, the corresponding data processing method is adopted and described as follows.

[0063] (E-1) When the time corresponding to the data bits of the collection array is greater than or equal to the time of the falling edge section (E-11) First, set the sampling data read during the sampling delay period to 0, the low level of the signal, or a null signal, and then pad it to the sampling array. (E-12) Mark the sampling data read during the sampling delay period and introduced into the sampling array. When outputting the sampling data, set the data bits corresponding to the falling edge section in the sampling array to 0, the low level of the signal, or a null signal. (E-13) During the period when the sampling time delay starts, no matter what sampling data is read, the entire data in the sampling array still maintains the FIFO operation. When the sampling time delay ends, set all the data fields in the sampling array to 0, the low level of the signal, or a null signal, and at the same time, perform normal data sampling operations. Process it by any one of these methods.

[0064] (E-2) When the time corresponding to the data bit of the collection array is less than the time of the falling edge section, process the data read by the method of (E-11) or (E-12).

[0065] (F) Determine whether the input signal has transitioned from the high level of the signal to the falling edge section by the peak threshold, and also determine whether the input signal has transitioned from the falling edge section to the low level of the signal by the reference threshold.

[0066] When reading sampling data, once the sampling data that is to be introduced into the sampling array and has been read is below the peak threshold, it is considered that the signal has entered the falling edge. In this case, start the sampling delay. When the sampling data that is to be introduced into the sampling array and has been read is below the reference threshold, it is considered that the signal has entered the low level from the falling edge. In this case, end the sampling delay and resume normal sampling data reading operations and padding operations to the sampling array.

[0067] In some embodiments, the time of the sampling delay needs to be determined by the time when the read sampling value is between the reference threshold and the peak threshold, that is, the actual time of the falling edge section. That is, it means that only the reference threshold and the peak threshold are used to determine the high level of the signal, the falling edge, and the low level of the signal. The data processing method is as described in (E-1) and (E-2) above.

[0068] (G) By comparing the sampling values read before and after, based on the change in data size, it is determined whether the input signal has transitioned from the high level of the signal to the falling edge section, and whether it has transitioned from the falling edge section to the low level of the signal.

[0069] When reading sampling data, once the continuously multiple sampling data to be introduced into the sampling array are read, if they change from a certain high-level data to rising data (the data read before is lower than the data behind), the signal is considered to have entered the falling edge, and in this case, the sampling delay is started. When the continuously multiple sampling data to be introduced into the sampling array are read and change from rising data to a certain low-level data (the data read before is equal to the data behind), the signal is considered to have entered the low level of the signal from the falling edge, and in this case, the sampling delay is terminated, and the normal sampling data reading operation and the padding operation to the sampling array are resumed.

[0070] In some embodiments, when the falling edge section is known, according to the length of the corresponding collection array, the corresponding data processing method as in (E-1) and (E-2) above is used.

[0071] In some embodiments, the time of the sampling delay needs to be determined by the time when the read sampling value is between the reference threshold and the peak threshold, that is, the actual time of the rising edge section. That is, it means that the low level, rising edge, and high level of the signal can be determined by the conversion between fixed data and rising data without considering the time of the rising edge section. The data processing method is as described in (E-11) and (E-12) above.

[0072] In some embodiments, S22 includes, when sampling data, delaying the sampling time to set the data bit corresponding to the falling edge section in the sampling array to 0, a low level of the signal, or a null signal, or when outputting the sampling data, setting the data bit corresponding to the falling edge section or the falling edge section in the sampling array to 0, a low level of the signal, or a null signal.

[0073] In some embodiments, S221 may include starting the first sampling delay from the rising edge start point within the current pulse period and setting the data bit corresponding to the first sampling delay in the sampling array to 0, a low level of the signal, or a null signal. The above-mentioned setting the data bit corresponding to the falling edge section in the sampling array to 0, a low level of the signal, or a null signal by delaying the sampling time may include starting the second sampling delay from the falling edge start point within the current pulse period and setting the data bit corresponding to the second sampling delay in the sampling array to 0, a low level of the signal, or a null signal.

[0074] In some embodiments, particularly when some rising-edge power reference thresholds cannot be obtained, S222, simultaneously with the completion of signal sampling at the rising-edge end point within the current pulse period, determines first abnormal data that is the data within a first predetermined length before the data bit corresponding to the rising-edge end point in the sampling array, resets the first abnormal data to make it a low-level signal or a null signal of the signal, and the first predetermined length is the array length corresponding to the rising-edge section. This may include the step of Here, setting the data bit corresponding to the falling-edge section in the sampling array to 0, a low-level signal or a null signal of the signal can be realized by a process in which, simultaneously with the completion of signal sampling at the falling-edge end point within the current pulse period, second abnormal data that is the data within a second predetermined length before the data bit corresponding to the falling-edge end point in the sampling array is determined, the second abnormal data is reset to make it a low-level signal or a null signal of the signal, and the second predetermined length is the array length corresponding to the falling-edge section.

[0075] In some embodiments, setting the data bit corresponding to the first sampling delay in the sampling array to 0, a low-level signal or a null signal of the signal may be to set the data bit corresponding to the first predetermined sampling time in the sampling array to 0, a low-level signal or a null signal of the signal to end the delay. Setting the data bit corresponding to the second sampling delay in the sampling array to 0, a low-level signal or a null signal of the signal may be to set the data bit corresponding to the second predetermined sampling time in the sampling array to 0, a low-level signal or a null signal of the signal to end the delay.

[0076] In some embodiments, setting the data bit corresponding to the first sampling delay in the sampling array to 0, a low level of the signal, or a null signal may be to set the data bit corresponding to the first predetermined array length in the sampling array to 0, a low level of the signal, or a null signal to end the delay. Setting the data bit corresponding to the second sampling delay in the sampling array to 0, a low level of the signal, or a null signal may be to set the data bit corresponding to the second predetermined array length in the sampling array to 0, a low level of the signal, or a null signal to end the delay.

[0077] In some embodiments, S21 is a. determining the rising edge section and the falling edge section within the current pulse period according to a reference threshold for representing a low level of the signal, a rising edge time, and a falling edge time, or b. determining the rising edge section and the falling edge section within the current pulse period according to the reference threshold and a peak threshold for representing a high level of the signal, or c. may include determining the rising edge section and the falling edge section within the current pulse period according to the power change of the sampling point.

[0078] In some embodiments, specifically, perform test sampling. Using the sampling period as a base number, starting from the time when the power rise begins to exceed the rising threshold, and ending at the time when the power reaches the falling threshold, calculate the number of samplings or the sampling time to obtain the rising edge section. Conversely, starting from the time when the power drop begins to exceed the falling threshold, and ending at the time when the power reaches the rising threshold, calculate the number of samplings or the sampling time to obtain the falling edge section.

[0079] In some embodiments, the first sampling delay time is equal to the rising edge time, and the second sampling delay time is equal to the falling edge time.

[0080] In some embodiments, the first predetermined array length ≧ fall edge time / sampling period, and the second predetermined array length ≧ fall edge time / sampling period.

[0081] In some embodiments, the first predetermined array length and the second predetermined array length are determined based on a predetermined arithmetic relationship from the rise edge time or the fall edge time and the sampling period.

[0082] In a specific embodiment, the first predetermined array length is equal to the rise edge time / sampling period, the second predetermined array length is equal to the fall edge time / sampling period, or the first predetermined array length, the second predetermined array length, and the rise edge time / sampling period are equal, or the first predetermined array length, the second predetermined array length, and the fall edge time / sampling period are equal.

[0083] In some embodiments, when the first predetermined array length, the second predetermined array length, and the rise edge time / sampling period are equal, and the rise edge time is greater than the fall edge time, sampling delay or resetting the output of sampling data to set the data bits corresponding to the rise edge section and the fall edge section in the sampling array to 0, the low level of the signal, or the null signal is At the time of outputting the sampling data, simultaneously with the completion of signal sampling for the fall edge end point within the current pulse period, calculate the time of the third delay, which is the difference value between the rise edge time and the fall edge time, start the third delay, and at the end of the third delay, determine the third abnormal data, which is the data within the third predetermined length before the data bit corresponding to the end point of the third delay in the sampling array, reset the third abnormal data to the low level of the signal or the null signal, and the third predetermined length is the array length corresponding to the fall edge section.

[0084] In some embodiments, S21 may include: obtaining a rising edge start point, which is a sampling point at which the power first becomes greater than a reference threshold within the current pulse period; obtaining a rising edge end point, which is a sampling point at which the power first becomes greater than a peak threshold within the current pulse period; obtaining a falling edge start point, which is a sampling point at which the power first becomes less than a falling edge reference threshold within the current pulse period; and obtaining a falling edge end point, which is a sampling point at which the power first becomes less than the reference threshold within the current pulse period.

[0085] For the convenience of the reader's understanding, hereinafter, the above high-frequency power supply signal collection method will be described by way of a specific example. First, assume that the rising edge time is 10 μs (T1), the falling edge time is 4 μs (T2), the length of the sampling array is 5, and the period is 1 μs.

[0086] Example 1 (known reference threshold), as shown in FIGS. 7 and 4, Within the rising edge interval, it is determined by a reference threshold whether the input signal has transitioned from the low level of the signal to the rising edge interval. Once the sampling data to be introduced into the sampling array, which has been read, exceeds the reference threshold, the signal is considered to have entered the rising edge, and in this case, the sampling delay is started. When the leading bit of the FIFO array reaches point A of the rising edge, when the power (Pa) of the next collection point exceeds the reference threshold, a delay of 10 μs of T1 is started. In this case, each data in the FIFO array is limited to 0. When the leading bit of the FIFO array reaches point B of the rising edge, the sampling delay is terminated, and data padding is started at the leading bit of the FIFO array. The entire FIFO array is initially padded up to point C, and then, according to the FIFO theory, the first-in-first-out of the data is executed. The data output before the FIFO array reaches point C is still 0, and the data of point B, which was first input up to point C, begins to be output. Before reaching point E, the data output is normal output.

[0087] Within the falling edge section, it is determined by a reference threshold whether the input signal has reached the falling edge section and transitioned to the low level of the signal. When sampling data is read, if the sampling data that has once been read and is planned to be introduced into the sampling array is below the reference threshold, it is considered that the signal has passed the falling edge end and further reached the low level of the signal, the zero point, or no output. In this case, the sampling delay is started. At the falling edge stage, when the leading bit of the FIFO array reaches the F point of the falling edge, the power (Pb) at the collection point becomes lower than the reference threshold, and the data at point D is substantially output. In this case, a delay of T2 = 5us - 4us = 1us is started. At the end of the delay, the leading bit of the FIFO array reaches point G, the trailing bit reaches point E, and the FIFO array clears and outputs the data.

[0088] Example 2 (known reference threshold, peak threshold), as shown in FIGS. 7 and 5, Within the rising edge section, it is determined by a reference threshold whether the input signal has transitioned from the low level of the signal to the rising edge section, and it is determined by a peak threshold whether the input signal has transitioned from the rising edge section to the high level of the signal. At the rising edge stage, when the leading bit of the FIFO array reaches point A of the rising edge, if the power (Pa) at the next collection point is greater than the reference threshold, the sampling delay is started. When the leading bit of the FIFO array reaches point B of the rising edge, when the power (Pa) at the next collection point is greater than the peak threshold, the sampling delay ends. Data padding is started for the leading bit of the FIFO array, and the entire FIFO array is initially padded up to point C. Then, according to the FIFO theory, the first-in-first-out of the data is executed. The data output before the FIFO array reaches point C is still 0, and the data at point B that was first input up to point C starts to be output. Before reaching point E, the data output is normal output.

[0089] Within the falling edge interval, it is determined by the peak threshold whether the input signal has transitioned from the high level of the signal to the falling edge interval, and it is determined by the reference threshold whether the input signal has transitioned from the falling edge interval to the low level of the signal. The data bit corresponding to the falling edge interval in the sampling array is set to 0, the low level of the signal, or a null signal, and the data processing method is as described in (E-1) above. When the leading bit of the FIFO array reaches point E of the falling edge, the power (Pb) at the collection point becomes lower than the peak threshold. In this case, the sampling delay is started. When the leading bit of the FIFO array reaches point F of the falling edge, the power (Pb) at the collection point becomes lower than the reference threshold. In this case, the sampling delay is terminated, and the normal sampling data reading operation and the padding operation to the sampling array are resumed.

[0090] Example 3 is, as shown in FIG. 6, Within the rising edge interval, by comparing the sampling numerical values read before and after, based on the change in the data size, it is determined whether the input signal has transitioned from the low level of the signal to the rising edge interval and whether it has transitioned from the rising edge interval to the high level of the signal. Specifically, the rising edge interval within the current pulse period is determined by the power change at the sampling point, and the data bit corresponding to the falling edge interval in the sampling array can be set to 0, the low level of the signal, or a null signal, and the data processing method is as described in (A-1) or (A-1) above.

[0091] When reading sampling data, if a plurality of consecutive sampling data to be introduced into the sampling array, once read, rises from a certain low-level data to rising data (the data before being read is lower than the subsequent data), the signal is regarded as entering the rising edge, and in this case, the sampling delay is started. If a plurality of consecutive sampling data to be introduced into the sampling array, once read, becomes a certain high-level data from the rising data (the data before being read is equal to the subsequent data), the signal is regarded as entering the high level of the signal from the rising edge, and in this case, the sampling delay is terminated, and the normal sampling data reading operation and the padding operation to the sampling array are resumed.

[0092] The low-power data collected from the start to point A is accurate. From point A to point B, it is a rising ramp, and the data collected at this time is not accurate. The high-power data collected from point B to point C is accurate.

[0093] Within the falling edge interval, by comparing the sampling numerical values read before and after, based on the change in the data size, it is determined whether the input signal transitions from the high level of the signal to the falling edge interval, and whether it transitions from the falling edge interval to the low level of the signal. The data processing method is as described in (E-1) and (E-2) above.

[0094] When reading sampling data, if a plurality of consecutive sampling data that have been read and are planned to be introduced into the sampling array rise from a certain high-level data to rising-edge data (the data read previously is lower than the subsequent data), the signal is regarded as entering the falling edge, and in this case, the sampling delay is started. When a plurality of consecutive sampling data that have been read and are planned to be introduced into the sampling array become a certain low-level data from the falling-edge data (the data read previously is equal to the subsequent data), the signal is regarded as entering the low level of the signal from the falling edge. In this case, the sampling delay is terminated, and the normal sampling data reading operation and the padding operation to the sampling array are resumed.

[0095] From point C to point D, it is a descending ramp. The data collected at this time is not accurate, while the low-power data collected from point D to point E is accurate. The time series of the continuously collected three power values P1, P2, and P3 is as shown in FIG. 6. P1 is the data collected latest, P2 is the next, and P3 is the data collected earliest.

[0096] The collected power values are sequentially differentiated to obtain the change amounts Δ1 = P1 - P2 and Δ2 = P2 - P3. Δth is a threshold for determining whether the collected data is accurate and is greater than 0. When the absolute values of the two change amounts are both greater than or equal to 0, the null signal value, or the low-level value of the signal and less than the threshold Δth, the collected data is accurate. In this case, the corresponding collected data is retained; otherwise, the abnormal data bit is set to 0, the null signal value, or the low-level value of the signal, or when outputting the sampling data, the data of the abnormal data bit is skipped and output. That is, if the absolute value of at least one of Δ1 and Δ2 is greater than or equal to +Δth, the data is not accurate, and in this case, all the collected data is discarded.

[0097] It should be noted that for the rising edge time (T1) and falling edge time (T2) in the embodiments of the present invention, test sampling is performed. Taking the sampling period as the base number, starting from the time when the power starts to exceed the rising threshold and ending at the time when the power reaches the falling threshold, the rising edge time can be obtained by calculating the number of samples or sampling time. Conversely, starting from the time when the power drop starts to exceed the falling threshold and ending at the time when the power reaches the rising threshold, the falling edge time can be obtained by calculating the number of samples or sampling time. It may also be other methods selected by those skilled in the art according to the needs of the process, and detailed description is omitted here. This method is particularly suitable for solving the problem that the signal collection is inaccurate within one pulse period, especially when the switch is switched and under the PULSE mode.

[0098] The technical solution provided by this embodiment is to determine the rising edge section and falling edge section within the current pulse period, set the data bits corresponding to the rising edge section and falling edge section in the sampling array to 0, the low level of the signal or the null signal, and mask the data of the abnormal segment by resetting the FIFO (First Input First Output) sampling array, that is, output the data of the ramp segment to 0 when the switch is switched and in the PULSE mode, and output the power only in the correct time zone other than the ramp. Embodiment 3

[0099] In some selectable embodiments, in order to obtain the parameter values required for determining the rising edge section and falling edge section, a sampling test stage may be added on top of Embodiment 1. Specifically, as shown in FIG. 7, which is a flowchart of another high-frequency power signal collection method provided by the disclosed embodiments of the present invention, the method includes the following S31 and S32.

[0100] In S31, it is the sampling test stage. Through continuous sampling tests, the predetermined power rise threshold, the predetermined power fall threshold, the number of padding data for the predetermined rising edge, and the number of padding data for the predetermined falling edge are obtained.

[0101] In S32, it is the signal sampling stage, specifically including the following S321, S322, and S323.

[0102] In S321, the rising edge section (also called the data padding section of the rising edge) and the falling edge section (also called the data padding section of the falling edge) within the current pulse period are determined. Specifically, based on the predetermined power rise threshold, the predetermined power fall threshold, the number of padding data for the predetermined rising edge, and the number of padding data for the predetermined falling edge, the rising edge section and the falling edge section within the current pulse period are respectively determined.

[0103] In S322, in the sampling process, the data bits corresponding to the rising edge section and the falling edge section in the sampling array are set (i.e., padded) to 0, the low level of the signal (also called the low level value of the signal), or the null signal (also called the null signal value) by the data padding method.

[0104] In S323, sampling data is read and sequentially output at times other than the rising edge section and the falling edge section.

[0105] In specific execution, as shown in the content of the dashed line part in Figure 7, the step S31 of obtaining the predetermined power rise threshold, the predetermined power fall threshold, the number of padding data for the predetermined rising edge, and the number of padding data for the predetermined falling edge by continuous sampling tests is S311 of continuously collecting the first high-frequency power signal including the first voltage V and the first current I at each of a plurality of sampling points, Based on the first voltage V and the first current I, it includes S312 for determining a predetermined power rise threshold, a predetermined power fall threshold, the number of padding data for the rising edge, and the number of padding data for the falling edge.

[0106] In specific execution, the step S321 of determining the rising edge section and the falling edge section within the current pulse period based on the predetermined power rise threshold, the predetermined power fall threshold, the number of padding data for the predetermined rising edge, and the number of padding data for the predetermined falling edge is S3211 for continuously collecting a second high-frequency power signal including the second voltage V and the second current I for each of a plurality of sampling points; S3212 for determining the power of each sampling point based on the second voltage V and the second current I; S3213 for determining the start point of the rising edge section and the number of padding data for the predetermined rising edge based on the power of each sampling point, the power rise threshold, and the number of padding data for the rising edge; It includes S3214 for determining the start point of the falling edge section and the number of padding data for the predetermined falling edge based on the power of each sampling point, the power fall threshold, and the number of padding data for the falling edge.

[0107] In specific execution, the step S312 of determining the predetermined power rise threshold, the predetermined power fall threshold, the number of padding data for the predetermined rising edge, and the number of padding data for the predetermined falling edge based on the first voltage V and the first current I is Calculating the power value of each sampling point by P = VI to obtain the first specific power value P after the zero potential r , the average power value P at the peak potential e and the first P after that e which is not the power value P d and taking P r as the predetermined power rise threshold of the power and P d as the predetermined power fall threshold.

[0108] In a specific implementation, based on the first voltage V and the first current I, the step S312 of determining the predetermined power rise threshold, the predetermined power fall threshold, the number of padding data of the predetermined rise edge, and the number of padding data of the predetermined fall edge is In a specific implementation, T r / T, based on which the number of padding data of the predetermined rise edge in the rise edge is determined, and T d / T, based on which the number of padding data of the predetermined fall edge in the fall edge can be determined, where T d is the fall edge time, T r is the rise edge time, and the step further includes that T is the sampling period. Here, the fall edge time and the rise edge time are obtained by those skilled in the art through testing or obtained by other known means, and detailed description is omitted here.

[0109] In a specific implementation, when the switch is switched and under the PULSE mode, it takes a certain time for the high-frequency power supply output to rise from the zero potential to the peak potential, which is called the rise process. Similarly, the process of dropping from the peak potential to the zero potential is called the fall process. Therefore, when the high-frequency power supply is continuously sampled, a ramp data segment is generated. The above rise process and fall process respectively correspond to the rise edge and fall edge of the ramp segment. These data are inaccurate for the high-frequency power supply and should be masked by corresponding methods. FIG. 8 is a schematic diagram of masking the data of the ramp segment by the data padding method. At the stages of the rise edge and the fall edge, by padding the corresponding number of data 0, the ramp data can be output as 0 by default, thereby achieving the purpose of masking the data of the ramp segment and avoiding the collection of inaccurate numerical values.

[0110] For the convenience of readers' understanding, the implementation method of the above high-frequency power supply signal collection method will be described below by way of specific examples.

[0111] First, determine the judgment threshold and the number of padding data.

[0112] In the sampling test stage, first, obtain multiple sets of data including lamp data through continuous sampling. Next, analyze the data. Here, the collected data is voltage V and current I, and the power value is calculated from P = VI. As shown in FIG. 9, the first specific power value after the zero potential is taken as the power rising threshold P r Let it be, and the power average value of the peak potential be P e Let it be, and the first power value that is not P e after the peak potential is taken as the falling threshold P d Let it be. The time from the rising threshold P r to the power average value P e of the peak potential is taken as the rising edge time T r Let it be, then the number of padding data can be determined. If the sampling period is T, the number of padding data is T r / T. Similarly, the time from the falling threshold P d to the zero potential is taken as the falling edge time T d Let it be, then the number of padding data is T d / T. The padded data is 0 and is used to mask the data of the lamp segment. Here, the specific power value is calculated and set by those skilled in the art according to the requirements of the process, and the detailed description is omitted here.

[0113] Next, the specific flow of the data padding method is of the following three types.

[0114] Type 1 When the high-frequency power supply is at zero potential, the collection board operates normally, collects data through the FIFO array, and the sampling period is T. In the ON or PULSE mode, the high-frequency power supply gradually rises from zero potential to the peak potential. Accordingly, when the leading bit of the FIFO array reaches point A of the rising edge, the power begins to rise. When the power value becomes higher than the rising threshold P r more, start limited data padding, pad 0 to the FIFO array, and the number is T r / T.

[0115] T r After padding T / T pieces of data 0 to the FIFO array, when the leading bit of the FIFO array reaches point B of the rising edge, end the limited data padding, start padding sampling data to the leading bit of the FIFO array, and initially pad the sampling data to the entire FIFO array until point C. Then, according to the FIFO theory, perform first-in, first-out of the data. The data output before the FIFO array reaches point C is still the limited data 0. The data at point B that was first input until point C begins to be output. Before reaching point E, the data output is normal output. At this time, the power value is the average power value P of the peak potential e is.

[0116] In the OFF or PULSE mode, the high-frequency power supply gradually drops from the peak potential to zero potential. Accordingly, when the leading bit of the FIFO array reaches point E of the falling edge, the power begins to drop. When the power value becomes lower than the falling threshold P d more, start limited data padding, pad 0 to the FIFO array, and the number is T d / T.

[0117] T d After padding T / T pieces of data 0 to the FIFO array, when the leading bit of the FIFO array reaches point F of the falling edge, end the limited data padding, start padding sampling data to the leading bit of the FIFO array. At this time, the high-frequency power supply is at zero potential.

[0118] The sampling flowchart based on the above data padding method is as shown in FIG. 10.

[0119] Type 2 Referring to FIG. 11, in the case of the ON or PULSE mode, the high-frequency power supply gradually rises from zero potential to the peak potential. Accordingly, when the leading bit of the FIFO array reaches point A of the rising edge, the power starts to rise, and when the power value reaches or exceeds the rising threshold P r limited data padding is started, and 0 is padded into the FIFO array.

[0120] The difference from Type 1 is that when the power value reaches or exceeds the falling threshold P d it means that the leading bit of the corresponding FIFO array is very close to or reaches point B of the rising edge. In this case, the limited data padding is terminated, and sampling data is started to be padded to the leading bit of the FIFO array. Generally, the number of 0 paddings at the rising edge corresponds to the interval time between the two thresholds. In some embodiments, it is T r / T or a number close to it.

[0121] After the limited data padding is terminated, sampling data is started to be padded to the leading bit of the FIFO array. Sampling data is initially padded throughout the FIFO array until point C. Then, according to the FIFO theory, the data is executed in a first-in first-out manner. The data output before the FIFO array reaches point C is still the limited data 0. The data at point B that was first input until point C starts to be output. Before reaching point E, the data output is normal output. At this time, the power value is the power average value P e of the peak potential.

[0122] In contrast, in the OFF or PULSE mode, the high-frequency power supply gradually drops from the peak potential to the zero potential. Accordingly, when the leading bit of the FIFO array reaches point E of the falling edge, the power starts to drop, and when the power value becomes lower than the falling threshold P d than, limited data padding is started, and 0 is padded into the FIFO array.

[0123] The difference from Type 1 is that when the power value reaches or becomes lower than the falling threshold P r r , it means that the leading bit of the corresponding FIFO array is very close to or has reached point F of the falling edge. In this case, the limited data padding is terminated, and sampling data is started to be padded into the leading bit of the FIFO array. Generally, the number of 0 paddings at the falling edge corresponds to the interval time between the two thresholds. In some embodiments, it is T d / T or a number close to it.

[0124] After the limited data padding is terminated, sampling data is started to be padded into the leading bit of the FIFO array. In this case, the high-frequency power supply is at the zero potential.

[0125] Type 3 can be regarded as a combination of Type 1 and Type 2.

[0126] Regarding the rising edge, when the leading bit of the FIFO array reaches point A of the rising edge, the power starts to rise. When the power value becomes higher than the rising threshold P r than, limited data padding is started, and 0 is padded into the FIFO array, and the number is T r / T.

[0127] When the power value becomes lower than the falling threshold P dWhen it is determined that the power value reaches or exceeds a certain level, it means that the leading bit of the corresponding FIFO array is very close to or has reached point B of the rising edge. In this case, the limited data padding ends, and sampling data starts to be padded to the leading bit of the FIFO array. Conversely, when the power value has not reached the falling threshold P d padding continues.

[0128] Regarding the falling edge, when the leading bit of the FIFO array reaches point E of the falling edge, the power starts to drop. When the power value becomes lower than the falling threshold P d limited data padding is started, 0 is padded to the FIFO array, and the number is T d / T.

[0129] When it is determined that the power value reaches or is lower than the rising threshold P r it means that the leading bit of the corresponding FIFO array is very close to or has reached point F of the rising edge. In this case, the limited data padding ends, and sampling data starts to be padded to the leading bit of the FIFO array. Conversely, when the power value has not reached the rising threshold P r padding continues.

[0130] The technical solution provided by this embodiment masks the data of the lamp segment by the data padding method, pads the corresponding number of data 0 at the stages of the rising edge and the falling edge, and can output the lamp data as 0 by default, thereby achieving the purpose of masking the data of the lamp segment, avoiding the collection of inaccurate numerical values, padding the corresponding number of limited data for the rising edge and the falling edge, and solving the problem in the related technology that the data read by the acquisition board at the lamp stage is inaccurate and affects the subsequent calculation of the power value and the resistance value.

[0131] Example 4 As shown in FIG. 12, an embodiment of the present invention an abnormal data section determination module 71 for determining a rising edge section and a falling edge section within the current pulse period, and a sampling data reset module 72 for setting data bits corresponding to the rising edge section and the falling edge section in the sampling array to 0, a low level of the signal, or a null signal, and further provides a high-frequency power supply signal collection device.

[0132] In some embodiments, as shown in the dashed portion in FIG. 12, the device further includes a FIFO array output module 73 for the sampling array to read and sequentially output sampling data outside the rising edge section and the falling edge section.

[0133] In some embodiments, setting the data bits corresponding to the rising edge section and the falling edge section in the sampling array to 0, a low level of the signal, or a null signal by the above sampling data reset module 72 means that the sampling data reset module 72 sets the data bits corresponding to the rising edge section and the falling edge section in the sampling array to 0, a low level of the signal, or a null signal by sampling delay or resetting the output of the sampling data.

[0134] In some embodiments, as shown in the dashed portion in FIG. 12, the sampling data reset module 72 within the rising edge section, at the time of data sampling, by delaying the sampling time, sets the data bits corresponding to the rising edge section in the sampling array to 0, a low level of the signal, or a null signal, or at the time of output of the sampling data, sets the data bits corresponding to the rising edge section in the sampling array to 0, a low level of the signal, or a null signal, and a rising edge anomaly processing sub-module 721; Within the falling edge section, during data sampling, by delaying the sampling time, the data bit corresponding to the falling edge section in the sampling array is set to 0, the low level of the signal, or a null signal, or, when outputting the sampling data, a falling edge abnormal processing sub-module 722 for setting the data bit corresponding to the falling edge section or the falling edge section in the sampling array to 0, the low level of the signal, or a null signal is provided.

[0135] In some embodiments, by the rising edge abnormal processing sub-module 721 mentioned above, in the sampling process, by delaying the sampling time, setting the data bit corresponding to the rising edge section in the sampling array to 0, the low level of the signal, or a null signal includes starting a first sampling delay from the rising edge start point within the current pulse period by the rising edge abnormal processing sub-module 721, and setting the data bit corresponding to the first sampling delay in the sampling array to 0, the low level of the signal, or a null signal. By the falling edge abnormal processing sub-module 722 mentioned above, by delaying the sampling time, setting the data bit corresponding to the falling edge section in the sampling array to 0, the low level of the signal, or a null signal includes starting a second sampling delay from the falling edge start point within the current pulse period, and setting the data bit corresponding to the second sampling delay in the sampling array to 0, the low level of the signal, or a null signal.

[0136] In some embodiments, by the above rising-edge anomaly processing sub-module 721, setting the data bit corresponding to the rising-edge section in the sampling array to 0, a low-level signal of the signal, or a null signal means that, simultaneously with the completion of signal sampling for the rising-edge end point within the current pulse period, determining first abnormal data which is the data within a first predetermined length before the data bit corresponding to the rising-edge end point in the sampling array, resetting the first abnormal data, setting it to a low-level signal of the signal or a null signal, and the first predetermined length includes the array length corresponding to the rising-edge section. By the above falling-edge anomaly processing sub-module 722, setting the data bit corresponding to the falling-edge section in the sampling array to 0, a low-level signal of the signal, or a null signal means that, simultaneously with the completion of signal sampling for the falling-edge end point within the current pulse period, determining second abnormal data which is the data within a second predetermined length before the data bit corresponding to the falling-edge end point in the sampling array, resetting the second abnormal data, setting it to a low-level signal of the signal or a null signal, and the second predetermined length includes the array length corresponding to the falling-edge section.

[0137] In some embodiments, by the above rising-edge anomaly processing sub-module 721, setting the data bit corresponding to the first sampling delay in the sampling array to 0, a low-level signal of the signal, or a null signal means ending the delay by setting the data bit corresponding to the first predetermined sampling time in the sampling array to 0, a low-level signal of the signal, or a null signal. By the above falling-edge anomaly processing sub-module 722, setting the data bit corresponding to the second sampling delay in the sampling array to 0, a low-level signal of the signal, or a null signal means ending the delay by setting the data bit corresponding to the second predetermined sampling time in the sampling array to 0, a low-level signal of the signal, or a null signal.

[0138] In some embodiments, setting the data bit corresponding to the first sampling delay in the sampling array to 0, a low-level signal of the signal, or a null signal by the rising-edge anomaly processing sub-module 721 described above means that the rising-edge anomaly processing sub-module 721 sets the data bit corresponding to the first predetermined array length in the sampling array to 0, a low-level signal of the signal, or a null signal to end the delay. Setting the data bit corresponding to the second sampling delay in the sampling array to 0, a low-level signal of the signal, or a null signal by the falling-edge anomaly processing sub-module 722 described above means that the falling-edge anomaly processing sub-module 722 sets the data bit corresponding to the second predetermined array length in the sampling array to 0, a low-level signal of the signal, or a null signal to end the delay.

[0139] In some embodiments, the abnormal data section determination module 71 a reference threshold value determination unit for determining a rising-edge section and a falling-edge section within the current pulse period based on a reference threshold value for representing a low level of the signal, a rising-edge time, and a falling-edge time, a peak threshold value determination unit for determining a rising-edge section and a falling-edge section within the current pulse period based on the reference threshold value and a peak threshold value for representing a high level of the signal, and a power determination unit for determining a rising-edge section and a falling-edge section within the current pulse period based on a power change of the sampling point.

[0140] In some embodiments, the first predetermined sampling time is equal to the rising-edge time, and the second predetermined sampling time is equal to the falling-edge time.

[0141] In some embodiments, the first predetermined array length and the second predetermined array length are determined based on a predetermined arithmetic relationship from the rising-edge time or the falling-edge time and the sampling period.

[0142] In a specific embodiment, the first predetermined array length is equal to the rising edge time / sampling period, the second predetermined array length is equal to the falling edge time / sampling period, or the first predetermined array length, the second predetermined array length, and the rising edge time / sampling period are equal, or the first predetermined array length, the second predetermined array length, and the falling edge time / sampling period are equal.

[0143] In some embodiments, as shown in the content of the dashed line part in FIG. 12, the abnormal data interval determination module 71 includes a rising edge start point acquisition sub-module 711 and a falling edge start point acquisition sub-module 712. The rising edge start point is the sampling point at which the power first becomes greater than the rising edge reference threshold within the current pulse period. The falling edge start point is the sampling point at which the power first becomes less than the falling edge reference threshold within the current pulse period.

[0144] In some embodiments, when the first predetermined array length, the second predetermined array length, and the rising edge time / sampling period are equal, and the rising edge time is greater than the falling edge time, the sampling data reset module 72 sets the data bits corresponding to the rising edge section and the falling edge section in the sampling array to 0, the low level of the signal, or the null signal by sampling delay or resetting the output of the sampling data. When the sampling data is output, the sampling data reset module 72 calculates the time of the third delay, which is the difference value between the rising edge time and the falling edge time, simultaneously with the completion of the signal sampling for the falling edge end point within the current pulse period, starts the third delay, determines the third abnormal data, which is the data within the third predetermined length before the data bit corresponding to the third delay end point in the sampling array, resets the third abnormal data, and sets it to the low level of the signal or the null signal at the end of the third delay. The third predetermined length includes the array length corresponding to the falling edge section.

[0145] The technical solution provided by this embodiment is to determine the rising edge section and the falling edge section within the current pulse period, set the data bits corresponding to the rising edge section and the falling edge section in the sampling array to 0, the low level of the signal or a null signal, mask the data of the abnormal segment by resetting the FIFO (First Input First Output) sampling array, that is, output the data of the switching time of the switch and the lamp segment in the PULSE mode to 0, and it is understandable that power is output only in the correct time zone other than the lamp.

[0146] Embodiment 5 As shown in FIG. 13, the embodiment of the present invention further provides a high-frequency power supply signal collection device including a signal sampling module 81. The signal sampling module 81 includes An abnormal data section determination module 811 (also called a padding section determination sub-module) for determining the rising edge section and the falling edge section within the current pulse period respectively based on a predetermined power rising threshold, a predetermined power falling threshold, the number of padding data of a predetermined rising edge, and the number of padding data of a predetermined falling edge, and A sampling data reset module 812 (also called a data padding sub-module) for setting the data bits corresponding to the rising edge section and the falling edge section in the sampling array to 0, the low level of the signal or a null signal during the sampling process.

[0147] In specific implementation, as shown by the dashed line part in FIG. 13, the signal sampling module 81 further includes An array output module 813 for collecting and outputting the data of the corresponding sampling points at times other than the rising edge section and the falling edge section.

[0148] In specific implementation, as shown by the dashed-line part in FIG. 13, the apparatus further includes a sampling test module 82 for obtaining a predetermined power rise threshold, a predetermined power fall threshold, the number of padding data of a predetermined rising edge, and the number of padding data of a predetermined falling edge by continuous sampling tests.

[0149] In specific implementation, as shown by the dashed-line part in FIG. 13, the sampling test module 82 includes a first signal collection sub-module 821 for continuously collecting first high-frequency power signals each including a first voltage V and a first current I at a plurality of sampling points, and a threshold determination sub-module 822 for determining a predetermined power rise threshold, a predetermined power fall threshold, the number of padding data of a predetermined rising edge, and the number of padding data of a predetermined falling edge based on the first voltage V and the first current I.

[0150] In specific implementation, the abnormal data section determination module 811 includes a second signal collection sub-module for continuously collecting second high-frequency power signals each including a second voltage V and a second current I at a plurality of sampling points, a sampling point power determination sub-module for determining the power of each sampling point based on the second voltage V and the second current I, a rising edge threshold data determination sub-module for determining the start point of a rising edge section and the number of padding data of a predetermined rising edge based on the power of each sampling point, the power rise threshold, and the number of padding data of a rising edge, and a falling edge threshold data determination sub-module for determining the start point of a falling edge section and the number of padding data of a predetermined falling edge based on the power of each sampling point, the power fall threshold, and the number of padding data of a falling edge.

[0151] In specific implementation, the threshold determination sub-module 822 determines a predetermined power rise threshold, a predetermined power fall threshold, the number of padding data of a predetermined rising edge, and the number of padding data of a predetermined falling edge based on the first voltage V and the first current I, which is The threshold determination sub-module 822 calculates the power value of each sampling point according to P = VI, and obtains the first specific power value P after the zero potential r and the average power value P of the peak potential e and the first P after that e and the power value P that is not d and takes P r as the predetermined power rise threshold and P d as the predetermined power fall threshold.

[0152] The threshold determination sub-module 822 determines the number of padding data of a predetermined rising edge in the rising edge based on T r / T, and determines the number of padding data of a predetermined falling edge in the falling edge based on T d / T, where T d is the falling edge time, T r is the rising edge time, and T is the sampling period.

[0153] The technical solution provided by this embodiment masks the data of the lamp segment by the data padding method, pads the corresponding number of data 0 at the rising edge and the falling edge stages, and can output the lamp data as 0 by default, thereby achieving the purpose of masking the data of the lamp segment, avoiding the collection of inaccurate numerical values, padding the corresponding number of limited data for the rising edge and the falling edge, and solving the problem that the data read by the acquisition board at the lamp stage in the related technology is inaccurate and affects the subsequent calculation of the power value and the resistance value.

[0154] Example 6 Based on the same technical concept, an embodiment of the present application further provides a computer device including a memory 1 and a processor 2. As shown in FIG. 14, a computer program is stored in the memory 1, and when the computer program is executed by the processor 2, the method for collecting high-frequency power supply signals described in any one of the above is realized.

[0155] Here, the memory 1 includes at least one type of readable storage medium, and the readable storage medium includes flash memory, hard disk, multimedia card, card-type memory (such as SD or DX memory, etc.), magnetic memory, magnetic disk, optical disk, etc. The memory 1 may be, in some embodiments, an internal storage unit of an OTT video service monitoring system such as a hard disk. The memory 1 may be, in some other embodiments, an external storage device of an OTT video service monitoring system such as a plug-in hard disk, Smart Media (registered trademark) Card (SMC), Secure Digital (SD) card, Flash Card, etc. Further, the memory 1 may simultaneously include an internal storage unit and an external storage device of the OTT video service monitoring system. The memory 1 may be used not only to store application software installed in the OTT video service monitoring system and various data such as the code of an OTT video service monitoring program, etc., but also to temporarily store data that has already been output or data to be output.

[0156] In some embodiments, the processor 2 may be a central processing unit (CPU), a controller, a microcontroller, a microprocessor, or other data processing chips, and is used to execute the program code stored in the memory 1 or process data, such as to execute an OTT video service monitoring program, etc.

[0157] The technical solution provided by this embodiment is to determine the rising edge section and the falling edge section within the current pulse period, set the data bits corresponding to the rising edge section and the falling edge section in the sampling array to 0, a low level of the signal, or a null signal, mask the data of the abnormal segment by resetting the FIFO (First Input First Output) sampling array, that is, output the data of the switching time of the switch and the lamp segment in the PULSE mode as 0, and it can be understood that power is output only in the correct time zone other than the lamp.

[0158] The disclosed embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the high-frequency power signal collection method described in the above method embodiment are realized. Here, the storage medium may be a volatile or non-volatile computer-readable storage medium.

[0159] The computer program product related to the high-frequency power signal collection method provided by the disclosed embodiment of the present invention includes a computer-readable storage medium in which program code is stored. The commands included in the program code can be used to execute the steps of the high-frequency power signal collection method described in the above method embodiment. Specifically, reference can be made to the embodiments of the above method, and detailed descriptions are omitted here.

[0160] The disclosed embodiments of the present invention further provide a computer program, and when the computer program is executed by a processor, any one of the above-described methods of the embodiments is realized. The computer program product can specifically be realized by hardware, software, or a combination thereof. In an alternative embodiment, the computer program product is specifically realized as a computer storage medium. In another alternative embodiment, the computer program product is specifically realized as a software product such as, for example, a Software Development Kit (SDK).

[0161] The same or similar parts in the above-described embodiments may be referred to each other. It is understandable that for the content not described in detail in some embodiments, the same or similar content in other embodiments may be referred to.

[0162] It should be noted that in the description of the present invention, terms such as "first", "second", etc. are only for the purpose of description and should not be understood as indicating or implying relative importance. Also, in the description of the present invention, unless otherwise specified, "a plurality" means at least two.

[0163] The description of any process or method shown in the flowchart or described herein in other ways may be understood to represent a module, segment, or part that includes code of one or more executable commands for realizing a specific logical function or process step. Further, the scope of the preferred embodiments of the present invention includes further realizations. Those skilled in the art may execute the functions without following the shown or considered order. For example, depending on the related functions, the functions may be executed substantially simultaneously or in the reverse order, which is understandable.

[0164] It should be understood that each part of the present invention can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, a plurality of steps or methods may be implemented by software or firmware stored in a memory and executed by a suitable command execution system. For example, when implemented by hardware, similar to another embodiment, it may be implemented by any one or a combination of technologies known in the art, such as a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, an application-specific integrated circuit having a suitable mixed logic gate circuit, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0165] A person skilled in the art can achieve the implementation of all or part of the steps included in the method of the above-described embodiments by instructing corresponding hardware through a program. The program may be stored in a computer-readable storage medium. It can be understood that when the program is executed, one or a combination of the steps according to the method embodiments is included.

[0166] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing module, may be individual physical units, or two or more units may be integrated into one module. The above integrated module may be implemented by hardware or by a software functional module. When the integrated module is implemented by a software functional module and is sold or used as an independent product, it may be stored in a computer-readable storage medium.

[0167] The storage medium mentioned above may be a read-only memory, a magnetic disk, an optical disk, or the like.

[0168] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described based on the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the exemplary descriptions for the above terms are not necessarily for the same embodiment or example. Also, the described specific features, structures, materials, or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0169] Although the embodiments of the present invention have been illustrated and described above, the above embodiments are exemplary and should not be understood as limiting the present invention. It is understandable that those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments without departing from the scope of the present invention.

Claims

1. Determining a rising edge section and a falling edge section within a current pulse period; Setting data bits corresponding to the rising edge section and the falling edge section in a sampling array to 0, a low level of a signal, or a null signal, wherein the method for collecting a high-frequency power supply signal is characterized by comprising the above steps.

2. The step of setting data bits corresponding to the rising edge section and the falling edge section in a sampling array to 0, a low level of a signal, or a null signal is a step of setting data bits corresponding to the rising edge section and the falling edge section in a sampling array to 0, a low level of a signal, or a null signal by means of a sampling delay or a reset of an output of sampling data, and the method for collecting a high-frequency power supply signal according to Claim 1 is characterized by this.

3. The step of setting data bits corresponding to the rising edge section and the falling edge section in a sampling array to 0, a low level of a signal, or a null signal by means of a sampling delay or a reset of an output of sampling data is as follows: Within the rising edge section, when sampling data, delaying the sampling time to set a data bit corresponding to the rising edge section in the sampling array to 0, a low level of a signal, or a null signal, or when outputting sampling data, setting a data bit corresponding to the rising edge section in the sampling array to 0, a low level of a signal, or a null signal; and Within the falling edge section, when sampling data, delaying the sampling time to set a data bit corresponding to the falling edge section in the sampling array to 0, a low level of a signal, or a null signal, or when outputting sampling data, setting a data bit corresponding to the falling edge section or the falling edge section in the sampling array to 0, a low level of a signal, or a null signal, and the method for collecting a high-frequency power supply signal according to Claim 2 is characterized by comprising the above steps.

4. By delaying the sampling time, the step of setting the data bit corresponding to the rising edge section in the sampling array to 0, a low level signal of the signal, or a null signal includes starting a first sampling delay from the rising edge start point within the current pulse period, and setting the data bit corresponding to the first sampling delay in the sampling array to 0, a low level signal of the signal, or a null signal. By delaying the sampling time, the step of setting the data bit corresponding to the falling edge section in the sampling array to 0, a low level signal of the signal, or a null signal includes starting a second sampling delay from the falling edge start point within the current pulse period, and setting the data bit corresponding to the second sampling delay in the sampling array to 0, a low level signal of the signal, or a null signal. The method for collecting a high-frequency power supply signal according to claim 3 is characterized by including the above steps.

5. The step of setting the data bit corresponding to the rising edge section in the sampling array to 0, a low level signal of the signal, or a null signal includes, simultaneously with the completion of signal sampling for the rising edge end point within the current pulse period, determining first abnormal data which is data within a first predetermined length before the data bit corresponding to the rising edge end point in the sampling array, resetting the first abnormal data, making it a low level signal of the signal or a null signal, and the first predetermined length being the array length corresponding to the rising edge section. The step of setting the data bit corresponding to the falling edge section in the sampling array to 0, a low level signal of the signal, or a null signal includes, simultaneously with the completion of signal sampling for the falling edge end point within the current pulse period, determining second abnormal data which is data within a second predetermined length before the data bit corresponding to the falling edge end point in the sampling array, resetting the second abnormal data, making it a low level signal of the signal or a null signal, and the second predetermined length being the array length corresponding to the falling edge section. The method for collecting a high-frequency power supply signal according to claim 3 is characterized by including the above steps.

6. The step of setting the data bit corresponding to the first sampling delay in the sampling array to 0, a low level of the signal, or a null signal is to set the data bit corresponding to the first predetermined sampling time in the sampling array to 0, a low level of the signal, or a null signal to end the delay. The step of setting the data bit corresponding to the second sampling delay in the sampling array to 0, a low level of the signal, or a null signal is to set the data bit corresponding to the second predetermined sampling time in the sampling array to 0, a low level of the signal, or a null signal to end the delay, which is characterized in that the method for collecting high-frequency power supply signals according to claim 4.

7. The step of setting the data bit corresponding to the first sampling delay in the sampling array to 0, a low level of the signal, or a null signal is to set the data bit corresponding to the first predetermined array length in the sampling array to 0, a low level of the signal, or a null signal to end the delay. The step of setting the data bit corresponding to the second sampling delay in the sampling array to 0, a low level of the signal, or a null signal is to set the data bit corresponding to the second predetermined array length in the sampling array to 0, a low level of the signal, or a null signal to end the delay, which is characterized in that the method for collecting high-frequency power supply signals according to claim 4.

8. The step of determining the rising edge section and the falling edge section within the current pulse period is determining the rising edge section and the falling edge section within the current pulse period according to a reference threshold for representing a low level of the signal, a rising edge time, and a falling edge time, or determining the rising edge section and the falling edge section within the current pulse period according to the reference threshold and a peak threshold for representing a high level of the signal, or including determining the rising edge section and the falling edge section within the current pulse period according to the power change of the sampling points, which is characterized in that the method for collecting high-frequency power supply signals according to claim 4.

9. The first predetermined sampling time is equal to the rising edge time, and the second predetermined sampling time is equal to the falling edge time, which is characterized in that the method for collecting high-frequency power supply signals according to claim 6.

10. The method for collecting a high-frequency power supply signal according to claim 7, wherein the first predetermined array length and the second predetermined array length are determined based on a predetermined arithmetic relationship from a rising edge time or a falling edge time and a sampling period.

11. The method for collecting a high-frequency power supply signal according to claim 10, wherein the first predetermined array length is equal to the rising edge time / sampling period, the second predetermined array length is equal to the falling edge time / sampling period, or the first predetermined array length, the second predetermined array length, and the rising edge time / sampling period are equal, or the first predetermined array length, the second predetermined array length, and the falling edge time / sampling period are equal.

12. The step of determining a rising edge section and a falling edge section within a current pulse period based on a power change of sampling points includes: obtaining a rising edge start point, which is a sampling point at which the power first becomes greater than a rising edge reference threshold within the current pulse period; obtaining a falling edge start point, which is a sampling point at which the power first becomes less than a falling edge reference threshold within the current pulse period. The method for collecting a high-frequency power supply signal according to claim 8 is characterized by including the above steps.

13. The method for collecting a high-frequency power supply signal according to any one of claims 1 to 12, further including a step of reading and sequentially outputting sampling data by the sampling array outside the rising edge section and the falling edge section.

14. When the first predetermined array length, the second predetermined array length, and the rising edge time / sampling period are equal, and the rising edge time is greater than the falling edge time, the step of setting data bits corresponding to the rising edge section and the falling edge section in the sampling array to 0, a low level of a signal, or a null signal by sampling delay or resetting the output of sampling data includes: When outputting sampling data, at the same time as the completion of signal sampling for the falling edge end point within the current pulse period, calculate the time of the third delay, which is the difference value between the rising edge time and the falling edge time, start the third delay, and at the end of the third delay, determine the third abnormal data, which is the data within the third predetermined length before the data bit corresponding to the end point of the third delay in the sampling array, reset the third abnormal data to a low level or a null signal of the signal, and the third predetermined length is the array length corresponding to the falling edge section. The method for collecting a high-frequency power supply signal according to claim 11 is characterized by including this step.

15. The step of determining the rising edge section and the falling edge section within the current pulse period is characterized by including the step of determining the rising edge section and the falling edge section within the current pulse period respectively based on a predetermined power rising threshold, a predetermined power falling threshold, the number of padding data for a predetermined rising edge, and the number of padding data for a predetermined falling edge. The method for collecting a high-frequency power supply signal according to claim 1 is

16. Before the step of determining the rising edge section and the falling edge section within the current pulse period, further including the step of obtaining the predetermined power rising threshold, the predetermined power falling threshold, the number of padding data for a predetermined rising edge, and the number of padding data for a predetermined falling edge by continuous sampling tests. The method for collecting a high-frequency power supply signal according to claim 15 is

17. The step of obtaining the predetermined power rising threshold, the predetermined power falling threshold, the number of padding data for a predetermined rising edge, and the number of padding data for a predetermined falling edge by continuous sampling tests is characterized by including the step of continuously collecting first high-frequency power supply signals each including a first voltage V and a first current I at a plurality of sampling points, and the step of determining the predetermined power rising threshold, the predetermined power falling threshold, the number of padding data for a predetermined rising edge, and the number of padding data for a predetermined falling edge based on the first voltage V and the first current I. The method for collecting a high-frequency power supply signal according to claim 16 is ​

18. The step of determining the rising edge section and the falling edge section within the current pulse period respectively based on the predetermined power rising threshold, the predetermined power falling threshold, the number of padding data of the predetermined rising edge, and the number of padding data of the predetermined falling edge is as follows: continuously collecting a second high-frequency power signal including a second voltage V and a second current I at each of a plurality of sampling points; determining the power of each sampling point based on the second voltage V and the second current I; determining the start point of the rising edge section and the number of padding data of the predetermined rising edge based on the power of each sampling point, the power rising threshold, and the number of padding data of the rising edge; determining the start point of the falling edge section and the number of padding data of the predetermined falling edge based on the power of each sampling point, the power falling threshold, and the number of padding data of the falling edge. The method for collecting a high-frequency power signal according to claim 16 is characterized by including the above steps.

19. The step of determining the predetermined power rising threshold, the predetermined power falling threshold, the number of padding data of the predetermined rising edge, and the number of padding data of the predetermined falling edge based on the first voltage V and the first current I is as follows: calculating the power value of each sampling point by P = VI, obtaining the first specific power value Pr after the zero potential and the power value Pd that is not the first Pe after the power average value Pe of the peak potential, using Pr as the predetermined power rising threshold, and using Pd as the predetermined power falling threshold. The method for collecting a high-frequency power signal according to claim 17 is characterized by including the above steps.

20. The step of determining the predetermined power rising threshold, the predetermined power falling threshold, the number of padding data of the predetermined rising edge, and the number of padding data of the predetermined falling edge based on the first voltage V and the first current I is as follows: Determine the number of padding data of the predetermined rising edge in the rising edge based on Tr / T, and determine the number of padding data of the predetermined falling edge in the falling edge based on Td / T, where Td is the falling edge time, Tr is the rising edge time, and T is the sampling period, further comprising the step of: The method for collecting a high-frequency power supply signal according to claim 19.

21. An abnormal data section determination module for determining a rising edge section and a falling edge section within the current pulse period, A sampling data reset module for setting data bits corresponding to the rising edge section and the falling edge section in the sampling array to 0, a low level of the signal, or a null signal. The high-frequency power supply signal collection device is characterized by comprising:

22. Comprising a processor, a memory, and a bus, wherein computer-readable commands executable by the processor are stored in the memory. When the computer device operates, communication occurs between the processor and the memory via the bus. When the computer-readable commands are executed by the processor, the method for collecting a high-frequency power supply signal according to any one of claims 1 to 20 is implemented. A computer device is characterized by this.

23. A computer-readable storage medium characterized in that a computer program is stored which, when executed by a processor, implements the method for collecting a high-frequency power supply signal according to any one of claims 1 to 20.

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