Display pixel with an electroluminescent source

Abstract

The present disclosure comprises a light-emitting circuit (LEDS) comprising at least a first electroluminescent source, a controllable current source (82) for driving the light-emitting circuit with a current pulse (I_LED), and a driver circuit (70) for controlling the current source, the driver circuit being configured to receive a digital signal (Data) and control the current source to supply a current pulse modulated by pulse-width modulation and a current pulse modulated by pulse-amplitude modulation based on the bits of the digital signal, for a display pixel (12 i,j ) of a display screen.

Description

Technical Field

[0001] The present disclosure relates to display pixels comprising an electroluminescent source, such as a light-emitting diode, and to display screens having such display pixels.

Background Art

[0002] Pixels of an image correspond to unit elements of the image displayed by a display screen. For the display of a color image, the display screen generally comprises at least three components, also called display sub-pixels, each emitting a light radiation, called an image pixel color component of a substantially single color (e.g., red, green, and blue), for the display of each pixel of the image. The superposition of the image pixel color components emitted by the three display sub-pixels provides the observer with a colored sensation corresponding to the pixel of the displayed image. In this case, the assembly formed by the three display sub-pixels used for the display of a pixel of the image is called a display pixel of the display screen. Each display sub-pixel may comprise a light source, in particular a light-emitting diode.

[0003] The display pixels may be dispersed in an array, and each display pixel is located at the intersection of a row (or line) and a column of the array. Generally, each row of display pixels is selected sequentially, and the display pixels of the selected row are programmed to display the desired image pixels.

[0004] An active array, as opposed to an array said to be passive, is a screen drive architecture that enables all pixel rows to be maintained active throughout the duration of an image, in which each row is active only for a time T = Tframe / M, where Tframe is the duration of the display of the entire image and M is the number of lines of the screen. Thereby, the luminance of the display screen can be increased. Further, it is possible to send low voltage or current levels on the array control lines, thereby enabling a larger data flow to be displayed.

[0005] Pulse width modulation, also known as PWM (the English acronym for Pulse Width Modulation), is known to control electroluminescent sources such as light-emitting diodes. This type of control consists of circulating a continuous current pulse of a certain intensity in a light-emitting diode, the pulses are repeated periodically, and the duty cycle determines the light intensity emitted by the light-emitting diode. With such control, there is an advantage that the light-emitting diode can be operated at its optimum operating point where the efficiency of the light-emitting diode (equal to the ratio of the light power emitted by the light-emitting diode to the power consumed by the light-emitting diode) is maximized.

[0006] Color depth, also known as bit depth, is the number of bits used to code the color of each image pixel color component of a single display pixel. Usually, it is desirable to have a high color depth. However, the implementation of pulse width modulation with a high color depth can lead to a complex display driving architecture, especially since the generation of pulse width modulation pulses may require the generation of a large number of clock signals as the color depth increases. Summary of the Invention Problems to be Solved by the Invention

[0007] An object of an embodiment is to provide a display pixel including an electroluminescent source and a display screen including such display pixels that overcome all or part of the drawbacks of existing display pixels including an electroluminescent source and display screens including such display pixels.

[0008] Another object of an embodiment is to be controlled by a pulse width modulation display pixel having a high color depth.

[0009] Another object of an embodiment is to shorten the duration of the period for the control of the electroluminescent source. Means for Solving the Problems

[0010] One embodiment comprises a light emitting circuit including at least a first electroluminescent source, a controllable current source for driving the light emitting circuit with current pulses, and a driver circuit for controlling the current source. The driver circuit receives a digital signal including a first bit and one second bit different from the first bit, and is configured to control the current source to supply a current pulse modulated by pulse width modulation and a current pulse modulated by pulse amplitude modulation based on the bits of the digital signal, providing a display pixel for a display screen. The driver circuit is configured to instruct the current source to provide a current that is the sum of a continuous first current pulse having a first duration depending on a certain intensity and the first bit of the digital signal, and a second current pulse having a second duration indicated by the second bit of the digital signal and having a certain second duration, wherein the sum of the first durations is less than or equal to the second duration. This advantageously makes it possible to reduce the number of clock signals.

[0011] Regarding control using only pulse width modulation, according to this embodiment, there is an advantage that the duration of the control period of the electroluminescent source can be shortened while maintaining the same color depth.

[0012] According to an embodiment, the current source is configured to generate continuous first current pulses while the second current pulse is being generated.

[0013] According to an embodiment, the bits of the digital signal are ranked from the most significant bit to the least significant bit, and the intensity of the second current pulse depends on the rank of the second bit of the digital signal.

[0014] According to an embodiment, the second bit includes the most significant bit of the digital signal. This makes it possible to change the current intensity in the electroluminescent source only for high values of the digital signal. In particular, when the electroluminescent source comprises a three-dimensional light-emitting diode, this makes it possible to limit the wavelength shift of the light emitted by the light-emitting diode, which may occur when the intensity of the current circulating through the light-emitting diode changes, only to high values of the digital signal.

[0015] According to an embodiment, the digital signal includes a third bit that is different from the first bit and the second bit. The driver circuit is configured to instruct a controllable current source to supply a current that is the sum of a continuous first current pulse, a second current pulse, and a third current pulse indicated by the third bit of the digital signal and having a second duration.

[0016] According to an embodiment, the current source is configured to generate the third current pulse simultaneously with the second current pulse. According to an embodiment, the intensity of the third current pulse depends on the rank of the third bit of the digital signal and is different from the intensity of the second current pulse. According to an embodiment, the third bit is the second most significant bit of the digital signal.

[0017] This advantageously makes it possible to further reduce the number of clock signals required to perform pulse amplitude modulation, and thus to shorten the duration of the control period of the electroluminescent source.

[0018] According to an embodiment, the digital signal includes a fourth bit that is different from the first bit, the second bit, and the third bit. The driver circuit is configured to instruct a controllable current source to supply a current that is the sum of a continuous first current pulse, a second current pulse, a third current pulse, and a fourth current pulse indicated by the fourth bit of the digital signal and having a second duration.

[0019] According to an embodiment, the current source is configured to generate a fourth current pulse simultaneously with the second current pulse. According to an embodiment, the intensity of the fourth current pulse depends on the rank of the fourth bit of the digital signal and is different from the intensity of the second current pulse and the intensity of the third current pulse. According to an embodiment, the fourth bit is the third most significant bit of the digital signal.

[0020] This advantageously makes it possible to further reduce the number of clock signals required to perform pulse amplitude modulation, and thus to shorten the duration of the control period of the electroluminescent source.

[0021] According to an embodiment, the driver circuit comprises a first storage circuit for storing the first bit of the digital signal, and the first storage circuit comprises a shift register clocked by a pulse width modulation clock signal. The structure of the driver circuit of the display pixel is advantageously simplified and can take up a reduced silicon area when the driver circuit is manufactured integrally.

[0022] According to an embodiment, the driver circuit comprises a second storage circuit for storing the second bit of the digital signal, and continuously receives the first bit from a shift register controlled by a control signal and clocked by a pulse width modulation clock signal, receives the second bit from the second storage circuit, and controls a controllable current source from the first bit and the second bit continuously received when the control signal is in a given state. configured logic circuit. This advantageously makes it possible to control the duration of the display phase.

[0023] According to an embodiment, the light-emitting circuit includes a first group of electroluminescent sources having a first number of electroluminescent sources and a second group of electroluminescent sources having a second number of electroluminescent sources. The controllable current source includes a first controllable current source indicated by a first bit and connected to the electroluminescent sources of the first group, and a second controllable current source indicated by a second bit and connected to the electroluminescent sources of the second group. Thereby, the current density in each electroluminescent source can be made the same.

[0024] According to an embodiment, the controllable current source is: a first MOS transistor connected to the light-emitting circuit and a first switch connected to the first MOS transistor, and a second MOS transistor connected to the light-emitting circuit and a second switch connected to the second MOS transistor and includes.

[0025] The structure of the controllable current source of the display pixel is advantageously simplified.

[0026] According to an embodiment, the logic circuit is configured to continuously control the first switch from each first bit and control the second switch based on the second bit.

[0027] According to an embodiment, the driver circuit is configured to control only the first switch based on some of the first bits and control both the first switch and the second switch based on the other of the first bits.

[0028] According to an embodiment, an electroluminescent source among the first group of electroluminescents is connected to a first MOS transistor, and an electroluminescent source of the second group is connected to a second MOS transistor. Thereby, the current density in each electroluminescent source can be made the same.

[0029] According to an embodiment, a light-emitting circuit includes an electroluminescence source of a third group having a third number of light-emitting diodes, and a control source includes a third MOS transistor connected to the electroluminescent source of the third group and a third switch connected to the third MOS transistor, where the first number is equal to the second number and the third number is greater than the second number.

[0030] One embodiment also provides a display screen including an array of display pixels as defined above.

[0031] According to an embodiment, the display screen includes a circuit configured to change a supply voltage of the display pixels according to a second bit. Thereby, there is an advantage that the power consumption of the display can be reduced with an easy-to-use instruction.

Brief Description of the Drawings

[0032] The foregoing features and advantages, as well as others, are described in detail in the following description of specific embodiments given by way of example and not limitation with reference to the accompanying drawings.

[0033]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Mode for Carrying Out the Invention

[0034] Similar features are designated by similar reference numerals in the various figures. In particular, structural and / or functional features that are common among the various embodiments may have the same reference numeral and may be given the same structural, dimensional, and material characteristics. For clarity, only the steps and elements useful for understanding the embodiments described in this specification are illustrated and described in detail.

[0035] Unless otherwise indicated, when referring to two elements connected to each other, this means a direct connection without intermediate elements other than conductors, and when referring to two elements coupled to each other, this means that these two elements can be connected or that they can be coupled through one or more other elements. Also, a signal that alternates between a first steady state, for example a low state denoted as "0", and a second steady state, for example a high state denoted as "1", is called a "binary signal". The high and low states of different binary signals in the same electronic circuit may be different. In practice, a binary signal may correspond to a voltage or current that is not completely constant in the high or low state. Also, in the following description, the source and drain of a MOS transistor are referred to as the "power terminals" of an insulated gate field effect transistor or MOS transistor.

[0036] Also, unless otherwise indicated, when referring to the voltage of a conductive pad, the difference between the potential in the conductive pad and the reference potential (for example, a ground potential equivalent to 0 V) is considered.

[0037] Unless otherwise specified, the expressions "about," "approximately," "substantially," and "on the order of" mean within 10%, preferably within 5%. Further, the expression "substantially constant" means changing by less than 10% over time with respect to the reference value.

[0038] Pulse-width modulation driving of an electroluminescent source, such as a light-emitting diode, consists of circulating continuous pulses of a current having a constant intensity with a varying duration in the electroluminescent source. Pulse-amplitude modulation driving of an electroluminescent source, such as a light-emitting diode, consists of circulating continuous pulses of a current having a constant duration with a varying intensity in the electroluminescent source.

[0039] In the following specification, embodiments regarding display pixels including light-emitting diodes are disclosed. However, these embodiments can be implemented for display pixels including electroluminescent sources different from light-emitting diodes, such as organic light-emitting diodes, field-induced polymer electroluminescent components, and laser diodes.

[0040] In the following specification, embodiments for a color display screen including color display pixels are disclosed, and each display pixel includes a light-emitting diode adapted to emit different-color radiation. However, these embodiments are also applicable to a monochromatic display screen including monochromatic display pixels, and each monochromatic display pixel includes one or more light-emitting diodes adapted to emit radiation of a single color.

[0041] 1 partially and diagrammatically illustrates an example of a display screen 10. The display screen 10 comprises display pixels 12 arranged, for example, in M rows and N columns. i,j where M is an integer varying from 1 to 8,000, N is an integer varying from 1 to 16,000, i is an integer varying from 1 to M, and j is an integer varying from 1 to N. By way of example, in FIG. 1, M and N are equal to 6. Each display pixel 12 i,j Electrode 14 i via a low reference potential Gnd, e.g., to the source of ground, and via electrode 16 j 1. The electrode 14 is coupled to the source of the high reference potential Vcc via i are shown aligned along rows in FIG. 1, and electrodes 16 j are shown aligned along a column in FIG. 1, although an inverse layout is also possible. The power supply voltage of the display screen corresponds to a voltage between a high reference potential Vcc and a low reference potential Gnd. The power supply voltage depends, inter alia, on the arrangement of the light emitting diodes and on the technology for manufacturing the light emitting diodes. By way of example, the power supply voltage may be in the order of 4V to 5V.

[0042] For each row, display pixels 12 in the row i,j At least one row electrode 18 i For each column, the display pixels 12 in the column i,j At least one column electrode 20 j The display screen 10 is coupled to row electrodes 18. i 18 is coupled to the row electrode 18 i The display screen 10 comprises a selection circuit 22 adapted to transmit signals on the column electrodes 20. j , and is coupled to column electrode 20 j The selection circuit 22 and the control circuit 24 are controlled by a circuit 26 which may, for example, comprise a microprocessor.

[0043] FIG. 2 shows a display pixel 12 of a display screen 10. i,jAn example of a block diagram is shown. For a color display screen, display pixel 12 i,j includes a light-emitting circuit LEDS having at least three light-emitting diodes that emit different colored emissions, and a single light-emitting diode LED is shown in FIG. 2. Each light-emitting diode LED is coupled in series to a controllable current source CS having, for example, a MOS transistor. In this example, for each light-emitting diode LED, the anode of the light-emitting diode LED receives the high reference potential Vcc, the cathode of the light-emitting diode LED is coupled to the terminal of the controllable current source CS, for example, and the other terminal of the controllable current source CS receives the low reference potential Gnd.

[0044] Display pixel 12 i,j further includes a driver circuit 40 for driving the controllable current source CS. The driver circuit 40 may particularly include electronic components such as MOS transistors. The driver circuit 40 includes a memory circuit 48 (color data register) clocked by a clock signal Clk and configured to store digital color signals R, G, B based on the received digital data Data. The digital color signals R, G, B each include a number of bits NB and represent the image pixel color components to be displayed. The driver circuit 40 includes a circuit 50 (LED driver) configured to control the controllable current source CS coupled to the light-emitting diode LED with the digital color signals R, G, B, and signals I_red, I_green, and I_blue obtained from the signal PWM.

[0045] FIG. 3 shows a timing diagram of signals I_red_1, I_red_2, I_red_3, and I_red_4 corresponding to the signal I_red provided by the circuit 50 of FIG. 2 and the signal PWM for the display of four different color signals R. According to an embodiment, display pixel 12 i,j i,j ​The light-emitting diode LED is controlled by pulse-width modulation. For this purpose, during the display phase, the signal PWM represents successive pulses in the logic state "1" that rate the operation of circuit 50 for controlling the light-emitting diode LED by pulse-width modulation. The number of successive pulses corresponds to the number of bits NB of each digital color signal R, G, and B.

[0046] As an example, when the current source CS corresponds to a MOS transistor, this transistor is turned on or off at the rate of the pulses of the signal PWM according to the logic value "0" or "1" of each bit of the color signal R, G, or B starting from the most significant bit, and this transistor is maintained on or off until the next pulse of the signal PWM. The duration between two successive pulses of the signal PWM is divided by 2 each time, whereby the total duration during which the light-emitting diode is on depends on the value of the color signal R, G, or B. The successive pulses of the signal PWM can be repeated until the display of another image pixel. In that case, the successive pulses of the signal PWM form a display period, and the display phase includes more than one display period.

[0047] In FIG. 3, as an example, the number of pulses in the display period of the signal PWM is equal to 7, and only one display period is shown. The signal I_red_1 is obtained for the display of the image pixel color component corresponding to the color signal R equal to "1010101". The signal I_red_2 is obtained for the display of the image pixel color component corresponding to the color signal R equal to "0101010". The signal I_red_3 is obtained for the display of the image pixel color component corresponding to the color signal R equal to "1111111". The signal I_red_4 is obtained for the display of the image pixel color component corresponding to the color signal R equal to "0000000".

[0048] The signal PWM can be generated from a periodic clock signal. The number of clock signals required to generate the signal PWM increases along with the number of bits NB of the color signals R, G, and B. Generating a large number of clock signals may lead to a complex circuit. Further, from the first row to the last row of the display screen, the image pixels of the new image to be displayed are continuously displayed.

[0049] FIG. 4 shows the timing diagram of the signal PWM received by the display pixels of the first row (signal PWM j ) of the display screen and the subsequent second row (signal PWM j+1 ). The signal PWM j+1 corresponds to the signal PWM j shifted by a duration H equal to Tframe / M, where Tframe is the duration of the display of the entire image and M is the number of rows of the display screen. The shift H of the signal PWM from the first row to the subsequent second row can be obtained by providing it to the subsequent latch before providing the signal PWM j to the second row.

[0050] Furthermore, the power consumed by the display screen 10 when the light-emitting diodes of each display pixel 12 i,j are controlled by pulse-width modulation does not depend on the luminance of the displayed image. When the luminance of the displayed image decreases, it is desirable that the power consumed by the display screen decreases.

[0051] According to an embodiment, each display pixel of the display screen is configured to drive a light-emitting circuit by pulse-amplitude modulation (PAM) for some bits of the digital color signal and by pulse-width modulation (PWM) for other bits of the digital color signal for the display of the image pixel color components corresponding to the digital color signal. According to an embodiment, the pulse-amplitude modulation is used for at least the most significant bit (MSB) of the digital color signal and, in some cases, one or more consecutive bits directly adjacent to the MSB.

[0052] According to an embodiment, for pulse width modulation, a current pulse having a constant intensity and a variable first duration is supplied to the light emitting diode for each display phase period. According to an embodiment, for pulse amplitude modulation, a current pulse having a constant second duration and a variable intensity is supplied to the light emitting diode for each display phase period. The second duration of the pulse of the pulse amplitude modulation is equal to the full duration Tcycle of the display phase period of the pulse width modulation. According to an embodiment, at each time during the display period of the pulse width modulation, the intensity of the current supplied to the light emitting circuit is equal to the sum of the intensity of the current resulting from the pulse amplitude modulation and the intensity of the current resulting from the pulse width modulation. According to an embodiment, the full duration Tcycle of the display phase period is also equal to the sum of the first durations of the current pulses by pulse width modulation when all bits of the digital color signal used for pulse width modulation are replenished by the duration associated with the least significant bit (LSB) to a "1".

[0053] According to an embodiment, pulse amplitude modulation is used for the most significant bit (MSB) of the digital color signal and the second most significant bit (MSB - 1) of the digital color signal which is the bit following the MSB, and pulse width modulation is used for the other bits of the digital color signal. According to an embodiment, when only the MSB of the digital color signal is equal to "1", the intensity of the current supplied to the light emitting circuit is twice the intensity of the current supplied to the light emitting circuit when only the MSB - 1 of the digital color signal is equal to "1". According to an embodiment, the intensity of the current supplied to the light emitting circuit when only the MSB - 1 of the digital color signal is equal to "1" is equal to the intensity of the current supplied to the light emitting circuit for the pulse of the pulse width modulation when the MSB, MSB - 1 and MSB - 2 are equal to "0".

[0054] According to an embodiment, pulse amplitude modulation is used for the MSB of the digital color signal, the MSB-1 of the digital color signal, and the third most significant bit (MSB-2) of the digital color signal which is the bit following MSB-1, and pulse width modulation is used for the other bits of the digital color signal. According to an embodiment, the intensity of the current supplied to the light emitting circuit when only the MSB of the digital color signal is equal to "1" is twice the intensity of the current supplied to the light emitting circuit when only the MSB-1 of the digital color signal is equal to "1", and is equal to four times the intensity of the current supplied to the light emitting circuit when only the MSB-2 of the digital color signal is equal to "1". According to an embodiment, the intensity of the current supplied to the light emitting circuit when only the MSB-2 of the digital color signal is equal to "1" is equal to the intensity of the current supplied to the light emitting circuit for the pulse of the pulse width modulation when the MSB, MSB-1, and MSB-2 are equal to "0".

[0055] FIGS. 5 and 6 show examples of timing diagrams of the current I_LED supplied to the light emitting circuit of an embodiment of the display pixel to display the image pixel color components encoded on a digital color signal having 10 bits for three different digital color signals. The reference sign I_MSB indicates a part of the intensity of the current I_LED by pulse amplitude modulation when the MSB is equal to "1". The reference sign I_MSB-1 indicates a part of the intensity of the current I_LED by pulse amplitude modulation when the MSB-1 is equal to "1". The reference sign I_MSB-2 indicates a part of the intensity of the current I_LED by pulse amplitude modulation when the MSB-2 is equal to "1". The reference sign I_PWM indicates a part of the intensity of the current I_LED by pulse width modulation. In FIGS. 5 and 6, the duration of the pulse of the pulse amplitude modulation is equal to the full duration of the display phase period Tcycle of the pulse width modulation.

[0056] In FIG. 5, pulse amplitude modulation is used for the MSB, MSB-1, and MSB-2 of the digital color signal, and pulse width modulation is used for the other 7 bits of the digital color signal. The first digital color signal is equal to "1110101010". The second digital color signal is equal to "0010101010". The third digital color signal is equal to "0000101010".

[0057] In FIG. 6, pulse amplitude modulation is used for the MSB and MSB-1 of the digital color signal, and pulse width modulation is used for the other 8 bits of the digital color signal. The first digital color signal is equal to "1101010100". The second digital color signal is equal to "0101010100". The third digital color signal is equal to "0001010100".

[0058] FIG. 7 shows an embodiment of the block diagram of the display pixel 12 of FIG. 1 configured to implement the driving of the light emitting diode previously disclosed in connection with FIGS. 5 and 6. i,j of the block diagram.

[0059] display pixel 12 i,jIt includes all the elements previously disclosed in connection with FIG. 2, except that the driver circuit 40 and the controllable current source CS are replaced by a driver circuit 70 and a current driver circuit 82, respectively. The driver circuit 70 may in particular comprise electronic components such as MOS transistors. According to an embodiment, the driver circuit 70 comprises two memory circuits 72 and 74 configured to store bits of a digital color signal representing the image pixel color component to be displayed based on the received data Data for each image pixel color component. The first memory circuit 72 (shift register for lower bits (PWM)) is a shift register that stores the number of bits LB of the digitally color signal subjected to pulse width modulation. The second memory circuit 74 (shift register for upper bits (PAM)) is a shift register that stores the number of bits HB of the digitally color signal subjected to pulse amplitude modulation. According to an embodiment, for each image pixel color component, the digital color signal includes NB bits, among which, LB bits start from the least significant bits (LSB) stored in the first memory circuit 72 and used for pulse width modulation, and HB bits start from the most significant bits (MSB) stored in the second memory circuit 74 and used for pulse amplitude modulation.

[0060] The driver circuit 70 further comprises a first shift circuit 76 (switching circuit) that receives consecutive bits of the data Data, a write clock signal Clk_wr, and a signal PWM, provides bits of the data Data, and writes the clock signal Clk_wr or the signal PWM to the first memory circuit 72. The first shift circuit 76 is controlled by a binary signal Line. The driver circuit 70 further comprises a second shift circuit 78 (switching circuit) that receives the write clock signal Clk_wr and bits of the data from the first memory circuit 72 and provides the write clock signal Clk_wr and bits of the data to the second memory circuit 74. The second shift circuit 78 is controlled by a binary signal Line.

[0061] The driver circuit 70 further includes a logic circuit 80 (AND gate (HB + 1)) that receives a binary signal CPWM from the first memory circuit 72 and a digital signal CPAM from the second memory circuit 74. The digital signal CPAM has the number of bits HB. The logic circuit 80 is controlled by the binary signal Ctrl.

[0062] The current driver circuit 82 supplies a current I_LED to the light emitting circuit LEDS. The logic circuit 80 is configured to provide a binary signal CPWM' and a digital signal CPAM' to the current driver circuit 82. When the signal Ctrl is controlled, the binary signal CPWM' can be equal to the binary signal CPWM, and the digital signal CPAM' can be equal to the digital signal CPAM. The current driver circuit 82 may include a digital - to - analog converter (DAC).

[0063] FIG. 8 shows a more detailed embodiment of the driver circuit 70 of FIG. 7 when, as an example, HB is equal to 3.

[0064] The first memory circuit 72 includes consecutive D - flip - flops FF1 to FF LB The number of D - flip - flops FF1 to FF LB is equal to LB. The Q output of the flip - flop FF LB provides the signal CPWM. The second memory circuit 74 is three flip - flops FF MSB-2 FF MSB-1 and FF MSB which are HB consecutive flip - flops shown as an example in FIG. 8. The Q output of the flip - flop FF MSB-2 provides the binary signal CPAM MSB-2 The Q output of the flip - flop FF MSB-1 provides the binary signal CPAM MSB-1 The Q output of the flip - flop FF MSB provides the binary signal CPAM MSB The binary signals CPAM MSB-2 CPAM MSB-1 and CPAM MSB form the digital signal CPAM shown in FIG. 7.

[0065] The first shift circuit 76 includes a first 2-to-1 multiplexer MUX1 and a second 2-to-1 multiplexer MUX2, and the second shift circuit 78 includes a third 2-to-1 multiplexer MUX3 and a fourth 2-to-1 multiplexer MUX4. Each of the first multiplexer MUX1, the second multiplexer MUX2, the third multiplexer MUX3, and the fourth multiplexer MUX4 is controlled by a signal Line, and includes a first input, a second input, and an output. The output is connected to the first input when the signal Line is at a first value, for example, "0", and is connected to the second input when the signal Line is at a second value, for example, "1".

[0066] The first input of the first multiplexer MUX1 is connected to the Q output of the flip-flop FF LB of the first memory circuit 72. The second input of the first multiplexer MUX1 receives the signal Data, and the output of the first multiplexer MUX1 is connected to the D input of the flip-flop FF1 of the first memory circuit 72. The first input of the second multiplexer MUX2 receives the signal PWM. The second input of the second multiplexer MUX2 receives the write clock signal Clk_wr, and the output of the second multiplexer MUX2 is connected to the clock inputs of each of the flip-flops FF1~FF LB of the first memory circuit 72.

[0067] The first input of the third multiplexer MUX3 receives the reference potential Gnd. The second input of the third multiplexer MUX3 is connected to the Q output of the flip-flop FF LB of the first memory circuit 72, and the output of the third multiplexer MUX3 is connected to the D input of the flip-flop FF MSB-2 of the second memory circuit 74. The first input of the fourth multiplexer MUX4 receives the reference potential Gnd. The second input of the fourth multiplexer MUX4 receives the write clock signal Clk_wr, and the output of the fourth multiplexer MUX4 is connected to each of the flip-flops FF MSB-2 、FF MSB-1 、and FFMSB is connected to the clock input.

[0068] The logic circuit 80 includes HB + 1 AND-type logic gates AND PWM , AND MSB-2 , AND MSB-1 , AND MSB . Each gate AND PWM , AND MSB-2 , AND MSB-1 , AND MSB has a first input for receiving the signal Ctrl. The second input of the gate AND PWM is connected to the Q output of the flip-flop FF of the first memory circuit 72 LB . The second inputs of the gates AND MSB-2 , AND MSB-1 , and AND MSB are connected to the Q outputs of the flip-flops FF of the second memory circuit 74 MSB-2 , FF MSB-1 , and FF MSB respectively.

[0069] FIG. 9 shows a more detailed embodiment of the current driver circuit 82 of FIG. 7 when HB is equal to 3 as an example. The light emitting circuit LEDS is shown in FIG. 9 by a single light emitting diode LED. However, the light emitting circuit LEDS can include several light emitting diodes LED connected in parallel.

[0070] The current driver circuit 82 includes, for example, HB + 1 N-type MOS transistors, one of which, transistor T PWM is used for pulse width modulation, and HB transistors T MSB-2 , T MSB-1 , and T MSB are used for pulse amplitude modulation. The drain of each transistor T PWM , T MSB-2 , T MSB-1 , and T MSB is connected to the cathode of the light emitting diode LED. The anode of the light emitting diode LED receives the high reference potential Vcc. The source of each transistor T PWM , T MSB-2 , TMSB-1 and T MSB The gates of and T receive the signal Bias. The width of transistor T MSB-2 is equal to the width of transistor T PWM . The width of transistor T MSB-1 is equal to twice the width of transistor T MSB-2 . The width of transistor T MSB is equal to four times the width of transistor T MSB-2 .

[0071] The current driver circuit 82 includes HB + 1 switches, among which one switch SW PWM is used for pulse width modulation, and HB switches SW MSB-2 , SW MSB-1 , and SW MSB are used for pulse amplitude modulation. The first terminal of each switch SW PWM , SW MSB-2 , SW MSB-1 , and SW MSB receives the low reference potential Gnd. The second terminal of switch SW PWM is connected to the source of transistor T PWM . The second terminal of each switch SW MSB-2 , SW MSB-1 , and SW MSB is connected to the sources of transistors T MSB-2 , T MSB-1 , and T MSB respectively. Switch SW PWM is controlled by the binary signal CPWM’. Switches SW MSB-2 , SW MSB-1 , and SW MSB are controlled by the binary signals CPAM’ MSB-2 , CPAM’ MSB-1 , and CPAM’ MSB respectively.

[0072] Figure 10 shows an example of the timing diagrams of signals Line, Clk_wr, Ctrl, and PWM during the operation of a display pixel having the structure shown in FIGS. 8 and 9.

[0073] To perform a write operation in the first memory circuit 72 and the second memory circuit 74, the signal Line is set to the logic level "1" in the write phase WP. More precisely, when the signal Line is at the logic level "1", the multiplexer MUX1 provides the signal Data at its output, the multiplexer MUX2 provides the clock signal Clk_wr at its output, the multiplexer MUX3 provides, at its output, the signal provided by the Q output of the flip-flop FF LB and the multiplexer MUX4 provides the clock signal Clk_wr at its output. The consecutive bits of the data Data are stored in the first memory circuit 72 and the second memory circuit 74 that are clocked by the clock signal Clk_wr. According to an embodiment, the bits of the data Data are continuously provided to the first flip-flop FF1 of the memory circuit 72 from the MSB to the LSB of the digital color signal. The bits are shifted at the cadence of the clock signal Clk_wr, pass through the first memory circuit 72, and finally pass through the second memory circuit 74. Specifically, the MSB of the digital color signal is shifted from the flip-flop FF1 of the first memory circuit 72 to the flip-flop FLL LB and then shifted from the flip-flop FF of the second memory circuit 74 MSB-2 to the flip-flop FF MSB . When the MSB of the digital color signal reaches the flip-flop FF MSB , the LSB of the digital color signal reaches the flip-flop FF1.

[0074] In the display phase DP between two consecutive write phases WP, the signal Line is set to the logic level "0". During the display phase DP, the signal Ctrl is set to the logic level "1" in at least one display period DC for the display of the image pixel color components by the light-emitting diode LED. When the signal Line is at the logic level "0", the multiplexer MUX1 provides, at its output, the flip-flop FF LBprovides the Q output, multiplexer MUX2 provides signal PWM at its output, multiplexer MUX3 provides a low reference potential Gnd at its output, and multiplexer MUX4 provides a low reference potential Gnd at its output. Further, since signal Ctrl is at logic level "1", each gate AND PWM 、AND MSB-2 、AND MSB-1 、and AND MSB provides the bit present at its second input as its output. Thus, gate AND PWM provides, at its output, the bit present at the output of flip-flop FF LB , and each gate AND MSB-2 、AND MSB-1 、and AND MSB provides, at its output, the MSB-2, MSB-1, and MSB of the color signal data, respectively. Flip-flops FF1 to FF LB of the first storage circuit 72 are clocked by signal PWM, and the bits of the digital color signal stored in the first storage circuit 72 are shifted from one flip-flop to the next flip-flop at each pulse of signal PWM, whereby the bit present at the output of flip-flop FF LB corresponds continuously to the LB bit of the color data signal, and the last bit is provided to be the LSB of the color data signal.

[0075] FIG. 11 shows another embodiment in which signal PWM and signal Clk_wr are merged into a single binary signal Clk_PWM. According to this variation, multiplexer MUX2 may not be present.

[0076] In the timing diagrams shown in FIGS. 10 and 11, there is only one display period DC during the display phase DP between two consecutive write phases WP. Alternatively, the display phase DP between two consecutive write phases WP can include more than one display period DC.

[0077] FIG. 12 is similar to FIG. 10 and shows an example of a timing diagram of signals Line, Clk_wr, Ctrl, and PWM during the operation of a display pixel having the structure shown in FIGS. 8 and 9. In FIG. 12, each display phase DP between two consecutive write phases WP includes a repetition of four identical display cycles DC.

[0078] FIG. 13 is a block diagram showing an embodiment of a method for changing the supply power Vcc of display screen 10. The method includes the following steps. - Receive video data to be displayed by circuit 26 of display screen 10 (step 100); - Determine the maximum gray level of the image to be displayed (step 102). To simplify the calculation of the gray level of the image, only the bits of the digital color signal used for pulse amplitude modulation are considered for each image pixel color component of each image pixel; - Determine the current intensity required for displaying the image based on the maximum gray level of the image (step 104); and - Adjust the supply voltage Vcc (step 106), whereby when displaying the image, the desired current intensity can be supplied to the light-emitting diodes of the display pixels.

[0079] For a dark-tone image, in that case, since only a low-intensity current is required to display the image, the level of the supply voltage Vcc can be lowered. For a bright-tone image, in that case, since a high-intensity current is required to display the image, the level of the supply voltage Vcc can be increased. Therefore, according to this embodiment, the power consumption of the display screen can be reduced.

[0080] FIG. 14 shows an example of the progression of the power supply Vcc during the display of video data. In this example, the bits used for pulse amplitude modulation are the MSB and MSB-1 of the color data signal. As an example, FIG. 14 shows four consecutive phases P1, P2, P3, and P4 with different maximum gray levels. In phases P1 and P4, the maximum gray level corresponds to the MSB and MSB-1 in the logical state "1". In phase P2, the maximum gray level corresponds to the MSB in the logical state "0" and the MSB-1 in the logical state "1". In phase P3, the maximum gray level corresponds to the MSB and MSB-1 in the logical state "0". As seen in FIG. 14, in each of the phases P1, P2, P3, and P4, the potential Vcc is adjusted to a constant level. The change from one constant level of the potential Vcc to another can be implemented at a given rate of change in order to prevent a sudden change in the displayed image.

[0081] In some cases, the wavelength of the radiation emitted by the light-emitting diode can vary depending on the intensity of the current passing through the light-emitting diode. This may be undesirable.

[0082] FIG. 15 is a diagram similar to FIG. 9 and shows another embodiment of the display pixel 12 i,j . The display pixel 12 shown in FIG. 15 i,j comprises all the elements of the display pixel 12 shown in FIG. 9 except for a light-emitting circuit LEDS comprising several light-emitting diodes LED for each image pixel color component, and only the light-emitting diode LED for one image pixel color component is shown in FIG. 15. This embodiment is advantageously easily implemented when each light-emitting diode comprises, for example, a micrometer or nanometer three-dimensional element having a shape of a micro wire, a nano wire, or a pyramid, a cone, or a frustum of a cone, and the micrometer or nanometer three-dimensional element is covered by the active region of the light-emitting diode which is the region where most of the electromagnetic radiation supplied by the light-emitting diode is emitted. i,j

[0083] For each image pixel color component, the light-emitting diode LED of the light-emitting circuit LEDS is a group of LEDs consisting of HB + 1 light-emitting diodes PWM , LED MSB-2 , LED MSB-1 , and LED MSB is dispatched at, HB is equal to 3 as an example in Figure 9, and the light-emitting diode LED PWM , LED MSB-2 , LED MSB-1 , and LED MSB each group is indicated by the electrical symbol of a single light-emitting diode LED in Figure 15. The anode of each light-emitting diode in the group of light-emitting diodes LED PWM , LED MSB-2 , LED MSB-1 , and LED MSB receives the high reference potential Vcc. The cathode of each light-emitting diode in the group of LEDs PWM is connected to the drain of the transistor T PWM . The cathode of each light-emitting diode in the group of LEDs MSB-2 is connected to the drain of the transistor T MSB-2 . The cathode of each light-emitting diode in the group of LEDs MSB-1 is connected to the drain of the transistor T MSB-1 . The cathode of each light-emitting diode in the group of LEDs MSB is connected to the drain of the transistor T MSB . The number of light-emitting diodes in each group of LEDs PWM , LED MSB-2 , LED MSB-1 , and LED MSB when turned on, the light intensity emitted by the group of LEDs MSB-2 is equal to the light intensity emitted by the group of LEDs PWM , and the light intensity emitted by the group of LEDs MSB-1 is equal to twice the light intensity emitted by the group of LEDs MSB-2 , and the light intensity emitted by the group of LEDs MSB is selected to be equal to twice the light intensity emitted by the group of LEDs MSB-1 . Therefore, each group of LEDsPWM , LED MSB-2 , LED MSB-1 , and LED MSB The current density of each light-emitting diode of, and LED is preferably the same. When all the light-emitting diodes have the same structure, the number of light-emitting diodes in the group LED MSB-2 is equal to the number of light-emitting diodes in the group LED PWM , the number of light-emitting diodes in the group LED MSB-1 is equal to the number of light-emitting diodes in the group LED MSB-2 , the number of light-emitting diodes in the group LED is equal to twice the number of light-emitting diodes in the group LED MSB , the number of light-emitting diodes in the group LED MSB-1 is equal to twice the number of light-emitting diodes in the group LED. Therefore, each group LED PWM , LED MSB-2 , LED MSB-1 , and LED MSB The current density of each light-emitting diode of is preferably the same.

[0084] FIG. 16 is a top view of an embodiment of the display pixel 12 shown in FIG. 15, showing the arrangement of the light-emitting diodes of the light-emitting circuit LEDS. Each light-emitting diode LED is indicated by a circle, and within the circle, the letter "R" representing a light-emitting diode that emits red radiation, the letter "G" representing a light-emitting diode that emits green radiation, and the letter "B" representing a light-emitting diode that emits blue radiation are shown. In FIG. 16, the group LED i,j includes four light-emitting diodes for each image pixel color component, the group LED MSB includes two light-emitting diodes for each image pixel color component, the group LED MSB-1 includes one light-emitting diode for each image pixel color component, the group LED MSB-2 includes one light-emitting diode for each image pixel color component, and the group LED PWM includes one light-emitting diode for each image pixel color component.

[0085] It may be desirable to reduce the storage capacity of the digital signal of the display pixel 12 i,j .

[0086] FIG. 17 is a diagram similar to FIG. 15, showing display pixel 12 i,j and showing another embodiment thereof. The display pixel 12 shown in FIG. 17 i,j is such that, for the light emitting circuit LEDS, group LED PWM is labeled as LED1, group LED MSB-2 is labeled as LED2, group LED MSB-1 is labeled as LED3, group LED MSB is labeled as LED4, transistor T PWM is labeled as T1, transistor T MSB-2 is labeled as T2, transistor T MSB-1 is labeled as T3, transistor T MSB is labeled as T1, switch SW PWM is labeled as SW1, switch SW MSB-2 is labeled as SW2, switch SW MSB-1 is labeled as SW3, switch SW MSB is labeled as SW4, and except that the gates of transistors T1, T2, T3, T4 are controlled by control circuit 110, display pixel 12 shown in FIG. 15 i,j comprises all elements thereof.

[0087] FIG. 18 shows a timing diagram of the signal Vsync and Clk_wr of the light emitting diodes and the control signal CLED for an embodiment of a display screen comprising the display pixel 12 i,j shown in FIG. 17. In this embodiment, for the display of the color components of the color image pixels, the bits of the digital color signal are transmitted to each display pixel in successive write phases WP separated by the display phase DP. Four write phases WP and four display phases DP are shown as an example in FIG. 18 for the display of the image pixels, and 2 bits of the digital color signal are stored in the display pixel between each write phase WP, and the digital color signal comprises 8 bits.

[0088] Each display phase DP is divided into a first sub-phase DP_1 and a second sub-phase DP_2. The total duration of the display phase DP, the duration of the first sub-phase DP_1, and the duration of the second sub-phase DP_2 are the same for all display phases DP. The duration of the first sub-phase DP_1 is equal to a multiple of the duration of the second sub-phase DP_2. In this example, the duration of the first sub-phase DP_1 is equal to 16 times the duration of the second sub-phase DP_2. For each display phase DP, different groups of light-emitting diodes among group LEDs 1, 2, 3, and 4 are switched on or off based on the first memory bit of the digital color signal in the first sub-phase DP_1 and based on the second memory bit of the digital color signal in the second sub-phase DP_2.

[0089] In FIG. 18, groups of light-emitting diodes LED1, LED2, LED3, and LED4 that can be used for the display phase DP are shown below the display phase DP. In this embodiment, the light-emitting diodes of group LED1 are used in the first sub-phase DP_1 and the second sub-phase DP_2 of all display phases DP. The light-emitting diodes of group LED2 are used in the first sub-phase DP_1 and the second sub-phase DP_2 of three display phases DP and are systematically turned off in other display phases DP. The light-emitting diodes of group LED3 are used in the first sub-phase DP_1 and the second sub-phase DP_2 of two display phases DP and are systematically turned off in other display phases DP. The light-emitting diodes of group LED4 are used in the first sub-phase DP_1 and the second sub-phase DP_2 of one display phase DP and are systematically turned off in other display phases DP. Four consecutive display phases correspond to a single display phase in which the light-emitting diodes are controlled by pulse width modulation and pulse amplitude modulation.

[0090] FIG. 19 shows another embodiment of the display pixel 12 i,j The display pixel 12 shown in FIG. 19i,j comprises all the elements of the display pixel 12 shown in FIG. 8, except that the second memory circuit 74, the second shift circuit 78, and the logic circuit 80 do not exist. i,j Furthermore, the display pixel 12 i,j comprises the light-emitting circuit LEDS shown in FIG. 17, which has two groups of light-emitting diodes, LED1 and LED2. The number of flip-flops in the first memory circuit 72 is equal to 4 in the example of FIG. 19. The flip-flops FF1 to FF4 are clocked by the binary signal Clk_PWM. Furthermore, the first shift circuit 76 comprises only the first multiplexer MUX1. The first input of the first multiplexer MUX1 receives the low reference potential Gnd. The second input of the first multiplexer MUX1 receives the signal Data, and the output of the first multiplexer MUX1 is connected to the D input of the flip-flop FF1 of the first memory circuit 72.

[0091] The driver circuit 70 further comprises an additional D flip-flop FF Cl clocked by the binary signal Clk_PWM. Cl The D input of the flip-flop FF Cl is connected to the QB output of the flip-flop FF Cl . The driver circuit 70 further comprises an inverter INV and a NOR-type logic gate NOR. The input of the inverter INV is connected to the Q output of the flip-flop FF Cl . The inverter INV provides the binary signal CLED. The QB output of the flip-flop FF4 is connected to the first input of the gate NOR. The output of the inverter INV is connected to the second input of the gate NOR. In this embodiment, the display pixel 12 i,j comprises only the groups of light-emitting diodes LED1 and LED2.

[0092] FIG. 20 shows the display pixel 12 shown in FIG. 18 i,jShows the timing diagrams of signals Vsync and Clk_PWM, and signal CLED for an embodiment of a display screen comprising. The binary signal Clk_PWM includes a write clock Clk_wr and a signal PWM. In this embodiment, the bits of the digital color signal are sent to the first storage circuit 72 of the display pixel 12 i,j during the write phase WP. During the display phase DP following the write phase WP, the signal Clk_PWM includes first, second, third, fourth, and fifth consecutive pulses P1, P2, P3, P4, and P5. The first pulse P1 indicates the start of the display phase DP, and the fifth pulse P5 indicates the end of the display phase DP. The storage circuit 72 is clocked by the consecutive pulses P1, P2, P3, P4 to continuously provide the bits stored in the storage circuit 72 at the Q output of the flip-flop FF4.

[0093] The duration between the first pulse P1 and the second pulse P2 is equal to the duration between the second pulse P2 and the third pulse P3. The duration between the third pulse P3 and the fourth pulse P4 is equal to the duration between the fourth pulse P4 and the fifth pulse P5, and is equal to four times the duration between the first pulse P1 and the second pulse P2. The signal CLED provided by the inverter INV alternates between logical states "0" and "1" at each pulse of the signal Clk_PWM such that CLED is in the logical state "0" between the first pulse P1 and the second pulse P2 and between the third pulse P3 and the fourth pulse P4, and the signal CLED is in the logical state "1" between the second pulse P2 and the third pulse P3 and between the fourth pulse P4 and the fifth pulse P5.

[0094] In FIG. 20, there is a group of light-emitting diodes LED1 that can be used throughout the entire display phase DP, and a group of light-emitting diodes LED2 that can be used only between the second pulse P2 and the third pulse P3 and between the fourth pulse P4 and the fifth pulse P5. Therefore, between the first pulse P1 and the second pulse P2, and between the third pulse P3 and the fourth pulse P4, only the light-emitting diodes of the group LED1 are turned on or off based on the bit provided by the flip-flop FF4, and between the second pulse P2 and the third pulse P3, and between the fourth pulse P4 and the fifth pulse P5, the light-emitting diodes of both the group LED1 and LED2 are turned on or off based on the bit provided by the flip-flop FF4. Therefore, the current density of each light-emitting diode of each of the groups LED1 and LED2 is advantageously the same.

[0095] FIG. 21 shows another embodiment of the display pixel 12 i,j . The display pixel 12 shown in FIG. 21 i,j includes only one group of light-emitting diodes LED1 for each image pixel color component, and has all the elements of the display pixel 12 shown in FIG. 18, except that the cathodes of the light-emitting diodes of the group LED1 are connected to the drains of the transistors T1 and T2. The operation of the display pixel 12 shown in FIG. 21 i,j is the same as the operation of the display pixel 12 shown in FIG. 19 i,j . i,j

[0096] As will be described later, to limit the number of conductive pads Gnd, P_Vcc, P_Col, P_Row for each display pixel 12 i,j , the data signal Data j enables each display pixel 12 i,j to make a decision based on both the clock signal and the color signals R, G, B representing the desired light intensities for radiation at the first, second, and third wavelengths. As a variant, the data signal Data j is for each display pixel 12 of the color signals R, G, B i,jIt can only be used for the determination by, and the clock signal is received by each pixel 12 on a separate conductive pad i,j is received by.

[0097] According to the embodiment of the display screen 10 shown in FIG. 1, for each row, the display pixels 12 in the row i,j are coupled to a single row electrode 18 i For each column, the display pixels 12 in the column i,j are coupled to a single column electrode 20 j The display screen 10 is coupled to the row electrode 18 i and includes a selection circuit 22 adapted to transmit selection and timing signals Com i on each row electrode 18 i The display screen 10 is coupled to the column electrode 20 j and includes a data transmission circuit 24 adapted to transmit data signals Data j on each column electrode 20 j The selection circuit 22 and the control circuit 24 are controlled by a circuit 26 including, for example, a microprocessor.

[0098] FIG. 22 is a very simplified cross-sectional view of a known example of the display pixel 12 i,j and FIG. 23 is a bottom view of the display pixel 12 i,j Each display pixel 12 i,jIt includes a control circuit 30 covered by a display circuit 32. The display circuit 32 includes at least one light-emitting diode LED, preferably at least three light-emitting diodes LEDs. The display pixel includes a lower surface 34 and an upper surface 35 facing the lower surface 34, and the surfaces 34 and 35 are preferably planar and parallel. The control circuit 30 further includes conductive pads P_Gnd, P_Vcc, P_Col, and P_Row on the lower surface 34. The control circuit 30 can correspond to an integrated circuit including electronic components, particularly an insulated-gate field-effect transistor also called a MOS transistor or a thin-film transistor also called a TFT. Preferably, the display circuit 32 includes only the light-emitting diode LEDs and the conductive elements of these light-emitting diode LEDs, and the control circuit 30 includes all the electronic components necessary for controlling the light-emitting diode LEDs of the display circuit 32. As a variant, the display circuit 32 can also include other electronic components in addition to the light-emitting diode LEDs. The light-emitting diode LED can be a 2D light-emitting diode also called a planar light-emitting diode with a stack of planar layers, or a 3D light-emitting diode with three-dimensional semiconductor elements each covered by an active region. In FIG. 22, the light-emitting diodes are shown as being connected to a common anode. However, it may be desirable to arrange the light-emitting diode LEDs with a different configuration. As an example, the light-emitting diodes can be connected to a common cathode or connected independently of each other.

[0099] According to an embodiment, the display pixel 12 i,j includes three display sub-pixels that emit light at a first, a second, and a third wavelength. According to an embodiment, the first wavelength corresponds to blue light and is in the range of 430 nm to 490 nm. According to an embodiment, the second wavelength corresponds to green light and is in the range of 510 nm to 570 nm. According to an embodiment, the third wavelength corresponds to red light and is in the range of 600 nm to 720 nm. As a variant, the display pixel 12 i,j can include only one light source that emits light at a first, a second, or a third wavelength, or only two light sources that emit light at two of the first, the second, and the third wavelengths.

[0100] Each of the conductive pads P_Gnd, P_Vcc, P_Col, and P_Row is intended to be connected to any one of the electrodes 14 i , 16 j , 18 i , 20 j shown schematically in FIG. 22. The first conductive pad P_Gnd is coupled to the source of the low reference potential Gnd. The second conductive pad P_Vcc is coupled to the source of the high reference potential Vcc. The third conductive pad P_Row is coupled to the row electrode 18 i and receives the selection and timing signal Com i . The fourth conductive pad P_Col is coupled to the column electrode 20 j and receives the data signal Data j .

[0101] FIG. 24 shows a known example of a block diagram of the display pixels 12 i,j of the display screen 10. In FIG. 24, above each block, the power supply voltage used to supply power to the electronic components of the block is shown.

[0102] The display pixel 12 i,j comprises a driver circuit 70 for driving a controllable current source 82. The driver circuit 70 may in particular comprise electronic components such as MOS transistors. In order to supply power to the electronic components of the driver circuit 70, it may be desirable to use a reduced power supply voltage, for example on the order of 1 V or 1.8 V and less than 4 V, which corresponds to the voltage that is likely to be applied across the power terminals of the MOS transistors. For this purpose, the display pixel 12 i,j comprises a circuit 42 (Vdd generation) for transmitting a reduced power supply voltage Vdd used in particular for the power supply of the driver circuit 40 from the power supply voltage Vcc. The circuit 42 comprises, for example, a voltage divider.

[0103] According to an embodiment, the detection and timing signal Com i,j received at the conductive pad P_Row of each display pixel 12 iis a binary signal that alternates between a low state "0" and a high state "1", where the low state corresponds to a low reference potential Gnd, and the high state "1" corresponds to a low voltage, for example, about 1V, which is smaller than the reduced power supply voltage Vdd. Each display pixel 12 i,j The data signal Data received by the conductive pad P_Col of j is a binary signal that alternates between a low state "0" and a high state "1", where the low state corresponds to a low reference potential Gnd, and the high state "1" corresponds to a low voltage, for example about 1V, which is smaller than the reduced power supply voltage Vdd.

[0104] The display pixel 12 i,j is coupled to the conductive pad P_Col that receives the data signal Data j and includes a circuit 44 (Clk & data separation) that transmits the clock signal Clk and data from the data signal Data j . The display pixel 12 i,j includes a circuit 46 (mode selection) that receives the signals Clk and Data, which is coupled to the conductive pad P_Row that receives the selection and timing signal Com i and is configured to transmit the signals Clk_wr and Data, or to transmit a PWM signal to the driver circuit 70 to control the controllable current source 82 associated with each light emitting diode LED.

[0105] As will be described later, to limit the number of conductive pads Gnd, P_Vcc, P_Col, P_Row for each display pixel 12 i,j the data signal Data j enables determination by each display pixel 12 of both the clock signal and the color signals R, G, B representing the desired light intensities for emission at the first, second, and third wavelengths. As a variant, the data signal Data i,j can be used only for determination by each display pixel 12 of the color signals R, G, B, and the clock signal is received by each pixel 12 on a separate conductive pad j . i,j i,j

[0106] ​​ FIG. 25 shows the display pixel 12 i,j and represents a block diagram of an embodiment. The display pixel 12 of FIG. 25 i,j has the same structure as the display pixel 12 of FIG. 24, except that the circuit 42 for supplying the reduced supply voltage Vdd is replaced by a circuit 60 that receives the selection and timing signal Com i and the data signal Data j and supplies the reduced supply voltage Vdd. In this embodiment, the reduced power supply voltage Vdd is supplied from the selection and timing signal Com i,j and the data signal Data i and the data signal Data j and the reduced power supply voltage Vdd is supplied.

[0107] According to an embodiment, for each display pixel 12 i,j , the circuit 44 determines the clock signal Clk and the data Data based on the pulses of the data signal Data j . As an example, each pulse of the data signal Data j may have a first length, or a second length longer than the first length. The signal Clk may correspond to a sequence of pulses of the same length having a rising edge that coincides with the rising edge of the pulse of the data signal Data j within a possible fixed offset. The data Data may correspond to a binary signal in the state "0" when the pulse of the signal Data j has the first length, and in the state "1" when the pulse of the signal Data j has the second length. The circuit 46 selected by the signal Com i in the state "1" transmits the data Data stored in the circuit 70 in the form of digital color signals R, G, B having bits provided by consecutive values of the signal Data at the rate of the clock signal Clk.

[0108] Various embodiments and variations have been described. Those skilled in the art will understand that they can combine specific features of these embodiments and that other variations will be readily envisioned by those skilled in the art. In particular, in the embodiments disclosed above, the light-emitting diodes have a common anode, i.e., the anode of the light-emitting diode receives a high reference voltage and the cathode of the light-emitting diode is connected to a controllable current source. However, these embodiments are also applicable to display pixels in which the light-emitting diodes have a common cathode, i.e., the cathode of the light-emitting diode receives a low reference voltage and the anode of the light-emitting diode is connected to a controllable current source.

[0109] Finally, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art based on the functional descriptions provided above.

[0110] Cross-reference to related applications This application claims the benefit of priority of French Patent Application No. 22 / 06042, filed on June 20, 2022, entitled "Display Pixel Comprising an Electroluminescent Source", which is incorporated herein by reference in its entirety to the maximum extent permitted by law.

Claims

1. Display pixels (12) for the display screen (10) ｉ，ｊ ) which are A light-emitting circuit (LEDS) comprising at least a first electroluminescent source (LED); A controllable current source (82) for driving the light-emitting circuit with a current pulse (I_LED); A driver circuit (70) for controlling the current source and comprising, The driver circuit receives a digital signal (Data) including a first bit and a second bit different from the first bit, and based on the bits of the digital signal, modulates the current pulse by pulse width modulation and modulates the current pulse by pulse amplitude modulation. The current source is configured to control the supply of the current pulse, The driver circuit (70) is configured to indicate to the current source (82) to provide a current that is the sum of a continuous first current pulse having a first duration depending on a certain intensity and the first bit of the digital signal, and a second current pulse having a certain second duration (Tcycle) indicated by the second bit of the digital signal. The sum of the first durations is less than or equal to the second duration, A display pixel.

2. The display pixel according to claim 1, wherein the current source (82) is configured to generate the continuous first current pulse while the second current pulse is generated.

3. The bits of the digital signal are ranked from the most significant bit to the least significant bit, and the intensity of the second current pulse depends on the rank of the second bit of the digital signal (Data). The display pixel according to claim 1 or 2.

4. The display pixel according to claim 6, wherein the second bit includes the most significant bit of the digital signal (Data).

5. The digital signal (Data) includes a third bit different from the first bit and the second bit, and the driver circuit (70) is configured to supply a current that is the sum of the continuous first current pulse, the second current pulse, and a third current pulse having the second duration (Tcycle) indicated by the third bit of the digital signal (Data). The controllable current source (82) is configured to indicate. The display pixel according to claim 3 or 4.

6. The display pixel according to claim 5, wherein the current source (82) is configured to generate the third current pulse simultaneously with the second current pulse.

7. The display pixel according to claim 5 or 6, wherein the intensity of the third current pulse depends on the rank of the third bit of the digital signal and is different from the intensity of the second current pulse.

8. The display pixel according to claim 7, wherein the third bit is the second most significant bit of the digital signal (Data).

9. The digital signal (Data) includes a fourth bit different from the first bit, the second bit, and the third bit, and the driver circuit (70) is configured to supply a current that is a sum of the continuous first current pulse, the second current pulse, the third current pulse, and a fourth current pulse having the second duration (Tcycle) and indicated by the fourth bit of the digital signal (Data). The display pixel according to any one of claims 5 to 8, wherein the display pixel is configured to instruct the controllable current source (82).

10. The display pixel according to claim 6, wherein the current source (82) is configured to generate the fourth current pulse simultaneously with the second current pulse.

11. The display pixel according to claim 9 or 10, wherein the intensity of the fourth current pulse depends on the rank of the fourth bit of the digital signal (Data) and is different from the intensity of the second current pulse and the intensity of the third current pulse.

12. The display pixel according to claim 11, wherein the fourth bit is the third most significant bit of the digital signal (Data).

13. The driver circuit (70) includes a first storage circuit (72) for storing the first bit of the digital signal, and the first storage circuit (72) includes a shift register clocked by a pulse width modulation clock signal (PWM). The display pixel according to any one of claims 1 to 12.

14. The driver circuit (70) includes a second storage circuit (72) for storing the second bit of the digital signal, and is controlled by a control signal (Ctrl) and clocked by the pulse width modulation clock signal (PWM). The shift register (72) continuously receives the first bit, receives the second bit from the second storage circuit (74), and controls the controllable current source (82) from the continuously received first bit and the second bit when the control signal is in a given state. The display pixel according to claim 13, further comprising a logic circuit (80).

15. The light emitting circuit (LEDS) has a first group of electroluminescent sources (LEDs) having a first number of electroluminescent sources ＰＷＭ ; LEDs １ ), and a second group of electroluminescent sources (LEDs) having a second number of electroluminescent sources ＭＳＢ－２ , LEDs ＭＳＢ－１ , LEDs ＭＳＢ ; LED ２ 、LED ３ 、LED ４ ), and the controllable current source (82) is instructed by the first bit and is connected to the first group of electroluminescent sources (LED ＰＷＭ ; LED １ ) a first controllable current source (T ＰＷＭ , SW ＰＷＭ ; T1), and a second controllable current source (T ＭＳＢ－２ , LED ＭＳＢ－１ , LED ＭＳＢ ; LED ２ , LED ３ , LED ４ ) that is instructed by the second bit and is connected to the second group of electroluminescent sources (LED ＭＳＢ , SW ＭＳＢ , T ＭＳＢ－１ , SW ＭＳＢ－１ , T ＭＳＢ－２ , SW ＭＳＢ－２ ; T ２ 、 T ３ 、 T ４ ), the display pixel according to any one of claims 1 to 14.

16. The controllable current source (82) A first MOS transistor (TPWM; T1) connected to the light emitting circuit (LEDS), and a first switch (SW ＰＷＭ ; SW １ ) and, The second MOS transistor (T ＭＳＢ－２ , T ＭＳＢ－１ , T ＭＳＢ ; T ２ , T ３ , T ４ ) connected to the light-emitting circuit, and the second switch (SW ＭＳＢ－２ , SW ＭＳＢ－１ , SWB ＭＳＢ ; SW ２ , SW ３ , SW ４ ) connected to the second MOS transistor The display pixel according to any one of claims 1 to 15, comprising

17. The logic circuit (80) continuously controls the first switch (SW ＰＷＭ ; SW １ ), and is configured to control the second switches (SW ＭＳＢ－２ , SW ＭＳＢ－１ , SWB ＭＳＢ ) based on the second bit. The display pixel according to claim 16

18. The driver circuit (70) controls only the first switch (SW １ ) based on some of the first bits, and controls both the first switch and the second switch (SW １ ) based on the other first bits, the display pixel according to claim 17.

19. the electroluminescent source (LED ＰＷＭ ; LED １ ) of the first group is connected to the first MOS transistor (T ＰＷＭ ; T １ ), and the electroluminescent sources (LED ＭＳＢ－２ , LED ＭＳＢ－１ , LED ＭＳＢ ; LED ２ 、LED ３ 、LED ４ ), the second MOS transistor (T ＭＳＢ－２ , T ＭＳＢ－１ , T ＭＳＢ ; T ２ 、 T ３ 、 T ４ The display pixel according to claim 15 or 16, which is connected to

20. The light emitting circuit (LEDS) has a third group of electroluminescent sources (T ＭＳＢ－２ , T ＭＳＢ－１ , T ＭＳＢ ; T ２ 、 T ３ 、 T ４ ), and the controllable current source (82) is a third MOS transistor (T ＭＳＢ－２ 、 T ＭＳＢ－１ 、 T ＭＳＢ ; T ２ 、 T ３ 、 T ４ ), and a third switch (SW ＭＳＢ－２ 、 SW ＭＳＢ－１ 、 SWB ＭＳＢ ; SW ２ 、 SW ３ 、 SW ４ ), wherein the first number is equal to the second number, and the third number is greater than the second number. The display pixel according to claim 19.

21. A display screen (60) comprising an array of display pixels (12i, j) according to any one of claims 1 to 20.

22. The display screen according to claim 21, further comprising a circuit (26) configured to change a power supply voltage (Vcc) of the display pixel according to the second bit.

Images