Transceiver Device for Array Signal Processing

Abstract

An IC having two serial data ports configured to transmit and receive aggregated signal port IQ data packets to and from adjacent ICs within a subarray of transceiver integrated circuits ICs suitable for distributed placement across an active antenna unit, or to a beamformer processor. A packet header inspection circuit can identify aggregated signal port IQ data packets aggregated for local processing and aggregated signal port IQ data packets received for processing by another device.

Description

Technical Field

[0001] The present disclosure relates to the field of telecommunications, and more specifically, to the distribution of signals for transmission via an antenna radiating element. It can find applications in the field of wireless communications such as 2G / 3G / 4G, LTE, LTE-Advanced, and 5G.

Background Art

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 357,582, filed on June 30, 2022, named Yaniv Kaver, Efi Dror, Jongheon Kim, and Yang Xu as inventors, and titled "Transceiver Device for Array Signal Processing", which is hereby incorporated by reference in its entirety for all purposes.

[0003] This section is intended to introduce the reader to various aspects of the technology that may be related to the various aspects of the present disclosure described and / or claimed below. This description is considered useful in providing the reader with background information that facilitates a better understanding of the various aspects of the systems and methods described herein. Accordingly, it should be understood that these descriptions should be read from this perspective and should not be read as an admission of prior art.

Summary of the Invention

[0004] This specification describes embodiments of a transceiver integrated circuit suitable for distributed placement across active antenna units. One such embodiment includes an IC having two serial data ports configured to transmit and receive aggregated signal port IQ data packets. The connections can be made to adjacent ICs within a subarray of the ICs or to a beamformer processor. The IC also includes a packet header inspection circuit configured to (i) identify aggregated signal port IQ data packets for local processing, (ii) identify aggregated signal port IQ data packets received for processing by another device, and (iii) transfer, using a second serial data interface, the received aggregated signal port IQ data packets identified for processing by another device. The packet header inspection circuit enables intelligent transfer of packets between transceiver IC subarrays. The IC further includes a digital signal processor (DSP) configured to perform an inverse fast Fourier transform (IFFT) to convert the identified aggregated signal port IQ data packets into a downlink (DL) aggregated signal port discrete time domain baseband data signal for local processing and to perform an FFT of the received and sampled uplink (UL) data (after direct conversion to baseband). The IC also can include a time domain processing circuit configured to convert the DL aggregated signal port discrete time domain baseband data signal into an oversampled signal port discrete time domain data signal and an integrated digital power amplifier (DPA) and polyphase carrier generator configured to convert the oversampled signal port discrete time domain data signal into an analog modulated radio frequency signal. The analog modulated radio frequency signal generated by the DPA may be provided directly to a corresponding antenna element for transmission or, in configurations requiring a higher power output level, to an external power amplifier. The IC also can include a UL time domain processing circuit configured to convert the sampled received UL data into a downsampled data stream for each component carrier in the received UL RF signal.The downsampled data stream is then converted into an aggregated signal port IQ UL data packet.

[0005] References to "an embodiment", "embodiment", "exemplary embodiment", etc. in this specification indicate that the described embodiment may include a particular feature, structure, or characteristic, but not all embodiments necessarily include that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, such feature, structure, or characteristic may be used in connection with other embodiments whether or not explicitly described. BRIEF DESCRIPTION OF THE DRAWINGS

[0006]

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[0007] FIG. 1 shows an antenna array assembly 100 according to some embodiments. As shown, the antenna array assembly 100 has a grid of radiating elements (also referred to herein as antenna elements or antenna radiating elements) generally disposed in rows (e.g., row 104) and columns (e.g., column 100) on a panel 102, which can be a printed circuit board (PCB) for the radiating elements or other suitable support structure. Positions within the grid, such as position 116, have juxtaposed radiating elements, such as elements 112 and 114, and can typically provide different radiation polarization, such as horizontal and vertical polarization, or equivalently, plus 45 degrees (+45°) and minus 45 degrees (−45°). The grid of radiating elements may be arranged in a regular array pattern as shown in FIG. 1. In one embodiment, the radiating elements are spaced apart by approximately one-half wavelength (λ) distance, where the wavelength (λ) is associated with the desired frequency operating range of the antenna array, which can be associated with the carrier frequency of the system, or more generally, the center frequency of the system, particularly in embodiments using a frequency division duplexing (FDD) system that utilizes multiple carrier frequencies. Some embodiments may operate within multiple frequency bands, and in such an embodiment, the array as shown in FIG. 1 may be configured to operate within a first band using a first frequency of wavelength λ1 and to operate in a second frequency band having a wavelength λ2 = 2λ1. In such an embodiment, operation in the first band (λ1) can utilize adjacent antenna radiating elements spaced apart by a distance of 0.5λ1 as shown, but for operation in the second, lower frequency band (having wavelength λ2), two spaced-apart (e.g., every other row, or every other column) elements have a spacing of 0.5λ2 and can thus be used for operation in the second frequency band.

[0008] The antenna array panel may be composed of more antenna pairs (e.g., 128, 194, 256, 512, etc.) or even fewer antennas (e.g., 32, 16, etc.). However, the specific array in FIG. 1 shows 64 horizontal radiating elements and 64 vertical radiating elements arranged in an 8×8 square configuration on a panel of approximately 35 - 40 centimeters by 35 - 40 centimeters, with the radiating elements spaced approximately 4.3 centimeters apart. The antenna array assembly 100 also includes a circuit board assembly 128 that includes a power module 130, a clock distribution circuit 132, a global positioning system (GPS) receiver 134, a processor circuit 138 for performing packet protocol processing among other things, beamforming in some embodiments, a network data interface 136, a power connector 140, and a GPS connector 142.

[0009] In various embodiments described hereinafter in this specification, the radiating elements may be grouped into sub - arrays such as column sub - array 106 having 8 vertical radiating elements and 8 horizontal radiating elements, or smaller sub - arrays such as groups 108 and 122 each having 4 horizontal elements and 4 vertical elements, or groups 110, 120, 124, 126 each having 2 vertical radiating elements and 2 horizontal radiating elements. In some embodiments, the antenna sub - array may comprise a two - dimensional set of elements such as 4 cross - polarized radiating elements arranged in a square configuration, or 6 cross - polarized pairs arranged in a 2×3 grid. Alternative forms include a set of two or more adjacent vertically polarized elements forming one antenna element sub - array and a corresponding set of vertically polarized elements of cross - polarized pairs forming a separate sub - array. In further embodiments, each cross - polarized pair of radiating elements may be an array element driven individually.

[0010] Each sub - array of the radiating elements can be driven by a radio - frequency (RF) signal generated by a set of transceivers located adjacent to the antenna. As used herein, the term "antenna sub - array" is functionally inter - related primarily according to the connection to a corresponding set of cooperative RF transceiver integrated circuits (ICs) used to process the RF signal associated with the radiating elements of the antenna sub - array, and refers to a group of radiating elements arranged in a corresponding array pattern. In such a case, the transceiver circuit comprises a set or group of serially - connected transceiver integrated circuit packages (hereinafter referred to as "transceiver ICs") having a first transceiver IC connected to a beamformer processor via a serial data connection (or "link") and a series of point - to - point serial data connections between the transceiver ICs. In some embodiments, the data path terminates at the last transceiver IC of the group. In an alternative embodiment, the transceiver ICs may be interconnected in a ring configuration, and the last transceiver IC in the chain may be connected back to the beamformer processor using an additional serial data connection, or may be connected to the last transceiver IC in a separate sub - array chain of serially - connected transceiver ICs.

[0011] In some embodiments, note that a given group of transceiver ICs (i.e., a set of serially connected transceiver ICs) within a transceiver IC subarray associated with a corresponding antenna subarray may be capable of processing an independent RF signal for each radiating element. Thus, as used herein, the term "antenna subarray" refers to a set of antenna elements (of a possibly larger antenna element array in some cases) associated with a given set of transceiver ICs. In some embodiments described herein, a group of radiating elements can operate in a cooperative manner by transmitting the same or similar RF signals (or a set of RF signals for H and V polarizations) with possible phase differences therebetween to achieve a desired radiation pattern for beamforming, antenna tilt, or the like.

[0012] FIG. 2 shows a wireless unit architecture having multiple groups of serially connected transceivers used to process RF communication signals associated with corresponding groups of antenna radiating elements, according to some embodiments. As shown in FIG. 2, each group of serially connected transceiver ICs includes at least two serially connected transceiver ICs physically disposed within a transceiver IC subarray. Specifically, transceiver IC 222 connected to beamformer processor (referred to herein in some places as "BFP") 202 via serial data link 206 is also serially connected to transceiver IC 232 via full-duplex serial data link 228, thereby forming a transceiver IC subarray oriented vertically along a column of a panel array such as panel array 110. Similarly, transceiver IC 212 is connected to transceiver IC 230, forming another transceiver IC subarray.

[0013] Each serial data link between transceiver ICs (e.g., 228) establishes a point-to-point link using a Serdes (Serializer / Deserializer) transceiver or a set of Serdes transceivers. In one embodiment, each transceiver IC includes two such Serdes transceivers. Alternatively, a greater number of Serdes devices may be included to provide a higher level of interconnectivity between transceiver ICs. Serdes may utilize a standard serial data signaling format, such as a two-level pulse amplitude modulation (PAM2) non-return-to-zero (NRZ) differential signal transmitted over a pair of conductors. In one embodiment, a data rate of 6 gigabits per second (Gbps) PAM2 is sufficient to carry aggregated signal port IQ data packets (including headers) and to provide additional throughput capacity for transmitting control plane messaging to the transceiver IC. The serial link data rate can be selected to accommodate data packets between individual transceiver IC sub-arrays according to a desired deployment, including the desired number of independent signal ports, the desired number of component carriers, multi-band operation (thereby adding additional carriers), FDD or TDD, the number of transceiver ICs connected within a transceiver IC sub-array, and the like.

[0014] Furthermore, as will be described in more detail below, in various embodiments, each serial data link between the beamformer processor 202 and a given transceiver IC subarray, as well as the serial data links that serially interconnect the individual transceiver ICs within a given transceiver IC subarray, can have a data rate sufficient to accommodate data packets that carry IQ data in either the frequency domain or the time domain. In this regard, as will be described in more detail, each transceiver IC subarray may, for example, (i) receive / transmit aggregated frequency domain IQ data packets to / from the beamformer processor when frequency-time domain conversion (transmission side) and time-frequency domain conversion (reception side) are performed in the individual transceiver ICs (e.g., via respective iFFT (inverse fast Fourier transform) and FFT (fast Fourier transform) processes), or (ii) receive / transmit aggregated time domain IQ data packets to / from the beamformer processor when frequency-time domain conversion (transmission side) and time-frequency domain conversion (reception side) are instead performed in the beamformer processor (e.g., via respective iFFT and FFT processes).

[0015] As an example of a serial link data rate, one symbol of a 100 MHz OFDM 5G carrier with a 30 kHz subcarrier spacing is transmitted in a 33.33 microsecond (μs) time window. For such transmission on two signal ports (e.g., separate signals for H and V polarizations) having 3300 subcarriers, 2 samples (I / Q) per subcarrier, and having, for example, 12 bits / sample, the data rate required is 2×3,300×2×12 = 158.4 kbps for each of 14 OFDM symbol time slots, 14 of which are transmitted in a 0.5 millisecond transmission slot, resulting in a net required data rate of 158.4 k×14 bits / 0.5 millisecond = 4.43 Gbps. If 8b-10b encoding is used on the serial data link and an additional 10% is added for packet headers and protocol overhead, for the dual signal port case, a throughput of approximately 1.1×4.43×10 / 8 Gbps = 6.1 Gbps per carrier is required. In some embodiments, a serial data transmission capacity of 6.1 Gbps (i.e., a set of serially linked transceiver ICs) is sufficient for each transceiver IC subarray. In other embodiments having signal ports independently controlled in each transceiver IC, a total throughput of 12 Gbps, or even on the order of 20 Gbps, is sufficient for most of the applications and configurations described herein, although 30 Gbps may be achieved if desired for some other embodiments.

[0016] For lower-capacity deployments, a lower serial data rate is sufficient. For example, a dual-polarization 20 MHz 4G LTE data signal utilizing a size 2,048 FFT that occupies a transmission slot time window of 66.67 μs requires a data throughput of 2 ports × 1,200 subcarriers x 2 (I / Q samples / subcarrier) x 12 (bits / sample) / 66.67 μs window = 1,200 x 2 x 12 x / 66.67 μs = approximately 864 Mbps. If the data rate is increased by 10 / 8 to accommodate 8b-10b encoding and the overhead is 10%, the data rate is approximately 1.2 Gbps.

[0017] In a further embodiment of the transceiver IC serial data port, a 4-wire interface can be used to double the data rate. Alternatively, so-called ensemble NRZ (ENRZ) signaling, which uses correlation signals in the form of vector signal codes, may be transmitted over 4 wires to carry 3 bits / baud (i.e., per signaling interval), resulting in a 3-fold increase in data rate rather than just a 2-fold increase (at the same baud rate). Thus, using a signaling rate of 7.5 Gbaud / s, a data throughput of 22.5 Gbps can be reliably achieved over the distance from the beamformer to the transceiver IC subarray. As a further alternative, PAM4 signaling (in combination with NRZ or ENRZ signaling) or other vector signal formats (e.g., correlation NRZ (so-called CNRZ-5) that uses correlation signals to carry 5 bits over 6 wires) can be used to increase the data throughput without significantly increasing the signaling baud rate.

[0018] Overall, FIG. 2 shows a total of eight columns of transceiver ICs, each column having eight transceiver ICs for a total of 64 transceiver ICs, and each transceiver IC is configured to process two separate transmit signals (e.g., different RF signals on the H and V signal ports) and two separate receive signals (H / V signal ports). However, in the embodiment of FIG. 2, since the first two rows of the eight transceiver ICs are connected in pairs, these 16 transceiver ICs form a single "row" 238a of eight transceiver IC groups, also referred to herein as transceiver IC sub-arrays. Similarly, the other transceiver ICs are grouped into three additional "rows" (238b, 238c, 238d) of each of the eight transceiver sub-arrays, resulting in a total of eight columns by four rows of transceiver IC groups (32 transceiver IC sub-arrays). In terms of physical dimensions, each column is the width associated with a single juxtaposed cross-polarized antenna, while each "row" of the transceiver IC group encompasses two rows of cross-polarized antenna elements.

[0019] FIG. 4, further described below, also shows 32 transceiver IC sub-arrays within an 8×4 transceiver IC sub-array configuration. However, each transceiver IC sub-array includes three serially connected transceiver ICs. Note that the transceiver IC sub-arrays are arranged adjacent to each corresponding radiating antenna element disposed in a corresponding antenna sub-array on a per-element basis. In some embodiments, the transceiver IC sub-arrays are disposed on the back side of the antenna array panel 102 but are still adjacent (i.e., in proximity) to each respective radiating element used to transmit and / or receive RF communication signals associated with a given transceiver IC. In some embodiments, the transceiver ICs can be coupled to the radiating elements through vias, intermediate structures, and / or circuitry, such as transmit filters and receive filters mounted on the panel or on a sub-panel disposed behind a structure supporting the array of antenna radiating elements.

[0020] Element-by-element adjacency refers to the relative arrangement in which a transceiver IC subarray and a corresponding antenna subarray are superimposed on each other such that each individual transceiver IC of a given transceiver IC subarray is disposed within a region of panel 102 associated with a corresponding antenna radiating element of an antenna array or subarray used to transmit and receive signals associated with that individual transceiver IC.

[0021] As a further example of element-by-element adjacency, in some embodiments such as a frequency division duplexing (FDD) system, two transceiver ICs (one dedicated to generating two transmit (H / V) signals at a transmit frequency and the other for processing two receive (H / V) signals at a receive frequency) can form a transceiver IC subarray associated with an antenna subarray consisting of a single juxtaposed cross-polarized antenna. In a dual-band FDD configuration, four transceiver ICs can be linked as a transceiver subarray and disposed adjacent to an antenna subarray consisting of a single juxtaposed cross-polarized antenna.

[0022] The feature of element-by-element adjacency provides a distributed transceiver IC architecture that allows an amplified transmit RF signal generated by each given transceiver IC to incur very little power loss or noise degradation as it traverses a very short physical connection from the transceiver IC to the radiating element. In some embodiments, different ratios of transceiver ICs to radiating elements can be adjacent in pairs, such that two transceiver ICs can be disposed adjacent to each set of three cross-polarized elements.

[0023] Throughout this description, many embodiments are depicted using transceiver ICs (e.g., 212, 222, 230, 232, etc.) that include two independent full-duplex transceivers each having two transmitters / amplifiers and two independent receivers, and each transceiver is associated with an RF signal port (e.g., 214 or 216) that is interconnected to a respective antenna radiating element (e.g., 218, 220 respectively). Thus, in one embodiment, a single transceiver IC comprises an integrated circuit having two full transceivers that transmit and receive two independent RF signals configured such that one RF signal port (tx / rx) is associated with an H-polarized signal port (e.g., 214) and one RF signal port (tx / rx) is associated with a V-polarized signal port (e.g., 216). In such an embodiment, each transceiver IC may be referred to as a 2T2R transceiver IC and may be associated with a pair of juxtaposed cross-polarized radiating elements. By way of example, each cross-polarized pair of radiating elements (218, 220), (224, 226), (234, 236) is associated with a respective single transceiver integrated circuit such as transceiver IC 212 associated with cross-polarized radiating elements (218, 220), transceiver IC 222 associated with elements (224, 226), and transceiver IC 232 associated with elements (234, 236).

[0024] In other embodiments, each transceiver IC may be configured to provide four separate analog RF transmit and receive paths, e.g., through four independent signal ports (4T4R). Such embodiments may include a dual PLL for generating both the transmit and receive carrier frequencies for full utilization of the transceiver IC when operating in an FDD signaling mode. The particular number of transceivers included within a given transceiver IC may depend on factors such as the desired total output power of the panel, use of additional external power amplifiers, FDD or TDD operation, data throughput of the serial data link providing interconnection between transceiver ICs, and many other factors.

[0025] More generally, referring to FIG. 2, the circuitry of the wireless unit 200 may all be disposed within a single active antenna panel assembly and includes a high throughput packet-based interface 252 to a base station or distributed unit (DU) (not shown). The interface 252 can comprise multiple distinct physical network interfaces, such as four distinct 25 gigabit Ethernet links provided via an optical fiber cable using a small form factor pluggable (SFP) module 242 or a quad SFP (QSFP) module. Data can be conveyed via the interface 240 using an Ethernet protocol, a CPRI / eCPRI protocol, or a similar protocol. The beamformer processor (BFP) 202 performs pre-coding and beamforming operations for downlink transmit data and, in response, generates an aggregated signal port IQ data packet for transmission to each transceiver IC sub-array, as will be further described below with reference to FIGS. 8, 9, and 10. As described above, in some embodiments, the IQ data packet can include frequency domain IQ values of sub-carriers within an OFDM (orthogonal frequency division multiplexing) communication system, such as an LTE or 5G communication system. In other embodiments, the IQ data packet may instead include time domain IQ values for sub-carriers within an OFDM communication system or for other carriers, such as a 2G GSM signal. In the uplink direction, the BFP 202 performs beamformer combining to acquire virtual beamforming antenna port signals and further combining to recover the user data layer, as will be further described below with reference to FIG. 11.

[0026] In the embodiment shown in FIG. 2, the beamformer processor 202 is connected to each transceiver IC subarray via a serial data link such as link 206. Depending on the length of the data links shown as four sets 204a, 204b, 204c, 204d of eight links each, each data link can utilize Serdes repeaters / retimers 208, 210 to extend the range of the serial data link from BFP 202 to the area of panel 102 where a given transceiver IC subarray (and corresponding antenna subarray element) is located. In the alternative embodiment shown in FIG. 4, BFP 400 is connected to a set of transceiver IC subarrays via a high-speed Serdes link 402, and then a Serdes multiplexer (MUX) 404 (and respective high-speed links to Serdes MUXes 422, 424, 426) demultiplexes (i.e., separates) the high-speed serial data stream into slower-speed serial data streams 406 directed to each individual transceiver IC subarray. The Serdes MUX devices 404, 422, 424, 426 perform a demultiplexing operation on the uplink data being carried from the transceiver IC subarrays to BFP 202.

[0027] Referring to FIG. 2, one exemplary transceiver IC subarray comprises transceiver IC 222 and transceiver IC 232 coupled via serial data link 228. These two transceiver ICs are located adjacent to respective antenna radiating elements 224, 226 and 234, 236. In some embodiments, they are disposed on one side of a printed circuit board in proximity to the antenna elements and are electrically connected using through vias or by intermediate circuit elements such as filters, diplexers, quadplexers, SPDT (single pole double throw) TDM switches. As shown in FIG. 2, each transceiver IC generates two separate RF transmit downlink (DL) signals for H and V polarities and receives and processes two separate RF uplink (UL) signals. Also shown is monitoring transceiver 246 connected to BFP202 by serial data link 244, and RF signal connection 248 is interconnected with each transceiver via a calibration network.

[0028] Figure 3 shows one such group of serially connected transceivers disposed at the transceiver IC subarray positions adjacent to each corresponding antenna radiating element of the corresponding antenna subarray disposed within the antenna panel array 102. An incoming packet for DL transmission is received at the first transceiver IC 312 from 300BFP via the serial data link 308, and at least some of the packets are propagated to other transceiver circuits within the transceiver group in the transceiver ICs 350, 366 through the serial data connections 348, 364. Similarly, an incoming RF signal on the UL is processed and packetized for sending back along the serial data transceiver IC chain 362, 346, 310. In this embodiment, each transceiver IC is configured to process two separate transmit signal paths and two separate receive signal paths via two separate signal ports typically associated with two corresponding antenna radiating elements. The transceiver subarray of Figure 3 operating in TDD mode is configured such that the transceiver IC 312 transmits and receives RF signals on the first signal port 328 and transmits and receives RF signals on the second signal port 344. Similarly, the transceiver IC 350 is associated with signal ports 356 and 360, and the transceiver IC 366 is associated with signal ports 370 and 378.

[0029] As described above, the two transceiver signal ports of the transceiver IC may be interconnected to a single set of cross-polarized antenna elements. In the case of TDD operation, this provides 2T2R (two transmit and two receive) signal processing capabilities. In an alternative embodiment, the two signal ports can each be connected to corresponding radiating elements within two different cross-polarized antenna pairs. For example, the first transceiver of the transceiver IC process transmits and receives signals regarding the vertical polarized element of the first cross-polarized radiating element pair, and the second transceiver of the same transceiver IC process transmits and receives signals regarding the vertical polarized element of the second cross-polarized radiating element pair. Next, the second transceiver IC can be used to process signals related to the two horizontal polarized elements of the two cross-polarized pairs.

[0030] In a further alternative embodiment, the output of each signal port may be split and one signal port may be connected in parallel to two (or three, etc.) vertically polarized radiating elements, and the other signal port may be connected in parallel to horizontally polarized radiating elements of the same two (or three, etc.) cross-polarization pairs, etc., and may be connected in parallel to a plurality of radiating elements. In further embodiments described herein below, the amplified RF signals generated by a transceiver IC, or by a plurality of transceiver ICs, may be provided to additional amplifier stages external to the transceiver IC and / or combined before being provided to the radiating elements.

[0031] In some embodiments, for example, frequency domain I / Q data packets are transmitted to a set of serially connected transceiver ICs distributed on an active antenna panel. The aggregated data packets are a superposition of frequency domain sub-carrier specific data and typically represent resource blocks (RBs) allocated over many data layers and possibly many users, with different beamforming weights applied, and thus contain full beamforming (including MIMO precoding if used) sub-carrier IQ sample data for a specified band, component carrier, and signal port. Each IQ data packet may have a single header, but nevertheless may contain concatenated or interleaved data for multiple signal ports such as H and V signal ports. Such packets may be referred to as dual signal port packets. In some embodiments, the packet header may include identification data associated with a particular transceiver IC and may include IQ data for any number of signal ports processed by that transceiver IC and may generally be referred to as multi-signal port data.

[0032] The user-aggregated frequency domain data of packet 302 in FIG. 3 represents frequency domain IQ data packets that are commonly processed by the transceiver ICs within a given transceiver IC subarray. Packet 302 may include a header (not shown for clarity) that identifies various aspects of the type of data contained in the packet, as well as packet identification data such as one or more of a frequency band ID, a component carrier ID, a signal port ID, and / or a transceiver ID. The primary payload data within packet 302 includes subcarrier-specific IQ data for a signal port (e.g., a horizontal polarization RF signal for a particular component carrier labeled "H" in FIG. 3). The same packet (or, in some embodiments, a separate packet with a separate header and ID data fields) includes subcarrier IQ data for a second signal port (e.g., a vertical polarization RF signal for, e.g., the same component carrier labeled "V" in FIG. 3). In many of the embodiments described herein, a single transceiver IC is configured to process two separate signal port IQ packets, and the corresponding IQ data for the two signal ports may be combined into a single packet having a single header, and is sometimes referred to herein as a "dual signal port packet." Packet 302 is shown as a concatenated IQ data set for the subcarriers of the H-polarization signal port and the V-polarization signal port, but the IQ data may be interleaved, such as an IQ sample pair for the H signal port and a pair for the V signal port for subcarrier 1, followed by IQ pairs for H and V for subcarrier 2, and so on. Each I and Q sample may be represented as some number of bits, such as 12, 14, or 16, depending on the desired signal resolution. Packet 302 may include IQ sample data for some number of subcarriers, such as 612, 1,596, 3,276, or more, for each signal port, for a particular carrier, and for a frequency band.

[0033] As described above, the aggregated beamforming IQ data packets communicated from / to the BFP (beamformer processor) via the serial data connection (link) and between the transceiver ICs may include either frequency domain (subcarrier specific) IQ data or time domain (subcarrier specific) IQ data. In this regard, it should be noted that packet data transmission of the aggregated beamforming frequency domain IQ data packets via the serial data connection from / to the BFP and between the transceiver ICs is more efficient than packet data transmission of the aggregated beamforming time domain IQ data. In particular, the frequency domain IQ data specifies the in-phase and quadrature (IQ) values of specific subcarriers used for data transmission (and reception) in a given communication system. However, in the case of DL signals in an OFDM communication system (e.g., an LTE or 5G communication system), before converting the frequency domain IQ data to time domain digital data via an iFFT, 0 values may need to be inserted into the IQ data set to account for unused subcarriers (e.g., subcarriers used as guard bands) within a given component carrier, thereby resulting in a time domain sequence of the converted IQ data having more IQ data points that need to be carried to the transceiver IC / transceiver IC subarray (e.g., first carried from the BFP and then distributed among the transceiver ICs within a given transceiver IC subarray accordingly). Similarly, in the case of UL signals, the frequency domain IQ data processed via an FFT can exclude the frequency domain values of the unused subcarriers, but the equivalent time domain IQ data associated with the unused subcarriers is a component of the time domain IQ data that may not be removed prior to the transmission of the time domain data via the serial data connection as described herein.

[0034] In this regard, depending on the bandwidth of a given communication channel, an increase in the efficiency of communicating frequency-domain IQ data across the corresponding time-domain IQ data can be relatively important. As an example, in the case of a 20 MHz-wide LTE channel, the ratio of unused subcarriers to data-modulated subcarriers will be larger than the similar ratio in the case of a 100 MHz-wide LTE channel. Therefore, it becomes more efficient to communicate subcarrier-specific IQ data in the frequency domain rather than in the time domain. More specifically, as explained above, even when a subset of subcarriers remains unused (not modulated / loaded with data), their time-domain representation still results in complex time-domain samples, thereby increasing the amount of data that needs to be transmitted over a serial data link. Further, the serial data links between the BFP subarray and the transceiver IC subarray, as well as the serial data links interconnecting the individual transceiver ICs within a given transceiver subarray, may have a limited data-carrying capacity (e.g., how much data can be communicated over those links per given period (data rate)). Thus, in some embodiments, it may be more desirable to perform IQ packet data transmission in the frequency domain, from / to the BFP and between transceiver ICs.

[0035] Nevertheless, various embodiments of the signal processing methods and apparatuses described herein can instead utilize time domain IQ data packets. More specifically, as will be described in more detail, in some embodiments, a beamforming processor (BFP) (e.g., BFP202, 300, 400, etc.) can be configured to include a digital signal processing architecture (e.g., iFFT and FFT processing elements) to transmit and receive time domain IQ data packets from / to a transceiver IC / transceiver IC subarray. For example, in some embodiments, the beamforming processor may include a digital signal processor (DSP) configured with appropriate programming instructions to execute algorithms for IFFT and FFT operations. For purposes of explanation, assuming, for example, that the IQ data packets communicated to / from BFP300 and between individual transceiver ICs are frequency domain IQ data packets, the various operating principles associated with the arrangement shown in FIG. 3 can be described below.

[0036] The transceiver subarray shown in FIG. 3 is one of many such subarrays on a panel, and each serially connected group of transceiver ICs receives a unique data stream of aggregated signal port (or dual signal port, or multi-signal port) IQ data packets. It should be recalled that each serially connected group of transceiver ICs has at least two serially connected transceiver ICs and is physically located within the transceiver IC subarray. Next, the transceiver IC subarray is disposed adjacent to corresponding radiating antenna elements disposed in a corresponding antenna subarray on a per-element basis.

[0037] Transceiver IC 312 receives, at serial port receiver 314, a unique data stream of an aggregated signal port IQ data packet, such as the user-aggregated frequency domain data of packet 302 (as described above), and provides the data to split copy register 318 for further processing. In one embodiment, split copy register 318 is a packet header processor configured to inspect the packet header to determine whether the IQ data is intended to be processed by its corresponding transceiver IC, and if so, transfer the packet to signal port split processor 320. Signal port split processor 320 (also labeled H / V split) is addressed to different signal ports within the transceiver IC and identifies H and V polarization signals, or packets or portions of packets that may be other configurations described herein. Signal port split processor 320 may be implemented as a register that performs a memory write operation to a digital signal processor (DSP) memory space integrated within transceiver IC 312. Further, split copy register 318 can determine that the same packet should also be transferred to the next transceiver IC within the transceiver IC subarray for processing by one or more of the serially-connected transceiver ICs. To reduce latency, the packet header processor or split copy register 318 does not need to buffer the entire signal port IQ data packet before making a decision to transfer the packet to the next transceiver IC by sending the data to serial data transmitter 332 for transmission via serial link 348. In a further embodiment, packet header processor 318 may be configured to operate in a transparent mode, in which case all packets are saved for local processing and transferred to a second serial transceiver without header inspection.

[0038] Regarding the signal port packet format 302, the aggregated IQ signal port packets are transferred to each transceiver IC using split copy circuits 318, 352, 368 and are commonly processed by each transceiver IC. Transceiver IC 366 is the last transceiver IC in the chain, and in the illustrated embodiment, note that split copy register 368 transfers the packet to the corresponding signal port split processor, but serial transceivers 372 / 374 are not used.

[0039] Next, each transceiver IC processes the packet by first separating the IQ data for the first signal port (H IQ data 322) and the second signal port (V IQ data 338) and providing the data to the transmitters in transceivers 321 and 335 to convert it to the time domain via an inverse fast Fourier transform (iFFT). As previously explained, the individual IQ port specific data may be carried in separate packets, in which case the signal port data may be directly stored for further processing without any separation or deinterleaving. The iFFT processing and subsequent time domain processing generate an aggregated signal port discrete time domain baseband data signal, which is then followed by a conversion to a radio frequency (RF) signal amplified at ports 328, 344. The transmitters of transceivers 321, 335, more fully described with respect to FIGS. 12A and 13A, include a DSP for calculating the iFFT, frequency domain and time domain signal processing elements (cyclic prefix addition, phase and gain adjustment, frequency offset, filtering and sample rate conversion, crest factor reduction (CFR), digital pre-distortion (DPD), etc.), and RF modulation and amplification circuitry in the form of a polyphase carrier generator and a digital power amplifier. For example, in an alternative embodiment including the communication of aggregated signal port / user IQ data packets in the time domain (more particularly described in relation to FIG. 12B), note that the iFFT processing may be performed in the beamformer processor instead of the transceiver IC itself.

[0040] Accordingly, some embodiments include receiving, in each of a plurality of serially connected transceiver IC groups, a unique data stream of aggregated signal port IQ data packets, where each serially connected transceiver IC group is physically disposed within a transceiver IC subarray and includes at least two serially connected transceiver ICs disposed adjacent to each corresponding radiating antenna element disposed within a corresponding antenna subarray; transferring at least a subset of the aggregated signal port IQ data packets from a first transceiver IC to the next serially connected transceiver IC within each serially connected transceiver IC group; processing, in each transceiver IC of the at least two serially connected transceiver ICs within each serially connected transceiver IC group, at least a portion of the aggregated signal port IQ data packets using an integrated inverse fast Fourier transform (IFFT) processor of the transceiver IC to convert the aggregated signal port IQ data packets to an aggregated signal port discrete time domain baseband data signal; converting the aggregated signal port discrete time domain baseband data signal to an amplified modulated radio frequency signal using an integrated digital power amplifier and a polyphase carrier generator of the transceiver IC; and transmitting the amplified modulated radio frequency signal using at least one of the corresponding adjacent radiating antenna elements.

[0041] Furthermore, some embodiments can include an apparatus comprising a plurality of transceiver IC sub-arrays, each transceiver IC sub-array comprising: a first transceiver IC having (i) a first serial digital data port that provides a serial data connection to a beamformer processor and is configured to receive a unique data stream of an aggregated signal port IQ data packet, and (ii) a second serial digital data port; and a second transceiver IC connected to the second serial data port of the first transceiver IC and having a third serial digital data port that provides a serial data connection to the first transceiver IC. The first transceiver IC and the second transceiver IC are physically disposed within the transceiver IC sub-array and may be disposed adjacent to each other for each of a plurality of radiating antenna elements disposed within the antenna sub-array. The first transceiver IC of each transceiver IC sub-array may further include a packet processor configured to transfer at least a subset of the aggregated signal port IQ data packets received from the beamformer processor to the respective second transceiver IC. Each of the first transceiver IC and the second transceiver IC may include a digital signal processor configured to perform an inverse fast Fourier transform (IFFT) to convert the aggregated signal port IQ data packet into an aggregated signal port discrete-time domain baseband data signal, a time domain processing circuit configured to convert the aggregated signal port discrete-time domain baseband data signal into an oversampled signal port discrete-time domain data signal, and an integrated digital power amplifier and polyphase carrier generator configured to convert the oversampled signal port discrete-time domain data signal into an analog-modulated radio frequency signal.

[0042] When receiving an uplink (UL) signal, the receiver parts of transceivers 321 and 335 perform frequency down-conversion and analog-to-digital conversion, and then perform further time-domain processing (such as sample rate conversion, quadrature error correction, filtering, frequency offset correction, cyclic prefix detection and removal, etc.). After that, for each of the multiple subcarriers in the OFDM signal, an FFT conversion to frequency-domain IQ data values is performed. Therefore, in the receive operation mode, the transceiver IC generates the IQ data packets 322 and 338 shown in FIG. 3 from the received RF signal.

[0043] In one embodiment, the transceiver IC not only performs all of the iFFT calculations to generate a downlink (DL) transmit time-domain signal port signal, but also includes a digital signal processor (DSP) that processes received uplink (UL) data samples via an FFT to generate a received frequency-domain IQ data signal associated with each of the signal ports. However, in an alternative embodiment, for example, including communication of aggregated signal port / user IQ data packets in the time domain, the FFT processing may be performed in a beamformer processor instead of the transceiver IC itself (as described in more detail in connection with FIG. 12B).

[0044] Regarding embodiments related to the packet structure 302, the UL frequency domain IQ data from each signal port can first be concatenated into a single packet of the format of packet 302, which has H and V parts representing UL receive frequency domain IQ information locally generated in the transceiver IC. However, since the received IQ packet is carried along the transceiver IC subarray, the received UL frequency domain IQ packet received via a serial data link from another transceiver IC within the subarray can be combined with the locally generated received IQ data before being transmitted to the next transceiver IC. Specifically, when transceiver IC 350 receives a UL IQ packet on link 362 from transceiver IC 366, the UL IQ packet processor 358 combines the received IQ data with its locally generated UL IQ data. As will be more fully described herein, the combination can involve sample-by-sample addition (i.e., for each subcarrier, the I data samples are added and the Q samples are added), or the I data and Q data of one packet can have phase rotation added before combination. Next, the combined UL IQ data packet received on link 346 via the Serdes receiver 330 is further combined with the locally generated UL IQ data from transceivers 321 and 335 stored in the UL signal port IQ data combiner 336. In this way, in embodiments related to the packet data format 302, the amount of received data transmitted along links 362, 346, 310 remains the same for each serial data link along the transceiver IC subarray.

[0045] Accordingly, in a further embodiment, the method comprises receiving modulated RF signals at a plurality of signal ports of each transceiver IC within a sub-array of serially-connected transceiver ICs, demodulating each of the modulated RF signals from each signal port using an FFT processor within each transceiver IC to generate one or more frequency domain digital data packets of sub-carrier IQ data associated with each signal port, forming a plurality of combined frequency domain digital data packets from the transceiver ICs using a set of serial data links between the transceiver ICs of the sub-array of serially-connected transceiver ICs, and transmitting the plurality of combined frequency domain digital data packets from the sub-array of transceiver ICs to a beamformer processor.

[0046] Furthermore, in some embodiments, each transceiver IC may be configured to process signals from two signal ports, such as from a cross-polarized antenna element or a set of parallel-connected elements. Other embodiments may use a transceiver IC having four distinct signal ports. In each embodiment, a given signal port may receive a plurality of modulated carriers (each having a set of subcarriers), and the demodulated frequency-domain data may be packetized according to the component carriers on which it was received. Thus, one or more frequency-domain digital data packets of subcarrier IQ data associated with each signal port may be packetized with header information identifying the signal port (such as a signal port ID), the component carrier (such as a component carrier ID), and additional identification information (e.g., a subcarrier subset ID for use in multi-layer beamforming). Each transceiver IC can participate in the formation of a plurality of combined frequency-domain digital data packets by receiving frequency-domain digital data packets of subcarrier IQ data from an adjacent transceiver IC via a serial data link and combining it with its own locally-generated frequency-domain digital data packets of subcarrier IQ data. Depending on the position of a given transceiver IC within a transceiver IC subarray, some transceiver ICs actually receive a partially formed combination of frequency-domain digital data packets.

[0047] In an embodiment related to the packet structure 304 (note that no header is shown for clarity), six separate signal port packets may be provided to the transceiver IC subarray, from which six independent transmit signals may be generated. Generally, the ability of an AAU system to generate independent RF transmit signals from separate digital IQ data associated with each radiating element is referred to herein as full-dimensional beamforming. In this embodiment, full-dimensional digitally beamformed signals are represented, and all six packets are received at the transceiver IC 312 via link 308 at the receive Serdes 314 and provided to the split copy processor 318. The split copy processor 308 examines the packet header and transfers the first set of two signal port packets (the H / V portions 324, 340 at the right end of format 304) to the signal port split processor 320 for transmission processing of the IQ data 324 (for port 328) by the transceiver 321 and transmission processing of the IQ data 340 (for port 344) by the transceiver 335, and transfers the remaining four packets to the Serdes transmitter 332. The next transceiver IC 350 receives the four packets via link 348 at its Serdes receiver, and the split copy processor 352 performs packet header analysis and transfers the two signal port packets to its signal port split processor 354 within 350, and transfers the remaining two packets to the Serdes transmitter (TX#0 of transceiver IC 350) for transmission to the transceiver IC 366 via link 364. The signal port split processor 354 provides the H and V signal port IQ data to its transceiver for transmission on signal ports 356, 360 respectively. The transceiver IC 366 receives the remaining two IQ data packets and processes them in a similar manner for transmission at ports 370, 378. Note that the amount of serial data decreases along the transceiver IC subarray for the DL IQ data packets. In this embodiment, the receive processing does not include any UL IQ packet data combining.Rather, the packets are simply retransmitted from each transceiver IC (using the UL IQ packet processors 358 and 334 for concatenation / resending), and as a result, all six received UL signal port IQ packets are carried to the beamformer processor via link 310 (the packets may be formatted with individual headers or carried as a concatenated payload with a single header). Note that the amount of data increases as the packets on link 362 from transceiver IC 366 are concatenated with the IQ data from transceiver IC 350 in UL IQ packet processor 358 for transmission via link 346. The amount of data increases again on link 310 as the UL IQ data 340 and 324 from UL signal port IQ data concatenator 336 are concatenated by UL IQ packet processor 334.

[0048] In some embodiments, fully dimensional beamforming packets that are unique to each signal port may be provided for narrower bandwidth signals such as 20 MHz data bandwidth. This may be desirable in some deployments where the AAU panel is configured with lower rate serial data connections in the transceiver IC subarray. Thus, even in a system with slower serial data interconnects, it is possible to support full control of the signal port signals (and corresponding radiating elements) by concatenating the separate IQ data of the interconnected transceiver ICs and extracting the relevant data sets at each IC. This enables support for MU-MIMO in the vertical plane with much higher accuracy and supports use cases associated with flying drones (either drones with data connectivity as users within the system or drones that block interference from high altitude jamming drones).

[0049] In a third embodiment of the antenna array system, a multi-layer beamforming signaling scheme can be used to provide data transmission and reception. In this embodiment, some transmit IQ data packets are processed commonly among a plurality of transceiver ICs to achieve a first level of beamforming resolution, and an additional set of IQ data packets is distributed to each of the transceiver IC subarrays, and each packet of a given additional set of transmit IQ data packets is processed among fewer (or even one) transceiver ICs within the transceiver IC subarray to obtain a second, higher resolution level of beamforming. Specifically, the data format 306 provides a combination of beamforming resolutions, whereby two signal port IQ data packets (e.g., the first two H and V parts of 306, 326, 342) are processed for transmission by each of the transceiver ICs 312, 350, and 366 in a manner similar to the signal processing described above with respect to the packet format 302. Since the same IQ data is converted and transmitted by a plurality of corresponding radiating elements within the subarray, these IQ data packets, referred to herein as "commonly processed" IQ data, result in a first layer of beamforming resolution, and the beam is formed as a result of the phase signal contributions from other subarrays (i.e., inter-subarray beamforming). However, further, an additional set of six signal port IQ data packets (three additional sets of the H / V data of 306) is distributed across a given transceiver IC subarray in a manner similar to the signal processing described above with respect to the packet format 304 for full digital beamforming data. These additional packets are specific to a given signal port and / or transceiver IC and provide a unique IQ data stream for transmission by each individual signal port within a given transceiver IC subarray, thereby providing transmission and reception at a second layer of beamforming resolution.Specifically, the beam is formed as a result of the phase signal contributions emitted from other transceiver ICs within a given subarray, as well as the phase signal contributions emitted from other transceiver ICs within other transceiver IC subarrays (i.e., second layer beamforming from both in-subarray beamforming and between-subarray beamforming).

[0050] Multilayer beamforming having a packet of form 306, shown in FIG. 3 and further described below with respect to FIGS. 12A - 12B, 13A, and 13B, utilizes the processing of two separate signal port IQ packets, such as IQ data 326 and IQ data 327 (and similarly 342, 343), that are shown to be combined for transmission on the same signal port. In one embodiment, the beamforming IQ packets, separately, can include IQ data points for different sub - carriers within a set of sub - carriers of a single component carrier. Thus, each transceiver IC can form its own unique combined set of IQ data points for its respective signal port prior to the iFFT processing. Specifically, transceiver IC 312 combines IQ data 326 and 327 for transmission on signal port 328 and combines IQ data 342 with IQ data 343 for transmission on signal port 344 via concatenation. Transceiver IC 350, the next transceiver IC within the transceiver IC sub - array, combines IQ data 326 (the same as that processed by transceiver 321 of transceiver IC 312) with signal port IQ data 355 and combines IQ data 342 (the same jointly processed IQ data as that processed by transceiver 335 of transceiver IC 312) with signal port IQ data 359. A similar unique concatenated combination is shown for transceiver IC 366, where IQ signal port data packets 326 and 342 are combined with unique signal port IQ data 369, 377 respectively. Within the transceiver IC sub - array, the jointly processed IQ packets 326 and 342 provide a first - layer beamforming component contributed by the sub - array, and an additional set of IQ packets distributed within the transceiver IC sub - array provides a second - layer beamforming component associated with that sub - array.

[0051] In a further embodiment, the separate IQ packets may have overlapping subcarriers, in which case the transceiver IC processing includes forming a weighted average of the overlapping subcarriers prior to the iFFT processing. In such an embodiment, the beamformer processor can carry one or more weights for the transceiver IC used when forming combinations of IQ transmit data for the overlapping subcarriers.

[0052] Thus, in one embodiment, multi-layer transmit beamforming includes receiving, in a plurality of transceiver ICs of a transceiver IC subarray, a first layer beamforming IQ packet and a plurality of second layer beamforming packets via a serial data connection interconnecting the transceiver ICs; forming, in each transceiver IC, a multi-layer beamforming packet by combining the first layer beamforming IQ packet with at least one of the second layer beamforming packets of the plurality of second layer beamforming packets; generating a time domain signal from the multi-layer beamforming packet; and transmitting a multi-layer beamforming signal by transmitting, from the transceiver ICs of the transceiver IC subarray, respective amplified radio frequency time domain signals via corresponding adjacent antenna element subarrays.

[0053] In some embodiments, each of the first layer beamforming IQ packet and the plurality of second layer beamforming packets includes frequency domain IQ data. In other embodiments, each of the first layer beamforming IQ packet and the plurality of second layer beamforming packets includes time domain IQ data.

[0054] In some embodiments, the multi-layer beamforming packet is formed by concatenating IQ samples of separate sub-carriers via concatenation and then processing the packet using the same iFFT operation. In other embodiments, the multi-layer beamforming packet is formed by combining overlapping sub-carriers using weights provided via management plane messages and then processed by the same iFFT operation.

[0055] In yet further embodiments, the IQ packet carrying data used for second layer beamforming may be associated with sub-carriers of separate component carriers. In such embodiments, additional higher resolution beamforming data may be processed independently using separate iFFTs before combining the two layers of time domain signals of the beamforming signal. Thus, in one embodiment, multi-layer transmit beamforming includes receiving, in a plurality of transceiver ICs of a transceiver IC sub-array, a first layer beamforming IQ packet and a plurality of second layer beamforming packets via a serial data connection interconnecting the transceiver ICs; in each transceiver IC, converting the first layer (commonly processed) beamforming IQ packet into a time domain signal and separately converting, via separate iFFTs, at least one of the plurality of second layer beamforming IQ packets into a time domain signal; combining the two time domain signals to form a signal port specific multi-layer beamforming time domain signal; and transmitting, from the transceiver ICs of the transceiver IC sub-array, an amplified radio frequency time domain signal generated from each signal port specific multi-layer beamforming time domain signal via a corresponding adjacent antenna element sub-array, thereby transmitting a multi-layer beamforming signal. The plurality of transceiver IC sub-arrays and their corresponding antenna element sub-arrays cooperate to generate a multi-layer beamforming signal.

[0056] In multi-layer beamforming that uses the distribution of multi-layer IQ packet data among each of a plurality of transceiver IC sub-arrays, one set of users can be served by aggregated IQ signal port packets that are copied and transferred for processing by each transceiver IC along a given transceiver IC sub-array, resulting in a first level of beamforming resolution (e.g., as determined by the total number of unique independent signal port IQ packet streams transmitted to the total number of corresponding transceiver IC sub-arrays for processing by each transceiver IC). However, further, by distributing additional signal port-specific IQ data packets along the transceiver IC sub-array for separate processing by each individual transceiver IC (i.e., IQ data not processed in common), a separate set of users can be served by higher-resolution beamforming.

[0057] Note that in many embodiments, the IQ packets processed in common for multi-layer beamforming signal processing are unique to a particular transceiver IC sub-array. However, in some scenarios, in order to achieve a desired beam radiation pattern (i.e., one with a lower degree of beamforming resolution), some IQ packets processed in common can be the same for two or more transceiver IC sub-arrays.

[0058] The UL received signal processing for multi-layer beamforming is also a hybrid of the UL received signal processing described above, where IQ data combination can be performed for the first pair of signal port IQ packets, and IQ data concatenation can be performed for an additional set of independent UL signal port IQ data packets. Thus, the first layer beamforming is performed by each transceiver IC involved in the formation of the UL combined frequency domain digital data packet by receiving the frequency domain digital data packet of the sub-carrier IQ data from an adjacent transceiver IC via a serial data link and combining it with its own locally generated frequency domain digital data packet of the sub-carrier IQ data. The second layer beamformer processing involves carrying the UL received IQ packets, without combining them, rather via concatenation (either sample-by-sample or packet-by-packet so as not to change the IQ samples) along a transceiver IC sub-array.

[0059] In some embodiments configured as an array of N×M transceiver ICs comprising a set of N transceiver IC sub-arrays each having M serially-connected transceiver ICs, multi-layer beamforming processes a first set of aggregated beamforming frequency domain IQ user data according to a first layer of beamforming resolution to generate N unique beamforming IQ data packets (or a set of packets such as an IQ data set for each signal port (e.g., H and V) within a transceiver IC), each of which is assigned to one of each of the N transceiver IC sub-arrays, and processes a second set of beamforming aggregated frequency domain IQ user data sets according to a second layer of beamforming resolution to generate N different sets of M unique beamforming IQ data packets (or a set of packets for a set of signal ports of each transceiver IC), each of the N sets of M packets being assigned to one of each of the N transceiver IC sub-arrays. Each of the various packets is transmitted to the N transceiver IC sub-arrays via respective serial data links. Each transceiver of a given sub-array processes in common the packets associated with the first layer beamforming data, combined separately with only a portion of the second layer beamforming packets.

[0060] Referring to FIG. 16, an embodiment of two-layer beamforming is shown, where the panel uses sub-array level beamforming (such as shown in configuration 1604) with three dual-polarization elements per sub-array 1606 and is configured to process UL and DL data according to first-layer beamforming that provides a beam (e.g., 1612) within a scanning range 1614. In the embodiment shown, the sub-array level beamformer generates beamforming IQ packets for frequency content 1618 that is commonly processed within each respective sub-array, as described with respect to IQ data 326 and 342. The same panel can be configured simultaneously (as shown in configuration 1600) to provide another or second-layer beamforming with higher phase resolution using a unique beamforming IQ data set for generating a unique signal at each cross-polarization element 1602. In the embodiment of FIG. 16, the frequency content 1616 can be assigned to a high-resolution beamforming layer such as data 327, 343, 355, 359, 369, and 377. The frequency content of frequency range 1616 and frequency range 1618 can correspond to different sub-carriers within a single component carrier or can be separate component carriers, etc., as described herein.

[0061] In the beamforming of the second layer, it should be noted that individual beams (e.g., 1608) can be directed over a wider scanning range 1610 due to higher phase resolution. In contrast, the scanning angle in subarray beamforming (where multiple signal ports transmit and receive signals processed according to a common IQ beamforming packet) has a limited scanning range due to increased quantization error in the beamforming weights, as shown in FIG. 17. In particular, the scanning angles of two representative beams represented by the slashes labeled "desired BF weights" show two individual beams with different scanning angles. In full-dimensional beamforming, the IQ data for each signal port is formed using the desired weights with phases as shown, including, for example, points 1702, 1710, and 1706 for lower-angle scanning angles, and exemplary points 1712, 1720, and 1716 for steeper scanning angles (shown as dashed lines). However, in subarray beamforming, the beamforming IQ data processed in common can be generated using the average phase for the desired beam over the elements within a given subarray, as indicated by the exemplary phases 1704, 1710, 1708 for one beam and 1714, 1718, 1720 for the steeper beam. The corresponding beamforming weight phase error is indicated by the line labeled "BF weight error". Note that steeper scanning angles have higher beamformer weight errors. As a result, the beamforming of the second layer allows for larger scanning angles because there is no quantization error and subarray beamforming has a reduced scanning range. In the case of a two-element subarray, it should be noted that the beamforming weights used in forming individual beams can be the average value between two desired phase values, or otherwise a value between two desired weight phases. Finer phase control avoids what is sometimes called a "quantization lobe" that is generated because the weights applied are constrained to be the same for several adjacent elements within the subarray. The quantization lobe increases as the scanning angle increases.

[0062] In short, full-dimensional beamforming is performed with a higher level of precision in the beamformer weights, while subarray beamforming is performed with the average of the desired weights, introducing errors. Therefore, an element configured according to configuration 1600 with full-dimensional control has a larger scanning range than the subarray beamforming configuration 1604 that is beamformed using the average bf weights for each given beam (such as a UE-specific beam or a spatial multiplexing layer beam).

[0063] The multi-layer beamforming described herein can be used to provide high-quality services to a set of users, such as users located in high-rise buildings within a cell sector, without sacrificing the coverage of other user devices located at ground level (e.g., by restricting the allocated data bandwidth). Similarly, the system enables support for communication with drones and other high-altitude devices in combination with user devices at ground level. The systems described herein are configured to provide these alternative beamforming transmissions among user devices within a single radio unit.

[0064] A multi-mode beamforming system can be configured to sequentially or dynamically allocate OFDM transmissions for each slot according to two or more levels of beamforming resolution. In particular, the first time transmission time interval (TTI) or even the first OFDM symbol time slot can be assigned to a user device that is beamformed according to a first layer of sub-array level beamforming such that the transmitted IQ data packets sent to each transceiver IC sub-array are commonly processed by each of the transceiver ICs within such each sub-array during transmission signal processing. Similarly, during signal reception, the processed IQ data packets of each transceiver IC are combined as they are conveyed from transceiver IC to transceiver IC along the serially connected transceiver ICs within each sub-array. In a second or subsequent time slot, the frequency resource blocks can be assigned to the user device for higher resolution beamforming, including full control beamforming IQ data according to a second layer of higher phase resolution beamforming, where the individual transmitted IQ packets are separately formed for serial data transmission and are sent to each transceiver IC sub-array for individual processing by specifically addressed transceiver ICs within each transceiver IC sub-array.

[0065] In some embodiments, the transmit bandwidth associated with a full-control digital beamforming IQ data packet (i.e., the number of IQ sample pairs corresponding to the number of modulated subcarriers) may be smaller than the bandwidth utilized by the commonly processed IQ data packet, such as a comparison between the commonly processed packet data of 302 and the full digital beamforming packet data of 304. In some embodiments, the method of multi-layer beamforming is to receive a first-layer beamforming frequency-domain IQ data packet and a plurality of second-layer beamforming frequency-domain IQ data packets in a transceiver IC sub-array having a plurality of interconnected transceiver integrated circuits (ICs), where the transceiver ICs are interconnected via a plurality of serial data connections, and in each transceiver IC of the transceiver IC sub-array, combining the beamforming frequency-domain IQ data from the first-layer beamforming frequency-domain IQ data packet with the beamforming frequency-domain IQ data from a selected one of the second-layer beamforming frequency-domain IQ data packets among the plurality of second-layer beamforming frequency-domain IQ data packets to form a multi-layer beamforming frequency-domain IQ data set, using a digital signal processor (DSP) within the transceiver IC to generate a discrete-time domain signal from the multi-layer beamforming frequency-domain IQ data set, generating a modulated radio frequency (RF) signal from the discrete-time domain signal, and transmitting a multi-layer beamforming signal by transmitting each modulated RF signal from the transceiver ICs of the transceiver IC sub-array via the corresponding adjacent antenna element sub-arrays. Transmitting the multi-layer beamforming signal may be performed by transmitting each modulated RF signal from the transceiver ICs of the plurality of transceiver IC sub-arrays via the corresponding plurality of adjacent antenna element sub-arrays.

[0066] In some embodiments, the method includes receiving a first layer beamforming frequency domain IQ data packet and a plurality of second layer beamforming frequency domain IQ data packets in a transceiver integrated circuit (IC) subarray, the receiving including transferring the first layer beamforming frequency domain IQ data packet from a first transceiver IC of the transceiver IC subarray to an additional transceiver IC of the transceiver IC subarray for common processing, and transferring only a subset of the plurality of second layer beamforming frequency domain IQ data packets from the first transceiver IC to the additional transceiver IC. In some embodiments, the subset of the second layer beamforming frequency domain IQ data packets is identified according to a packet header. Some methods combine beamforming frequency domain IQ data from the first layer beamforming frequency domain IQ data packet with beamforming frequency domain IQ data from a selected one of the second layer beamforming frequency domain IQ data packets by concatenating the beamforming frequency domain IQ data from the first layer beamforming frequency domain IQ data packet with the beamforming frequency domain IQ data from a selected one of the second layer beamforming frequency domain IQ data packets. Combining the beamforming frequency domain IQ data from the first layer beamforming frequency domain IQ data packet with the beamforming frequency domain IQ data from a selected one of the second layer beamforming frequency domain IQ data packets is, in some instances, performed by forming a weighted sum of the beamforming frequency domain IQ data from the first layer beamforming frequency domain IQ data packet and the beamforming frequency domain IQ data from a selected one of the second layer beamforming frequency domain IQ data packets prior to frequency-time domain conversion. The weighted sum can be calculated according to beamforming weights received from a beamformer.

[0067] In a further embodiment, combining the beamforming frequency domain IQ data from the first layer beamforming frequency domain IQ data packet with the beamforming frequency domain IQ data from one of the selected second layer beamforming frequency domain IQ data packets is performed in the time domain by converting the beamforming frequency domain IQ data from the first layer beamforming frequency domain IQ data packet into a first layer beamforming time domain signal, converting the beamforming frequency domain IQ data from one of the selected second layer beamforming frequency domain IQ data packets into a second layer beamforming time domain signal, and adding the first layer beamforming time domain signal and the second layer beamforming time domain signal.

[0068] The first layer beamforming frequency domain IQ data packet and one of the selected second layer beamforming frequency domain IQ data packets may be associated with different component carriers. The method can include queuing data packets according to the intended transceiver IC position such that the second layer beamforming frequency domain IQ data packet is received for processing by the last transceiver IC of the transceiver IC subarray before being received for processing by the first transceiver IC of the transceiver IC subarray.

[0069] In some alternative embodiments, as described above, the method of multi-layer (transmission) beamforming includes receiving a first layer beamforming time domain IQ data packet and a plurality of second layer beamforming time domain IQ data packets in a transceiver integrated circuit (IC) subarray, and further, for common processing, transferring the first layer beamforming time domain IQ data packet from a first transceiver IC of the transceiver IC subarray to an additional transceiver IC of the transceiver IC subarray, and transferring only a subset of the plurality of second layer beamforming time domain IQ data packets from the first transceiver IC to the additional transceiver IC. In some embodiments, the subset of the second layer beamforming time domain IQ data packets is identified according to a packet header. Some alternative methods can directly combine the beamforming time domain IQ data from the first layer beamforming time domain IQ data packet with the beamforming time domain IQ data from a selected one of the second layer beamforming time domain IQ data packets in the time domain, for example, by adding the beamforming time domain IQ data from the first layer beamforming time domain IQ data packet to the beamforming time domain IQ data from a selected one of the second layer beamforming time domain IQ data packets.

[0070] Some exemplary embodiments of the apparatus include a beamformer processor configured to generate a first layer beamforming frequency domain IQ data packet and a plurality of second layer beamforming frequency domain IQ data packets, a transceiver integrated circuit (IC) subarray connected to the beamformer processor and having a plurality of interconnected transceiver ICs interconnected via a plurality of serial data connections, wherein each transceiver IC of the transceiver IC subarray is configured to form a multi-layer beamforming frequency domain IQ data set and generate a discrete time domain signal from the multi-layer beamforming frequency domain IQ data set, a radio frequency modulator configured to generate a modulated radio frequency (RF) signal from the discrete time domain signal, and an antenna element subarray connected to the transceiver IC subarray and configured to transmit a multi-layer beamforming signal by transmitting respective modulated RF signals from the transceiver ICs of the transceiver IC subarray. The transceiver IC subarray can include a first transceiver IC having a packet header processor configured to transfer a first layer beamforming frequency domain IQ data packet from the first transceiver IC to additional transceiver ICs of the transceiver IC subarray for common processing and configured to transfer only a subset of the second layer beamforming frequency domain IQ data packets from the first transceiver IC to the additional transceiver ICs. The packet header processor may be configured to identify a subset of the second layer beamforming frequency domain IQ data packets according to a packet header.

[0071] The DSP may be configured to combine the beamforming frequency-domain IQ data from the first-layer beamforming frequency-domain IQ data packet with the beamforming frequency-domain IQ data from one selected from among the second-layer beamforming frequency-domain IQ data packets by concatenating the beamforming frequency-domain IQ data from the first-layer beamforming frequency-domain IQ data packet with the beamforming frequency-domain IQ data from one selected from among the second-layer beamforming frequency-domain IQ data packets before the frequency-time domain conversion. The DSP may be configured to combine the beamforming frequency-domain IQ data from the first-layer beamforming frequency-domain IQ data packet with the beamforming frequency-domain IQ data from one selected from among the second-layer beamforming frequency-domain IQ data packets by forming a weighted sum of the beamforming frequency-domain IQ data from the first-layer beamforming frequency-domain IQ data packet and the beamforming frequency-domain IQ data from one selected from among the second-layer beamforming frequency-domain IQ data packets before the frequency-time domain conversion. The DSP may be configured to calculate the weighted sum according to the beamforming weights received from the beamformer processor.

[0072] In some embodiments, the DSP is configured to convert the beamforming frequency-domain IQ data from the first-layer beamforming frequency-domain IQ data packet into a first-layer beamforming time-domain signal, convert the beamforming frequency-domain IQ data from one selected from among the second-layer beamforming frequency-domain IQ data packets into a second-layer beamforming time-domain signal, and add the first-layer beamforming time-domain signal and the second-layer beamforming time-domain signal.

[0073] The apparatus may include a packet header processor configured to identify a separate component carrier associated with one of a first layer beamforming frequency domain IQ data packet and a selected one of second layer beamforming frequency domain IQ data packets. The beamformer processor may be configured to transmit a second layer beamforming frequency domain IQ data packet for processing by a last transceiver IC in a transceiver IC subarray before transmitting the second layer beamforming frequency domain IQ data packet for processing by a first transceiver IC in the transceiver IC subarray. The apparatus may also include a plurality of transceiver IC subarrays configured to transmit multi-layer beamforming signals, and a corresponding plurality of adjacent antenna element subarrays.

[0074] Some alternative embodiments of the apparatus include a beamformer processor configured to generate a first layer beamforming time domain IQ data packet and a plurality of second layer beamforming time domain IQ data packets, a transceiver integrated circuit (IC) subarray connected to the beamformer processor and having a plurality of interconnected transceiver ICs interconnected via a plurality of serial data connections, and each transceiver IC of the transceiver IC subarray comprising digital front-end signal processing circuitry configured to form a multi-layer beamforming time domain IQ data set and generate a discrete time domain signal from a separate first layer beamforming time domain IQ data set and a second layer beamforming time domain IQ data set. The first layer time domain IQ data and the second layer time domain IQ data may have different sampling rates, and the digital front-end circuit may interpolate each of the first layer time domain IQ data and the second layer time domain IQ data to a common sample rate before additively combining the discrete time signals. Some embodiments include a radio frequency modulator configured to generate a modulated radio frequency (RF) signal from the discrete time domain signal, and an antenna element subarray connected to the transceiver IC subarray configured to transmit a multi-layer beamforming signal by transmitting respective modulated RF signals from the transceiver ICs of the transceiver IC subarray. The transceiver IC subarray may comprise a first transceiver IC having a packet header processor configured to transfer a first layer beamforming time domain IQ data packet from the first transceiver IC to additional transceiver ICs of the transceiver IC subarray for common processing and configured to transfer only a subset of the second layer beamforming time domain IQ data packets from the first transceiver IC to the additional transceiver ICs. The packet header processor may be configured to identify a subset of the second layer beamforming time domain IQ data packets according to the packet header.

[0075] Some embodiments may utilize a full-dimensional beamforming data stream within a serially connected transceiver array. In these embodiments, each signal port has a unique signal for complete control over the beamforming phase. Thus, a unique packet addressed to each transceiver within a subarray (via a combination of one or more field IDs or a set of ID combinations) is sent to each transceiver IC subarray. The packets are time-ordered to accommodate latency such that the IQ packet addressed to the transceiver at the end of the serially linked chain of transceiver ICs is sent first and thus received at the end of the array. Thus, the packets can be ordered in a round-robin fashion where the first packet is sent to each transceiver IC so that processing can begin at each IC, and then additional packets are sent to each transceiver IC.

[0076] Each transceiver has a serial link and a packet header analyzer circuit for performing header inspection, and each stream to a subarray includes a separate data packet with unique digital beamforming data addressed to an individual transceiver within the set of serially connected transceivers. The packet header analyzer within each transceiver Serdes can make per-packet transfer decisions. In one configuration, the packet bandwidth is equally allocated between two signal paths of each transceiver IC, such as packets for two signal ports (H and V).

[0077] When receiving signals within serially connected transceiver ICs in a subarray, the serial data rate between ICs is limited, and thus subarray beamforming may include combining received IQ data before sending it to and back from the beamformer. In some embodiments, combining weights are provided to the transceivers within a given subarray, and thus the transceivers adjust the phase as part of the received combination. Electronic tilt is one such situation.

[0078] Figure 4 is an alternative embodiment of a radio unit architecture having a hierarchical data distribution topology to each group of transceiver ICs serially connected from a DL / UL beamformer 400 (e.g., one such transceiver IC subarray is a set of transceiver ICs connected via serial links 418 and 420). In this embodiment, the beamformer 400 has a high-speed serial data connection (e.g., 402) to an intermediate Serdes MUX device 404 (as well as connections to 422, 424, 426), each of which then provides a separate serial data connection (e.g., a set of links 406). The separate serial connections from each Serdes MUX may utilize a lower data rate for connection to each respective subset of transceiver IC subarrays 421a, 421b, 421c, 421d. In the embodiment of Figure 4, the subset of transceiver IC subarray 421a includes eight transceiver IC subarrays, each subarray having three transceiver ICs connected to corresponding antenna elements. The remaining sets of transceiver IC subarrays 421b, 421c, 421d are shown in a simplified form for clarity (including connectivity to a simplified set of antenna element subarrays).

[0079] The transceiver IC subarrays of Figure 4 are also configured in a time division duplex (TDD) configuration having SPDT (single-pole double-throw) switches 412. Received signals may be filtered via filter 410 and amplified by a low noise amplifier (LNA) 408. Also shown are signal couplers, such as 414, 416, that provide a signal copy of the transmitted RF signal (typically at much lower power) to a calibration port 430 for monitoring or observing by transceiver 428.

[0080] FIG. 5 shows an embodiment of a synchronization and clock distribution circuit 500 for use with transceiver ICs distributed across an active antenna array assembly. More specifically, some embodiments include a method that includes receiving a clock signal and at least one synchronization pulse signal at each transceiver IC of a plurality of transceiver IC sub-arrays, each transceiver IC sub-array including a respective set of serially-connected transceiver ICs. The method further includes, at each transceiver IC, (i) synchronizing the transceiver IC with other transceiver ICs of the respective set of serially-connected transceiver ICs by resetting a delta-sigma modulator (DSM) circuit to a predetermined state in accordance with the received at least one synchronization pulse signal, (ii) generating a carrier frequency signal using a phase-locked loop (PLL) circuit that includes the DSM circuit, and (iii) using the generated carrier frequency signal to process frequency domain in-phase and quadrature (IQ) data.

[0081] Furthermore, some embodiments include a plurality of transceiver IC sub-arrays, each transceiver IC sub-array including a respective set of serially-connected transceiver ICs, a beamformer processor coupled to the plurality of transceiver IC sub-arrays, the beamformer processor being configured to generate at least one synchronization pulse signal and provide the at least one synchronization pulse signal to each transceiver IC, a plurality of clock buffer circuits coupled to the beamformer processor via a clock distribution circuit, the plurality of clock buffer circuits being configured to output a plurality of clock signals and provide a respective clock signal to each transceiver IC, and each transceiver IC being configured to (i) receive the respective clock signal and the at least one synchronization pulse signal, (ii) synchronize the transceiver IC with other transceiver ICs of the respective set of serially-connected transceiver ICs by resetting a delta-sigma modulator (DSM) circuit to a predetermined state in accordance with the received at least one synchronization pulse signal, (iii) generate a carrier frequency signal using a phase-locked loop (PLL) circuit including the delta-sigma modulator (DSM) circuit, and (iv) use the generated carrier frequency signal to process frequency-domain IQ data.

[0082] Referring back to FIG. 5, within the beamformer processor circuit 502, the data interface circuit 506 may be used to generate a clock signal from the clock and data recovery (CDR) circuit 508, which is then provided to a dual PLL clock circuit 512 that provides clock signals 522, 524 for use by the beamformer processor 502, and the beamformer processor may then generate additional clock signals on line 526. The clock signal distribution to the transceiver IC (e.g., one such transceiver IC 540 is depicted in FIG. 5) via clock line 538 is provided by a clock buffer 536 that receives an input from a clock distribution circuit 534 driven by PLL2 532, PLL1, 530, based on a selection from MUX528, in conjunction with the system reference clock. Thus, in some embodiments, the clock distribution circuit 534 is driven by the clock signal (on line 526) from the beamformer processor 502 and the system reference clock.

[0083] In some embodiments, the distributed clock signal is a high-frequency signal within the frequency range of 50 MHz to 150 MHz. Further, in some embodiments, the clock buffer clock circuit 536 is configured to adjust the clock signal timing at the output of each clock buffer circuit such that each clock signal is received by each transceiver IC substantially simultaneously. For example, in an exemplary embodiment, the clock buffer circuit 536 is programmable and configurable to adjust the clock signal timing at each output such that the clock signal (specifically, the rising edge transition and / or falling edge transition of the clock signal) arrives at each transceiver IC with a low relative skew to account for the signal transmission latency associated with the clock signal path. In this regard, low skew means substantially simultaneous arrival with an arrival time distribution in the range of less than 1 or 2 nanoseconds of each other. In some embodiments, low skew refers to less than 333 picoseconds (1 / 3 nanosecond). In this regard, the clock buffer 536 can be adjusted according to a calibration procedure.

[0084] In some embodiments, in addition to receiving a substantially synchronized clock signal, transceiver ICs (e.g., transceiver IC 540) are also synchronized with respect to each other at the macro timing level by at least one additional synchronization pulse signal for one or more purposes. In particular, the transceiver ICs may be interconnected within a transceiver IC subarray via an asynchronous serial data bus and, as described herein, are directly or indirectly interconnected with a beamformer processor 502 and have one or more subsystems that can benefit from further synchronization. In some embodiments, as shown in FIG. 5, such a synchronization pulse signal (shown as a "SYNC" pulse signal) is generated by the beamformer processor 502 and provided to each transceiver IC for further synchronization.

[0085] In some embodiments, as generally shown in FIG. 5, the synchronization pulse signal ("SYNC" pulse) generated by the beamformer processor 502 may be processed through an additional buffer tree network 527 such that each synchronization pulse signal is received by each transceiver IC substantially simultaneously, similar to the clock signal. More specifically, in some embodiments, some of the transceiver ICs grouped into a transceiver IC subarray may be distributed at different positions across the antenna panel. Similar to the clock distribution described above, each synchronization pulse signal may have different signal transmission latencies associated with different physical signal paths to individual transceiver ICs that may be distributed across the antenna panel. For example, depending on the physical location of a given transceiver IC on the panel, a longer signal path for the SYNC pulse may experience greater signal degradation than a shorter signal path.

[0086] In some embodiments, the buffer tree network 527 may be configured to distribute the synchronization pulse signal in a tree-like manner by synchronously branching the SYNC pulse to different panel regions. For example, in such a network, the primary buffer circuit may drive a given number of outputs that are distributed across different regions of the panel and drive a corresponding number of at least secondary buffer circuits that provide the synchronization pulse signal to transceiver ICs located in their respective regions. In some embodiments, the timing of the output signal from the primary buffer circuit may be appropriately adjusted (e.g., delayed) such that, for example, the distributed secondary buffers receive the synchronization pulse signal substantially simultaneously. Next, each of the secondary buffer circuits can provide several separate outputs to drive the corresponding number of transceiver ICs within their respective regions of the panel, and the output signal timing (e.g., signal delay) can be adjusted such that each synchronization pulse signal is received by each transceiver IC at substantially the same time / simultaneously.

[0087] In an exemplary embodiment, the buffer tree network 527 may be implemented by a signal distribution chip / IC that is programmable through an appropriate calibration procedure for adjusting the timing of the synchronization pulse signal such that the SYNC pulse actually arrives at each transceiver IC substantially simultaneously. In this regard, such a distribution chip can be configured, for example, to selectively delay the buffered signal output to account for the signal transmission latency associated with different signal paths of the SYNC pulse.

[0088] In one aspect, each of the transceiver ICs physically distributed across the antenna array assembly independently processes a low-skew distribution (e.g., high-frequency) clock signal and, in response, is configured to generate a carrier frequency signal for processing transmitted and received modulated RF signals. Thus, the voltage-controlled oscillator (VCO) of each transceiver IC used to generate the carrier phase for modulating the transmitted signal and mixing / down-converting the received RF signal is closely aligned across the transceiver IC sub-arrays distributed across the antenna array assembly.

[0089] In some embodiments, the transceiver IC VCO used herein employs a VCO tuning loop comprising a phase-locked loop (PLL) circuit including a delta-sigma modulator (DSM) 544, a multi-modulus divider (MMD) 546, a phase / frequency detector (PFD) 548, a loop filter 550, a VCO 552, and a divider 554. The fractional divider within the VCO tuning loop functions to adjust the frequency division factor (i.e., the division ratio) used by the MMD 546. The MMD 546 utilizes a sequence of divisor values obtained from the DSM 544.

[0090] In this regard, as described above, some embodiments described herein include methods that include synchronizing the transceiver ICs with other transceiver ICs of each set of serially connected transceiver ICs (within each transceiver sub-array), in particular, by resetting the DSM circuit to a predetermined state according to at least one received synchronization pulse signal, and generating a carrier frequency signal using a PLL circuit including the DSM circuit.

[0091] Furthermore, in one embodiment, to generate a carrier frequency signal using a PLL circuit (including a DSM circuit), each transceiver IC is configured to: (i) use the DSM circuit to set the division ratio of the MMD; and (ii) provide the divided frequency signal from the MMD to the PFD to compare with a clock signal and further adjust the division ratio of the MMD. In a further embodiment, the DSM circuit includes a plurality of accumulators, and each transceiver IC is further configured to set the plurality of accumulators of the DSM circuit according to at least one received synchronization pulse signal to reset the DSM circuit to a predetermined state according to the at least one received synchronization pulse signal.

[0092] Generally speaking, various embodiments described herein utilize a DSM circuit (such as DSM544) to increase the frequency resolution of the carrier frequency signal generated by each transceiver IC for processing transmitted and received modulated RF signals. In this regard, in some embodiments, the DSM circuit is configured to use a time-varying sequence representing a fractional input part in combination with a fixed integer input part to obtain a relatively high-resolution carrier frequency. In one example, by using a DSM circuit in a PLL circuit, the VCO frequency resolution can be made as fine as about 114 Hz. The operation of the DSM circuit will be described in more detail below.

[0093] As shown in FIG. 5, DSM544 can include a fractional input (FRAC IP) block 572, a DSM accumulator (DSM ACC) 574, a fractional output (FRAC OP) block 576, and an addition circuit 578. During operation, FRAC IP receives an input 570 that includes a digital fractional input value and generates a corresponding fractional input portion that is input to DSM ACC574. As further shown, DSM accumulator 574 and FRAC OP576 form a loop. Generally, in this loop, the fractional input portion passed to the DSM accumulator 574 at the current time is also referenced back from FRAC OP576 to the accumulator. Here, the current fractional output is subtracted from the current fractional input portion value stored in accumulator 574. Although not explicitly shown in FIG. 5, in an exemplary embodiment, DSM ACC574 includes a plurality of accumulators, and each accumulator can (i) receive a version stored prior to its cumulative output, (ii) subtract the current fractional output using feedback from FRAC OP576, and (iii) pass the result to a subsequent accumulator.

[0094] As a result of the operation described above, all fractional outputs generated by FRAC OP576 are provided to addition circuit 578. Next, addition circuit 578 sums (adds) the fractional output portion with the actual integer input portion 580 to generate a desired divisor value that is provided as an input to MMD546. In some embodiments, the output of DSM544 is in the form of a divisor control word (e.g., a set of data bits) that sets which divisor to use in MMD546. Due to the time-varying characteristics of the fractional input portion, the control word also changes over time. However, over a given operating interval, on average, the desired ratio can be achieved.

[0095] As described above, in one embodiment, the transceiver IC 540 is synchronized with other transceiver ICs in its respective transceiver IC sub-array by resetting a DSM circuit (such as DSM 544) to a predetermined state in accordance with at least one received synchronization pulse signal. In this regard, as further shown in the example of FIG. 5, the transceiver 540 is configured to receive such a synchronization pulse signal (here, the "SYNC" pulse signal from the beamformer processor 502), and the synchronization pulse signal is provided to the DSM ACC 574 to set a plurality of accumulators of the DSM ACC 574 in accordance with the synchronization pulse signal.

[0096] In some embodiments, the reset provided by the synchronization pulse signal is a one-time event that is executed, for example, during startup. Thereafter, transceiver IC synchronization can be automatically obtained due to the globally shared high-speed clock distributed to each transceiver IC (as described above).

[0097] During normal operation, the MMD 546 utilizes the sequence of division ratios obtained from the DSM 544. In this way, the sequence of divisors used to divide the VCO frequency from the VCO 552 (or the already divided signal supplied by a divider such as the divider 554) is the same across all of the transceiver ICs. Thus, in some embodiments, the MMD 546 is configured to utilize the sequence of division ratios provided by the DSM 544, and the sequence of divisors is synchronized across all of the transceiver ICs in accordance with the synchronization pulse signal.

[0098] As further shown in FIG. 5, the divided frequency signal from MMD546 is provided to PFD548 for comparison against the high frequency distribution clock signal from clock buffer 536. PFD548 generates a phase error signal, which is then filtered by loop filter 550 having a transfer function H(z). The filtered phase error signal is then supplied to VCO552 to correct the phase error. Synchronization of VCO phase error measurement circuits such as the DSM544 divisor sequence across the transceiver IC provides reduction of the jitter of the carrier frequency used for transmission and reception signal processing between transceiver ICs.

[0099] Further, as shown in FIG. 5, the output carrier frequency signal from divider 554 may be provided to digital delay line (DDL) 556. In some embodiments, DDL556 is configured to generate a carrier frequency signal having multiple phases at output 558. As an example, in one embodiment, the multiple phases can include at least four phases of 0 degrees, 45 degrees, 90 degrees, and 135 degrees, and the carrier frequency ranges from 3.6 GHz to 4 GHz. As described in more detail below, the generated carrier phases (and, e.g., their inversions) can be used by a polyphase digital power amplifier for RF modulation. More specifically, in some embodiments, a discrete time domain signal representing DL (downlink) frequency domain IQ data may be modulated onto the generated carrier frequency signal using a polyphase DPA, and the polyphase DPA uses a selected phase of the generated carrier frequency signal for RF modulation. The phase can be selected according to the discrete time domain signal.

[0100] In another aspect, the transmit and receive signal processing circuits within the transceiver IC can use a numerically controlled oscillator (NCO) such as NCO542 shown in FIG. 5. The NCO can be used to provide a frequency shift (conversion) via time domain complex multiplication as described herein with respect to FIGS. 13A, 13B.

[0101] The NCO can also utilize components that can benefit from synchronization by a SYNC pulse signal. In some embodiments, the NCO utilizes a phase accumulator that is incremented by a frequency control word (FCW) at each clock interval. If different NCOs within different transceiver ICs have different phase accumulator values, this can introduce a phase offset in transmit and receive signal processing. Synchronization of the NCO phase accumulator circuits across the transceiver IC provides a reduction in the phase offset in transmit and receive signal processing between the transceiver ICs.

[0102] Referring again to the example of FIG. 5, NCO 542 includes an FCW register 562, a phase accumulator (PACC) 564, and a phase amplitude converter (PAC) 566. As shown in FIG. 5, the FCW register 562 receives an FCW input 560 (from, e.g., a DSP, etc.) and, in response, can generate an FCW to be loaded into the PACC 564 at each clock interval. Generally, the FCW is a series of data bits that represents a phase increment value. In some embodiments, the FCW register 562 is configured to use the FCW to generate a corresponding phase increment (e.g., via a look-up table, etc.). In some embodiments, the PACC 564 is configured to add the corresponding phase increment to its internal memory register. In this way, the phase value accumulated by the PACC 564 through the stepped phase increments starts at 0 degrees, ramps up to 360 degrees, wraps around back to 0 degrees again, and is the binary representation of the angle at which all starts again in the next cycle (clock interval). Next, the output phase value of the PACC 564 is passed to the PAC 566 to be converted into a complex sine wave output by the NCO 542. The PAC 566 is configured to convert the accumulated phase value from the PACC 564 into a dual output of a sine function and a cosine function of the angle corresponding to that phase value, representing the real and imaginary components that form the complex sine wave at the NCO output 568.

[0103] Furthermore, in some embodiments, NCO 542 receives a synchronization pulse signal and resets NCO 542 according to the synchronization pulse signal. This can synchronize the NCO phase accumulator circuit across the transceiver IC as described above. More specifically, in some embodiments, the phase accumulator of the NCO is reset according to the received synchronization pulse signal. As shown in the example of FIG. 5, the SYNC pulse signal is provided to PACC 564 of NCO 542 to reset PACC 564. Due to the advantage that such phase accumulation remains in each transceiver IC, all of the transceiver ICs distributed across the active antenna array assembly can start phase value accumulation at 0 degrees.

[0104] It should be noted that in some embodiments, as described in connection with the operation of the DSM circuit, the synchronization pulse signal reset is provided as a one-time event that occurs, for example, at a certain point during startup. Thereafter, transceiver IC synchronization can be automatically obtained due to the globally shared high-speed clock distributed to each transceiver IC (as described above).

[0105] Furthermore, as will be described in more detail herein with reference to FIGS. 13A and 13B, the synchronous NCO 542 can be used to provide a frequency shift (conversion) via time-domain complex multiplication. For example, in the transmit-side signal processing (FIG. 13A) within transceiver 540, NCO 542 can be configured to multiply a time-domain signal by a complex sine function to perform a frequency shift of a baseband signal to a desired frequency range, such as a separate frequency range that does not overlap with other component carriers. On the receive signal processing side (FIG. 13B), the signal received by transceiver IC 540 can be shifted to a desired baseband signal by complex multiplication via NCO 542.

[0106] Furthermore, in some embodiments, the synchronous NCO 542 can be used to operate on frequency domain data to provide an incremental phase rotation to sub-carrier specific frequency domain IQ data for electronic beam tilt, as described herein. Of course, multiple instances of the NCO 542 may be utilized for various signal processing functions as described herein.

[0107] Clock distribution is configured according to signal lines routed across panel 102, as shown in various embodiments shown in FIG. 6, to provide clock signals to the transceiver IC sub-array to reduce clock skew. As described above, in some embodiments, multiple clock buffer circuits (e.g., 536) can be configured to adjust the clock signal timing at the output of each clock buffer circuit such that each clock signal is received substantially simultaneously by each transceiver IC. In some further embodiments, multiple transceiver IC sub-arrays, beamformer processors (e.g., 502), and multiple clock buffer circuits are all physically located in the same location within the antenna array assembly, and each clock buffer circuit is physically dispersed across the antenna array assembly at a physical location corresponding to the physical location of one or more transceiver IC sub-arrays.

[0108] For illustration purposes, in one embodiment, the clock signal distribution has a tree-like structure that symmetrically provides clock signals to each transceiver IC subarray, such as subarray 600 (which can be one or more transceiver IC subarrays). Specifically, in the illustrated embodiment, a given branched clock signal from clock buffer 610 is conveyed on clock signal conductor 606, which is split to provide clocking signals on lines 602, 608, which drive a further set of clock buffers (e.g., buffer 604 driven by line 602), and then provided to the transceiver IC subarray, e.g., 600. In one embodiment, four clock buffers at the level of 610 can be provided by clock distribution circuit 534. Further, each clock buffer 536 is physically distributed across the antenna array assembly and serves the transceiver IC subarrays that are likewise physically distributed across the antenna array assembly. In the illustrated embodiment, each clock buffer can provide eight separate clock outputs to eight separate transceiver ICs. In the embodiment of FIG. 6, one clock buffer circuit is shown as clock buffers 603, 604 and, as shown, supplies clock signals to four transceiver ICs within block 600 and four transceiver ICs below it.

[0109] FIG. 7 is a system 700 block diagram of a distributed unit (DU) 702 having a baseband transmission unit 706, a precoding unit 710 (receiving a scheduler input 708), a channel estimation unit 714, and a baseband reception unit 716. The DU 702 includes an ORAN interface 712 for connecting to a radio unit (RU) 704 via a fronthaul data interface that carries control information (C plane 718), management information (M plane 720), and user data (U plane 722). Also shown is a hierarchical beamformer architecture 722 within the radio unit 704. The hierarchical beamformer 722 includes a main (primary) beamformer processor 724 (or abbreviated as "main beamformer 724") and secondary beamformer processors BF#1 (728), BF#2 (734), BF#3 (736), and BF#4 (738) (or abbreviated as "layer 2 beamformers") connected by a serial data link (e.g., link 726 from the main beamformer 724 to BF#1). In one embodiment of the hierarchical beamformer architecture 722, the main beamformer 724 calculates a complete beamforming matrix (to be described in more detail with reference to FIGS. 8 - 10) and distributes portions of the beamforming matrix to the layer 2 beamformers (e.g., BF#1 - 4).

[0110] Furthermore, main beamformer 724 also communicates the associated layer of user data to each second layer beamformer. As described above, the beamforming processor within the wireless unit can be configured to transmit and receive IQ data packets either in the time domain or the frequency domain. In some embodiments, each second layer beamformer receives the associated layer of user data from main beamformer 724 in the form of frequency domain IQ data and can then compute an aggregated frequency domain IQ data packet specific to the signal ports for the transceiver IC (or transceiver IC subarray) that it serves. In an alternative embodiment, each second layer beamformer may similarly receive the associated layer of user data from main beamformer 724 in the form of frequency domain IQ data via its respective serial data link 726, but instead first converts that frequency domain IQ data to time domain IQ data and then computes an aggregated IQ data packet (here containing time domain data instead) specific to the signal ports for the transceiver IC (or transceiver IC subarray) that it serves. In this regard, each of second layer beamformers 728, 834, 736, and 738 is comprised of a suitable iFFT process (e.g., a digital signal processor (DSP) comprised of suitable programming instructions to execute an algorithm for IFFT operations) for converting frequency domain IQ data to time domain IQ data.

[0111] In the embodiment shown in FIG. 7, RU 704 is shown as having a beamformer connection to transceiver IC 730, and the transceiver IC element may be an individual transceiver IC having two or four signal ports for driving antenna elements 732, or may be a transceiver IC subarray of serially connected transceiver ICs according to the various embodiments described herein. The Serdes mux device of FIG. 4 (e.g., 404) can also implement portion BF processor 728 of the hierarchical beamformer apparatus.

[0112] As described above, some embodiments, such as those shown in FIG. 7, include a hierarchical beamformer apparatus having a main (primary) beamforming processor 724 and a set of secondary beamformer processors 728, 734, 736, 738. In these embodiments, the primary beam processor allocates beamforming combining weights (optionally in combination with pre-coder combining weights) to form a complete beamforming matrix (as described in more detail with respect to FIG. 8), and then distributes portions of the beamforming matrix to the respective secondary beamformer processors. More specifically, in some embodiments, the transceiver IC subarrays may be partitioned according to their physical locations on the panel (e.g., 100), and each set of transceiver IC subarrays within a given partition is serviced and interconnected by a corresponding secondary beamformer processor, which may be distributed across the panel adjacent to or within the partition. In some embodiments, each distributed secondary beamformer processor also receives a frequency domain sub-carrier IQ user data layer, applies its respective distributed beamforming weights to the IQ user data layer, and calculates fully beamformed IQ data points for distribution to the respective partitioned subsets of the transceiver IC subarrays (where the fully beamformed IQ data points can be in either a frequency domain format or a time domain format, as described above).

[0113] Embodiments of the secondary beamformer processor can include a digital signal processor circuit that executes software instructions to perform matrix multiplication operations, or can take the form of data registers interconnected with a hardware multiplier circuit that performs matrix operations. The hardware may include a hardware processor, a field programmable gate array (FPGA), application specific digital logic, or combinations thereof. Further, in some embodiments, each secondary beamformer processor includes a digital signal processor (DSP) configured to execute software instructions to perform an iFFT process to convert frequency domain IQ data to time domain IQ data (e.g., if the IQ data received from the primary beamformer processor is in the frequency domain), and to perform an FFT process to convert the time domain IQ data to frequency domain IQ data (e.g., if the IQ data transmitted to the primary beamformer processor is in the time domain).

[0114] FIG. 8 is a graphical representation of a downlink transmission beamforming operation. User data is represented by layers of data along dimension 818, and subcarrier specific IQ data for each such layer is shown along dimension 816. In some embodiments, the user data layer along dimension 818 is a frequency domain IQ data layer (e.g., a data layer distributed on each respective link 726 to an individual secondary beamformer as described in connection with FIG. 7). Each data layer such as layers 820, 822, etc. can actually be aggregated user data for one or more users, and different users are allocated / assigned different subsets of subcarriers represented along dimension 816. Further, a given user can be allocated one or more data layers (along dimension 818), such as in the case of spatial multiplexing.

[0115] A beamformer (e.g., 202, 300, 400, 724 (primary beamformer), etc.) calculates beamforming weights for a set of carriers along dimension 802, for a user data layer represented by IQ data along dimension 800, and for signal ports along dimension 804. As shown in FIG. 8, according to matrix multiplication, the beamforming weights shown in the top layer of the matrix (i.e., the horizontal slice of the matrix along dimensions 802×800) are applied to the data layer (816×818) to generate the top layer (the top of dimension 824) of beamforming IQ data with subcarriers along dimension 826. For simplicity, the rows or layers along beamforming dimension 804 alternate between H polarization and V polarization, so that, for example, elements 806, 808 each contain separate signal port weights such as "H" weights and "V" weights, which are used independently to combine data layers such as layers 820, 822, etc. Note that the H / V pairs of weights shown to be interleaved in the matrix columns in the vertical direction (dimension 804) can be associated in some operating modes or can be beams selected completely independently for the H and V components (i.e., signal ports). Columns of the beamforming matrix, such as column 807 or 809, can be applied to a given set of subcarriers in a corresponding given data layer according to the desired beamforming operation. Note that the beamforming matrix can also incorporate precoding matrix calculations to form a linear combination of data layers according to the desired precoding matrix. In this way, the beamformer matrix is used to operate on the user data layer to generate signal port-specific IQ data.

[0116] In the embodiment shown in FIG. 8, as described with respect to FIG. 3, each set of beamforming IQ data points is packetized and transmitted to the corresponding transceiver IC subarray. In some embodiments, the packetized IQ data can remain in the frequency domain. However, in other embodiments, the packetized IQ data may instead be converted to time domain IQ data. In some embodiments, the IQ data for the 64 signal ports along dimension 826 includes the IQ data for the 32H and 32V signal ports. Each of the four sections 828, 830, 832, and 834 of the IQ data specific to the 826 signal ports contains 16 beamforming IQ data packets, which can be combined via concatenation into eight separate dual signal port H / V packets that are similar in format to packet 302 of FIG. 3. Each of these eight H / V IQ packets contains either time domain or frequency domain IQ data and is transmitted via a single serial data link to a respective transceiver IC subarray, such as one of the eight transceiver IC subarrays along the rows of subarray 238a shown in FIG. 2. The IQ data for sections 830, 832, and 834 are each similarly packetized into eight unique IQ data packet streams and transmitted to the eight corresponding transceiver subarrays within transceiver subarray rows 238b, 238c, and 238d, respectively. In this embodiment, each dual signal port IQ data packet can be processed jointly by two serially connected transceiver ICs. Alternatively, each of the eight H / V packets obtained from section 828 may be transmitted to the respective transceiver IC subarrays in the first row of transceiver IC subarray 421a of FIG. 4, along with a similar distribution of dual signal port IQ packets to the rows of transceiver IC subarrays 421b, 421c, 421d. In the embodiment of FIG. 4, each beamforming IQ data packet is processed jointly by three serially connected transceiver ICs.

[0117] Regarding the multi-layer beamforming IQ data packet 850 representing beamforming IQ data for an embodiment of a transceiver IC subarray, the beamformer processor, for use by a transceiver IC that processes signals according to first-layer beamforming, a commonly processed IQ data packet 864 (either in time-domain or frequency-domain format) for one signal port (e.g., representing subcarrier IQ data for all subcarriers, or a subset of subcarriers of one component carrier of the signal port), and a second commonly processed IQ data packet 866 for a second signal port (the second commonly processed IQ data packet 866 is either in time-domain or frequency-domain format, e.g., depending on the format of the commonly processed IQ data packet 864 for the first port) are generated, and at the same time, may be configured to also generate higher-resolution beamforming of the second layer. The second-layer beamforming is performed according to the full-digital beamforming IQ packets 852, 854, 856 for processing by individual transceiver ICs and their respective horizontal signal ports (H1, H2, H3 shown in FIG. 8), and the full-digital beamforming IQ packets 858, 860, 862 for processing by individual transceiver ICs and their respective vertical signal ports (V1, V2, V3 shown in FIG. 8), as described above with respect to FIG. 3. Further, as described above, the second-layer beamforming IQ data packets can include subcarriers associated with the same component carrier as the commonly processed IQ data packets, or subcarriers associated with a second component carrier.

[0118] More specifically, the first beamforming IQ data packet may include IQ data 864 (labeled Hc, where "c" indicates IQ data for common processing) and 866 (Vc) for common processing by all transceiver ICs (e.g., three separate transceiver ICs each capable of 2T2R operation) within a given transceiver IC subarray. Three additional packets of transceiver-IC-specific IQ data, each including data 852 concatenated with data 858, data 854 concatenated with data 860, and data 856 concatenated with data 862, are also transmitted to the transceiver IC subarray. The first transceiver IC combines the commonly processed data 864 with data 852 and the commonly processed data 866 with data 858. Another transceiver IC combines the commonly processed data 864 with data 854 and the commonly processed data 866 with data 860, and a third transceiver IC combines the commonly processed data 864 with data 856 and the commonly processed data 866 with data 862.

[0119] FIG. 9 is a graph showing the conversion of user data layers 906, 916, 918 represented by a matrix [X]900 of dimension L (i.e., the number of layers) into beamforming downlink transmission IQ data packets for logical baseband ports 926 represented by a matrix [Z]904 of dimension M at m,k = uiu. In some embodiments, user data layers 906, 916, 918 remain in frequency domain format until the data associated therewith is beamformed. After the beamforming operation is completed, in some embodiments, the beamforming downlink transmission IQ data may be packetized to form frequency domain beamforming downlink transmission IQ data. However, in other embodiments, after the beamforming operation is completed, the beamformed downlink transmission frequency domain IQ data is instead first converted to beamformed downlink transmission time domain IQ data, and then packetized before transmission to respective transceiver ICs (e.g., transceiver IC 730 as shown in FIG. 7) or transceiver IC sub-arrays (e.g., transceiver sub-array 914 as shown in FIG. 9). According to the simplified signal processing shown in FIG. 9, data layer [X]900 undergoes a precoding operation by matrix PM920 according to the precoding operation to obtain a logical antenna port signal 922 represented by matrix [Y]902, and then continues with a beamforming operation by digital beamforming matrix DB924 using various beamforming beam indices (e.g., "beam IDx") having weights such as "beam 1"910, applies beam weights, and distributes appropriately weighted precoded signals at node 908 (which is a precoded linear combination of data layers 906, 916, 918) across various logical baseband ports 926 represented by matrix [Z]904 (also shown as IQ data 828, 830, 832, 834). Each beamforming packet of matrix [Z], such as IQ data packet 912, is conveyed to its corresponding transceiver IC sub-array 914.

[0120] As described above, in some embodiments, the IQ data that has undergone pre-coding and beamforming operations is then packetized to generate frequency domain IQ data packets 912 that are frequency domain IQ data that are carried to the corresponding transceiver IC sub-array 914. However, in other embodiments, following the pre-coding and beamforming operations, the beamformed / pre-coded frequency domain IQ data may instead first be converted to the time domain and then packetized to generate time domain IQ data packets 912 that are carried to the corresponding transceiver IC sub-array 914.

[0121] FIG. 10 is a diagram of the conversion of a user data layer into a beamforming IQ data stream by operation 1000 of a generalized combined precoding and beamforming matrix 1012 obtained from the matrix multiplication of a precoding matrix PM920 and a beamforming matrix DB924. A user IQ data layer [X]1004 is provided by a processor 1002 that provides user IQ data processed according to standard coding, cyclic redundancy check (CRC), rate matching (RM), and resource element (RE) mapping. The data layer [X]1004 is processed according to a generalized space multiplexer / beamformer matrix PM in conversion 1000 to generate a logical baseband port IQ signal packet 1014 represented by a signal port IQ data matrix [Z]1006 for transmission via respective serial data links to a transceiver IC subarray such as subarray 1008. As used herein, the terms “beamforming” and “beamforming matrix” refer to the combined beamforming / precoding operation as described, whether implemented in a single matrix operation or in multiple separate matrix operations. As described in connection with FIG. 9, the IQ data packet (and thus the subsequent beamforming / precoding operation) carried from each respective logical baseband port 1014 to its corresponding transceiver IC subarray 1008 can be either a time domain IQ data packet (when converted to the time domain) or a frequency domain IQ data packet.

[0122] FIG. 11 is a diagram of receive uplink signal processing including receive beamforming and layer decoding. Each transceiver IC subarray 1108 provides received IQ data to the beamformer processor as logical baseband ports 1116 represented by matrix [Z] 1106. In some embodiments, the IQ data received by the beamformer processor can be either frequency-domain IQ data or time-domain IQ data. In embodiments where the received IQ data is in the time domain, the conversion to frequency-domain IQ data can be performed via an FFT operation in the beamformer processor (when received via logical baseband port 1116). The virtual antenna port signals 1112 can be formed according to matrix [Y] 1104. Finally, the individual data layers 1110 represented by matrix [X] 1102 can be restored.

[0123] FIG. 12A shows a block diagram of an example of a single transceiver IC device architecture according to some embodiments. The transceiver IC device architecture shown in FIG. 12A is also suitable for forming a group of serially connected transceivers. The transceiver IC is suitable for operation in both FDD mode and TDD mode. By way of example, the configuration shown in FIG. 12A is connected for operation in TDD mode. Further, the embodiment of FIG. 12A shows a scenario where transceiver IC 1200 receives and transmits frequency domain IQ data packets (e.g., to / from a beamformer processor such as BFP200, 300, 400, 722, etc., or directly to / from another transceiver IC). Transceiver IC 1200 includes a plurality of signal processing paths for both transmit signal processing and receive signal processing. For DL transmit signal processing, transceiver IC 1200 includes a serial data receiver RX#0 1202 for receiving frequency domain IQ data packets via serial data receiver 1202. Serial data receiver 1202 includes a data buffer for storing several deserialized data words and a data analysis circuit for performing packet header analysis to determine whether the received packet is intended to be processed by the current transceiver IC and / or whether it is intended to be processed by one or more other transceiver ICs within the transceiver IC subarray. If the packet is to be processed locally, the packet is transferred via 1206 to DSP memory 1210 accessible to integrated digital signal processor (DSP) 1215, e.g., via a memory storage device or direct memory access (DMA) operation. In an alternative embodiment, the header inspection may be performed by DSP 1215, which places the data in DSP memory 1210 designated for retransmission via Serdes transmitter TX#1 1262.

[0124] DSP1215 includes programming stored in non-volatile memory that causes the DSP1215 to execute an algorithm 1214 for converting frequency domain digital IQ data to time domain digital data when executed. The stored algorithm instructions include processor instructions for an iFFT operation 1214 and further include instructions for expanding data transformed by the addition of a cyclic prefix (CP).

[0125] In the subarray beamforming described herein, each IC within a given subarray processes the same frequency domain (or time domain) IQ packet (referred to herein as "co-processed" IQ data) for transmission and generates a frequency domain (or time domain) IQ packet during reception. The frequency domain IQ packets are aggregated at each transceiver IC as they cross a cascaded set of transceiver ICs on their way to the beamformer processor (e.g., the secondary beamformer processor and the primary beamformer processor as described above in connection with FIG. 7). Since the signals co-processed by the transceiver ICs are aggregated beamforming signals having components from multiple data layers and multiple individual beams, it is not possible to adjust the individual beams within a given subarray of the co-processed IQ data packets. However, at each element (i.e., each signal port) within the subarray, it is possible to apply a unique phase rotation to the aggregated beamforming signal, which has the effect of tilting the entire synthesized / aggregated beamforming signal. Thus, when beam tilt is desired, the transceiver is configured to incrementally adjust the phase of each co-processed IQ data packet according to the position of the radiating elements driven by the transceiver ICs within the IC subarray. Without the incremental adjustment of the phase at each subarray element, perhaps only one of the elements is aligned and the wavefronts from the remaining elements progress (or lag) incrementally according to their positions within the subarray for a given downward (upward) tilt, so that a true tilt is not obtained. In this way, beam tilt can be obtained through digital baseband signal processing without directly adjusting any signal components in the analog domain (including not adjusting the VCO phase).

[0126] More specifically, when the linear array of antenna elements is physically "tilted" (either a vertical array tilted up / down in height or a horizontal array tilted left / right in azimuth), the result can be regarded as an incremental time delay in signal transmission (or reception) across the antenna elements of the array, thereby changing the direction in which the propagating wavefronts are added to reinforce each other to form the main lobe (and combined to weaken each other to form nulls). Electronic tilt is a process of imposing an appropriate signal delay without actually physically repositioning the antenna. The relationship between the time delay and the corresponding phase change of the signal depends on the tilt angle as well as the frequency of the signal. That is, a given time delay between two signals corresponds to a linear phase shift in the frequency content of the signal, and a given time delay results in a lower phase change for lower frequencies within the signal and a linearly higher phase change at higher frequencies. Thus, in the case of a narrowband signal, a specific time delay is approximately converted into a specific phase shift between the delayed signals. However, in the case of a wideband signal such as an OFDM signal of 50 or 100 MHz or more, a given time delay affects the phases of the OFDM subcarriers differently. Nevertheless, in a phase array where each subcarrier is rotated by the same phase, this results in a non-linear phase characteristic generally referred to as beam squint. A certain amount of beam squint is acceptable in an OFDM signal with a bandwidth of about 100 MHz.

[0127] Accordingly, electronic beam tilt in a physically static array can be achieved by various methods performed by individual transceivers described herein, including (i) applying an incremental phase rotation to each subcarrier frequency domain IQ data point (e.g., via an NCO), (ii) applying a constant phase rotation to each subcarrier frequency domain IQ data point (e.g., via complex multiplication), (iii) applying a constant phase rotation to each sample of the baseband time domain signal (e.g., via complex multiplication), (iv) imposing a time delay on the discrete time domain signal of the transmitted baseband signal, or (v) a combination of the above methods. It should be noted that methods (ii) and (iii) result in a certain amount of beam squint distortion.

[0128] In this regard, beam tilt can be implemented by applying a linearly increasing phase rotation across sub-carriers by a complex multiplier 1212 implemented as a numerically controlled oscillator (NCO) as described with respect to NCO 542 in FIG. 5. The NCO 1212 is configured to provide a sequence of complex numbers having a linearly increasing phase for multiplication by a corresponding sequence of sub-carrier frequency domain IQ data points. For a desired beam tilt, an initial phase and an increment rate at which the phase increases from sub-carrier to sub-carrier are determined and the values are loaded into the NCO phase accumulator 564 and the FCW register 562, respectively. The phase increment value can be determined according to one or more various factors including (i) the desired beam tilt angle, (ii) the sub-carrier spacing, (iii) the carrier frequency, and (iv) the position of the particular radiating element being driven by the transceiver IC. Generally, to achieve a beam tilt of angle φ, the phase rotation θ at a given sub-carrier frequency 1 / λ at position n within the array is given by the following equation,

[0129]

Equation

[0130] where the element is at a distance d = λ c / 2 with respect to the carrier wavelength λ c and is arranged. In the receive beam tilt operation, the NCO can be implemented in the complex multiplier 1238 after the FFT processing.

[0131] Alternatively, the complex multiplier 1212 can be configured to impart a constant phase rotation to each frequency domain IQ data point prior to the transformation via the iFFT 1214 to implement an approximate time delay to achieve beam tilt. For a desired beam tilt, a frequency domain phase rotation represented by a single complex number is determined and the value is loaded into the complex multiplier 1212. The frequency domain phase value can be determined according to one or more various factors including (i) the desired beam tilt angle, (ii) the array position of the particular radiating element being driven by the transceiver IC, and (iii) the carrier frequency. In the receive beam tilt operation, a constant phase rotation can be implemented in the complex multiplier 1238 after the FFT process.

[0132] In some embodiments, beam tilt is implemented by applying a constant phase rotation to each sample of the baseband time domain signal (e.g., via complex multiplication). For a desired beam tilt, a time domain phase rotation represented by a single complex number is determined and the value is loaded into a complex multiplier (which can also implement a gain function). Such a complex multiplier can be, for example, the complex multiplier 1306 as shown in FIG. 13A, which shows the transmit time domain signal processing portion of the transceiver IC, as described in more detail below. The time domain phase value can be determined according to one or more various factors including (i) the desired beam tilt angle, and (ii) the position of the particular radiating element being driven by the transceiver IC. In the receive beam tilt operation, a constant phase rotation can be implemented in a complex multiplier (while also implementing a gain function) prior to the FFT process that can be performed in either the transceiver IC or the beamformer processor, as described above. Such a complex multiplier can be, for example, the complex multiplier 1386 as shown in FIG. 13B, which shows the receive time domain signal processing portion of the transceiver, as described in more detail below.

[0133] In some further embodiments, beam tilt is implemented by imposing a time delay on the discrete-time domain signal of the transmitted baseband signal (instead of phase rotation via complex multiplication as in the above-described embodiments). For a desired beam tilt, a time domain delay is determined and the value is loaded into delay buffer 1312, as shown in FIG. 13A. The time domain delay value can be determined according to one or more various factors including (i) the desired beam tilt angle, (ii) the time domain sample rate, and (iii) the position of the particular radiating element being driven by the transceiver IC. In the receive beam tilt operation, the time delay can be implemented with delay buffer 1378 shown in FIG. 13B.

[0134] In yet further embodiments, combinations of the above methods can be used. In a particular embodiment, the electronic beam tilt may be composed of a coarse adjustment and a fine adjustment, where the coarse beam tilt may be implemented by applying a linearly increasing phase rotation across subcarriers by complex multiplier 1212 implemented as an NCO using a limited resolution or a limited number of bits, and the fine resolution may be implemented by further adjustment in the time domain, such as a time delay or a time domain constant phase rotation.

[0135] In various embodiments of beam tilt phase adjustment, the phase rotation can be specified by a control message provided to the transceiver IC. A particular phase value may be provided, or a phase index value may be included in the control message, or may be included in the header of the IQ data packet itself. The phase index value can be used, for example, to retrieve a pre-computed phase value from a look-up table. In some embodiments, the transceiver IC can combine coefficients to calculate the particular rotation to be applied (e.g., a desired tilt angle can be provided and the transceiver IC can adjust the phase rotation according to its predetermined position within the array and / or transceiver IC sub-array). Such a phase rotation can be used to implement beam tilt phase rotation.

[0136] In some embodiments, beam tilt can be implemented using a combination of a linear phase rotation applied in the frequency domain followed by either a constant phase rotation in the time domain or a time delay in the time domain after an iFFT transform. In some embodiments, the frequency domain rotation can achieve a coarse tilt or an approximation of the desired beam tilt, while the time domain rotation can be a fine tilt. This can be particularly useful when a larger tilt angle is desired.

[0137] In further embodiments, the dynamic adjustment of the tilt angle may be implemented on a per-slot basis, significantly improving the available scan range and coverage from a panel array using subarray beamforming. In such embodiments, beam tilt information is shown, as well as which time slots, subcarriers, or component carriers can be specified via a control message.

[0138] In one embodiment, for common processing by the transceiver, electronic antenna beam tilt is implemented in a transceiver subarray by distributing beamforming IQ data packets to a plurality of serially connected transceiver ICs. The IQ data packets have individual IQ values for each of a plurality of subcarriers. In each transceiver IC, an electronic beam tilt phase rotation is applied. In some embodiments, applying the beam tilt phase rotation is done by changing the phase of each IQ modulated subcarrier based on a desired antenna tilt and array position. The phase change may be a constant phase rotation applied to all subcarriers, or a linear increasing phase rotation increasing from subcarrier to subcarrier. The phase adjustment may be specified according to one or more control messages. The control message may be specific to a given subarray, a transceiver IC within the subarray, or an individual transceiver IC. The phase adjustment may be specified in terms of time delay, frequency domain multiplication rotation, or time domain complex rotation, or equivalent data. A given transceiver IC can also calculate a final phase adjustment by combining phase adjustment data with array position data unique to the transceiver IC.

[0139] Referring again to FIG. 12A, the time domain IQ data is stored in the DSP memory 1216 that is accessible by the transmit time domain signal processing circuit 1217 (described further with respect to FIG. 13A). In the embodiment of FIG. 12, the circuit 1217 includes two parallel component carrier processing circuits 1218, 1228 and corresponding time domain signal processing circuits 1220, 1230, each providing a baseband time domain OFDM signal (each being a single or multi-component carrier signal) to a corresponding digital power amplifier (DPA) circuit 1222, 1232.

[0140] In one embodiment, DPA1220, 1232 perform simultaneous RF modulation and amplification, and this amplification may be the final power amplification of the RF signal. In some embodiments, the DPA provides pre-amplification of the RF signal applied to an external power amplifier that drives the radiating antenna element. The external power amplifiers are distributed adjacently for each element across the active antenna panel assembly. The DPA1220, 1232 are provided with a plurality of RF carrier phases resulting from a system phase lock loop (SYSPLL) and are further processed by a synchronous RF PLL1262 that drives an RF carrier generator VCO1260. The selected RF carrier phases are used to switch amplifier cells within the DPA. As described herein, the specific RF carrier phases, and the respective number of activated cells that determine their relative magnitudes, are selected according to the time domain IQ data points provided by circuits 1220, 1230.

[0141] Transceiver IC 1200A also includes a receive time domain signal processing circuit 1241 (further described with respect to FIG. 13B) for down-converting an analog RF signal via an IQ mixer driven by VCO 1260 and generating separate baseband I and Q analog signals for sampling by analog-to-digital converters (ADCs) in circuits 1244, 1252. The sampled signals are then processed by time domain filtering and downsampling circuits 1242, 1250. The processed time domain signals are then stored in DSP memory 1216 for further processing including removal of CP and conversion to subcarrier specific frequency domain IQ data by the FFT algorithm (“FFT” 1240 of FIG. 12). DSP 1215 includes programming stored in non-volatile memory that, when executed, causes DSP 1215 to execute an algorithm for converting time domain digital data to frequency domain digital IQ data. Next, an NCO (e.g., 1238) can be used to apply a linearly increasing phase rotation to each frequency domain IQ (i.e., subcarrier) value, which is also one embodiment of electronic beam tilt. Next, the received IQ frequency domain data is processed by MUX / combining circuit 1264 for transmission to the serial data bus via serial transmitter TX#0 1204.

[0142] FIG. 12B shows a block diagram of another example of a single transceiver IC device architecture according to some embodiments. Similar to the embodiment of FIG. 12A, the transceiver IC device architecture shown in FIG. 12B is also suitable for forming a group of serially connected transceivers. Similar to FIG. 12A, the transceiver IC 1200B is suitable for operation in both FDD mode and TDD mode. As an example, the configuration shown in FIG. 12B is connected for operation in TDD mode. Further, different from the embodiment of FIG. 12A, the alternative embodiment of FIG. 12B shows a scenario where the transceiver IC 1200B receives and transmits time domain IQ data packets to / from a beamformer processor (e.g., directly from / to BFP 200, 300, 400, 722, etc., or to / from another transceiver IC). Each transceiver IC 1200B includes a plurality of signal processing paths for both transmit signal processing and receive signal processing. However, in this embodiment, the transceiver IC 1200B is configured to process the IQ data completely in the time domain without additional processing elements involving frequency-time domain conversion of IQ data (transmit side) and frequency-time domain conversion of IQ data (receive side) as described in connection with the transceiver IC device architecture shown in FIG. 12A.

[0143] More specifically, for DL transmission signal processing, the transceiver IC 1200B includes a serial data receiver RX#0 1202 configured to receive time domain IQ data packets via a serial data receiver 1202. As in the transceiver IC device architecture of FIG. 12A, the serial data receiver 1202 includes a suitable data buffer for storing several deserialized data words, and a data analysis circuit that performs packet header analysis to determine whether the received time domain IQ data packet is intended for processing by the current transceiver IC and / or whether it is intended for processing by one or more other transceiver ICs within the transceiver IC subarray. When the packet is to be processed locally, the packet is transferred to the memory 1211 via the link 1206, such as via a memory storage device or a direct memory access (DMA) operation. In an alternative embodiment, the header inspection may be performed, for example, via a dedicated DSP element (not shown) coupled to the memory 1211, and the dedicated DSP element then places the data to be resent via the Serdes transmitter TX#1 1262 in the memory 1211.

[0144] In the embodiment of FIG. 12A, the frequency domain IQ data packet is stored in the DSP memory 1210 accessible by the DSP 1215 configured to execute an algorithm 1214 for converting the frequency domain digital IQ data into time domain digital IQ data. Such an algorithm includes processor instructions for the iFFT operation 1214 and processor instructions for extending the data converted by the addition of a cyclic prefix (CP). It should be recalled that although not explicitly shown, in some embodiments, the memory 1211 can be a DSP memory readable by a DSP processor (not shown) configured with appropriate programming instructions for performing the addition of the CP to the time domain digital IQ data. In an alternative embodiment, such CP addition can instead be performed, for example, by a dedicated circuit (not shown) configured to reread a portion of the time domain IQ data from the memory 1211, whereby such a reread portion serves as the CPE and can then be supplied to the transmit time domain signal processing circuit 1217 along with the rest of the time domain IQ data by the dedicated circuit.

[0145] It should be noted that the addition of the CP to the time domain IQ data typically increases the amount of data for subsequent time domain baseband signal processing. Therefore, ideally, the addition of the CP should be performed in the digital front-end circuit of the transceiver IC 1200B to reduce the amount of data that needs to be communicated via the serial data link between the beamformer processor and a given transceiver IC / transceiver subarray. However, in an alternative embodiment, it may be possible for the addition of the CP to be performed instead in the beamformer processor.

[0146] Referring again to FIG. 12B, in some embodiments, the time domain IQ data is stored in a memory 1211 that is (directly or indirectly) accessible by a transmit time domain signal processing circuit 1217 (further described with respect to FIG. 13A). As previously described in connection with FIG. 12A, circuit 1217 includes two parallel component carrier processing circuits 1218, 1228 and corresponding time domain signal processing circuits 1220, 1230, each providing a baseband time domain OFDM signal (each being a single or multi-component carrier signal) to corresponding digital power amplifier (DPA) circuits 1222, 1232. The operation of DPAs 1220 and 1232 is essentially the same as that described in connection with the embodiment of FIG. 12A and is omitted here for brevity.

[0147] Similar to transceiver IC 1200A, in some embodiments, transceiver IC 1200B also includes a receive time domain signal processing circuit 1241 (further described with respect to FIG. 13B) that downconverts an analog RF signal via an IQ mixer driven by VCO 1260 to generate separate baseband I and Q analog signals for sampling by analog-to-digital converters (ADCs) within circuits 1244, 1252. As in FIG. 12A, the sampled signals are then processed by time domain filtering and downsampling circuits 1242, 1250.

[0148] In this embodiment, the processed time-domain signal may then be stored in the memory 1211 for further processing. In some embodiments, the further processing may include CP removal. As described above, in some embodiments, the memory 1211 may be a DSP memory configured with appropriate programming instructions for further performing the removal of the received-side CP from the time-domain digital IQ data, by a DSP processor (not shown). In an alternative embodiment, such CP removal may instead be performed by a dedicated circuit (not shown) configured to, for example, reread a portion of the time-domain IQ data from the memory 1211, remove the reread portion as the CP, and store the modified time-domain IQ data back in the memory 1211.

[0149] As described above, in some embodiments, the transceiver IC 1200B is configured to process the IQ data completely in the time domain without additional processing elements involving frequency-time domain conversion of the IQ data (transmission side) and frequency-time domain conversion of the IQ data (reception side) as described in relation to the transceiver IC device architecture shown in FIG. 12A. Thus, on the reception side, the processed time-domain digital data need not be converted to frequency-domain digital IQ data via an FFT operation as in the embodiment of FIG. 12A. Rather, the received time-domain IQ data may be processed by the MUX / Combining Circuit 1264 for transmission to the serial data bus via the Serial Transmitter TX#0 1204, for example, for transmission to a beamformer processor. Subsequent time-frequency IQ data conversion may be performed in the beamformer processor as described previously herein.

[0150] As described above, when beam tilt is desired, the transceiver ICs described herein can be configured to incrementally adjust the phase of each IQ data packet that is commonly processed according to the position of the radiating elements driven by the transceiver ICs within a given IC sub-array. Further, electronic beam tilt is a process that imposes an appropriate signal delay without actually physically repositioning the antenna. As described above, electronic beam tilt in a physically static array can be achieved by various methods performed by the individual transceivers described herein, including (i) applying an incremental phase rotation to each sub-carrier frequency domain IQ data point (e.g., via an NCO), (ii) applying a constant phase rotation to each sub-carrier frequency domain IQ data point (e.g., via complex multiplication), (iii) applying a constant phase rotation to each sample of the baseband time domain signal (e.g., via complex multiplication), (iv) imposing a time delay on the discrete time domain signal of the transmitted baseband signal, or (v) a combination of the above methods. Since a detailed description of these various methods has been provided above, it will not be repeated here.

[0151] However, it should be noted that in the embodiment of FIG. 12B (different from the embodiment of FIG. 12A), the transceiver IC 1200B is configured to process IQ data entirely in the time domain. Therefore, an electronic beam tilt method (or, more generally, any other suitable frequency domain-based electronic beam tilt technique) that includes applying, for example, a phase rotation (e.g., incremental or constant) to each subcarrier frequency domain IQ data point is not applicable to the transceiver IC device architecture of FIG. 12B. Instead, the electronic beam tilt can be achieved via any suitable time domain technique, such as applying a constant phase rotation (e.g., via complex multiplication) to each sample of the baseband time domain signal, or imposing a time delay on the discrete time domain signal of the transmitted baseband signal, as described herein. For example, in FIG. 12B, the time domain IQ data (after CP addition operation) is passed to the transmit time domain signal processing circuit 1217 (further described with respect to FIG. 13A) and processed therein for electronic beam tilt by performing complex multiplication in the time domain or by imposing a time delay.

[0152] FIG. 13A is a block diagram 1300 of an example of a time-domain signal processing circuit 1217 according to some embodiments. The time-domain IQ data is received directly or indirectly from memory via line 1302 (similarly, lines 1304, 1344, and 1346) and applied to a signal path power detector and a gain unit 1306 for adjusting the power level. As described above, the memory may be a DSP memory or a memory coupled to a dedicated circuit (e.g., as in some embodiments described above in connection with FIG. 12B). Further, in some embodiments, the gain multiplier may also include a complex phase that rotates each time-domain value by the same phase. This time-domain phase rotation may be used to apply an approximate time delay that can be used to implement an electronic beam tilt. This corresponds to the phase rotation of each constituent subcarrier by the same phase, rather than a linearly incremented phase rotation, but is accurate enough for a bandwidth of about 100 MHz within the frequency range of the bands used for LTE and 5G signals. The signal is filtered by an FIR filter stage 1308 that also includes one or more interpolation stages to increase the sample rate of the discrete-time domain signal. The discrete-time digital UL signal is then processed by a numerically controlled oscillator (NCO) 1310. The NCO (e.g., 1310) may be configured to multiply the time-domain signal by a complex sine function to perform a frequency shift of the baseband signal to a desired frequency range, such as a separate frequency range that does not overlap with other component carriers. In some embodiments, one transmit signal can be shifted slightly up in frequency so that two time-domain signals representing, for example, two component carriers can be added together without the frequency content of one signal overlapping the frequency content of the other signal, while another transmit signal, such as a separate component carrier provided on connection 1304, can be shifted slightly down using the corresponding NCO. The signal is further processed by a delay buffer 1312 that enables precise time offset adjustment of the transmit signal. In some embodiments, the delay buffer 1312 is used to provide delay adjustment for each carrier.The latency buffer 1312 compensates for different processing times between different supported subcarrier spacings (SCS) and bandwidths. Assuming that all filtering is performed using FIR filters for all carriers, the adjustable latency per carrier is the difference between the larger latency and the shortest latency, which is on the order of 10 μs. However, sharing its function with windowing relaxes that requirement.

[0153] The other discrete-time domain signals on lines 1304, 1344, and 1346 are processed in the same manner as the discrete-time domain signal on line 1302. In some embodiments, the discrete-time domain signals on lines 1302, 1304, 1344, and 1346 result from a frequency domain to time domain conversion from the DSP 1215, as described in more detail in connection with FIG. 12A. In other embodiments, the discrete-time domain signals on lines 1302, 1304, 1344, and 1346 result from received time domain IQ data by the transceiver IC, as described in more detail in connection with FIG. 12B. Each of these signals can then be coupled and / or routed via the MUX / ADD circuit 1314 to the transmit signal processing circuits 1316, 1348 for crest factor reduction (e.g., CFR 1318), further FIR filtering (including further upsampling / interpolation), and IQ multiplication (e.g., FIR IQ circuit 1322) for phase adjustment and / or correction. Each signal can also receive digital pre-distortion (DPD, e.g., DPD circuit 1324) to correct for phase and amplitude distortion present in the modulators / amplifiers DPA 1328a, 1328b with respect to the first signal port 1342 from the RF signal adder 1340 (and with respect to DPA 1328c, 1328d, signal port 1350). Each section 1328a - 1328d of each DPA (e.g., DPA 1222 and 1232 as shown in FIGS. 12A - 12B) includes a clock domain crossing circuit 1330, a cascaded integrator comb (CIC) filter 1332, a mapper circuit 1334, a delay circuit 1336, and a final DPA stage 1338.

[0154] FIG. 13B shows an example of a receive time domain signal processing circuit 1241 according to some embodiments. Digital samples from the ADC are received by a clock domain crossing circuit 1362 and adjusted for DC offset by a DC offset circuit 1364. An IQ multiplier 1366 can be used to provide automatic gain control of the baseband time domain signal in response to the power measured by a power detector PD 1368. A quadrature error compensation circuit (QEC 1370) provides compensation for frequency-dependent quadrature errors in the RX analog front end. In one embodiment, the QEC circuit 1370 divides a time domain signal (e.g., having a sample rate of 245.76 MHz) into 16 frequency bins each of 15.36 MHz. Each frequency bin is added to the mirror frequency bin content shaped by a complex multiplier. A notch filter 1372 can be used to reduce any unwanted out-of-band signals.

[0155] The MUX1374 can be configured to selectively direct received signal samples from either path RX0 (1360) or RX1 (1394) to any or all of the RX signal paths 1376, 1392, 1396, or 1398. Some examples of the different possibilities are all four RX signal paths from RX0, all four RX signal paths from RX1, RX0 to RX signal paths 1376 and 1392, RX1 to RX signal paths 1396 and 1398, RX0 to RX signal path 1376, and RX1 to RX signal paths 1392, 1396, and 1398. Each RX signal path includes a delay buffer (e.g., 1378), an NCO (e.g., 1380), a FIR filter and a downsampler (e.g., 1384, 1382), and a power detector (e.g., PD1390). Note that the gain multiplier (e.g., 1386) can also implement a fixed phase rotation for the time domain signal. In such an embodiment, this is equivalent to a fixed phase shift applied to each subcarrier, rather than a linearly increasing phase shift across the subcarriers, but still provides a suitable approximation of the time delay for the purpose of implementing electronic beam tilt. FIR1382 can also include a notch filter to remove component carriers not being processed by a given signal path. In some embodiments, the NCO1380 can be used to apply a time domain frequency shift that moves the desired component carrier into the low pass passband of the notch filter 1382.

[0156] FIG. 14 is a diagram showing a generalized configuration of exemplary signal processing through the transceiver IC devices of FIGS. 12A-12B and FIGS. 13A-13B for dual-carrier, dual-polarization communication signals according to some embodiments. More specifically, the example of the signal processing configuration shown in FIG. 14 may be applicable in embodiments involving the communication of data packets associated with two different carriers (e.g., two component carriers), where each carrier signal has two polarizations (e.g., horizontal and vertical polarizations as described previously herein). In an exemplary embodiment, the transceiver device is a transceiver IC. Further, in the exemplary configuration of FIG. 14, the transceiver IC operates in TDD mode within an OFDM-modulated wireless network such as an LTE- or 5G-based communication system.

[0157] As shown in FIG. 14, the transceiver device (IC) 1400 includes a first serial communication port 1406 (e.g., a first serial port transmitter / receiver such as a Serdes transmitter / receiver) (shown as "Link 0" in FIG. 14) and a second serial communication port 1434 (e.g., a second serial port transmitter / receiver such as a Serdes transmitter / receiver) (shown as "Link 1" in FIG. 14). However, although the transceiver IC is shown as having two separate serial communication ports (1406 and 1434), it should be noted that in the exemplary embodiment of FIG. 14, only one of ports 1406 and 1434 is being used. More specifically, as shown, only serial communication port 1406 is connected to serial data links 1402 and 1404 to communicate data to / from the transceiver IC, and serial communication port 1434 is not being actively used. However, in some embodiments, the transceiver IC may be further serially connected to a second transceiver IC via port 1434 (e.g., as in various embodiments described herein (e.g., see FIGS. 2-4)).

[0158] Generally, as described above, the transceiver IC can be configured to process four separate transmit component carriers and four separate receive component carriers. The transceiver IC is typically composed of at least two separate transmit signal port paths (chains) and at least two separate receive signal port paths (chains), and is typically associated with two corresponding antenna radiating elements, but as described herein, other configurations are also possible. Also generally, the transceiver IC can include a number of signal processing elements such as, for example, an integrated digital signal processor (DSP) for converting time domain digital data to / from frequency domain digital data (via some iFFTs and FFTs), adding and removing cyclic prefixes (in embodiments where the IQ data packets received / transmitted by the transceiver IC are in the frequency domain), a plurality of integrated modulation digital power amplifiers (DPAs) for converting digital baseband time domain signals to amplified analog RF signals, analog RF down converters, and analog to digital converters.

[0159] Referring to FIG. 14, in some embodiments, the serial communication port 1406 can receive, via the serial data link 1402, a data packet stream (e.g., four multiplexed data packet streams) for DL (downlink) transmission (e.g., from a beamformer processor), and the packets include, for each of the horizontal (H) polarization and the vertical (V) polarization, a packet for a first component carrier (hereinafter, "carrier C1") and an IQ data packet for a second different component carrier (hereinafter, "carrier C2"). For simplicity, in this specification, the combinations of two different component carriers and horizontal and vertical polarizations are denoted as "C1H", "C2H", "C1V", and "C2V", respectively. In the UL (uplink) direction, the serial communication port 1406 can receive, for each of the two carriers C1 and C2, for each of the two H and V polarizations, an IQ data packet stream (e.g., four multiplexed sets of IQ data for four sets of OFDM subcarriers) and transmit them (e.g., to a beamformer processor) via the serial data link 1404.

[0160] It should be noted that for the exemplary transceiver IC configuration shown in FIG. 14, it is assumed that data packets received or transmitted at serial port communication port 1406 contain digital IQ data specific to a frequency domain sub-carrier. However, in an alternative embodiment, it should be understood that transceiver IC 1400 may instead be configured to receive and transmit (e.g., to / from a beamformer processor) data packets containing time domain sub-carrier specific digital IQ data (see, for example, FIG. 12B and the corresponding description for an example of such a configuration). In such an alternative (time domain only) embodiment, the iFFT and FFT processing may be shifted from the transceiver IC, as described above, for example, to a beamformer processor. Further, in some embodiments, different carrier packets addressed to the same transceiver IC (including either frequency domain or time domain IQ data) may contain a unique carrier ID and may be addressed to the same transceiver IC.

[0161] As shown in FIG. 14, serial communication port 1406 may be coupled to a signal processing unit 1408 that includes several elements configured to provide various digital signal processing functions, as previously described in connection with FIGS. 12A_B and 13A_B. In some embodiments, signal processing unit 1408 may be a single digital signal processor (DSP) that performs all of the iFFT and FFT calculations, as well as other signal processing functions (not shown) associated with, for example, frequency domain / time domain I / Q data signals.

[0162] During operation, in the downlink (DL) transmission direction, the IQ packet data stream received via link 0 (1406) for DL transmission can be provided to a demultiplexer (or a similar element such as a section of memory by a memory map) 1410 that can separate the received data into two respective data streams for two separate transmission chains, i.e., one stream of IQ data for the dual carrier horizontal polarization signal (C1H / C2H signal) transmitted from the signal port coupled to radiating element 1430 and another stream of IQ data for the dual carrier vertical polarization signal (C1V / C2V signal) transmitted from the signal port coupled to radiating element 1422. An element 1412 (e.g., in the form of DSP memory) can further separate the horizontal and vertical frequency domain components (data points) for the sub-carriers of each respective component carrier C1 and C2, which are then transmitted to four separate iFFT / CP (IFFT / cyclic prefix) elements 1414 for conversion from the frequency domain to the time domain to generate four separate discrete time domain baseband data signals (two for each carrier frequency and two for each signal polarization). Although not explicitly shown, additional time domain and frequency domain processing may include, for example, cyclic prefix addition, frequency offset, phase and gain adjustment, filtering, and sample rate conversion.

[0163] In reality, as described above, the incoming data is split into four separate transmission paths. More specifically, as shown in FIG. 14, the output of unit 1408 includes (i) two separate discrete-time domain-based band data signals 1416 and 1418, shown as C1H(1416) and C2H(1418), and (ii) two separate discrete-time domain-based band data signals 1426 and 1428, shown as C1V(1426) and C2V(1428). As shown, following the conversion from the frequency domain to the time domain, the time domain signals C1H(1416) and C2H(1418) are added (summed) in time, and C1V(1426) and C2V(1428) are added (summed) in time, and the results of the signal addition are supplied to respective TX / DPA elements 1420, generally representing the transmission RF chain and the digital power amplifier, to generate an amplified analog RF signal C1H / C2H(1424) for the horizontal signal port and an amplified analog RF signal C1V / C2V(1432) for the vertical signal port. Then, signals 1424 and 1432 are provided to corresponding radiating elements 1422 and 1430 via respective SPDTs for transmission. Although not explicitly shown, it should be noted that additional time domain processing may include, for example, additional sample rate conversion, crest factor reduction (CFR), digital pre-distortion (DPD), etc., as previously described herein.

[0164] During operation, in the receive direction, the data-modulated dual-component carrier RF uplink signal can be received by transceiver IC (1400) at the horizontal and vertical signal ports via radiating elements 1422 and 1430. For ease of explanation and merely by way of example, it is assumed here that the amplified analog RF signals C1H / C2H (1424) and the amplified analog RF signals C1V / C2V (1432) are the uplink signals received by the transceiver IC. As shown in FIG. 14, the horizontally polarized RF signal and the vertically polarized RF signal can be provided to separate LNA / DC / ADC elements 1446 via their respective SPDTs. The LNA / DC / ADC elements 1446 perform the conversion from RF to baseband signal and the conversion from analog to digital signal, and then, for example, can perform further time-domain processing (e.g., quadrature error correction, filtering, etc. (not explicitly shown)).

[0165] As further shown, the output of element 1446 includes two copies of a discrete-time domain baseband data signal. The two signals are filtered by FIR filters 1442, 1444, but one of the signals has its frequency first shifted by an NCO (either within filter 1442 or 1444) to separate the component carriers. The separated carriers are shown as C1H (1442) and C2H (1444). Two additional identical discrete-time domain baseband data signals are provided to filters 1426 and 1428 and generate time domain signals representing the component carrier time domain signals (after NCO conversion and FIR filtering) shown as C1V (provided by filter 1448) and C2V (provided by filter 1450). These four distinct time domain baseband signals 1442, 1444, 1148, and 1450 (two for each carrier, two for each polarization) are then input to DSP 1408 for signal processing including CP removal and conversion (via FFT element 1440) from the time domain IQ signal samples to frequency domain IQ data representing the magnitude and phase of each sub-carrier of the corresponding component carrier.

[0166] Accordingly, in this embodiment, the received RF signal is effectively split into four discrete-time domain baseband data signals that are processed on four separate receive paths. More specifically, the C1H signal (1442), C2H signal (1444), C1V signal (1448), and C2V signal (1450) are analyzed for four separate FFT signal processing operations (e.g., 1440) for conversion (by FFT) from the time domain to the frequency domain, such as by memory mapping, and for each of the two component carrier frequencies, for each signal polarization, four distinct frequency domain IQ data packets (or a stream of packets where each packet in the stream represents the symbol time within a slot) are generated.

[0167] Although not explicitly shown, other time-frequency pre-conversion signal processing may include, for example, sample rate conversion, filtering, cyclic prefix detection and removal, etc., as described above. Following the conversion performed by the FFT element 1440, elements 1436, 1438 (e.g., in the form of DSP memory and digital logic) can then formulate IQ data packets for different component carriers associated with both component carriers C1 and C2 for each polarization (H or V). In an alternative embodiment without time-frequency domain conversion (as described above), it should be noted that IQ data packets for different component carriers associated with both component carriers C1 and C2 for each polarization (H or V) can instead be formulated in the time domain.

[0168] As a further illustration of other embodiments, FIG. 15 shows a generalized configuration of exemplary signal processing through two serially connected transceiver devices of FIGS. 12 and 13 for generating a 4-carrier dual-polarization communication signal according to some embodiments. More specifically, FIG. 15 shows a transceiver device architecture 1500 including a first transceiver device 1504a and a second transceiver device 1504b. As in FIG. 14, in an exemplary embodiment, the transceiver device is a transceiver IC and operates in TDD mode within an OFDM modulation system such as a 5G or LTE-based communication system. It should be noted that various operating principles and nomenclatures described in connection with FIG. 14 apply to the embodiment of FIG. 15, and thus, some details of the operations are omitted or generalized for ease of explanation.

[0169] Referring to FIG. 15, the first transceiver device (IC) 1504a includes a first serial communication port 1506 (e.g., a first serial port transmitter / receiver such as a Serdes transmitter / receiver), shown as "Link 0" in FIG. 15, and a second serial communication port 1530 (e.g., a second serial port transmitter / receiver such as a Serdes transmitter / receiver), shown as "Link 1" in FIG. 15. Similarly, the second transceiver device (IC) 1504b includes a first serial communication port 1546 (e.g., a first serial port transmitter / receiver such as a Serdes transmitter / receiver), shown as "Link 0" in FIG. 15, and a second serial communication port 1562 (e.g., a second serial port transmitter / receiver such as a Serdes transmitter / receiver), shown as "Link 1" in FIG. 15. The transceiver devices (ICs) 1504a and 1504b are serially connected via a bidirectional serial data link 1544.

[0170] In some embodiments, serial communication port 1506 can receive, via bidirectional serial data link 1502, an IQ data packet stream for DL transmission (eight sets of IQ data packetized in four carrier-specific H / V combinations or, in the illustrated embodiment, as eight separate data packet streams), where the packets include IQ sub-carrier data for four different component carriers (hereinafter, "carrier C1", "carrier C2", "carrier C3", and "carrier C4") for each of horizontal (H) polarization and vertical (V) polarization. For simplicity, the combinations of four different carriers on horizontal and vertical polarizations are herein denoted as "C1H", "C2H", "C3H", "C4H", "C1V", "C2V", "C3V", and "C4V", respectively. In the UL (uplink) direction, serial communication port 1506 can receive data packet streams (e.g., eight multiplexed data packet streams) for each of the four carriers C1, C2, C3, and C4 for each of two H polarizations and V polarizations and transmit them (e.g., to a beamformer processor) via the same bidirectional serial data link 1502.

[0171] Note that in the transceiver device architecture 1500 shown in FIG. 15, for example, it should be noted that the packets received at or transmitted from the serial port communication port 1506 are assumed to contain frequency domain sub-carrier specific digital IQ data. However, in an alternative embodiment, each transceiver device 1504a and 1505b may be configured accordingly such that the packets received at or transmitted from the serial port communication port 1506 (e.g., from / to the beamformer processor) instead contain time domain sub-carrier specific digital IQ data (see, for example, FIG. 12B and the corresponding description of an example of such a configuration). In this regard, the iFFT and FFT processing may be shifted from the transceiver device (IC) side to the beamformer processor as described above.

[0172] During operation, in the DL transmission direction, the first transceiver IC (1504a) receives a packetized IQ data stream via port 1506 for DL transmission. The first transceiver IC is configured to process data related to the first two carriers for each polarization, i.e., C1H, C2H, C1V, and C2V. Similar to the transmission operation described in relation to FIG. 14, the first transceiver IC (1504a) separates the received IQ data for carriers C1 and C2 into respective data sets for two separate transmission paths, i.e., one stream of IQ data for the dual-carrier horizontal polarization signal (C1H / C2H signal) and another stream of IQ data for the dual-carrier vertical polarization signal (C1V / C2V signal) (via a demultiplexer or similar element (1508)). As shown generally by elements 1510 and 1520 (shown as "C1H / C2H" and "C1V / C2"), the horizontal and vertical frequency domain components for the sub-carriers of each respective component carrier C1 and C2 are further split and processed by four separate iFFT / CP elements to generate four separate discrete-time domain baseband data signals (two for each component carrier, two for each signal polarization), which are then time-aligned and added pairwise, and the results of the signal addition (C1H + C2H, and C1V + C2V) are provided to the respective TX / DPA elements 1512 and 1522 to generate a modulated and amplified analog RF signal C1H / C2H for the horizontal signal port of transceiver IC 1504a and an amplified analog RF signal C1V / C2V for the vertical signal port of transceiver IC 1504a.

[0173] Unlike the embodiment of FIG. 14, the packet data related to the other two carriers C3 and C4 received at port 1506 is transferred to the second transceiver IC (1504b) for processing. More specifically, the first transceiver IC (1504a) can be configured to transfer the IQ data packets for carriers C3 and C4 for each polarization, i.e., C3H, C4H, C3V, and C4V, to the second transceiver IC (1504b) for processing. In some embodiments, different carrier packets addressed to either the first or second transceiver IC can include a unique carrier ID and can be addressed to their respective transceiver ICs via one or more identification fields within the IQ data packet. Thus, the first transceiver IC can be configured to inspect incoming packets to determine which packets are addressed to the first transceiver IC and which packets should be transferred to the second transceiver IC.

[0174] In some embodiments, the first transceiver IC may transfer these packets serially to its second serial communication port 1530, which is serially interconnected with the serial communication port 1546 within the second transceiver IC (i.e., the second transceiver IC) via the internal path 1532 and via the serial data link 1544. The second transceiver IC performs signal processing similar to that of the first transceiver IC (with respect to carriers C3 and C4) via elements 1548, 1550, 1556, 1552, and 1558, and outputs the amplified analog RF signals C3H / C4H and C3V / C4V on two signal ports of the transceiver IC 1504b.

[0175] Subsequently, (i) the two signals C1H / C2H and C3H / C4H for horizontal polarization are combined via an adder element 1514 to generate a combined signal 1518 that is provided to a radiating element 1526 via a first SPDT for transmission, and (ii) the two signals C1V / C2V and C3V / C4V for vertical polarization are combined via an adder element 1524 to generate a combined signal 1528 that is provided to a radiating element 1516 via a second SPDT for transmission.

[0176] Similarly, in the receiving direction, the data-modulated 4-carrier dual-polarization RF uplink signal can be received by two serially-connected transceiver ICs (1504a and 1504b) via radiating elements 1516 and 1526 respectively corresponding to the horizontal and vertical signal ports. Similar to the case of FIG. 14, for ease of explanation and for illustrative purposes only, it is assumed that the analog RF signals C1H / C2H / C3H / C4H (1518) and the analog RF signals C1V / C2V / C3V / C4V (1628) are the current received uplink signals.

[0177] As shown in FIG. 15, the RF signal (1518) received by the horizontal polarization antenna element 1516 is supplied via respective SPDTs to the RX / LNA element 1538 in the first transceiver IC (1504a), and the RF signal (1528) received by the vertical polarization antenna element is supplied via respective SPDTs to the RX / LNA element 1570 in the second transceiver IC (1504b). Similar to the processing shown in FIG. 14, each of the respective horizontal receive RX / LNA chains and vertical receive RX / LNA chains is configured to perform signal conversion from RF to baseband, signal conversion from analog to digital, etc., to output a first 4-carrier discrete-time domain signal on the horizontal receive path and a second 4-carrier discrete-time domain signal on the vertical path. Thus, in some embodiments, the output of the RX / LNA 1538 element can be the first 4-carrier discrete-time domain signal on the horizontal polarization receive path, and the output of the RX / LNA element 1570 can be the second 4-carrier discrete-time domain signal on the vertical polarization receive path. Note that in this embodiment, each transceiver IC processes four component carriers in one of the RX / LNA elements, and the other RX / LNA elements (1542, 1576) are disabled.

[0178] Returning to the signal processing shown in FIG. 15, with respect to horizontal polarization, the output of the RX / LNA element 1538 includes discrete-time domain baseband data signals 1536 and 1540 that are processed on two separate signal processing branches, where (i) carriers C1 and C2, shown as C1H / C2H (1536), are processed on one branch, and (ii) carriers C3 and C4, shown as C3H / C4H (1540), are processed on the other branch. Similarly, with respect to vertical polarization, the output of the RX / LNA element 1570 can include discrete-time domain baseband data signals 1568 and 1574 to be processed on two separate signal processing branches, where (i) carriers C1 and C2, shown as C1V / C2V (1568), are processed on one branch, and carriers C3 and C4, shown as C3V / C4V (1574), are processed on the other branch.

[0179] The various principles of the operation of received signal processing (including, for example, the conversion from a time domain signal to frequency domain IQ data) are similarly applicable to the receive path of the arrangement of FIG. 15 as described in connection with FIG. 14 and will not be repeated in detail here. For purposes of illustration, in some embodiments, the received C1H / C2H signals (1536) for horizontal polarization are separated from C3H / C4H by time domain FIR filtering, notch filtering, etc., and further separated into the constituent carriers C1H and C2H in one signal path for removing the C2H component to obtain C1H. Another path, however, includes complex multiplication via a numerically controlled oscillator (NCO) frequency for shifting the C2H component to the desired baseband signal, followed by additional filtering for removing the residual component of C1H. Thus, one transceiver IC (1504a) can receive four component carriers on a single receive RF signal port (e.g., via either one of an H polarization antenna element or a V polarization antenna element) and decompose the signal into four separate component carriers. In the illustrated embodiment, all four separate component carriers C1H, C2H, C3H, C4H are separated using time domain signal processing and then transmitted to four separate FFT operations (in some embodiments, all performed by a single DSP processor) for conversion from the time domain to the frequency domain. Similarly, the C1V / C2V / C3V / C4V signals (1528) for vertical polarization, first processed by a single LNA and ADC 1570, are processed through filtering, frequency offset (i.e., NCO modulation), and further filtering and conditioned for four separate FFT operations for conversion from the time domain to the frequency domain. Although not explicitly shown, other time-frequency pre-conversion signal processing may include, for example, sample rate conversion, filtering, cyclic prefix detection and removal, etc., as described above.

[0180] Following the time-frequency domain conversion, in the present embodiment, elements 1534 and 1566 (on the horizontal path and vertical path respectively) then route and / or store IQ data points for sub-carriers associated with the individual component carriers C1, C2, C3, and C4 for each respective polarization (H or V). The frequency domain IQ data for all four component carriers can be further combined into a packet data stream (e.g., eight packet data streams, or four combined V / H packet streams) for transmission (e.g., to a beamformer processor) via the bidirectional serial link 1502 from two serially connected transceiver ICs (1504a and 1504b) for each polarization.

[0181] More specifically, in this regard, the frequency domain IQ packet data corresponding to the vertical polarization signals for the four carriers C1, C2, C3, and C4 can be received at the serial communication port 1562 of the second transceiver IC (1504b). The second transceiver IC can be configured to transfer those data packets serially, via the internal link 1564, to another serial communication port 1530 that is serially interconnected with the first transceiver IC (i.e., the serial communication port 1546 within the first transceiver IC) via the serial data link 1544. Although not explicitly shown in FIG. 15, in some embodiments, by multiplexing the packet data corresponding to the vertical polarization signals of the four carriers C1, C2, C3, and C4 received at the serial communication port 1530, the packet data output by the element 1534 (for the horizontal polarization of all four carriers C1, C2, C3, and C4) can be combined to generate an IQ data packet stream that is transmitted on the data link 1532 to the serial data link transceiver 1506 for communication to the beamformer processor via the serial communication link 1502. However, it should be noted that in alternative embodiments that do not include the time-frequency domain conversion (as described above), the frequency domain IQ data for all four component carriers for each polarization can instead be combined into a packet data stream for transmission in the time domain (e.g., via the bidirectional serial link 1502 to the beamformer processor).

[0182] Furthermore, in the embodiment of FIG. 15, DL and UL signal processing is not executed symmetrically across serially connected transceiver ICs. DL transmission signal processing is split according to component carriers (both the H and V polarities of C1 and C2 are processed by the first transceiver IC (1504a), and both the polarities of C3 and C4 are processed by the second transceiver IC (1504b)), while UL reception signal processing is split according to polarity (all H polarities of C1, C2, C3, and C4 are processed by the first transceiver IC (1504a), and all V polarities of C1, C2, C3, and C4 are processed by the second transceiver IC (1504b)). In some embodiments, this has the advantage of relaxing the bandwidth requirements in the transmission modulator so as to span only two component carriers (e.g., C1, C2 processed in the first transceiver IC (1504a) and C3, C4 processed in the second transceiver IC (1504b)) on the transmission side, while on the reception side, it has the advantage of not splitting the received RF signal into two different signal ports of two different transceiver ICs before processing by downconversion and sampling by the ADC. Thus, in the described embodiment, a dual-polarity four-component carrier system can be implemented using the wideband capabilities of the receiver portion of the transceiver IC to process a received signal having the bandwidth of a four-component carrier while relaxing the transmission modulator / amplifier bandwidth requirements to accommodate a transmission signal having the bandwidth of only two component carriers.

Claims

Claim 1 An apparatus comprising: a first serial data interface and a second serial data interface of a transceiver configured to transmit and receive aggregated signal port IQ data packets; a packet header inspection circuit configured to (i) identify aggregated signal port IQ data packets for local processing, (ii) identify aggregated signal port IQ data packets received for processing by another transceiver device, and (iii) transfer the identified received aggregated signal port IQ data packets for processing by another transceiver device using the second serial data interface; a digital signal processor (DSP) configured to perform an inverse fast Fourier transform (IFFT) to convert the identified aggregated signal port IQ data packets for local processing into an aggregated signal port discrete time domain baseband data signal; a downlink (DL) time domain processing circuit configured to convert the aggregated signal port discrete time domain baseband data signal into an oversampled signal port discrete time domain data signal; an integrated digital converter and a polyphase carrier generator configured to convert the oversampled signal port discrete time domain data signal into an analog modulated radio frequency signal. Claim 2 The apparatus of claim 1, wherein the DL time domain processing circuit comprises at least four DL signal path processing circuits, each DL signal path processing circuit including an upsampling circuit, a numerically controlled oscillator (NCO), and a delay buffer. Claim 3 The apparatus of claim 2, wherein each DL signal path processing circuit is configured to operate on a separate aggregated signal port discrete time domain baseband data signal provided by the DSP. Claim 4 Two of the at least four DL signal path processing circuits are configured to generate a first oversampled signal port discrete-time domain data signal, and a second two of the at least four DL signal path processing circuits are configured to generate a second oversampled signal port discrete-time domain data signal. The apparatus according to claim 2.

5. The DL time domain processing circuit further includes a first crest factor reduction circuit configured to process the first oversampled signal port discrete-time domain data signal, and a second crest factor reduction circuit configured to process the second oversampled signal port discrete-time domain data signal. The apparatus according to claim 4.

6. The apparatus according to claim 1, further comprising a numerically controlled oscillator configured to apply an incremental phase rotation to the data points in the aggregated signal port IQ data packet before iFFT processing.

7. The apparatus according to claim 1, further comprising an uplink (UL) time domain processing circuit configured to convert a sampled and received downconverted aggregated signal port discrete-time domain baseband data signal into a downsampled signal port discrete-time domain data signal for FFT processing by the DSP.

8. The UL time domain processing circuit includes at least four UL signal path processing circuits, and each UL signal path processing circuit includes a downsampling circuit, a numerically controlled oscillator (NCO), and a delay buffer. The apparatus according to claim 7.

9. A method comprising: transmitting and receiving an aggregated signal port IQ data packet at a first serial data interface and a second serial data interface of a transceiver; storing the received aggregated signal port IQ data packet identified for local processing; transferring the received aggregated signal port IQ data packet identified for processing by another transceiver device using the second serial data interface; Execute an inverse fast Fourier transform (IFFT) using a digital signal processor (DSP) to convert the received aggregated signal port IQ data packet identified for local processing into an aggregated signal port discrete-time domain baseband data signal, Use a downlink (DL) time domain processing circuit to convert the aggregated signal port discrete-time domain baseband data signal into an oversampled signal port discrete-time domain data signal, Convert the oversampled signal port discrete-time domain data signal into an analog-modulated radio frequency signal, a method comprising.

10. The method according to claim 9, further comprising processing at least four DL signals using at least four DL signal path processing circuits.

11. The method according to claim 10, wherein the DSP is configured to provide a separate aggregated signal port discrete-time domain baseband data signal.

12. The method according to claim 9, further comprising applying an incremental phase rotation to data points within the aggregated signal port IQ data packet using a numerically controlled oscillator.

13. For FFT processing by the DSP, the method according to claim 9, further comprising using an uplink (UL) time domain processing circuit to convert a sampled, received, and down-converted aggregated signal port discrete-time domain baseband data signal into a downsampled signal port discrete-time domain data signal.

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