Display substrate and display device

Abstract

The present invention provides a display substrate and a display device. The display substrate includes a first signal line (200) and a second signal line (300). The display substrate includes a first region (101) and a second region (102), and neither the first signal line (200) nor the second signal line (300) passes through the second region (102). The first signal line (200) extends along a first direction, and the second signal line (300) extends along a second direction. Portions of the first signal line (200) located on both sides of the second region (102) among those whose extension lines pass through the second region (102) are electrically connected via a first connection line (410) extending along the first direction and a second connection line (420) extending along the second direction. Portions of the second signal line (300) located on both sides of the second region (102) among those whose extension lines pass through the second region (102) are electrically connected via a third connection line (430) extending along the first direction and a fourth connection line (440) extending along the second direction. The second connection line (420) and the third connection line (430) overlap, and on the same side of the second region (102), the first connection line (410) is located on the side away from the second region (102) of the third connection line (430). The display substrate reduces the wiring space around the second region and reduces a sudden change in the load of the first signal line and the second signal line.

Description

Technical Field

[0001] This application claims the priority of Chinese Patent Application No. 202210898751.4 filed on July 28, 2022, and all the disclosure contents of the above Chinese patent application are incorporated herein by reference.

[0002] Embodiments of the present disclosure relate to a display substrate and a display device.

Background Art

[0003] In the field of display technology, thin film transistors (TFTs) include amorphous silicon (a-Si) TFTs, low temperature poly-silicon (LTPS) TFTs, and oxides (e.g., indium gallium zinc oxide TFTs). Low temperature polycrystalline oxide (LTPO) is a low power consumption display technology. The LTPO technology combines the low temperature poly-silicon process and the oxide process to manufacture LTPS TFTs and oxide TFTs on a display panel, thereby combining the advantages of LTPS TFTs and oxide TFTs, maximizing the advantages of the ultra-high mobility of low temperature poly-silicon and the small leakage current of oxides, and realizing better display performance.

[0004] As the pursuit of the visual effect of display products continues, narrow bezel and full screen display have gradually become the current development trend of organic light emitting diode (OLED) display products.

Summary of the Invention

Problems to be Solved by the Invention

[0005] Embodiments of the present disclosure provide a display substrate and a display device.

Means for Solving the Problems

[0006] In an embodiment of the present disclosure, the display substrate includes a base substrate, a plurality of first signal lines located on the base substrate, and a plurality of second signal lines. The base substrate includes a first region and a second region, the first region is located around the second region, the plurality of first signal lines do not pass through the second region, the plurality of second signal lines are located in a layer different from the plurality of first signal lines and do not pass through the second region. At least a part of the first signal lines extends along a first direction, at least a part of the second signal lines extends along a second direction, the first direction and the second direction intersect, the plurality of first signal lines include partial first signal lines whose extension lines pass through the second region, each of the first signal lines among the partial first signal lines includes a first sub-signal line and a second sub-signal line located on both sides of the second region, the first sub-signal line and the second sub-signal line are electrically connected via a first connection line extending along the first direction and a second connection line extending along the second direction, and the partial first signal lines are electrically connected to a plurality of first connection lines and a plurality of second connection lines. The plurality of second signal lines include partial second signal lines whose extension lines pass through the second region, each of the second signal lines among the partial second signal lines includes a third sub-signal line and a fourth sub-signal line located on both sides of the second region, the third sub-signal line and the fourth sub-signal line are electrically connected via a third connection line extending along the first direction and a fourth connection line extending along the second direction, and the partial second signal lines are electrically connected to a plurality of third connection lines and a plurality of fourth connection lines. In a direction perpendicular to the base substrate, at least one second connection line and at least one third connection line overlap, and on the same side of the second region, at least one first connection line is located on the side away from the second region of at least one third connection line.

[0007] For example, according to an embodiment of the present disclosure, the plurality of first signal lines include data lines, and the plurality of second signal lines include at least emission control signal lines.

[0008] For example, according to an embodiment of the present disclosure, a minimum distance between one fourth connection line closest to the second region and an edge of the second region is less than a minimum distance between one first connection line closest to the second region and the edge of the second region.

[0009] For example, according to an embodiment of the present disclosure, on the same side of the second region, a first set of connection lines among the plurality of second connection lines is located on a side closer to the second region of at least one fourth connection line, and a second set of connection lines among the plurality of second connection lines is located on a side away from the second region of the at least one fourth connection line.

[0010] For example, according to an embodiment of the present disclosure, along a direction perpendicular to the base substrate, the first set of connection lines and the third connection line overlap, and the second set of connection lines and the third connection line do not overlap.

[0011] For example, according to an embodiment of the present disclosure, when a distance between one second connection line closest to the second set of connection lines among the first set of connection lines and one second connection line closest to the first set of connection lines among the second set of connection lines is defined as a first distance, and a distance between two adjacent second connection lines among the second set of connection lines is defined as a second distance, a ratio of the first distance to the second distance is greater than 2.

[0012] For example, according to an embodiment of the present disclosure, the first connection line connected to one second connection line closest to the second set of connection lines among the first set of connection lines includes two portions respectively located on both sides in the first direction of the one second connection line.

[0013] For example, according to an embodiment of the present disclosure, the first connection line connected to the one second connection line closest to the second set of connection lines among the first set of connection lines extends to a position of one second connection line closest to the first set of connection lines among the second set of connection lines.

[0014] For example, according to an embodiment of the present disclosure, each of the N first connection lines respectively connected to the N second connection lines among the first set of connection lines that are closest to the second set of connection lines includes two portions respectively located on both sides of the second connection line in the first direction, and among the N first connection lines arranged along the direction approaching the second region, the length of the portion of the first connection line located on the side closer to the second set of connection lines of the second connection line connected to the first connection line gradually decreases, N is a positive integer greater than or equal to 1, and the number of the second connection lines among the first set of connection lines located on the central side of the second region is greater than or equal to N.

[0015] For example, according to an embodiment of the present disclosure, among the plurality of second signal lines, the one second signal line closest to the second region among the second signal lines whose extension lines do not pass through the second region is located between the one fourth connection line closest to the second region and the fourth connection line adjacent thereto.

[0016] For example, according to an embodiment of the present disclosure, on the same side of the second region, at least one first signal line among the plurality of first signal lines whose extension lines do not pass through the second region is located on the side closer to the second region of the first connection line.

[0017] For example, according to an embodiment of the present disclosure, the ratio of the distance between one first connection line and one third connection line that are close to each other among the plurality of first connection lines and the plurality of third connection lines to the distance between two adjacent third connection lines is 0.8 to 1.2.

[0018] For example, according to an embodiment of the present disclosure, within the first region, at least one first connection line and at least one third connection line are located on the same layer, and at least one second connection line and at least one fourth connection line are located on the same layer.

[0019] For example, according to an embodiment of the present disclosure, at least one first connection line and at least one third connection line are both located on the same layer as the plurality of first signal lines.

[0020] For example, according to an embodiment of the present disclosure, the plurality of second signal lines are located between the plurality of first signal lines and the base substrate, and the fourth connection line is located between the plurality of first signal lines and the plurality of second signal lines.

[0021] For example, according to an embodiment of the present disclosure, the first region is a display region, the first region surrounds the second region, the base substrate further includes a peripheral region surrounding the display region, the plurality of second sets of connection lines include the second connection lines located in the first region and the second connection lines located in the peripheral region, the second connection lines located in the first region are provided in a layer different from the first connection lines, and the second connection lines located in the peripheral region are provided in the same layer as the first connection lines.

[0022] For example, according to an embodiment of the present disclosure, the second connection lines located in the peripheral region are provided in the same layer as the first signal lines.

[0023] For example, according to an embodiment of the present disclosure, at least one second connection line and at least one fourth connection line among the first set of connection lines are provided in the same layer with a space therebetween and are on the same straight line.

[0024] For example, according to an embodiment of the present disclosure, on the same side of the second region, at least one first signal line connected to the second set of connection lines overlaps with each fourth connection line in a direction perpendicular to the base substrate.

[0025] For example, according to an embodiment of the present disclosure, the orthographic projection of each first connection line on a straight line extending along the first direction and the orthographic projection of each third connection line on the straight line overlap, and the orthographic projection of at least one second connection line on a straight line extending along the second direction and the orthographic projection of at least one fourth connection line on the straight line do not overlap.

[0026] For example, according to an embodiment of the present disclosure, the display substrate further includes a light-emitting element and a pixel circuit located on the base substrate. The pixel circuit and the light-emitting element are electrically connected. The pixel circuit includes a driving transistor, a light-emitting control transistor, and a reset transistor. The gate of the light-emitting control transistor is electrically connected to the light-emitting control signal line. The first pole of the light-emitting control transistor is electrically connected to the first pole of the driving transistor. The second pole of the light-emitting control transistor is electrically connected to the light-emitting element. The gate of the reset transistor is electrically connected to the reset control signal line. One pole of the reset transistor is electrically connected to the second pole of the driving transistor, or one pole of the reset transistor is electrically connected to the second pole of the light-emitting control transistor. The second signal line includes the reset control signal line.

[0027] For example, according to an embodiment of the present disclosure, the display substrate further includes a light-emitting element and a pixel circuit located on the base substrate. The pixel circuit and the light-emitting element are electrically connected. The pixel circuit includes at least one N-type thin-film transistor and at least one P-type thin-film transistor. The second signal line includes a signal line connected to the gate of at least one of the P-type thin-film transistors.

[0028] For example, according to an embodiment of the present disclosure, the display substrate further includes a light-emitting element and a pixel circuit located on the base substrate. The pixel circuit and the light-emitting element are electrically connected. The pixel circuit includes at least one oxide thin-film transistor and at least one low-temperature polysilicon thin-film transistor. The second signal line includes a signal line connected to the gate of at least one of the low-temperature polysilicon thin-film transistors.

[0029] For example, according to an embodiment of the present disclosure, The first region is a display region, the first region surrounds the second region, and the base substrate further includes a peripheral region surrounding the display region. The display substrate further includes a plurality of fifth connection lines extending along the first direction and a plurality of sixth connection lines extending along the second direction. The fifth connection lines located in the same layer and on the same straight line as the first connection line are provided at intervals from the first connection line. The fifth connection lines located in the same layer and on the same straight line as the third connection line are provided at intervals from the third connection line. The sixth connection lines located in the same layer and on the same straight line as the second connection line are provided at intervals from the second connection line. The sixth connection lines located in the same layer and on the same straight line as the fourth connection line are provided at intervals from the fourth connection line. And at least one of the fifth connection lines and the sixth connection lines is electrically connected to a third signal line, and the third signal line is located in the peripheral region.

[0030] For example, according to an embodiment of the present disclosure, at least one of the spaced portions between the fifth connection line and the first connection line and the spaced portion between the fifth connection line and the third connection line overlaps with the film layer where the fourth connection line is located. At least one of the spaced portions between the sixth connection line and the second connection line and the spaced portion between the sixth connection line and the fourth connection line overlaps with the film layer where the first connection line is located.

[0031] For example, according to an embodiment of the present disclosure, on both sides of at least one first connection line, two first signal lines adjacent to the first connection line are provided, and the ratio of the minimum distance between the two first signal lines and the first connection line is 0.9 to 1.1. On both sides of at least one third connection line, two first signal lines adjacent to the third connection line are provided, and the ratio of the minimum distance between the two first signal lines and the third connection line is 0.9 to 1.1.

[0032] Another embodiment of the present disclosure provides a display device including any one of the above display substrates.

Brief Description of the Drawings

[0033] To more clearly explain the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It is clear that the drawings in the following description are only related to some embodiments of the present disclosure and do not limit the present disclosure.

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Embodiments for Carrying out the Invention

[0034] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will refer to the drawings of the embodiments of the present disclosure to clearly and completely describe the technical solutions of the embodiments of the present disclosure. It is obvious that the described embodiments are only part of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts shall be included in the protection scope of the present disclosure.

[0035] Unless otherwise defined, technical or scientific terms used in this disclosure shall have the ordinary meanings as understood by those skilled in the art. The terms "first", "second", and similar words used in this disclosure do not indicate order, quantity, or importance, but are only used to distinguish different components. Terms such as "comprising" or "containing" mean that the element or thing appearing before that term includes the elements or things listed after that term and their equivalents without excluding other elements or things.

[0036] Features such as "parallel", "perpendicular", "identical", etc. used in the embodiments of this disclosure include the features of "parallel", "perpendicular", "identical", etc. in a strict sense, and cases including certain errors such as "substantially parallel", "substantially perpendicular", "substantially identical", etc. Considering the errors related to measurement and the measurement of specific quantities (for example, the limitations of the measurement system), it indicates that it is within the range of deviation that those skilled in the art determine to be acceptable for a specific value. For example, "substantially" can represent within one or more standard deviations, or within 10% or 5% of that value. When the amount of a component is not specified in the following embodiments of this disclosure, it means that the component can be one or more, or can be understood to be at least one. "At least one" refers to one or more, and "a plurality" refers to at least two. The "same layer" in the embodiments of this disclosure refers to the relationship between a plurality of film layers formed of the same material through the same step (for example, a one-step patterning process). The "same layer" mentioned here does not necessarily mean that the thicknesses of the plurality of film layers are the same, or that the heights in the cross-sectional view of the plurality of film layers are the same.

[0037] Embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a base substrate, a plurality of first signal lines located on the base substrate, and a plurality of second signal lines. The base substrate includes a first region and a second region, the first region is located around the second region, the plurality of first signal lines are located on the base substrate and do not pass through the second region, the plurality of second signal lines are located in a layer different from the plurality of first signal lines and do not pass through the second region. At least a part of the first signal lines extends along a first direction, at least a part of the second signal lines extends along a second direction, the first direction and the second direction intersect, the plurality of first signal lines include partial first signal lines whose extension lines pass through the second region, each of the first signal lines among the partial first signal lines includes a first sub-signal line and a second sub-signal line located on both sides of the second region, the first sub-signal line and the second sub-signal line are electrically connected via a first connection line extending along the first direction and a second connection line extending along the second direction, and the partial first signal lines are electrically connected to the plurality of first connection lines and the plurality of second connection lines. The plurality of second signal lines include partial second signal lines whose extension lines pass through the second region, each of the second signal lines among the partial second signal lines includes a third sub-signal line and a fourth sub-signal line located on both sides of the second region, the third sub-signal line and the fourth sub-signal line are electrically connected via a third connection line extending along the first direction and a fourth connection line extending along the second direction, and the partial second signal lines are electrically connected to the plurality of third connection lines and the plurality of fourth connection lines. In a direction perpendicular to the base substrate, at least one second connection line and at least one third connection line overlap, and on the same side of the second region, at least one first connection line is located on the side away from the second region of at least one third connection line.

[0038] The display substrate according to the embodiments of the present disclosure connects the signal lines located on both sides of the second region via the first connection line, the second connection line, the third connection line, and the fourth connection line, and the first connection line is located on the side away from the second region of the third connection line, and the second connection line and the third connection line overlap, thereby reducing the wiring space around the second region, increasing the area of the display region, and reducing a sudden change in the load of the first signal lines and the second signal lines.

[0039] Hereinafter, a display substrate and a display device according to an embodiment of the present disclosure will be described with reference to the drawings.

[0040] FIG. 1 is a partial plan schematic view of a display substrate according to an embodiment of the present disclosure. As shown in FIG. 1, the display substrate includes a base substrate 100, a plurality of first signal lines 200 located on the base substrate 100, and a plurality of second signal lines 300. The base substrate 100 includes a first region 101 and a second region 102, and the first region 101 is located around the second region 102. For example, in FIG. 1, it is illustrated that the first region 101 surrounds the second region 102, but it is not limited thereto. The first region 101 may be located only in a part of the peripheral position of the second region 102. For example, the first region 101 may surround only a part of the second region 102.

[0041] For example, as shown in FIG. 1, the first region 101 may be a display region, and the second region 102 may be a via region within the first region 101. For example, the second region 102 may be a display region or a non-display region. For example, the second region 102 is a region through which no signal line passes. For example, the edge of the second region 102 may be the edge of the via region. For example, at least a part of the edge of the second region 102 is not parallel to either the first direction or the second direction. For example, the shape of the second region 102 may be circular or elliptical. Without being limited thereto, the shape of the second region 102 may be a polygon, such as a quadrilateral, a hexagon, or an octagon. For example, the shape of the first region 101 may be a quadrilateral, such as a rectangle, but it is not limited thereto. The shape of the first region 101 may be circular or a polygon other than a quadrilateral, such as a hexagon or an octagon.

[0042] As shown in FIG. 1, a plurality of first signal lines 200 do not pass through the second region 102. The plurality of second signal lines 300 are located in a layer different from the plurality of first signal lines 200 and do not pass through the second region 102. For example, each first signal line 200 does not pass through the second region 102, and each second signal line 300 does not pass through the second region 102. For example, the plurality of first signal lines 200 that do not pass through the second region 102 include a first signal line 200 whose extension line does not pass through the second region 102 and a first signal line 200 whose extension line passes through the second region 102, and the plurality of second signal lines 300 that do not pass through the second region 102 include a second signal line 300 whose extension line does not pass through the second region 102 and a second signal line 300 whose extension line passes through the second region 102.

[0043] As shown in FIG. 1, at least a part of the first signal line 200 extends along the first direction, at least a part of the second signal line 300 extends along the second direction, and the first direction and the second direction intersect. In FIG. 1, the first direction is exemplarily shown as the X direction and the second direction is shown as the Y direction, but it is not limited thereto, and the first direction and the second direction may be exchanged. For example, the first direction and the second direction may be perpendicular, but it is not limited thereto, and the angle formed by the first direction and the second direction may be 60 to 110 degrees. For example, one of the first direction and the second direction may be the row direction and the other may be the column direction. For example, each first signal line 200 extends along the first direction, and each second signal line 200 extends along the second direction. In the embodiments of the present disclosure, that the first signal line extends along the first direction means that the extension direction of the entire first signal line is the first direction, and the first signal line may be a straight line extending along the first direction or a broken line extending along the first direction. That the second signal line extends along the second direction means that the extension direction of the entire second signal line is the second direction, and the second signal line may be a straight line extending along the second direction or a broken line extending along the second direction.

[0044] As shown in FIG. 1, the plurality of first signal lines 200 include a partial first signal line 200 where the extension line passes through the second region 102. Each of the first signal lines 200 in the partial first signal line 200 includes a first sub-signal line 210 and a second sub-signal line 220 located on both sides of the second region 102. The first sub-signal line 210 and the second sub-signal line 220 are electrically connected via a first connection line 410 extending along the first direction and a second connection line 420 extending along the second direction. Moreover, the partial first signal line 200 is electrically connected to a plurality of first connection lines 410 and a plurality of second connection lines 420. For example, the first connection line 410 and the second connection line 420 are electrically connected. The first signal line 200 whose extension line passes through the second region 102 is divided at the position of the second region 102 into two parts, namely the first sub-signal line 210 and the second sub-signal line 220. These two parts transmit the same signal and are electrically connected via the first connection line 410 and the second connection line 420.

[0045] For example, the embodiments of the present disclosure are not limited to the case where all of the first connection lines are in the same layer and all of the second connection lines are in the same layer. A part of the second connection line may be located in the same layer as the first connection line, and a part of the second connection line may be located in a layer different from the first connection line.

[0046] As shown in FIG. 1, the plurality of second signal lines 300 include a partial second signal line 300 where the extension line passes through the second region 102. Each of the second signal lines 300 in the partial second signal line 300 includes a third sub-signal line 310 and a fourth sub-signal line 320 located on both sides of the second region 102. The third sub-signal line 310 and the fourth sub-signal line 320 are electrically connected via a third connection line 430 extending along the first direction and a fourth connection line 440 extending along the second direction. Moreover, the partial second signal line 300 is electrically connected to a plurality of third connection lines 430 and a plurality of fourth connection lines 440. For example, the third connection line 430 and the fourth connection line 440 are electrically connected. The second signal line 300 whose extension line passes through the second region 102 is divided at the position of the second region 102 into two parts, namely the third sub-signal line 310 and the fourth sub-signal line 320. These two parts transmit the same signal and are electrically connected via the fourth connection line 440 and the third connection line 430.

[0047] For example, the "portion of the extension line passing through the second region 102 of the first signal line 200" mentioned above may be a portion extending from the end point of the first signal line 200 close to the second region 102 to the second region 102. For example, the "portion of the extension line passing through the second region 102 of the second signal line 300" may be a portion extending from the end point of the second signal line 300 close to the second region 102 to the second region 102.

[0048] For example, the embodiments of the present disclosure are not limited to all of the third connection lines being in the same layer and all of the fourth connection lines being in the same layer. For example, some of the fourth connection lines may be in the same layer as the third connection lines, and some of the fourth connection lines may be in a different layer from the third connection lines.

[0049] For example, as shown in FIG. 1, the first signal line 200 through which the extension line does not pass through the second region 102 may be a single continuous signal line, and the second signal line 300 through which the extension line does not pass through the second region 102 may be a single continuous signal line.

[0050] As shown in FIG. 1, in the direction perpendicular to the base substrate 100, at least one second connection line 420 and at least one third connection line 430 overlap, and on the same side of the second region 102, at least one first connection line 410 is located on the side away from the second region 101 of at least one third connection line 430.

[0051] The display substrate according to the embodiments of the present disclosure connects the first signal lines located on both sides of the second region with the first connection line and the second connection line, connects the second signal lines located on both sides of the second region with the third connection line and the fourth connection line, and at least one first connection line is located on the side away from the second region of at least one third connection line, and the second connection line and the third connection line overlap, thereby reducing the wiring space around the second region and increasing the space of the display region, and reducing a sudden change in the load (loading) of the first signal line and the second signal line, and preventing display non-uniformity, such as display mura.

[0052] In a normal display substrate, at least one of the first signal line and the second signal line adopts a design that surrounds the boundary of the second region around the second region. In contrast, in the display substrate according to the embodiments of the present disclosure, both the first signal line and the second signal line are electrically connected via connection lines extending along the first direction and the second direction. For example, two portions located on both sides of the second region are electrically connected by FIP (Fan-out In Pixel, the fan-out line is located in the pixel region) connection lines, thereby reducing the size of the boundary around the second region. For example, the frame around the second region can be narrowed, which is advantageous for increasing the area of the display region and improving the display effect.

[0053] For example, as shown in FIG. 1, in the first region 101 of the display substrate, the length of the first signal line 200 whose extension line does not pass through the second region 102 is greater than the length of the second signal line 300 whose extension line does not pass through the second region 102.

[0054] For example, as shown in FIG. 1, if the ratio of the size of the first signal line 200 in the first direction whose extension line does not pass through the second region 102 to the maximum size of the second region 102 in the first direction is r1, and the ratio of the maximum size of the second signal line 400 in the second direction whose extension line does not pass through the second region 102 to the maximum size of the second region 102 in the second direction is r2, then r1 is greater than r2.

[0055] In some examples, as shown in FIG. 1, the minimum distance between the fourth connection line 440 closest to the second region 102 and the edge of the second region 102 is less than the minimum distance between the first connection line 410 closest to the second region and the edge of the second region 102.

[0056] The ratio of the size of the second region to the length of the first signal line is less than the size of the second region to the length of the second signal line. Therefore, the influence of the length of the third connection line on the load of the second signal line is greater than the influence of the length of the second connection line on the load of the first signal line. In the display substrate according to the embodiment of the present disclosure, by designing the fourth connection line closer to the edge of the second region than the first connection line, the length of the third connection line connected to the second signal line through which the extension line passes through the second region is shortened, thereby reducing the difference between the load on the second signal line through which the extension line passes through the second region and the load on the second signal line through which the extension line does not pass through the second region.

[0057] For example, as shown in FIG. 1, on the same side of the second region 102, the distance between one fourth connection line 440 closest to the second region 102 and one second signal line 300 closest to the second region 102 and through which the extension line does not pass through the second region is D1, and the distance between one first connection line 410 closest to the second region 102 and one first signal line 200 closest to the second region 102 and through which the extension line does not pass through the second region is D2. Then, D1 is less than D2.

[0058] In some examples, as shown in FIG. 1, the first signal line 200 includes a data line, and the second signal line 300 includes at least an emission control signal line.

[0059] FIG. 2 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure, FIGS. 3A to 3H are schematic diagrams of each film layer of the pixel circuit, and FIG. 3I is a schematic diagram of the stack of the film layers shown in FIGS. 3A to 3F.

[0060] In some examples, as shown in FIG. 2, the display substrate further includes a plurality of sub-pixels, and at least a part of the sub-pixels includes a light-emitting element 120 and a pixel circuit 110 electrically connected to the light-emitting element 120.

[0061] For example, as shown in FIGS. 2 to 3I, the pixel circuit includes a plurality of transistors and at least one capacitor. For example, the pixel circuit includes a second reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a second light emission control transistor T5, a first light emission control transistor T6, a first reset transistor T7, a third reset transistor T8, and an accumulation capacitor C.

[0062] For example, as shown in FIGS. 2 to 3I, the display substrate further includes reset power signal lines 561, 551, and 554, scan signal lines 552, 531, and 523, a power signal line 581, reset control signal lines 522, 532, and 553, a light emission control signal line 521, and a data line 200.

[0063] For example, as shown in FIGS. 2 to 3I, the first pole of the threshold compensation transistor T2 is electrically connected to the first pole of the driving transistor T3, the second pole of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, the gate of the threshold compensation transistor T2 is electrically connected to the scanning signal lines 531 and 552, receives a compensation control signal, the first pole of the first reset transistor T7 is electrically connected to the reset power signal line 561, receives a reset signal Vinit2, the second pole of the first reset transistor T7 is electrically connected to the first electrode of the light emitting element (i.e., N4 node), the gate of the first reset transistor T7 is electrically connected to the reset control signal line 522, receives a reset control signal Reset(N + 1), the first pole of the third reset transistor T8 is electrically connected to the reset power signal line 551, receives a reset signal Vref, the second pole of the third reset transistor T8 is electrically connected to the second pole of the driving transistor T3, and the gate of the third reset transistor T8 is electrically connected to the reset control signal line 522. The first pole of the data writing transistor T4 is electrically connected to the second pole of the driving transistor T3, the second pole of the data writing transistor T4 is electrically connected to the data line 200 (first signal line 200), receives a data signal Data, and the gate of the data writing transistor T4 is electrically connected to the scanning signal line 523, receives a scanning signal Gate. The first pole of the storage capacitor C is electrically connected to the power signal line 581, and the second pole of the storage capacitor C is electrically connected to the gate of the driving transistor T3.The first pole of the second reset transistor T1 is electrically connected to the reset power signal line 554, receives the reset signal Vinit1, the second pole of the second reset transistor T1 is electrically connected to the gate of the driving transistor T3, the gate of the second reset transistor T1 is electrically connected to the reset control signal lines 553 and 532, receives the reset control signal Reset(N), the gate of the first light emission control transistor T6 is electrically connected to the light emission control signal line 521, receives the light emission control signal EM, the first pole of the first light emission control transistor T6 is electrically connected to the first pole of the driving transistor T3, and the second pole of the first light emission control transistor T6 is electrically connected to the first electrode of the light emitting element 120. The first pole of the second light emission control transistor T5 is electrically connected to the power signal line 581, receives the first power signal VDD, the second pole of the second light emission control transistor T5 is electrically connected to the second pole of the driving transistor T3, the gate of the second light emission control transistor T5 is electrically connected to the light emission control signal line 521, receives the light emission control signal EM, and the second electrode of the light emitting element 120 is electrically connected to the voltage terminal VSS (the subsequent third signal line 600). The above-mentioned power signal line refers to a signal line that outputs the voltage terminal signal VDD, is connected to the voltage terminal source, and may output a certain voltage terminal signal, for example, a positive voltage terminal signal.

[0064] In addition, in the embodiments of the present disclosure, each pixel circuit may have a structure including other numbers of transistors, such as a 7T1C structure, a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, in addition to the 8T1C (that is, eight transistors and one capacitor) structure shown in FIG. 2, and is not limited in the embodiments of the present disclosure.

[0065] FIG. 3A shows the first active layer pattern 510. For example, as shown in FIG. 3A, the first active layer pattern 510 may be used to form the channel regions of the above-described driving transistor T3, data writing transistor T4, second light emission control transistor T5, first light emission control transistor T6, first reset transistor T7, and third reset transistor T8 by fabricating the active layers of these transistors. The first active layer pattern 510 includes the active region patterns (channel regions) and doping region patterns (source-drain regions) of the above-described transistors for each sub-pixel, and the active region patterns and doping region patterns of the above-described transistors in the same pixel circuit are provided integrally.

[0066] For example, the first active layer pattern 510 may include an integrally formed low-temperature polysilicon layer, and in the source region and drain region, each structure may be electrically connected by conductivity conversion such as doping. For example, the source region and drain region may be regions doped with p-type impurities.

[0067] FIG. 3B shows the first conductive layer pattern 520 located on the side away from the base substrate of the first active layer pattern 510. For example, as shown in FIG. 3B, the first conductive layer pattern 520 includes a reset control signal line 522, a scanning signal line 523, the first electrode 524 of the capacitor, and a light emission control signal line 521. For example, the first conductive layer pattern 520 may include the gates of the driving transistor T3, data writing transistor T4, second light emission control transistor T5, first light emission control transistor T6, first reset transistor T7, and third reset transistor T8.

[0068] Note that in FIG. 3A, each rectangular box formed by the dashed lines shows each portion where the first active layer pattern 510 and the first conductive layer pattern 520 overlap, that is, the channel region. As the channel region of each transistor, the active semiconductor layers located on both sides of each channel region are made conductive by a process such as ion doping and function as the first and second electrodes of each transistor. Since the source and drain of a transistor may be symmetric in structure, the source and drain thereof are not distinguished in terms of physical structure. In the embodiments of the present disclosure, in order to distinguish transistors, except for the gate which is the control electrode, one of the electrodes is described as the first electrode and the other electrode is described as the second electrode. Therefore, in the embodiments of the present disclosure, all or part of the first and second electrodes of a transistor may be exchanged as necessary.

[0069] For example, as shown in FIGS. 3B and 3I, the gate of the data write transistor T4 may be a portion where the scan signal line 523 and the first active layer pattern 510 overlap, the gate of the first light emission control transistor T6 may be a first portion where the light emission control signal line 521 and the first active layer pattern 510 overlap, and the gate of the second light emission control transistor T5 may be a second portion where the light emission control signal line 521 and the first active layer pattern 510 overlap. The gate of the third reset transistor T8 is a first portion where the reset control signal line 522 and the first active layer pattern 510 overlap, and the gate of the first reset transistor T7 is a second portion where the reset control signal line 522 and the first active layer pattern 510 overlap.

[0070] FIG. 3C shows a second conductive layer pattern 530 on the side of the first conductive layer pattern 520 away from the base substrate. For example, as shown in FIG. 3C, the second conductive layer pattern 530 includes a scan signal line 531, a second electrode 533 of the capacitor C, and a reset control signal line 532.

[0071] FIG. 3D shows the second active layer pattern 540 on the side away from the base substrate of the second conductive layer pattern 530. For example, as shown in FIG. 3D, the second active layer pattern 540 includes the channel regions of the second reset transistor T1 and the threshold compensation transistor T2. For example, when an oxide semiconductor is used for the active layers of the second reset transistor T1 and the threshold compensation transistor T2, transistors using an oxide semiconductor have excellent hysteresis characteristics and low leakage current. Therefore, instead of the low-temperature polysilicon material in the transistor, an oxide semiconductor transistor may be used to form a low-temperature polysilicon-oxide (LTPO) pixel circuit, thereby reducing the leakage current and being advantageous for improving the stability of the voltage terminal of the gate of the transistor.

[0072] For example, as shown in FIGS. 3C, 3D, and 3I, the gate of the second reset transistor T1 may be the overlapping portion of the reset control signal line 532 and the second active layer pattern 540, and the gate of the threshold compensation transistor T2 may be the overlapping portion of the scan signal line 531 and the second active layer pattern 540.

[0073] FIG. 3E shows the third conductive layer 550 on the side away from the base substrate of the second active layer pattern 540. For example, as shown in FIG. 3E, the third conductive layer 550 includes a reset power signal line 554, a reset control signal line 553, a scan signal line 552, and a reset power signal line 551.

[0074] For example, as shown in FIGS. 3C to 3F and 3I, the reset control signal line 553 overlaps the channel region of the second reset transistor T1, and the second reset transistor T1 includes a top gate and a bottom gate located on both sides of the active layer. The scan signal line 552 overlaps the channel region of the threshold compensation transistor T2, and the threshold compensation transistor T2 includes a top gate and a bottom gate located on both sides of the active layer.

[0075] For example, the second reset transistor T1 and the threshold compensation transistor T2 may be N-type transistors. The drive transistor T3, the data write transistor T4, the second light emission control transistor T5, the first light emission control transistor T6, the first reset transistor T7, and the third reset transistor T8 may be P-type transistors.

[0076] FIG. 3F shows a fourth conductive layer 560 located on the side of the third conductive layer 550 away from the base substrate. For example, as shown in FIG. 3F, the fourth conductive layer 560 includes a reset power supply signal line 561, connection portions 568, 569, 563, 567, 562, 564, 565, and 566.

[0077] For example, as shown in FIGS. 2 to 3I, reset power supply signal lines 551 are connected to both ends of the connection portion 568, and the first electrode of the third reset transistor T8 is connected to the center. The connection portion 569 connects the first signal line 200 and the second electrode of the data write transistor T4. The connection portion 563 electrically connects the first electrode of the data write transistor T4 and the second electrode of the third reset transistor T8, and introduces the reset signal Vref to the N2 node. The connection portion 567 electrically connects the first electrode of the drive transistor T3 and the first electrode of the threshold compensation transistor T2. A power supply signal line 581 is connected to the center of the connection portion 562, and the second electrodes 533 of the capacitors are connected to both ends of the connection portion 562. In this way, the second electrodes 533 of the adjacent capacitors C are electrically connected while applying the power supply voltage terminal to the second electrodes 533 of the capacitor C. One end of the connection portion 564 is connected to the second electrode 533 of the capacitor C, and the other end of the connection portion 564 is connected to the first electrode of the second light emission control transistor T5. The connection portion 565 electrically connects the first electrode of the light emitting element and the second electrode of the first light emission control transistor T6. The connection portion 566 electrically connects the reset power supply signal line 554 and the first electrode of the second reset transistor T1.

[0078] FIG. 3G shows a fifth conductive layer 570 located on the side of the fourth conductive layer 560 away from the base substrate. For example, as shown in FIG. 3G, the fifth conductive layer 570 includes a connection portion 573, a connection portion 575, a power signal line 572, a connection portion 574, a second connection line 420, and a sixth connection line 460. For example, the fifth conductive layer 570 further includes a fourth connection line.

[0079] For example, as shown in FIGS. 2 to 3G, the connection portion 573 is electrically connected to the first signal line 200. For example, the first signal line 200 is electrically connected to the second connection line 420 via the connection portion 573, and transmits a first signal to the second connection line 420. For example, the first signal line 200 and the second connection line 420 may be electrically connected by adding a connection block between the connection portion 573 and the second connection line 420. The connection portion 575 is a pad, and this pad may be electrically connected to the first connection line via a via hole. At a position where an electrical connection between the first connection line and the second connection line is required, a connection block is added between the second connection line 420 and the connection portion 575, whereby the first connection line can be electrically connected to the second connection line 420 via the pad. Similarly, the third connection line may be electrically connected to the fourth connection line via a pad. For example, the connection portion 574 and the connection portion 565 are electrically connected, whereby the second pole of the first light emission control transistor T6 is electrically connected to the first electrode of the light emitting element. For example, the power signal line 572 is electrically connected to the power signal line 581.

[0080] FIG. 3H shows a sixth conductive layer 580 located on the side of the fifth conductive layer 570 away from the base substrate. For example, as shown in FIG. 3H, the sixth conductive layer 580 includes a first signal line 200, a power signal line 581, a fifth connection line 450, a connection portion 584, and a connection portion 585. For example, the sixth conductive layer 580 further includes a first connection line and a third connection line.

[0081] For example, the connection portion 584 and the connection portion 585 are electrically connected to the first electrodes of different light emitting elements.

[0082] For example, as shown in FIGS. 3G and 3H, the first signal line 200 includes an adapter pad 290. The first signal line 200 is connected to the connection portion 573 via the adapter pad 290 and is electrically connected to the second connection line. For example, the fifth connection line, the first connection line, and the third connection line all include an adapter pad 459, and each connection line is electrically connected to the connection portion 575 via the corresponding adapter pad 459.

[0083] For example, as shown in FIGS. 1 to 3H, the second signal line 300 may be located within the first conductive layer pattern 520. For example, the second signal line 300 may include at least one of a light emission control signal line 521 and a reset control signal line 522.

[0084] For example, as shown in FIGS. 1 to 3H, a plurality of second signal lines 300 are located between the plurality of first signal lines 200 and the base substrate 100, and the fourth connection line 440 is located between the plurality of first signal lines 200 and the plurality of second signal lines 300.

[0085] For example, as shown in FIG. 1, on the same side of the second region 102, all of the first connection lines 410 are located on the side of the third connection line 430 that is away from the second region 102. By providing all of the first connection lines on the side of the third connection line that is away from the second region, the length of the third connection line to which the extension line is connected to the second signal line passing through the second region can be minimized as much as possible, and further, it is advantageous for reducing the difference in load between the second signal line through which the extension line passes through the second region and the second signal line through which the extension line does not pass through the second region.

[0086] Of course, the embodiments of the present disclosure are not limited thereto, and a partial first connection line and a partial third connection line may be provided in an exchanged manner, which is advantageous for reducing the difference in load between the first signal line through which the extension line passes through the second region and the first signal line through which the extension line does not pass through the second region.

[0087] For example, as shown in FIG. 1, the partial second connection line 420 is located in the same layer as each fourth connection line 440, and among the second connection lines 420 and the fourth connection lines 440 provided in the same layer, at least one second connection line 420 is provided at an interval on the same straight line as the fourth connection line 440. For example, in the direction perpendicular to the base substrate 100, the second connection line 420 on the same straight line as the fourth connection line 440 overlaps with the third connection line 430.

[0088] For example, as shown in FIG. 1, on the same side of the second region 102, the first signal line 200 with at least one extension line passing through the second region 102 is located between at least one third connection line 430 and the second region 102. For example, on the same side of the second region 102, the first signal line 200 with at least one extension line not passing through the second region 102 is located between at least one third connection line 430 and the second region 102. For example, at least one third connection line 430 is located between the first signal line 200 with at least one extension line not passing through the second region 102 and the first signal line 200 with at least one extension line passing through the second region 102.

[0089] In some examples, as shown in FIG. 1, on the same side of the second region 102, at least one first signal line 200 among the plurality of first signal lines 200 whose extension line does not pass through the second region 102 is located on the side closer to the second region 102 of the first connection line 410.

[0090] For example, as shown in FIG. 1, at least a part of the first connection lines 410 provided on the same side of the second region 102 is provided at equal intervals. For example, at least a part of the fourth connection lines 440 provided on the same side of the second region 102 is provided at equal intervals. The fact that the first connection lines are provided at equal intervals is advantageous for reducing a significant sudden change in the load on the first signal lines connected to the first connection lines. The fact that the fourth connection lines are provided at equal intervals is advantageous for reducing a significant sudden change in the load on the second signal lines connected to the fourth connection lines. In some examples, as shown in FIG. 1, the ratio of the distance between one first connection line 410 and one third connection line 430 that are close to each other among the plurality of first connection lines 410 and the plurality of third connection lines 430 to the distance between two adjacent third connection lines 430 is 0.8 to 1.2. For example, the ratio of the distance between one first connection line 410 and one third connection line 430 that are close to each other to the distance between two adjacent third connection lines 430 is 0.9 to 1.1. For example, the distance between one first connection line 410 and one third connection line 430 that are close to each other is equal to the distance between two adjacent third connection lines 430.

[0091] By reducing the distance between one first connection line and one third connection line that are closest to the second region, the length of the second connection line connected to the first connection line is shortened. Furthermore, the difference between the load on the first signal line connected to the first connection line and the load on the first signal line that is closest to the second region and whose extension line does not pass through the second region is reduced, which is advantageous for avoiding the unevenness phenomenon during the display of the display substrate.

[0092] In some examples, as shown in FIG. 1, in the first region 101, at least a part of the first connection line 410 and at least a part of the third connection line 430 are located in the same layer, and at least a part of the second connection line 420 and at least a part of the fourth connection line 440 are located in the same layer.

[0093] For example, the orthographic projection of the straight line extending along the first direction of each first connection line 410 overlaps with the orthographic projection of the straight line extending along the first direction of each third connection line 430, and the orthographic projection of the straight line extending along the second direction of at least one second connection line 420 does not overlap with the orthographic projection of the straight line of at least one fourth connection line 440 in this straight line.

[0094] In an embodiment of the present disclosure, the first connection line and the third connection line are arranged along the second direction, so that interference between the first connection line and the third connection line is avoided. Since the partial second connection line and the fourth connection line are provided at intervals in the second direction, a part of the second connection line can be interposed between the third connection lines, and such a second connection line may be electrically connected to the first signal line located on the side closer to the second region of the third connection line, thereby minimizing the length of the second connection line as much as possible. For example, the parasitic capacitance of the second connection line is the difference in load between the first signal line through which the extension line passes through the second region and the normal signal line, where the closest extension line to the normal signal line (also referred to as the normal signal line) does not pass through the second region. In this way, the difference in load between the first signal line electrically connected to the second connection line and the normal signal line is further reduced.

[0095] In some examples, as shown in FIG. 1, among the plurality of second signal lines 300, the second signal line 300 closest to the second region 102 among the partial second signal lines 300 whose extension lines do not pass through the second region 102 is located between the fourth connection line 440 closest to the second region 102 and the fourth connection line 440 adjacent thereto. By configuring the fourth connection line closest to the second region to be close to the second signal line closest to the second region and whose extension line does not pass through the second region, the length of the third connection line connected to the fourth connection line closest to the second region is reduced, and further, the difference in load between the second signal line electrically connected to the fourth connection line and the second signal line whose extension line does not pass through the second region is reduced, which is advantageous for reducing display unevenness.

[0096] In some examples, as shown in FIG. 1, on the same side of the second region 102, among the plurality of second connection lines 420, the first set of connection lines 4201 is located on the side closer to the second region 102 of at least one fourth connection line 440, and the second set of connection lines 4202 among the plurality of second connection lines 420 is located on the side farther from the second region 102 of this at least one fourth connection line 440. For example, the number of second connection lines 420 included in the first set of connection lines 4201 may be less than the number of second connection lines 420 included in the second set of connection lines 4202. For example, a plurality of fourth connection lines 440 are provided between the first set of connection lines 4201 and the second set of connection lines 4202.

[0097] In the display device according to the embodiments of the present disclosure, by making the second connection line include two sets of connection lines located on both sides of the fourth connection line, while avoiding interference caused by the fourth connection line and the second connection line being provided in the same layer, it is possible to avoid display unevenness caused by a sudden change in load between the first signal line and the second signal line.

[0098] In some examples, as shown in FIG. 1, along the direction perpendicular to the base substrate 100, the first set of connection lines 4201 overlaps with the third connection line 430, and the second set of connection lines 4202 does not overlap with the third connection line 430. For example, as shown in FIG. 1, in the direction perpendicular to the base substrate 100, at least one third connection line 430 does not overlap with the second connection line 420. For example, each connection line 420 among the first set of connection lines 4201 overlaps with at least one third connection line 430.

[0099] In some examples, as shown in FIG. 1, on the same side of the second region 102, at least one first signal line 200 connected to the second set of connection lines 4202 overlaps with each fourth connection line 440 in the direction perpendicular to the base substrate 100. For example, on the same side of the second region 102, each first signal line 200 connected to the second set of connection lines 4202 overlaps with all of the fourth connection lines 440 in the direction perpendicular to the base substrate 100.

[0100] Since the first signal line and the fourth connection line connected to the second set of connection lines overlap, in order to avoid interference between the positions of the second connection line and the fourth connection line among the second set of connection lines, in the display substrate according to the embodiment of the present disclosure, the second set of connection lines are provided on the side away from the second region of the fourth connection line.

[0101] For example, as shown in FIG. 1, on the same side of the center line extending along the second direction of the second region 102, the second connection lines 420 among the first set of connection lines 4201 are provided at equal intervals. For example, on the same side of the center line extending along the second direction of the second region 102, the second connection lines 420 among the second set of connection lines 4202 are provided at equal intervals. For example, the distance between two adjacent second connection lines 420 among the first set of connection lines 4201 may be equal to the distance between two adjacent second connection lines 420 among the second set of connection lines 4202.

[0102] For example, the distance between the second connection line 420 closest to the fourth connection line 440 among the second set of connection lines 4202 and the fourth connection line 440 may be equal to the distance between two adjacent second connection lines 420 among the second set of connection lines 4202.

[0103] In some examples, as shown in FIG. 1, when the distance between the second connection line 420 closest to the second set of connection lines 4202 among the first set of connection lines 4201 and the second connection line 420 closest to the first set of connection lines 4201 among the second set of connection lines 4202 is the first distance S1, and the distance between two adjacent second connection lines 420 among the second set of connection lines 4202 is the second distance S2, the ratio of the first distance S1 to the second distance S2 is greater than 2. For example, the ratio of the first distance S1 to the second distance S2 is greater than 3. For example, the ratio of the first distance S1 to the second distance S2 is greater than 4. For example, the ratio of the first distance S1 to the second distance S2 is greater than 5. For example, the ratio of the first distance S1 to the second distance S2 is greater than 6. For example, the ratio of the first distance S1 to the second distance S2 is greater than 7. For example, the ratio of the first distance S1 to the second distance S2 is greater than 8. For example, the ratio of the first distance S1 to the second distance S2 is greater than 9. For example, the ratio of the first distance S1 to the second distance S2 is greater than 10.

[0104] FIG. 4 is a schematic diagram of a partial planar structure according to another example of an embodiment of the present disclosure.

[0105] FIG. 5 is a schematic diagram of a part of the film layer in the region E1 shown in FIG. 4, FIGS. 6 and 7 are schematic diagrams of the two-layer conductive layer at the position shown in FIG. 5, FIG. 8 is a schematic diagram of a part of the film layer in the region E2 shown in FIG. 4, and FIGS. 9 to 10 are schematic diagrams of the two-layer conductive layer at the position shown in FIG. 8. The film layer structure in the regions shown in FIGS. 5 to 10 may have the same characteristics as the film layer structure in the corresponding regions of the display substrate shown in FIG. 1.

[0106] For example, as shown in FIGS. 4 to 10, the first signal line 200 includes the first signal lines 201-1 and 201-2 whose extension lines pass through the second region 102, and the first signal lines 202-1 and 202-2 whose extension lines do not pass through the second region 102. The first signal line 201-1 is one first signal line whose extension line passes through the second region 102 and is closest to the first signal line whose extension line does not pass through the second region 102. The first signal line 202-1 is one first signal line whose extension line does not pass through the second region 102 and is closest to the first signal line whose extension line passes through the second region 102.

[0107] For example, as shown in FIGS. 4 to 10, the second connection line 420 includes the second connection line 420-2 electrically connected to the first signal line 201-2 and the second connection line 420-1 electrically connected to the first signal line 201-1. For example, the second connection line 420-1 is electrically connected to the first signal line 201-1 via the connection portion 0421, and the second connection line 420-2 is electrically connected to the first signal line 201-2 via the connection portion 0422.

[0108] For example, as shown in FIGS. 4 to 10, the first connection line 410 includes the first connection line 410-1 connected to the second connection line 420-1 and the first connection line 410-2 electrically connected to the second connection line 420-2. For example, the second connection line 420-1 is electrically connected to the first connection line 410-1 via the connection portion 0423, and the second connection line 420-2 is electrically connected to the first connection line 410-2 via the connection portion 0425.

[0109] For example, as shown in FIGS. 4 to 10, a first signal line 210 (i.e., the first signal line 201-1) located on one side of the second region 102 transmits a first signal to a first signal line 220 located on the other side of the second region 102 via a second connection line 420-1 and a first connection line 410-1. A first signal line 201-2 located on one side of the second region 102 transmits a first signal to a first signal line 220 located on the other side of the second region 102 via a second connection line 420-2 and a first connection line 410-2. The black dotted arrows in FIGS. 5 and 8 exemplarily show the transmission path of the first signal.

[0110] In some examples, as shown in FIGS. 9 and 10, the display substrate further includes a plurality of fifth connection lines 450 extending along a first direction and a plurality of sixth connection lines 460 extending along a second direction.

[0111] In some examples, as shown in FIGS. 9 and 10, the plurality of fifth connection lines 450 further includes at least a part of the fifth connection lines 450 located in the same layer as the first connection line 410, and among at least a part of the above-mentioned fifth connection lines 450, the fifth connection lines 450 that are in the same straight line as the first connection line 410 are provided at intervals from the first connection line 410. For example, an interval 0426 is provided between the first connection line 410-1 and the fifth connection line 450.

[0112] For example, two connection lines provided at intervals on the same straight line may be two different connection lines obtained by dividing the same connection line.

[0113] In some examples, as shown in FIGS. 9 and 10, the plurality of sixth connection lines 460 includes at least a part of the sixth connection lines 460 located in the same layer as the second connection line 420, and among at least a part of the above-mentioned sixth connection lines 460, the sixth connection lines 460 that are in the same straight line as the second connection line 420 are provided at intervals from the second connection line 420. For example, an interval 0424 is provided between the second connection line 420-1 and the sixth connection line 460.

[0114] In some examples, as shown in FIG. 1, a plurality of fifth connection lines 450 include at least a part of the fifth connection lines 450 located in the same layer as the third connection line 430, and among at least a part of the fifth connection lines 450, the fifth connection lines 450 that are in the same straight line as the third connection line 430 are provided at intervals from the third connection line 430.

[0115] In some examples, as shown in FIG. 1, a plurality of sixth connection lines 460 include at least a part of the sixth connection lines 460 located in the same layer as the fourth connection line 440, and among at least a part of the sixth connection lines 460, the sixth connection lines 460 that are in the same straight line as the fourth connection line 440 are provided at intervals from the fourth connection line 440.

[0116] In some examples, as shown in FIG. 1, the display substrate further includes a peripheral region 103, and the peripheral region 103 surrounds a display region, for example, the first region 101. For example, the peripheral region 103 is a non-display region, the display region is a display region, and for example, the first region 101 is a display region.

[0117] In some examples, as shown in FIGS. 1, 17, and 18, the display substrate further includes a third signal line 600 located in the peripheral region 103, and at least one of the fifth connection line 450 and the sixth connection line 460 is electrically connected to the third signal line 600. For example, the third signal line 600 may be an annular signal line that surrounds the display region for one week. For example, the third signal line 600 is configured to transmit a VSS signal. For example, the third signal line 600 is configured to be electrically connected to the second electrode of the light-emitting element, for example, the cathode.

[0118] For example, both the fifth connection line 450 and the sixth connection line 460 are electrically connected to the third signal line 600.

[0119] In the embodiments of the present disclosure, by providing a plurality of fifth connection lines and a plurality of sixth connection lines, it is advantageous to improve the uniformity at the position of the connection lines and reduce display unevenness. Further, by electrically connecting the fifth connection line and the sixth connection line to the third signal line, it is advantageous to reduce the load of the third signal line.

[0120] In some examples, as shown in FIGS. 5 to 10, at least one first connection line 410 and at least one third connection line 430 are both located in the same layer as a plurality of first signal lines 200. For example, each first connection line 410 is provided in the same layer as the first signal line 200. For example, each third connection line 430 is provided in the same layer as the first signal line 200.

[0121] In some examples, as shown in FIGS. 5 to 10, at least one of the interval portions between the fifth connection line 450 and the first connection line 410 and the interval portion between the fifth connection line 450 and the third connection line 430 overlaps with the film layer where the fourth connection line 440 exists, for example, overlaps with the structure of the fifth conductive layer 570. For example, at least one of the interval portions between the sixth connection line 460 and the second connection line 420 and the interval portion between the sixth connection line 460 and the fourth connection line 440 overlaps with the film layer where the first connection line 410 exists, for example, overlaps with the structure of the sixth conductive layer 580.

[0122] For example, as shown in FIGS. 5 to 10, the interval 0424 between the second connection line 420 and the sixth connection line 460 overlaps with the first signal line 200. For example, the interval 0426 between the first connection line 410 and the fifth connection line 450 overlaps with the second connection line 420.

[0123] In the display substrate according to the embodiments of the present disclosure, by blocking the interval between two connection lines on the same straight line with a connection line in another layer or a signal line in another layer, it is advantageous to reduce display unevenness, such as breathing screen unevenness.

[0124] In some examples, as shown in FIG. 8, on both sides of at least one first connection line 410, two first signal lines 200 adjacent to the first connection line 410 are provided, and the ratio of the minimum distance between the two first signal lines 200 and the first connection line 410 is 0.9 to 1.1. For example, the minimum distances between the two first signal lines 200 and the first connection line 410 are the same.

[0125] For example, as shown in FIG. 8, a plurality of first signal lines 200 may be divided into a plurality of first signal line pairs 200. Each first signal line pair 200 is located between two adjacent sub-pixels, for example, between two light-emitting elements, and one first connection line 410 is provided between at least one pair of first signal lines 200.

[0126] In some examples, as shown in FIG. 1, on both sides of at least one third connection line 430, two first signal lines 200 adjacent to the third connection line 430 are provided, and the ratio of the minimum distance between the two first signal lines 200 and the third connection line 430 is 0.9 to 1.1. For example, the minimum distances between the two first signal lines 200 and the third connection line 430 are the same.

[0127] For example, one third connection line 430 is provided between at least one pair of first signal lines 200.

[0128] For example, as shown in FIG. 10, on both sides of at least one fifth connection line 450, two first signal lines 200 adjacent to the fifth connection line 450 are provided, and the ratio of the minimum distance between the two first signal lines 200 and the fifth connection line 450 is 0.9 to 1.1. For example, the minimum distances between the two first signal lines 200 and the fifth connection line 450 are the same.

[0129] In the display substrate according to the embodiment of the present disclosure, the first connection line and the first signal line are provided in a 2-in-1 form, the third connection line and the first signal line are provided in a 2-in-1 form, and the fifth connection line and the first signal line are provided in a 2-in-1 form.

[0130] Of course, the embodiments of the present disclosure are not limited thereto. It may be located between at least one pair of first signal lines, and for example, two first connection lines may be further provided in a 1-in-1 form.

[0131] FIG. 11 is a schematic diagram of a part of the film layer in the region E3 shown in FIG. 4, and FIG. 12 is a schematic diagram of a part of the film layer in the region E4 shown in FIG. 4. FIG. 13 is a schematic diagram of a part of the film layer including the region E1 shown in FIG. 4, and FIGS. 14 and 15 are schematic diagrams of two conductive layers at the position shown in FIG. 13.

[0132] In some examples, as shown in FIGS. 4 and 11, the first connection line 410 connected to one of the second connection lines 420 closest to the second set of connection lines 4202 among the first set of connection lines 4201 includes two portions 411 and 412 respectively located on both sides in the first direction of one of the second connection lines 420. For example, the portion 411 of this first connection line 410 transmits a first signal to the first signal line 200 located on the other side of the second region 102, and the portion 412 of this first connection line 410 eliminates the difference between the parasitic capacitance at this first connection line 410 and the parasitic capacitance at one of the second connection lines 420 closest to the first set of connection lines 4201 among the second set of connection lines 4202. For example, the portion 412 may function as a load compensation portion. For example, the portion 411 of this first connection line 410 may be regarded as a portion extending in the forward direction, and the portion 412 may be regarded as a portion extending in the reverse direction.

[0133] When the distance between two adjacent second connection lines among the first set of connection lines and the second set of connection lines respectively is greater than the distance between two adjacent second connection lines among the first set of connection lines (or the second set of connection lines), the length of the first connection line connected to one of the second connection lines closest to the second set of connection lines among the first set of connection lines is increased. For example, the first connection line includes a portion extending in the forward direction for transmitting a first signal line and another portion extending in a direction opposite to this forward direction, thereby reducing a sudden change in the load of the second connection line among the two sets of connection lines, reducing display unevenness, and improving the display effect.

[0134] In some examples, as shown in FIGS. 4, 11, and 12, the first connection line 410 connected to the second connection line 420-11, which is the one of the first set of connection lines 4201 closest to the second set of connection lines 4202, extends to the position of the second connection line 420-12, which is the one of the second set of connection lines 4202 closest to the first set of connection lines 4201. For example, the portion 412 extending in the reverse direction of the first connection line 410 connected to the second connection line 420-11 extends to the position of the second connection line 420-12.

[0135] In the embodiments of the present disclosure, the portion extending in the reverse direction of the first connection line connected to the second connection line, which is the one of the first set of connection lines closest to the second set of connection lines, extends to the position of the second connection line, which is the one of the second set of connection lines closest to the first set of connection lines, thereby minimizing the difference in load at two second connection lines located respectively on the first set of connection lines and the second set of connection lines and close to each other, and avoiding a large jump in load due to the distance between the two sets of connection lines being too large.

[0136] For example, as shown in FIGS. 4, 11, and 12, the distance between the portion 412 extending in the reverse direction of the first connection line 410 connected to the second connection line 420-11 and the fifth connection line 450 overlaps with the second connection line 420-12.

[0137] In some examples, as shown in FIGS. 4, 11 to 15, each of the N first connection lines 410 respectively connected to the N second connection lines 420, which are the ones of the first set of connection lines 4201 closest to the second set of connection lines 4202, includes two portions 411 and 412 respectively located on both sides in the first direction of the second connection line 420 to which it is connected. And along the direction approaching the second region 102, among the N first connection lines 410, the lengths of both of the two portions 411 and 412 located on both sides in the first direction of the second connection line 420 to which it is connected gradually decrease. N is a positive integer of 1 or more, and the number of the second connection lines 420 of the first set of connection lines 4101 on the center side of the second region 102 is N or more.

[0138] For example, as shown in FIGS. 4, 13 to 15, among the first set of connection lines 4201, the second connection line 420 closest to the second set of connection lines 4202 includes the second connection line 420-1, the second connection line 420-2, and the second connection line 420-3. The first connection line 410 includes the first connection line 410-1 connected to the second connection line 420-1, the first connection line 410-2 connected to the second connection line 420-2, and the first connection line 410-3 connected to the second connection line 420-3.

[0139] For example, as shown in FIGS. 4, 13 to 15, along the direction from the second set of connection lines 4202 to the first set of connection lines 4201, the second connection line 420-3, the second connection line 420-2, and the second connection line 420-1 are sequentially arranged. For example, the second connection line 420-3 is closer to the second set of connection lines 4202 than the second connection line 420-2.

[0140] For example, as shown in FIGS. 4, 13 to 15, the lengths of the portion 412-3 of the first connection line 410-3, the portion 412-2 of the first connection line 410-2, and the portion 412-1 of the first connection line 410-1 gradually decrease. For example, the length of the portion 412-3 of the first connection line 410-3 is greater than the length of the portion 412-2 of the first connection line 410-2.

[0141] In the display substrate according to the embodiments of the present disclosure, adjusting the length of the portion extending in the reverse direction of the first connection line according to the relationship between the distance between each second connection line among the first set of connection lines and the second set of connection lines can reduce the sudden change in the load of the second connection line among the second set of connection lines and the second connection line among the first set of connection lines, while reducing the difference in load between adjacent second connection lines among the first set of connection lines.

[0142] For example, as shown in FIGS. 4, 13 to 15, among the plurality of first connection lines 410 connected to at least a part of the second connection line 420 among the first set of connection lines 4201, the difference in the length of the portions extending in the reverse direction of any two adjacent first connection lines 410 is within a predetermined range. For example, this difference in length may be the size in the first direction of 1 to 5 sub-pixels, or may be the size in the first direction of 2 to 4 sub-pixels.

[0143] For example, as shown in FIG. 4, the first connection line 410 connected to the second connection line 420 among the first set of connection lines 4201 may include two portions 412 extending in the reverse direction and a portion 411 extending in the forward direction located between the two portions 412 extending in the reverse direction. For example, the lengths of the two portions 412 extending in the reverse direction included in each first connection line 410 are equal.

[0144] FIG. 16 is a schematic diagram of a part of the film layer in the region E5 shown in FIG. 1, FIG. 17 is a schematic diagram of a part of the film layer in the region E6 shown in FIG. 16, and FIG. 18 is a schematic diagram of a part of the film layer in the region E7 shown in FIG. 16.

[0145] In some examples, as shown in FIGS. 1, 11, 12, and 16 to 18, the plurality of second sets of connection lines 4202 include the second connection line 420 located in the first region 101 and the second connection line 420 located in the peripheral region 103. The second connection line 420 located in the first region 102 is provided in a different layer from the first connection line 410, and the second connection line 420 located in the peripheral region 103 is provided in the same layer as the first connection line 410.

[0146] For example, as shown in FIGS. 1, 16 to 18, one first connection line 410 is electrically connected to two second connection lines 420. One of the two second connection lines 420 located within the first region 101 is provided in a different layer from the first connection line 410, and one second connection line 420 located within the peripheral region 103 is integrally provided in the same layer as the first connection line 410.

[0147] In some examples, as shown in FIGS. 1, 16 to 18, the second connection line 420 located in the peripheral region 103 is provided in the same layer as the first signal line 200. For example, the second sub-signal line 220 located in the second region 102 and close to the peripheral region 103 is integrally provided in the same layer as the second connection line 420 connected thereto.

[0148] For example, FIGS. 17 and 18 schematically show that the fifth connection line 450 is electrically connected to the third signal line 600 located in the peripheral region 103. For example, the fifth connection line 450 in the E6 region is directly electrically connected to the third signal line 600, and the fifth connection line 450 in the E7 region is electrically connected to the third signal line 600 via an adapter line 0450 provided on the same layer as the second connection line provided in the first region 101.

[0149] For example, as shown in FIG. 1, both the third connection line 430 and the fourth connection line 440 are located in the first region 101.

[0150] For example, as shown in FIG. 1, each second connection line 420 included in the first set of connection lines 4201 and the first connection line 410 connected to each second connection line 420 of the first set of connection lines 4201 are all located in the first region 101.

[0151] For example, the display substrate further includes a plurality of first light-emitting elements, a plurality of first pixel circuits, and a plurality of second pixel circuits located in the first region 101, and a plurality of second light-emitting elements located in the second region 102. The plurality of first pixel circuits are electrically connected to the plurality of first light-emitting elements in a one-to-one correspondence, and the plurality of second pixel circuits are electrically connected to the plurality of second light-emitting elements in a one-to-one correspondence. For example, the second region 102 may be a region where a camera is disposed, and the second pixel circuit that drives the second light-emitting element in the second region 102 is located in the first region 101. In this way, the light transmittance of the second region 102 can be improved, that is, the light transmittance of the second region 102 can be improved by providing the light-emitting element and the pixel circuit separately.

[0152] FIG. 19 is a schematic diagram of a part of the structure of the region E8 shown in FIG. 4, FIG. 20 is a schematic diagram of a part of the structure of the region E9 shown in FIG. 19, and FIGS. 21 to 25 are schematic diagrams of each film layer at the position shown in FIG. 20. The E9 region is a small region within the E8 region.

[0153] For example, as shown in FIGS. 2 to 4 and FIGS. 19 to 25, the second signal line 300 includes a light emission control signal line 521. For example, the light emission control signal line 521 employs single-sided driving.

[0154] For example, as shown in FIGS. 2 to 4 and FIGS. 19 to 25, the light emission control signal line 521 is electrically connected to a fourth connection line 440-11 in a fifth conductive layer 570 via an adapter line 5611. The fourth connection line 440-11 is electrically connected to a third connection line 430-1 in a sixth conductive layer 580 by a connection portion 575. The third connection line 430-1 is electrically connected to a fourth connection line 440-1 by the connection portion 575. Thereby, a third sub-signal line 310 (light emission control signal line 521) located on the left side of the second region 102 (the direction opposite to the arrow in the Y direction shown in the figure is defined as left) and a fourth sub-signal line 320 (light emission control signal line 521) located on the right side of the second region 102 are electrically connected.

[0155] For example, as shown in FIGS. 2 to 4 and FIGS. 19 to 25, among the plurality of light emission control signal lines 521, the light emission control signal line 521 that is closest to the second region 102 among the light emission control signal lines 521 whose extension lines do not pass through the second region 102 is located between the fourth connection line 440-1 that is closest to the second region 102 and the adjacent fourth connection line 440-2.

[0156] For example, as shown in FIGS. 2 to 4 and FIGS. 19 to 25, the second signal line 300 includes a reset control signal line 522. For example, the reset control signal line 522 employs single-sided driving.

[0157] For example, as shown in FIGS. 2 to 4 and FIGS. 19 to 25, the reset control signal line 522 is electrically connected to the fourth connection line 440-12 in the fifth conductive layer 570 via an adapter line in the fourth conductive layer 560. The fourth connection line 440-12 is electrically connected to the third connection line 430-2 in the sixth conductive layer 580 by a connection portion 575. The third connection line 430-2 is electrically connected to the fourth connection line 440-2 by the connection portion 575. Thereby, the third sub-signal line 310 (reset control signal line 522) located on the left side of the second region 102 and the fourth sub-signal line 320 (reset control signal line 522) located on the right side of the second region 102 are electrically connected.

[0158] In the display substrate according to the embodiment of the present disclosure, the influence of the parasitic capacitance on the process of writing a signal to the light emission control transistor is small, and the influence of the parasitic capacitance on the signals of the reset transistors T7 and T8 is small. For at least one of the reset control signal line to which the reset transistors T7 and T8 are electrically connected and the light emission control signal line, by a configuration in which two portions located on both sides of the second region are electrically connected by a connection line extending along the first direction and a connection line extending along the second direction, while minimizing the influence on the operation performance of the pixel circuit, the wiring space around the second region is reduced and the area of the display region is increased.

[0159] For example, since the scanning signal line 523 employs double-sided driving, the scanning signal lines 523 located on both sides of the second region may be separated.

[0160] For example, as shown in FIGS. 2 to 4 and FIGS. 19 to 25, the scanning signal line 531 electrically connected to the threshold compensation transistor T2 employs single-sided driving. For example, the scanning signal line 531 located on one side of the second region 102 is electrically connected to the scanning signal line 531 located on the other side of the second region 102 via a connection line 525 in the first conductive layer 520 and / or a connection line in the fourth conductive layer 560.

[0161] In the display substrate according to an embodiment of the present disclosure, for the scanning signal line electrically connected to the threshold compensation transistor T2, instead of electrically connecting two portions located on both sides of the second region by a connection line extending along the first direction and a connection line extending along the second direction, the two portions located on both sides of the second region are electrically connected by surrounding and coiling the edge of the second region, and in this way, the parasitic capacitance generated in the scanning signal line electrically connected to the threshold compensation transistor T2 is reduced.

[0162] For example, as shown in FIGS. 2 to 4 and FIGS. 19 to 25, the reset control signal line 532 electrically connected to the second reset transistor T1 employs single-sided driving. For example, the reset control signal line 532 located on one side of the second region 102 is electrically connected to the reset control signal line 532 located on the other side of the second region 102 via a connection line in the fourth conductive layer 560, or the reset control signal line 532 located on one side of the second region 102 is directly wired to the other side of the second region 102 at the edge of the second region 102.

[0163] In the display substrate according to an embodiment of the present disclosure, for the reset control signal line electrically connected to the second reset transistor T1, instead of electrically connecting two portions located on both sides of the second region by a connection line extending along the first direction and a connection line extending along the second direction, the two portions located on both sides of the second region are electrically connected by surrounding and coiling the edge of the second region, and in this way, the parasitic capacitance generated in the reset control signal line electrically connected to the second reset transistor T1 is reduced.

[0164] In the pixel circuit according to an embodiment of the present disclosure, a first light emission control transistor electrically connected to a light emission control signal line, a second light emission control transistor, and a first reset transistor and a third reset transistor electrically connected to a reset control signal line are all P-type transistors, and a threshold compensation transistor and a second reset transistor are both N-type transistors. Compared with N-type transistors, in P-type transistors, since the influence due to the jump of the voltage terminal of the gate signal is small, for all or part of the corresponding gate control lines of the P-type transistors, connection lines extending along a first direction and connection lines extending along a second direction (that is, the FIP connection method) are used to electrically connect two portions located on both sides of a second region, thereby reducing the area of the non-display region around the second region and realizing narrow bezeling. Further, the above-mentioned coiling is used for a control signal line electrically connected to the gates of the threshold compensation transistor and the second reset transistor as N-type transistors.

[0165] Of course, the embodiments of the present disclosure are not limited thereto. All transistors in the pixel circuit are low-temperature polysilicon transistors (LTPS). For example, when all transistors are P-type transistors, for some or all of the gate control signal lines electrically connected to the gates of all P-type transistors, the connection lines extending along the first direction and the connection lines extending along the second direction (that is, the FIP connection method) can be used to electrically connect two portions located on both sides of the second region, thereby reducing the area of the non-display region around the second region and realizing narrow bezeling.

[0166] Optionally, according to an embodiment of the present disclosure, the display substrate may further include a light emitting element and a pixel circuit located on the base substrate. The pixel circuit and the light emitting element are electrically connected. The pixel circuit includes at least one N-type thin film transistor and at least one P-type thin film transistor. The second signal line includes a signal line connected to the gate of at least one of the P-type thin film transistors.

[0167] Optionally, according to an embodiment of the present disclosure, the display substrate further includes a light-emitting element and a pixel circuit located on the base substrate, the pixel circuit and the light-emitting element are electrically connected, the pixel circuit includes at least one oxide thin-film transistor and at least one low-temperature polysilicon thin-film transistor, and the second signal line includes a signal line connected to the gate of at least one of the low-temperature polysilicon thin-film transistors.

[0168] Another embodiment of the present disclosure provides a display device including any of the above display substrates.

[0169] For example, the display device may be a QHD (Quad High Definition) display device, and QHD refers to a resolution four times that of a full HD screen. For example, the display device may be an FHD (Full High Definition) display device, and FHD refers to full HD.

[0170] For example, the display device according to an embodiment of the present disclosure may be an organic light-emitting diode display device, such as an active-matrix organic light-emitting diode (AMOLED) display device.

[0171] For example, the display device may further include a cover located on the display side of the display substrate. For example, the display device may further include a functional member located on the side of the base substrate away from the light-emitting element, and the functional member faces the second region. For example, the functional member includes at least one of a camera module (for example, a front camera module), a 3D structured light module (for example, a 3D structured light sensor), a time-of-flight 3D imaging module (for example, a time-of-flight sensor), an infrared detection module (for example, an infrared detection sensor), and the like.

[0172] The display device according to an embodiment of the present disclosure electrically connects signal lines located on both sides of a second region via a first connection line, a second connection line, a third connection line, and a fourth connection line. The first connection line is located on the side away from the second region of the third connection line, and the second connection line and the third connection line overlap, thereby reducing the wiring space around the second region, increasing the area of the display region, and reducing a sudden change in the load between the first signal line and the second signal line.

[0173] For example, this display device includes any product or component having a display function such as a mobile phone, a tablet computer, a notebook computer, a navigator, etc., and the embodiments of the present invention are not limited thereto.

[0174] It is necessary to explain the following points. (1) The drawings of the embodiments of the present disclosure only include the structures related to the embodiments of the present disclosure, and other structures can refer to the common design. (2) The features of the same and different embodiments of the present disclosure can be combined with each other without contradiction. The above description is only an exemplary embodiment of the present disclosure and is not used to limit the protection scope of the present disclosure. The protection scope of the present disclosure is determined by the appended claims.

Description of Reference Numerals

[0175] 101 First Region 102 Second Region 200 First Signal Line 300 Second Signal Line 410 First Connection Line 420 Second Connection Line 430 Third Connection Line

Claims

1. A display substrate, comprising: a base substrate including a first region and a second region, wherein the first region is located around the second region; a plurality of first signal lines located on the base substrate and not passing through the second region; a plurality of second signal lines located in a layer different from the plurality of first signal lines and not passing through the second region; at least a part of the first signal lines extends along a first direction, at least a part of the second signal lines extends along a second direction, and the first direction intersects the second direction; the plurality of first signal lines include partial first signal lines whose extension lines pass through the second region, and each of the first signal lines among the partial first signal lines includes a first sub-signal line and a second sub-signal line located on both sides of the second region. The first sub-signal line and the second sub-signal line are electrically connected via a first connection line extending along the first direction and a second connection line extending along the second direction, and the partial first signal lines are electrically connected to a plurality of first connection lines and a plurality of second connection lines; the plurality of second signal lines include partial second signal lines whose extension lines pass through the second region, and each of the second signal lines among the partial second signal lines includes a third sub-signal line and a fourth sub-signal line located on both sides of the second region. The third sub-signal line and the fourth sub-signal line are electrically connected via a third connection line extending along the first direction and a fourth connection line extending along the second direction, and the partial second signal lines are electrically connected to a plurality of third connection lines and a plurality of fourth connection lines; in a direction perpendicular to the base substrate, at least one second connection line and at least one third connection line overlap, and on the same side of the second region, at least one first connection line is located on a side away from the second region of at least one third connection line. The display substrate.

2. The display substrate according to claim 1, wherein the plurality of first signal lines include data lines, and the plurality of second signal lines include at least emission control signal lines.

3. The display substrate according to claim 1 or 2, wherein a minimum distance between one fourth connection line closest to the second region and an edge of the second region is less than a minimum distance between one first connection line closest to the second region and the edge of the second region.

4. On the same side of the second region, among the plurality of second connection lines, a first set of connection lines is located on the side closer to the second region of at least one fourth connection line, and a second set of connection lines among the plurality of second connection lines is located on the side away from the second region of the at least one fourth connection line. The display substrate according to any one of claims 1 to 3.

5. Along the direction perpendicular to the base substrate, the first set of connection lines and the third connection lines overlap, and the second set of connection lines and the third connection lines do not overlap. The display substrate according to claim 4.

6. When the distance between one second connection line closest to the second set of connection lines among the first set of connection lines and one second connection line closest to the first set of connection lines among the second set of connection lines is a first distance, and the distance between two adjacent second connection lines among the second set of connection lines is a second distance, the ratio of the first distance to the second distance is greater than 2. The display substrate according to claim 4 or 5.

7. The first connection line connected to one second connection line closest to the second set of connection lines among the first set of connection lines includes two portions respectively located on both sides of the one second connection line in the first direction. The display substrate according to claim 4.

8. The first connection line connected to the one second connection line closest to the second set of connection lines among the first set of connection lines extends to the position of one second connection line closest to the first set of connection lines among the second set of connection lines. The display substrate according to claim 7.

9. Each of the N first connection lines respectively connected to N second connection lines closest to the second set of connection lines among the first set of connection lines includes two portions respectively located on both sides of the second connection line to which it is connected in the first direction, and among the N first connection lines arranged along the direction approaching the second region, the length of the portion of the first connection line located on the side closer to the second set of connection lines of the second connection line to which the first connection line is connected gradually decreases. N is a positive integer greater than or equal to 1, and the number of the second connection lines among the first set of connection lines located on the central side of the second region is N or more. The display substrate according to claim 7 or 8.

10. Among the plurality of second signal lines, the one second signal line closest to the second region among the second signal lines whose extension line does not pass through the second region is located between the one fourth connection line closest to the second region and the fourth connection line adjacent thereto. The display substrate according to any one of claims 4 to 9.

11. On the same side of the second region, at least one first signal line among the plurality of first signal lines whose extension line does not pass through the second region is located on the side of the first connection line closer to the second region. The display substrate according to any one of claims 1 to 10.

12. The ratio between the distance between one first connection line and one third connection line that are close to each other among the plurality of first connection lines and the plurality of third connection lines and the distance between two adjacent third connection lines is 0.8 to 1.

2. The display substrate according to any one of claims 1 to 11.

13. Within the first region, at least one first connection line and at least one third connection line are located in the same layer, and at least one second connection line and at least one fourth connection line are located in the same layer. The display substrate according to any one of claims 1 to 12.

14. At least one first connection line and at least one third connection line are both located in the same layer as the plurality of first signal lines. The display substrate according to claim 13.

15. The plurality of second signal lines are located between the plurality of first signal lines and the base substrate, and the fourth connection line is located between the plurality of first signal lines and the plurality of second signal lines. The display substrate according to claim 13.

16. The first region is a display region, the first region surrounds the second region, the base substrate further includes a peripheral region surrounding the display region, the plurality of second sets of connection lines include the second connection lines located in the first region and the second connection lines located in the peripheral region, the second connection lines located in the first region are provided in a layer different from the first connection line, and the second connection lines located in the peripheral region are provided in the same layer as the first connection line. The display substrate according to any one of claims 4 to 10.

17. The second connection lines located in the peripheral region are provided in the same layer as the first signal lines. The display substrate according to claim 16.

18. At least one second connection line and at least one fourth connection line among the connection lines of the first group are provided on the same layer with a space therebetween and are on the same straight line. The display substrate according to claim 4.

19. On the same side of the second region, at least one first signal line connected to the connection lines of the second group overlaps with each fourth connection line in a direction perpendicular to the base substrate. The display substrate according to claim 4.

20. The orthographic projection of each first connection line on a straight line extending along the first direction and the orthographic projection of each third connection line on the straight line overlap, and the orthographic projection of at least one second connection line on a straight line extending along the second direction and the orthographic projection of at least one fourth connection line on the straight line do not overlap. The display substrate according to any one of claims 1 to 19.

21. Further including a light-emitting element and a pixel circuit located on the base substrate, the pixel circuit and the light-emitting element are electrically connected. The pixel circuit includes a driving transistor, a light-emitting control transistor, and a reset transistor. The gate of the light-emitting control transistor is electrically connected to the light-emitting control signal line. The first pole of the light-emitting control transistor is electrically connected to the first pole of the driving transistor. The second pole of the light-emitting control transistor is electrically connected to the light-emitting element. The gate of the reset transistor is electrically connected to the reset control signal line. One pole of the reset transistor is electrically connected to the second pole of the driving transistor, or one pole of the reset transistor is electrically connected to the second pole of the light-emitting control transistor. The second signal line includes the reset control signal line. The display substrate according to claim 2.

22. Further including a light-emitting element and a pixel circuit located on the base substrate, the pixel circuit and the light-emitting element are electrically connected. The pixel circuit includes at least one N-type thin film transistor and at least one P-type thin film transistor. The second signal line includes a signal line connected to the gate of at least one of the P-type thin film transistors. The display substrate according to claim 1.

23. Further including a light-emitting element and a pixel circuit located on the base substrate, the pixel circuit and the light-emitting element are electrically connected. The pixel circuit includes at least one oxide thin film transistor and at least one low-temperature polysilicon thin film transistor. The display substrate according to claim 1, wherein the second signal line includes a signal line connected to the gate of at least one of the low-temperature polysilicon thin film transistors.

24. The first region is a display region, the first region surrounds the second region, and the base substrate further includes a peripheral region surrounding the display region. The display substrate further includes a plurality of fifth connection lines extending along the first direction and a plurality of sixth connection lines extending along the second direction. The fifth connection line located in the same layer and on the same straight line as the first connection line is provided at an interval from the first connection line. The fifth connection line located in the same layer and on the same straight line as the third connection line is provided at an interval from the third connection line. The sixth connection line located in the same layer and on the same straight line as the second connection line is provided at an interval from the second connection line. The sixth connection line located in the same layer and on the same straight line as the fourth connection line is provided at an interval from the fourth connection line. And at least one of the fifth connection line and the sixth connection line is electrically connected to a third signal line, and the third signal line is located in the peripheral region. The display substrate according to any one of claims 1 to 23.

25. At least one of the spaced portions between the fifth connection line and the first connection line and the spaced portion between the fifth connection line and the third connection line overlaps with the film layer where the fourth connection line is present. At least one of the spaced portions between the sixth connection line and the second connection line and the spaced portion between the sixth connection line and the fourth connection line overlaps with the film layer where the first connection line is present. The display substrate according to claim 24.

26. On both sides of at least one first connection line, two first signal lines adjacent to the first connection line are provided, and the ratio of the minimum distance between the two first signal lines and the first connection line is 0.9 to 1.

1. On both sides of at least one third connection line, two first signal lines adjacent to the third connection line are provided, and the ratio of the minimum distance between the two first signal lines and the third connection line is 0.9 to 1.

1. The display substrate according to any one of claims 1 to 25.

27. A display device including the display substrate according to any one of claims 1 to 26.

Images