Fast frequency tracking control for radio frequency power amplifiers with rapidly varying plasma loads.

Abstract

A radio frequency (RF) power amplifier for a plasma processing system includes a switching transistor having a drain terminal, a source terminal, and a gate. The source terminal is connected to a reference ground potential. The RF power amplifier includes a DC power source connected to the drain terminal of the switching transistor. The RF power amplifier includes an impedance matching network connected between the drain terminal of the switching transistor and a coil of the plasma processing system. The RF power amplifier includes an electrical parameter measuring device positioned to measure an electrical parameter associated with the coil. The RF power amplifier includes a phase delay module that receives a switching feedback signal from the electrical parameter measuring device. The phase delay module applies a phase adjustment to the switching feedback signal to generate a switching control signal used to drive the gate of the switching transistor.

Description

[Background technology]

[0001] Plasma processing systems are used to fabricate semiconductor devices, e.g., chips / dies, on semiconductor wafers. In plasma processing systems, semiconductor wafers are exposed to various types of plasma to induce predetermined changes in the condition of the semiconductor wafer, such as through material deposition and / or material removal and / or material implantation and / or material modification. During plasma processing of semiconductor wafers, radio frequency (RF) power is transmitted through a process gas in a chamber and converts the process gas into a plasma when exposed to the semiconductor wafer. Reactive components of the plasma, such as radicals and ions, interact with materials on the semiconductor wafer to achieve a predetermined effect on the semiconductor wafer. In some plasma processing systems, RF power is transmitted from an antenna or coil to a processing region in the chamber through a window, e.g., an RF-transparent ceramic structure, and converts the process gas into a plasma when exposed to the semiconductor wafer. Various embodiments described herein arise in this context. Summary of the Invention

[0002] In an exemplary embodiment, an RF power amplifier for a plasma processing system is disclosed. The RF power amplifier includes a switching transistor having a drain terminal, a source terminal, and a gate. The source terminal is electrically connected to a reference ground potential. The RF power amplifier also includes a direct current (DC) power supply electrically connected to the drain terminal of the switching transistor. The RF power amplifier also includes an impedance matching network electrically connected between the drain terminal of the switching transistor and a coil of the plasma processing system. The RF power amplifier also includes an electrical parameter measuring device arranged to measure an electrical parameter associated with the coil. The RF power amplifier also includes a phase delay module having an input electrically connected to receive a switching feedback signal from the electrical parameter measuring device. The phase delay module is configured to apply a phase adjustment to the switching feedback signal to generate a switching control signal. The phase delay module has an output electrically connected to the gate of the switching transistor. The phase delay module is configured to transmit the switching control signal to the gate of the switching transistor through the output of the phase delay module.

[0003] In an exemplary embodiment, a method for zero-voltage switching of an RF power amplifier for a plasma processing system is disclosed. The method includes operating a switching transistor, a DC power supply, and an impedance matching network to generate an RF signal. The method also includes transmitting the RF signal to a coil of the plasma processing system. The method also includes measuring an electrical parameter associated with the coil. The method also includes transmitting a switching feedback signal based on the measured electrical parameter to an input of a phase delay module. The method also includes generating a switching control signal within the phase delay module by applying a phase adjustment to the switching feedback signal. The method also includes transmitting the switching control signal to a gate of the switching transistor to control operation of the switching transistor and corresponding generation of the RF signal transmitted to the coil.

[0004] Other aspects and advantages of the embodiments disclosed herein will become more apparent from the following detailed description and accompanying drawings. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a diagram illustrating an exemplary configuration of an RF power amplifier according to some embodiments.

[0006] [Figure 2] FIG. 2 is a diagram illustrating a voltage versus time plot of an exemplary oscillating square wave signal output by a switching transistor, according to some embodiments.

[0007] [Figure 3A] FIG. 3A is a diagram illustrating an example plot of the voltage at a switching transistor drain node as a function of time, according to some embodiments.

[0008] [Figure 3B]FIG. 3B illustrates an example plot of the voltage at the switching transistor drain node as a function of time in the absence of ZVS conditions, according to some embodiments.

[0009] [Figure 4] FIG. 4 is a diagram illustrating plots of impedance at a switching transistor drain node as a function of switching frequency of the switching transistor for different coil inductances, according to some embodiments.

[0010] [Figure 5] FIG. 5 illustrates an RF power amplifier that uses measured electrical parameters associated with a coil to generate a switching control signal that is sent to the gate of a switching transistor to maintain a ZVS condition, according to some embodiments.

[0011] [Figure 6] FIG. 6 illustrates an example power amp characteristic curve for various coil inductances for implementing an example frequency adjustment method to maintain ZVS conditions, along with an example theta curve, in accordance with some embodiments.

[0012] [Figure 7] FIG. 7 illustrates an exemplary configuration of a phase delay module for implementing a theta curve as shown in FIG. 6, according to some embodiments.

[0013] [Figure 8] FIG. 8 illustrates an example of a phase delay module implemented to substantially pass a switching feedback signal as a switching control signal, according to some embodiments.

[0014] [Figure 9]FIG. 9 illustrates an example of a phase delay module implemented to impart a phase shift of approximately 180° to a switching feedback signal received at the input of the phase delay module, according to some embodiments.

[0015] [Figure 10] FIG. 10 illustrates an example of a phase delay module implementing an RC circuit that imparts a fixed (and optionally adjustable) time delay to a switching feedback signal received at the input of the phase delay module, according to some embodiments.

[0016] [Figure 11] FIG. 11 illustrates an example of a phase delay module implementing a passive lead compensator, according to some embodiments.

[0017] [Figure 12] FIG. 12 illustrates an example of a phase delay module implementing an active lead-lag compensator, according to some embodiments.

[0018] [Figure 13A] FIG. 13A illustrates an example of a phase delay module implementing a lead compensator, according to some embodiments.

[0019] [Figure 13B] FIG. 13B illustrates power amplifier characteristic curves and theta curves implemented by the phase delay module of FIG. 13A for different coil inductances along with corresponding coil current responses, according to some embodiments.

[0020] [Figure 14] FIG. 14 illustrates an example of a phase delay module implementing a phase-locked loop (PLL) that applies a negative time delay to a switching feedback signal to generate a switching control signal, according to some embodiments.

[0021] [Figure 15] FIG. 15 illustrates an example of a phase delay module implementing a PLL that cancels signal propagation delay of a switching feedback signal to generate a switching control signal, according to some embodiments.

[0022] [Figure 16] FIG. 16 illustrates an example phase delay module that combines various features of the phase delay modules described with respect to FIGS. 7-15 to generate switching control signals, according to some embodiments.

[0023] [Figure 17] FIG. 17 is a flowchart of a method for zero voltage switching of an RF power amplifier for a plasma processing system, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0024] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail in order to avoid unnecessarily obscuring the present disclosure.

[0025] FIG. 1 illustrates an exemplary configuration of an RF power amplifier 100, according to some embodiments. The RF power amplifier 100 is configured to generate an RF signal and transmit the RF signal through an output 102 of the RF power amplifier 100. The output 102 of the RF power amplifier 100 is electrically connected to an input terminal 113i of a coil 113 through a connection 117. The output terminal 113o of the coil 113 is electrically connected to a reference ground potential 115 through a connection 119. The coil 113 is disposed above a window 121 of a plasma processing chamber 107. The plasma processing chamber 107 includes a substrate support structure 123 configured to support a substrate 125 undergoing plasma processing in the plasma processing chamber 107. In various embodiments, the window 121 is formed of a dielectric material, such as quartz or another similar material, allowing RF power to be transmitted from the coil 113 through the window 121 to the plasma processing chamber 107. The plasma processing chamber 107 is electrically connected to a reference ground potential 127.

[0026] RF power is transmitted through and into the plasma processing chamber 107, converting the process gas into plasma 129 within the plasma processing chamber 107 when exposed to a substrate 125 supported on a substrate support structure 123. The RF power amplifier 100 injects a high voltage and a high current into the coil 113 to drive the plasma 129. In various embodiments, the plasma 129 is used to provide controlled modification of the condition of the substrate 125, such as through material deposition and / or material removal and / or material implantation and / or material modification. In some embodiments, the plasma 129 is also generated to clean the plasma processing chamber 107. During operation of the plasma processing chamber 107, exhaust gases and byproducts from the processing of the substrate 125 are exhausted from the plasma processing chamber 107.

[0027] It should be understood that in various embodiments, operation of the plasma processing chamber 107 can include many other additional operations, such as generating a bias voltage at the level of the substrate 125 to attract charged components of the plasma 129 toward or away from the substrate 125, and / or controlling the temperature of the substrate 125, and / or applying additional RF power to one or more electrodes disposed within the substrate support structure 123 to generate additional plasma, among other additional operations. Also, in various embodiments, the plasma processing chamber 107 is operated according to a predetermined recipe that specifies a time schedule for controlling one or more of the supply of process gases to the plasma processing chamber 107, the pressure and temperature within the plasma processing chamber 107, the supply of RF power to the coil 113, the supply of a bias voltage at the level of the substrate 125, the supply of RF power to the electrodes in the substrate support structure 123, among essentially any other process parameters associated with the operation of the plasma processing chamber 107.

[0028] The RF power amplifier 100 is configured to generate an RF signal having a predetermined waveform as a function of time and deliver the generated RF signal to the coil 113. The RF power amplifier 100 includes a signal generator 109, a switching transistor 101, a direct current (DC) power supply 105, and an impedance matching network 103. The DC power supply 105 is implemented in conjunction with the switching transistor 101 to generate the RF signal used to drive the plasma 129. The switching transistor 101 has a source terminal 101s, a drain terminal 101d, and a gate 101g. The source terminal 101s is electrically connected to a reference ground potential 131. The drain terminal 101d is electrically connected to a switching transistor drain node 133, which is an electrical connection between the switching transistor 101 and the impedance matching network 103. The switching transistor drain node 133 is electrically connected to the impedance matching network 103. DC power supply 105 has a negative terminal electrically connected to reference ground potential 135 and a positive terminal 105 p electrically connected to impedance matching network 103 through connection 137 .

[0029] The impedance matching network 103 includes a first inductor 139 having an input terminal 139a electrically connected to the positive terminal 105p of the DC power supply 105 through connection 137. The first inductor 139 also has an output terminal 139b electrically connected to the switching transistor drain node 133. The impedance matching network 103 also includes a second inductor 141 having an input terminal 141a and an output terminal 141b. The input terminal 141a of the second inductor 141 is electrically connected to the switching transistor drain node 133. The impedance matching network 103 also includes a first capacitor 143 having an input terminal 143a electrically connected to the output terminal 141b of the second inductor 141. The first capacitor 143 also has an output terminal 143b electrically connected to the output 102 of the RF power amplifier 100. The impedance matching network 103 also includes a second capacitor 145 having an input terminal 145a electrically connected to the switching transistor drain node 133. The second capacitor 145 also has an output terminal 145b electrically connected to the reference ground potential 147. The impedance matching network 103 also includes a third capacitor 149 having an input terminal 149a electrically connected to both the output terminal 141b of the second inductor 141 and the input terminal 143 of the first capacitor 143. The third capacitor 149 also has an output terminal 149b electrically connected to the reference ground potential 147.

[0030] The signal generator 109 is configured to generate and output an oscillating square wave signal on an electrical connection 110 that is electrically connected to the gate 101g of the switching transistor 101. In this manner, the oscillating square wave signal output by the signal generator 109 controls the operation of the switching transistor 101. Specifically, when the oscillating square wave signal has a sufficiently high voltage level at the gate 101g, the switching transistor 101 is turned on, causing current to flow from the switching transistor drain node 133 to the reference ground potential 131. Conversely, when the oscillating square wave signal has a sufficiently low voltage level at the gate 101g, the switching transistor 101 is turned off, causing current not to flow from the switching transistor drain node 133 to the reference ground potential 131. In this manner, the switching transistor 101 functions similarly to an NMOS transistor.

[0031] FIG. 2 shows a voltage versus time plot of an exemplary oscillating square wave signal 201 output by the switching transistor 101, according to some embodiments. The oscillating square wave signal 201 has cycles 203 that include off periods 205 and on periods 207. During the off periods 205, the voltage of the oscillating square wave signal 201 is sufficiently low (V_off) at the gate 101g, turning the switching transistor 101 off and preventing current from flowing from the switching transistor drain node 133 to the reference ground potential 131. During the on periods 207, the voltage of the oscillating square wave signal 201 is sufficiently high (V_on) at the gate 101g, turning the switching transistor 101 on and allowing current to flow from the switching transistor drain node 133 to the reference ground potential 131. The frequency of the oscillating square wave signal 201 is defined as the number of cycles 203 that occur within one second. In some embodiments, the controller 111 provides a frequency input setting to the signal generator 109 via the electrical connection 112. In various embodiments, the frequency input setting is an RF value, for example, in some embodiments, the frequency input setting is about 2 MHz or about 13 MHz, or another target frequency.

[0032] 3A shows an exemplary plot of the voltage at the switching transistor drain node 133 as a function of time, according to some embodiments. When the switching transistor 101 is on, the voltage at the switching transistor drain node 133 is zero because the switching transistor 101 functions to effectively short the switching transistor drain node 133 to the reference ground potential 131. When the switching transistor 101 is turned off, the resonant behavior of the impedance matching network 103 causes the voltage at the switching transistor drain node 133 to increase and then decrease. The temporal switching behavior of the switching transistor 101 as shown in FIG. 3A represents a condition called zero-voltage switching (ZVS). Specifically, the ZVS condition exists when the voltage on the switching transistor drain node 133 resonantly drops to zero (or near zero) each time the switching transistor 101 is switched off and before the switching transistor 101 is switched on again by the oscillating square wave signal output by the signal generator 109. Maintaining a ZVS condition is desirable because current flow from switching transistor drain node 133 through switching transistor 101 (in the ON state) to reference ground potential 131 is minimized when the voltage on switching transistor drain node 133 is zero (or near zero). A ZVS condition is advantageous because it minimizes power losses in switching transistor 101 and optimizes the operating life of switching transistor 101.

[0033] 3B shows an example plot of the voltage at the switching transistor drain node 133 as a function of time when a ZVS condition does not exist, according to some embodiments. Changes in the inductance of the coil 113 (coil inductance), such as those caused by changes in the load of the plasma 129, can affect the temporal voltage behavior at the switching transistor drain node 133, potentially resulting in a loss of the ZVS condition. The coil inductance is the load inductance represented by the combination of the coil 113 and the plasma 129. For example, assume an initial situation exists in which the oscillating square wave signal output by the signal generator 109 has a frequency of 11 MHz and the plasma 129 is generated with a coil inductance of 1700 nH (nanohenries), thus a ZVS condition exists. Next, assume that a perturbation occurs in the plasma 129, such as an E-to-H transition, a change in plasma density, or other plasma change, causing the coil inductance to change from 1700 nH to 1500 nH. The perturbation condition changes the temporal voltage behavior at the switching transistor drain node 133, causing the voltage on the switching transistor drain node 133 to take longer to return to zero (or near zero) after the switching transistor 101 is switched off. However, in the perturbation condition, the oscillating square wave signal output by the signal generator 109 does not change and continues to have a frequency of 11 MHz. In this exemplary perturbation condition as illustrated in FIG. 3B, the switching transistor 101 is controlled to switch on again when the voltage on the switching transistor drain node 133 may be a high voltage rather than zero, which corresponds to a loss of the ZVS condition.

[0034] If the oscillating square wave signal output by signal generator 109 causes switching transistor 101 to turn on after switching off but before the voltage on switching transistor drain node 133 returns to zero (or near zero), a ZVS condition does not exist. As shown in FIG. 3B, if the voltage on switching transistor drain node 133 is high when switching transistor 101 turns on, significant current will flow from switching transistor drain node 133 through switching transistor 101 to reference ground potential 131. This current flow through switching transistor 101 causes significant power loss in switching transistor 101, potentially leading to overheating and failure of switching transistor 101. Therefore, if the switching frequency of switching transistor 101 in RF power amplifier 100 is not adjusted when plasma 129 is experiencing changes that cause coil inductance to change, the ZVS condition will be lost and switching transistor 101 will overheat and eventually be damaged. Therefore, to avoid overheating and the resulting damage to the hardware, it is necessary to control the switching frequency of the switching transistor 101 of the RF power amplifier 100 to maintain the ZVS condition and accordingly minimize the power loss through the switching transistor 101. In the above example, if the frequency of the oscillating square wave signal output by the signal generator 109 is adjusted from 11 MHz to 11.7 MHz according to the change in the plasma 129, and the coil inductance is reduced from 1700 nH to 1500 nH, the ZVS condition is maintained, as shown in FIG. 3A.

[0035] FIG. 4 illustrates a plot of impedance at the switching transistor drain node 133 as a function of the switching frequency of the switching transistor 101 for different coil inductances, according to some embodiments. FIG. 4 shows that as the coil inductance decreases, the plot of impedance at the switching transistor drain node 133 versus the switching frequency of the switching transistor 101 shifts toward a higher switching frequency of the switching transistor 101. Conversely, FIG. 4 also illustrates that as the coil inductance increases, the plot of impedance at the switching transistor drain node 133 versus the switching frequency of the switching transistor 101 shifts toward a lower switching frequency of the switching transistor 101. To maintain a ZVS condition, a substantially constant impedance must be maintained at the switching transistor drain node 133. Therefore, as the coil inductance increases, the switching frequency of the switching transistor 101 must be reduced to maintain a ZVS condition. Conversely, as the coil inductance decreases, the switching frequency of the switching transistor 101 must be increased to maintain a ZVS condition. Generally speaking, the smaller the coil inductance, the higher the switching frequency of the switching transistor 101 must be to maintain a ZVS condition, and vice versa.

[0036] When the RF power amplifier 100 drives the plasma 129 (inductively coupled plasma (ICP)), maintaining a ZVS condition can be difficult due to, among other reasons, the rapidly changing load impedance seen by the plasma 129 during the E-to-H transition, the RF power amplifier 100 operating in a pulsed mode, or the electronegative plasma 129 becoming unstable and rapidly pulsing the plasma 129. Also, changes in the density of the plasma 129 can change the effective inductance of the coil 113, resulting in a shift in the frequency control bandwidth over which the RF power amplifier 100 can maintain a ZVS condition. Because the time scale of changes in the density of the plasma 129 can be as fast as 10 microseconds, the frequency control bandwidth of the RF power amplifier 100 should be 100 kHz or greater to ensure reliable operation under various plasma 129 processing conditions. Microcontroller- or FPGA-based digital control solutions for the RF power amplifier 100 are often too slow and / or too costly to provide fast enough control to maintain a ZVS condition in response to such rapid changes in the plasma 129.

[0037] Disclosed herein are systems and methods for controlling the switching frequency of a switching transistor 101 in an RF power amplifier 100 under rapidly changing plasma 129 load conditions, thereby maintaining a ZVS condition. The systems and methods disclosed herein provide switching frequency control that not only maintains a ZVS condition of the RF power amplifier 100, but also achieves control speeds of less than 10 microseconds, sufficient to track essentially any plasma 129 load changes that occur during plasma processing operations on a substrate 125. The systems and methods disclosed herein achieve this performance by maintaining a constant or frequency-dependent phase angle between a reference signal (switching control signal) used by the RF power amplifier 100 and a characteristic signal (switching feedback signal) derived from the RF power amplifier 100.

[0038] 5 illustrates an RF power amplifier 100A that uses a measured electrical parameter associated with the coil 113 to generate a switching control signal that is sent to the gate 101g of the switching transistor 101 to maintain a ZVS condition, according to some embodiments. The RF power amplifier 100A is a modified version of the RF power amplifier 100. Accordingly, components within the RF power amplifier 100A that have the same reference numbers as the RF power amplifier 100 are the same components as those described with respect to the RF power amplifier 100. The RF power amplifier 100A includes an electrical parameter measuring device 503 that is connected to measure an electrical parameter associated with the coil 113. In some embodiments, the electrical parameter measuring device 503 measures the voltage (V) across the coil 113. coil In some embodiments, the electrical parameter measuring device 503 is configured to measure the current (I) across the coil 113. coil In some embodiments, the electrical parameter measured by the electrical parameter measuring device 503 is V coil and I coil In some embodiments, the electrical parameter measured by the electrical parameter measuring device 503 is substantially but indirectly related to the coil 113, e.g., one or more of current, voltage, and power are measured in an electrical circuit that is electrically correlated to the coil 113. For example, in some embodiments, the electrical parameter measuring device 503 is positioned to measure the electrical parameter, e.g., one or more of current, voltage, and power, at a location within the impedance match network 103 that is electrically correlated to the coil 113.

[0039] The RF power amplifier 100A includes a phase delay module 501 having an input 501i connected through connection 505 to receive a voltage signal corresponding to an electrical parameter associated with the coil 113 measured by an electrical parameter measuring device 503. The voltage signal received at the input of the phase delay module 501 is referred to as a switching feedback signal. In some embodiments, the switching feedback signal is a signal corresponding to the voltage (V coil In some embodiments, the switching feedback signal corresponds to the current (I coil ) The phase delay module 501 is configured to generate a switching control signal by applying a phase delay (Θ) to the switching feedback signal. The phase delay module 501 has an output 501o connected to the gate 101g of the switching transistor 101 by connection 507 and connection 110. The switching control signal is sent through the output 501o of the phase delay module 501 and through connections 507 and 110 to the gate 101g of the switching transistor 101. The switching control signal output by the phase delay module 501 is used to drive the gate 101g and accordingly control the operation of the switching transistor 101 in the RF power amplifier 100A. In this manner, the phase delay module 501 is implemented in a feedback loop to control the switching frequency (f) of the switching transistor 101.

[0040] In the RF power amplifier 100A, the signal generator 109 is used to supply an initial oscillating square wave signal to the gate 101g of the switching transistor 101 to initiate the switching operation of the switching transistor 101. Then, when the switching control signal output by the phase delay module 501 reaches an equilibrium condition corresponding to a ZVS condition, the signal generator 109 is turned off (or disconnected from connection 110), so that the operation of the switching transistor 101 is controlled exclusively by the switching control signal output by the phase delay module 501. In various embodiments, the signal generator 109 is implemented within the RF power amplifier 100A as an oscillator, a microcontroller, or a direct digital synthesizer. The controller 111 provides user control of the signal generator 109, such as by allowing setting of the initial switching frequency (f) of the switching transistor 101.

[0041] The phase delay module 501 delays the measured voltage (V) across the coil 113 by the phase delay (Θ). coil ) (switching feedback signal) to generate a gate 101g drive voltage (switching control signal) for the switching transistor 101. When the switching control signal output by the phase delay module 501 reaches an equilibrium condition corresponding to a ZVS condition, the state of Equation 1 exists, where ∠V coil is the phase angle of the voltage across the coil 113, and ∠V gate is the phase angle of the voltage supplied to the gate 101g of the switching transistor 101, and Θ is the phase delay implemented by the phase delay module 501. Also, when the switching control signal output by the phase delay module 501 reaches an equilibrium condition corresponding to the ZVS condition, the state of Equation 2 exists, where ∠V gate is the phase angle of the voltage supplied to the gate 101g of the switching transistor 101, and ∠V drainis the phase angle of the voltage at the switching transistor drain node 133. Combining Equation 1 and Equation 2, we obtain the equilibrium condition corresponding to the ZVS condition for the frequency regulation method, as shown in Equation 3. According to Equation 3, the "phase delay (Θ) vs. switching frequency (f) curve" is

number

number

[0042]

number

[0043]

number

[0044]

number

[0045] FIG. 6 illustrates exemplary power amplifier characteristic curves 601, 602, and 603 for various coil inductances for implementing an exemplary frequency adjustment method, along with an exemplary theta curve 604, according to some embodiments. It should be understood that RF power amplifier 100A is operating in a ZVS condition at several points along any of power amplifier characteristic curves 601, 602, and 603. For example, in the example of FIG. 6, RF power amplifier 100A is operating in a ZVS condition at locations on power amplifier characteristic curves 601, 602, and 603 to the right of their respective inflection points near −100r. As changes in plasma 129 decrease the coil inductance, the power amplifier characteristic curve shifts toward higher frequencies. Conversely, as changes in plasma 129 increase the coil inductance, the power amplifier characteristic curve shifts toward lower frequencies. Essentially any point past (to the right of) the inflection point on each of power amplifier characteristic curves 601, 602, and 603 can be selected as the operating state for RF power amplifier 100A to maintain ZVS conditions. Once operating points along the various power amplifier characteristic curves 601, 602, and 603 are selected, respectively, to define the operation of RF power amplifier 100A, a theta curve 604 is defined to intersect (meet) the selected operating points along the various power amplifier characteristic curves 601, 602, and 603. For example, in FIG. 6, operating points 605, 606, and 607 for RF power amplifier 100A are selected along power amplifier characteristic curves 601, 602, and 603, respectively. Theta curve 604 is defined to pass through operating points 605, 606, and 607.

[0046] The phase delay module 501 is configured to implement a theta curve 604. Specifically, the phase delay module 501 is configured to apply a predetermined phase delay, provided by the theta curve 604, to a switching feedback signal received at the input of the phase delay module 501 from the electrical parameter measurement device 503. The phase delay module 501 applies the predetermined phase delay as a function of the switching frequency (f), i.e., applies the theta curve 604 to the switching feedback signal. Thus, when the coil inductance decreases (shifts toward higher frequencies), the switching frequency (f) of the RF power amplifier 100A shifts to higher frequencies in accordance with the theta curve 604, thereby maintaining a ZVS condition. Conversely, when the coil inductance increases (shifts toward lower frequencies), the switching frequency (f) of the RF power amplifier 100A shifts to lower frequencies in accordance with the theta curve 604, thereby maintaining a ZVS condition. The implementation of the theta curve 604 by the phase delay module 501 ensures that the RF power amplifier 100A operates under ZVS conditions even when the power amplifier characteristic curve shifts due to changes in coil inductance caused by changes in the plasma 129.

[0047] FIG. 7 illustrates an exemplary configuration of a phase delay module 501A for implementing the theta curve 604 as shown in FIG. 6 , according to some embodiments. In this example, the phase delay module 501A is implemented as the phase delay module 501 in the RF power amplifier 100A of FIG. 5 . The phase delay module 501A includes a buffer circuit 701 having an input terminal 701 a and an output terminal 701 b. The input terminal 701 a of the buffer circuit 701 is electrically connected to the input 501 of the phase delay module 501A. Thus, the input terminal 701 a of the buffer circuit 701 receives a switching feedback signal corresponding to a measurement of an electrical parameter (such as voltage, current, power, etc.) associated with the coil 113. The phase delay module 501A also includes a resistor 703 having an input terminal 703 a and an output terminal 703 b. The input terminal 703 a of the resistor 703 is electrically connected to the output terminal 701 b of the buffer circuit 701. The phase delay module 501A also includes an inverter circuit 705 having an input terminal 705a and an output terminal 705b. The input terminal 705a of the inverter circuit 705 is electrically connected to the output terminal 703b of the resistor 703. The output terminal 705b of the inverter circuit 705 is electrically connected to the output 501o of the phase delay module 501A. The phase delay module 501A also includes a capacitor 707 having an input terminal 707a and an output terminal 707b. The input terminal 707a of the capacitor 707 is electrically connected to both the output terminal 703b of the resistor 703 and the input terminal 705a of the inverter circuit 705. The output terminal 707b of the capacitor 707 is electrically connected to the reference ground potential 709.

[0048] Buffer circuit 701, resistor 703, and capacitor 707 collectively impart a fixed time delay to the switching feedback signal received at input 501i of phase delay module 501A, such that a delayed version of the switching feedback signal is provided to input terminal 705a of inverter circuit 705. For example, in some embodiments, the fixed time delay imparted to the switching feedback signal by the combination of buffer circuit 701, resistor 703, and capacitor 707 is on the order of a few nanoseconds. Inverter circuit 705 then imparts a 180° phase shift to the delayed version of the switching feedback signal to generate a switching control signal that is sent through output 501o of phase delay module 501A and through connections 507 and 110 to gate 101g of switching transistor 101. The phase delay module 501A is configured to apply a predetermined linearly varying phase delay (Θ) as a function of frequency (f) (i.e., a theta curve) to a switching feedback signal corresponding to an electrical parameter related to the coil 113 measured by the electrical parameter measuring device 503 to generate a switching control signal used to drive the gate 101g of the switching transistor 101 in the RF power amplifier 100A.

[0049] In some embodiments, phase delay module 501A is implemented in a static configuration where resistor 703 has a fixed resistance value and capacitor 707 has a fixed capacitance value. However, in some embodiments, phase delay module 501A is implemented in a dynamic configuration where resistor 703 has a variable resistance value and capacitor 707 has a variable capacitance value. In some embodiments, in the dynamic configuration, resistor 703 is connected to a microcontroller that controls the resistance value of resistor 703. Also, in some embodiments, in the dynamic configuration, capacitor 707 is connected to a microcontroller that controls the capacitance value of capacitor 707.

[0050] It should be understood that the theta curve for the RF power amplifier 100A can be arbitrarily defined as needed. The phase delay module 501 is configured as needed to implement the arbitrarily defined theta curve. In other words, the phase delay module 501 is configured to impart a frequency-dependent phase delay / shift to the switching feedback signal (a characteristic signal of the RF power amplifier 100A) to generate a switching control signal that drives the gate 101g of the switching transistor 101. Therefore, depending on how the theta curve is defined, the phase delay module 501 can have various configurations.

[0051] The impedance of the coil 113 is usually very inductive (the Q factor is usually high). Therefore, the voltage across the coil 113 (V coil ) and the current in the coil 113 (I coil ) are almost always about 90° out of phase with each other, i.e.,

number

[0052] 8 illustrates an example of a phase delay module 501B implemented to substantially pass the switching feedback signal as the switching control signal, according to some embodiments. The phase delay module 501B includes a buffer circuit 801 having an input terminal 801i electrically connected to the input 501i of the phase delay module 501B and an output terminal 801o electrically connected to the output 501o of the phase delay module 501B. The buffer circuit 801 boosts the switching feedback signal to generate the switching control signal, such that the switching control signal has substantially the same phase as the switching feedback signal.

[0053] 9 illustrates an example of a phase delay module 501C implemented to impart a phase shift of approximately 180° to a switching feedback signal received at an input 501i of the phase delay module 501C, according to some embodiments. The phase delay module 501C includes an inverter circuit 901 having an input terminal 901i electrically connected to the input 501i of the phase delay module 501C and an output terminal 901o electrically connected to the output 501o of the phase delay module 501C. In some embodiments, the inverter circuit 901 is implemented as a digital logic NOT gate. In some embodiments, the inverter circuit 901 is implemented as an operational amplifier. The inverter circuit 901 imparts a phase shift of approximately 180° to the switching feedback signal to generate a switching control signal.

[0054] 10 shows an example of a phase delay module 501D that implements an RC circuit that applies a fixed (and optionally adjustable) time delay to a switching feedback signal received at input 501i of phase delay module 501C, according to some embodiments. Phase delay module 501D includes a resistor 1001 having an input terminal 1001a and an output terminal 1001b. Input terminal 1001a of resistor 1001 is electrically connected to input 501i of phase delay module 501D. Output terminal 1001b of resistor 1001 is electrically connected to output 501o of phase delay module 501. Phase delay module 501D also includes a capacitor 1003 having input terminal 1003a and output terminal 1003b. Input terminal 1003a of capacitor 1003 is electrically connected to both output terminal 1001b of resistor 1001 and output 501o of phase delay module 501. The output terminal 1003b of the capacitor 1003 is electrically connected to a reference ground potential 1005. The phase delay module 501D imparts a time delay (T) to the switching feedback signal to generate a switching control signal. The time delay (T) imparted by the phase delay module 501D corresponds to a phase shift (2πfT) of the switching feedback signal. Thus, in the phase delay module 501D, the switching control signal used to drive the gate 101g of the switching transistor 101 in the RF power amplifier 100A is a phase-shifted version of the switching feedback signal, where the amount of phase shift is equal to (2πfT) and the time delay (T) is defined by the resistance of the resistor 1001 and the capacitance of the capacitor 1003. In some embodiments, the phase delay module 501D is implemented in a static configuration, where the resistor 1001 has a fixed resistance value and the capacitor 1003 has a fixed capacitance value. In some embodiments, the phase delay module 501D is implemented in a dynamic configuration in which the resistor 1001 has a variable resistance value and the capacitor 1003 has a variable capacitance value.In these embodiments, a microcontroller (or another form of control device) is used to control the resistance value of resistor 1001 and the capacitance value of capacitor 1003 to impart a predetermined time delay (T) and corresponding phase shift (2πfT) to the switching feedback signal to generate the switching control signal that is supplied to the gate 101g of the switching transistor 101.

[0055] In some embodiments, the phase delay module 501 is configured to include an active or passive lead compensator and / or lag compensator to implement a predetermined theta curve. For example, FIG. 11 illustrates an example of a phase delay module 501E implementing a passive lead compensator, according to some embodiments. The passive lead compensator of the phase delay module 501E applies a frequency-dependent phase shift to the switching feedback signal, enabling manipulation of the phase versus frequency profile to generate the switching control signal. The phase delay module 501E includes an RLC circuit including a resistor 1105, an inductor 1103, and a capacitor 1101. The capacitor 1101 has an input terminal 1101a electrically connected to the input 501i of the phase delay module 501E. The capacitor 1101 has an output terminal 1101b electrically connected to the output 501o of the phase delay module 501E. Inductor 1103 has input terminal 1103a electrically connected to both output terminal 1101b of capacitor 1101 and output 501o of phase delay module 501E. Resistor 1105 has input terminal 1105a electrically connected to output terminal 1103b of inductor 1103. Resistor 1105 has output terminal 1105b electrically connected to reference ground potential 1107. In some embodiments, capacitor 1101 has a fixed capacitance value, inductor 1103 has a fixed inductance value, and resistor 1105 has a fixed resistance value, thereby causing phase delay module 501E to have a static configuration that implements a static theta curve. In some embodiments, one or more of capacitor 1101, inductor 1103, and resistor 1105 are adjustable / variable by respective control signals from a microcontroller (or another form of control device), thereby causing phase delay module 501E to have a dynamic configuration that can implement an adjustable / variable theta curve.

[0056] 12 illustrates an example of a phase delay module 501F implementing an active lead-lag compensator, according to some embodiments. The phase delay module 501F includes a resistor 1201 having an input terminal 1201a electrically connected to an input 501i of the phase delay module 501F. The resistor 1201 has an output terminal 1201b electrically connected to each of a first input terminal 1203i1 (negative input terminal) of a zero-crossing detector 1203, an input terminal 1205a of a resistor 1205, and an input terminal 1207a of a resistor 1207. The zero-crossing detector 1203 has a second input terminal 1203i2 (positive input terminal) electrically connected to a reference ground potential 1211. The zero-crossing detector 1203 has an output terminal 1203o electrically connected to both the output 501o of the phase delay module 501F and the output terminal 1205b of the resistor 1205. Resistor 1207 has output terminal 1207b electrically connected to input terminal 1209a of capacitor 1209. Capacitor 1209 has output terminal 1209b electrically connected to reference ground potential 1213. In some embodiments, resistors 1201, 1205, and 1207 have respective fixed resistance values and capacitor 1209 has a fixed capacitance value, such that phase delay module 501F has a static configuration that implements a static theta curve. In some embodiments, one or more of resistors 1201, 1205, 1207 and capacitor 1209 are adjustable / variable by respective control signals from a microcontroller (or another form of control device), such that phase delay module 501F has a dynamic configuration that can implement an adjustable / variable theta curve.

[0057] 13A shows an example of a phase delay module 501G implementing a lead compensator, according to some embodiments. The phase delay module 501G includes a capacitor 1301 having an input terminal 1301a electrically connected to an input 501i of the phase delay module 501G. The capacitor 1301 has an output terminal 1301b electrically connected to both a first input terminal 1303i1 (positive input terminal) of a zero-crossing detector 1303 and an input terminal 1309a of an inductor 1309. The zero-crossing detector 1303 has a second input terminal 1303i2 (negative input terminal) electrically connected to a reference ground potential 1307. The zero-crossing detector 1303 has an output terminal 1303o electrically connected to an input terminal 1305a of an inverter 1305. The inverter 1305 has an output terminal 1305b electrically connected to an output 501o of the phase delay module 501G. Inductor 1309 has output terminal 1309b electrically connected to input terminal 1311a of resistor 1311. Resistor 1311 has output terminal 1311b electrically connected to reference ground potential 1313. Resistor 1311 has output terminal 1311b electrically connected to reference ground potential 1313. In some embodiments, capacitor 1301, inductor 1309, and resistor 1311 have respective fixed configurations, such that phase delay module 501G has a static configuration that implements a static theta curve. In some embodiments, one or more of capacitor 1301, inductor 1309, and resistor 1311 are adjustable / variable by respective control signals from a microcontroller (or another form of control device), such that phase delay module 501G has a dynamic configuration that can implement an adjustable / variable theta curve.

[0058] FIG. 13B illustrates the inductance L of each of the different coils 113 according to some embodiments. coil,1 , L coil,2 , and L coil,313A. The bottom plot of FIG. 13B shows the current through inductor 113 (I ) as a function of switching frequency (f) for power amplifier characteristic curves 1315, 1316, and 1317 shown in the top plot of FIG. 13B. coil Specifically, curve 1322 shows the inductance (L coil,1 ) for the power amplifier characteristic curve 1315 corresponding to the current (I coil ) The curve 1323 shows the inductance (L coil,2 ) for the power amplifier characteristic curve 1316 corresponding to the current (I coil ) of the coil 113. coil,3 ) for the power amplifier characteristic curve 1317 corresponding to the current (I coil ) in the diagram. Theta curve 1314 is defined to intersect with power amplifier characteristic curve 1315 at operating point 1319, which corresponds to a ZVS condition. Theta curve 1314 is also defined to intersect with power amplifier characteristic curve 1316 at operating point 1320, which corresponds to a ZVS condition. Theta curve 1314 is also defined to intersect with power amplifier characteristic curve 1317 at operating point 1321, which corresponds to a ZVS condition. Operating point 1319 is the point at which the current (I coil ) curve 1322. Operating point 1320 corresponds to point 1325 on curve 1322. coil ) curve 1323. Operating point 1321 corresponds to point 1326 on the current (I coil ) curve 1324. Thus, FIG. 13B shows that as the inductance of coil 113 decreases, the phase of the switching control signal is adjusted according to theta curve 1314, thereby maintaining a ZVS condition. In addition, FIG. 13B shows that as the inductance of coil 113 decreases, the current (I coil) automatically decreases as the current through the coil 113 (I) decreases as a function of the inductance of the coil 113 while maintaining ZVS conditions. coil ) is useful in some applications.

[0059] For example, in some embodiments, it may be desirable to apply a high current to the coil 113 at the beginning so that the plasma 129 transitions from E-mode to H-mode. In some embodiments, the power amplifier characteristic curve 1315 may be a function of the coil inductance (L coil,1 ) corresponds to low coil inductance (L coil,2 and L coil,3 ), indicates the presence of some plasma 129 near the window 121 under the coil 113, which indicates that the plasma 129 has likely transitioned from E-mode to H-mode. When the plasma 129 is in H-mode, it is desirable to prevent RF power amplifier 100A from delivering full power to the coil 113, as this could cause the hardware to overheat and reduce system reliability. Therefore, as the coil inductance decreases, the current (I coil ) away from its peak value. FIG. 13B shows that the theta curve 1314 implemented by the phase delay module 501G reduces the current (I) through the coil 113 as the inductance of the coil 113 decreases, as shown by points 1325, 1326, and 1327. coil ) automatically move away from its peak value while all maintaining ZVS conditions.

[0060] Phase delay modules 501E, 501F, and 501G, shown in Figures 11, 12, and 13A, respectively, represent examples of how lead and / or lag compensators can be used to implement control of the theta curve to maintain ZVS conditions. It should be understood that in various embodiments, phase delay module 501 can be configured to implement essentially any configuration of active lead and / or lag compensators or any configuration of passive lead and / or lag compensators.

[0061] FIG. 14 illustrates an example of a phase delay module 501H implementing a phase-locked loop (PLL) 1403 that applies a negative time delay to a switching feedback signal to generate a switching control signal, according to some embodiments. The phase delay module 501H includes a time delay component 1401 having an input terminal 1401i electrically connected to an input 501i of the phase delay module 501H. The time delay component 1401 has an output terminal 1401o electrically connected to a first input terminal 1403i1 of the PLL 1403. The time delay component 1401 is configured to apply a time delay (Tp) to a signal received at the input terminal 1401i and transmit a corresponding delayed signal through the output 1401o. The PLL 1403 has an output terminal 1403o electrically connected to the output 501o of the phase delay module 501H. The output terminal 1403o of the PLL 1403 is also electrically connected to a second input terminal 1403i2 of the PLL 1403 through a feedback loop. The feedback loop includes a time delay element 1405. Specifically, an output terminal 1403o of the PLL 1403 is electrically connected to an input terminal 1405i of the time delay element 1405. The time delay element 1405 has an output terminal 1405o electrically connected to a second input terminal 1403i2 of the PLL 1403. The time delay element 1403 is configured to impart a time delay (Tn) to the signal received at the input terminal 1405i and communicate the corresponding delayed signal through the output 1405o. In this manner, the phase delay module 501H operates to delay the switching feedback signal received at the input 501i by a time delay amount (Tp-Tn) corresponding to a phase shift amount of (2πf·(Tp-Tn)) to generate a switching control signal that is communicated through the output 501o. The phase delay module 501H allows for the application of a negative time delay, which can be useful when the theta curve needs to be shifted in phase space to shift the desired operating point of the RF amplifier module 100A.It should be appreciated that in various embodiments, the phase delay module 501 may implement a delay locked loop (DLL) or a PLL with a delay line in the feedback loop of the DLL / PLL and be configured to impart essentially any amount of positive or negative constant time delay to the switching feedback signal to generate the switching control signal.

[0062] FIG. 15 illustrates an example of a phase delay module 501I implementing a PLL 1501 that cancels the signal propagation delay of a switching feedback signal to generate a switching control signal, according to some embodiments. The PLL 1501 has a first input terminal 1501i electrically connected to an input 501i of the phase delay module 501I. The PLL 1501 has an output terminal 1501o electrically connected to an input terminal 1503i of a theta curve generation circuit 1503. In various embodiments, the theta curve generation circuit 1503 can include essentially any combination of connectors, wires, logic gates, buffers, etc., as needed to implement a predetermined theta curve. The theta curve generation circuit 1503 has an output terminal 1503o electrically connected to an input terminal 1505i of a buffer circuit 1505. The buffer circuit 1505 has an output terminal 1505o electrically connected to both the output 501o of the phase delay module 501I and a second input terminal 1501i2 of the PLL 1501. There is some time delay between when the switching feedback signal is measured by the electrical parameter measuring device 503 and when the switching control signal reaches the gate 101g of the switching transistor 101. For example, in some embodiments, the voltage (V coilThe total time delay from the time when the switching feedback signal 1505 is measured at the coil 113 to generate the switching feedback signal to the time when the gate 101g of the switching transistor 101 is driven by the corresponding switching control signal is approximately 30 nanoseconds, which is approximately half a 13 MHz (megahertz) switching frequency cycle and is a fairly long total time delay. The phase delay module 501I eliminates unnecessary propagation delays in the signal path from the measurement of the switching feedback signal at the coil 113 to the delivery of the switching control signal to the gate 101g of the switching transistor 101. The switching feedback signal is provided to a first input terminal 1501i1 of the PLL 1501, and the switching control signal is provided to a second input terminal 1501i2 of the PLL 1501 from the output terminal 1505o of the buffer circuit 1505 (or from a final electrical node connected to the output 501o of the phase delay module 501I). In this way, the switching control signal is used as a feedback signal for the PLL 1501. PLL 1501 operates to adjust the timing of the signal output by PLL 1505 to compensate for the phase difference between the two signals received at inputs 1501i1 and 1501i2 of PLL 1501, i.e., the switching feedback signal and the switching control signal. As a result, unwanted propagation delays in the signal path from measuring the switching feedback signal at coil 113 to delivering the switching control signal to gate 101g of switching transistor 101, along with the corresponding phase lag, are significantly reduced or eliminated by phase delay module 501I. Thus, phase delay module 501I effectively cancels all of the signal propagation delays from measuring the switching feedback signal at coil 113 to driving gate 101g of switching transistor 101 with the switching control signal.

[0063] In various embodiments, the phase delay module 501 can be implemented to combine any of the features of the phase delay modules 501A-501I to implement a predetermined theta curve necessary to maintain ZVS conditions. For example, FIG. 16 illustrates an example of a phase delay module 501J that combines various features of the phase delay modules 501A-501I described with respect to FIGS. 7-15 to generate switching control signals, according to some embodiments. The phase delay module 501J includes an RLC lead compensator 1601 having an input terminal 1601i electrically connected to an input 501i of the phase delay module 501J. The RLC lead compensator 1601 has an output terminal 1601o electrically connected to an input terminal 1603i of a time delay element 1603. The time delay element 1603 has an output terminal 1603o electrically connected to a first input terminal 1605i1 of a PLL 1605. The PLL 1605 has an output terminal 1605o electrically connected to an input terminal 1607i of the theta curve generation circuit 1607. The theta curve generation circuit 1607 has an output terminal 1607o electrically connected to an input terminal 1609i of a buffer circuit 1609. The buffer circuit 1609 has an output terminal 1609o electrically connected to the output of the phase delay module 501. The output terminal 1609o of the buffer circuit 1609 is also electrically connected to an input terminal 1611i of a time delay element 1611. The time delay element 1611 has an output terminal 1611o electrically connected to a second input terminal 1605i2 of the PLL 1605.

[0064] The above exemplary configurations of the phase delay module 501 can be combined to create a phase shift unit with a desired frequency response. For example, the voltage (V coil ) and uses a PLL for propagation delay compensation, adding a 3 ns RC delay line before the input of the PLL, which reduces the current in coil 113 (I coil) can be generated. In this example, the switching frequency increases by a factor of four, while the phase offset varies by only 32° within a range of 45° to 90°. In some RF power amplifier 100A configurations, this phase offset variation is small enough to maintain ZVS conditions across the entire frequency band. It should be understood that the foregoing description of phase delay module 501 is provided by way of example. In various embodiments, phase delay module 501 is configured as needed to implement a predetermined theta curve as needed to maintain ZVS conditions across the switching frequency (f) operating range of RF power amplifier 100A.

[0065] 17 shows a flowchart of a method for zero-voltage switching of an RF power amplifier 100A for a plasma processing system, according to some embodiments. The method includes an operation 1701 for operating a switching transistor 101, a DC power supply 105, and an impedance matching network 103 to generate an RF signal. The method includes an operation 1703 for transmitting the RF signal to a coil 113 of the plasma processing system. The method also includes an operation 1705 for measuring an electrical parameter associated with the coil 113, such as by an electrical parameter measuring device 503. In some embodiments, operation 1705 includes measuring a voltage across the coil 113. In some embodiments, operation 1705 includes measuring a current across the coil 113. The method also includes an operation 1707 for transmitting a switching feedback signal based on the electrical parameter measured in operation 1705 to an input 501i of the phase delay module 501. The method also includes an operation 1709 for generating a switching control signal within the phase delay module 501 by applying a phase adjustment to the switching feedback signal. The phase adjustment applied by the phase delay module 501 is represented by a theta curve as described herein. The method also includes an operation 1711 for communicating a switching control signal to a gate 101g of the switching transistor 101 to control operation of the switching transistor 101 and corresponding generation of the RF signal communicated to the coil 113. In some embodiments, the method also includes controlling the phase adjustment to maintain a ZVS condition in which the voltage on the switching transistor drain node 133 approaches substantially zero whenever the switching control signal turns on the switching transistor 101 to allow current flow between the drain terminal 101d of the switching transistor 101 and the reference ground potential 131.

[0066] Various embodiments disclosed herein enable the implementation of phase shifting of a characteristic signal (switching feedback signal) from an RF power amplifier. The embodiments disclosed herein enable the creation of a phase shift element (phase delay module 501) with an appropriate frequency response, thereby achieving fast feedback control that maintains ZVS conditions for the RF power amplifier 100A over a wide range of plasma load impedances. Because ZVS is necessary to maintain high power efficiency and high reliability of the RF power amplifier 100A, it should be appreciated that the embodiments disclosed herein provide an inexpensive solution for increasing the reliability and reducing power consumption of RF power systems. The embodiments disclosed herein are applicable for use with any switch-mode RF power amplifier topology class.

[0067] The various embodiments described herein can be practiced in conjunction with a variety of computer system configurations, including handheld hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, and the like. The various embodiments described herein can also be practiced in conjunction with distributed computing environments in which tasks are performed by remote processing hardware units linked through a computer network. It should also be understood that the various embodiments disclosed herein include the performance of various computer-implemented operations involving data stored in computer systems. These computer-implemented operations are operations that manipulate physical quantities. In various embodiments, the computer-implemented operations are performed by either general-purpose or special-purpose computers. In some embodiments, the computer-implemented operations are performed by selectively activated computers and / or are directed by one or more computer programs stored in computer memory or retrieved over a computer network. When computer programs and / or digital data are retrieved over a computer network, the digital data may be processed by other computers on the computer network (e.g., a cloud of computational resources). The computer programs and digital data are stored as computer-readable code on non-transitory computer-readable media. A non-transitory computer-readable medium is any data storage hardware unit, such as a memory device, that stores data, which is then read by a computer system. Examples of non-transitory computer-readable media include hard drives, network-attached storage (NAS), ROM, RAM, compact disc ROM (CD-ROM), CD-recordable (CD-R), CD-rewritable (CD-RW), digital video / versatile disc (DVD), magnetic tape, and other optical and non-optical data storage hardware units.In some embodiments, the computer program and / or digital data is distributed among multiple computer-readable media located on different computer systems within a network of coupled computer systems such that the computer program and / or digital data is executed and / or stored in a distributed fashion.

[0068] Although the foregoing disclosure includes some details for clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. For example, it should be understood that one or more features of any embodiment disclosed herein can be combined with one or more features of any other embodiment disclosed herein. Therefore, the present embodiments should be considered illustrative rather than limiting, and the claims should not be limited to the details set forth herein, but may be modified within the scope and equivalents of the described embodiments.

[0069] The claims are as follows:

Claims

1. A high-frequency power amplifier for a plasma processing system, A switching transistor having a drain terminal, a source terminal, and a gate, wherein the source terminal is electrically connected to a reference ground potential, A DC power supply electrically connected to the drain terminal of the switching transistor, An impedance matching network electrically connected between the drain terminal of the switching transistor and the coil of the plasma processing system, An electrical parameter measuring device arranged to measure electrical parameters related to the coil, A phase delay module having an input electrically connected to receive a switching feedback signal from the electrical parameter measuring device, having an output electrically connected to the gate of the switching transistor, configured to apply phase adjustment to the switching feedback signal to generate a switching control signal, and configured to transmit the switching control signal to the gate of the switching transistor through the output of the phase delay module. A high-frequency power amplifier for plasma processing systems, equipped with the above features.

2. A high-frequency power amplifier for a plasma processing system according to claim 1, A high-frequency power amplifier for a plasma processing system, wherein the electrical parameter measuring device is configured to measure the voltage across the coil and to provide the switching feedback signal as a voltage signal representing the voltage measured across the coil.

3. A high-frequency power amplifier for a plasma processing system according to claim 1, A high-frequency power amplifier for a plasma processing system, wherein the electrical parameter measuring device is configured to measure the current across the coil and to provide the switching feedback signal as a voltage signal representing the current measured across the coil.

4. A high-frequency power amplifier for a plasma processing system according to claim 1, The impedance matching network comprises at least one capacitor and at least one inductor, and is a high-frequency power amplifier for a plasma processing system.

5. A high-frequency power amplifier for a plasma processing system according to claim 1, A high-frequency power amplifier for a plasma processing system, wherein the switching transistor is configured to allow current to flow from the drain terminal to the reference ground potential when the switching control signal applies a sufficiently high voltage to the gate of the switching transistor, and the switching transistor is configured to disable current flow from the drain terminal to the reference ground potential when the switching control signal applies a sufficiently low voltage to the gate of the switching transistor.

6. A high-frequency power amplifier for a plasma processing system according to claim 1, The phase adjustment maintains a zero-voltage switching condition in which the voltage on the drain terminal of the switching transistor approaches substantially zero each time the switching control signal turns on the switching transistor and allows current to flow between the drain terminal of the switching transistor and the reference ground potential.

7. A high-frequency power amplifier for a plasma processing system according to claim 1, A high-frequency power amplifier for a plasma processing system, wherein the phase delay module includes a buffer circuit having an input terminal electrically connected to the input of the phase delay module, the phase delay module includes a resistor having an input terminal electrically connected to the output terminal of the buffer circuit, the phase delay module includes an inverter circuit having an input terminal electrically connected to the output terminal of the resistor, the inverter circuit has an output terminal electrically connected to the output of the phase delay module, and the phase delay module includes a capacitor having an input terminal electrically connected to both the output terminal of the resistor and the input terminal of the inverter circuit, the capacitor having an output terminal electrically connected to a reference ground potential.

8. A high-frequency power amplifier for a plasma processing system according to claim 1, A high-frequency power amplifier for a plasma processing system, wherein the phase delay module includes a buffer circuit having an input terminal electrically connected to the input of the phase delay module, and the buffer circuit has an output terminal electrically connected to the output of the phase delay module.

9. A high-frequency power amplifier for a plasma processing system according to claim 1, A high-frequency power amplifier for a plasma processing system, wherein the phase delay module includes an inverter circuit having an input terminal electrically connected to the input of the phase delay module, and the inverter circuit has an output terminal electrically connected to the output of the phase delay module.

10. A high-frequency power amplifier for a plasma processing system according to claim 1, A high-frequency power amplifier for a plasma processing system, wherein the phase delay module includes a resistor having an input terminal electrically connected to the input of the phase delay module, the resistor having an output terminal electrically connected to the output of the phase delay module, and the phase delay module includes a capacitor having an input terminal electrically connected to both the output terminal of the resistor and the output terminal of the phase delay module, the capacitor having an output terminal electrically connected to a reference ground potential.

11. A high-frequency power amplifier for a plasma processing system according to claim 1, A high-frequency power amplifier for a plasma processing system, wherein the phase delay module includes a capacitor having an input terminal electrically connected to the input of the phase delay module, the capacitor having an output terminal electrically connected to the output of the phase delay module, the phase delay module includes an inductor having an input terminal electrically connected to both the output terminal of the capacitor and the output of the phase delay module, the phase delay module includes a resistor having an input terminal electrically connected to the output terminal of the inductor, and the resistor having an output terminal electrically connected to a reference ground potential.

12. A high-frequency power amplifier for a plasma processing system according to claim 1, A high-frequency power amplifier for a plasma processing system, comprising: a phase delay module, comprising a first resistor having an input terminal electrically connected to the input of the phase delay module; a zero-crossing detector having a first input terminal electrically connected to the output terminal of the first resistor; the zero-crossing detector having a second input terminal electrically connected to a reference ground potential; the zero-crossing detector having an output terminal electrically connected to the output of the phase delay module; a second resistor having an input terminal electrically connected to both the output terminal of the first resistor and the first input terminal of the zero-crossing detector; the second resistor having an output terminal electrically connected to both the output terminal of the zero-crossing detector and the output of the phase delay module; a third resistor having an input terminal electrically connected to both the output terminal of the first resistor and the first input terminal of the zero-crossing detector; and a capacitor having an input terminal electrically connected to the output terminal of the third resistor, the capacitor having an output terminal electrically connected to the reference ground potential.

13. A high-frequency power amplifier for a plasma processing system according to claim 1, A high-frequency power amplifier for a plasma processing system, comprising: a phase delay module, a capacitor having a first input terminal electrically connected to the input of the phase delay module; a zero-crossing detector having a first input terminal electrically connected to the output terminal of the capacitor; the zero-crossing detector having a second input terminal electrically connected to a reference ground potential; a phase delay module, an inverter circuit having an input terminal electrically connected to the output terminal of the zero-crossing detector; the inverter circuit having an output terminal electrically connected to the output of the phase delay module; a phase delay module, an inductor having an input terminal electrically connected to both the output terminal of the capacitor and the first input terminal of the zero-crossing detector; a phase delay module, a resistor having an input terminal electrically connected to the output terminal of the inductor; and a resistor having an output terminal electrically connected to the reference ground potential.

14. A high-frequency power amplifier for a plasma processing system according to claim 1, A high-frequency power amplifier for a plasma processing system, wherein the phase delay module includes a first time delay component having an input terminal electrically connected to the input of the phase delay module, the phase delay module includes a phase-locked loop (PLL) having a first input terminal electrically connected to the output terminal of the first time delay component, the PLL having an output terminal electrically connected to the output of the phase delay module, and the phase delay module includes a second time delay component having an input terminal electrically connected to both the output terminal of the PLL and the output of the phase delay module, the second time delay component having an output terminal electrically connected to the second input terminal of the PLL.

15. A high-frequency power amplifier for a plasma processing system according to claim 1, A high-frequency power amplifier for a plasma processing system, wherein the phase delay module includes a phase-locked loop (PLL) having a first input terminal electrically connected to the input of the phase delay module, the phase delay module includes a theta curve generation circuit having an input terminal electrically connected to the output terminal of the PLL, the phase delay module includes a buffer circuit having an input terminal electrically connected to the output terminal of the theta curve generation circuit, the buffer circuit has an output terminal electrically connected to the output of the phase delay module, and the PLL has a second input terminal electrically connected to both the output terminal of the buffer circuit and the output of the phase delay module.

16. A high-frequency power amplifier for a plasma processing system according to claim 1, A high-frequency power amplifier for a plasma processing system, wherein the phase delay module includes a lead compensator circuit having an input terminal electrically connected to the input of the phase delay module, the phase delay module includes a first time delay component having an input terminal electrically connected to the output terminal of the lead compensator circuit, the phase delay module includes a phase-locked loop (PLL) having a first input terminal electrically connected to the output terminal of the first time delay component, the phase delay module includes a theta curve generation circuit having an input terminal electrically connected to the output terminal of the PLL, the phase delay module includes a buffer circuit having an input terminal electrically connected to the output terminal of the theta curve generation circuit, the buffer circuit having an output terminal electrically connected to the output of the phase delay module, and the phase delay module includes a second time delay component having an input terminal electrically connected to both the output terminal of the buffer circuit and the output of the phase delay module, the second time delay component having an output terminal electrically connected to the second input terminal of the PLL.

17. A method for zero-voltage switching of a high-frequency power amplifier for a plasma processing system, By operating switching transistors, a DC power supply, and an impedance matching network, a high-frequency signal is generated. The high-frequency signal is transmitted to the coil of the plasma processing system. The electrical parameters related to the coil are measured, A switching feedback signal based on the measured electrical parameters is transmitted to the input of the phase delay module. By applying phase adjustment to the switching feedback signal, a switching control signal is generated within the phase delay module. The switching control signal is transmitted to the gate of the switching transistor in order to control the operation of the switching transistor and the corresponding generation of the high-frequency signal transmitted to the coil. A method that includes [a certain feature].

18. The method according to claim 17, A method for measuring the electrical parameters related to the coil, comprising measuring the voltage across the coil.

19. The method according to claim 17, A method for measuring the electrical parameters related to the coil, including measuring the current on the coil.

20. The method according to claim 17, further, A method comprising controlling the phase adjustment and maintaining a zero-voltage switching condition such that the voltage on the drain terminal of the switching transistor approaches substantially zero each time the switching transistor is turned on by the switching control signal, thereby enabling the flow of current between the drain terminal of the switching transistor and a reference ground potential.

Images