Method for controlling an active matrix display, associated control device, and computer program product

Abstract

A method for controlling an active matrix display (4) that allows control with low-cost and highly flexible color diversity, the method comprising the steps of: executing a program stored in a program storage device (5) of a microcontroller (3), the program controlling a DMA controller (6) to read image data with a color depth of 1 bit per pixel from a data storage device (2), and transferring the RGB image data generated by the program to a hardware SPI (7) connected to the DMA controller (6) and transferring the RGB image data in a serial manner via MOSI to the active matrix display (4), the SCK controlling the PCLK of the active matrix display (4) for data transfer synchronization. The invention also relates to a corresponding control device (1) and computer program product.

Description

[Technical Field]

[0001] The present invention relates to a method for controlling an active matrix display, and to a control device having a program storage device on which is stored a program configured and arranged to carry out the method, and to a computer program product having a machine-readable carrier on which is stored the program code of a program for carrying out the method on a control device. [Background technology]

[0002] The '1999 patent describes a host computer that provides image data for each image in a sequence over a serial bus. The image data is extracted from data received over the serial bus to an electronic subassembly connected between the host computer and the display device. The extracted image data is stored in an image memory of the electronic subassembly and displayed under the control of the electronic subassembly. The patent also describes an apparatus for operating the display device by receiving a border or frame of image data defining one or more pixels to generate a continuously updated display.

[0003] Patent Document 2 describes a method and system for processing video data to be displayed on a first video display connected to a single mobile multimedia processor that supports various display formats. The single mobile multimedia processor may be integrated into a mobile device. The video data transferred from memory to the first video display by a DMA controller may be limited based on a specific first video format associated with the video data displayed on the first video display. Only a limited amount of video data to be displayed on the first video display can be transferred from memory to the first video display by the DMA controller. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] European Patent Application Publication No. 1560190 [Patent Document 2] European Patent Application Publication No. 1691272 Summary of the Invention [Problem to be solved by the invention]

[0005] The object of the present invention is to establish a method for controlling an active matrix display, which method allows to control active matrix displays in a cost-effective manner, in particular with a very flexible color variety. [Means for solving the problem]

[0006] This object is solved by a method for controlling an active matrix display, the method comprising the following steps: - loading image data of an image to be displayed on an active matrix display at a color depth of 1 bit per pixel into a data storage device; - executing a program stored in a program storage device of the microcontroller, the program controlling the DMA controller to read 1-bit-per-pixel color depth image data from the data storage device, the program extending the read 1-bit-per-pixel color depth image data with additional blanking data corresponding to the parallel RGB interface specification to generate an RGB image data set that can be read by an active matrix display; - transferring the RGB image dataset generated by the program using a DMA controller to a hardware SPI connected to the DMA controller, which serially transmits the RGB image dataset via its data output to the active matrix display, wherein the SPI clock output controls the pixel clock input of the active matrix display to synchronize the data transfer to the active matrix display.

[0007] An active matrix display (AMD) is in particular a liquid crystal display means that actively controls a large number of dot-like image display elements (pixels) arranged in rows and columns to form a matrix of image display elements that can be controlled, for example, via thin film transistors on the matrix. Active matrix displays include, for example, active matrix liquid crystal displays, also known by the acronym AMLCD (active matrix liquid crystal display). Alternatively, active matrix displays can be based on different display technologies, such as organic light-emitting diodes (OLED or AMOLED).

[0008] Active matrix displays (AMDs) are typically configured either with an internal image memory or without an internal image memory, also commonly referred to as a frame buffer. The method according to the invention is particularly advantageous for controlling active matrix displays without an internal image memory.

[0009] Image memory generally includes almost any data storage device, but must be suitable for storing image data. Preferably, the data storage device is at least one electronic memory module that allows random access, i.e., direct access. This type of memory is also called RAM. For example, static RAM (SRAM) or dynamic RAM (DRAM).

[0010] Because large amounts of data storage or image memory become relatively expensive above a certain resolution, active matrix displays are preferably manufactured and provided without internal image memory in order to keep their price as low as possible. However, customers of such active matrix displays without image memory must provide the necessary data storage or image memory to enable the active matrix display to display images of the desired color depth.

[0011] The objective of the method for controlling an active-matrix display according to the present invention is to find a technical solution that allows images with reduced color depth, in particular with a color depth of one or more bits per pixel, to be displayed on the controlled active-matrix display without requiring a data storage device or image memory with a memory size corresponding to the desired or displayed color depth. The method according to the present invention requires only one data storage device or image memory with a color depth of one bit per pixel. Therefore, in the simplest case, only information regarding whether a particular point-like image display element, i.e., a particular pixel, should be displayed bright or dark is stored in the data storage device or image memory. According to the present invention, color information that may be required for each pixel, row, and / or column of the active-matrix display matrix does not need to be stored in the data storage device or image memory, but can be provided individually for each pixel, row, and / or column of the active-matrix display matrix via a program stored in a program storage device. Since many applications, due to their design, do not require the full color depth that a correspondingly selected active-matrix display is capable of displaying, the method according to the present invention allows for the use of a much smaller data storage device or image memory. This allows active matrix displays to be controlled in a very cost-effective manner.

[0012] Active-matrix displays (e.g., AM-LCD and AM-OLED) offer high resolutions, up to 4096 x 2180 dots (pixels) or higher, depending on their size and design, and typically feature 24-bit color depth per pixel. Active-matrix displays can therefore display approximately 16.8 million colors per pixel. The high resolution and color depth of active-matrix displays significantly increase the memory requirements for image content compared to passive-matrix displays. This large image content, at display sizes around 3.5 inches and resolutions around 320 x 240 pixels, cannot be stored in chip-on-glass (COG) or chip-on-board (COB) memory; therefore, these displays lack internal image memory. However, like passive-matrix displays, the display matrix must be constantly updated to maintain a flicker-free image, and the image data required for this must be continuously provided by a microcontroller or application processor. This data is taken from internal memory (such as SRAM) or, in many cases, from external SD-RAM or DDR-RAM, which is the only way to ensure sufficient memory capacity.

[0013] Controlling an active-matrix display requires high data rates ranging from 100 Mbit / s to over 10 Gbit / s, depending on the required update frequency of the display (e.g., 50 Hz or higher) and the associated required image memory capacity. These data rates must be continuously transferred, even for still images, between the microcontroller or processor and the display, and between the microcontroller or processor and external image data storage. Such high bandwidth can only be transferred to the display via special interfaces, such as parallel RGB (DPI) or LVDS. Furthermore, the microcontroller must be equipped with powerful peripheral components capable of processing and delivering the data rates, making the cost of controlling an active-matrix display significantly higher than that of a passive-matrix display.

[0014] Active-matrix displays often have very large color depths, so signal sources, such as microcontrollers and processors, that control such displays require appropriate interfaces, such as parallel RGB interfaces, complex peripheral modules, such as hardware acceleration, DRAM controllers, and numerous inputs and outputs (I / Os). These peripheral modules require additional chip area. The large number of I / Os not only increases the size of the chip package, increasing the cost of the microcontroller, but also significantly complicates the layout. Therefore, microcontrollers can be divided into two categories, depending on whether they are suitable for controlling active-matrix displays without image memory and their resolution. Many microcontrollers with the necessary peripheral modules and display interfaces offer the option to subsequently reduce the color depth, for example, to 8 bits per pixel or 256 colors per pixel, saving pins and memory, but users must use a fully equipped microcontroller with a special peripheral module and a predefined display interface. In the following, we will primarily refer to microcontrollers. However, instead of a microcontroller, processors and microcontrollers and processors implemented on FPGAs can also be used.

[0015] While this can be frustrating for users who do not require a color display or who only require a very limited number of colors, active matrix displays are generally more attractive than passive matrix displays due to other advantages such as high contrast ratio, high resolution, high brightness, a wide selection of standard sizes, and / or better optical appearance.

[0016] The advantage of the method according to the invention is that it allows users to use low-cost, simple and relatively primitive microcontrollers or processors, in particular to emulate and directly and inexpensively control a parallel RGB interface for an active matrix display without the need for an external display controller with image memory (e.g. SSD2119, FT800) or a timing generator (e.g. CPLD, FPGA).

[0017] A microcontroller preferably used for carrying out the method comprises a data storage device for image data and a program storage device for storing a program comprising program code readable by the microcontroller, the program code being executed by the microcontroller to set up and / or configure the microcontroller to carry out the method according to the invention.

[0018] The microcontroller preferably also includes a DMA controller (DMAC) and a hardware SPI peripheral (hereinafter abbreviated as hardware SPI) with a serial data output (MOSI) and a clock output (SCK).

[0019] After a program-controlled DMA controller reads image data with a color depth of 1 bit per pixel from a data storage device, the image data is expanded by the method with blanking data corresponding to the specifications of the parallel RGB interface of the active matrix display being controlled. The blanking data supplements the visibly displayed matrix of image data pixels with additional data pixels to expand the image data pixels to form an expanded matrix, which includes, in addition to the internal image data pixels, a vertical front blanking interval (vertical front porch), a vertical back blanking interval (vertical back porch), a vertical synchronization signal, and a horizontal front blanking interval (horizontal front porch), a horizontal back blanking interval (horizontal back porch), and a horizontal synchronization signal.

[0020] Therefore, the program automatically extends the image data with this additional blanking data to generate an RGB image data set (frame) that can be read by an active matrix display. This automatically generated RGB image data set is then sent, according to the method of the present invention, i.e., in a specific manner by the program, using a DMA controller (DMAC) to a hardware SPI (English: serial peripheral interface) connected to the DMA controller. In this way, the program automatically adds the additional blanking data to the image data to generate an RGB image data set (frame) that can be read by an active matrix display in particular, and meets the requirements of displays with a parallel RGB interface. In most cases, displays with a parallel RGB interface are color displays, and a corresponding parallel RGB interface is provided. However, the method of the present invention can also be used for purely monochrome active matrix displays, in which case the data lines for transferring color information of the parallel RGB interface are usually R0, R1, R2, ... R in the case of a color display. n , G0, G1, G2, … G n , B0, B1, B2, … B n Instead of D0, D1, D2, …D n It is called.

[0021] The hardware SPI serially transmits the RGB image dataset, constructed automatically by the program, to the display via its data output (MOSI; English: master out, slave in).

[0022] To synchronize data transfer to the active matrix display, the SPI clock output (SCK) controls the pixel clock input (PCLK) of the active matrix display. To achieve this, as part of a hardware setup including the microcontroller required to perform the method and the desired active matrix display, the SPI clock output (SCK) of the microcontroller must be connected to the pixel clock input (PCLK) of the active matrix display.

[0023] Other signals such as the horizontal synchronization pulse (HSYNC), vertical synchronization pulse (VSYNC), and data enable signal (DE) are also generated by the program, i.e., provided by the program, so no special pins are required and only simple GPIOs on the microcontroller can be used. The program tracks the horizontal and vertical position in the data stream and controls the HS, VS, and DE signals accordingly. The pixel clock input (PCLK) is used as the transfer pulse for loading color information onto the display, and in the method described here, the SPI clock line (SCK) of the microcontroller's hardware SPI peripheral is connected directly to the pixel clock input (PCLK) as already mentioned.

[0024] The color information is provided directly from the data output of the hardware SPI peripheral (MOSI). In the simplest case, all color inputs of the display are connected together and to the MOSI pin of the microcontroller. The display operates in pure monochrome as a black-and-white display. However, by appropriately connecting the color inputs of the display, the display can also operate as a monochrome color display instead of a black-and-white display, for example a black-and-red display or a black-and-yellow display, and in particular any color within the color depth palette of the display. In the further description of advantageous variants of the invention, alternative configurations for connecting and / or controlling the color inputs of the display are described below, according to which any color display instead of a monochrome display is also possible.

[0025] As a further development of the method, the program stored on the program storage device, when executed for emulation of a parallel RGB interface, can automatically add to the image data any additional blanking data required according to predetermined specifications.

[0026] Such addition can be achieved in particular by inserting blanking data into the serial data stream of image data section by section according to a row-by-row and column-by-column grid.

[0027] In order to partially insert blanking data into the serial data stream, the program may be configured to automatically insert a number of dummy bytes corresponding to the specifications of the parallel RGB interface into the data stream of image data. The dummy bytes can be provided by configuring the program to read specified bytes from a predetermined memory location in the data storage device and automatically copy the read bytes to the corresponding locations in the data stream of image data to generate the required blanking data. Based on the known display specifications of the parallel RGB interface, the length of the image row data, i.e., the number of pixels per row of the image to be displayed, and the length of the image column data, i.e., the number of pixels per column of the image to be displayed, are known. Therefore, the blanking data or dummy bytes can be inserted in sections at appropriate positions in the serial data stream of image data.

[0028] A program stored in the program storage device may automatically synchronize and generate synchronization signals (HSYNC, VSYNC, Data-Enable) required for synchronous reading of the data stream of image data to the active matrix display (AMD), and the synchronization signals are sent to the active matrix display (AMD) via the GPIO of the microcontroller.

[0029] This program supplies the necessary synchronization signals at the necessary times according to the specifications of the parallel RGB interface. The horizontal synchronization signal can be supplied, for example, from the first GPIO of the microcontroller. The vertical synchronization signal can be supplied, for example, from the second GPIO of the microcontroller. The data-enable signal can be supplied, for example, from the third GPIO of the microcontroller. As is well known to those skilled in the art, each GPIO is a general-purpose input / output pin on a microcontroller port. For example, the GPIO can be used as a digital input or output.

[0030] As described above, in a first embodiment of the method, one or more RGB inputs of an active-matrix display are connected to each other and jointly connected to the data output (MOSI) of the hardware SPI peripheral. In this case, the data output (MOSI) of the hardware SPI peripheral independently controls one connected RGB input of the active-matrix display, or the data output (MOSI) of the hardware SPI peripheral jointly controls multiple connected RGB inputs of the active-matrix display. For example, if a single pin of an 8-bit color channel, i.e., the red channel, the green channel, or the blue channel, is connected to the data output (MOSI) of the hardware SPI peripheral, an image read from a data storage device is displayed on the connected active-matrix display in the respective color tone, i.e., a specific red, a specific green, or a specific blue. Accordingly, the connection can be hard-wired so that this color setting is not programmable, i.e., cannot be changed without structural intervention.

[0031] Depending on the type and number of RGB color channel pins connected to the hardware SPI peripheral data output (MOSI), any color can be selected from a color palette corresponding to the display's parallel RGB interface specifications.

[0032] Alternatively or additionally, in a second embodiment of the method, the data stream provided via the data output (MOSI) may be passed through an inverter (complement gate) before being supplied to one or more RGB inputs of the active matrix display (AMD) to set a particular color tone. Alternatively or additionally, it is optionally possible to set various pins of each 8-bit color channel to "0" instead of "1", for example, to be able to set a particular color value.

[0033] Alternatively or additionally, in a third embodiment of the method, the data stream provided via the data output (MOSI) may be supplied to a first input of each of one or more AND gates, and the program may provide control data for masking the data stream via at least one additional GPIO of the microcontroller, which GPIO is connected to a second input of each of the one or more AND gates, so that the desired RGB values are automatically set by controlling the at least one AND gate via a program stored in a program storage device before the masked data stream is supplied to one or more RGB inputs of the active matrix display (AMD). In this manner, for example, the program can set one or more pins of each 8-bit color channel to "1" or "0." The color channel pins controlled by the data output (MOSI) of the hardware SPI peripheral can thus be switched at any time as desired by the program to select or activate a different color for display on the active matrix display. Such programmable switching can be performed not only for each displayed frame, but also within a frame, allowing the display color to be freely changed, for example, after one or more rows of a frame, or in the middle of a row, e.g., one or more columns to be displayed in a particular color, or the color to be switched pixel by pixel, as in an active matrix display.

[0034] To achieve this particular embodiment, a program stored in the program storage device may be configured, when executed, to automatically switch at least one AND gate in time synchronization with the data stream, in particular based on a signal at the SPI clock output (SCK), in order to change the color displayed on an active matrix display (AMD) column by column, row by row or pixel by pixel.

[0035] In another possible embodiment, instead of sending the RGB image data set directly to the active matrix display, it may be sent to an interface converter which converts the data stream of the RGB image data set into a modified data stream for another display interface, in particular a modified data stream for a non-parallel RGB interface, for example a modified data stream for an LVDS interface, and the converted data stream may be supplied as the image data set to the active matrix display, in particular an active matrix display having an interface different from the parallel RGB interface.

[0036] This object is also achieved by a control device according to the invention, which control device comprises: - a data storage device for storing image data at a color depth of 1 bit per pixel for an image to be displayed on the active matrix display; - a microcontroller having a program storage device storing a program configured and set up to perform one or more of the methods described above, the microcontroller controlling a DMA controller controlled by the program and a hardware SPI connected to the DMA controller, the microcontroller comprising: - controlling the DMA controller to transfer the RGB image data set generated by the program to a hardware SPI connected to the DMA controller, so that the hardware SPI can serially transmit the RGB image data set to an active matrix display via its data output; - Here, the SPI clock output of the microcontroller is connected to the pixel clock input of the active matrix display to synchronize the data transfer to the active matrix display.

[0037] The microcontroller can be any standard microcontroller, such as an Arm Cortex-Mx IP-Core with a RISC architecture. Alternatively, an Arm Cortex-Ax IP-Core, which is already widely used in smartphones, mobile computers, and digital televisions, can be used. No special display controllers, such as those of type SSD2119 or FT800, are required. No special timing generators, such as those found in CPLDs or FPGAs, are also required.

[0038] The DMA controller may also be part of a microcontroller having a program storage device on which a program for configuring and setting up the execution of the method is stored.A hardware SPI connected to the DMA controller may also be part of a microcontroller having a program storage device on which a program for configuring and setting up the execution of the method is stored.

[0039] The microcontroller together with the DMA controller and the control device including the hardware SPI connected thereto can form a display assembly when connected to a selected active matrix display, in particular by connecting the SPI clock output of the hardware SPI peripheral to the pixel clock input of the active matrix display.

[0040] In a display assembly, a first GPIO port of the microcontroller may be connected to an HSYNC port of an active matrix display to transmit a horizontal synchronization signal. A second GPIO port of the microcontroller may be connected to a VSYNC port of the active matrix display to transmit a vertical synchronization signal. A third GPIO port of the microcontroller may be connected to a Data-Enable port of the active matrix display to transmit a Data-Enable signal. Each GPIO is a general-purpose input / output pin on a port of the microcontroller, as known to those skilled in the art. For example, a GPIO can be used as a digital input or output.

[0041] In a display assembly, one or more RGB inputs of an active matrix display (AMD) may be connected together and commonly connected to the data output (MOSI) of a hardware SPI peripheral of a microcontroller.

[0042] In the display assembly, if desired, the microcontroller's data output (MOSI) may be connected to an inverter (complement gate) and the inverter output may be connected to one or more RGB inputs of the active matrix display.

[0043] In the display assembly, if desired, the data output (MOSI) of the microcontroller may be connected to a first input of each of one or more AND gates, thereby allowing the program to supply control data for masking the data stream via at least one additional GPIO of the microcontroller, which GPIO is connected to a second input of each of the AND gates, to automatically set desired RGB values by controlling the at least one AND gate by a program stored in the program storage device before the masked data stream is supplied to one or more RGB inputs of the active matrix display (AMD).

[0044] In the display assembly, instead of being directly connected to the active matrix display, the microcontroller may be connected at its input to an interface converter, whereby the data stream of RGB image data is converted into a modified data stream of another display interface, in particular a modified data stream of a non-parallel RGB interface, and the converted data stream is supplied as an image data set to the active matrix display, in particular an active matrix display having an interface different from the parallel RGB interface. In this respect, in such a modified display assembly, the interface converter is connected at its output to the active matrix display.

[0045] The invention also relates to a computer program product having a machine-readable carrier on which is stored a program code of a program readable by a control device as described above, the program code being readable by a control device as described above and which, when executed, configures and / or sets up the control device to perform one or more of the methods described above.

[0046] The machine readable carrier may for example comprise a memory module such as a ROM or EPROM, or may be a USB memory stick, a CD, a CD-ROM, a DVD, etc. Alternatively, the machine readable carrier may be a data storage device on the server configured and arranged to read the program from a data storage device on the server upon request, make a copy of the data, and send the copy to the requesting client for storage on the data storage device of the client computer.

[0047] Specific embodiments of the present invention are described in more detail in the following description with reference to the accompanying figures. Specific features of these exemplary embodiments may be taken individually or in further combinations, regardless of the particular context in which they are mentioned, and may represent generalized features of the present invention. [Brief explanation of the drawings]

[0048] The drawings show: [Figure 1] FIG. 1 is a schematic diagram of a first exemplary embodiment of a control device or display assembly for implementing a method according to the present invention, in which the hardwired RGB inputs of an active matrix display are connected to the SPI data output (MOSI) of a microcontroller, and the data storage is internal RAM. [Figure 2] FIG. 1 is a schematic diagram of a first exemplary embodiment of a control device or display assembly for implementing a method according to the present invention, in which the hardwired RGB inputs of an active matrix display are connected to the SPI data output (MOSI) of a microcontroller, and the data storage is external RAM. [Figure 3] Schematic diagram of a second exemplary embodiment of a control device or display assembly for implementing a method according to the present invention, in which the representative RGB input for green of the active matrix display is connected to the data output of the microcontroller via an inverter, and the representative RGB input for red of the active matrix display is set to level "0". [Figure 4] FIG. 10 is a schematic diagram of a third exemplary embodiment of a control device or display assembly for implementing a method according to the present invention, in which the RGB inputs of a representative active matrix display for green and red are connected to the data outputs of a microcontroller via inverters, respectively. [Figure 5]FIG. 10 is a schematic diagram of a fourth exemplary embodiment of a control device or display assembly for implementing a method according to the present invention, in which the RGB inputs of representative active matrix displays for blue, green and red are each connected to the data outputs of a microcontroller via AND gates, and the AND gates are controlled via separate GPIOs. [Figure 6] FIG. 10 is a schematic diagram of a fifth exemplary embodiment of a control device and display assembly for implementing a method according to the present invention, in which a microcontroller is connected to the input of an interface converter, and the output of the interface converter is connected to an active matrix display. [Figure 7] Schematic diagram of the structure of image data and blanking data corresponding to the parallel RGB interface specification. [Figure 8] Schematic diagram of the horizontal timing for the parallel RGB interface. [Figure 9] Schematic diagram of the vertical timing for the parallel RGB interface. [Figure 10] 1 is a flow chart of the basic method steps according to the present invention. [Figure 11] Schematic diagram of an 8-bit color channel of an RGB input of an exemplary active matrix display. [Figure 12] Schematic diagram of the state machine H_STATE for generating horizontal synchronization signals and transferring image data. [Figure 13] Schematic diagram of the state machine V_STATE for generating the vertical synchronization signal. [Figure 14] 1 is a schematic diagram of a flow diagram for generating a horizontal synchronization signal HSYNC. [Figure 15] 1 is a schematic diagram of a flow diagram for generating a vertical synchronization signal VSYNC. [Figure 16] 1 is a schematic diagram of a flow diagram for generating a synchronization signal DATA-ENABLE. DETAILED DESCRIPTION OF THE INVENTION

[0049] 1 to 6 show various exemplary implementations of a control device 1 according to the invention, which are capable of carrying out the method according to the invention.

[0050] Each control device 1 comprises a data store 2 (RAM) for storing image data at a color depth of 1 bit per pixel. Each control device 1 comprises a microcontroller 3 connected in the manner of the present invention to an active matrix display 4.

[0051] The microcontroller 3 further comprises a program storage device 5 (PRG) having stored therein a program configured and set to carry out the method of the present invention, and the microcontroller 3 controls a DMA controller 6 controlled by the program and a hardware SPI 7 connected to the DMA controller 6, so that the DMA controller 6 can transfer an RGB image dataset generated by the program to the hardware SPI 7 connected to the DMA controller 6, so that the RGB image dataset can be transmitted in a serial manner to the active matrix display 4 via the SPI data output MOSI of the microcontroller, wherein the SPI clock output SCK of the microcontroller 3 is connected to the pixel clock input PCLK of the active matrix display 4 for synchronizing the data transfer to the active matrix display 4.

[0052] DMA controller 6 may be part of microcontroller 3 as shown, and its program storage device 5 may store a program configured and configured to carry out the method. A hardware SPI peripheral 7 connected to DMA controller 6 may also be part of microcontroller 3, and its program storage device may store a program configured and configured to carry out the method.

[0053] The microcontroller 3, DMA controller 6 and connected hardware SPI 7 can form a display assembly when connected to a selected active matrix display 4. In the display assembly, in particular, the SPI clock output SCK of the hardware SPI 7 can be connected to the pixel clock input PCLK of the active matrix display 4.

[0054] In the display assembly, a first GPIO port GPIO_1 of the microcontroller 3 may be connected to an HSYNC port of the active matrix display 4 to transmit a horizontal synchronization signal. A second GPIO port GPIO_2 of the microcontroller 3 may be connected to a VSYNC port of the active matrix display 4 to transmit a vertical synchronization signal. A third GPIO port GPIO_3 of the microcontroller 3 may be connected to a DATA_ENABLE port of the active matrix display 4 to transmit a data enable signal. Each GPIO is a general-purpose input / output pin at a port of the microcontroller 3, as is well known to those skilled in the art. For example, a GPIO can be used as a digital input or output.

[0055] In a display assembly, one or more RGB inputs of the active matrix display 4 may be connected together via connections 8 and jointly connected to a line 9 leading to a data output MOSI of the hardware SPI peripheral 7 of the microcontroller 3, as shown in particular in Figures 1 and 2.

[0056] In order to synchronize the data transfer to the active matrix display 4, the SPI clock output SCK controls the pixel clock input PCLK of the active matrix display 4. To enable this, as part of the hardware structure comprising the microcontroller 3 and the desired active matrix display 4 required to carry out the method, the SPI clock output SCK of the microcontroller 3 is connected by a fixed line 17 to the pixel clock input PCLK of the active matrix display 4.

[0057] In the display assembly, the SPI data output MOSI of the microcontroller 3 may also be connected via line 10 to an inverter 11 (complement gate) if desired, where the output of the inverter 11 is connected via line 12 to one or more RGB inputs of the active matrix display 4. In FIG. 3, for example, the inverter 11 is connected only to the color inputs for green (G0, G1, G2, ..., etc.) via one or more lines 12. The color inputs for red (R0, R1, R2, ..., etc.) are always set to "0" by line 13.

[0058] On the other hand, in FIG. 4, for example, two inverters 11.1 and 11.2 are provided, the first inverter 11.1 being connected to a color input for red (R0, R1, R2, etc.) via one or more first lines 12.1, and the second inverter 11.2 being connected to a color input for green (G0, G1, G2, etc.) via one or more second lines 12.2.

[0059] FIG. 5 shows in a modified embodiment how in a display assembly the SPI data output MOSI of the microcontroller 3 should be connected to a respective first input 14.1 of one or more AND gates 15, whereby a program can supply control data via, for example, three additional GPIOs (GPIO_4, GPIO_5, GPIO_6) of the microcontroller 3, which are connected to a respective second input 14.2 of each AND gate 15, for masking the data stream, before the masked data stream is supplied to one or more RGB inputs (R0, R1, R2, etc., G0, G1, G2, etc., B0, B1, B2, etc.) of the active matrix display 4, thereby automatically setting the desired RGB values by controlling at least one AND gate 15 by a program stored in the program storage device 5.

[0060] 6, in the display assembly, instead of being directly connected to the active matrix display 4, the microcontroller 3 may also be connected on the input side to an interface converter 16, whereby the data stream of RGB image data is converted into a modified data stream of another display interface, in particular a modified data stream of a non-parallel RGB interface, and the converted data stream is supplied as an image data set to the active matrix display 4, in particular an active matrix display 4 having an interface different from the parallel RGB interface. In this respect, in the case of such a modified display assembly, the interface converter 16 is connected on the output side to the active matrix display 4.

[0061] Figure 7 shows a schematic diagram of the structure of image data (pixels Pxl(0,0) to Pxl(x-1,y-1)) and blanking data corresponding to the specifications of a parallel RGB interface. This method uses a hardware SPI peripheral 7 and a DMA controller 6 peripheral module included in a microcontroller 3 to emulate a parallel RGB interface for controlling an active matrix display 4. The microcontroller 3 only needs to have sufficient RAM or ROM memory (internal or external) to store the display image or a portion of it with a color depth of 1 bit per pixel. This data storage device 2 is also referred to as a frame buffer below. In this method, for example, an active matrix display 4 with a resolution of 320 x 240 pixels only needs a 9.6 kB frame buffer. Here, the DMA controller 6 is used to directly send the frame buffer to the hardware SPI peripheral 7 module. This transmission is controlled by an interrupt set by a software algorithm or microcontroller program, according to which the hardware SPI peripheral 7 transmits user data as well as the necessary blanking data (also called black shoulders or porches) that the parallel RGB interface must provide for synchronization of the active-matrix display 4. Blanking data is transmitted before and after each visible row of data (horizontal front and back porches) and before and after each visible column of data (vertical front and back porches). Therefore, according to the parallel RGB interface specifications, the displayed image is surrounded by an invisible border. During this period, a "black" color value is transmitted. The parallel RGB interface's data enable signal (DE for short) indicates whether the currently transmitted signal is for the visible or invisible portion. Furthermore, this interface requires a horizontal synchronization pulse (HSYNC line, abbreviated as HS) before each row of data and a vertical synchronization pulse (VSYNC line, abbreviated as VS) before each image, as shown in Figures 8 and 9.This results in four regions horizontally and four regions vertically, the duration of which, and therefore the number of pixels transmitted, depends on the active matrix display 4 being controlled.

[0062] FIG. 10 shows a flow chart of a method for controlling the active matrix display 4.

[0063] In a first step S1, image data at a colour depth of 1 bit per pixel of the image to be displayed on the active matrix display 4 is loaded into the data store 2.

[0064] In a second step S2, a program stored in the program storage device 5 of the microcontroller 3 is executed, and this program controls the DMA controller 6 to read image data with a color depth of 1 bit per pixel from the data storage device 2, and blanking data corresponding to the specifications of the parallel RGB interface is added by the program to the read image data with a color depth of 1 bit per pixel, thereby generating an RGB image data set (frame) that can be read by the active matrix display 4.

[0065] In a third step S3, the RGB image data set generated by the program is transferred by the DMA controller 6 to a hardware SPI 7 connected to the DMA controller 6, and the RGB image data set is transmitted serially to the active matrix display 4 via the SPI data output MOSI, and the SPI clock output SCK controls the pixel clock input PCLK of the active matrix display 4 to synchronize the data transfer of the active matrix display 4.

[0066] The first step S1 of the method, the second step S2 of the method, and the third step S3 of the method do not necessarily have to be performed sequentially and separately. Rather, steps S1, S2, and / or S3, or substeps of each, can be performed simultaneously, staggered in time, and / or in a different order; in particular, the insertion of blanking data can be performed on the fly, for example, when horizontal sync, horizontal back porch, and horizontal front porch are added to the visible image data during transmission of image row data.

[0067] FIG. 11 shows a schematic diagram of 8-bit color channels of the RGB input of an exemplary active-matrix display 4. For clarity, in FIGS. 1-6, only a single line (R0, R1, R2, etc., G0, G1, G2, etc., B0, B1, B2, etc.) is shown for each color channel (red, green, blue). Of course, depending on the color depth of the selected active-matrix display, there will be a defined number of multiple lines for each color channel (red, green, blue), each of which can be individually wired according to the described configuration, for example, hardwired as shown in FIGS. 1 and 2, connected via inverter 11 as shown in FIGS. 3 and 4, and / or connected via AND gate 15 as shown in FIG. 5. FIG. 11 shows the input of RGB color channels for an 8-bit color depth per pixel as a representative example. This means that there may be eight input lines (R0, R1, R2, R3, R4, R5, R6, R7, G0, G1, G2, G3, G4, G5, G6, G7, B0, B1, B2, B3, B4, B5, B6, B7) for each of the red, green, and blue primary colors. Each of the eight input lines can be connected in the same way or in different ways.

[0068] FIG. 12 shows an example of a state machine H_STATE for generating a horizontal synchronization signal and transferring image data.

[0069] The state machine (H_STATE) for generating horizontal synchronization signals and transferring image data performs the following tasks:

[0070] When the required number of transferred image dots (THS, THB, THD, or THE) is reached depending on the current state (H_SYNC, H_BACK, H_DATA, or H_FRONT), the state changes to the next state. The DMA controller 6 is responsible for counting the transferred image dots. Each state change of H_STATE is preceded by the completion of one or more DMA transfer processes. The state machine H_STATE is controlled by the progress of the DMA controller 6. The horizontal timing of the emulated parallel RGB interface is specified by the parameters THS, THB, THD, and THF. These values must be adjusted to suit the display being used. If the state machine H_STATE is in state H_DATA and V_STATE is in state V_DATA, the DMA controller 6 transfers visible image data from the frame buffer to the hardware SPI peripheral 7. Otherwise, blanking data is transferred depending on H_STATE and V_STATE. For this purpose, the DMA controller 6 sends the required number of dummy data (0x00) to the hardware SPI peripheral 7. Each time state H_FRONT is exited, one complete row of data is transferred, after which the row counter is incremented, controlling the state machine V_STATE.

[0071] FIG. 13 shows an example of a state machine V_STATE for generating a vertical synchronization signal.

[0072] The state machine V_STATE for generating the vertical synchronization signal performs the following tasks:

[0073] Depending on the current state (V_SYNC, V_BACK, V_DATA, or V_FRONT), a change to the next state occurs when the corresponding number of lines in the line counter (TVS, TVB, TVD, or TVF) is reached. Before each state change of V_STATE, the line counter is reset. The state machine V_STATE is controlled by the line counter and can only reset it. The line counter is incremented by the state machine H_STATE. The vertical timing of the emulated parallel RGB interface is specified by the parameters TVS, TVB, TVD, and TVF. These values must be adjusted to suit the display used. Each time state V_FRONT is left, one complete image is transferred. Afterwards, it is therefore useful to reset the frame buffer data pointer or set a new image source.

[0074] FIG. 14 shows an example of a flowchart H_SYNC for generating the horizontal synchronization signal H_SYNC.

[0075] The logic level of the signal H_SYNC is often "low active."

[0076] FIG. 15 shows an example of a flowchart V_SYNC for generating the vertical synchronization signal V_SYNC.

[0077] The logic level of the signal V_SYNC is often "low active."

[0078] FIG. 16 shows an example of a flowchart DATA_ENABLE for generating the synchronization signal DATA_ENABLE.

[0079] The logic level of the DATA_ENABLE signal is often "active high."

Claims

1. A method for controlling an active matrix display (4), comprising: - loading into a data store (2) image data of an image to be displayed on an active matrix display (4) with a color depth of 1 bit per pixel; - executing a program stored in a program storage device (5) of a microcontroller (3), the program controlling a DMA controller (6) to read the image data with a color depth of 1 bit per pixel from the data storage device (2), the program extending the read image data with a color depth of 1 bit per pixel with additional blanking data corresponding to the specifications of a parallel RGB interface to generate an RGB image data set (frame) that can be read by the active matrix display (4); - transferring the RGB image data set generated by the program using the DMA controller (6) to a hardware SPI (7) connected to the DMA controller (6), which sends the RGB image data set serially to the active matrix display (4) via its data output (MOSI), wherein an SPI clock output (SCK) controls a pixel clock input (PCLK) of the active matrix display (4) for synchronizing the data transfer to the active matrix display (4); A method comprising:

2. 2. The method of claim 1, wherein the program stored in the program storage device (5), when executed for emulating a parallel RGB interface, automatically adds to the image data additional blanking data required according to a predetermined specification, in particular the blanking data is inserted section by section into the serial data stream of the image data according to a row-by-row and column-by-column grid, in particular the program automatically inserts a number of dummy bytes into the data stream of the image data corresponding to the specification of the parallel RGB interface.

3. 3. The method according to claim 1 or 2, characterized in that the program stored in the program storage device (5) automatically synchronously generates synchronization signals (HSYNC, VSYNC, Data-Enable) required for synchronous reading of a data stream of image data to the active matrix display (4) and transmits the synchronization signals to the active matrix display (4) via a GPIO of the microcontroller (3).

4. 4. The method according to claim 1, wherein one or more RGB inputs of the active matrix display (4) are connected together and jointly to a data output (MOSI) of a hardware SPI peripheral (7).

5. 5. The method according to claim 1, wherein the data stream provided via the data output (MOSI) is passed through an inverter (11) before being supplied to one or more RGB inputs of the active matrix display (4).

6. 6. The method according to claim 1, wherein the data stream provided via the data output (MOSI) is supplied to a first input of each of one or more AND gates (15), and the program supplies control data for masking the data stream via at least one additional GPIO of the microcontroller (3), which GPIO is connected to a second input of each of the one or more AND gates (15), and wherein the desired RGB values are automatically set by controlling at least one AND gate (15) by a program stored in the program storage device (5) before the masked data stream is supplied to one or more RGB inputs of the active matrix display (4).

7. 7. The method of claim 6, wherein the program stored in the program storage device (5) automatically switches at least one of the AND gates (15) when executed in time synchronization with the data stream, in particular based on the signal of the SPI clock output (SCK), in order to change the color displayed on the active matrix display (4) column by column, row by row or pixel by pixel.

8. 8. The method according to claim 1, further comprising transmitting the RGB image data set to an interface converter (16) instead of transmitting the data stream of the RGB image data set directly to the active matrix display (4), which converts the data stream of the RGB image data set into a modified data stream of another display interface, in particular a modified data stream of a non-parallel RGB interface, and the converted data stream is supplied as an image data set to the active matrix display (4), in particular to an active matrix display (4) having an interface different from a parallel RGB interface.

9. a data storage device (2) for storing image data at a color depth of 1 bit per pixel of an image to be displayed on an active matrix display (4); a microcontroller (3) having a program storage device (5) storing a program configured and set to perform the method of any one of claims 1 to 8, said microcontroller (3) controlling a DMA controller (6) controlled by said program and a hardware SPI (7) connected to said DMA controller (6), so that an RGB image data set generated by said program is transferred by said DMA controller (6) to said hardware SPI (7) connected to said DMA controller (6), and said hardware SPI (7) is able to serially transmit said RGB image data set via its data output to said active matrix display (4), wherein an SPI clock output (SCK) of said microcontroller (3) is connected to a pixel clock input (PCLK) of said active matrix display (4) for synchronizing the data transfer to said active matrix display (4); A control device comprising:

10. 10. A computer program product having a machine-readable carrier on which is stored a program code of a program readable by a control device according to claim 9, the program code being for configuring and / or setting up the control device when the program is executed to perform a method according to any one of claims 1 to 8.

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