DELAY CALIBRATION DEVICE AND DELAY CALIBRATION METHOD

Abstract

The present disclosure provides a delay calibration apparatus including a delay calibration module, the delay calibration module including a coarse delay calibration unit and a fine delay calibration unit, the coarse delay calibration unit configured to receive an air interface pulse signal and perform delay compensation on a channel associated pulse signal in a digital clock domain based on the air interface pulse signal, the fine delay calibration unit including a fine delay calibration subunit and a phase calibration subunit, the fine delay calibration subunit configured to perform delay compensation on the channel associated pulse signal in an analog clock domain, and the phase calibration subunit configured to calibrate the phase of the clock domain. The present disclosure further provides a delay calibration method.

Description

[Technical Field]

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS] This disclosure claims priority to a Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on August 31, 2022, bearing publication number CN202211058378.8 and entitled "Delay calibration device and delay calibration method," the entire contents of which are incorporated herein by reference. [Technical field] TECHNICAL FIELD Embodiments of the present disclosure relate to, but are not limited to, the technical field of communications, and specifically to a delay calibration apparatus and a delay calibration method. [Background technology]

[0002] In recent years, 5G communications have rapidly developed, and technologies such as Massive MIMO (large-scale antenna technology) and GPS 1PPS (Global Positioning System Pulse Per Second) time signaling have improved system capacity and clock accuracy. Accordingly, the demand for accurate digital link delay in radio frequency transmission and reception systems has also increased. However, due to limitations such as asynchronous processing of clock domain crossing in the digital link, differences in reset path length, and changes in integrated circuit process characteristics (e.g., process corner, power supply voltage, and temperature, collectively referred to as PVT), there are differences in digital link delay during initial power-on and operation. These differences are expressed in the product's multi-antenna configuration, requiring data alignment processing.

[0003] Currently, the method used for this process involves constructing special excitation data, two-point sampling digital link data, analyzing it based on a correlation algorithm to obtain the data link transmission delay, and then calibrating and aligning the data. However, the delay calibration accuracy of the two-point sampling link is limited, and the entire algorithm analysis process is complex and cumbersome, and the cost is high. Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides a delay calibration apparatus and a delay calibration method. [Means for solving the problem]

[0005] According to a first aspect, an embodiment of the present disclosure provides a delay calibration device including a delay calibration module, the delay calibration module including a coarse delay calibration unit and a fine delay calibration unit. The coarse delay calibration unit is configured to receive an air interface pulse signal and perform delay compensation on a channel associated pulse signal in a digital clock domain based on the air interface pulse signal. The fine delay calibration unit includes a fine delay calibration subunit and a phase calibration subunit. The fine delay calibration subunit is configured to perform delay compensation on the channel associated pulse signal in an analog clock domain after the coarse delay calibration unit performs delay compensation on the channel associated pulse signal in the digital clock domain based on the air interface pulse signal, and the phase calibration subunit is configured to calibrate a phase of the clock domain after the fine delay calibration subunit performs delay compensation on the channel associated pulse signal in the analog clock domain.

[0006] According to another aspect, an embodiment of the present disclosure further provides a delay calibration method applicable to the delay calibration apparatus as described above, the method including: receiving an air interface pulse signal; and performing delay compensation on a channel associated pulse signal in a digital clock domain based on the air interface pulse signal; and performing delay compensation on the channel associated pulse signal in an analog clock domain to calibrate a phase of the clock domain. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic diagram illustrating a configuration of a delay calibration module in a delay calibration device according to an embodiment of the present disclosure. [Figure 2] 1 is a diagram illustrating an overall schematic configuration of a delay calibration device according to an embodiment of the present disclosure. [Figure 3] FIG. 10 is a schematic diagram of a second delay calibration module according to an embodiment of the present disclosure. [Figure 4] FIG. 1 is a schematic diagram of an RX link delay calibration sequence according to an embodiment of the present disclosure. [Figure 5] FIG. 2 is a schematic diagram of a first delay calibration module according to an embodiment of the present disclosure. [Figure 6] FIG. 1 is a schematic diagram of a TX link delay calibration sequence according to an embodiment of the present disclosure. [Figure 7] FIG. 1 is a schematic configuration diagram of a gate_pluse differential circuit according to an embodiment of the present disclosure. [Figure 8] FIG. 10 is a schematic diagram of a gate_pluse differential circuit sequence according to an embodiment of the present disclosure. [Figure 9] 1 is a flowchart of a delay calibration method according to an embodiment of the present disclosure. [Figure 10] 10 is a flowchart illustrating a delay compensation process for a channel associated pulse signal in a transmission link according to an embodiment of the present disclosure. [Figure 11]10 is a flowchart illustrating a delay compensation process for a channel associated pulse signal in a receiving link according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0008] The following examples are more fully described with reference to the drawings, but the illustrative examples may be embodied in different forms and are not limited to the examples set forth herein. Rather, the purpose of providing these examples is so that this disclosure will be clear and complete, and that those skilled in the art will fully appreciate the scope of the disclosure.

[0009] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0010] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural unless the context clearly dictates otherwise. It will be further understood that the use of the terms "comprising" and / or "made from" herein specifies the presence of said features, wholes, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0011] The embodiments described herein may be described with reference to plan views and / or cross-sectional views in accordance with idealized schematic diagrams of the present disclosure. Therefore, the exemplary illustrations may vary based on manufacturing techniques and / or tolerances. Therefore, the embodiments are not limited to the illustrated examples, but include variations in configurations formed based on manufacturing steps. Therefore, the illustrated exemplary regions have exemplary attributes, and the shapes of the illustrated regions indicate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0012] Unless otherwise specified, the meaning of all terms (including technical and scientific terms) used herein is the same as that commonly understood by those skilled in the art. It is further understood that, unless expressly limited herein, those terms, for example, those limited to their common dictionary definitions, should be interpreted as having a meaning consistent with the relevant art and meaning in the context of this disclosure, and not as having an ideal or excessively formal meaning.

[0013] In the related art, when delay calibration is performed by performing two-point sampling on digital link data, there are the following drawbacks.

[0014] 1. The accuracy of link delay calibration is limited. In the conventional two-point synchronous sampling method, when a clock domain crossing occurs in a link, there is an uncertainty in the clock cycle accuracy of the clock domain. In addition, since sampling is performed in a digital clock domain, the clock frequency is low and there is a time difference of a single clock cycle.

[0015] 2. The entire algorithm analysis process is complex, tedious, and costly. First, different systems and digital links require different scenarios for data processing methods, requiring the construction and processing of corresponding excitation data. Second, offline analysis makes it impossible to realize immediate product application. Online analysis consumes a large amount of software and hardware resources, significantly increasing power consumption. Finally, both the initialization correction during the power-on process and the re-correction during normal operation take a long time, which is unfavorable for quickly completing the system's high-precision timekeeping.

[0016] To solve the above problem, an embodiment of the present disclosure provides a delay calibration apparatus, which includes a delay calibration module. Figure 1 is a schematic configuration diagram of the delay calibration module in the delay calibration apparatus according to the embodiment of the present disclosure. As shown in Figure 1, the delay calibration module includes a coarse delay calibration unit 10 and a fine delay calibration unit 20. The coarse delay calibration unit 10 is configured to receive an air interface pulse signal (ref_pluse) and perform delay compensation on a channel associated pulse signal (data_pluse) in a digital clock domain based on the air interface pulse signal (ref_pluse).

[0017] The fine delay calibration unit 20 includes a fine delay calibration subunit 21 and a phase calibration subunit 22, and the fine delay calibration subunit 21 is configured to perform delay compensation on the channel associated pulse signal in the analog clock domain after the coarse delay calibration unit 22 performs delay compensation on the channel associated pulse signal in the digital clock domain based on the air interface pulse signal.

[0018] The phase calibration subunit 22 is configured to calibrate the phase of the clock domain after the fine delay calibration subunit 21 performs delay compensation on the channel associated pulse signal in the analog clock domain.

[0019] The air interface pulse signal (ref_pluse) is generated by dividing the GPS 1PPS signal, and is typically an integer multiple of the T period, maintaining a high level for a fixed period. The channel association pulse signal (data_pluse) has the same period as the air interface pulse signal, and maintains a high level for one period of the corresponding clock domain.

[0020] The delay calibration device according to the embodiment of the present disclosure uses an air interface pulse signal as a reference, performs delay compensation in the digital clock domain, and performs phase calibration in the analog high-frequency clock domain, thereby improving the delay calibration accuracy to two high-frequency clock cycles. Instead of the traditional algorithm analysis after two-point synchronous sampling, the delay of the channel-linked pulse signal and the digital clock phase in the digital clock domain are adjusted, which simplifies the calibration process, reduces the amount of algorithm calculation, and realizes high-speed and high-precision link timing. The overall structure of the delay calibration device is simple, and it can be adapted to multiple channels, multiple modes, and multiple operating scenarios.

[0021] 2 is a schematic diagram of an overall configuration of a delay calibration apparatus according to an embodiment of the present disclosure. As shown in FIG. 2, the delay calibration apparatus includes a transmission link (TX link), a delay calibration module includes a first delay calibration module (DAC calibration) 100, the first delay calibration module is located in the transmission link, the coarse delay calibration unit 10 is a first coarse delay calibration unit 101, the fine delay calibration unit 20 is a first fine delay calibration unit 201, and the channel associated pulse signal is a transmit channel associated pulse signal.

[0022] The transmit link (TX link) further includes a transmit channel associated pulse generation module 110 and a transmit link channel associated pulse transmission module 120. The transmit channel associated pulse generation module 110 is configured to receive an air interface pulse signal and generate a transmit channel associated pulse signal based on the air interface pulse signal.

[0023] The transmit link channel associated pulse transmission module 120 is configured to use a data valid enable signal to align and transmit the transmit channel associated pulse signal and link data within the multi-clock domain of the transmit link, and transmit them to the first coarse delay calibration unit 101 of the first delay calibration module 100.

[0024] The transmit channel associated pulse signal is generated in the transmit channel associated pulse signal generation module 110, passes through each clock domain of the TX link, and reaches the first delay calibration module (DAC calibration) 100 for calibration. When transmitting a signal, the transmit channel associated pulse signal and link data pass through multiple clock domains of the TX link together, and are transmitted aligned with the link data using a data valid enable signal, so that the transmit channel associated pulse signal can represent the delay status of link data transmission.

[0025] As shown in FIG. 2, the delay calibration device further includes a receive link (RX link), where the delay calibration module includes a second delay calibration module (ADC calibration) 200, where the second delay calibration module 200 is located in the receive link, the channel associated pulse signal is a receive channel associated pulse signal, the fine delay calibration unit 20 is a second fine delay calibration unit 202, and the coarse delay calibration unit 10 is a second coarse delay calibration unit 102, where the second coarse delay calibration unit 102 further receives an air interface pulse signal and then generates a receive channel associated pulse signal (rx_data_pluse) based on the air interface pulse signal.

[0026] The receive link (RX link) further includes a receive channel associated pulse calibration module 210 and a receive link channel associated pulse transmission module 220. The receive link channel associated pulse transmission module 220 is configured to align and transmit receive channel associated pulse signals and link data to the receive channel associated pulse calibration module 210 using a data valid enable signal within the multiple clock domains of the receive link.

[0027] The receive channel associated pulse calibration module 210 is configured to perform delay compensation on the received channel associated pulse signal in the digital clock domain based on the air interface pulse signal.

[0028] The receive channel associated pulse signal is generated in a second delay calibration module (ADC calibration) 200, passes through each clock domain of the RX link, and reaches the receive channel associated pulse calibration module 210 for calibration. During signal transmission, the receive channel associated pulse signal and link data pass through multiple clock domains of the RX link together, and are transmitted aligned with the link data using a data valid enable signal, so that the receive channel associated pulse signal can represent the delay status of link data transmission.

[0029] FIG. 3 is a schematic diagram of a second delay calibration module according to an embodiment of the present disclosure. As shown in FIG. 3, the second delay calibration module 200 includes a second coarse delay calibration unit (GEN_PLUSE) 102 and a second fine delay calibration unit (ADC_FT_PLUSE) 202.

[0030] The second coarse delay calibration unit 102 includes a second air interface pulse processing subunit (posedge0), a second channel associated pulse signal regeneration subunit (regen2), a second delay subunit (delay2), and a second coarse delay calibration subunit (ct_g). The second air interface pulse processing subunit (posedge0) is configured to generate a single-period air interface pulse signal based on the rising edge of the air interface pulse signal (ref_pluse).

[0031] The second channel associated pulse signal regeneration subunit (regen) is connected to the second air interface pulse processing subunit (posedge0) and the second delay subunit (delay2), and is configured to reduce the single-period air interface pulse signal transmitted from the second air interface pulse processing subunit (posedge0) by a predetermined multiple with the same ratio period to generate a regenerated received channel associated pulse signal, and transmit the regenerated received channel associated pulse signal to the second delay subunit (delay2). The period T and the predetermined multiple N of the air interface pulse signal are preset in the second channel associated pulse signal regeneration subunit (regen), and the loop-regenerated received channel associated pulse signal is generated according to the period T and the predetermined multiple N of the air interface pulse signal.

[0032] The second delay subunit (delay2) is configured to remove the delay between the recovered received channel associated pulse signal and the next air interface pulse signal to obtain a second signal, where the second signal is the recovered received channel associated pulse signal from which the delay has been removed. The second delay subunit (delay2) sets a delay close to the period T of the air interface pulse signal, and then performs successive approximation by increasing the delay by one beat each time. FIG. 4 is a schematic diagram of an RX link delay calibration sequence according to an embodiment of the present disclosure. As shown in FIG. 4, in this case, the delay difference Rd1 between the received channel associated pulse signal (i.e., the second signal) and the next air interface pulse signal is the asynchronous sampling uncertainty delay.

[0033] The second coarse delay calibration subunit (ct_g) is configured to perform a logical AND operation on the second signal and the single-period air interface pulse signal, and perform coarse delay calibration if the operation result is not 1, and stop the operation until the operation result is 1, and generate a second indication signal (gen_int_flag) that instructs the second fine delay calibration unit 202 to perform fine delay calibration. The second coarse delay calibration subunit (ct_g) triggers a coarse delay calibration interrupt every time a rising edge of the air interface pulse signal occurs, and generates ct_int_flag until the logical AND operation result between the channel association pulse signal and the air interface pulse signal becomes 1, indicating that the coarse delay calibration is completed.

[0034] 3 , the second coarse delay calibration unit 102 further includes a second expansion subunit (expand2), which is connected to the second delay subunit (delay2) and the second coarse delay calibration subunit (ct_g) and is configured to expand the high-level duration of the second signal by one clock cycle and send the expanded signal to the second coarse delay calibration subunit (ct_g), so that the second coarse delay calibration subunit (ct_g) performs a logical AND operation on the expanded signal and the single-cycle air interface pulse signal. By expanding the high-level duration of the channel associated pulse signal (i.e., the second signal) by one clock cycle, the second expansion subunit (expand2) eliminates the influence of uncertainty in asynchronous sampling delay difference and ensures that the channel associated pulse signal is earlier than the air interface pulse signal.

[0035] As shown in FIG. 2 and FIG. 4, the second delay calibration module 200 transmits a receive channel associated pulse signal. The receive channel associated pulse signal passes through multiple clock domains of the receive link channel associated pulse transmission module 220 in sequence, ensuring that the receive channel associated pulse signal maintains a high level for one clock cycle. When the receive channel associated pulse signal is transmitted to the next circuit in synchronization with the data, and reaches the receive channel associated pulse calibration module 210, the difference between the receive channel associated pulse signal and the air interface pulse signal is R. d3 -R d2 and R d2 is the delay between the received channel association pulse signal and the next air interface pulse signal, and R d3 is the link fixed delay R d31 and the uncertain delay R of the clock domain crossing d32 The coarse delay calibration is performed in the receive channel associated pulse calibration module 210, and the coarse delay calibration process is the same as that of the first delay calibration module 100. The final delay accuracy is R d5 =R d2 +R d51 and R d51 is the clock cycle R1 of one RX interface clock domain, and R d2 is the clock cycle T of the two ADC analog clock domains. adc_ana It is the sum of.

[0036] 5 is a schematic diagram of a first delay calibration module 100 according to an embodiment of the present disclosure. As shown in FIG. 5, the first delay calibration module 100 includes a first coarse delay calibration unit (CT_PLUSE) 101 in the digital domain and a first fine delay calibration unit (DAC_FT_PLUSE) 201 in the analog domain.

[0037] The first coarse delay calibration unit 101 includes a first air interface pulse processing subunit (posedge0), a first delay subunit (delay1) and a first coarse delay calibration subunit (ct_f).

[0038] The first air interface pulse processing sub-unit (posedge0) is configured to generate a single-period air interface pulse signal based on a rising edge of the air interface pulse signal.

[0039] The first delay sub-unit (delay1) is configured to remove a delay between the transmit channel associated pulse signal transmitted to the first coarse delay calibration unit 101 and the next air interface pulse signal to obtain a first signal (ct_data_pluse). The transmit channel associated pulse signal transmitted to the first coarse delay calibration unit 101 is the signal (dac_data_pluse) transmitted from the transmit link channel associated pulse transmission module 120 to the first coarse delay calibration unit 101.

[0040] The first coarse delay calibration subunit (ct_f) performs a logical AND operation on the first signal (ct_data_pluse) and the single-cycle air interface pulse signal, and if the logical AND operation result is not 1, performs coarse delay calibration, stops the operation until the logical AND operation result becomes 1, and generates a first indication signal (ct_int_flag) that instructs the first fine delay calibration unit 201 to perform fine delay calibration. The first coarse delay calibration subunit (ct_f) triggers a coarse delay calibration interrupt every time a rising edge of the channel association pulse signal occurs, and generates ct_int_flag until the logical AND operation result between the channel association pulse signal and the air interface pulse signal becomes 1, indicating that the coarse delay calibration is completed.

[0041] 6 is a schematic diagram of a TX link delay calibration sequence according to an embodiment of the present disclosure. As shown in FIG. 6, after performing the coarse delay calibration, the delay difference between the transmit channel associated pulse signal and the next air interface pulse signal is T d4 =T d1 +T d22 +T d31 and T d1 is the asynchronous sampling delay between the transmission channel associated pulse signal and the air interface pulse signal, and T d22 is the uncertain delay of the clock domain crossing, and T d31 is the sampling delay of the air interface pulse signal in the DAC digital clock domain.

[0042] 5, the first coarse delay calibration unit 101 further includes a comparison subunit (counter0), which is configured to calculate a time difference between the single-cycle air interface pulse signal and a transmit channel associated pulse signal (dac_data_pluse) transmitted to the first coarse delay calibration unit 101, and set a delay between the transmit channel associated pulse signal (dac_data_pluse) transmitted to the first coarse delay calibration unit and a next air interface pulse signal based on the time difference. After obtaining the time difference between the single-cycle air interface pulse signal and the transmit channel associated pulse signal (dac_data_pluse), the comparison subunit (counter0) performs successive comparison by increasing the delay by one beat each time.

[0043] In some embodiments, as shown in FIG. 5, the first coarse delay calibration unit 101 further includes a first air interface pulse signal regeneration subunit (regen_1) and a first channel associated pulse signal regeneration subunit (regen_0).

[0044] The first air interface pulse signal regeneration subunit (regen_1) is connected to the first air interface pulse processing subunit (posedge0) and the first coarse delay calibration subunit (ct_f), and is configured to reduce the air interface pulse signal (ref_pluse) by a predetermined multiple with the same ratio period to generate a regenerated air interface pulse signal, and send the regenerated air interface pulse signal to the first coarse delay calibration subunit (ct_f). The period T and the predetermined multiple N of the air interface pulse signal (ref_pluse) are preset in the first air interface pulse signal regeneration subunit (regen_1), and the loop regenerated air interface pulse signal is generated according to the period T and the predetermined multiple N of the air interface pulse signal (ref_pluse).

[0045] The first channel associated pulse signal regeneration subunit (regen_0) is connected to the first delay subunit (delay1) and is configured to generate a regenerated transmit channel associated pulse signal by reducing the transmit channel associated pulse signal (dac_data_pluse) transmitted to the first coarse delay calibration unit 101 by a predetermined multiple with the same ratio period, and transmit the regenerated transmit channel associated pulse signal to the first delay subunit (delay1), so that the first delay subunit removes a delay between the regenerated transmit channel associated pulse signal and the next air interface pulse signal. The period T and the predetermined multiple N of the transmit channel associated pulse signal (dac_data_pluse) are preset in the first channel associated pulse signal regeneration subunit (regen_0), and the loop-regenerated transmit channel associated pulse signal is generated according to the period T and the predetermined multiple N of the transmit channel associated pulse signal (dac_data_pluse).

[0046] By reducing the transmission channel associated pulse signal (dac_data_pluse) and the air interface pulse signal (ref_pluse) by N times at the same ratio period and loop-playing them, it is possible to perform N coarse delay calibration processes within one air interface pulse signal period, thereby significantly accelerating the speed of coarse delay calibration.

[0047] 5, the first coarse delay calibration unit 101 further includes a first expansion subunit (expand1), which is connected to the first delay subunit (delay1) and the first coarse delay calibration subunit (ct_f) and is configured to expand the high-level duration of the first signal (ct_data_pluse) by one clock cycle and send the expanded signal to the first coarse delay calibration subunit (ct_f), so that the first coarse delay calibration subunit (ct_f) performs a logical AND operation on the expanded signal and the single-cycle air interface pulse signal. By expanding the high-level duration of the channel associated pulse signal (i.e., the first signal) by one clock cycle, the first expansion subunit (expand1) avoids uncertainty in delay difference due to two asynchronous samplings and clock domain crossings and ensures that the channel associated pulse signal is earlier than the air interface pulse signal.

[0048] 2 and 6, the transmit channel associated pulse generating module 110 receives an air interface pulse signal (ref_pluse) and then synchronously generates a channel associated pulse signal (data_pluse). Note that the channel associated pulse signal (data_pluse) here refers to the transmit channel associated pulse signal. In this case, since the clock asynchronously samples the air interface pulse signal (ref_pluse), a metastable state may exist, and the delay difference between the channel associated pulse signal (data_pluse) and the air interface pulse signal (ref_pluse) is one T1 clock domain period Td1. The channel associated pulse signal (data_pluse) passes through multiple clock domains in the transmit link channel associated pulse transmission module 120 and is controlled by a data valid enable signal to process the channel associated pulse signal (data_pluse) according to different operating scenarios or modes, such as through multiple extension of different extraction filters or non-power-saving processing in a time division duplexing (TDD) scenario. The channel associated pulse signal is sampled by the next-stage circuit and held high for one clock cycle to ensure that it is transmitted to the next-stage circuit in synchronization with the data. However, due to factors such as power-on and long-term clock fluctuations, the clock phase relationship between both sides of the clock domain crossing is uncertain. Therefore, there is one clock cycle of uncertainty in each clock domain crossing transmission. When the channel associated pulse signal (data_pluse) reaches the DAC digital clock domain, the difference between the channel associated pulse signal (data_pluse) and the air interface pulse signal (ref_pluse) that generates it is Td1+Td2, where Td2 is the sum of the link fixed delay Td21 and the clock domain crossing uncertainty delay Td22.

[0049] In the embodiment of the present disclosure, the first fine delay calibration unit 201 and the second fine delay calibration unit 202 have basically the same structure. As shown in Figures 3 and 5, the first fine delay calibration unit 201 and the second fine delay calibration unit 202 each include a channel associated pulse processing subunit (posedge), a determination subunit (count), an air interface pulse synchronization subunit (sync1), a channel associated pulse synchronization subunit (sync0), a fine delay calibration subunit (not shown), and a fine delay calibration interrupt subunit (ft_int_gen).

[0050] The channel associated pulse processing subunit (posedge) is configured to receive a channel associated pulse signal transmitted from a coarse delay calibration unit in the delay calibration module in which it resides, generate a single-period channel associated pulse signal based on a rising edge of the channel associated pulse signal, and transmit the single-period channel associated pulse signal to the first fine delay calibration interrupt subunit, where in the first fine delay calibration unit 201, the channel associated pulse signal is the first signal transmitted from the first coarse delay calibration unit 101, and in the second fine delay calibration unit 202, the channel associated pulse signal is the second signal transmitted from the second coarse delay calibration unit 102.

[0051] The air interface pulse synchronization sub-unit (sync1) is configured to synchronize the air interface pulse signal to its existing clock domain and send the synchronized air interface pulse signal to the determination sub-unit (count).

[0052] The channel associated pulse synchronization subunit (sync0) is configured to synchronize the channel associated pulse signal to the clock domain in which it resides and transmit the synchronized channel associated pulse signal to the determination subunit (count).

[0053] The determination sub-unit (count) is configured to perform a logical AND operation on the synchronized air interface pulse signal and the synchronized channel association pulse signal.

[0054] The fine delay calibration subunit performs fine delay calibration when the calculation result calculated by the determination subunit (count) is 0. The fine delay calibration subunit may be a functional module realized by software.

[0055] The fine delay calibration interrupt subunit (ft_int_gen) is configured to trigger and generate an interrupt signal for stopping the fine delay calibration based on the single-period channel associated pulse signal.

[0056] In some embodiments, the fine delay calibration subunit of the first fine delay calibration unit 201 is configured to adjust the delay of the transmit channel associated pulse signal (dac_data_pluse) transmitted to the first coarse delay calibration unit 101 by incrementing the read address of a first-in-first-out memory (FIFO) of a clock domain crossing in the transmit link by one.

[0057] In some embodiments, the fine delay calibration subunit of the second fine delay calibration unit 202 is configured to adjust the delay between the recovered received channel association pulse signal and the next air interface pulse signal.

[0058] 3 and 5, the first fine delay calibration unit 201 of the first delay calibration module 100 includes a phase calibration subunit, and the second fine delay calibration unit 202 of the second delay calibration module 200 includes a phase calibration subunit. The phase calibration subunit includes a differential pulse gating subunit (gate_pluse) and a clock division subunit (clk_div), where the differential pulse gating subunit (gate_pluse) is configured to adjust the initial phase of the analog domain clock signal based on a gating signal. The clock division subunit (clk_div) is configured to adjust the initial phase of the digital domain clock signal based on the initial phase of the analog domain clock signal.

[0059] After the coarse delay calibration is completed, the fine delay calibration is started. The fine delay calibration includes fine delay compensation and phase calibration. The synchronized air interface pulse signal and the synchronized channel association pulse signal are ANDed in the judgment subunit (count). If the calculation result (adc_ft_counter) is not 0, the fine delay calibration subunit is instructed to perform fine delay compensation until the calculation result is not 0, indicating that the uncertain delays of the two asynchronous sampling air interface pulses and clock domain crossings have been eliminated. In this case, the delay difference is one clock cycle T of the DAC digital clock domain. dac_dig and one clock cycle T of the DAC analog clock domain dac_ana It is the sum of.

[0060] FIG. 7 is a schematic diagram of a gate_pluse differential circuit according to an embodiment of the present disclosure, and FIG. 8 is a schematic diagram of a gate_pluse differential circuit sequence according to an embodiment of the present disclosure. As shown in FIGS. 5, 6, 7, and 8, taking the first fine delay calibration unit 201 as an example, the differential pulse gating subunit (gate_pluse) can turn off the clock for one clock cycle each time the gating enable is enabled, and in cooperation with the clock division subunit (clk_div), can adjust the initial phase of the division of the analog clock clk_dac_ana of one DAC every time the digital clock clk_dac_dig of the DAC is generated. In this way, when the calculation result reaches a maximum, the phase calibration is completed. As shown in FIG. 6, after the fine delay calibration, the delay accuracy of the transmission channel associated pulse signal and the next air interface pulse signal is T d5 That is, the clock cycle of the two DAC analog clock domains is T dac_ana is.

[0061] In the second delay calibration module 200, after the second coarse delay calibration unit 102 completes the coarse delay calibration, the second fine delay calibration unit 202 performs the fine delay calibration, which is the same as the fine delay calibration performed by the first fine delay calibration unit 201, except for the following differences:

[0062] 1. Fine delay compensation differs in the delay adjustment method. The second fine delay calibration unit 202 adjusts the delay between the recovered received channel associated pulse signal and the next air interface pulse signal. The first fine delay calibration unit 201 increments the FIFO read address of the clock domain crossing in the transmit link by one to adjust the delay of the transmit channel associated pulse signal (dac_data_pluse) transmitted to the first coarse delay calibration unit.

[0063] 2. The trigger signals for the fine delay calibration interrupt are different. In the second fine delay calibration unit 202, the fine delay calibration interrupt is triggered by the rising edge of the air interface pulse signal (ref_pluse), while in the first fine delay calibration unit 201, the fine delay calibration interrupt is triggered by the rising edge of the channel association pulse signal (data_pluse).

[0064] As shown in Figure 4, after the precision delay calibration, the delay accuracy between the received channel association pulse signal and the next air interface pulse signal is R d2 That is, the clock cycles of the two ADC analog clock domains are T adc_ana is.

[0065] The delay calibration device according to the embodiment of the present disclosure utilizes the synchronous transmission characteristics of the channel associated pulse signal and link data after alignment based on the air interface pulse signal, performs delay compensation in the digital clock domain, and performs phase calibration in the analog ADDA high-frequency clock domain, thereby improving the delay calibration accuracy to two high-frequency clock cycles. Instead of the traditional algorithm analysis after two-point synchronous sampling, software adjusts the channel associated pulse signal delay and digital clock phase in the digital clock domain at the first and last levels, significantly simplifying the calibration process and avoiding large amounts of algorithm calculation. This allows for rapid, high-precision link timing even during the initial power-on or normal operation. The entire delay calibration device according to the embodiment of the present disclosure has a simple structure and is adaptable to multiple channels, multiple modes, and multiple operating scenarios.

[0066] The embodiments of the present disclosure are applicable to a radio frequency transceiver system of a terminal or base station, and can support high-precision delay calibration across multiple links, multiple clock domains, and multiple operating modes. TX and RX multilink extensions are supported, and multilink channel associated pulse signals can be generated and calibrated by combining the transmit channel associated pulse signal generation module 110 and the receive channel associated pulse signal calibration module 210 in the digital interface. The embodiments of the present disclosure support multi-system docking of the entire device, and the transmit channel associated pulse signal generation module 110 and the receive channel associated pulse signal calibration module 210 in the digital interface can be transferred to the link source / end of the upstream chip system, thereby enabling high-precision calibration of the entire link delay.

[0067] The embodiments of the present disclosure are applicable to transceiver systems with high delay requirements and clock domain crossing or asynchronous clock domains, and are widely applicable to radio frequency chips, terminal chips and baseband chips with corresponding needs.

[0068] An embodiment of the present disclosure further provides a delay calibration method applied to the delay calibration apparatus as described above, and as shown in FIG. 9, the method includes the following steps S11 to S12.

[0069] In step S11, an air interface pulse signal is received, and delay compensation is performed on the channel association pulse signal in the digital clock domain based on the air interface pulse signal.

[0070] In this step, the coarse delay calibration unit 10 performs delay compensation on the channel associated pulse signal in the digital clock domain based on the air interface pulse signal.

[0071] In step S12, delay compensation is performed on the channel associated pulse signal in the analog clock domain to calibrate the phase of the clock domain.

[0072] In this step, the fine delay calibration subunit 21 of the fine delay calibration unit 20 performs delay compensation on the channel associated pulse signal in the analog clock domain, and the phase calibration subunit of the fine delay calibration unit 20 calibrates the phase of the clock domain.

[0073] The delay calibration method according to the embodiments of the present disclosure uses an air interface pulse signal as a reference, performs delay compensation in the digital clock domain, and performs phase calibration in the analog high-frequency clock domain, thereby improving the delay calibration accuracy to two high-frequency clock cycles. Instead of performing algorithm analysis after the traditional two-point synchronous sampling, the delay of the channel-linked pulse signal in the digital clock domain and the phase of the digital clock are adjusted, thereby simplifying the calibration process and reducing the amount of algorithm calculation, thereby realizing high-speed and high-precision link timing. The overall structure of the delay calibration device is simple, and it can be adapted to multi-channel, multi-mode, and multiple operating scenarios.

[0074] In some embodiments, as shown in FIG. 10 , in the transmit link, the step of performing delay compensation on the channel associated pulse signal in the digital clock domain based on the air interface pulse signal (i.e., step S11) includes: Step S111 of generating a transmission channel associated pulse signal based on the air interface pulse signal; Step S112: aligning and transmitting a transmission channel associated pulse signal and link data in the multi-clock domain of the transmission link using a data valid enable signal; and step S113 of performing delay compensation on the transmit channel associated pulse signal in the digital clock domain based on the air interface pulse signal.

[0075] In some embodiments, as shown in FIG. 11 , in the receive link, the step of performing delay compensation on the channel associated pulse signal in the digital clock domain based on the air interface pulse signal (i.e., step S11) includes: Step S111' of generating a received channel associated pulse signal based on the air interface pulse signal; In a step S112', in the multi-clock domain of the receiving link, the data valid enable signal is used to align and transmit the receiving channel associated pulse signal and the link data; and step S113' of performing delay compensation on the received channel associated pulse signals that are transmitted in alignment in the digital clock domain based on the air interface pulse signals.

[0076] In some embodiments, the step of generating a receive channel associated pulse signal based on the air interface pulse signal (i.e., step S111′) includes the steps of generating a single-cycle air interface pulse signal based on a rising edge of the air interface pulse signal, and reducing the single-cycle air interface pulse signal by a predetermined factor with the same ratio period to generate a regenerated receive channel associated pulse signal.

[0077] The step of performing delay compensation on the received channel association pulse signal, which is aligned and transmitted in the digital clock domain based on the air interface pulse signal (i.e., step S113′), includes: The method includes the steps of: removing a delay between the recovered received channel associated pulse signal and the next air interface pulse signal to obtain a second signal; performing a logical AND operation on the second signal and the single-period air interface pulse signal; if the operation result is not 1, performing coarse delay calibration, stopping the operation until the operation result is 1, and generating a second indication signal.

[0078] In some embodiments, after obtaining the second signal, and before performing a logical AND operation on the second signal and the single-cycle air interface pulse signal, the method further includes extending a high-level length of the second signal according to one clock cycle, and performing a logical AND operation on the extended signal and the single-cycle air interface pulse signal.

[0079] In some embodiments, the step of performing delay compensation on the transmit channel associated pulse signal in the digital clock domain based on the air interface pulse signal (i.e., step S113) includes: The method includes the steps of: generating a single-period air interface pulse signal based on a rising edge of the air interface pulse signal; removing a delay between the transmission channel associated pulse signal transmitted to the first coarse delay calibration unit and the next air interface pulse signal to obtain a first signal; performing a logical AND operation on the first signal and the single-period air interface pulse signal; if the operation result is not 1, performing coarse delay calibration, stopping the operation until the operation result is 1, and generating a first indication signal.

[0080] In some embodiments, before removing the delay between the transmit channel associated pulse signal transmitted to the first coarse delay calibration unit and a next air interface pulse signal, the method further includes calculating a time difference between the single-cycle air interface pulse signal and the transmit channel associated pulse signal transmitted to the first coarse delay calibration unit, and setting a delay between the transmit channel associated pulse signal transmitted to the first coarse delay calibration unit and a next air interface pulse signal based on the time difference.

[0081] In some embodiments, before removing the delay between the transmit channel associated pulse signal transmitted to the first coarse delay calibration unit and a next air interface pulse signal, the method further includes: generating a regenerated air interface pulse signal by reducing the air interface pulse signal by a predetermined factor with the same ratio period; and removing the delay between the regenerated transmit channel associated pulse signal and the next air interface pulse signal by reducing the transmit channel associated pulse signal transmitted to the first coarse delay calibration unit by a predetermined factor with the same ratio period to generate a regenerated transmit channel associated pulse signal.

[0082] In some embodiments, before performing a logical AND operation on the first signal and the single-cycle air interface pulse signal, the method further includes extending a high-level length of the first signal according to one clock cycle, and performing a logical AND operation on the extended signal and the single-cycle air interface pulse signal.

[0083] In some embodiments, after performing the coarse delay calibration, the method comprises: receiving a channel association pulse signal and generating a single-period channel association pulse signal based on a rising edge of the channel association pulse signal, wherein the channel association pulse signal is a first signal or a second signal; synchronizing air interface pulse signals to their existing clock domains and synchronizing channel associated pulse signals to their existing clock domains; The method further includes a step of performing a logical AND operation on the synchronized air interface pulse signal and the synchronized channel associated pulse signal, and performing fine delay calibration if the operation result is 0, wherein the fine delay calibration is performed by triggering an interrupt signal to stop the fine delay calibration based on the single-cycle channel associated pulse signal.

[0084] In some embodiments, the step of performing fine delay calibration comprises: Incrementing the read address of a first-in-first-out memory of a clock domain crossing in a transmission link by one to adjust the delay of the transmission channel associated pulse signal transmitted to the first coarse delay calibration unit; or adjusting the delay between the recovered received channel associated pulse signal and the next air interface pulse signal.

[0085] In some embodiments, the step of calibrating the phase of the clock domains comprises: adjusting an initial phase of a clock signal in the analog domain based on the gating signal; and adjusting the initial phase of the clock signal in the digital domain based on the initial phase of the clock signal in the analog domain.

[0086] In order to clearly describe the technical solutions of the embodiments of the present disclosure, a specific example will be used to describe in detail the delay calibration process according to the embodiments of the present disclosure. The specific steps of the delay calibration process are as follows:

[0087] 1. According to the actual chip needs, start TX and RX delay calibration after power-on.

[0088] 2. According to the application scenario of the product, the software initializes and sets the parameters such as pulse period, link setting, calibration initial value, register, etc. related to TX and RX channel linked pulse generation and calibration.

[0089] 3. The air interface pulse signal is loop-transmitted from the outside, and the TX channel association pulse signal is directly generated using the TX channel association pulse generator. The ADC calibration unit is used to generate the RX link channel association pulse signal through coarse delay calibration and fine delay calibration.

[0090] The ADC coarse delay calibration process is that the rising edge of the air interface pulse signal triggers the software ADC coarse delay calibration interrupt, and the software increases the delay by one beat each time until the logical AND result of the channel association pulse signal and the air interface pulse signal is 1, indicating that the coarse delay calibration is completed.

[0091] The ADC fine delay calibration process involves the rising edge of the air interface pulse signal triggering the software ADC fine calibration interrupt. If the logical AND result of the channel association pulse signal and the air interface pulse signal is 0, the software continues to increase the delay by one beat to perform fine delay compensation. If the count value is not 0, the software performs the process of turning clock gating off and on once, and performs phase adjustment until the count value is equal to the predetermined threshold, indicating that fine delay calibration is complete.

[0092] 4. The TX and RX channel associated pulse signals are transmitted in the link and reach the DAC calibration unit and the RX channel associated pulse signal calibrator respectively.

[0093] 5. Coarse delay calibration and fine delay calibration are performed sequentially in the DAC calibration unit, and coarse delay calibration is performed in the RX channel linked pulse calibrator.

[0094] The DAC coarse delay calibration process is as follows: the rising edge of the channel association pulse signal triggers the software DAC coarse delay calibration interrupt, reads the counter value of the comparison module, and then sets the nearest delay value. Then, the software increases the delay by one beat each time until the logical AND result of the channel association pulse signal and the air interface pulse signal becomes 1, indicating that the coarse delay calibration is completed.

[0095] The DAC fine delay calibration process involves the rising edge of the channel-associated pulse signal triggering a software DAC fine delay calibration interrupt. If the logical AND result of the channel-associated pulse signal and the air interface pulse signal is 0, the software increments the read address of the DAC clock domain crossing FIFO by 1 to adjust the channel-associated pulse delay and perform fine delay compensation. If the count value is not 0, the software performs a clock gating off-on process once, adjusting the phase until the count value equals the predetermined threshold, indicating that fine delay calibration is complete. The coarse delay calibration in the RX channel-associated pulse calibrator is the same as the DAC coarse delay calibration process.

[0096] 6. End the delay calibration process, wait for the next delay detection calibration of the TX and RX links in the normal operation process, and repeat steps 2 to 5.

[0097] Although the present disclosure discloses exemplary embodiments and employs specific terms, they are used and should be interpreted in a general, illustrative sense only, and not for purposes of limitation. In some embodiments, unless otherwise specified, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, as will be apparent to those skilled in the art. Accordingly, as will be apparent to those skilled in the art, various changes in form and detail may be made without departing from the scope of the present invention, as defined by the appended claims.

Claims

1. A delay calibration apparatus including a delay calibration module, the delay calibration module including a coarse delay calibration unit and a fine delay calibration unit; The coarse delay calibration unit is configured to receive an air interface pulse signal and perform delay compensation on a channel associated pulse signal in a digital clock domain based on the air interface pulse signal; the fine delay calibration unit includes a fine delay calibration subunit and a phase calibration subunit; the fine delay calibration subunit is configured to perform delay compensation on the channel associated pulse signal in an analog clock domain after the coarse delay calibration unit performs delay compensation on the channel associated pulse signal in a digital clock domain based on the air interface pulse signal; The delay calibration apparatus, wherein the phase calibration subunit is configured to calibrate a phase of a clock domain after the fine delay calibration subunit performs delay compensation on the channel associated pulse signal in an analog clock domain.

2. a transmission link, wherein the delay calibration module includes a first delay calibration module, the first delay calibration module being located in the transmission link; the coarse delay calibration unit is a first coarse delay calibration unit, the fine delay calibration unit is a first fine delay calibration unit, and the channel associated pulse signal is a transmit channel associated pulse signal; The transmit link further includes a transmit channel associated pulse generating module and a transmit link channel associated pulse transmitting module; the transmit channel associated pulse generation module is configured to receive an air interface pulse signal and generate the transmit channel associated pulse signal based on the air interface pulse signal; 2. The delay calibration device of claim 1, wherein the transmit link channel associated pulse transmission module is configured to align and transmit the transmit channel associated pulse signal and link data to the first coarse delay calibration unit of the first delay calibration module using a data valid enable signal within multiple clock domains of the transmit link.

3. a receiving link, wherein the delay calibration module includes a second delay calibration module, the second delay calibration module being located in the receiving link; the channel associated pulse signal is a received channel associated pulse signal, the fine delay calibration unit is a second fine delay calibration unit, the coarse delay calibration unit is a second coarse delay calibration unit, the second coarse delay calibration unit is further configured to receive an air interface pulse signal, and then generate the received channel associated pulse signal based on the air interface pulse signal; The receive link further includes a receive channel associated pulse calibration module and a receive link channel associated pulse transmission module; The receive link channel associated pulse transmission module is configured to use a data valid enable signal to align and transmit the receive channel associated pulse signal and link data within the multiple clock domains of the receive link, and transmit the aligned receive channel associated pulse signal and link data to the receive channel associated pulse calibration module; The delay calibration device according to claim 1 or 2, wherein the receiving channel associated pulse calibration module is configured to perform delay compensation on the channel associated pulse signal received in a digital clock domain based on the air interface pulse signal.

4. the second coarse delay calibration unit includes a second air interface pulse processing subunit, a second channel associated pulse signal regeneration subunit, a second delay subunit, and a second coarse delay calibration subunit; the second air interface pulse processing subunit is configured to generate a single-period air interface pulse signal based on a rising edge of the air interface pulse signal; the second channel associated pulse signal regeneration subunits are respectively connected to the second air interface pulse processing subunit and the second delay subunit, and are configured to reduce the single-cycle air interface pulse signal transmitted from the second air interface pulse processing subunit by a predetermined factor with the same ratio period to generate a regenerated received channel associated pulse signal, and transmit the regenerated received channel associated pulse signal to the second delay subunit; the second delay subunit is configured to remove a delay between the recovered received channel association pulse signal and a next air interface pulse signal to obtain a second signal; 4. The delay calibration device of claim 3, wherein the second coarse delay calibration subunit is configured to perform a logical AND operation on the second signal and the single-cycle air interface pulse signal, and if the operation result is not 1, perform coarse delay calibration, stop the operation until the operation result is 1, and generate a second indication signal.

5. the second coarse delay calibration unit further includes a second extension subunit; 5. The delay calibration device of claim 4, wherein the second extension subunit is connected to the second delay subunit and the second coarse delay calibration subunit, and is configured to extend a high-level length of the second signal according to one clock cycle and send the extended signal to the second coarse delay calibration subunit so that the second coarse delay calibration subunit performs a logical AND operation on the extended signal and the single-cycle air interface pulse signal.

6. the first coarse delay calibration unit includes a first air interface pulse processing subunit, a first delay subunit, and a first coarse delay calibration subunit; the first air interface pulse processing subunit is configured to generate a single-period air interface pulse signal based on a rising edge of the air interface pulse signal; The first delay subunit is configured to remove a delay between a transmission channel alignment pulse signal transmitted to the first coarse delay calibration unit and a next air interface pulse signal to obtain a first signal; 5. The delay calibration device of claim 4, wherein the first coarse delay calibration subunit is configured to perform a logical AND operation on the first signal and the single-cycle air interface pulse signal, and if the operation result is not 1, perform coarse delay calibration, stop the operation until the operation result is 1, and generate a first indication signal.

7. the first coarse delay calibration unit further includes a comparison sub-unit; 7. The delay calibration device according to claim 6, wherein the comparison subunit is configured to calculate a time difference between the single-cycle air interface pulse signal and the transmission channel associated pulse signal transmitted to the first coarse delay calibration unit, and set a delay between the transmission channel associated pulse signal transmitted to the first coarse delay calibration unit and a next air interface pulse signal based on the time difference.

8. the first coarse delay calibration unit further includes a first air interface pulse signal regeneration subunit and a first channel associated pulse signal regeneration subunit; the first air interface pulse signal regeneration subunit is connected to the first air interface pulse processing subunit and the first coarse delay calibration subunit, and is configured to reduce the air interface pulse signal by a predetermined factor with the same ratio period to generate a regenerated air interface pulse signal, and send the regenerated air interface pulse signal to the first coarse delay calibration subunit; 7. The delay calibration device according to claim 6, wherein the first channel associated pulse signal regeneration subunit is connected to the first delay subunit and configured to reduce the transmit channel associated pulse signal transmitted to the first coarse delay calibration unit by a predetermined factor at the same ratio period to generate a regenerated transmit channel associated pulse signal, and transmit the regenerated transmit channel associated pulse signal to the first delay subunit, thereby removing a delay between the regenerated transmit channel associated pulse signal and a next air interface pulse signal.

9. the first coarse delay calibration unit further includes a first extension subunit; 7. The delay calibration device of claim 6, wherein the first extension subunit is connected to the first delay subunit and the first coarse delay calibration subunit, and is configured to extend a high-level length of the first signal according to one clock cycle and send the extended signal to the first coarse delay calibration subunit so that the first coarse delay calibration subunit performs a logical AND operation on the extended signal and the single-cycle air interface pulse signal.

10. The first fine delay calibration unit and the second fine delay calibration unit each include a channel associated pulse processing subunit, a determination subunit, an air interface pulse synchronization subunit, a channel associated pulse synchronization subunit, a fine delay calibration subunit, and a fine delay calibration interrupt subunit; The channel associated pulse processing subunit is configured to receive a channel associated pulse signal transmitted from a coarse delay calibration unit in the delay calibration module in which the channel associated pulse processing subunit resides, generate a single-period channel associated pulse signal based on a rising edge of the channel associated pulse signal, and transmit the single-period channel associated pulse signal to the first fine delay calibration interrupt subunit, wherein the channel associated pulse signal in the first fine delay calibration unit is the first signal, and the channel associated pulse signal in the second fine delay calibration unit is the second signal; the air interface pulse synchronization subunit is configured to synchronize the air interface pulse signal to an existing clock domain and send the synchronized air interface pulse signal to the determination subunit; the channel associated pulse synchronization subunit is configured to synchronize the channel associated pulse signal to an existing clock domain and transmit the synchronized channel associated pulse signal to the determination subunit; the determining subunit is configured to perform a logical AND operation on the synchronized air interface pulse signal and the synchronized channel association pulse signal; the fine delay calibration subunit is configured to perform fine delay calibration when the calculation result calculated by the determination subunit is 0; 7. The delay calibration device according to claim 6, wherein the fine delay calibration interrupt subunit is configured to trigger and generate an interrupt signal for stopping fine delay calibration based on the single-cycle channel associated pulse signal.

11. 11. The delay calibration apparatus of claim 10, wherein the fine delay calibration subunit of the first fine delay calibration unit is configured to adjust the delay of the transmit channel associated pulse signal transmitted to the first coarse delay calibration unit by incrementing a read address of a first-in-first-out memory of a clock domain crossing in a transmit link by one.

12. 11. The delay calibration apparatus of claim 10, wherein the fine delay calibration subunit of the second fine delay calibration unit is configured to adjust a delay between the recovered received channel association pulse signal and a next air interface pulse signal.

13. the phase calibration subunit includes a differential pulse gating subunit and a clock division subunit; the differential pulse gating subunit is configured to adjust an initial phase of a clock signal in an analog domain based on a gating signal; 13. The delay calibration device according to claim 1, wherein the clock division subunit is configured to adjust an initial phase of a clock signal in a digital domain based on an initial phase of the clock signal in the analog domain.

14. A delay calibration method applied to the delay calibration device according to any one of claims 1 to 13, comprising: receiving an air interface pulse signal and performing delay compensation on a channel associated pulse signal in a digital clock domain based on the air interface pulse signal; performing delay compensation on the channel associated pulse signal in an analog clock domain to calibrate the phase of the clock domain.

15. In a transmission link, performing delay compensation on a channel associated pulse signal in a digital clock domain based on the air interface pulse signal includes: generating the transmit channel associated pulse signal based on the air interface pulse signal; aligning transmission of the transmit channel associated pulse signal and link data using a data valid enable signal within multiple clock domains of the transmit link; and performing delay compensation on the transmit channel associated pulse signal in a digital clock domain based on the air interface pulse signal.

16. In a receiving link, performing delay compensation on a channel associated pulse signal in a digital clock domain based on the air interface pulse signal, includes: generating a received channel associated pulse signal based on the air interface pulse signal; aligning transmission of the receive channel associated pulse signal and link data within the multiple clock domains of the receive link using a data valid enable signal; and performing delay compensation on a received channel associated pulse signal that is transmitted in alignment in a digital clock domain based on the air interface pulse signal.

17. The present invention is applied to the delay calibration device according to any one of claims 4 to 13, wherein the step of generating a reception channel associated pulse signal based on the air interface pulse signal comprises: generating a single-period air interface pulse signal based on a rising edge of the air interface pulse signal, and reducing the single-period air interface pulse signal by a predetermined factor with the same ratio period to generate a regenerated received channel associated pulse signal; The step of performing delay compensation on the received channel associated pulse signals transmitted in alignment in a digital clock domain based on the air interface pulse signals includes: removing a delay between the recovered received channel associated pulse signal and a next air interface pulse signal to obtain a second signal; 17. The method of claim 16, further comprising: performing a logical AND operation on the second signal and the single-period air interface pulse signal; and if the result is not 1, performing coarse delay calibration, stopping the operation until the result is 1, and generating a second indication signal.

18. This method is applied to the delay calibration device according to any one of claims 5 to 13, and after acquiring a second signal, before performing a logical AND operation on the second signal and the single-cycle air interface pulse signal, 18. The method of claim 17, further comprising the step of: extending a high level length of the second signal according to one clock cycle; and performing a logical AND operation on the extended signal and the single-cycle air interface pulse signal.

19. The delay calibration device according to any one of claims 6 to 13, wherein the step of performing delay compensation on the transmission channel associated pulse signal in a digital clock domain based on the air interface pulse signal comprises: generating a single-period air interface pulse signal based on a rising edge of the air interface pulse signal; removing a delay between the transmit channel associated pulse signal sent to the first coarse delay calibration unit and a next air interface pulse signal to obtain a first signal; 20. The method of claim 17, further comprising: performing a logical AND operation on the first signal and the single-period air interface pulse signal; and if the result of the operation is not 1, performing coarse delay calibration, stopping the operation until the result of the operation is 1, and generating a first indication signal.

20. The present invention is applied to a delay calibration apparatus according to any one of claims 7 to 13, wherein before removing a delay between a transmission channel association pulse signal transmitted to the first coarse delay calibration unit and a next air interface pulse signal, the method comprises:

20. The method of claim 19, further comprising: calculating a time difference between the single-cycle air interface pulse signal and the transmit channel associated pulse signal transmitted to the first coarse delay calibration unit; and setting a delay between the transmit channel associated pulse signal transmitted to the first coarse delay calibration unit and a next air interface pulse signal based on the time difference.

21. The present invention is applied to a delay calibration apparatus according to any one of claims 8 to 13, wherein before removing a delay between a transmission channel association pulse signal transmitted to the first coarse delay calibration unit and a next air interface pulse signal, the method comprises: generating a regenerated air interface pulse signal by reducing the air interface pulse signal by a predetermined factor with the same periodic ratio; 20. The method of claim 19, further comprising: reducing the transmit channel associated pulse signal transmitted to the first coarse delay calibration unit by a predetermined factor with the same ratio period to generate a regenerated transmit channel associated pulse signal, thereby eliminating a delay between the regenerated transmit channel associated pulse signal and a next air interface pulse signal.

22. This method is applied to the delay calibration device according to any one of claims 9 to 13, and before performing a logical AND operation on the first signal and the single-cycle air interface pulse signal, the method further comprises:

20. The method of claim 19, further comprising the steps of: extending a high level length of the first signal according to one clock cycle; and performing a logical AND operation on the extended signal and the single-cycle air interface pulse signal.

23. The method is applied to the delay calibration device according to any one of claims 10 to 13, wherein after performing coarse delay calibration, the method comprises: receiving a channel association pulse signal and generating a single-period channel association pulse signal based on a rising edge of the channel association pulse signal, the channel association pulse signal being the first signal or the second signal; synchronizing the air interface pulse signals to their existing clock domains and synchronizing the channel associated pulse signals to their existing clock domains; 20. The method of claim 19, further comprising: performing a logical AND operation on the synchronized air interface pulse signal and the synchronized channel associated pulse signal; and performing fine delay calibration when the operation result is 0, wherein triggering and generating an interrupt signal based on the single-cycle channel associated pulse signal to stop fine delay calibration.

24. The step of performing fine delay calibration includes: Incrementing a read address of a first-in-first-out memory of a clock domain crossing in a transmission link by one to adjust the delay of the transmission channel associated pulse signal transmitted to the first coarse delay calibration unit; and adjusting a delay between the recovered received channel associated pulse signal and a next air interface pulse signal.

25. The step of calibrating the phase of the clock domains includes: adjusting an initial phase of a clock signal in the analog domain based on the gating signal; and adjusting an initial phase of a clock signal in a digital domain based on the initial phase of the clock signal in the analog domain.

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