Dual processor device, its control method, and processor

Abstract

This application discloses a dual processor device and a control method and processor therefor, the dual processor including a control processor and an arithmetic processor, the method being implemented by the control processor, and characterized in that, upon detecting an arc occurrence, the method includes sending a pre-turn-off output preshake hand to the arithmetic processor, causing the arithmetic processor to stop a related arithmetic operation based on the pre-turn-off output preshake hand; receiving an operation stop notification sent by the arithmetic processor, the operation stop notification being issued after the arithmetic processor has completed an operation on the received data after receiving the pre-turn-off output preshake hand; and executing a turn-off operation. This solves the problem of data accuracy between the control processor and the arithmetic processor, which is caused by a lack of synchronization between the control processor and the arithmetic processor in the prior art.

Description

[Technical Field]

[0001] The present invention relates to the technical field of device control, and more particularly to a dual processor device, a control method thereof, and a processor. [Background technology]

[0002] In the control mode of conventional dual-processor equipment, processor A is used to control the circuit and detect arcs, and processor B performs PID calculations and provides processor A with control circuit operating parameters. When processor A detects an arc, it executes disable control (DISABLE) to immediately disconnect the circuit or stop signal output. However, since the PID calculation cannot be interrupted, when processor A executes disable control, processor B continues the PID calculation and feeds back the control circuit operating parameters to processor A. However, for processor A, the calculation parameters fed back by processor B at this time are redundant, unnecessary, and erroneous. Furthermore, if processor A's disable control occurs suddenly, the operating parameters fed back by processor B may prevent processor A from connecting to subsequent monitoring data, which may invalidate the entire control data group.

[0003] Therefore, how to design a highly reliable and highly accurate dual processor device and its control method is a technical problem that needs to be solved. Summary of the Invention [Problem to be solved by the invention]

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the problem that in the prior art, when PID control is performed between dual processors, the control circuit of the control processor immediately halts, but the calculation processor continues the PID calculation, thereby affecting the accuracy of data between the control processor and the calculation processor.To this end, a dual processor device, a control method thereof, and a processor are provided. [Means for solving the problem]

[0005] To solve the above technical problems, the embodiments disclosed in the present invention at least provide a dual-processor device, a control method thereof, and a processor.

[0006] According to a first aspect, a disclosed embodiment of the present invention is a dual processor device control method, wherein the dual processors include a control processor and an arithmetic processor, the method being implemented by the control processor; Upon detecting an arc occurrence, sending a pre-turn-off output pre-shake hand to the calculation processor, so that the calculation processor stops related calculation operations based on the pre-turn-off output pre-shake hand; receiving an operation stop notification sent by the arithmetic processor, the operation stop notification being issued after the arithmetic processor has completed the operation of the received data since receiving the pre-turn-off output pre-shake handset; and performing a turn-off operation.

[0007] Preferably, the method comprises: If a restart condition is satisfied, sending a restarted preshake hand to the computing processor, so that the computing processor regains its computing readiness based on the restarted preshake hand; The method further includes a step of recovering acquisition of equipment operation data and recovering transmission of the equipment operation data to the calculation processor after receiving a recovery confirmation message fed back by the calculation processor, wherein the recovery confirmation message is transmitted after the calculation processor completes preparation for calculation.

[0008] Preferably, before sending a restarted preshake handset to the computing processor: further comprising determining whether the computing processor is in a sleep state; Sending a restarted preshake hand to the computing processor means sending a restarted preshake hand to the computing processor if the computing processor is in a sleep state.

[0009] Preferably, before sending a restarted preshake handset to the computing processor: The method further includes the step of directly acquiring the appliance operation data and transmitting the appliance operation data to the computing processor when the computing processor is not in a sleep state.

[0010] Preferably, the restart conditions include whether or not the turn-off time satisfies a preset length of the turn-off time and / or whether or not restart instruction information is received.

[0011] Preferably, The method further includes the step of entering a sleep state after performing the turn-off operation.

[0012] Preferably, before entering the sleep state, the method further comprises the step of freezing equipment operational data for the period of arcing.

[0013] According to a second aspect, the disclosed embodiment of the present invention is a control processor for a dual processor machine, comprising: a pre-turn-off instruction module for sending a pre-turn-off output pre-shake hand to an arithmetic processor upon detecting an arc occurrence, thereby causing the arithmetic processor to stop an associated arithmetic operation based on the pre-turn-off output pre-shake hand; a pre-turn-off execution module for receiving an operation stop notification sent by the arithmetic processor, the operation stop notification being issued after the arithmetic processor has completed an operation on the received data after receiving the pre-turn-off output pre-shake handset; and a turn-off module for performing a turn-off operation.

[0014] According to a third aspect, a disclosed embodiment of the present invention is a dual processor device control method, wherein the dual processors include a control processor and an arithmetic processor, the method being implemented by the arithmetic processor; receiving a pre-turn-off output pre-shake handset sent by the control processor; completing the operation on the received data and then stopping the associated operation; and sending an operation stop notification to the control processor, so that the control processor performs a turn-off operation after receiving the operation stop notification.

[0015] Preferably, receiving a preshake handshake sent and reinitiated by the control processor; completing preparations for operation recovery based on the restarted preshake handshake; sending a recovery confirmation message to the control processor, whereby the control processor recovers acquisition of equipment operational data based on the recovery confirmation message; receiving the equipment operational data transmitted by the control processor.

[0016] Preferably, after sending an operation stop notification to the control processor, the method further comprises the step of entering a sleep state.

[0017] Preferably, before entering the sleep state, the method further includes freezing equipment operational data for the period of arcing.

[0018] According to a fourth aspect, the disclosed embodiment of the present invention is a computing processor for a dual processor device, comprising: a pre-turn-off instruction receiving module for receiving a pre-turn-off output pre-shake hand signal sent by the control processor; an operation stop control module for stopping the associated operation after completing the operation of the received data; and an operation stop notification module for sending an operation stop notification to the control processor, so that the control processor performs a turn-off operation after receiving the operation stop notification.

[0019] According to a fifth aspect, an embodiment disclosed in the present invention provides a dual processor device, characterized in that it includes a control processor for the dual processor device according to the second aspect and an arithmetic processor for the dual processor device according to the fourth aspect.

[0020] According to a sixth aspect, an embodiment disclosed in the present invention is a method for controlling a dual-processor device, the dual-processor device including a control processor, an arithmetic processor, and a shared memory, the shared memory being configured with a turn-off instruction identifier, the method being implemented by the control processor; performing a turn-off operation upon detecting an arc; A dual processor equipment control method is provided, comprising: a step in which the calculation processor skips acquiring first equipment operation data based on the state of the turn-off instruction identifier by setting the turn-off instruction identifier in the shared memory to a turn-off state, wherein the first equipment operation data is equipment operation data acquired by the control processor during an arc generation period.

[0021] Preferably, before detecting an arc occurrence, the method comprises: acquiring second device operational data; and transmitting the second device operation data to the computing processor via the shared memory.

[0022] Preferably, the step of transmitting the second device operation data to the calculation processor via the shared memory includes: The method includes storing the second equipment operation data in the shared memory so that the computing processor can obtain the second equipment operation data from the shared memory.

[0023] Preferably, after performing the turn-off operation, the method further comprises the step of entering a sleep state.

[0024] Preferably, the method comprises: If the restart condition is met, restarting; setting a turn-off instruction identifier in the shared memory to a normal state; Restoring the acquisition of the second device operational data; The method further includes a step of recovering transmission of the second device operation data to the computing processor via the shared memory, whereby the computing processor obtains the second device operation data from the shared memory based on the state of the turn-off instruction identifier.

[0025] Preferably, the restart condition is: This includes whether the turn-off time meets a preset turn-off time length and / or whether restart instruction information is received.

[0026] Preferably, before entering the sleep state, the method further comprises the step of freezing equipment operational data for the period of arcing.

[0027] According to a seventh aspect, an embodiment disclosed in the present invention is a dual processor device, the dual processor device including a control processor, an arithmetic processor, and a shared memory, the shared memory being configured with a turn-off instruction identifier, and the control processor: a turn-off indication module for performing a turn-off operation upon detecting an arc; and a turn-off state setting module for causing the calculation processor to skip acquiring first equipment operation data based on the state of the turn-off instruction identifier by setting the turn-off instruction identifier in the shared memory to a turn-off state, wherein the first equipment operation data is equipment operation data acquired by the control processor during an arc generation period.

[0028] According to an eighth aspect, an embodiment disclosed in the present invention is a method for controlling a dual-processor device, the dual-processor device including a control processor, a calculation processor, and a shared memory, the shared memory being configured with a turn-off instruction identifier, the method being implemented by the calculation processor, obtaining a state of the turn-off indication identifier in the shared memory; A dual-processor equipment control method is provided, comprising the step of: if the turn-off instruction identifier is in a turn-off state, skipping acquisition of first equipment operation data based on the state of the turn-off instruction identifier, wherein the first equipment operation data is equipment operation data acquired by the control processor during an arc generation period.

[0029] Preferably, If the turn-off instruction identifier is in a normal state, acquiring first device operation data from the shared memory; performing a control parameter calculation based on the first device operation data; and transmitting the calculated control parameters to the control processor via the shared memory.

[0030] Preferably, the method further includes entering a sleep state when the turn-off instruction identifier is in a turn-off state.

[0031] Preferably, before obtaining the state of the turn-off instruction identifier in the shared memory, the method comprises: If a restart condition is satisfied, the method further includes the step of restarting the device; The step of acquiring the status of the turn-off instruction identifier in the shared memory is to recover the acquisition of the status of the turn-off instruction identifier in the shared memory.

[0032] Preferably, before entering the sleep state, the method further comprises the step of freezing equipment operational data for the period of arcing.

[0033] According to a ninth aspect, an embodiment disclosed in the present invention is a dual processor device, comprising a control processor, an arithmetic processor, and a shared memory, wherein a turn-off instruction identifier is set in the shared memory, and the arithmetic processor: a turn-off identifier acquisition module for acquiring a status of the turn-off indication identifier in the shared memory; and a turn-off data processing module for skipping acquisition of first equipment operation data based on the state of the turn-off instruction identifier when the turn-off instruction identifier is in a turn-off state, wherein the first equipment operation data is equipment operation data acquired by the control processor during an arc generation period.

[0034] According to a tenth aspect, an embodiment disclosed in the present invention provides a dual processor device comprising a shared memory, a control processor according to the ninth aspect, and an arithmetic processor according to the ninth aspect, wherein a turn-off instruction identifier is set in the shared memory.

[0035] According to an eleventh aspect, an embodiment disclosed in the present invention provides a computing device comprising a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the computing device is executed, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the computing device performs a dual processor device control method described in any one of the first, third, sixth or eighth aspects.

[0036] According to a twelfth aspect, an embodiment disclosed herein provides a computer-readable storage medium having a computer program stored thereon, the computer program being configured to, when executed by a processor, perform a dual processor device control method as set forth in any one of the first, third, sixth or eighth aspects.

[0037] (Effects of the Invention) The technical solution according to the embodiment of the present invention can have the following beneficial effects: In a dual-processor control process, when the control processor detects an arc occurrence, it can perform a turn-off operation, stop the processor that is operated on from acquiring equipment operation data, and send a turn-off calculation instruction to the calculation processor. The calculation processor can determine whether to suspend the calculation of related control parameters or stop sending related control parameters that have been calculated to the control processor based on whether the equipment operation data is acquired or whether a turn-off calculation instruction is acquired, thereby ensuring that the control processor acquires accurate control parameters and preventing an arc from occurring. When the control processor turns off the circuit, the data between the dual processors can maintain good accuracy, the PID calculation can be stopped in a timely manner, the turn-off occasion point can be avoided to be extended, and the situation of data discarding can be reduced. When one end of the circuit is turned off, the other end can continue to execute, which can cause the entire circuit to operate erratically. Unless the entire PID calculation has started, the calculation can be suspended or the operating parameters of the calculation can be omitted. This is applicable to command, handshake or data sharing. When the control processor turns off, the data is frozen, which can ensure the stability and consistency of data transmission between the control processor and the calculation processor. When the control processor circuit is turned off, the other end can continue to execute unnecessary calculations, which can cause the entire circuit to operate erratically. When an arc occurs, the data accuracy between the control processor and the calculation processor can be effectively ensured.

[0038] A more complete understanding of exemplary embodiments of the present invention can be obtained by reference to the following drawings. The drawings are intended to provide a further understanding of the examples of the present application and, together with the examples of the present application, constitute a part of the specification for explaining the present invention and are not intended to limit the present invention. In the drawings, like reference numerals generally represent like parts or steps. [Brief explanation of the drawings]

[0039] [Figure 1] 2 is a flowchart of a dual processor appliance control method according to an embodiment of the present invention; [Figure 2] 4 is a flowchart of another dual-processor appliance control method according to a disclosed embodiment of the present invention. [Figure 3] FIG. 2 is a timing schematic diagram of the interaction between the control processor and the calculation processor according to a disclosed embodiment of the present invention; [Figure 4] FIG. 2 is a timing schematic diagram of the interaction between the control processor and the calculation processor according to a disclosed embodiment of the present invention; [Figure 5] FIG. 2 is a timing schematic diagram of the interaction between the control processor and the calculation processor according to a disclosed embodiment of the present invention; [Figure 6] FIG. 2 is a timing schematic diagram of the interaction between the control processor and the calculation processor according to a disclosed embodiment of the present invention; [Figure 7] 10 is a flowchart of another dual-processor appliance control method according to an embodiment of the present invention; [Figure 8] 10 is a flowchart of another dual-processor appliance control method according to an embodiment of the present invention; [Figure 9] 1 is a structural schematic diagram of a control processor for a dual-processor device according to an embodiment of the present invention; [Figure 10] 1 is a structural schematic diagram of an arithmetic processor for a dual-processor device according to an embodiment of the present invention; [Figure 11] 1 is a structural schematic diagram of a dual processor device according to an embodiment disclosed in the present invention; [Figure 12] 2 is a flowchart of a dual processor appliance control method according to an embodiment of the present invention; [Figure 13] 4 is a flowchart of another dual-processor appliance control method according to a disclosed embodiment of the present invention. [Figure 14] 10 is a flowchart of another dual-processor appliance control method according to an embodiment of the present invention; [Figure 15] 10 is a flowchart of another dual-processor appliance control method according to an embodiment of the present invention; [Figure 16] 1 is a structural schematic diagram of a control processor in a dual-processor device according to an embodiment of the present invention; [Figure 17] 2 is a structural schematic diagram of an arithmetic processor in another dual-processor device according to an embodiment of the present invention; FIG. [Figure 18] 1 is a schematic diagram of a dual processor device architecture according to an embodiment of the present invention; [Figure 19] 3 is a timing relationship diagram of a dual processor device control method according to an embodiment of the present invention; [Figure 20] 3 is a timing relationship diagram of a dual processor device control method according to an embodiment of the present invention; [Figure 21] 3 is a timing relationship diagram of a dual processor device control method according to an embodiment of the present invention; [Figure 22] 4 is a flowchart of another dual-processor appliance control method according to a disclosed embodiment of the present invention. [Figure 23] 4 is a flowchart of another dual-processor appliance control method according to a disclosed embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0040] Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the drawings. Although the drawings illustrate exemplary embodiments of the present disclosure, it should be understood that the present disclosure should not be limited to the embodiments described herein and may be implemented in various forms. On the contrary, these embodiments are provided to facilitate a better understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0041] In the description of the present invention, unless otherwise clearly specified or limited, the terms "attached," "connected," and "coupled" should be understood in a broad sense, and may refer to, for example, a fixed connection, a detachable connection, an integral connection, a mechanical connection, an electrical connection, a direct connection, an indirect connection via an intermediate medium, or an internal connection between two elements. Those skilled in the art can specifically understand the specific meanings of the above terms in the present invention according to specific circumstances.

[0042] Furthermore, the technical features according to different embodiments of the present invention described below can be combined with each other if there is no conflict between them.

[0043] Example 1 As shown in FIG. 1, it is a flowchart of a dual processor device control method according to an embodiment disclosed in the present invention, where the dual processor includes a control processor and an arithmetic processor, and the method is implemented by the control processor and includes the following steps:

[0044] S11: When an arc is detected, a pre-turn-off output pre-shake hand is sent to the calculation processor, and the calculation processor stops the related calculation operation based on the pre-turn-off output pre-shake hand.

[0045] S12: Receive an operation stop notification sent by the operation processor. The operation stop notification is issued after the operation processor has received the pre-turn-off output pre-shake handset and completed the operation of the received data.

[0046] S13: Execute the turn-off operation.

[0047] As can be seen, in the technical solution of this embodiment, in the control process of the dual-processor device, when the control processor detects the occurrence of an arc, it sends a pre-turn-off output pre-shake hand to the calculation processor, and the calculation processor completes the calculation of the received data and stops the related calculation operation based on the pre-turn-off output pre-shake hand, and after receiving the calculation stop notification sent by the calculation processor, the control processor performs the turn-off operation. The handshaking ensures the stability and consistency of data transmission between the control processor and the calculation processor, and avoids the disruptive operation of the entire circuit caused by the calculation processor at the other end still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures the accuracy of data between the control processor and the calculation processor when an arc occurs.

[0048] Example 2 As an improvement of Example 1, as shown in FIG. 2, is a flowchart of another dual-processor device control method according to an embodiment disclosed in the present invention, where the dual processor includes a control processor and an arithmetic processor, and the method is implemented by the control processor and includes:

[0049] S21: If the restart condition is met, the control processor determines whether the calculation processor is in a sleep state, and if the calculation processor is in a sleep state, executes S22, and if the calculation processor is not in a sleep state, executes S24.

[0050] S22: The control processor sends a restarted preshake hand to the operation processor, and the operation processor recovers its operation readiness based on the restarted preshake hand.

[0051] S23: The control processor receives the recovery confirmation message fed back by the operation processor, and resumes the execution of S24. The recovery confirmation message is sent by the operation processor after it has completed preparation for operation.

[0052] S24: The control processor acquires the equipment operation data and transmits the equipment operation data to the calculation processor.

[0053] S25: When an arc is detected, the control processor sends a pre-turn-off output pre-shake hand to the calculation processor, so that the calculation processor stops the relevant calculation operation based on the pre-turn-off output pre-shake hand.

[0054] S26: The control processor receives the operation stop notification sent by the operation processor, and the operation stop notification is issued after the operation processor has received the pre-turn-off output pre-shake handset and completed the operation of the received data.

[0055] S27: The control processor executes the turn-off operation.

[0056] S28: The control processor freezes the equipment operation data for the period during which the arc occurred.

[0057] S29: The control processor goes into a sleep state.

[0058] In some alternative embodiments, the restart condition includes whether the turn-off time meets a preset turn-off time length and / or whether restart instruction information is received.

[0059] Additionally, data can be frozen and CPUB can go into limited sleep either alone or both CPUA and CPUB can go into limited sleep simultaneously.

[0060] It should be noted that the examples described in this specific embodiment are merely for illustrative purposes of describing the specific embodiment conceived by the present invention, and the execution order of the steps in each example is not limited to the examples described in this specification. In implementing specific processes, those skilled in the art can adjust the execution order of each step based on actual circumstances. For example, S21 and S27 have no necessary causal relationship or chronological relationship, and the restart operation of S21 may be described after the turn-off operation of S27.

[0061] To facilitate the reader's understanding, the following will describe in detail the interaction process and timing relationships of the dual-processor device control method in accordance with an embodiment of the present invention, with CPUA as the control processor and CPUB as the calculation processor, in conjunction with Figures 3, 4, 5, and 6. At a first timing, CPUA transmits data required for PID calculation to CPUB, CPUB receives the data and performs PID calculation, CPUA detects an arc and sends a pre-turn-off output pre-shake handshake signal, CPUB completes the PID calculation, obtains the correct data, and returns it to CPUA, CPUB responds to the handshake signal to feed back the PID calculation preparation for the stopped timing to CPUA, CPUA receives the feedback from CPUB and executes the turn-off output, and CPUA discards the fed-back PID data at this timing.

[0062] At the Nth timing, where N is an integer greater than 1, there are two cases: CUPB is asleep and CUPB is not asleep. 1. When CPUB is not asleep, CPUA restarts the control circuit to output power, and CPUA transmits data required for PID calculation to CPUB, which receives the data and performs PID calculation.

[0063] 2. When CPUB goes to sleep, CPUA outputs a restarted pre-shake hand, and CPUB feedbacks that CPUA is ready, and CPUA transmits the data required for PID calculation to CPUB, and CPUB obtains the data and performs PID calculation.

[0064] As can be seen, in the technical solution of this embodiment, in the control process of the dual-processor device, when the control processor detects the occurrence of an arc, it sends a pre-turn-off output pre-shake hand to the calculation processor, and the calculation processor completes the calculation of the received data and stops the related calculation operation based on the pre-turn-off output pre-shake hand, and after receiving the calculation stop notification sent by the calculation processor, the control processor performs the turn-off operation. The handshaking ensures the stability and consistency of data transmission between the control processor and the calculation processor, and avoids the disruptive operation of the entire circuit caused by the calculation processor at the other end still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures the accuracy of data between the control processor and the calculation processor when an arc occurs.

[0065] Example 3 As shown in FIG. 7, an embodiment of the present invention further provides a dual-processor device control method, where the dual processor includes a control processor and an arithmetic processor, and the method is implemented by the arithmetic processor, and includes:

[0066] S31: Receive the pre-turn-off output pre-shake handset sent by the control processor.

[0067] S32: After completing the calculation of the received data, stop the related calculation operation.

[0068] S33: Sending an operation stop notification to the control processor, so that the control processor performs a turn-off operation after receiving the operation stop notification.

[0069] As can be seen, in the technical solution of this embodiment, in the control process of the dual-processor device, when the control processor detects the occurrence of an arc, it sends a pre-turn-off output pre-shake hand to the calculation processor, and the calculation processor completes the calculation of the received data and stops the related calculation operation based on the pre-turn-off output pre-shake hand, and after receiving the calculation stop notification sent by the calculation processor, the control processor performs the turn-off operation. The handshaking ensures the stability and consistency of data transmission between the control processor and the calculation processor, and avoids the disruptive operation of the entire circuit caused by the calculation processor at the other end still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures the accuracy of data between the control processor and the calculation processor when an arc occurs.

[0070] Example 4 As an improvement of the third embodiment, as shown in FIG. 8, the present embodiment further provides a dual-processor device control method, where the dual processor includes a control processor and an arithmetic processor, and the method is implemented by the arithmetic processor and includes:

[0071] S41: The arithmetic processor receives the pre-turn-off output pre-shake hand signal sent by the control processor.

[0072] S42: After completing the calculation of the received data, the calculation processor stops the related calculation operation.

[0073] S43: The processor freezes the equipment operation data during the arc occurrence period.

[0074] S44: The operation processor sends an operation stop notification to the control processor, so that the control processor performs a turn-off operation after receiving the operation stop notification.

[0075] S45: The processor enters a sleep state.

[0076] S46: The arithmetic processor receives the preshake handshake sent and restarted by the control processor.

[0077] S47: The operation processor completes preparations for operation recovery based on the restarted pre-shake handshake.

[0078] S48: The calculation processor sends a recovery confirmation message to the control processor, and the control processor recovers the acquisition of the equipment operation data based on the recovery confirmation message.

[0079] S49: The calculation processor receives the equipment operation data sent by the control processor.

[0080] As can be seen, in the technical solution of this embodiment, in the control process of the dual-processor device, when the control processor detects the occurrence of an arc, it sends a pre-turn-off output pre-shake hand to the calculation processor, and the calculation processor completes the calculation of the received data and stops the related calculation operation based on the pre-turn-off output pre-shake hand, and after receiving the calculation stop notification sent by the calculation processor, the control processor performs the turn-off operation. The handshaking ensures the stability and consistency of data transmission between the control processor and the calculation processor, and avoids the disruptive operation of the entire circuit caused by the calculation processor at the other end still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures the accuracy of data between the control processor and the calculation processor when an arc occurs.

[0081] Example 5 As shown in FIG. 9 , an embodiment of the present invention further provides a control processor for a dual-processor equipment, which includes a pre-turn-off instruction module 51 for sending a pre-turn-off output preshake hand to an operation processor upon detecting an arc occurrence, thereby causing the operation processor to stop related operation operations based on the pre-turn-off output preshake hand; a pre-turn-off execution module 52 for receiving an operation stop notification sent by the operation processor, where the operation stop notification is issued after the operation processor completes operation on the received data after receiving the pre-turn-off output preshake hand; and a turn-off module 53 for executing a turn-off operation.

[0082] In some alternative embodiments, as shown by the dashed line in the drawings, the control processor further includes: a restart handshake module 54 for sending a restarted preshake hand to the computing processor when a restart condition is met, so that the computing processor resumes computing readiness based on the restarted preshake hand; and a recovery confirmation module 55 for recovering acquisition of equipment operation data and recovering transmission of the equipment operation data to the computing processor after receiving a recovery confirmation message fed back by the computing processor, and directly acquiring equipment operation data and transmitting the equipment operation data to the computing processor when the computing processor is not in a sleep state, where the recovery confirmation message is sent after the computing processor has completed computing readiness.

[0083] In some alternative embodiments, as shown by the dashed lines in the drawings, the control processor further includes a first data freezing module 56 for freezing equipment operation data during the arcing period, a first sleep wake-up module 57 for causing the control processor to enter a sleep state after performing a turn-off operation, and a sleep determination module 58 for determining whether the operation processor is in a sleep state.

[0084] The restart handshake module 54 sends a restarted preshake hand to the computing processor when the computing processor is in a sleep state.

[0085] In some alternative embodiments, the restart condition includes whether the turn-off time meets a preset turn-off time length and / or whether restart instruction information is received.

[0086] As can be seen, in the technical solution of this embodiment, in the control process of the dual-processor device, when the control processor detects the occurrence of an arc, it sends a pre-turn-off output pre-shake hand to the calculation processor, and the calculation processor completes the calculation of the received data and stops the related calculation operation based on the pre-turn-off output pre-shake hand, and after receiving the calculation stop notification sent by the calculation processor, the control processor performs the turn-off operation. The handshaking ensures the stability and consistency of data transmission between the control processor and the calculation processor, and avoids the disruptive operation of the entire circuit caused by the calculation processor at the other end still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures the accuracy of data between the control processor and the calculation processor when an arc occurs.

[0087] Example 6 As shown in FIG. 10, an embodiment of the present invention further provides an operation processor for a dual-processor device, which operation processor for the dual-processor device includes: a pre-turn-off instruction receiving module 61 for receiving a pre-turn-off output pre-shake hand sent by a control processor; an operation stop control module 62 for stopping related operation operations after completing the operation of the received data; and an operation stop notification module 63 for sending an operation stop notification to the control processor, so that the control processor performs a turn-off operation after receiving the operation stop notification.

[0088] In some optional embodiments, as shown by the dashed line in the drawings, the computing processor includes a second data freezing module 64 for freezing equipment operation data during the arc occurrence period, a second sleep start-up module 65 for causing the computing processor to enter a sleep state, a handshake receiving module 66 for receiving a preshake handshake sent and restarted by the control processor, an operation recovery module 67 for completing preparations for operation recovery based on the restarted preshake handshake, and a recovery message sending module 68 for sending a recovery confirmation message to the control processor, so that the control processor can resume obtaining equipment operation data based on the recovery confirmation message and resume sending operation data to the equipment. and an equipment data receiving module 69 for receiving equipment operation data transmitted by the control processor.

[0089] As can be seen, in the technical solution of this embodiment, in the control process of the dual-processor device, when the control processor detects the occurrence of an arc, it sends a pre-turn-off output pre-shake hand to the calculation processor, and the calculation processor completes the calculation of the received data and stops the related calculation operation based on the pre-turn-off output pre-shake hand, and after receiving the calculation stop notification sent by the calculation processor, the control processor performs the turn-off operation. The handshaking ensures the stability and consistency of data transmission between the control processor and the calculation processor, and avoids the disruptive operation of the entire circuit caused by the calculation processor at the other end still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures the accuracy of data between the control processor and the calculation processor when an arc occurs.

[0090] Example 7 As shown in FIG. 11, an embodiment of the present invention further provides a dual processor device, which includes a control processor for the dual processor device of the above fifth embodiment and an arithmetic processor for the dual processor device of the above sixth embodiment.

[0091] As can be seen, in the technical solution of this embodiment, in the control process of the dual-processor device, when the control processor detects the occurrence of an arc, it sends a pre-turn-off output pre-shake hand to the calculation processor, and the calculation processor completes the calculation of the received data and stops the related calculation operation based on the pre-turn-off output pre-shake hand, and after receiving the calculation stop notification sent by the calculation processor, the control processor performs the turn-off operation. The handshaking ensures the stability and consistency of data transmission between the control processor and the calculation processor, and avoids the disruptive operation of the entire circuit caused by the calculation processor at the other end still performing unnecessary calculations when the control processor circuit is turned off, and effectively ensures the accuracy of data between the control processor and the calculation processor when an arc occurs.

[0092] Example 8 As shown in Figure 12, this is a flowchart of a dual-processor device control method according to an embodiment disclosed in the present invention, where the dual-processor device includes a control processor, an arithmetic processor, and a shared memory, and a turn-off instruction identifier is set in the shared memory. The method is implemented by the control processor and includes the following steps:

[0093] S81: When an arc is detected, a turn-off operation is performed.

[0094] S82: By setting the turn-off instruction identifier in the shared memory to a turn-off state, the calculation processor skips acquiring the first equipment operation data based on the state of the turn-off instruction identifier, and the first equipment operation data is equipment operation data acquired by the control processor during the arc generation period.

[0095] As can be seen, in the technical solution of this embodiment, in the PID control process based on dual processors, when the control processor detects the occurrence of an arc, it performs a turn-off operation and sets the turn-off instruction identifier in the shared memory to a turn-off state. The calculation processor skips acquiring the equipment operating data that the control processor would acquire during the arcing period based on the state of the turn-off instruction identifier. The shared memory utilizes a data sharing mode in which even if one CPU writes and area protection occurs, the other CPU can still read. Therefore, no matter what work both CPUs are performing, they can immediately acquire the changing data and operating status of the other CPU from the high-speed storage unit. This ensures the stability and consistency of data transmission between the control processor and the calculation processor, and avoids the disruptive operation of the entire circuit caused by the calculation processor at the other end still performing unnecessary calculations when the control processor circuit is turned off. This effectively ensures the accuracy of data between the control processor and the calculation processor when an arc occurs.

[0096] Example 9 As an improvement of Example 8, as shown in Figure 13, is a flowchart of another dual-processor device control method according to an embodiment disclosed in the present invention, where the dual-processor device includes a control processor, an arithmetic processor, and a shared memory, and a turn-off instruction identifier is set in the shared memory, and the method is implemented by the control processor and includes the following steps:

[0097] S91: The control processor acquires second equipment operation data.

[0098] S92: The control processor transmits the second device operation data to the calculation processor via the shared memory.

[0099] S93: Upon detecting an arc, the control processor performs a turn-off operation.

[0100] S94: The control processor sets the turn-off instruction identifier in the shared memory to a turn-off state, so that the calculation processor skips acquiring the first equipment operation data based on the state of the turn-off instruction identifier, and the first equipment operation data is equipment operation data acquired by the control processor during the arc generation period.

[0101] S95: The control processor freezes the equipment operation data for the period of arcing.

[0102] S96: The control processor goes into a sleep state.

[0103] S97: If the restart condition is met, the control processor restarts.

[0104] S98: The control processor sets the turn-off instruction identifier in the shared memory to the normal state and resumes execution of S91.

[0105] In some alternative embodiments, the control processor stores the second equipment operational data in the shared memory, such that the operational processor can retrieve the second equipment operational data from the shared memory.

[0106] In some alternative embodiments, the restart condition includes whether the turn-off time meets a preset turn-off time length and / or whether restart instruction information is received.

[0107] It should be noted that the examples described in this specific embodiment are merely for illustrative purposes of describing the specific embodiment under the concept of the present invention, and the execution order of the steps in each example is not limited to the examples in this specification. In implementing specific processes, those skilled in the art can adjust the execution order of each step based on actual circumstances. For example, S91 and S97 have no necessary causal relationship or chronological relationship, and the restart operation of S97 may be described after the acquisition of the second device operation data of S91.

[0108] As can be seen, in the technical solution of this embodiment, in the PID control process based on dual processors, when the control processor detects the occurrence of an arc, it performs a turn-off operation and sets the turn-off instruction identifier in the shared memory to a turn-off state. The calculation processor skips acquiring the equipment operating data that the control processor would acquire during the arcing period based on the state of the turn-off instruction identifier. The shared memory utilizes a data sharing mode in which even if one CPU writes and area protection occurs, the other CPU can still read. Therefore, no matter what work both CPUs are performing, they can immediately acquire the changing data and operating status of the other CPU from the high-speed storage unit. This ensures the stability and consistency of data transmission between the control processor and the calculation processor, and avoids the disruptive operation of the entire circuit caused by the calculation processor at the other end still performing unnecessary calculations when the control processor circuit is turned off. This effectively ensures the accuracy of data between the control processor and the calculation processor when an arc occurs.

[0109] Example 10 As shown in FIG. 14, an embodiment of the present invention further provides a dual-processor device control method, where the dual-processor device includes a control processor (arithmetic processor) and a shared memory, and a turn-off instruction identifier is set in the shared memory, and the method is implemented by the arithmetic processor and includes the following steps:

[0110] S101: The state of the turn-off instruction identifier in the shared memory is obtained.

[0111] S102: If the turn-off instruction identifier is in a turn-off state, skip acquiring first equipment operation data based on the state of the turn-off instruction identifier, where the first equipment operation data is equipment operation data acquired by the control processor during the arc occurrence period.

[0112] As can be seen, in the technical solution of this embodiment, in the dual-processor-based PID control process, when the control processor detects an arc, it performs a turn-off operation and sets the turn-off instruction identifier in the shared memory to a turn-off state. The calculation processor skips acquiring the equipment operation data that the control processor would acquire during the arc period based on the state of the turn-off instruction identifier. The shared memory utilizes a data sharing mode in which even if one CPU writes and area protection occurs, the other CPU can still read. Therefore, no matter what work both CPUs are performing, they can immediately obtain the data or operating status of the other CPU from the high-speed storage unit. This ensures the stability and consistency of data transmission between the control processor and the calculation processor, and avoids the disruptive operation of the entire circuit caused by the calculation processor at the other end still performing unnecessary calculations when the control processor circuit is turned off. This effectively ensures the accuracy of data between the control processor and the calculation processor when an arc occurs.

[0113] Example 11 As an improvement of Example 10, as shown in FIG. 15, this embodiment of the present invention further provides a dual-processor device control method, where the dual-processor device includes a control processor, an arithmetic processor, and a shared memory, and a turn-off instruction identifier is set in the shared memory, and the method is implemented by the arithmetic processor and includes the following steps:

[0114] S111: If the restart condition is met, the processor restarts and resumes the execution of S42.

[0115] S112: The processor acquires the state of the turn-off instruction identifier in the shared memory.

[0116] S113: If the turn-off instruction identifier is in a normal state, the calculation processor obtains the first device operation data from the shared memory.

[0117] S114: The calculation processor performs control parameter calculation based on the first device operation data.

[0118] S115: The arithmetic processor transmits the control parameters obtained by the calculation to the control processor via the shared memory.

[0119] S116: If the turn-off instruction identifier is in the turn-off state, the calculation processor skips acquiring the first equipment operation data based on the state of the turn-off instruction identifier, and the first equipment operation data is the equipment operation data acquired by the control processor during the arc generation period.

[0120] S117: The processor freezes the equipment operation data during the arc occurrence period.

[0121] S118: If the turn-off instruction identifier is in the turn-off state, the computing processor enters a sleep state and waits for the triggering of a restart condition.

[0122] As can be seen, in the technical solution of this embodiment, in the PID control process based on dual processors, when the control processor detects the occurrence of an arc, it performs a turn-off operation and sets the turn-off instruction identifier in the shared memory to a turn-off state. The calculation processor skips acquiring the equipment operating data that the control processor would acquire during the arcing period based on the state of the turn-off instruction identifier. The shared memory utilizes a data sharing mode in which even if one CPU writes and area protection occurs, the other CPU can still read. Therefore, no matter what work both CPUs are performing, they can immediately acquire the changing data and operating status of the other CPU from the high-speed storage unit. This ensures the stability and consistency of data transmission between the control processor and the calculation processor, and avoids the disruptive operation of the entire circuit caused by the calculation processor at the other end still performing unnecessary calculations when the control processor circuit is turned off. This effectively ensures the accuracy of data between the control processor and the calculation processor when an arc occurs.

[0123] Example 12 The present embodiment further provides a dual-processor device, the dual-processor device including a control processor, an arithmetic processor and a shared memory, and a turn-off instruction identifier is set in the shared memory, as shown in FIG. 16 , the control processor includes a turn-off instruction module 121 for performing a turn-off operation when detecting an arc occurrence; and a turn-off state setting module 122 for causing the calculation processor to skip acquiring first equipment operation data based on the state of the turn-off instruction identifier by setting the turn-off instruction identifier in the shared memory to a turn-off state, the first equipment operation data being equipment operation data acquired by the control processor during the arc generation period.

[0124] In some alternative embodiments, as shown by the dashed lines in the drawings, the device may include an operational data acquisition module 123 for acquiring second equipment operational data; an operational data transmission module 124 for transmitting second equipment operational data to the computing processor via the shared memory, recovering the acquisition and transmitting the second equipment operational data to the computing processor via the shared memory, so that the computing processor acquires the second equipment operational data from the shared memory based on the state of the turn-off instruction identifier; a first data freezing module 125 for freezing equipment operational data for the duration of the arc; a first sleep module 126 for entering a sleep state; a first restart module 127 for restarting when a restart condition is met; The device may further include a shared identifier setting module 128 for setting the turn-off instruction identifier in the shared memory to a normal state.

[0125] In some alternative embodiments, the restart condition includes whether the turn-off time meets a preset turn-off time length and / or whether restart instruction information is received.

[0126] As can be seen, in the technical solution of this embodiment, in the PID control process based on dual processors, when the control processor detects the occurrence of an arc, it performs a turn-off operation and sets the turn-off instruction identifier in the shared memory to a turn-off state. The calculation processor skips acquiring the equipment operating data that the control processor would acquire during the arcing period based on the state of the turn-off instruction identifier. The shared memory utilizes a data sharing mode in which even if one CPU writes and area protection occurs, the other CPU can still read. Therefore, no matter what work both CPUs are performing, they can immediately acquire the changing data and operating status of the other CPU from the high-speed storage unit. This ensures the stability and consistency of data transmission between the control processor and the calculation processor, and avoids the disruptive operation of the entire circuit caused by the calculation processor at the other end still performing unnecessary calculations when the control processor circuit is turned off. This effectively ensures the accuracy of data between the control processor and the calculation processor when an arc occurs.

[0127] Example 13 An embodiment of the present invention further provides a dual-processor device, the dual-processor device including a control processor, an operation processor and a shared memory, and a turn-off instruction identifier is set in the shared memory, as shown in FIG. 17, the operation processor includes: a turn-off identifier acquisition module 131 for acquiring the status of the turn-off instruction identifier in the shared memory; and a turn-off data processing module 132 for skipping acquisition of first equipment operation data based on the state of the turn-off instruction identifier when the turn-off instruction identifier is in a turn-off state, the first equipment operation data being equipment operation data acquired by the control processor during the arcing period.

[0128] In some alternative embodiments, as shown by the dashed line in the drawings, the device may include an operation data extraction module 133 for acquiring first device operation data from the shared memory when the turn-off instruction identifier is in a normal state, and recovering the acquisition of the state of the turn-off instruction identifier in the shared memory after rebooting; a control parameter calculation module 134 for calculating control parameters based on the first device operation data; a control parameter transmission module 135 for transmitting the calculated control parameters to the control processor via the shared memory; a second sleep module 1313 for entering a sleep state when the turn-off indication identifier is a turn-off state; a second restart module 137 for restarting if a restart condition is met; and a second data freezing module 138 for freezing the equipment operational data for the period of arcing.

[0129] As can be seen, in the technical solution of this embodiment, in the PID control process based on dual processors, when the control processor detects the occurrence of an arc, it performs a turn-off operation and sets the turn-off instruction identifier in the shared memory to a turn-off state. The calculation processor skips acquiring the equipment operating data that the control processor would acquire during the arcing period based on the state of the turn-off instruction identifier. The shared memory utilizes a data sharing mode in which even if one CPU writes and area protection occurs, the other CPU can still read. Therefore, no matter what work both CPUs are performing, they can immediately acquire the changing data and operating status of the other CPU from the high-speed storage unit. This ensures the stability and consistency of data transmission between the control processor and the calculation processor, and avoids the disruptive operation of the entire circuit caused by the calculation processor at the other end still performing unnecessary calculations when the control processor circuit is turned off. This effectively ensures the accuracy of data between the control processor and the calculation processor when an arc occurs.

[0130] Example 14 As shown in FIG. 18, an embodiment of the present invention further provides a dual processor device, which includes a shared memory 141, a control processor 142 and an arithmetic processor 143 in the dual processor device, and a turn-off instruction identifier is set in the shared memory 141.

[0131] For the convenience of readers, the following describes the dual processor device in detail with the timing diagrams of Figures 19, 20 and 21, where CPUA is the control processor, CPUB is the arithmetic processor, RAM is the shared memory, and FLAG is the turn-off instruction identifier. In normal mode, the PID control of a dual-processor device involves the following steps: CPUA does not detect an arc and does not rewrite the CPUA activation flag in RAM. CPUA transmits the data required for PID calculation and writes it to RAM. CPUB reads the enable flag of CPUA in RAM and determines that it is ENABLE. CPUB reads RAM, gets the data, performs PID calculation, The CPUB writes the circuit control parameters generated by the calculations into RAM, The CPUA reads the RAM to obtain parameters to control circuit operation and power output.

[0132] The PID control of a dual processor machine in shared memory mode includes the following steps: During the first timing, CPUA detects the arc and rewrites the CPUA operation flag in RAM to DISABLE. CPUA executes turn-off output, CPUB reads the CPUA's operation flag in RAM and determines that it is DISABLE. CPU B does not read RAM and does not perform currently timed PID calculations.

[0133] Additionally, data can be frozen and CPUB or dual CPUs can go into limited sleep.

[0134] At the Nth timing, N is an integer greater than 1; The CPUA restarts the control circuit and outputs power. CPUA rewrites the CPUA operation flag in RAM, CPUA transmits the data required for PID calculation and writes it to RAM. CPUB reads the enable flag of CPUA in RAM and determines that it is ENABLE. CPUB reads RAM, gets the data, performs PID calculation, The CPU B writes the circuit control parameters generated by the calculation into the RAM.

[0135] As can be seen, in the technical solution of this embodiment, in the PID control process based on dual processors, when the control processor detects the occurrence of an arc, it performs a turn-off operation and sets the turn-off instruction identifier in the shared memory to a turn-off state. The calculation processor skips acquiring the equipment operating data that the control processor would acquire during the arcing period based on the state of the turn-off instruction identifier. The shared memory utilizes a data sharing mode in which even if one CPU writes and area protection occurs, the other CPU can still read. Therefore, no matter what work both CPUs are performing, they can immediately acquire the changing data and operating status of the other CPU from the high-speed storage unit. This ensures the stability and consistency of data transmission between the control processor and the calculation processor, and avoids the disruptive operation of the entire circuit caused by the calculation processor at the other end still performing unnecessary calculations when the control processor circuit is turned off. This effectively ensures the accuracy of data between the control processor and the calculation processor when an arc occurs.

[0136] Example 15 The dual processor device according to the embodiment disclosed in the present invention has the same structural schematic diagram as that of FIG. 11, and the device comprises: a control processor 151 (not shown) that executes a designated operation when detecting an arc occurrence, the designated operation including at least one of an operation 1 for stopping acquisition of equipment operation data by a calculation processor 152 (not shown) and an operation 2 for sending a turn-off calculation instruction to the calculation processor 152; A calculation processor 152 determines an operation policy based on the result generated by the specified operation, thereby ensuring that the control processor 11 obtains accurate control parameters. The result generated by the specified operation includes whether or not the device operation data is obtained and whether or not the turn-off calculation instruction is obtained. The operation policy is: Method 1 for interrupting the calculation operation of the relevant control parameters; and a calculation processor 152 including at least one of a method 2 for stopping transmission of related control parameters to the control processor 151 for which calculation has been completed.

[0137] As can be seen, in the technical solution according to this embodiment, when the control processor detects an arc occurrence during the control of the dual-processor equipment, it can stop the processor that is operated on from acquiring the equipment operation data and can also send a turn-off calculation instruction to the calculation processor. The calculation processor can determine whether to suspend the calculation of the relevant control parameters or stop sending the relevant control parameters that have been calculated to the control processor based on whether the equipment operation data is acquired or whether a turn-off calculation instruction is acquired, thereby ensuring that the control processor acquires accurate control parameters and preventing the occurrence of an arc. When the control processor turns off the circuit, the data between the dual processors can maintain good accuracy, the PID calculation can be stopped in a timely manner, the turn-off occasion point can be avoided to be extended, and the situation of data discarding can be reduced. When one end of the circuit is turned off, the other end can continue to execute, which can cause the entire circuit to operate erratically. Unless the entire PID calculation has started, the calculation can be suspended or the operating parameters of the calculation can be omitted. This is applicable to command, handshake or data sharing. When the control processor turns off, the data is frozen, which can ensure the stability and consistency of data transmission between the control processor and the calculation processor. When the control processor circuit is turned off, the other end can continue to execute unnecessary calculations, which can cause the entire circuit to operate erratically. When an arc occurs, the data accuracy between the control processor and the calculation processor can be effectively ensured.

[0138] Example 16 As an improvement of the fifteenth embodiment, the schematic diagram is the same as FIG. 18, and another dual processor device according to the disclosed embodiment of the present invention comprises: a control processor that performs a specified operation upon detecting an arc, the specified operation comprising: Operation 1: stopping the acquisition of device operation data by the processor; a control processor including at least one of the following operations: The operation policy is determined based on the result of the specified operation, thereby ensuring that the control processor 21 obtains accurate control parameters. The result of the specified operation includes whether or not the device operation data is obtained and whether or not the turn-off operation instruction is obtained. The operation policy is: Method 1 for interrupting the calculation operation of the relevant control parameters; and a calculation processor including at least one of a method 2 for stopping transmission of related control parameters to the control processor once calculation has been completed.

[0139] In some alternative embodiments, the control processor performs a turn-off operation simultaneously with stopping the acquisition of equipment operational data by the operating processor.

[0140] It should be noted that the manner in which the arithmetic control module acquires the equipment operation data may be that the control processor voluntarily transmits the equipment operation data to the arithmetic processor, or that the arithmetic processor reads the equipment operation data from the control processor. In an embodiment of the present invention, when the control processor stops the processor operated by the control processor from acquiring the equipment operation data, this may be understood as the control processor stopping the voluntarily transmitting the equipment operation data to the arithmetic processor, or the arithmetic processor stopping the voluntarily reading the equipment operation data of the arithmetic processor.

[0141] In some alternative embodiments, the apparatus further includes a shared memory in which a turn-off instruction identifier is set, the state of the turn-off instruction identifier including a turn-off state and a normal state, and the control processor sending the turn-off operation instruction to the operation processor including the control processor performing a turn-off operation and setting the state of the turn-off instruction identifier to the turn-off state, and an operation processor that obtains the state of the turn-off instruction identifier from the shared memory and considers the turn-off state to be the turn-off operation instruction.

[0142] In some alternative embodiments, the control processor obtains equipment operating data from the compute processor via the shared memory, and the compute processor obtains equipment operating data from the shared memory and sends control parameters to the control processor via the shared memory.

[0143] In some alternative embodiments, the control processor sending the turn off operation instruction to the operation processor comprises: the control processor sending a pre-turn-off output pre-shake handset to the calculation processor; The calculation processor receives a pre-turn-off output pre-shake hand, stops the relevant calculation operation based on the pre-turn-off output pre-shake hand, and sends a calculation stop notification to the control processor after completing the calculation of the received data; After the control processor receives the operation stop notification sent by the operation processor, it performs a turn-off operation.

[0144] In some alternative embodiments, when the control processor detects an arc, it queries the existence of control parameters that are not being transmitted and stops transmitting control parameters that are not currently being transmitted.

[0145] In some alternative embodiments, if the operational processor does not receive equipment operating data transmitted by the control processor, it stops all current control parameter calculations.

[0146] In some alternative embodiments, the control parameter calculation includes a PID calculation step and a digital-to-analog conversion step in sequence, and the calculation processor determining the operation policy based on the result generated by the specified operation includes: determining a current control parameter calculation progress after the calculation processor receives a turn-off calculation instruction sent by the control processor; not performing the PID calculation and subsequent digital-to-analog conversion if related equipment operation data has been received and analog-to-digital conversion has been started but the PID calculation has not been started; and completing the current PID calculation if related equipment operation data has been received and PID calculation has been started but the digital-to-analog calculation has not been started.

[0147] In some alternative embodiments, if the computing processor does not receive equipment operation data sent by the control processor, or if the turn-off instruction identifier that the computing processor receives from the shared memory is in the turn-off state, the computing processor enters a limited sleep state.

[0148] In some alternative embodiments, after the computing processor ceases its associated computing operation based on the pre-turn-off output pre-shake hand, the computing processor enters a limited sleep state.

[0149] In some alternative embodiments, the method further includes a shared memory in which a turn-off instruction identifier is set in the shared memory, the state of the turn-off instruction identifier includes a turn-off state and a normal state, the control processor enters a limited sleep state after performing the turn-off operation, the control processor restarts when a restart condition is met, sets the turn-off instruction identifier in the shared memory to the normal state, and recovers the shared memory to transmit the reacquired equipment operation data to the calculation processor via the shared memory, and the calculation processor recovers the acquisition of the state of the turn-off instruction identifier in the shared memory.

[0150] In some alternative embodiments, the control processor enters a limited sleep state after performing a turn-off operation; When the restart condition is satisfied, the control processor sends a restarted preshake hand to the calculation processor, and after receiving the recovery confirmation message fed back by the calculation processor, it resumes obtaining the equipment operation data and allows the calculation processor to resume obtaining the equipment operation data; the calculation processor receives the preshake hand sent and restarted by the control processor, completes preparation for calculation recovery based on the restarted preshake hand, and sends a recovery confirmation message to the control processor.

[0151] In some alternative embodiments, the operational processor freezes the acquired equipment operational data for the arcing period before entering the limited sleep state, and the control processor freezes the equipment operational data for the arcing period before entering the limited sleep state.

[0152] As can be seen, in the technical solution according to this embodiment, in the process of controlling the dual-processor equipment, when the control processor detects the occurrence of an arc, it can stop the processor to calculate the equipment operation data, and can also send a turn-off calculation instruction to the calculation processor. The calculation processor can determine whether to suspend the calculation operation of the related control parameters or stop sending the related control parameters that have been calculated to the control processor based on whether the equipment operation data is obtained or whether a turn-off calculation instruction is obtained, thereby ensuring that the control processor obtains accurate control parameters and preventing the occurrence of an arc. When the control processor turns off the circuit, the data between the dual processors can maintain good accuracy, the PID calculation can be stopped in a timely manner, the turn-off occasion point can be avoided to be extended, and the situation of data discarding can be reduced. When one end of the circuit is turned off, the other end can continue to execute, which can cause the entire circuit to operate erratically. Unless the entire PID calculation has started, the calculation can be suspended or the operating parameters of the calculation can be omitted. This is applicable to command, handshake or data sharing. When the control processor turns off, the data is frozen, which can ensure the stability and consistency of data transmission between the control processor and the calculation processor. When the control processor circuit is turned off, the other end can continue to execute unnecessary calculations, which can cause the entire circuit to operate erratically. When an arc occurs, the data accuracy between the control processor and the calculation processor can be effectively ensured.

[0153] Example 17 As shown in FIG. 22, an embodiment of the present invention further provides a dual-processor device control method, which is used in a dual-processor device, where the dual processor includes a control processor and an arithmetic processor, and the method is used in the control processor, and includes:

[0154] S171: When an arc occurrence is detected, the control processor executes a specified operation, and the specified operation includes at least one of operation 1 of stopping the processor to acquire equipment operation data and operation 2 of sending a turn-off calculation instruction to the calculation processor.

[0155] S172: The calculation processor determines an operation policy based on the results generated by the specified operation to ensure that the control processor obtains accurate control parameters, where the results generated by the specified operation include whether or not equipment operation data has been obtained and whether or not a turn-off calculation instruction has been obtained, and the operation policy includes at least one of method 1 for suspending the calculation operation of the related control parameters and method 2 for stopping the transmission of related control parameters whose calculation has been completed to the control processor.

[0156] In some alternative embodiments, when the control processor detects an arc, it queries the existence of control parameters that are not being transmitted and stops transmission of control parameters that are not currently being transmitted.

[0157] In some alternative embodiments, the specified operation further includes performing a turn-off operation simultaneously with the control processor ceasing acquisition of equipment operational data by the computed processor.

[0158] In some alternative embodiments, the dual-processor device further includes a shared memory, wherein a turn-off instruction identifier is set in the shared memory, and the state of the turn-off instruction identifier includes a turn-off state and a normal state, and in that aspect, the control processor sending the turn-off operation instruction to the operation processor includes the control processor performing a turn-off operation and setting the state of the turn-off instruction identifier to a turn-off state, whereby the operation processor obtains the state of the turn-off instruction identifier from the shared memory and considers the turn-off state as the turn-off operation instruction.

[0159] In some alternative embodiments, the control processor transmits the equipment operational data to the computing processor via a shared memory.

[0160] In some alternative embodiments, the control processor sending a turn-off operation instruction to the calculation processor is that the control processor sends a pre-turn-off output pre-shake handset to the calculation processor, performs the turn-off operation after receiving the calculation stop notification sent by the calculation processor, and determines the operation policy based on whether the calculation processor has received the equipment operation data.

[0161] In some alternative embodiments, the control processor enters a limited sleep state after performing a turn-off operation, and restarts when a restart condition is met, sets a turn-off instruction identifier in the shared memory to a normal state, and resumes sending the re-acquired equipment operation data to the calculation processor via the shared memory, or sends a restarted preshake handset to the calculation processor when the restart condition is met, and resumes acquiring the equipment operation data after receiving a recovery confirmation message fed back by the calculation processor, and resumes acquiring the equipment operation data by the calculation processor.

[0162] As can be seen, in the technical solution according to this embodiment, in the process of controlling the dual-processor equipment, when the control processor detects the occurrence of an arc, it can stop the processor to calculate the equipment operation data, and can also send a turn-off calculation instruction to the calculation processor. The calculation processor can determine whether to suspend the calculation operation of the related control parameters or stop sending the related control parameters that have been calculated to the control processor based on whether the equipment operation data is obtained or whether a turn-off calculation instruction is obtained, thereby ensuring that the control processor obtains accurate control parameters and preventing the occurrence of an arc. When the control processor turns off the circuit, the data between the dual processors can maintain good accuracy, the PID calculation can be stopped in a timely manner, the turn-off occasion point can be avoided to be extended, and the situation of data discarding can be reduced. When one end of the circuit is turned off, the other end can continue to execute, which can cause the entire circuit to operate erratically. Unless the entire PID calculation has started, the calculation can be suspended or the operating parameters of the calculation can be omitted. This is applicable to command, handshake or data sharing. When the control processor turns off, the data is frozen, which can ensure the stability and consistency of data transmission between the control processor and the calculation processor. When the control processor circuit is turned off, the other end can continue to execute unnecessary calculations, which can cause the entire circuit to operate erratically. When an arc occurs, the data accuracy between the control processor and the calculation processor can be effectively ensured.

[0163] Example 18 As shown in FIG. 23, an embodiment of the present invention further provides a dual-processor device control method, which is used in a dual-processor device, where the dual processor includes a control processor and an arithmetic processor, and the method is used in the arithmetic processor, and includes:

[0164] S181: The calculation processor acquires a result generated after the control processor executes a specified operation, and the specified operation includes at least one of operation 1 of stopping the processor being calculated from acquiring equipment operation data and operation 2 of sending a turn-off calculation instruction to the calculation processor, and the result generated by the specified operation includes whether or not the equipment operation data has been acquired and whether or not the turn-off calculation instruction has been acquired.

[0165] S182: The calculation processor determines an operation policy based on the results generated by the specified operation to ensure that the control processor obtains accurate control parameters, and the operation policy includes at least one of method 1 of suspending the calculation operation of the related control parameters and method 2 of stopping the transmission of related control parameters whose calculation has been completed to the control processor.

[0166] In some alternative embodiments, the dual-processor device further includes a shared memory, in which a turn-off instruction identifier is set, and the state of the turn-off instruction identifier includes a turn-off state and a normal state, and in this aspect, after executing the turn-off operation, the control processor sets the state of the turn-off instruction identifier to a turn-off state, and the operation processor obtains the state of the turn-off instruction identifier from the shared memory and regards the turn-off state as a turn-off operation instruction.

[0167] In some alternative embodiments, the operational processor retrieves equipment operating data from the shared memory and transmits control parameters to the control processor via the shared memory.

[0168] In some alternative embodiments, when the control processor sends a pre-turn-off output preshake hand to the calculation processor, the calculation processor receives the pre-turn-off output preshake hand, stops the associated calculation operation based on the pre-turn-off output preshake hand, and sends a calculation stop notification to the control processor after completing the calculation of the received data, so that the control processor performs the turn-off operation after obtaining the calculation stop notification sent by the calculation processor.

[0169] In some alternative embodiments, if the operational processor does not obtain equipment operating data for the control processor, it will stop all current control parameter calculations.

[0170] In some alternative embodiments, the control parameter calculation includes a PID calculation step and a digital-to-analog conversion step in sequence, and the calculation processor determining the operation policy based on the result generated by the specified operation includes: determining a current control parameter calculation progress after the calculation processor receives a turn-off calculation instruction sent by the control processor; not performing the PID calculation and subsequent digital-to-analog conversion if related equipment operation data has been received and analog-to-digital conversion has been started but the PID calculation has not been started; and completing the current PID calculation if related equipment operation data has been received and PID calculation has been started but the digital-to-analog calculation has not been started.

[0171] In some alternative embodiments, if the computing processor does not acquire equipment operation data from the control processor, or if the turn-off instruction identifier acquired by the computing processor from the shared memory indicates a turn-off state, the computing processor enters a limited sleep state.

[0172] In some alternative embodiments, after the computing processor ceases its associated computing operation based on the pre-turn-off output pre-shake hand, the computing processor enters a limited sleep state.

[0173] In some alternative embodiments, the control processor sets the turn-off instruction identifier in the shared memory to a normal state and resumes sending reacquired equipment operation data to the computing processor via the shared memory, and the computing processor resumes acquiring the state of the turn-off instruction identifier in the shared memory, or the computing processor acquires the preshake handshake sent and restarted by the control processor, and then completes preparations for computing recovery based on the restarted preshake handshake and sends a recovery confirmation message to the control processor.

[0174] In some alternative embodiments, the computing processor freezes the acquired equipment operational data for the arcing period before entering the limited sleep state.

[0175] As can be seen, in the technical solution according to this embodiment, in the process of controlling the dual-processor equipment, when the control processor detects the occurrence of an arc, it can stop the processor to calculate the equipment operation data, and can also send a turn-off calculation instruction to the calculation processor. The calculation processor can determine whether to suspend the calculation operation of the related control parameters or stop sending the related control parameters that have been calculated to the control processor based on whether the equipment operation data is obtained or whether a turn-off calculation instruction is obtained, thereby ensuring that the control processor obtains accurate control parameters and preventing the occurrence of an arc. When the control processor turns off the circuit, the data between the dual processors can maintain good accuracy, the PID calculation can be stopped in a timely manner, the turn-off occasion point can be avoided to be extended, and the situation of data discarding can be reduced. When one end of the circuit is turned off, the other end can continue to execute, which can cause the entire circuit to operate erratically. Unless the entire PID calculation has started, the calculation can be suspended or the operating parameters of the calculation can be omitted. This is applicable to command, handshake or data sharing. When the control processor turns off, the data is frozen, which can ensure the stability and consistency of data transmission between the control processor and the calculation processor. When the control processor circuit is turned off, the other end can continue to execute unnecessary calculations, which can cause the entire circuit to operate erratically. When an arc occurs, the data accuracy between the control processor and the calculation processor can be effectively ensured.

[0176] Example 19 To facilitate the reader's understanding, the following describes a dual processor device and a control method thereof according to an embodiment of the present invention using specific examples.

[0177] In this embodiment, CPUA is a control processor and CPUB is an arithmetic processor. The two CPUs operate independently and control the control circuit and PID arithmetic circuit connected to them, respectively. Between the dual CPUs, commands (COMMAND / ORDER), shake hands (SHAKE HANDS), flags (FLAG), or data sharing methods are used to cause CPUB to interrupt PID. The entire PID arithmetic block is divided into three stages: an analog-to-digital conversion stage, a PID calculation stage, and a digital-to-analog conversion stage, i.e., DC-PID-DAC.

[0178] The entire PID control flow is as follows:

[0179] During the first timing, CPUA transmits the data required for PID calculation to CPUB, CPUB acquires the data and performs PID calculations. CPUA detects an arc and sends a turn-off command or a rewrite flag. The CPU B acquires the instruction or FLAG and determines at what stage to suspend the operation depending on the current operating state. If it is between ADC and PID, the calculation after PID is stopped. If it is before the PID period and DAC, the calculation is completed but the calculated data is not output.

[0180] Or, When CPUA decides to turn off, it will not transmit any data or information, At the time CPUB acquired the data, it had not acquired CPUA's data or information, Or if there is no updated data or information available in the shared RAM, all PID calculations are directly suspended.

[0181] At the Nth timing, N is an integer greater than 1; The CPUA restarts the control circuit and outputs power. CPUA transmits the data required for PID calculation to CPUB, CPUB acquires the data and performs PID calculations.

[0182] Or, The CPUA restarts the control circuit and outputs power. CPUA rewrites the CPUA operation flag in RAM, CPUA transmits the data required for PID calculation and writes it to RAM. CPUB reads the enable flag of CPUA in RAM and determines that it is ENABLE. CPUB reads RAM, gets the data, performs PID calculation, The CPU B writes the circuit control parameters generated by the calculation into the RAM.

[0183] As can be seen, in the technical solution according to this embodiment, in the process of controlling the dual-processor equipment, when the control processor detects the occurrence of an arc, it can stop the processor to calculate the equipment operation data, and can also send a turn-off calculation instruction to the calculation processor. The calculation processor can determine whether to suspend the calculation operation of the related control parameters or stop sending the related control parameters that have been calculated to the control processor based on whether the equipment operation data is obtained or whether a turn-off calculation instruction is obtained, thereby ensuring that the control processor obtains accurate control parameters and preventing the occurrence of an arc. When the control processor turns off the circuit, the data between the dual processors can maintain good accuracy, the PID calculation can be stopped in a timely manner, the turn-off occasion point can be avoided to be extended, and the situation of data discarding can be reduced. When one end of the circuit is turned off, the other end can continue to execute, which can cause the entire circuit to operate erratically. Unless the entire PID calculation has started, the calculation can be suspended or the operating parameters of the calculation can be omitted. This is applicable to command, handshake or data sharing. When the control processor turns off, the data is frozen, which can ensure the stability and consistency of data transmission between the control processor and the calculation processor. When the control processor circuit is turned off, the other end can continue to execute unnecessary calculations, which can cause the entire circuit to operate erratically. When an arc occurs, the data accuracy between the control processor and the calculation processor can be effectively ensured.

[0184] Example 20 Based on the same technical idea, an embodiment of the present application further provides a computer device, which includes a memory and a processor, a computer program stored in the memory, and when the processor executes the computer program, the dual processor device control method described in any one of the above claims is realized.

[0185] Here, the memory includes at least one type of readable storage medium, including a flash memory, a hard disk, a multimedia card, a card-type memory (e.g., SD or DX memory), a magnetic memory, a magnetic disk, an optical disk, etc. In some embodiments, the memory may be an internal storage unit of the OTT video traffic monitoring system, such as a hard disk. In other embodiments, the memory may be an external storage device of the OTT video traffic monitoring system, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, or a flash memory card.

[0186] Furthermore, the memory may include an internal storage unit of the OTT video traffic monitoring system and an external storage device, which can be used not only to store various data such as application software installed in the OTT video service monitoring system and the code of the OTT video service monitoring program, but also to temporarily store output data or data to be output.

[0187] The processor, in some embodiments, may be a central processing unit, controller, microcontroller, microprocessor, or other data processing chip for executing program code or processing data stored in memory, such as to execute an OTT video traffic monitoring program.

[0188] As can be seen, in the technical solution of this embodiment, in the PID control process based on dual processors, when the control processor detects the occurrence of an arc, it performs a turn-off operation and sets the turn-off instruction identifier in the shared memory to a turn-off state. The calculation processor skips acquiring the equipment operating data that the control processor would acquire during the arcing period based on the state of the turn-off instruction identifier. The shared memory utilizes a data sharing mode in which even if one CPU writes and area protection occurs, the other CPU can still read. Therefore, no matter what work both CPUs are performing, they can immediately acquire the changing data and operating status of the other CPU from the high-speed storage unit. This ensures the stability and consistency of data transmission between the control processor and the calculation processor, and avoids the disruptive operation of the entire circuit caused by the calculation processor at the other end still performing unnecessary calculations when the control processor circuit is turned off. This effectively ensures the accuracy of data between the control processor and the calculation processor when an arc occurs.

[0189] The disclosed embodiments of the present invention further provide a computer-readable storage medium having a computer program stored therein, which, when executed by a processor, performs the steps of the dual-processor appliance control method described in the above method embodiments. The storage medium may be a volatile or non-volatile computer-readable storage medium. A computer program product for the dual-processor appliance control method according to the disclosed embodiments of the present invention includes a computer-readable storage medium storing program code, and instructions included in the program code may be used to perform the steps of the dual-processor appliance control method described in the above method embodiments. Please refer to the above method embodiments for details, and no further description will be given herein.

[0190] The disclosed embodiments of the present invention further provide a computer program product, which, when executed by a processor, realizes any of the methods of the aforementioned embodiments. The computer program product may be specifically implemented in the form of hardware, software, or a combination thereof. In one alternative embodiment, the computer program product may be specifically embodied as a computer storage medium, and in another alternative embodiment, the computer program product may be specifically embodied as a software product, such as a software development kit (SDK).

[0191] As can be understood, identical or similar parts in each of the above embodiments can be referenced to each other, and content that is not described in detail in some embodiments can be referenced to identical or similar content in other embodiments.

[0192] It should be noted that in describing the present invention, the terms "first," "second," etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance. Also, in describing the present invention, unless otherwise specified, "plurality" means at least two.

[0193] Any process or method description described in a flowchart or otherwise herein may be understood as representing a module, segment, or portion comprising one or more codes of executable instructions for implementing specific logical functions or process steps, and the scope of the preferred embodiments of the present invention includes other implementations, and may include performing functions not in the order shown or discussed, but essentially simultaneously or in reverse order depending on the functionality involved, as should be understood by those skilled in the art to which the embodiments of the present invention pertain.

[0194] It should be understood that each part of the present invention may be realized by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods may be realized by software or firmware stored in a memory and executed by an appropriate instruction execution system. For example, when realized by hardware, as in other embodiments, it may be realized by any one or combination of technologies known in the art, such as a discrete logic circuit having logic gate circuits for implementing logic functions on data signals, an application specific integrated circuit having appropriate combinational logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0195] Those skilled in the art will understand that realizing all or part of the steps included in the method of the above embodiments can be accomplished by instructing relevant hardware by a program, and the program may be stored in a computer-readable storage medium, and when the program is executed, it will include one or a combination of the steps of the method embodiments.

[0196] Note that each functional unit in each embodiment of the present invention may be integrated into one processor, each unit may exist physically independently, or two or more units may be integrated into one module. The integrated module may be realized in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may be stored in a computer-readable storage medium.

[0197] The storage medium may be a read-only memory, a magnetic disk, an optical disk, etc.

[0198] In the description herein, references to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" mean that the specific features, structures, materials, or characteristics described with reference to the embodiment or example are included in at least one embodiment or example of the present invention. In the description herein, schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0199] Although the embodiments of the present invention have been described above, it should be understood that the above embodiments are illustrative and do not limit the present invention, and that those skilled in the art may make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. 1. A dual processor device control method, comprising: the dual processor includes a control processor and an arithmetic processor; The method is implemented by the control processor; Upon detecting an arc occurrence, sending a pre-turn-off output pre-shake hand to the calculation processor, so that the calculation processor stops related calculation operations based on the pre-turn-off output pre-shake hand; receiving an operation stop notification sent by the arithmetic processor, the operation stop notification being issued after the arithmetic processor has completed the operation of the received data since receiving the pre-turn-off output pre-shake handset; and performing a turn-off operation.

2. The method comprises: If a restart condition is satisfied, sending a restarted preshake hand to the computing processor, so that the computing processor regains its computing readiness based on the restarted preshake hand; 2. The dual-processor device control method of claim 1, further comprising: a step of recovering acquisition of device operation data and recovering transmission of the device operation data to the computing processor after receiving a recovery confirmation message fed back by the computing processor, wherein the recovery confirmation message is transmitted after the computing processor has completed preparation for operation.

3. before sending a restarted preshake handset to said processor; further comprising determining whether the computing processor is in a sleep state; 3. The dual processor device control method of claim 2, wherein sending a restarted preshake hand to the computing processor is sending a restarted preshake hand to the computing processor if the computing processor is in a sleep state.

4. before sending a restarted preshake handset to said processor; 4. The dual-processor appliance control method according to claim 3, further comprising the step of directly acquiring the appliance operation data and transmitting the appliance operation data to the arithmetic processor when the arithmetic processor is not in a sleep state.

5. The restart condition is Whether the turn-off time meets the preset turn-off time length; 3. The dual processor device control method according to claim 2, further comprising determining whether or not to receive restart instruction information.

6. 6. The dual-processor device control method of claim 5, further comprising the step of entering a sleep state after performing a turn-off operation.

7. Before going to sleep, 7. The dual processor appliance control method of claim 6, further comprising the step of freezing appliance operation data for the period of arcing.

8. 1. A control processor for a dual processor device, comprising: a pre-turn-off instruction module for sending a pre-turn-off output pre-shake hand to an arithmetic processor upon detecting an arc occurrence, thereby causing the arithmetic processor to stop an associated arithmetic operation based on the pre-turn-off output pre-shake hand; a pre-turn-off execution module for receiving an operation stop notification sent by the arithmetic processor, the operation stop notification being issued after the arithmetic processor has completed an operation on the received data after receiving the pre-turn-off output pre-shake handset; and a turn-off module for performing a turn-off operation.

9. 1. A dual processor device control method, comprising: the dual processor includes a control processor and an arithmetic processor; The method is implemented by a computing processor, receiving a pre-turn-off output pre-shake handset sent by the control processor; completing the operation on the received data and then stopping the associated operation; sending an operation stop notification to the control processor, so that the control processor performs a turn-off operation after receiving the operation stop notification.

10. receiving a preshake handshake sent and reinitiated by the control processor; completing preparations for operation recovery based on the restarted preshake handshake; sending a recovery confirmation message to the control processor, whereby the control processor recovers acquisition of equipment operational data based on the recovery confirmation message; 10. The dual processor appliance control method of claim 9, further comprising the step of: receiving the appliance operation data transmitted by the control processor.

11. 11. A dual processor device control method according to claim 9, wherein after sending a notice to stop operation to the control processor, the method further comprises entering a sleep state.

12. Before going to sleep, The method comprises:

12. The dual-processor appliance control method of claim 11, further comprising the step of freezing appliance operation data for the period of arcing.

13. 1. A computing processor for a dual processor device, comprising: a pre-turn-off instruction receiving module for receiving a pre-turn-off output pre-shake hand signal sent by the control processor; an operation stop control module for stopping the associated operation after completing the operation of the received data; and an operation stop notification module for sending an operation stop notification to the control processor, so that the control processor performs a turn-off operation after receiving the operation stop notification.

14. 1. A dual processor device, comprising: A dual processor device comprising: a control processor for a dual processor device according to claim 8; and an arithmetic processor for a dual processor device according to claim 13.

15. 1. A dual processor device control method, comprising: the dual processor device includes a control processor, an arithmetic processor, and a shared memory, and a turn-off instruction identifier is set in the shared memory; The method is implemented by the control processor; performing a turn-off operation upon detecting an arc; A dual processor equipment control method comprising: a step of causing the calculation processor to skip acquiring first equipment operation data based on the state of the turn-off instruction identifier by setting the turn-off instruction identifier in the shared memory to a turn-off state, wherein the first equipment operation data is equipment operation data acquired by the control processor during an arc generation period.

16. Before detecting an arc, The method comprises: acquiring second device operation data; 16. The dual-processor appliance control method of claim 15, further comprising the step of: transmitting the second appliance operation data to the computing processor via the shared memory.

17. The step of transmitting the second device operation data to the computing processor via the shared memory includes:

17. The dual processor appliance control method of claim 16, further comprising the step of storing the second appliance operation data in the shared memory so that the computing processor can obtain the second appliance operation data from the shared memory.

18. After performing the turn-off operation, 20. The dual processor appliance control method of claim 17, further comprising the step of entering a sleep state.

19. The method comprises: If the restart condition is met, restarting; setting a turn-off instruction identifier in the shared memory to a normal state; Restoring the acquisition of the second device operational data; 20. The dual-processor appliance control method of claim 18, further comprising: a step of recovering transmission of the second appliance operation data to the computing processor via the shared memory, whereby the computing processor acquires the second appliance operation data from the shared memory based on the state of the turn-off instruction identifier.

20. The restart condition is Whether the turn-off time meets the preset turn-off time length; 20. The dual processor device control method according to claim 19, further comprising determining whether or not to receive restart instruction information.

21. Before going to sleep, 21. The dual processor appliance control method of claim 20, further comprising freezing appliance operating data for the period of arcing.

22. 1. A dual processor device, comprising: the dual processor device includes a control processor, an arithmetic processor, and a shared memory, and a turn-off instruction identifier is set in the shared memory; The control processor a turn-off indication module for performing a turn-off operation upon detecting an arc; a turn-off state setting module for causing the calculation processor to skip acquiring first equipment operation data based on the state of the turn-off instruction identifier by setting the turn-off instruction identifier in the shared memory to a turn-off state, wherein the first equipment operation data is equipment operation data acquired by the control processor during an arc generation period.

23. 1. A dual processor device control method, comprising: The dual processor device includes a control processor and a shared memory, and a turn-off instruction identifier is set in the shared memory; The method is implemented by the computing processor, obtaining a state of the turn-off indication identifier in the shared memory; and if the turn-off instruction identifier is in a turn-off state, skipping acquisition of first equipment operation data based on the state of the turn-off instruction identifier, wherein the first equipment operation data is equipment operation data acquired by the control processor during an arc generation period.

24. If the turn-off instruction identifier is in a normal state, acquiring first device operation data from the shared memory; calculating a control parameter based on the first device operation data; 24. The dual processor appliance control method of claim 23, further comprising the step of: transmitting the calculated control parameters to the control processor via the shared memory.

25. 25. The dual processor device control method of claim 24, further comprising the step of entering a sleep state if the turn-off instruction identifier is a turn-off state.

26. before obtaining the state of the turn-off indication identifier in the shared memory; The method comprises: If a restart condition is satisfied, the method further includes the step of restarting the device; 25. The dual processor device control method of claim 24, wherein the step of acquiring the state of the turn-off instruction identifier in the shared memory is a step of recovering the acquisition of the state of the turn-off instruction identifier in the shared memory.

27. Before going to sleep, 26. The dual processor appliance control method of claim 25, further comprising freezing appliance operating data for the period of arcing.

28. 1. A dual processor device, comprising: a control processor, an arithmetic processor, and a shared memory, wherein a turn-off instruction identifier is set in the shared memory; The arithmetic processor a turn-off identifier acquisition module for acquiring a status of the turn-off indication identifier in the shared memory; a turn-off data processing module for skipping acquisition of first equipment operation data based on the state of the turn-off instruction identifier when the turn-off instruction identifier is in a turn-off state, the first equipment operation data being equipment operation data acquired by the control processor during an arc occurrence period.

29. 1. A dual processor device, comprising:

29. A dual processor apparatus comprising: a shared memory; a control processor according to claim 22; and an arithmetic processor according to claim 28, wherein a turn-off instruction identifier is set in the shared memory.

30. A computer device comprising a processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the computer device is executed, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the computer device performs a dual processor device control method described in any one of claims 1 to 7, 9 to 12, 15 to 21, or 23 to 27.

31. A computer-readable storage medium having a computer program stored therein, the computer program executing, when executed by a processor, a dual processor device control method according to any one of claims 1 to 7, 9 to 12, 15 to 21, or 23 to 27.

Images