Display substrate and display device

Abstract

The display substrate includes a substrate 100, a plurality of data lines DL, a plurality of sub-pixels Px, a plurality of data lead-out lines, and at least one first compensation unit 41. The substrate 100 includes a display area AA and a first bezel area B1 located on one side of the display area AA. The plurality of data lines DL and the plurality of sub-pixels Px are located in the display area AA. The plurality of data lead-out lines are located in the first bezel area B1 and are electrically connected to the plurality of data lines DL in the display area AA. The first compensation unit 41 is located in the first bezel area B1. At least one data lead-out line is electrically connected to the first compensation unit 41, and the first compensation unit 41 is configured to compensate for at least one of the resistance and capacitance of the data line DL electrically connected to the at least one data lead-out line.

Description

[Technical Field]

[0001] The present disclosure relates to the field of display technology, but is not limited thereto, and more particularly to display substrates and display devices. [Background technology]

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active light-emitting display devices that offer advantages such as autonomous light emission, wide viewing angles, high contrast, low power consumption, extremely fast response speeds, light weight, thinness, bendability, and low cost. Summary of the Invention

[0003] The following is a summary of the subject matter described in detail in the text, which is not intended to limit the scope of protection of the claims.

[0004] An embodiment of the present disclosure provides a display substrate and a display device.

[0005] In one aspect, an embodiment of the present disclosure provides a display substrate, including a substrate, a plurality of data lines, a plurality of subpixels, a plurality of data lead-out lines, and at least one first compensation unit. The substrate includes a display area and a first bezel area located on one side of the display area. The plurality of data lines and the plurality of subpixels are located in the display area. The plurality of subpixels are electrically connected to the plurality of data lines. The plurality of data lead-out lines are located in the first bezel area and electrically connected to the plurality of data lines in the display area. The at least one first compensation unit is located in the first bezel area. At least one of the plurality of data lead-out lines is electrically connected to the first compensation unit. The first compensation unit is configured to compensate for at least one of the resistance and capacitance of the data line electrically connected to the at least one data lead-out line.

[0006] In some exemplary embodiments, the first compensation unit includes at least one of at least one first compensation resistor and at least one first compensation capacitor, wherein the first compensation resistor is configured to compensate for a resistance of a data line electrically connected to the at least one data lead-out line, and the first compensation capacitor is configured to compensate for a capacitance of a data line electrically connected to the at least one data lead-out line.

[0007] In some exemplary embodiments, the first compensation unit includes at least one first compensation resistor, and the at least one first compensation resistor is electrically connected in series to the data lead-out line.

[0008] In some exemplary embodiments, the first compensation resistor includes a resistive wiring, the resistive wiring is located in a first gate metal layer or a second gate metal layer, and the first gate metal layer and the second gate metal layer are located in different layers.

[0009] In some exemplary embodiments, the orthogonal projection of the resistive trace of the first compensation resistor on the substrate is a serpentine trace.

[0010] In some exemplary embodiments, the first compensation unit further includes at least one first compensation capacitor, the at least one first compensation capacitor including a first electrode and a second electrode, the first electrode of the at least one first compensation capacitor electrically connected to the at least one first compensation resistor, and the second electrode of the at least one first compensation capacitor electrically connected to a ground terminal.

[0011] In some exemplary embodiments, the at least one first compensation capacitor includes a first plate, a second plate, and a third plate sequentially arranged along a direction away from the substrate, wherein the first plate, the second plate, and the third plate are orthogonally projected onto the substrate and overlap each other, the first plate is electrically connected to the third plate to form the first electrode, and the second plate is the second electrode.

[0012] In some exemplary embodiments, the second plate of the at least one first compensation capacitor is of unitary construction.

[0013] In some exemplary embodiments, the first plate is located on a first gate metal layer, the second plate is located on a second gate metal layer, the third plate is located on a third gate metal layer, and the first gate metal layer, the second gate metal layer, and the third gate metal layer are located on different layers.

[0014] In some exemplary embodiments, the first bezel region includes a first fan-out region located on one side of the display area, and at least one isolation dam is installed in the first fan-out region. At least one data lead-out line of the plurality of data lead-out lines includes a first data fan-out line and a second data fan-out line located in the first fan-out region and electrically connected to each other, the second data fan-out line being located on a side of the first data fan-out line away from the display area and the second data fan-out line being located on a side of the first data fan-out line closer to the substrate. A connection position between the first data fan-out line and the second data fan-out line is located on a side of the isolation dam closer to the display area, and an orthogonal projection of the connection position on the substrate and an orthogonal projection of the isolation dam on the substrate do not overlap.

[0015] In some exemplary embodiments, the resistivity of the material of the first data fan-out line is less than the resistivity of the material of the second data fan-out line.

[0016] In some exemplary embodiments, the first fan-out region includes a plurality of first data fan-out lines and a plurality of second data fan-out lines, the plurality of first data fan-out lines including a plurality of first data fan-out lines of a first type and a plurality of first data fan-out lines of a second type, the first data fan-out lines of the first type and the first data fan-out lines of the second type being spaced apart from each other, the first data fan-out lines of the first type being located closer to the substrate than the first data fan-out lines of the second type, and orthogonal projections of the first data fan-out lines of the first type on the substrate and the first data fan-out lines of the second type on the substrate not overlapping. The plurality of second data fanout lines include a plurality of second data fanout lines of a first type and a plurality of second data fanout lines of a second type, the second data fanout lines of the first type and the second data fanout lines of the second type being spaced apart, the second data fanout lines of the first type being located closer to the substrate than the second data fanout lines of the second type, and the orthogonal projections of the second data fanout lines of the first type on the substrate and the second data fanout lines of the second type on the substrate do not overlap.

[0017] In some exemplary embodiments, first data fanout lines of the first type are electrically connected to second data fanout lines of the first type, and first data fanout lines of the second type are electrically connected to second data fanout lines of the second type.

[0018] In some exemplary embodiments, the first data fan-out lines of the first type are located in a first source-drain metal layer, the first data fan-out lines of the second type are located in a second source-drain metal layer, the second data fan-out lines of the first type are located in a first gate metal layer, and the second data fan-out lines of the second type are located in a second gate layer, and the first gate metal layer, the second gate metal layer, the first source-drain metal layer, and the second source-drain metal layer are located in different layers.

[0019] In some exemplary embodiments, the first compensation unit is electrically connected to the first data fanout line, and the first compensation unit is located in the first fanout region and on a side of the first data fanout line closer to the display area.

[0020] In some exemplary embodiments, the first bezel region further includes a folding region and a second fan-out region sequentially arranged along a direction away from the display region of the first fan-out region, and the at least one data out-line includes a data folding line located in the folding region and a third data fan-out line located in the second fan-out region, and the data folding line is electrically connected to the second data fan-out line of the first fan-out region and the third data fan-out line of the second fan-out region.

[0021] In some exemplary embodiments, the first data fan-out line and the third data fan-out line electrically connected to the second data fan-out line are in the same layer structure.

[0022] In some exemplary embodiments, the substrate further includes a second bezel area located on the remaining side of the display area, wherein at least one second compensation unit and at least one first signal line are installed in the second bezel area, the at least one first signal line is electrically connected to the second compensation unit, and the second compensation unit is configured to compensate at least one of a resistance and a capacitance of the at least one first signal line.

[0023] In some exemplary embodiments, the second compensation unit includes at least one second compensation capacitor, a first electrode of the at least one second compensation capacitor electrically connected to the at least one first signal line, and a second electrode of the at least one second compensation capacitor electrically connected to a ground terminal.

[0024] In some exemplary embodiments, the substrate further includes a second bezel region located on the remaining side of the display region, the second bezel region including a gate drive circuit and a clock signal line electrically connected to the gate drive circuit, and the first bezel region further includes a third compensation unit, the clock signal line is electrically connected to the third compensation unit, and the third compensation unit is configured to compensate for at least one of a resistance and a capacitance of the clock signal line.

[0025] In another aspect, embodiments of the present disclosure provide a display device comprising a display substrate as described above.

[0026] Other aspects will be understood after reading and understanding the drawings and detailed description. [Brief explanation of the drawings]

[0027] [Figure 1] 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. [Figure 2] FIG. 1 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 3] 3 is an operation timing chart of the pixel circuit shown in FIG. 2. [Figure 4] FIG. 2 is a schematic plan view of a portion of a display area according to at least one embodiment of the present disclosure. [Figure 5] FIG. 5 is a schematic local cross-sectional view taken along the QQ′ direction in FIG. 4. [Figure 6] 5 is a schematic diagram of the display area after the light-shielding layer of FIG. 4 is formed. [Figure 7] 5 is a schematic diagram of the display region after the first semiconductor layer of FIG. 4 is formed. [Figure 8] 5 is a schematic diagram of the display area after the first gate metal layer of FIG. 4 is formed. [Figure 9] 5 is a schematic diagram of the display area after forming the second gate metal layer of FIG. 4. FIG. [Figure 10] 5 is a schematic diagram of the display region after the second semiconductor layer of FIG. 4 is formed. [Figure 11]5 is a schematic diagram of the display area after forming the third gate metal layer of FIG. 4. FIG. [Figure 12] 5 is a schematic diagram of the display area after the sixth insulating layer of FIG. 4 is formed. [Figure 13] 5 is a schematic diagram of the display region after the first source-drain metal layer of FIG. 4 is formed. [Figure 14] 5 is a schematic diagram of the display area after the eighth insulating layer of FIG. 4 is formed. FIG. [Figure 15] 5 is a schematic diagram of the display region after the second source-drain metal layer of FIG. 4 is formed. [Figure 16] FIG. 16 is a schematic diagram of the second source-drain metal layer of FIG. 15. [Figure 17] 5 is a schematic diagram of the display area after the ninth insulating layer of FIG. 4 is formed. [Figure 18] 5 is a schematic diagram of the display region after the third source-drain metal layer of FIG. 4 is formed. [Figure 19] FIG. 19 is a schematic diagram of the third source-drain metal layer of FIG. 18. [Figure 20] 5 is a schematic diagram of the display area after the tenth insulating layer of FIG. 4 is formed. [Figure 21] 5 is a schematic diagram of the display area after the anode layer of FIG. 4 is formed. [Figure 22] FIG. 1 is a schematic diagram of local wiring in a first bezel region in accordance with at least one embodiment of the present disclosure. [Figure 23] FIG. 2 is an equivalent circuit diagram of a first compensation unit according to at least one embodiment of the present disclosure. [Figure 24] FIG. 2 is a partial schematic view of a first bezel area of ​​at least one embodiment of the present disclosure. [Figure 25] FIG. 2 is an equivalent circuit diagram of a first anti-static circuit in accordance with at least one embodiment of the present disclosure. [Figure 26] FIG. 25 is a locally enlarged view of an area D1 in FIG. 24. [Figure 27] FIG. 27 is a schematic diagram of the light-shielding layer of FIG. 26. [Figure 28] 27 is a schematic local view of the first bezel region after the first semiconductor layer in FIG. 26 is formed. [Figure 29]27 is a schematic local view of the first bezel region after the first gate metal layer of FIG. 26 is formed. [Figure 30] 27 is a partial schematic view of the first bezel region after forming the second gate metal layer in FIG. 26. FIG. [Figure 31] 27 is a schematic local view of the first bezel region after the sixth insulating layer in FIG. 26 is formed. FIG. [Figure 32] 27 is a schematic local view of the first bezel region after the first source / drain metal layer in FIG. 26 is formed. [Figure 33] 27 is a schematic local view of the first bezel region after the eighth insulating layer of FIG. 26 is formed. FIG. [Figure 34] 27 is a schematic local view of the first bezel region after the second source / drain metal layer in FIG. 26 is formed. FIG. [Figure 35] 27 is a schematic local view of the first bezel area after the ninth insulating layer of FIG. 26 is formed. [Figure 36] FIG. 2 is a partial schematic diagram of a first compensation resistor according to at least one embodiment of the present disclosure. [Figure 37] FIG. 25 is a locally enlarged view of an area D2 in FIG. 24. [Figure 38] FIG. 38 is a local schematic view of the first fan-out region after forming the first gate metal layer of FIG. 37. [Figure 39] FIG. 38 is a local schematic view of the first fan-out region after forming the second gate metal layer of FIG. 37. [Figure 40] FIG. 38 is a local schematic view of the first fan-out region after forming the third gate metal layer of FIG. 37. [Figure 41] FIG. 38 is a local schematic view of the first fan-out region after the sixth insulating layer of FIG. 37 is formed. [Figure 42] FIG. 25 is a locally enlarged view of an area D3 in FIG. 24. [Figure 43] 43 is a local schematic view of the first fan-out region after forming the second gate metal layer of FIG. 42. FIG. [Figure 44] FIG. 43 is a local schematic view of the first fan-out region after the first source / drain metal layer in FIG. 42 is formed. [Figure 45] FIG. 25 is a locally enlarged view of an area D4 in FIG. 24. [Figure 46] 46 is a schematic local cross-sectional view taken along the UU' direction in FIG. 45. FIG. [Figure 47] FIG. 46 is a local schematic view of the first fan-out region after forming the second gate metal layer of FIG. 45. [Figure 48] FIG. 46 is a local schematic view of the first fan-out region after the first source / drain metal layer of FIG. 45 is formed. [Figure 49] FIG. 10 is a partial schematic view of a second bezel area of ​​at least one embodiment of the present disclosure. [Figure 50] FIG. 10 is an exemplary schematic diagram of a second compensation unit according to at least one embodiment of the present disclosure. [Figure 51] FIG. 51 is a schematic diagram of the first gate metal layer of FIG. 50. [Figure 52] FIG. 51 is a schematic diagram of the second gate metal layer of FIG. 50. [Figure 53] FIG. 10 is a connection schematic diagram of a third compensation unit according to at least one embodiment of the present disclosure. [Figure 54] FIG. 10 is another schematic diagram of a first bezel area of ​​at least one embodiment of the present disclosure. [Figure 55] 1 is a schematic diagram of a display device in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0028] The drawings are intended to facilitate a better understanding of the technical solution of the present disclosure, constitute a part of the specification, and are used to explain the technical solution of the present disclosure together with the embodiments of the present application, and are not intended to limit the technical solution of the present disclosure. The shape and size of one or more components in the drawings are intended only to provide a rough description of the present disclosure and do not reflect the true proportions.

[0029] The following describes in detail the embodiments of the present disclosure with reference to the drawings. The embodiments can be implemented in a variety of forms. Those skilled in the art can easily understand that the method and content can be converted into other forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to only those described in the following embodiments. Unless there is a conflict, the embodiments and features in the embodiments in the present disclosure can be arbitrarily combined.

[0030] In the drawings, for clarity, the size of one or more components, the thickness of layers, or the area thereof may be exaggerated. Therefore, one embodiment of the present disclosure is not necessarily limited to the dimensions, and the shape and size of one or more parts in the drawings do not reflect the true ratio. Furthermore, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes, numerical values, etc. shown in the drawings.

[0031] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of elements and are not intended to limit the quantity. In this disclosure, "plurality" means two or more.

[0032] For convenience, the present specification uses terms indicating orientations or positional relationships, such as "center," "top," "bottom," "front," "rear," "vertical," "horizontal," "upper," "bottom," "inner," and "outer," to describe the positional relationships of components with reference to the drawings. This is merely to facilitate and simplify the description of the specification, and does not indicate or imply that the devices or components referred to must have a specific orientation, be configured, or operate in a specific orientation, and is not intended to limit the present disclosure. The positional relationships of components may be changed as appropriate depending on the orientation of the components described. Therefore, the terms used in the description are not limited to those used in the description, and may be changed as appropriate depending on the situation.

[0033] In this specification, unless otherwise clearly specified or limited, the terms "attached," "coupled," and "connected" should be understood in a broad sense. For example, they may refer to a fixed connection, a detachable connection, or an integral connection, or may be a mechanical connection or connection. They may be a direct connection, an indirect connection via middleware, or internal communication between two elements. Those skilled in the art can understand the meaning of the above terms in this disclosure depending on the context.

[0034] In this specification, "electrically connected" includes cases where components are connected via an element having some kind of electrical function. The "element having some kind of electrical function" is not particularly limited as long as it allows transmission of an electrical signal between the connected components. Examples of the "element having some kind of electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having multiple functions.

[0035] In this specification, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, a channel region refers to a region through which current mainly flows.

[0036] In this specification, the first pole may be the drain and the second pole may be the source, or the first pole may be the source and the second pole may be the drain. The functions of "source" and "drain" may be interchanged, such as when using transistors with reversed polarity or when the direction of current flow changes during circuit operation. Therefore, in this specification, "source" and "drain" may be interchanged. The gate may also be referred to as the control pole.

[0037] In this specification, "parallel" refers to a state in which the angle between two lines is between -10° and 10°, inclusive, and also includes a state in which the angle is between -5° and 5°, inclusive. "Perpendicular" refers to a state in which the angle between two lines is between 80° and 100°, inclusive, and also includes a state in which the angle is between 85° and 95°, inclusive.

[0038] In this specification, the terms "circle, ellipse, triangle, rectangle, trapezoid, pentagon, hexagon, etc." are not used in the strict sense, and the shape may be an approximate circle, an approximate ellipse, an approximate triangle, an approximate rectangle, an approximate trapezoid, an approximate pentagon, an approximate hexagon, etc., and some small deformations due to tolerances may exist, for example, chamfers, arc edges, deformations, etc.

[0039] In this disclosure, the terms "about" and "approximately" do not strictly limit the scope of the invention, but rather refer to the scope of acceptable process or measurement error. In this disclosure, "almost the same" refers to the case where the difference in the numerical value is within 10%.

[0040] In the present disclosure, "A extends along direction B" means that A may include a main body portion and a secondary portion connected to the main body portion, the main body portion being a line, line segment, or strap-like body, the main body portion extending along direction B, and the length of the main body portion extending along direction B being longer than the length of the secondary portion extending along other directions. In the present disclosure, "A extends along direction B" always means "the main body portion of A extends in direction B."

[0041] With the advancement of the information society, there is an increasing demand for display devices that can display a variety of images. For example, there is an increasing demand for medium- to large-sized display devices and display devices with high resolution and high refresh rates. Medium- to large-sized display devices with high resolution and high refresh rates have issues such as an increased data load and short pixel charging times.

[0042] This embodiment provides a display substrate, including a substrate, a plurality of data lines, a plurality of subpixels, a plurality of data lead-out lines, and at least one first compensation unit. The substrate includes a display area and a first bezel area located on one side of the display area. The plurality of data lines and the plurality of subpixels are located in the display area. The plurality of subpixels are electrically connected to the plurality of data lines. The plurality of data lead-out lines are located in the first bezel area and electrically connected to the plurality of data lines in the display area. The first compensation unit is located in the first bezel area and electrically connected to the at least one data lead-out line. The first compensation unit is configured to compensate for at least one of the resistance and capacitance of the data line electrically connected to the at least one data lead-out line.

[0043] The display substrate according to this embodiment uses the first compensation unit to compensate for at least one of the resistance and capacitance of the data lines, thereby improving the load matching of multiple data lines and ensuring display performance. Furthermore, the use of the first compensation unit allows the data load of a large display substrate to be verified using a small display substrate, thereby reducing development costs.

[0044] In some exemplary embodiments, the display substrate of this embodiment may be a liquid crystal display (LCD), an organic light-emitting diode (OLED), a plasma display panel (PDP), or a field emission display (FED). However, this embodiment does not limit the type of the display substrate.

[0045] In some exemplary embodiments, the first compensation unit may include at least one of at least one first compensation resistor and at least one first compensation capacitor. The first compensation resistor may be configured to compensate for the resistance of a data line electrically connected to the at least one data lead-out line, and the first compensation capacitor may be configured to compensate for the capacitance of a data line electrically connected to the at least one data lead-out line. For example, the first compensation unit may include at least one first compensation resistor, or the first compensation unit may include at least one first compensation capacitor, or the first compensation unit may include at least one first compensation resistor and at least one first compensation capacitor. However, this embodiment is not limited thereto.

[0046] In some exemplary embodiments, at least one first compensation resistor included in the first compensation unit may be electrically connected in series to the data lead-out line. For example, the first compensation resistor may include a resistive wiring, which may be located in the first gate metal layer or the second gate metal layer, or the first gate metal layer and the second gate metal layer may be located in different layers. In some examples, to provide a larger compensation resistance, the orthogonal projection of the resistive wiring of the first compensation unit on the substrate may be a serpentine wiring. A serpentine wiring is a type of bent wiring. For example, one end of the wiring extends a distance in one direction, then bends and detours, extends a distance in the opposite direction, bends and detours again, and extends in the same direction, repeatedly bending and detouring in this manner to form a serpentine wiring. Alternatively, the orthogonal projection of the resistive wiring of the first compensation unit on the substrate may be a straight wiring. However, this embodiment is not limited thereto.

[0047] In some exemplary embodiments, the first compensation capacitor included in the first compensation unit may include a first electrode and a second electrode. The first electrode of the first compensation capacitor may be electrically connected to the at least one first compensation resistor, and the second electrode of the first compensation capacitor may be electrically connected to ground. For example, the second electrode of the at least one first compensation capacitor may have an integral structure.

[0048] In some exemplary embodiments, the first bezel region may include a first fan-out region located on one side of the display area. At least one isolation dam may be provided in the first fan-out region. The data lead-out lines may include a first data fan-out line and a second data fan-out line located in the first fan-out region and electrically connected to each other. The second data fan-out line may be located on a side of the first data fan-out line away from the display area. The second data fan-out line may be located on a side of the first data fan-out line closer to the substrate. The connection position of the first data fan-out line and the second data fan-out line may be located on a side of the isolation dam closer to the display area, and the orthogonal projection of the connection position on the substrate and the orthogonal projection of the isolation dam on the substrate do not overlap. In this example, the first data fan-out line and the second data fan-out line are transferred in the first fan-out region, and the connection position of both is located on a side of the isolation dam closer to the display area, thereby preventing water vapor from being introduced into the display area.

[0049] The display substrate of this embodiment will be described below with some examples. In the following exemplary embodiments, the display substrate will be described as an OLED display substrate. Since the number of data lines in the display area and data lead-out lines in the first bezel area is generally large, the drawings only show some of the data lines and data lead-out lines or only show the positions of the first bezel area, and do not limit the number of data lines and data lead-out lines.

[0050] FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 1, the display substrate according to this embodiment may include a display area AA and a bezel region located around the display area AA. The bezel region may include a first bezel region B1 located on one side of the display area AA and a second bezel region B2 located on the remaining side of the display area AA. The first bezel region B1 and the second bezel region B2 may be connected to each other and surround the display area AA. In some examples, the first bezel region B1 may be the bottom bezel of the display substrate, and the second bezel region B2 may be the top bezel, left bezel, and right bezel of the display substrate. However, this embodiment is not limited thereto.

[0051] 1, the display area AA may include a plurality of sub-pixels Px that form a pixel array, and the sub-pixels Px may be configured to display moving images or still images, and the display area AA may be referred to as an active area. In some examples, the display substrate may be a flexible substrate, and therefore, the display substrate may be deformable, such as by curling, bending, folding, or rolling up.

[0052] In some examples, as shown in FIG. 1 , the display area AA may further include a plurality of gate lines (not shown) and a plurality of data lines DL. The gate lines may extend along a first direction X, and the data lines DL may extend along a second direction Y. The first direction X may intersect with the second direction Y, for example, the first direction X may be perpendicular to the second direction Y. The orthogonal projections of the gate lines and the data lines DL on the substrate may intersect to form a plurality of subpixel regions, with one subpixel Px disposed in each subpixel region. The data lines DL may be electrically connected to the subpixels Px and configured to supply data signals to the subpixels Px. The gate lines may be electrically connected to the subpixels Px and configured to supply scanning signals to the subpixels Px.

[0053] In some examples, one pixel unit may include three subpixels, which are red, green, and blue subpixels, respectively. However, this embodiment is not limited thereto. In other examples, one pixel unit may include four subpixels, which are red, green, blue, and white subpixels, respectively.

[0054] In some examples, the shape of the subpixel may be rectangular, rhombic, pentagonal, or hexagonal. When one pixel unit includes three subpixels, the three subpixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, a square arrangement, or the like. When one pixel unit includes four subpixels, the four subpixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement. However, this embodiment is not limited thereto.

[0055] In some examples, at least one subpixel may include a pixel circuit and a light-emitting element. The pixel circuit may be configured to drive the connected light-emitting element. For example, the pixel circuit may be configured to provide a drive current to drive the light-emitting element to emit light. The pixel circuit may include multiple transistors and at least one capacitor, and may have, for example, a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit configurations, T refers to a thin-film transistor, C refers to a capacitor, and the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0056] In some examples, the multiple transistors in the pixel circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit simplifies the process flow, reduces the process difficulty of the display substrate, and improves product yield. In other examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors.

[0057] In some examples, the multiple transistors in the pixel circuit may be low-temperature polysilicon thin-film transistors, oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (oxide). The low-temperature polysilicon thin-film transistor has advantages such as high mobility and fast charging, while the oxide thin-film transistor has advantages such as low leakage current. By integrating the low-temperature polysilicon thin-film transistor and the oxide thin-film transistor on a single display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, the advantages of both can be utilized, enabling low-frequency operation, reducing power consumption, and improving display quality.

[0058] In some examples, the light-emitting element may be an organic light-emitting diode (OLED), and the light-emitting element may emit red light, green light, blue light, white light, or the like under the driving of a corresponding pixel circuit. The light-emitting color of the light-emitting element may be determined as needed. The light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited thereto.

[0059] 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 2, the pixel circuit according to the present embodiment may have an 8T1C structure, i.e., includes first transistor T1 to eighth transistor T8 and a storage capacitor Cst. In this example, the first transistor T1 may be further referred to as a first reset transistor, the second transistor T2 as a threshold compensation transistor, the third transistor T3 as a drive transistor, the fourth transistor T4 as a data write transistor, the fifth transistor T5 as a first light-emitting control transistor, the sixth transistor T6 as a second light-emitting control transistor, and the seventh transistor T7 as a second reset transistor.

[0060] In some examples, the first transistor T1 to the seventh transistor T7 of the pixel circuit may be transistors of a first type, such as P-type transistors, and the eighth transistor T8 may be a transistor of a second type, such as an N-type transistor. However, this embodiment is not limited thereto. For example, the multiple transistors of the first pixel circuit may all be P-type transistors or all be N-type transistors.

[0061] In some examples, the first transistor T1 to the seventh transistor T7 of the pixel circuit may be low-temperature polysilicon thin film transistors, and the eighth transistor T8 of the pixel circuit may be an oxide thin film transistor, but this embodiment is not limited thereto.

[0062] 2, the pixel circuit may be electrically connected to a first scan line GL1, a second scan line GL2, a data line DL, a first power supply line PL1, a second power supply line PL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a first reset control line RST1, and a second reset control line RST2. In some examples, the first power supply line PL1 may be configured to supply a constant first voltage signal VDD to the pixel circuit, and the second power supply line PL2 may be configured to supply a constant second voltage signal VSS to the pixel circuit, where the first voltage signal VDD is greater than the second voltage signal VSS. The first scan line GL1 may be configured to supply a first scan signal SCAN1 to the pixel circuit, the second scan line GL2 may be configured to supply a second scan signal SCAN2 to the pixel circuit, the data line DL may be configured to supply a data signal to the pixel circuit, the light emitting control line EML may be configured to supply a light emitting control signal EM to the pixel circuit, the first reset control line RST1 may be configured to supply a first reset control signal RESET1 to the pixel circuit, and the second reset control line RST2 may be configured to supply a second reset control signal RESET2 to the pixel circuit.

[0063] In some examples, in the pixel circuits in the nth row, the first reset control line RST1 may be connected to the first scan line GL1 of the pixel circuits in the (n-1)th row to input the first scan signal SCAN1(n-1), i.e., the first reset control signal RESET1(n) is the same as the first scan signal SCAN1(n-1). The second reset control line RST2 may be connected to the first reset control line RST1 of the pixel circuits in the (n+1)th row to input the first scan signal SCAN1(n), i.e., the second reset control signal RESET2(n) is the same as the first scan signal SCAN1(n). In this way, the number of signal lines on the display substrate can be reduced, and a narrower frame can be achieved on the display substrate.

[0064] In some examples, as shown in FIG. 2, the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The gate of the second transistor T2 is electrically connected to the first scan line GL1, the first electrode of the second transistor T2 is electrically connected to the fifth node N5, and the second electrode of the second transistor T2 is electrically connected to the third node N3. The gate of the fifth transistor T5 is electrically connected to the emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the fifth node N5. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the second scan line GL2, the first electrode of the eighth transistor T8 is electrically connected to the fifth node N5, and the second electrode of the eighth transistor T8 is electrically connected to the first node N1. A first electrode of the storage capacitor Cst is electrically connected to the first node N1, and a second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.

[0065] In this example, the first node N1 is the connection point between the storage capacitor Cst, the eighth transistor T8, and the third transistor T3, the second node N2 is the connection point between the fifth transistor T5, the fourth transistor T4, and the third transistor T3, the third node N3 is the connection point between the third transistor T3, the second transistor T2, and the sixth transistor T6, the fourth node N4 is the connection point between the sixth transistor T6, the seventh transistor T7, and the light-emitting element EL, and the fifth node N5 is the connection point between the first transistor T1, the second transistor T2, and the eighth transistor T8.

[0066] Figure 3 is an operation timing chart of the pixel circuit shown in Figure 2. In some examples, as shown in Figure 3, the operation process of the pixel circuit within one frame display period may include a first stage S1, a second stage S2, and a third stage S3. In this example, the second reset control signal received by the pixel circuits in one row may be the same as the first scan signal.

[0067] The first stage S1 is called the reset stage. The first reset control signal RESET1 supplied from the first reset control line RST1 is a low-level signal, turning on the first transistor T1. The second scan signal SCAN2 supplied from the second scan line GL2 is a high-level signal, turning on the eighth transistor T8. The first initial signal supplied from the first initial signal line INIT1 is supplied to the fifth node N5 and the first node N1, initializing the first node N1 and clearing the original data voltage of the storage capacitor Cst. The first scan signal SCAN1 supplied from the first scan line GL1 is a high-level signal, and the light-emitting control signal EM supplied from the light-emitting control line EML is a high-level signal, turning off the fourth transistor T4, the second transistor T2, the seventh transistor T7, the fifth transistor T5, and the sixth transistor T6. In this stage, the light-emitting element EL does not emit light.

[0068] The second stage S2 is called a data writing stage or threshold correction stage. The first scanning signal SCAN1 supplied from the first scanning line GL1 is a low-level signal, the second scanning signal SCAN2 supplied from the second scanning line GL2, the first reset control signal RESET1 supplied from the first reset control line RST1, and the light-emitting control signal EM supplied from the light-emitting control line EML are all high-level signals, and the data line DL outputs a data signal. In this stage, the first electrode of the storage capacitor Cst is low, so the third transistor T3 is turned on. The first scan signal SCAN1 is a low-level signal, turning on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. As a result, the data voltage Vdata output from the data line DL is supplied to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, the turned-on second transistor T2, the fifth node N5, and the turned-on eighth transistor T8. The difference between the data voltage Vdata output from the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage of the first electrode (i.e., the first node N1) of the storage capacitor Cst is Vdata-|Vth|, where Vdata is the data voltage output from the data line DL and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, and the second initial signal supplied from the second initial signal line INIT2 is supplied to the fourth node N4 to initialize (reset) the anode of the light-emitting element EL and clear the pre-stored voltage therein, completing the initialization and ensuring that the light-emitting element EL does not emit light. The first reset control signal RESET1 supplied from the first reset control line RST1 is a high-level signal, cutting off the first transistor T1. The light-emitting control signal EM supplied from the light-emitting control line EML is a high-level signal, cutting off the fifth transistor T5 and the sixth transistor T6.

[0069] The third stage S3 is called the light-emitting stage. The light-emitting control signal EM supplied from the light-emitting control line EML is a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The second scan signal SCAN2 supplied from the second scan line GL2 is a low-level signal, turning off the eighth transistor T8. The first scan signal SCAN1 supplied from the first scan line GL1 and the first reset control signal RESET1 supplied from the first reset control line RST1 are high-level signals, turning off the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the first transistor T1. The first voltage signal VDD output from the first power line PL1 supplies a driving voltage to the anode of the light-emitting element EL via the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, thereby driving the light-emitting element EL to emit light.

[0070] During the operation of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its control pole and first pole. Since the voltage at the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is given by the following formula:

[0071] I=K×(Vgs-Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2

[0072] I is the driving current flowing through the third transistor T3, i.e., the driving current that drives the light-emitting element, K is a constant, Vgs is the voltage difference between the control pole and the first pole of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output from the data line DL, and VDD is the first voltage signal output from the first power line PL1.

[0073] From the above equation, it can be seen that the current flowing through the light emitting element is independent of the threshold voltage of the third transistor T3, and therefore the pixel circuit of this embodiment can well compensate for the threshold voltage of the third transistor T3.

[0074] FIG. 4 is a schematic plan view of a display region in at least one embodiment of the present disclosure. FIG. 5 is a schematic cross-sectional view taken along the Q-Q' direction in FIG. 4. In FIG. 4, three subpixels are shown as an example. In this example, the pixel circuit is schematically shown using the 8T1C structure shown in FIG. 2 as an example. In some examples, as shown in FIG. 4, the three subpixels may be arranged in a square-shaped manner in a direction parallel to the display substrate.

[0075] 5 , in a direction perpendicular to the display substrate, the display region may include a substrate 100, and a circuit structure layer 10, a light emitting structure layer 20, and a package structure layer 30, which are sequentially disposed on the substrate 100. The circuit structure layer 10 may include a light shielding (LS) layer 11, a first semiconductor layer 12, a first gate metal layer 13, a second gate metal layer 14, a second semiconductor layer 15, a third gate metal layer 16, a first source-drain metal layer 17, a second source-drain metal layer 18, and a third source-drain metal layer 19, which are sequentially disposed on the substrate 100. A first insulating layer 101 is provided between the light-shielding layer 11 and the first semiconductor layer 12, a second insulating layer 102 is provided between the first semiconductor layer 12 and the first gate metal layer 13, a third insulating layer 103 is provided between the first gate metal layer 13 and the second gate metal layer 14, a fourth insulating layer 104 is provided between the second gate metal layer 14 and the second gate metal layer 15, a fifth insulating layer 105 is provided between the second semiconductor layer 15 and the third gate metal layer 16, a sixth insulating layer 106 is provided between the third gate metal layer 16 and the first source-drain metal layer 17, a seventh insulating layer 107 and an eighth insulating layer 108 are provided between the first source-drain metal layer 17 and the second source-drain metal layer 18, a ninth insulating layer 109 is provided between the second source-drain metal layer 18 and the third source-drain metal layer 19, and a tenth insulating layer 110 is provided between the third source-drain metal layer 19 and the light-emitting structure layer 20. In some examples, the first insulating layer 101 to the seventh insulating layer 107 may be inorganic insulating layers, and the eighth insulating layer 108 to the tenth insulating layer 110 may be organic insulating layers, but this embodiment is not limited thereto.

[0076] 4 and 5, the light-emitting structure layer 20 may include an anode layer 201 (which may include, for example, anodes 201a, 201b, and 201c), a pixel definition layer 204, an organic light-emitting layer (which may include, for example, organic light-emitting layer 202a), and a cathode layer 203, which are sequentially disposed on the substrate 100. The pixel definition layer 204 may have a plurality of pixel openings (for example, pixel openings OP1, OP2, and OP3). The orthogonal projection of pixel opening OP1 on the substrate may be located within the range of the orthogonal projection of anode 201a on the substrate, and pixel opening OP1 may expose a portion of the surface of anode 201a; the orthogonal projection of pixel opening OP2 on the substrate may be located within the range of the orthogonal projection of anode 201b on the substrate, and pixel opening OP2 may expose a portion of the surface of anode 201b; the orthogonal projection of pixel opening OP3 on the substrate may be located within the range of the orthogonal projection of anode 201c on the substrate, and pixel opening OP3 may expose a portion of the surface of anode 201c. An organic light-emitting layer 202a may be located within pixel opening OP1. The cathode layer 203 may be in direct contact with the organic light-emitting layer 202a.

[0077] Fig. 6 is a schematic diagram of the display region after the light-shielding layer of Fig. 4 is formed. In some examples, as shown in Figs. 4 to 6, the light-shielding layer 11 in the display region may include a plurality of light-shielding wirings 111. The plurality of light-shielding wirings 111 may be integrally formed. The plurality of light-shielding wirings 111 may be electrically connected along the first direction X and the second direction Y, and may form a mesh-like connection structure in the display region.

[0078] FIG. 7 is a schematic diagram of the display region after the first semiconductor layer of FIG. 4 is formed. In some examples, as shown in FIGS. 4 to 7, the first semiconductor layer 12 of the display region may include active layers of multiple first-type transistors of multiple pixel circuits (e.g., the active layer T10 of the first transistor T1, the active layer T20 of the second transistor T2, the active layer T30 of the third transistor T3, the active layer T40 of the fourth transistor T4, the active layer T50 of the fifth transistor T5, the active layer T60 of the sixth transistor T6, and the active layer T70 of the seventh transistor T7). In this example, the first transistor T1 to the sixth transistor T6 of the pixel circuit in the current row and the seventh transistor T7 of the pixel circuit in the previous row are shown as examples. In some examples, the active layers T10 of the first transistor T1 to the active layer T70 of the seventh transistor T7 of one pixel circuit may be connected to each other in an integrated structure.

[0079] The material of the first semiconductor layer 12 may include, for example, polysilicon. The active layer of any transistor may include at least one channel region and multiple doped regions. The channel region may be undoped and have semiconducting properties. Multiple doped regions may be located on either side of the channel region and may be doped with impurities and therefore be conductive. The impurities may vary depending on the type of transistor. In some examples, the doped regions of the active layer may be interpreted as the source or drain electrodes of the transistor. Portions of the active layer between transistors may be interpreted as doped wiring and may be used to electrically connect the transistors.

[0080] In some examples, as shown in Figures 6 and 7, the orthogonal projection of the light-shielding wiring 111 on the substrate can cover the orthogonal projection of the channel region of the active layer T30 of the third transistor T3 on the substrate, thereby protecting the third transistor T3 and preventing the external environment from affecting the performance of the third transistor T3.

[0081] Figure 8 is a schematic diagram of the display area after forming the first gate metal layer of Figure 4. In some examples, as shown in Figures 4 to 8, the first gate metal layer 13 of the display area may include gates of a plurality of first-type transistors of a plurality of pixel circuits (e.g., gate T11 of the first transistor T1, gate T21 of the second transistor T2, gate T31 of the third transistor T3, gate T41 of the fourth transistor T4, gate T51 of the fifth transistor T5, gate T61 of the sixth transistor T6, and gate T71 of the seventh transistor T7), first electrodes Cst-1 of storage capacitors Cst of the plurality of pixel circuits, and an emission control line EML.

[0082] In some examples, as shown in FIG. 8 , the first electrode Cst-1 of the storage capacitor Cst and the gate T31 of the third transistor T3 may be integral, e.g., rectangular, e.g., rectangular with rounded corners. The gate T11 of the first transistor T1 of the pixel circuit in the current row may be integral with the gate T71 of the seventh transistor T7 of the pixel circuit in the previous row. The gate T21 of the second transistor T2 of the pixel circuit in the current column may be integral with the gate T41 of the fourth transistor T4 of the pixel circuit in the adjacent column. The gate T51 of the fifth transistor T5, the gate T61 of the sixth transistor T6, and the emission control line EML may be integral. However, this embodiment is not limited to this.

[0083] 9 is a schematic diagram of the display region after forming the second gate metal layer of FIG. 4. In some examples, as shown in FIGS. 4 to 9, the second gate metal layer 14 of the display region may include second electrodes Cst-2 of storage capacitors Cst of a plurality of pixel circuits, a first initial signal line INIT1, a second initial signal line INIT2, and a scan connecting line 121. The first initial signal line INIT1, the second initial signal line INIT2, and the scan connecting line 121 may all extend along the first direction X. In the second direction Y, the second initial signal line INIT2 may be located between the first initial signal line INIT1 and the scan connecting line 121.

[0084] 10 is a schematic diagram of the display region after forming the second semiconductor layer of FIG. 4. In some examples, as shown in FIGS. 4 to 10, the second semiconductor layer 15 of the display region may include active layers of second-type transistors of multiple pixel circuits (e.g., the active layer T80 of the eighth transistor T8). The active layer T80 of the eighth transistor T8 may extend along the second direction Y. In some examples, the material of the second semiconductor layer 15 may include a metal oxide such as indium gallium zinc oxide (IGZO).

[0085] FIG. 11 is a schematic diagram of the display area after forming the third gate metal layer of FIG. 4. In some examples, as shown in FIGS. 4 to 11, the third gate metal layer 16 in the display area may include a gate of a second-type transistor (e.g., the gate T81 of the eighth transistor T8) and a second scan line GL2. The second scan line GL2 may extend along the first direction X. The gate T81 of the eighth transistor T8 may be integral with the second scan line GL2. In some examples, the gate T81 of the eighth transistor T8 may be a top gate, and the region of the scan connection line 121 that overlaps with the active layer T80 of the eighth transistor T8 may be a bottom gate of the eighth transistor T8. The scan connection line 121 may further be configured to shield the channel region of the active layer T80 of the eighth transistor T8 from light, thereby ensuring the performance of the eighth transistor T8.

[0086] 12 is a schematic diagram of the display area after the sixth insulating layer of FIG. 4 is formed. In some examples, as shown in FIGS. 4 to 12, a plurality of vias may be formed in the sixth insulating layer 106 of the display area, including, for example, a plurality of first-type vias (e.g., including the first via V1 to the sixth via V6) exposing the surface of the first semiconductor layer 12, a plurality of second-type vias (e.g., including the seventh via V7 and the eighth via V8) exposing the surface of the second semiconductor layer 15, a plurality of third-type vias (e.g., including the ninth via V9 to the eleventh via V11) exposing the surface of the first gate metal layer 13, and a plurality of fourth-type vias (e.g., including the twelfth via V12 to the sixteenth via V16) exposing the surface of the second gate metal layer 14. The sixth insulating layer 106 to the second insulating layer 102 within the first-type vias may be removed. The sixth insulating layer 106 to the fifth insulating layer 105 in the second type via may be removed, the sixth insulating layer 106 to the third insulating layer 103 in the third type via may be removed, and the sixth insulating layer 106 to the fourth insulating layer 104 in the fourth type via may be removed.

[0087] FIG. 13 is a schematic diagram of the display region after forming the first source-drain metal layer of FIG. 4. In some examples, as shown in FIGS. 4 to 13, the first source-drain metal layer 17 of the display region may include a plurality of connection electrodes (e.g., the first connection electrode 161 to the seventh connection electrode 167 and the first anode connection electrode 141), a first scan line GL1, a first reset control line RST1, and a first power supply connection line 131. In this example, the first reset control line RST1 electrically connected to the pixel circuits of the current row and the second reset control line RST2 electrically connected to the pixel circuits of the previous row may be integral with each other. The first scan line GL1, the first reset control line RST1, and the first power supply connection line 131 may all extend along the first direction X. In the second direction Y, the first scan line GL1 may be located between the first reset control line RST1 and the first power supply connection line 131. The orthogonal projection of the first reset control line RST1 on the substrate may be located between the orthogonal projections of the first initial signal line INIT1 and the second initial signal line INIT2 on the substrate.

[0088] In some examples, as shown in FIGS. 4 to 13 , the first connection electrode 161 may be electrically connected to one doping region of the active layer T10 of the first transistor T1 through the first via V1 and may further be electrically connected to the first initial signal line INIT1 through the twelfth via V12. The second connection electrode 162 may be electrically connected to one doping region of the active layer T70 of the seventh transistor T7 through the sixth via V6 and may further be electrically connected to the second initial signal line INIT2 through the thirteenth via V13. The third connection electrode 163 may be electrically connected to one doping region of the active layer T40 of the fourth transistor T4 through the third via V3. The fourth connection electrode 164 may be electrically connected to one doping region of the active layer T20 of the second transistor T2 through the second via V2 and may further be electrically connected to one doping region of the active layer T80 of the eighth transistor T8 through the seventh via V7. The fifth connection electrode 165 may be electrically connected to another doping region of the active layer T80 of the eighth transistor T8 through an eighth via V8, and may further be electrically connected to the gate T31 of the third transistor T3 through an eleventh via V11. The sixth connection electrode 166 may be electrically connected to the first initial signal line INIT1 through a fifteenth via V15. The seventh connection electrode 167 may be electrically connected to the second initial signal line INIT2 through a sixteenth via V16. The first anode connection electrode 141 may be electrically connected to one doping region of the active layer T60 of the sixth transistor T6 through a fifth via V5. The first reset control line RST1 may be electrically connected to the gate T11 of the first transistor T1 through a ninth via V9. The first scan line GL1 may be electrically connected to the gate T41 of the fourth transistor T4 through a tenth via V10. The first power supply connecting line 131 may be electrically connected to the second electrode Cst-2 of the storage capacitor Cst through a fourteenth via V14, and may further be electrically connected to one doping region of the active layer T50 of the fifth transistor T5 through a fourth via V4. The first power supply connecting line 131 may be configured to supply a first voltage signal.

[0089] FIG. 14 is a schematic diagram of the display area after the eighth insulating layer of FIG. 4 is formed. In some examples, as shown in FIGS. 4 to 14, the eighth insulating layer 108 in the display area may have multiple vias, such as vias V21 to V25. The eighth insulating layer 108 and the seventh insulating layer 107 in the via V21 may be removed to expose the surface of the third connecting electrode 163 located on the first source-drain metal layer 17. The eighth insulating layer 108 and the seventh insulating layer 107 in the via V22 may be removed to expose the surface of the first power supply connecting line 131 located on the first source-drain metal layer 17. The eighth insulating layer 108 and the seventh insulating layer 107 in the via V23 may be removed to expose the surface of the first anode connecting electrode 141 located on the first source-drain metal layer 17. The eighth insulating layer 108 and the seventh insulating layer 107 in the 24th via V24 may be removed to expose the surface of the seventh connection electrode 167 located on the first source-drain metal layer 17. The eighth insulating layer 108 and the seventh insulating layer 107 in the 25th via V25 may be removed to expose the surface of the sixth connection electrode 166 located on the first source-drain metal layer 17.

[0090] FIG. 15 is a schematic diagram of the display region after the second source-drain metal layer of FIG. 4 is formed. FIG. 16 is a schematic diagram of the second source-drain metal layer of FIG. 15. In some examples, as shown in FIGS. 4 to 16, the second source-drain metal layer 18 of the display region may include a plurality of data lines (e.g., including data lines DLa and DLb), a second power supply connecting line 132, and a plurality of connecting electrodes (e.g., including an eighth connecting electrode 168, a ninth connecting electrode 169, and a second anode connecting electrode 142). The plurality of data lines and the second power supply connecting line 132 may all extend along the second direction Y. The data line DLa may be electrically connected to one column of pixel circuits located in odd-numbered rows, and the data line DLb may be electrically connected to one column of pixel circuits located in even-numbered rows. Alternatively, the data line DLa may be electrically connected to one column of pixel circuits located in even-numbered rows, and the data line DLb may be electrically connected to one column of pixel circuits located in odd-numbered rows. The second power supply connecting line 132 may be located between the data lines DLa and DLb adjacent to each other in the first direction X, and the data lines DLa and DLb are disposed between two adjacent second power supply connecting lines 132. In this example, the pixel circuits in the odd and even rows are connected to different data lines, thereby reducing the load on each data line to some extent.

[0091] In some examples, as shown in FIGS. 4 to 16 , the eighth connection electrode 168 may be electrically connected to the sixth connection electrode 166 through the twenty-fifth via V25. The ninth connection electrode 169 may be electrically connected to the seventh connection electrode 167 through the twenty-fourth via V24. The data line DLa may be electrically connected to the third connection electrode 163 through the twenty-first via V21, thereby achieving electrical connection to the first electrode of the fourth transistor T4 of the pixel circuit. The second anode connection electrode 142 may be electrically connected to the first anode connection electrode 141 through the twenty-third via V23. The second power supply connection line 132 may be electrically connected to the first power supply connection line 131 through the twenty-second via V22. The data line DLb may be electrically connected to the first electrode of the fourth transistor T4 of the pixel circuit in an adjacent row.

[0092] FIG. 17 is a schematic diagram of the display area after the ninth insulating layer of FIG. 4 is formed. In some examples, as shown in FIGS. 4 to 17, the ninth insulating layer 109 of the display area may have multiple vias, such as vias V31 to V34. The ninth insulating layer 109 in via V31 may be removed to expose the surface of the second power supply connecting line 132 located on the second source-drain metal layer 18. The ninth insulating layer 109 in via V32 may be removed to expose the surface of the second anode connecting electrode 142 located on the second source-drain metal layer 18. The ninth insulating layer 109 in via V33 may be removed to expose the surface of the eighth connecting electrode 168 located on the second source-drain metal layer 18. The ninth insulating layer 109 in via V34 may be removed to expose the surface of the ninth connecting electrode 169 located on the second source-drain metal layer 18.

[0093] FIG. 18 is a schematic diagram of the display region after the third source-drain metal layer of FIG. 4 is formed. FIG. 19 is a schematic diagram of the third source-drain metal layer of FIG. 18. In some examples, as shown in FIGS. 4 to 19, the third source-drain metal layer 19 of the display region may include a third power supply connecting line 133, a fourth power supply connecting line 134, a first initial connection line 151, a second initial connection line 152, and a third anode connecting electrode (e.g., third anode connecting electrodes 143a, 143b, and 143c). The third power supply connecting line 133, the fourth power supply connecting line 134, the first initial connection line 151, and the second initial connection line 152 may all extend along the second direction Y. The first initial connection line 151 and the second initial connection line 152 may be arranged in the first direction X with one third power supply connecting line 133 spaced apart. The fourth power supply connection line 134 may be located between two third power supply connection lines 133 adjacent to each other in the first direction X.

[0094] In some examples, as shown in FIGS. 4 to 19 , the first initial connection line 151 is electrically connected to the eighth connection electrode 168 through the via hole V33, thereby achieving electrical connection to the first initial signal line INIT1 through the eighth connection electrode 168 and the sixth connection electrode 166. The first initial connection line 151 and the first initial signal line INIT1 form a mesh transmission structure of the first initial signal in the display area, thereby improving the transmission stability of the first initial signal. The second initial connection line 152 is electrically connected to the ninth connection electrode 169 through the via hole V34, thereby achieving electrical connection to the second initial signal line INIT2 through the ninth connection electrode 169 and the seventh connection electrode 167. The second initial connection line 152 and the second initial signal line INIT2 form a mesh transmission structure of the second initial signal in the display area, thereby improving the transmission stability of the second initial signal. The third power supply connecting line 133 may be electrically connected to the second power supply connecting line 132 through at least two vias V31. In this example, the first power supply connecting line 131, the second power supply connecting line 132, and the third power supply connecting line 133 may be electrically connected and configured to transmit a first voltage signal VDD. The first power supply connecting line 131, the second power supply connecting line 132, and the third power supply connecting line 133 form a mesh transmission structure for the first voltage signal VDD in the display area, thereby reducing voltage drops of the first voltage signal at different positions and improving the transmission stability of the first voltage signal. The fourth power supply connecting line 134 may be configured to transmit a second voltage signal VSS. The third anode connecting electrodes 143a, 143b, and 143c may each be electrically connected to one second anode connecting electrode 142 through one via V32. The third anode connecting electrode 143b may extend along the second direction Y.

[0095] FIG. 20 is a schematic diagram of the display region after the tenth insulating layer of FIG. 4 is formed. In some examples, as shown in FIGS. 4 to 20, the tenth insulating layer 110 in the display region may have multiple vias, such as vias V41 to V43. The tenth insulating layer 110 in via V41 may be removed to expose the surface of the third anode-connecting electrode 143a located on the third source-drain metal layer 19. The tenth insulating layer 110 in via V42 may be removed to expose the surface of the third anode-connecting electrode 143b located on the third source-drain metal layer 19. The tenth insulating layer 110 in via V43 may be removed to expose the surface of the third anode-connecting electrode 143c located on the third source-drain metal layer 19.

[0096] FIG. 21 is a schematic diagram of the display region after forming the anode layer of FIG. 4. In some examples, as shown in FIGS. 4 to 21, the anode layer 201 of the display region may include multiple anodes, such as anodes 201a, 201b, and 201c. The anode 201a may be electrically connected to the third anode-connecting electrode 143a through a via V41. The anode 201b may be electrically connected to the third anode-connecting electrode 143b through a via V42, and the anode 201c may be electrically connected to the third anode-connecting electrode 143c through a via V43.

[0097] The bezel area of ​​the display substrate of this embodiment will be described below by taking an example.

[0098] In some examples, as shown in FIG. 1, the first bezel region B1 may include a first fan-out region B11, a folding region B12, a second fan-out region B13, a first circuit region B14, a third fan-out region B15, a first signal access region B16, and a second signal access region B17 arranged sequentially along a second direction Y away from the display region AA.

[0099] FIG. 22 is a schematic diagram of local wiring in the first bezel region in at least one embodiment of the present disclosure. In some examples, as shown in FIGS. 1 and 22, a first fanout region B11 may be connected to the display area AA. The first fanout region B11 may include a plurality of first data fanout lines 51 and a plurality of second data fanout lines 52. The plurality of first data fanout lines 51 may be electrically connected to the plurality of second data fanout lines 52 in a one-to-one correspondence. The plurality of first data fanout lines 51 may be electrically connected to the plurality of data lines DL in the display area AA, and the first data fanout lines 51 may be configured to be connected to the data lines DL in the display area AA in a fanout wiring manner. For example, the plurality of first data fanout lines 51 may be electrically connected to the plurality of data lines DL in a one-to-one correspondence. A first compensation unit 41 and a first electrostatic prevention circuit 44 may also be installed in the first fanout region B11. For example, the first data fan-out line 51 may have one end electrically connected to the first compensation unit 41 and the first electrostatic protection circuit 44, and the other end electrically connected to the second data fan-out line 52. The first data fan-out line 51 and the second data fan-out line 52 may extend along a direction away from the display area AA. The second data fan-out line 52 may be located on a side of the first data fan-out line 51 away from the display area AA. In a direction perpendicular to the display substrate, the second data fan-out line 52 may be located on a side of the first data fan-out line 51 closer to the substrate.

[0100] In some examples, as shown in FIGS. 1 and 22, the folding region B12 may be connected between the first fan-out region B11 and the second fan-out region B13. The folding region B12 may include a composite insulating layer having a groove and may be configured to fold the second fan-out region B13 to the second signal access region B17 toward the back surface of the display region AA. The folding region B12 may include a plurality of data folding lines 53. The plurality of data folding lines 53 may be electrically connected to the plurality of second data fan-out lines 52 in one-to-one correspondence. The second fan-out region B13 may be connected between the folding region B12 and the first circuit region B14. The second fan-out region B13 may include at least a plurality of third data fan-out lines 54 drawn out in a fan-out wiring manner. The plurality of third data fan-out lines 54 may be electrically connected to the plurality of data folding lines 53 in one-to-one correspondence. The first circuit area B14 may include a second anti-static circuit and a test circuit. The second anti-static circuit may be configured to remove static electricity and prevent electrostatic damage to the display substrate. The test circuit may be configured to supply a data test signal to the data lines DL of the display area AA. The third fanout area B15 may be connected between the first circuit area B14 and the first signal access area B16. The third fanout area B15 may include at least a plurality of fourth data fanout lines 55 drawn out in a fanout wiring manner. An integrated circuit (IC) may be installed in the first signal access area B16. The second signal access area B17 may include a plurality of bind pads, which may be configured to be bound and connected to an external flexible printed circuit (FPC). Connection wiring may be installed between the first signal access area B16 and the second signal access area B17.

[0101] 22, a ground connection line 61 may be further installed in the first bezel region B1, and the ground connection line 61 may be electrically connected to a ground end in the second signal access region B17. The ground connection line 61 may further be electrically connected to the first compensation unit 41 in the first fan-out region B11.

[0102] In some examples, as shown in FIG. 1 , the second bezel region B2 may include a second circuit region, a power line region, a crack dam region, and a cutting region sequentially arranged along the first direction X away from the display region AA. The second circuit region may be connected to the display region AA and may include at least a gate drive circuit, which may be electrically connected to the first scan line, the second scan line, and the emission control line connected to the pixel circuits in the display region AA. The power line region may be connected to the second circuit region and may include at least a bezel power lead, which extends along a direction parallel to the edge of the display region and is connected to a cathode in the display region. The crack dam region may be connected to the power line region and include at least a plurality of cracks arranged in the composite insulating layer. The cutting region may be connected to the crack dam region and include at least a cutting groove arranged in the composite insulating layer, and the cutting groove is configured to be cut along each of the cutting grooves by a cutting device after all film layers of the display substrate have been prepared.

[0103] In some examples, as shown in FIG. 1 , the first fan-out region B11 in the first bezel region B1 and the power line region in the second bezel region B2 may be provided with a first isolation dam DA1 and a second isolation dam DA2. The first isolation dam DA1 and the second isolation dam DA2 may extend parallel to the edge of the display area AA to form a ring-shaped structure surrounding the display area AA. The edge of the display area is the edge of the display area AA closer to the first bezel region B1 or the second bezel region B2. The second isolation dam DA2 may be located on the side of the first isolation dam DA1 that is farther from the display area AA. The first isolation dam DA1 and the second isolation dam DA2 may be configured to block water vapor from entering the display area AA from the periphery of the display area AA.

[0104] FIG. 23 is an equivalent circuit diagram of a first compensation unit in at least one embodiment of the present disclosure. In some examples, as shown in FIG. 23, the first compensation unit may include first compensation resistors R1, R2, R3, and R4 and first compensation capacitors C1, C2, and C3. The first compensation resistors R1 to R4 may be electrically connected in series. The first electrode of the first compensation capacitor C1 may be electrically connected between the first compensation resistors R1 and R2, and the second electrode may be grounded. The first electrode of the second compensation capacitor C2 may be electrically connected between the first compensation resistors R2 and R3, and the second electrode may be grounded. The first electrode of the third compensation capacitor C3 may be electrically connected between the first compensation capacitors R3 and R4, and the second electrode may be grounded. The first compensation unit of this embodiment employs a three-stage resistor-capacitor model, which is advantageous for approximating expected results and achieving a better compensation effect. This embodiment does not limit the number of first compensation resistors and first compensation capacitors included in the first compensation unit. In some other examples, the first compensation unit may employ an N-stage model, where N may be greater than three.

[0105] In this embodiment, the first compensation unit may have a first connection end that is the first end of the first compensation resistor R1 and a second connection end that is the second end of the first compensation resistor R4. In some examples, the first compensation unit may be located in the first fanout region, and the first connection end of the first compensation unit may be electrically connected to the data line and the second connection end of the first compensation unit may be electrically connected to the first data fanout line. However, this embodiment is not limited to this. In other examples, the first compensation unit may be located in the second fanout region or the third fanout region. For example, the third data fanout line in the second fanout region may be divided into two sub-data fanout lines, and the first compensation unit may be connected between the two sub-data fanout lines. For example, the first connection end of the first compensation unit may be electrically connected to one sub-data fanout line and the second connection end of the first compensation unit may be electrically connected to the other sub-data fanout line.

[0106] 23, the first compensation capacitors C1, C2, and C3 may have the same capacitance value, for example, all C / 3. The first compensation resistors R1 and R4 may have the same resistance value, for example, all R / 6, and the first compensation resistors R2 and R3 may have the same resistance value, for example, all R / 3. R may be a preset resistance parameter required for compensation, and C may be a preset capacitance parameter required for compensation.

[0107] FIG. 24 is a partial schematic diagram of a first bezel region in at least one embodiment of the present disclosure. In some examples, as shown in FIG. 24, the first compensation unit 41 may be located in the first fanout region B11. The data line DL in the display area AA may extend to the first fanout region B11 and be electrically connected to the first data connection line 50 in the first fanout region B11. One end of the first data connection line 50 may be electrically connected to the data line DL, and the other end of the first data connection line 50 may be electrically connected to the first electrostatic discharge prevention circuit 44 and the first compensation unit 41, and then electrically connected to the first data fanout line 51 via the first compensation unit 41. The first data fanout line 51 is electrically connected to the second data fanout line 52. The connection position between the first data fanout line 51 and the second data fanout line 52 (e.g., the black dot position in FIG. 24) may be located on the side of the first isolation dam DA1 closer to the display area AA.

[0108] 25 is an equivalent circuit diagram of a first electrostatic discharge (ESD) circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 25, the first ESD protection circuit may include a first release transistor ST1 to a fourth release transistor ST4. A first electrode of the first release transistor ST1 is electrically connected to the fourth power supply line VGL, a gate and a second electrode of the first release transistor ST1 are electrically connected to a first electrode of the second release transistor ST2, and a gate and a second electrode of the second release transistor ST2 are electrically connected to a signal input terminal L0 of the first ESD protection circuit. A first electrode of the third release transistor ST3 is electrically connected to the signal input terminal L0 of the first ESD protection circuit, a gate and a second electrode of the third release transistor ST3 are electrically connected to a first electrode of the fourth release transistor ST4, and a gate and a second electrode of the fourth release transistor ST4 are electrically connected to the third power supply line VGH. The third voltage signal provided by the third power supply line VGH may be greater than the fourth voltage signal provided by the fourth power supply line VGL. The signal input terminal L0 is electrically connected to a line transmitting a data signal (e.g., a first data connection line) to prevent damage caused by discharge breakdown due to static electricity accumulation in the line transmitting the data signal and to discharge the static electricity accumulated in the line to protect the line. However, this embodiment is not limited thereto. In another example, the first electrostatic discharge protection circuit may include two release transistors, one pole of each release transistor connected to its gate, thereby forming an equivalent diode connection, while the line to be protected is connected between the two "diodes," and the other ends of the two "diodes" are connected to the third power supply line VGH and the fourth power supply line VGL, respectively. As a result, if a momentary high voltage (e.g., 100V) occurs on the signal line due to accumulated positive charge, one of the "diodes" turns on and releases the positive charge in the wiring, while if a momentary low voltage (e.g., -100V) occurs on the wiring due to accumulated negative charge, another of the "diodes" turns on and releases the negative charge in the signal line.

[0109] FIG. 26 is a local enlarged view of region D1 in FIG. 24. FIG. 27 is a schematic diagram of the light-shielding layer in FIG. 26. FIG. 28 is a local schematic diagram of the first bezel region in FIG. 26 after the first semiconductor layer has been formed. FIG. 29 is a local schematic diagram of the first bezel region in FIG. 26 after the first gate metal layer has been formed. FIG. 30 is a local schematic diagram of the first bezel region in FIG. 26 after the second gate metal layer has been formed. FIG. 31 is a local schematic diagram of the first bezel region in FIG. 26 after the sixth insulating layer has been formed. FIG. 32 is a local schematic diagram of the first bezel region in FIG. 26 after the first source-drain metal layer has been formed. FIG. 33 is a local schematic diagram of the first bezel region in FIG. 26 after the eighth insulating layer has been formed. FIG. 34 is a local schematic diagram of the first bezel region in FIG. 26 after the second source-drain metal layer has been formed. FIG. 35 is a local schematic diagram of the first bezel region in FIG. 26 after the ninth insulating layer has been formed. 26 is a partial schematic view of the first bezel area after the third source-drain metal layer is formed. FIGS. 26 to 35 show eight data lines and eight first data connecting lines as examples. The first compensation resistor R1 may be located on the side of the first static electricity prevention circuit 44 away from the display area AA.

[0110] 26 and 27 , the light-shielding layer in the first fan-out region may include bezel light-shielding wiring 112. The bezel light-shielding wiring 112 may extend along the first direction X. A plurality of light-shielding wirings 111 in the display region may extend along the second direction Y to the first fan-out region B11 and be electrically connected to the bezel light-shielding wiring 112. For example, the light-shielding wiring 111 may be integral with the bezel light-shielding wiring 112.

[0111] 26 to 28, the first semiconductor layer of the first fan-out region may include active layers of multiple release transistors of multiple first electrostatic discharge prevention circuits (for example, the active layer ST10 of the first release transistor ST1, the active layer ST20 of the second release transistor ST2, the active layer ST30 of the third release transistor ST3, and the active layer ST40 of the fourth release transistor ST4). The active layers of the four release transistors of one first electrostatic discharge prevention circuit may have an integrated structure.

[0112] 26 to 29, the first gate metal layer in the first fan-out region may include gates of multiple release transistors of multiple first electrostatic discharge prevention circuits (e.g., gate ST11 of first release transistor ST1, gate ST21 of second release transistor ST2, gate ST31 of third release transistor ST3, and gate ST41 of fourth release transistor ST4), a third power supply line VGH, a fourth power supply line VGL, and a resistive wiring 411a of a first compensation resistor R1. The third power supply line VGH and the fourth power supply line VGL may both extend along the first direction X. As shown in FIG. 30, the second gate metal layer may include a resistive wiring 411b of another first compensation resistor R1.

[0113] In some examples, as shown in FIG. 31 , multiple vias may be opened in the sixth insulating layer in the first fan-out region, including vias V51 to V64, for example. The sixth to second insulating layers in vias V51 to V55 may be removed to expose the surface of the first semiconductor layer. The sixth to third insulating layers in vias V56 to V62 may be removed to expose the surface of the first gate metal layer. The sixth to fourth insulating layers in vias V63 may be removed to expose the surface of the second gate metal layer. The sixth to first insulating layers in vias V64 may be removed to expose the surface of the bezel light-shielding wiring 112 located in the light-shielding layer.

[0114] 26 to 32, the first source-drain metal layer in the first fan-out region may include a plurality of first data connection lines 50 and a plurality of connection electrodes (e.g., eleventh connection electrode 171 to fifteenth connection electrode 175). One first data connection line 50 may be electrically connected to one doping region of the active layer ST20 of the second release transistor ST2 through a via V53, may be further electrically connected to the gate ST21 of the second release transistor ST2 through a via V58, and may be further electrically connected to the resistive wiring 411b of the first compensation resistor R1 through two vias V63 arranged vertically. Another first data connection line 50 may be electrically connected to another first electrostatic discharge prevention circuit, and may be further electrically connected to the resistive wiring 411a of the other first compensation resistor R1 through two vias V62 arranged vertically. The eleventh connecting electrode 171 may be electrically connected to the fourth power line VGL through two vertically arranged vias V56, and may further be electrically connected to one doping region of the active layer ST10 of the first release transistor ST1 through a via V51. The twelfth connecting electrode 172 may be electrically connected to the gate ST11 of the first release transistor ST1 through a via V57, and may further be electrically connected to another doping region of the active layer ST10 of the first release transistor ST1 through a via V52. The thirteenth connecting electrode 173 may be electrically connected to the gate ST31 of the third release transistor ST3 through a via V59, and may further be electrically connected to one doping region of the active layer ST30 of the third release transistor ST3 through a via V54. The fourteenth connection electrode 174 may be electrically connected to the gate ST41 of the fourth release transistor ST4 through the sixtieth via V60, may be further electrically connected to one doping region of the active layer ST40 of the fourth release transistor ST4 through the fifty-fifth via V55, and may be further electrically connected to the third power supply line VGH through two sixty-first vias V61 arranged vertically side by side. The fifteenth connection electrode 175 may be electrically connected to the bezel light-shielding wiring 112 through the sixty-fourth via V64.

[0115] In the present disclosure, being arranged in a vertical line may also represent being arranged sequentially along the second direction Y.

[0116] 26 to 33, a plurality of vias may be provided in the eighth insulating layer of the first fan-out region, including, for example, a 65th via V65 and a 66th via V66. The eighth insulating layer and the seventh insulating layer in the 65th via V65 may be removed to expose the surface of the first data connecting line 50. The eighth insulating layer and the seventh insulating layer in the 66th via V66 may be removed to expose the surface of the 15th connecting electrode 175.

[0117] 26 to 34, the second source-drain metal layer in the first fan-out region may include a first bezel initial line 153, a second bezel initial line 154, a sixteenth connecting electrode 176, and data lines (e.g., data lines DLa and DLb) extending to the first fan-out region. The first bezel initial line 153 and the second bezel initial line 154 may both extend along the first direction X. The second bezel initial line 154 may be located on a side of the first bezel initial line 153 that is farther from the display area. The orthographic projections of the first bezel initial line 153 and the second bezel initial line 154 on the substrate may be located on a side closer to the display area of ​​the orthographic projection of the bezel light-shielding wiring 112 on the substrate. The data line DLa extending to the first fan-out region may be electrically connected to one first data connecting line 50 through two 65th vias V65 arranged vertically side by side, and the data line DLb extending to the first fan-out region may be electrically connected to another first data connecting line 50 through two other 65th vias V65 arranged vertically side by side. The 16th connecting electrode 176 may be electrically connected to the 15th connecting electrode 175 through two 66th vias V66 arranged vertically side by side.

[0118] In some examples, as shown in FIGS. 26 to 35 , the ninth insulating layer in the first fan-out region may have a plurality of vias formed therein, including, for example, a 67th via V67 to a 69th via V69. The ninth insulating layer in the 67th via V67 may be removed to expose the surface of the first bezel initial line 153. The ninth insulating layer in the 68th via V68 may be removed to expose the surface of the second bezel initial line 154. The ninth insulating layer in the 69th via V69 may be removed to expose the surface of the sixteenth connecting electrode 176.

[0119] 26 , the third source-drain metal layer in the first fan-out region may include at least a first initial connection line 151, a second initial connection line 152, a third power supply connection line 133, a fourth power supply connection line 134, and a first bezel power supply line 135. The first initial connection line 151, the second initial connection line 152, the third power supply connection line 133, and the fourth power supply connection line 134 may extend from the display region to the first fan-out region along the second direction Y. The first initial connection line 151 may be electrically connected to the first bezel initial line 153 through two 67th vias V67 arranged vertically next to each other. The second initial connection line 152 may be electrically connected to the second bezel initial line 154 through two 68th vias V68 arranged vertically next to each other. At least one of the plurality of third power connection lines 133 may be electrically connected to the sixteenth connection electrode 176 through the sixteenth via V69 and electrically connected to the bezel light-shielding wiring 122 through the sixteenth connection electrode 176 and the fifteenth connection electrode 175, so that the bezel light-shielding wiring 122 and the light-shielding wiring 111 can transmit a first voltage signal. The first bezel power line 135 may extend along the first direction X. An overlapping portion may exist between the orthogonal projection of the first bezel power line 135 on the substrate and the orthogonal projection of the plurality of first electrostatic prevention circuits on the substrate. The first bezel power line 135 may be integral with the plurality of third power connection lines 133 and configured to transmit a first voltage signal. The fourth power connection line 134 may be configured to transmit a second voltage signal. For example, a tenth insulating layer and an anode layer may be sequentially disposed on the side of the third source-drain metal layer away from the substrate, and the fourth power connection line 134 may be electrically connected to a power connection electrode located on the anode layer through a via formed in the tenth insulating layer and electrically connected to the second power line through the power connection electrode. For example, the second power line may be located on the third source-drain metal layer and on the side of the first bezel power line away from the display area.

[0120] FIG. 36 is a partial schematic diagram of a first compensation resistor in at least one embodiment of the present disclosure. FIG. 36 illustrates multiple first compensation resistors R1. In some examples, as shown in FIG. 36, the first compensation resistor may include a resistance wiring. In the first fan-out region, multiple first compensation resistors electrically connected to multiple first data connection lines may be sequentially arranged along a first direction X. The resistance wiring of adjacent first compensation resistors arranged along the first direction X may be located on different conductive layers, and their orthogonal projections on the substrate may not overlap. For example, one first compensation resistor R1 may include a resistance wiring 411a located on a first gate metal layer, and an adjacent first compensation resistor R1 may include a resistance wiring 411b located on a second gate metal layer. In this example, arranging the resistance wiring of adjacent first compensation resistors on the first gate metal layer and the second gate metal layer can save space, and the first gate metal layer and the second gate metal layer may be made of a metal material with high resistivity, which is advantageous for increasing the compensation resistance.

[0121] 36, the orthogonal projection of the resistive wiring 411a or 411b of the first compensating resistor R1 on the substrate may be a serpentine wiring, which is advantageous for increasing the compensation resistance. For example, the resistive wiring 411b of the first compensating resistor R1 may include a plurality of first line segments 4111 and a plurality of second line segments 4112. The extension directions of the plurality of first line segments 4111 may be substantially parallel, for example, all extending along the first direction X. The extension directions of the plurality of second line segments 4112 may be substantially parallel, for example, all extending along the second direction Y. The first line segments 4111 and the second line segments 4112 may be connected in series. Two adjacent first line segments 4111 may be connected via one second line segment 4112, and the two second line segments 4112 connected to both ends of one first line segment 4111 are located on both sides of the first line segment 4111 in the first direction X and on both sides of the first line segment 4111 in the second direction Y. The first line segment 4111 and the second line segment 4112 may be straight line segments. In other examples, the second line segment 4112 may be an arc line segment, or the first line segment 4111 may be an arc line segment, or both the first line segment 4111 and the second line segment 4112 may be arc line segments. However, this embodiment is not limited thereto. In other examples, the resistive wiring may be straight wiring. In this example, the length and shape of the resistive wiring of the first compensating resistor may be determined according to the magnitude of the resistance that needs to be compensated.

[0122] FIG. 37 is a local enlarged view of region D2 in FIG. 24. FIG. 37 is a diagram showing the connection positions of the first compensation resistor R1 and the first compensation capacitor C1. FIG. 38 is a local schematic view of the first fan-out region after the first gate metal layer of FIG. 37 has been formed. FIG. 39 is a local schematic view of the first fan-out region after the second gate metal layer of FIG. 37 has been formed. FIG. 40 is a local schematic view of the first fan-out region after the third gate metal layer of FIG. 37 has been formed. FIG. 41 is a local schematic view of the first fan-out region after the sixth insulating layer of FIG. 37 has been formed. FIG. 37 is a local schematic view of the first fan-out region after the first source-drain metal layer has been formed.

[0123] In some examples, as shown in FIG. 37, a plurality of first compensation capacitors C1 electrically connected to each of a plurality of first compensation resistors R1 may be sequentially arranged along the first direction X. As shown in FIG. 38, the first gate metal layer in the first fan-out region may further include a first plate 412a of the first compensation capacitor C1. When the resistive wiring of the first compensation resistor is located in the first gate metal layer, the first compensation resistor may be integral with the first plate of the first compensation capacitor to which it is electrically connected. For example, the resistive wiring 411a of the first compensation resistor R1 may be integral with the first plate 412a of the first compensation capacitor C1 to which it is electrically connected.

[0124] 39, the second gate metal layer in the first fan-out region may further include a second plate 412b of the first compensation capacitor C1. An orthogonal projection of the second plate 412b of the first compensation capacitor C1 on the substrate may overlap with an orthogonal projection of the first plate 412a on the substrate. In some examples, the second plates 412b of the multiple first compensation capacitors C1 may be integral, and a first opening 4120 may be formed at a connection position between adjacent second plates 412b. The orthogonal projection of the first opening 4120 on the substrate may not overlap with the orthogonal projection of the first plate 412a on the substrate. By forming the first opening 4120 in the integrally molded second plate, defects that occur during the manufacturing of large-area metal can be avoided.

[0125] 40, the third gate metal layer in the first fan-out region may include the third plate 412c of the first compensation capacitor C1. An orthogonal projection of the third plate 412c of the first compensation capacitor C1 on the substrate may overlap with an orthogonal projection of the second plate 412b and the first plate 412a on the substrate. An orthogonal projection of the third plate 412c on the substrate may not overlap with an orthogonal projection of the first opening 4120 on the substrate.

[0126] In some examples, as shown in FIG. 41 , the sixth insulating layer in the first fan-out region may further include multiple vias, such as vias V71 to V75. The sixth to third insulating layers in via V71 may be removed to expose the surface of the independently located first electrode plate 412a, and the sixth to third insulating layers in via V74 may be removed to expose the surface of the first electrode plate 412a integrated with the resistive wiring 411a of the first compensation resistor R1. The sixth to fourth insulating layers in via V72 may be removed to expose the surface of the resistive wiring 411b of the first compensation resistor R1. The sixth insulating layer in vias V73 and V75 may be removed to expose the surface of the third electrode plate 412c of the first compensation capacitor C1.

[0127] 37 , the first source-drain metal layer in the first fan-out region may further include a seventeenth connecting electrode 177 and an eighteenth connecting electrode 178. The seventeenth connecting electrode 177 may be electrically connected to the resistive wiring 411b of the first compensation resistor R1 located on the second gate metal layer through a via V72, to the first plate 412a of the separately placed first compensation capacitor C1 through a via V71, and to the third plate 412c through a via V73. The eighteenth connecting electrode 178 may be electrically connected to the resistive wiring 411a of the first compensation resistor R1 and the first plate 412a of the first compensation capacitor C1 through a via V74, and to the third plate 412c of the first compensation capacitor C1 through a via V75. In this example, the first plate 412a of one first compensation capacitor C1 may be electrically connected to the third plate 412c, thereby forming a first electrode of the first compensation capacitor C1, the first electrode being electrically connected to the first compensation resistor R1, and the second plate 412b of one first compensation capacitor C1 may be grounded as a second electrode. For example, the second plate 412b of the first compensation capacitor C1 may be electrically connected to the ground end of the second signal access area (second signal access area B17 shown in FIG. 22) via a ground connection line (ground connection line 61 shown in FIG. 22).

[0128] In this example, the three plates of the first compensation capacitor are arranged on the first to third gate metal layers, and the insulating layers between adjacent metal layers among the first to third gate metal layers are thin, ensuring the performance of the compensation capacitor. Furthermore, the second plates of the multiple second compensation capacitors are integrally formed, and may form a mesh structure, simplifying the manufacturing process and minimizing the space required.

[0129] 42 is a local enlarged view of region D3 in FIG. 24. FIG. 42 is a diagram showing the connection position between first compensation resistor R4 and first data fan-out line 51. FIG. 43 is a local schematic view of the first fan-out region after forming the second gate metal layer in FIG. 42. FIG. 44 is a local schematic view of the first fan-out region after forming the first source-drain metal layer in FIG. 42. FIG. 42 is a schematic view of the first fan-out region after forming the second source-drain metal layer.

[0130] In some examples, as shown in FIGS. 42 to 44 , the plurality of first data fan-out lines may include a plurality of first data fan-out lines of a first type 51 a and a plurality of first data fan-out lines of a second type 51 b. The first data fan-out lines of the first type 51 a and the first data fan-out lines of the second type 51 b may be spaced apart along the first direction X. The first data fan-out lines of the first type 51 a may be located closer to the substrate than the first data fan-out lines of the second type 51 b. For example, the first data fan-out lines of the first type 51 a may be located in a first source-drain metal layer, and the first data fan-out lines of the second type 51 b may be located in a second source-drain metal layer. The orthogonal projection of the first data fan-out lines of the first type 51 a on the substrate and the orthogonal projection of the first data fan-out lines of the second type 51 b on the substrate may not overlap.

[0131] In some examples, as shown in FIGS. 42 to 44 , the first compensation resistor R4 may include a resistive wiring 414a or 414b. The resistive wiring 414a may be located in the first gate metal layer, and the resistive wiring 414b may be located in the second gate metal layer. The resistive wiring 414a of one first compensation resistor R4 may be electrically connected to the first data fanout line 51a of the first type through two 82nd vias V82 arranged vertically next to each other. The resistive wiring 414b of the other first compensation resistor R4 may be electrically connected to the 19th connection electrode 179 through two 81st vias V81 arranged vertically next to each other. The 19th connection electrode 179 may be in the same layer as the first data fanout line 51a of the first type. The 19th connection electrode 179 may be electrically connected to the first data fanout line 51b of the second type through the 83rd via V83.

[0132] In this embodiment, the configuration of the first compensation resistors R2 and R3 may refer to the configuration of the first compensation resistors R1 and R4, the configuration of the first compensation capacitors C2 and C3 may refer to the configuration of the first compensation capacitor C1, and the connection relationship between the first compensation resistors and the first compensation capacitor may refer to the connection relationship between the first compensation resistor R1 and the first compensation capacitor C1, but this embodiment will not repeat this description.

[0133] 45 is a local enlarged view of region D4 in FIG. 24. FIG. 45 shows a schematic diagram of the connection between the first data fan-out line 51 and the second data fan-out line 52 in the first fan-out region. FIG. 46 is a local cross-sectional schematic view along the U-U' direction in FIG. 45. FIG. 47 is a local schematic view of the first fan-out region after the second gate metal layer in FIG. 45 has been formed. FIG. 48 is a local schematic view of the first fan-out region after the first source-drain metal layer in FIG. 45 has been formed.

[0134] In some examples, as shown in FIGS. 45 to 47, the plurality of first data fanout lines in the first fanout region are electrically connected to the plurality of second data fanout lines in one-to-one correspondence. The plurality of first data fanout lines may include a plurality of first data fanout lines 51a of a first type and a plurality of first data fanout lines 51b of a second type. The plurality of second data fanout lines may include a plurality of second data fanout lines 52a of a first type and a plurality of second data fanout lines 52b of a second type. The second data fanout lines 52a of the first type and the second data fanout lines 52b of the second type may be spaced apart from each other along the first direction X. The second data fanout lines 52a of the first type may be located closer to the substrate than the second data fanout lines 52b of the second type, and the orthogonal projection of the second data fanout lines 52a of the first type on the substrate may not overlap with the orthogonal projection of the second data fanout lines 52b of the second type on the substrate. For example, the second data fanout lines 52a of the first type may be located in a first gate metal layer, and the second data fanout lines 52b of the second type may be located in a second gate metal layer. In other examples, the second data fanout lines may be located in a third gate metal layer.

[0135] In some examples, as shown in FIGS. 45 to 47, a first data fanout line 51a of a first type located in the first source-drain metal layer may be electrically connected to a second data fanout line 52a of a first type located in the first gate metal layer through three vertically arranged vias V84. A twentieth connection electrode 180 located in the first source-drain metal layer may be electrically connected to a second data fanout line 52b of a second type located in the second gate metal layer through two vertically arranged vias V85. A first data fanout line 51b of a second type located in the second source-drain metal layer is electrically connected to the twentieth connection electrode 180 through a via V86, thereby achieving an electrical connection between the second data fanout line 52b of a second type and the first data fanout line 51b of a second type. This connection scheme in this example can avoid the need for excessively deep vias. However, this example is not limited to this. In some other examples, a first data fanout line of a first type may be electrically connected to a second data fanout line of a second type (e.g., via a connecting electrode), and a first data fanout line of a second type may be electrically connected to a second data fanout line of the first type (e.g., via a connecting electrode).

[0136] In some examples, the resistivity of the material of the first data fan-out line may be lower than the resistivity of the material of the second data fan-out line, thereby reducing the load on the data line. For example, the first data fan-out line may adopt a titanium (Ti) / aluminum (Al) / Ti stack structure, and the material of the second data fan-out line may be molybdenum (Mo).

[0137] In some examples, as shown in Figures 45 to 47, the connection position of the first data fan-out line 51a of the first type and the second data fan-out line 52a of the first type may be located on the side closer to the display area of ​​the first isolation dam DA1. The connection position of the first data fan-out line 51b of the second type and the second data fan-out line 52b may be located on the side closer to the display area of ​​the first isolation dam DA1. There may be an overlap between the orthogonal projection of the first data fan-out line 51a of the first type and the first data fan-out line 51b of the second type on the substrate and the orthogonal projection of the first isolation dam DA1 on the substrate, but there may be no overlap between the orthogonal projection of the second isolation dam DA2 on the substrate.

[0138] In some examples, as shown in FIG. 46 , the first isolation dam DA1 may include a first dam base DA11, a third dam base DA12, and a fifth dam base DA13, which are sequentially stacked. The second isolation dam DA2 may include a second dam base DA21, a fourth dam base DA22, and a sixth dam base DA23, which are sequentially stacked. The first dam base DA11 and the second dam base DA21 may be disposed on a ninth insulating layer 109, and the first to eighth insulating layers 101 to 108 may be disposed on the side of the ninth insulating layer 109 closer to the substrate 100. The first dam base DA11 and the second dam base DA21 may have the same layer structure as the tenth insulating layer. The third dam base DA12 and the fourth dam base DA22 may have the same layer structure as the pixel definition layer. The fifth dam base DA13 and the sixth dam base DA23 may have the same layer structure as the isolation pillar layer. In some examples, the heights of the first isolation dam DA1 and the second isolation dam DA2 may be approximately the same. In another example, the heights of the first isolation dam DA1 and the second isolation dam DA2 may be different, for example, the height of the second isolation dam DA2 may be higher than the height of the first isolation dam DA1. For example, the eighth insulating layer 108 or the ninth insulating layer 109 on the side of the first isolation dam DA1 closer to the substrate may be removed. However, this embodiment is not limited thereto.

[0139] In this example, the first data fan-out line is disposed in the first source-drain metal layer and the second source-drain metal layer, and the resistivity of the metal material of the first source-drain metal layer and the second source-drain metal layer is lower than that of the metal material of the first gate metal layer and the second gate metal layer, thereby reducing the resistivity of the first data fan-out line and the load on the data line. In this example, by transferring the first data fan-out line and the second data fan-out line on the side of the first isolation dam closer to the display area, it is possible to prevent water vapor from being introduced into the display area through the first source-drain metal layer and the second source-drain metal layer and corroding the light-emitting elements.

[0140] 24, the plurality of second data fan-out lines 52 may be electrically connected to a plurality of data folding lines 53 in the folding region B12. The plurality of data folding lines 53 may be located in a second source-drain metal layer. The plurality of data folding lines 53 may be electrically connected to a plurality of third data fan-out lines 54 in the second fan-out region B13. The plurality of third data fan-out lines 54 may include a plurality of third data fan-out lines of a first type and a plurality of third data fan-out lines of a second type, where the third data fan-out lines of the first type and the third data fan-out lines of the second type may be spaced apart, and the orthogonal projections of the third data fan-out lines of the first type on the substrate and the third data fan-out lines of the second type on the substrate may not overlap. For example, the third data fanout lines of the first type may be located in the first source-drain metal layer, and the third data fanout lines of the second type may be located in the second source-drain metal layer, thereby reducing the resistivity of the third data fanout lines and the load on the data lines. In other examples, the plurality of fourth data fanout lines 55 located within the third data fanout line B15 may include a plurality of fourth data fanout lines of the first type and a plurality of fourth data fanout lines of the second type, and the fourth data fanout lines of the first type and the fourth data fanout lines of the second type may be spaced apart, and the orthogonal projections of the fourth data fanout lines of the first type on the substrate and the fourth data fanout lines of the second type on the substrate may not overlap. For example, the fourth data fanout lines of the first type may be located in the first source-drain metal layer, and the fourth data fanout lines of the second type may be located in the second source-drain metal layer, thereby reducing the resistivity of the fourth data fanout lines and the load on the data lines. However, this embodiment is not limited to this.

[0141] In some examples, the data lead-out lines in the first bezel region may include a first data connection line 50, a first data fan-out line 51, a second data fan-out line 52, a data folding line 53, a third data fan-out line 54, and a fourth data fan-out line 55 electrically connected in sequence.

[0142] 49 is a partial schematic diagram of a second bezel region in at least one embodiment of the present disclosure. In some examples, as shown in FIG. 49 , the display substrate may include a plurality of first signal lines located in the second bezel region B2 and extending along the first direction X. For example, the plurality of first signal lines may include a third bezel initial line 155, a fourth bezel initial line 156, a first bezel wiring 601, a second bezel wiring 602, a third bezel wiring 603, a fourth bezel wiring 604, and a fifth bezel wiring 605. At least one first signal line may be connected to a second compensation unit 42, and the second compensation unit 42 may be configured to compensate for at least one of a resistance and a capacitance of the connected first signal line.

[0143] In some examples, as shown in FIG. 49 , the third bezel initial line 155 may be electrically connected to the first initial signal line INIT1 in the display area AA and configured to transmit a first initial signal. The fourth bezel initial line 156 may be electrically connected to the second initial signal line INIT2 in the display area AA and configured to transmit a second initial signal. The first bezel wiring 601 may be electrically connected to the first reset control line RST1 in the display area AA and configured to transmit a first reset control signal. The second bezel wiring 602 may be electrically connected to the first scan line GL1 in the display area AA and configured to transmit a first scan signal. The third bezel wiring 603 may be electrically connected to the scan connection line 121 in the display area AA and configured to supply a signal to the bottom gate of the eighth transistor of the pixel circuit. The fourth bezel wiring 604 may be electrically connected to the second scan line GL2 in the display area AA and configured to transmit a second scan signal. The fifth bezel wiring 605 may be electrically connected to the emission control line EML in the display area AA and configured to transmit an emission control signal. The first bezel wiring 601, the second bezel wiring 602, the fourth bezel wiring 604, and the fifth bezel wiring 605 may further be electrically connected to corresponding gate drive circuits. For example, the gate drive circuit in the second bezel area B2 may include a first scan drive circuit, a second scan drive circuit, and an emission control drive circuit. The first bezel wiring 601 and the second bezel wiring 602 may be electrically connected to an output terminal of the first scan drive circuit and configured to receive a first scan signal. The fourth bezel wiring 604 may be electrically connected to an output terminal of the second scan drive circuit and configured to receive a second scan signal. The fifth bezel wiring 605 may be electrically connected to an output terminal of the emission control drive circuit and configured to receive an emission control signal.

[0144] FIG. 50 is an exemplary schematic diagram of a second compensation unit in at least one embodiment of the present disclosure. FIG. 51 is a schematic diagram of the first gate metal layer of FIG. 50. FIG. 52 is a schematic diagram of the second gate metal layer of FIG. 50. In some examples, as shown in FIGS. 49 to 52, the second compensation unit 42 electrically connected to the third bezel initial line 155 may include a second compensation resistor 421a. The second compensation resistor 421a may be located in the second gate metal layer and include a linear resistive wiring. The second compensation resistor 421a may extend until electrically connected to the first initial signal line INIT1 in the display area, or may be electrically connected to the first initial signal line INIT1 via a connecting electrode.

[0145] 49 to 52, one end of the first bezel wiring 601 may be electrically connected to an output terminal of a gate driving circuit (e.g., a first scan driving circuit) and the other end may be electrically connected to the second compensation unit 42. The second compensation unit 42 electrically connected to the first bezel wiring 601 may include a second compensation resistor 421b and a second compensation capacitor 422a. The second compensation resistor 421b may be located in the first gate metal layer and include a linear resistive wiring. The second compensation capacitor 422a may include a first electrode 4221a and a second electrode 4222a. The first electrode 4221a may be located in the first gate metal layer or may be integral with the second compensation resistor 421b, and the second electrode 4222a may be located in the second gate metal layer. The first electrode 4221a of the second compensation capacitor 422a may extend to be electrically connected to the first reset control line RST1 in the display area, or may be electrically connected to the first reset control line RST1 via a connection electrode.

[0146] 49 to 52, the second compensation unit 42 electrically connected to the fourth bezel initial line 156 may include a second compensation resistor 421c. The second compensation resistor 421c may include a linear resistive wiring located in the second gate metal layer. The second compensation resistor 421c may extend to be electrically connected to the second initial signal line INIT2 in the display area, or may be electrically connected to the second initial signal line INIT2 via a connecting electrode.

[0147] 49 to 52, one end of the second bezel wiring 602 may be electrically connected to an output terminal of a gate driving circuit (e.g., a first scan driving circuit) and the other end may be electrically connected to the second compensation unit 42. The second compensation unit 42 electrically connected to the second bezel wiring 602 may include a second compensation resistor 421d and a second compensation capacitor 422b. The second compensation resistor 421d may be located in the first gate metal layer and include a linear resistive wiring. The second compensation capacitor 422b may include a first electrode 4221b and a second electrode 4222b. The first electrode 4221b may be located in the first gate metal layer or may be integral with the second compensation resistor 421d, and the second electrode 4222b may be located in the second gate metal layer. The first electrode 4221b of the second compensation capacitor 422b may extend to be electrically connected to the first scan line GL1 of the display area, or may be electrically connected to the first scan line GL1 via a connection electrode.

[0148] In some examples, as shown in FIGS. 49 to 52, the second compensation unit 42 electrically connected to the third bezel wiring 603 may include a second compensation resistor 421e and a second compensation capacitor 422c. The second compensation resistor 421e may be located in the second gate metal layer and include a snake-shaped resistive wiring. The second compensation capacitor 422b may include a first electrode 4221c and a second electrode 4222c. The first electrode 4221c may be located in the first gate metal layer and electrically connected to the second compensation resistor 421e via a connecting electrode 181, and the second electrode 4222c may be located in the second gate metal layer. The first electrode 4221c of the second compensation capacitor 422c may extend to be electrically connected to the scan connecting line 121 in the display area or may be electrically connected to the scan connecting line 121 via a connecting electrode.

[0149] In some examples, as shown in FIGS. 49 to 52, one end of the fourth bezel wiring 604 may be electrically connected to an output terminal of a gate driving circuit (e.g., a second scan driving circuit) and the other end may be electrically connected to the second compensation unit 42. The second compensation unit 42 electrically connected to the second bezel wiring 604 may include a second compensation resistor 421f and a second compensation capacitor 422d. The second compensation resistor 421f may be located in the first gate metal layer and include a snake-shaped resistance wiring. The second compensation capacitor 422d may include a first electrode 4221d and a second electrode 4222d, where the first electrode 4221d may be located in the first gate metal layer or may be integral with the second compensation resistor 421f, and the second electrode 4222d may be located in the second gate metal layer. The first electrode 4221d of the second compensation capacitor 422d may extend to be electrically connected to the second scan line GL2 of the display area, or may be electrically connected to the second scan line GL2 via a connection electrode.

[0150] In some examples, as shown in FIGS. 49 to 52, the fifth bezel wiring 605 may have one end electrically connected to an output terminal of a gate driving circuit (e.g., a light-emitting control driving circuit) and the other end electrically connected to the second compensation unit 42. The second compensation unit 42 electrically connected to the fifth bezel wiring 605 may include a second compensation resistor 421g and a second compensation capacitor 422e. The second compensation resistor 421g may be located in the second gate metal layer and include a snake-shaped resistive wiring. The second compensation capacitor 422e may include a first electrode 4221e and a second electrode 4222e, where the first electrode 4221e may be located in the first gate metal layer and may be electrically connected to the second compensation resistor 421g via the 22nd connection electrode 182, and the second electrode 4222e may be located in the second gate metal layer. The first electrode 4221e of the second compensation capacitor 422e may extend until it is electrically connected to the light-emitting control line EML in the display area, or may be electrically connected to the light-emitting control line EML via a connection electrode.

[0151] The 21st connecting electrode 181 and the 22nd connecting electrode 182 may be located on the first source-drain metal layer. The second electrodes of the second compensation capacitors 422a, 422b, 422c, 422d, and 422e may be integrally formed. The second electrodes of the second compensation capacitors may be electrically connected to a ground connection line (ground connection line 61 as shown in FIG. 22) so as to be electrically connected to the ground end of the second signal access area (second signal access area B17 as shown in FIG. 22). The second compensation capacitor of this example may have a two-electrode plate structure. However, this example is not limited thereto.

[0152] In some examples, the corresponding electrically connected second compensation unit may be installed according to the resistance and capacitance of the first signal line. For example, the first bezel initial wiring and the second bezel initial wiring may be connected only to the second compensation resistor for resistance compensation, and the resistance that needs to be compensated for by the first bezel wiring 601 and the second bezel wiring 602 may be small, while the resistance that needs to be compensated for by the third bezel wiring 603, the fourth bezel wiring 604, and the fifth bezel wiring 605 may be large.

[0153] The display substrate of this example is provided with a second compensation unit to reduce the voltage drop (IR drop) of the signal transmitted by the first signal line in the display area, thereby ensuring display uniformity, and enabling signal verification of a large display substrate on a small display substrate.

[0154] FIG. 53 is a connection schematic diagram of a third compensation unit in at least one embodiment of the present disclosure. In some examples, as shown in FIG. 53, a gate driving circuit and a clock signal line (e.g., including a first clock signal line CLK1 and a second clock signal line CLK2) may be installed in the second bezel area B2. One gate driving circuit may include multiple cascaded driving sub-circuits 70. The first clock signal line CLK1 and the second clock signal line CLK2 may supply first and second clock signals to the multiple driving sub-circuits 70. The first clock signal line CLK1 may be electrically connected to one third compensation unit 43, and the second clock signal line CLK2 may be electrically connected to one third compensation unit 43. The third compensation units 43 may be located in the first bezel area B1, for example, in the lower left and lower right corners of the first bezel area B1. The third compensation units 43 may include a third compensation resistor and a third compensation capacitor. The third compensation unit 43 may be configured to provide at least one of resistance compensation and capacitance compensation to the electrically connected clock signal line. The structure and connection manner of the third compensation resistor and the third compensation capacitor may refer to the structure and connection manner of the first compensation resistor and the first compensation capacitor in the previous embodiment, or may refer to the structure and connection manner of the second compensation resistor and the second compensation capacitor in the previous embodiment, and therefore will not be described again here.

[0155] The structure of the display substrate will be described below using an example of a manufacturing process for the display substrate. In this disclosure, the "patterning process" includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metal, inorganic, or transparent conductive materials, and organic material coating, mask exposure, and development for organic materials. The deposition process may be one or more of sputtering, evaporation, or chemical vapor deposition; the coating process may be one or more of spraying, spin coating, or inkjet printing; and the etching process may be one or more of dry etching or wet etching; these processes are not limited to these processes. A "thin film" refers to a thin film formed by depositing, coating, or otherwise depositing a material on a base substrate. If the "thin film" does not require a patterning process during the entire manufacturing process, it can also be referred to as a "layer." If the "thin film" requires a patterning process during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern." In the present disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously by the same patterning process, or that the surfaces of A and B closest to the substrate are substantially the same distance from the substrate, or that the surfaces of A and B closest to the substrate are in direct contact with the same film layer. The "thickness" of a film layer refers to the size of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of the present disclosure, "the orthogonal projection of B is located within the range of the orthogonal projection of A" or "the orthogonal projection of A includes the orthogonal projection of B" means that the boundary of the orthogonal projection of B is within the boundary of the orthogonal projection of A, or that the boundary of the orthogonal projection of A overlaps the boundary of the orthogonal projection of B.

[0156] In some exemplary embodiments, the manufacturing process for the display substrate may include the following operations.

[0157] (1) Provide a substrate. In some examples, the substrate 100 may be a rigid substrate such as a glass substrate, or may be a flexible substrate. This embodiment is not limited thereto.

[0158] (2) Forming a light-shielding layer. In some examples, a first conductive thin film is deposited on the substrate 100, and the first conductive thin film is patterned by a patterning process to form a light-shielding layer. As shown in FIGS. 6 and 27, the light-shielding layer may include light-shielding wiring 111 located in the display area and bezel light-shielding wiring 112 located in the first bezel area.

[0159] (3) Forming a first semiconductor layer. In some examples, a first insulating thin film and a first semiconductor thin film are sequentially deposited on the substrate 100 on which the structure is formed, and the first semiconductor thin film is patterned using a patterning process to form a first insulating layer 101 and a first semiconductor layer disposed on the first insulating layer 101. As shown in FIGS. 7 and 28, the first semiconductor layer may include active layers of first-type transistors of multiple pixel circuits located in the display area and active layers of multiple release transistors of a first electrostatic prevention circuit located in the first bezel area. In some examples, the material of the first semiconductor layer 12 may be polysilicon.

[0160] (4) Forming a first gate metal layer. In some examples, a second insulating thin film and a second conductive thin film are sequentially deposited on the substrate 100 on which the structure is formed, and the second conductive thin film is patterned by a patterning process to form a second insulating layer 102 and a first gate metal layer disposed on the second insulating layer 102. As shown in FIGS. 8 , 29 , 38 , 47 , and 51 , the first gate metal layer may include gates of first-type transistors of a plurality of pixel circuits located in the display area, a first electrode of a storage capacitor, an emission control line EML, a third power supply line VGH, a fourth power supply line VGL, gates of a plurality of release transistors of a first electrostatic discharge prevention circuit located in the first bezel area, resistive wiring of a plurality of first compensation resistors, first electrodes of a plurality of first compensation capacitors, a plurality of second first-type data fan-out lines, and resistive wiring of a second compensation resistor and a first electrode of a second compensation capacitor located in the second bezel area.

[0161] (5) Forming a second gate metal layer. In some examples, a third insulating thin film and a third conductive thin film are sequentially deposited on the substrate 100 on which the structure is formed, and the third conductive thin film is patterned by a patterning process to form a third insulating layer 103 and a second gate metal layer disposed on the third insulating layer 103. As shown in FIGS. 9, 30, 39, 47, and 52, the second gate metal layer may include the second electrode of the storage capacitor of the pixel circuit located in the display area, the scan connecting line 121, the first initial signal line INIT1, the second initial signal line INIT2, the resistive wiring of the first compensation resistor located in the first bezel area, the second plate of the first compensation capacitor, and the resistive wiring of the second compensation resistor and the second electrode of the second compensation capacitor located in the second bezel area.

[0162] (6) Forming a second semiconductor layer. In some examples, a fourth insulating thin film and a second semiconductor thin film are sequentially deposited on the substrate 100 on which the structure is formed, and the second semiconductor thin film is patterned by a patterning process to form a fourth insulating layer 104 and a second semiconductor layer disposed on the fourth insulating layer 104. As shown in FIG. 10 , the second semiconductor layer may include an active layer of a second type transistor of a pixel circuit located in the display area. In some examples, the material of the second semiconductor layer may be IGZO.

[0163] (7) Forming a third gate metal layer. In some examples, a fifth insulating thin film and a fourth conductive thin film are sequentially deposited on the substrate 100 on which the structure is formed, and the fourth conductive thin film is patterned by a patterning process to form a fifth insulating layer 105 and a third gate metal layer disposed on the fifth insulating layer 105. In some examples, as shown in FIGS. 11 and 40, the third gate metal layer may include the gate of the second type transistor of the pixel circuit located in the display area and the third plate of the second compensation capacitor located in the first bezel area.

[0164] (8) Forming a sixth insulating layer: In some examples, a sixth insulating thin film is deposited on the substrate 100 on which the structure is formed, and the sixth insulating thin film is patterned by a patterning process to form the sixth insulating layer 106. A first mask (abbreviated as Etch Bending A MASK, EBA MASK) is used to etch some of the insulating layers (e.g., the first insulating layer to the sixth insulating layer) in the bending region of the first bezel region.

[0165] (9) Forming a first source-drain metal layer. In some examples, a fifth conductive thin film is deposited on the substrate 100 on which the structure is formed, and the fifth conductive thin film is patterned by a patterning process to form a first source-drain metal layer. In some examples, as shown in FIGS. 13, 32, and 44, the first source-drain metal layer may include a plurality of connection electrodes located in the display area, a first power supply connection line 131, a first scan line GL1, and a plurality of first data connection lines 50 and a plurality of connection electrodes located in the first bezel area.

[0166] (10) A second source-drain metal layer is formed. In some examples, a seventh insulating thin film is deposited on the substrate 100 on which the structure is formed, and the seventh insulating thin film is patterned by a patterning process to form a seventh insulating layer 107. A second mask (Etch Bending B MASK, or EBB MASK) is used to etch a portion of the insulating layer (e.g., the seventh insulating layer) in the bending region of the first bezel region. Next, an eighth insulating thin film is applied, and the eighth insulating thin film is patterned by a patterning process to form an eighth insulating layer 108. Next, a sixth conductive thin film is deposited, and the sixth conductive thin film is patterned by a patterning process to form a second source-drain metal layer. In some examples, as shown in FIGS. 15 and 34, the second source-drain metal layer may include at least a plurality of data lines, second power supply connecting lines, and second anode connecting electrodes located in the display region, as well as first bezel initial lines 153 and second bezel initial lines 154 located in the first bezel region.

[0167] (11) Forming a third source-drain metal layer. In some examples, a ninth insulating thin film is applied to the substrate on which the structure is formed, and the ninth insulating thin film is patterned by a patterning process to form a ninth insulating layer 109. Next, a seventh conductive thin film is deposited, and the seventh conductive thin film is patterned by a patterning process to form a third source-drain metal layer. In some examples, as shown in FIGS. 18 and 26, the third source-drain metal layer may include at least a first initial connection line 151, a second initial connection line 152, a third power supply connection line 133, a fourth power supply connection line 134 located in the display area, and a fifth power supply connection line 135 located in the first bezel area.

[0168] (12) Forming a tenth insulating layer: In some examples, a tenth insulating thin film is applied to the substrate on which the structure is formed, and the tenth insulating thin film is patterned by a patterning process to form the tenth insulating layer 110.

[0169] (13) Forming a light-emitting structure layer and a package structure layer.

[0170] In some examples, an anode thin film is deposited on the substrate 100 on which the structure is formed, and the anode thin film is patterned using a patterning process to form an anode layer. A pixel defining thin film is applied to the substrate 100 on which the pattern is formed, and a pixel defining layer is formed using a mask, exposure, and development process. A plurality of pixel openings are opened in the pixel defining layer in the display area. An organic light-emitting layer is formed in the pixel opening, and the organic light-emitting layer is connected to the anode. Next, a cathode thin film is deposited, and the cathode thin film is patterned using a patterning process to form a cathode layer, which may be electrically connected to the organic light-emitting layer. Next, a package structure layer is formed on the cathode layer, and the package structure layer may include a laminated structure of inorganic material / organic material / inorganic material.

[0171] In some exemplary embodiments, the light-shielding layer, the first gate metal layer, the second gate metal layer, the third gate metal layer, the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer may be made of metal materials such as one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They may have a single-layer structure or a multi-layer composite structure such as Mo / Cu / Mo. The first insulating layer 101 to the seventh insulating layer 107 may be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be made of a single layer, multiple layers, or a composite layer. The eighth insulating layer 108 to the tenth insulating layer 110 may also be called planar layers and may be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel defining layer may be made of an organic material such as polyimide, acrylic, or polyethylene terephthalate, the anode layer may be made of a reflective material such as metal, and the cathode layer may be made of a transparent conductive material, but this embodiment is not limited thereto.

[0172] The structure of the display substrate and its manufacturing process in this embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure can be changed or the composition process can be increased or decreased according to actual needs. The manufacturing process in this exemplary embodiment can be realized using current mature manufacturing equipment, has good compatibility with existing manufacturing processes, is simple to realize and easy to implement, has high production efficiency, low production costs, and a high yield rate.

[0173] In some examples, a first compensation unit is installed to compensate for the resistance and capacitance of the data line, a second compensation unit is installed to compensate for the resistance and capacitance of the first signal line, and a third compensation unit is installed to compensate for the resistance and capacitance of the clock signal line. This allows the performance of a large display substrate to be verified on a small display substrate, thereby reducing verification costs. Furthermore, by compensating for the resistance and capacitance of the data line, the first signal line, and the clock signal line, IR drop of the signal in the display area can be reduced and display uniformity can be ensured. Furthermore, the placement spaces of the first compensation unit, second compensation unit, and third compensation unit in this example can be determined according to the maximum compensation amount required for the corresponding signal line, thereby achieving space optimization.

[0174] FIG. 54 is another schematic diagram of the first bezel region in at least one embodiment of the present disclosure. In some examples, as shown in FIG. 54, the first bezel region may include a first fanout region B11, a folding region B12, a second fanout region B13, four first circuit regions B14, a third fanout region B15, four first signal access regions B16, and two second signal access regions B17, which are arranged sequentially along the side away from the display region AA. The four first circuit regions B14 may be arranged sequentially along the first direction X, the four first signal access regions B16 may be arranged sequentially along the first direction X, and the two second signal access regions B17 may be arranged sequentially along the first direction X. One first signal access region B17 may correspond to two first signal access regions B16 and two first circuit regions B14. The wiring in the first bezel region may be the same as that shown in the previous embodiment, and the first compensation unit may be located in the first fan-out region or the second fan-out region. This embodiment is not limited thereto. The remaining configuration of the display substrate in this embodiment can be referenced to the description of the previous embodiment, and therefore will not be described here.

[0175] FIG. 55 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in FIG. 55, the embodiments provide a display device 91 including a display substrate 910. The display substrate 910 may be a display substrate according to any of the embodiments described above. The display substrate 910 may be an OLED display substrate. The display device 91 may be any product or component having a display function, such as an OLED display device, a mobile phone, a tablet, a television, a display, a laptop, a digital photo frame, or a navigation system. However, the embodiments are not limited thereto.

[0176] The drawings in this disclosure only relate to the structures of the present disclosure, and other structures may refer to general designs. Unless conflicting, the embodiments of the present disclosure, i.e., the features in the embodiments, may be combined with each other to obtain new embodiments. It should be understood that those skilled in the art may modify or equivalently replace the technical solutions of the present disclosure without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of the present disclosure. [Explanation of symbols]

[0177] 41 First Compensation Unit 100 boards AA display area B1 First bezel area DL data line Px subpixel

Claims

1. a display substrate, comprising: a substrate, a plurality of data lines, a plurality of sub-pixels, a plurality of data lead-out lines, and at least one first compensation unit; the substrate includes a display area and a first bezel area located on one side of the display area; the plurality of data lines are located in the display area; the plurality of sub-pixels are located in the display area and electrically connected to the plurality of data lines; the plurality of data lead-out lines are located in the first bezel area and electrically connected to the plurality of data lines in the display area; the at least one first compensation unit is located in the first bezel area; At least one data lead-out line among the plurality of data lead-out lines is electrically connected to the first compensation unit, and the first compensation unit is configured to compensate for at least one of a resistance and a capacitance of a data line electrically connected to the at least one data lead-out line.

2. The first compensation unit includes at least one of at least one first compensation resistor and at least one first compensation capacitor; 2. The display substrate of claim 1, wherein the first compensation resistor is configured to compensate for a resistance of a data line electrically connected to the at least one data lead-out line, and the first compensation capacitor is configured to compensate for a capacitance of a data line electrically connected to the at least one data lead-out line.

3. The display substrate of claim 2 , wherein the first compensation unit includes at least one first compensation resistor, the at least one first compensation resistor being electrically connected in series to the data lead-out line.

4. 4. The display substrate of claim 2, wherein the first compensation resistor includes a resistive wiring, the resistive wiring is located in a first gate metal layer or a second gate metal layer, and the first gate metal layer and the second gate metal layer are located in different layers.

5. The display substrate according to claim 4 , wherein the resistive wiring of the first compensation resistor is projected onto the substrate as a meandering wiring.

6. The display substrate of any one of claims 2 to 5, wherein the first compensation unit further includes at least one first compensation capacitor, the at least one first compensation capacitor including a first electrode and a second electrode, the first electrode of the at least one first compensation capacitor electrically connected to the at least one first compensation resistor, and the second electrode of the at least one first compensation capacitor electrically connected to a ground terminal.

7. 7. The display substrate of claim 6, wherein the at least one first compensation capacitor includes a first plate, a second plate, and a third plate sequentially arranged along a direction away from the substrate, the first plate, the second plate, and the third plate overlap when projected orthogonally onto the substrate, the first plate being electrically connected to the third plate to form the first electrode, and the second plate being the second electrode.

8. 8. The display substrate of claim 7, wherein the second plate of the at least one first compensation capacitor is a monolithic structure.

9. 9. The display substrate of claim 7, wherein the first electrode plate is located on a first gate metal layer, the second electrode plate is located on a second gate metal layer, the third electrode plate is located on a third gate metal layer, and the first gate metal layer, the second gate metal layer, and the third gate metal layer are located on different layers.

10. the first bezel region includes a first fan-out region located on one side of the display region, and at least one isolation dam is installed in the first fan-out region; At least one of the plurality of data lead-out lines includes a first data fan-out line and a second data fan-out line located in the first fan-out region and electrically connected to each other, the second data fan-out line being located on a side of the first data fan-out line away from the display region, and the second data fan-out line being located on a side of the first data fan-out line closer to the substrate; A display substrate described in any one of claims 1 to 9, wherein the connection position of the first data fanout line and the second data fanout line is located on the side of the isolation dam closer to the display area, and the orthogonal projection of the connection position on the substrate and the orthogonal projection of the isolation dam on the substrate do not overlap.

11. The display substrate of claim 10 , wherein a resistivity of a material of the first data fan-out lines is lower than a resistivity of a material of the second data fan-out lines.

12. the first fan-out region includes a plurality of first data fan-out lines and a plurality of second data fan-out lines; the plurality of first data fan-out lines include a plurality of first data fan-out lines of a first type and a plurality of first data fan-out lines of a second type, the first data fan-out lines of the first type and the first data fan-out lines of the second type being spaced apart, the first data fan-out lines of the first type being located closer to the substrate than the first data fan-out lines of the second type, and orthogonal projections of the first data fan-out lines of the first type on the substrate and the first data fan-out lines of the second type on the substrate do not overlap; 12. The display substrate of claim 10, wherein the plurality of second data fan-out lines includes a plurality of second data fan-out lines of a first type and a plurality of second data fan-out lines of a second type, the second data fan-out lines of the first type and the second data fan-out lines of the second type are spaced apart, the second data fan-out lines of the first type are located on a side of the second data fan-out lines of the second type closer to the substrate, and orthogonal projections of the second data fan-out lines of the first type on the substrate and the second data fan-out lines of the second type on the substrate do not overlap.

13. 13. The display substrate of claim 12, wherein the first data fan-out lines of the first type are electrically connected to the second data fan-out lines of the first type, and the first data fan-out lines of the second type are electrically connected to the second data fan-out lines of the second type.

14. the first data fan-out lines of the first type are located in a first source-drain metal layer, the first data fan-out lines of the second type are located in a second source-drain metal layer, the second data fan-out lines of the first type are located in a first gate metal layer, and the second data fan-out lines of the second type are located in a second gate metal layer; The display substrate of claim 12 or 13, wherein the first gate metal layer, the second gate metal layer, the first source / drain metal layer, and the second source / drain metal layer are located in different layers.

15. The display substrate of any one of claims 10 to 14, wherein the first compensation unit is electrically connected to the first data fan-out line, and the first compensation unit is located in the first fan-out region and on a side of the first data fan-out line that is closer to the display area.

16. the first bezel region further includes a folding region and a second fan-out region sequentially disposed along a direction away from the display region of the first fan-out region, 16. The display substrate of claim 10, wherein the at least one data outgoing line includes a data folding line located in the folding region and a third data fan-out line located in the second fan-out region, and the data folding line is electrically connected to the second data fan-out line in the first fan-out region and the third data fan-out line in the second fan-out region.

17. 17. The display substrate of claim 16, wherein the first and third data fan-out lines electrically connected to the second data fan-out lines have the same layer structure.

18. The display substrate of any one of claims 1 to 17, wherein the substrate further includes a second bezel area located on the remaining side of the display area, wherein at least one second compensation unit and at least one first signal line are installed in the second bezel area, the at least one first signal line is electrically connected to the second compensation unit, and the second compensation unit is configured to compensate for at least one of a resistance and a capacitance of the at least one first signal line.

19. 20. The display substrate of claim 18, wherein the second compensation unit includes at least one second compensation capacitor, a first electrode of the at least one second compensation capacitor electrically connected to the at least one first signal line, and a second electrode of the at least one second compensation capacitor electrically connected to a ground terminal.

20. the substrate further includes a second bezel region located on a remaining side of the display region; a gate driving circuit and a clock signal line electrically connected to the gate driving circuit are installed in the second bezel area; The display substrate of any one of claims 1 to 19, wherein a third compensation unit is further installed in the first bezel area, the clock signal line is electrically connected to the third compensation unit, and the third compensation unit is configured to compensate for at least one of a resistance and a capacitance of the clock signal line.

21. A display device comprising the display substrate according to any one of claims 1 to 20.

Images