MEMORY CONTROLLER, MEMORY SYSTEM FOR DATA SET MANAGEMENT HANDLING, METHOD, AND STORAGE MEDIUM THEREOF

Abstract

In some aspects, the memory controller includes a data classification accelerator, a deallocation accelerator, and a mapping table accelerator. The data classification accelerator is configured to divide the deallocated logical range into a set of deallocation zones. The set of deallocation zones includes one or more first deallocation zones that are each classified into one or more alignment zones. The deallocation accelerator is operatively coupled to the data classification accelerator and configured to update a data set management (DSM) bitmap based on the one or more alignment zones. The mapping table accelerator is operatively coupled to the data classification accelerator and the deallocation accelerator. The mapping table accelerator is configured to generate a response indicating that the deallocated logical range is to be processed in response to updating the DSM bitmap.

Description

[Technical Field]

[0001] The present disclosure relates to a memory controller, a memory system, and a method of operating the same. [Background technology]

[0002] A solid-state drive (SSD) is a type of non-volatile data storage device that has become very popular in recent years due to several advantages over traditional hard drive disks (HDDs), such as faster reads and writes, durability and reliability, low power consumption, quieter operation, and smaller form factors. SSDs may typically use NAND flash memory for non-volatile storage. Some SSDs, e.g., enterprise SSDs, may also use volatile memory (e.g., dynamic random access memory (DRAM)) to enhance performance, allowing for faster access to data and more efficient handling of read and write operations. Summary of the Invention [Means for solving the problem]

[0003] In one aspect, the memory controller includes a data classification accelerator, a deallocation accelerator, and a mapping table accelerator. The data classification accelerator is configured to divide the deallocated logical range into a set of deallocation zones. The set of deallocation zones includes one or more first deallocation zones that are each classified into one or more alignment zones. The deallocation accelerator is operatively coupled to the data classification accelerator and configured to update a data set management (DSM) bitmap based on the one or more alignment zones. The mapping table accelerator is operatively coupled to the data classification accelerator and the deallocation accelerator. The mapping table accelerator is configured to generate a response indicating that the deallocated logical range is to be processed in response to updating the DSM bitmap.

[0004] In some implementations, the mapping table accelerator is further configured to update a logical-to-physical (L2P) mapping table based on the DSM bitmap.

[0005] In some implementations, to update the L2P mapping table based on the DSM bitmap, the mapping table accelerator is further configured to identify one or more alignment zones from the DSM bitmap and update the L2P mapping table based on the one or more alignment zones.

[0006] In some implementations, to update the L2P mapping table based on the one or more alignment zones, the mapping table accelerator is further configured to identify a first list of logical addresses within the one or more alignment zones and invalidate the first list of logical addresses in the L2P mapping table.

[0007] In some implementations, the set of deallocated zones further includes one or more second deallocated zones that are each classified into one or more non-aligned zones. The mapping table accelerator is further configured to update the L2P mapping based on the one or more non-aligned zones and to generate a response responsive to both the update of the DSM bitmap and the update of the L2P mapping table based on the one or more non-aligned zones.

[0008] In some implementations, to update the L2P mapping table based on the one or more unaligned zones, the mapping table accelerator is further configured to identify a second list of logical addresses within the one or more unaligned zones and invalidate the second list of logical addresses in the L2P mapping table.

[0009] In some implementations, the data classification accelerator is configured to divide the deallocated logical ranges into a set of deallocated zones based on a zoning of the logical space of a non-volatile memory device coupled to the memory controller, such that the division of the deallocated logical ranges matches the zoning of the logical space of the non-volatile memory device.

[0010] In some implementations, the logical space of the non-volatile memory device is divided into a plurality of logical zones, each of which is equal to one or more first deallocated zones such that the one or more first deallocated zones are grouped into one or more aligned zones that are aligned with the one or more first logical zones from the plurality of logical zones, and each of which is smaller than one or more second deallocated zones such that the one or more second deallocated zones are grouped into one or more non-aligned zones that are not aligned with the one or more second logical zones from the plurality of logical zones.

[0011] In some implementations, the non-volatile memory device includes a NAND flash memory.

[0012] In another aspect, a memory system includes a non-volatile memory device and a memory controller operably coupled to the non-volatile memory device. The memory controller is configured to control the non-volatile memory device. The memory controller includes a data classification accelerator, a deallocation accelerator, and a mapping table accelerator. The data classification accelerator is configured to divide a deallocated logical range into a set of deallocation zones. The set of deallocation zones includes one or more first deallocation zones that are each classified into one or more alignment zones. The deallocation accelerator is operably coupled to the data classification accelerator and configured to update a DSM bitmap based on the one or more alignment zones. The mapping table accelerator is operably coupled to the data classification accelerator and the deallocation accelerator. The mapping table accelerator is configured to generate a response indicating that the deallocated logical range is to be processed in response to updating the DSM bitmap.

[0013] In some implementations, the mapping table accelerator is further configured to update the L2P mapping table based on the DSM bitmap.

[0014] In some implementations, to update the L2P mapping table based on the DSM bitmap, the mapping table accelerator is further configured to identify one or more alignment zones from the DSM bitmap and update the L2P mapping table based on the one or more alignment zones.

[0015] In some implementations, to update the L2P mapping table based on the one or more alignment zones, the mapping table accelerator is further configured to identify a first list of logical addresses within the one or more alignment zones and invalidate the first list of logical addresses in the L2P mapping table.

[0016] In some implementations, the set of deallocated zones further includes one or more second deallocated zones that are each classified as one or more non-aligned zones. The mapping table accelerator is further configured to update the L2P mapping table based on the one or more non-aligned zones and to generate a response responsive to both the update of the DSM bitmap and the update of the L2P mapping table based on the one or more non-aligned zones.

[0017] In some implementations, to update the L2P mapping table based on the one or more unaligned zones, the mapping table accelerator is further configured to identify a second list of logical addresses within the one or more unaligned zones and invalidate the second list of logical addresses in the L2P mapping table.

[0018] In some implementations, the data classification accelerator is configured to divide the deallocated logical range into a set of deallocated zones based on the zoning of the logical space of the non-volatile memory device, such that the division of the deallocated logical range matches the zoning of the logical space of the non-volatile memory device.

[0019] In some implementations, the logical space of the non-volatile memory device is divided into a plurality of logical zones, each of which is equal to one or more first deallocated zones such that the one or more first deallocated zones are grouped into one or more aligned zones that are aligned with the one or more first logical zones from the plurality of logical zones, and each of which is smaller than one or more second deallocated zones such that the one or more second deallocated zones are grouped into one or more non-aligned zones that are not aligned with the one or more second logical zones from the plurality of logical zones.

[0020] In some implementations, the non-volatile memory device includes a NAND flash memory.

[0021] In yet another aspect, a method for operating a memory controller is provided. A deallocated logical range is divided into a set of deallocated zones. The set of deallocated zones includes one or more first deallocated zones that are each classified into one or more alignment zones. A DSM bitmap is updated based on the one or more alignment zones. In response to updating the DSM bitmap, a response is generated indicating that the deallocated logical range is processed.

[0022] In some implementations, the L2P mapping table is updated based on the DSM bitmap.

[0023] In some implementations, updating the L2P mapping table based on the DSM bitmap includes identifying one or more alignment zones from the DSM bitmap and updating the L2P mapping table based on the one or more alignment zones.

[0024] In some implementations, updating the L2P mapping table based on the one or more alignment zones includes identifying a first list of logical addresses within the one or more alignment zones and invalidating the first list of logical addresses in the L2P mapping table.

[0025] In some implementations, the set of deallocated zones further includes one or more second deallocated zones that are classified as one or more non-aligned zones, respectively. The method further includes updating the L2P mapping table based on the one or more non-aligned zones, and generating a response responsive to both the update of the DSM bitmap and the update of the L2P mapping table based on the one or more non-aligned zones.

[0026] In some implementations, updating the L2P mapping table based on the one or more unaligned zones includes identifying a second list of logical addresses within the one or more unaligned zones and invalidating the second list of logical addresses in the L2P mapping table.

[0027] In some implementations, dividing the deallocated logical range into a set of deallocated zones includes dividing the deallocated logical range into the set of deallocated zones based on a zoning of a logical space of a non-volatile memory device coupled to the memory controller, such that the division of the deallocated logical range matches the zoning of the logical space of the non-volatile memory device.

[0028] In some implementations, the logical space of the non-volatile memory device is divided into a plurality of logical zones, each of which is equal to one or more first deallocated zones such that the one or more first deallocated zones are grouped into one or more aligned zones that are aligned with the one or more first logical zones from the plurality of logical zones, and each of which is smaller than one or more second deallocated zones such that the one or more second deallocated zones are grouped into one or more non-aligned zones that are not aligned with the one or more second logical zones from the plurality of logical zones.

[0029] In some implementations, the non-volatile memory device includes a NAND flash memory.

[0030] In yet another aspect, a non-transitory computer-readable storage medium is disclosed that stores instructions. When executed by a memory controller of a memory system, the instructions cause the memory controller to perform a method. The method includes dividing a deallocated logical range into a set of deallocated zones. The set of deallocated zones includes one or more first deallocated zones that are each classified into one or more alignment zones. The method also includes updating a DSM bitmap based on the one or more alignment zones. In response to updating the DSM bitmap, the method further includes generating a response indicating that the deallocated logical range is processed.

[0031] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable those skilled in the art to make and use the disclosure. [Brief explanation of the drawings]

[0032] [Figure 1] FIG. 1 is a block diagram of a system including a memory system in accordance with some aspects of the present disclosure. [Figure 2A] FIG. 1 is a diagram of a memory card having a memory device in accordance with some aspects of the present disclosure. [Figure 2B] 1 is a diagram of an SSD having a memory device according to some aspects of the present disclosure. [Figure 3] FIG. 1 is a block diagram of a memory controller in accordance with some aspects of the present disclosure. [Figure 4] FIG. 2 is a schematic diagram of a NAND flash memory device including peripheral circuitry in accordance with some aspects of the present disclosure. [Figure 5] 1 is a schematic diagram of a DRAM device including peripheral circuitry in accordance with some aspects of the present disclosure. [Figure 6] FIG. 1 is a detailed schematic diagram of a memory system for DSM handling, in accordance with some aspects of the present disclosure. [Figure 7]FIG. 1 illustrates an L2P mapping table in accordance with certain aspects of the present disclosure. [Figure 8A] FIG. 10 illustrates an example of updating a DSM bitmap in accordance with certain aspects of the present disclosure. [Figure 8B] FIG. 10 illustrates another example of updating a DSM bitmap in accordance with some aspects of the present disclosure. [Figure 9] 1 is a flowchart of a method for operating a memory controller in accordance with some aspects of the present disclosure. [Figure 10] 10 is a flowchart of another method for operating a memory controller in accordance with some aspects of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0033] The present disclosure will be described with reference to the accompanying drawings.

[0034] In general, terms may be understood, at least in part, from their usage in context. For example, as used herein, the term "one or more" may be used to describe any feature, structure, or characteristic in the singular sense, or may be used to describe a combination of features, structures, or characteristics in the plural sense, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may be understood as conveying the singular or the plural, depending at least in part on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exhaustive set of factors, and instead may allow for the existence of additional factors, also not necessarily expressly described, depending at least in part on the context.

[0035] The Non-Volatile Memory Express (NVMe) specification defines DSM commands that can be used to mark unused host data space to improve host performance. For example, the DSM command may indicate a logical range to be deallocated (or released) by the host. In response to receiving the DSM command, a memory controller coupled to the non-volatile memory device may handle the deallocation of the logical range. For example, the memory controller may deallocate or release one or more logical addresses, such as logical block addresses (LBAs), included in the DSM command. In a further example, the memory controller may deallocate or release one or more logical addresses from the logical space of a non-volatile memory device coupled to the memory controller. If the logical range is small, the memory controller may deallocate the logical range quickly. The DSM response time (e.g., the time to send a response indicating completion of the deallocation to the host) is short. However, if the logical range is large, the deallocation of the logical range by the memory controller may consume a significant amount of time. The DSM response time to the host is high, which can affect the host's read / write input / output (I / O) latency.

[0036] To address the aforementioned issues, the present disclosure introduces a handling scheme that can shorten DSM response times associated with allocating large logical ranges, thereby reducing the impact of DSM handling on host I / O latency. Specifically, a DSM command may instruct the deallocation of a large logical range. The large logical range may be divided into a set of deallocation zones, which may include at least one of: (1) one or more first deallocation zones, each classified into one or more aligned zones; or (2) one or more second deallocation zones, each classified into one or more non-aligned zones. The one or more non-aligned zones may be directly processed to update the L2P mapping table so that a list of logical addresses in the one or more non-aligned zones may be marked as invalid addresses in the L2P mapping table. Meanwhile, the one or more aligned zones may be processed to update the DSM bitmap to record corresponding deallocation information in the DSM bitmap. A response indicating that the deallocated logical range will be processed may then be generated and sent to the host before the L2P mapping table is updated for the one or more aligned zones. Then, after the response is sent to the host, the one or more alignment zones may be deallocated in the background based on the DSM bitmap, such that another list of logical addresses in the one or more alignment zones may be marked as invalid addresses in the L2P mapping table. Thus, for DSM handling, the DSM response time to DSM commands may be reduced because the response may be sent to the host before the one or more alignment zones are actually deallocated by the memory controller. The impact of DSM handling on host I / O latency may be reduced.

[0037] It is contemplated that the handling scheme disclosed herein may be applied not only to handling DSM commands related to the NVMe specification, but also to handling commands related to other standards not limited to this specification. For example, the handling scheme disclosed herein may also be applied to handling a Trim command. The Trim command is a command that notifies a solid-state drive (SSD) which LBAs are no longer needed by the host. The SSD may update its own internal records to mark the LBAs as invalid (e.g., by updating the corresponding entry in a logical-to-physical (L2P) mapping table to an empty address, clearing the corresponding bit in a valid page bitmap, updating the valid page count, etc.). The SSD may no longer move LBAs that are internally marked as invalid blocks during garbage collection, which eliminates time wasted rewriting invalid data to new flash pages. In another example, the handling scheme disclosed herein may also be applied to handling an UNMAP command, which is a Small Computer System Interface (SCSI) command that a host can issue to a storage array to free LBAs that no longer need to be allocated.

[0038] FIG. 1 illustrates a block diagram of a system 100 including a memory system 102 according to some aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device with storage. As illustrated in FIG. 1, the system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 108 may be configured to transmit data (also known as user data or host data) to or receive data from the memory system 102. The memory system 102 may be a storage product that integrates the memory controller 106 and one or more memory devices 104, such as an SSD.

[0039] The memory device 104 may be any memory device disclosed in this disclosure, including non-volatile memory devices such as NAND flash memory devices. In some implementations, the memory device 104 also includes one or more volatile memory devices, such as DRAM devices or static random access memory (SRAM) devices.

[0040] According to some implementations, the memory controller 106 is operably coupled to the memory device 104 and the host 108 and configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some implementations, the memory controller 106 is designed to operate in a low-duty-cycle environment, such as with a Secure Digital (SD) card, a CompactFlash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some implementations, the memory controller 106 is designed to operate in a high-duty-cycle environment with an SSD or an embedded multimedia card (eMMC) used as data storage for mobile devices such as smartphones, tablets, laptop computers, and enterprise storage arrays. The memory controller 106 can be configured to control operations of the memory device 104, such as read operations, program / write operations, and / or erase operations. Memory controller 106 may also be configured to manage various functions with respect to data stored or to be stored in memory device 104, including, but not limited to, bad block management, garbage collection, L2P address translation, wear leveling, etc. In some implementations, memory controller 106 is further configured to process error correcting codes (ECC) with respect to data read from and written to memory device 104. Any other suitable functions, such as formatting memory device 104, may also be performed by memory controller 106. Memory controller 106 can communicate with external devices (e.g., host 108) according to a particular communication protocol.For example, the memory controller 106 may communicate with external devices through at least one of a variety of interface protocols, such as a Non-Volatile Memory Express (NVMe) protocol, an NVMe-over-fabrics (NVMe-oF) protocol, a PCI-express (PCI-E) protocol, a Universal Serial Bus (USB) protocol, a Multimedia Card (MMC) protocol, a Peripheral Component Interconnection (PCI) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

[0041] The memory controller 106 and one or more memory devices 104 may be integrated into various types of storage devices and may be included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the memory system 102 may be implemented and packaged in different types of end electronic products. In one example, as shown in FIG. 2A , the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, personal computer memory card international association), a CF card, a SmartMedia (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS card, etc. The memory card 202 may further include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 of FIG. 1 ). In another example, as shown in FIG. 2B , the memory controller 106 and multiple memory devices 104 may be integrated into an SSD 206. The SSD 206 may further include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 108 in FIG. 1 ). In some implementations, the storage capacity and / or operating speed of the SSD 206 are greater than those of the memory card 202. In some implementations, the memory system 102 is implemented as an SSD 206 that includes both non-volatile memory devices, such as the memory device 104, such as an enterprise SSD, and volatile memory devices.

[0042] FIG. 3 shows a block diagram of a memory controller 300 according to some aspects of the present disclosure. The memory controller 300 may be an example of the memory controller 106 of FIG. 1. As shown in FIG. 3, the memory controller 300 may include a processing unit 308, a cache 310, and a read-only memory (ROM) 311. In some implementations, the processing unit 308 is implemented by a microprocessor (e.g., a digital signal processor (DSP)) or a microcontroller (also known as a microcontroller unit (MCU)) that executes firmware and / or software modules to perform various functions described herein. The various firmware modules in the memory controller 300 described herein may be implemented as firmware code or instructions stored in the ROM 311 and executed by the processing unit 308. In some implementations, the processing unit 308 includes one or more hardware circuits, e.g., fixed logic units such as logic gates, multiplexers, flip-flops, state machines, field programmable gate arrays (FPGAs), programmable logic devices (PLDs), etc. For example, hardware circuitry may include dedicated circuitry that performs a given logical function that is known at the time of device manufacture, such as an application specific integrated circuit (ASIC).

[0043] 3, memory controller 300 may also include various input / output (I / O) interfaces (I / F), such as non-volatile memory interface 312, DRAM interface 314, and host interface 316, operably coupled to non-volatile memory device 302, DRAM 304 (e.g., an example of a volatile memory device), and host 306 (e.g., an example of host 108), respectively. Non-volatile memory interface 312, DRAM interface 314, and host interface 316 may be configured to transfer data, commands, clocks, or any suitable signals between processing unit 308 and non-volatile memory device 302, DRAM 304, and host 306, respectively. Non-volatile memory interface 312, DRAM interface 314, and host interface 316 may implement any suitable communication protocol that facilitates data transport, communication, and management, such as the NVMe protocol, PCI-E protocol, double data rate (DDR) protocol, to name a few.

[0044] As described above, both the cache 310 and the DRAM 304 may be considered volatile memory devices that may be controlled and accessed by the memory controller 300 in the memory system. Without being inconsistent with the scope of this disclosure, the cache may be implemented as part of the volatile memory devices, for example, by SRAM and / or DRAM 304. While FIG. 3 shows the cache 310 within the memory controller 300, it is understood that the DRAM 304 is external to the memory controller 300. In some examples, both the cache 310 and the DRAM 304 may be internal to the memory controller 300 or external to the memory controller 300.

[0045] FIG. 4 shows a schematic circuit diagram of a NAND flash memory device 400 including peripheral circuits 402 according to some embodiments of the present disclosure. The NAND flash memory device 400 may be an example of the non-volatile memory device 302 of FIG. 3 . The NAND flash memory device 400 may include a memory cell array 401 and peripheral circuits 402 operatively coupled to the memory cell array 401. The memory cells 406 in the memory cell array 401 are arranged in the form of an array of memory strings 408, each extending vertically above a substrate (not shown). In some implementations, each memory string 408 includes multiple memory cells 406 operatively coupled in series and stacked vertically. Each memory cell 406 can hold a continuous analog value, such as a voltage or charge, depending on the number of electrons trapped in the region of the memory cell 406. Each memory cell 406 may be either a floating-gate memory cell including a floating-gate transistor or a charge-trap memory cell including a charge-trap transistor.

[0046] In some implementations, each memory cell 406 is a single-level cell (SLC), which has two possible levels (memory states) and can therefore store one bit of data. For example, a first state "0" may correspond to a first range of threshold voltages, and a second state "1" may correspond to a second range of threshold voltages. In some implementations, each memory cell 406 is an xLC, which is capable of storing multiple bits of data at more than four levels. For example, an xLC may store two bits per cell (also known as a multi-level cell (MLC)), three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each xLC has a range of possible nominal storage values ​​(i.e., 2 N In some implementations, each memory cell 406 can be programmed with two N-bit data bits corresponding to one N-bit data bit. Nlevels, where N is an integer greater than 1. N may indicate the total number of bits per cell. For example, N=2 for MLC, N=3 for TLC, or N=4 for QLC.

[0047] 4, each memory string 408 may also include a source select gate (SSG) transistor 410 on its source side and a drain select gate (DSG) transistor 412 on its drain side. The SSG transistor 410 and the DSG transistor 412 may be configured to activate a selected memory string 408 (a column of the array) during read and program operations. In some implementations, the sources of memory strings 408 in the same block 404 are coupled through the same source line (SL) 414, e.g., a common SL. In other words, according to some implementations, all memory strings 408 in the same block 404 have an array common source (ACS). According to some implementations, the drain of each memory string 408 is coupled to a respective bit line 416 from which data may be read and written via an output bus (not shown). In some implementations, each memory string 408 is configured to be selected or deselected by applying a select voltage or deselect voltage to the gate of the respective DSG transistor 412 through one or more DSG lines 413 and / or by applying a select voltage or deselect voltage to the gate of the respective SSG transistor 410 through one or more SSG lines 415.

[0048] 4, the memory strings 408 may be organized into multiple blocks 404, each of which may have a common source line 414 coupled to, for example, an ACS. In some implementations, each block 404 is the basic data unit for an erase operation, i.e., all memory cells 406 on the same block 404 are erased simultaneously. To erase the memory cells 406 in a selected block 404, the source line 414 coupled to the selected block 404, as well as the deselected blocks 404 on the same plane as the selected block 404, may be biased with an erase voltage (Vers), such as a high positive bias voltage (e.g., 20 V or greater).

[0049] Memory cells 406 of adjacent memory strings 408 may be coupled through word lines 418, which select which row of memory cells 406 is affected by read and program operations. In some implementations, each word line 418 is coupled to a physical page 420 of memory cells 406, which is the basic data unit for read and write (program) operations. The size of one physical page 420 in bits may be related to the number of memory strings 408 coupled by a word line 418 in one block 404. Each word line 418 may include multiple control gates (gate electrodes) for each memory cell 406 in the respective physical page 420 and gate lines coupling the control gates.

[0050] The peripheral circuitry 402 may be operatively coupled to the memory cell array 401 through bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. The peripheral circuitry 402 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of the memory cell array 401 by applying voltage and / or current signals to and sensing voltage and / or current signals from each selected memory cell 406 through the bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. The peripheral circuitry 402 may include various types of peripheral circuits formed using complementary metal-oxide-semiconductor (CMOS) technology.

[0051] FIG. 5 shows a schematic circuit diagram of a DRAM device 500 including peripheral circuitry 502 according to some embodiments of the present disclosure. The DRAM device 500 may be an example of the DRAM 304 of FIG. 3. The DRAM device 500 may include a memory cell array 501 and peripheral circuitry 502 operatively coupled to the memory cell array 501. The memory cells 503 may be arranged in the memory cell array 501 having rows and columns. The DRAM device 500 requires periodic refreshing of the memory cells 503. In some implementations, each memory cell 503 includes a capacitor 507 for storing a bit of data as a positive or negative charge, and a transistor 505 that controls access to the capacitor 507. That is, according to some implementations, each memory cell 503 shown in FIG. 5 is a one-transistor-one-capacitor (1T1C) cell.

[0052] The DRAM device 500 may include word lines 504 coupling the peripheral circuitry 502 to the memory cell array 501 for controlling switches of transistors 505 in the memory cells 503 located in rows, and bit lines 506 coupling the peripheral circuitry 502 to the memory cell array 501 for transmitting and / or receiving data to and / or from the memory cells 503 located in columns. That is, each word line 504 is coupled to a respective row of memory cells 503, and each bit line 506 is coupled to a respective column of memory cells 503. The gate of the transistor 505 may be coupled to the word line 504, one of the source and drain of the transistor 505 may be coupled to the bit line 506, the other of the source and drain of the transistor 505 may be coupled to one electrode of a capacitor 507, the other electrode of the capacitor 507 may be coupled to ground.

[0053] The peripheral circuitry 502 may be coupled to the memory cell array 501 through bit lines 506, word lines 504, and any other suitable metal wiring. The peripheral circuitry 502 may include any suitable circuitry for facilitating operation of the memory cell array 501 by applying voltage and / or current signals to and sensing voltage and / or current signals from each memory cell 503 through the word lines 504 and bit lines 506. The peripheral circuitry 502 may include various types of peripheral circuits formed using CMOS technology.

[0054] FIG. 6 shows a detailed schematic diagram of a memory system 600 for DSM handling in accordance with some aspects of the present disclosure. The memory system 600 may be an example of the memory system 102 of FIG. 1. As shown in FIG. 6, the memory system 600 may include a memory controller 601, a volatile memory device 602, and a non-volatile memory device 604. The memory controller 601 may be an example of the memory controller 106 of FIG. 1. The volatile memory device 602 and the non-volatile memory device 604 may be examples of the memory device 104 of FIG. 1. In some implementations, the volatile memory device 602 includes DRAM (e.g., the DRAM device 500 of FIG. 5), and the non-volatile memory device 604 includes NAND flash memory (e.g., the NAND flash memory device 400 of FIG. 4). In some implementations, the memory controller 601 is further configured to cache one host / user data in the volatile memory device 602 or flush the host / user data from the volatile memory device 602 to the non-volatile memory device 604.

[0055] To enable data retrieval and access, the non-volatile memory device 604 may be divided into multiple memory regions 605, each having a unique physical address. In some implementations, each memory region 605 comprises one or more logical pages, e.g., a portion (e.g., ½, ¼, or ⅛) of one physical page 420 of the NAND flash memory device 400. For example, each memory region 605 may be 4096 bytes in size. It will be understood that the memory region 605 may correspond to any suitable group of memory cells in the non-volatile memory device 604 other than a page, such as a portion of a page, a block (e.g., a block 404 of the NAND flash memory device 400), or the like. For example, the physical address of a memory region 605 may be referred to as a physical allocated address (PAA), and the logical address corresponding to a PAA may be referred to as a logical allocated address (LAA). In another example, the physical address of memory region 605 may be a physical page address (PAA) when memory region 605 corresponds to a page of non-volatile memory device 604, and the logical address corresponding to the PAA may be a logical block address (LBA).

[0056] The cache 606 may be a portion of the volatile memory device 602 that temporarily stores (caches) frequently used and / or recently accessed data to speed up read and write operations to the non-volatile memory device 604. Any suitable caching algorithm may be used to determine which data should be stored in the cache 606 and when the data should be replaced, including, for example, least recently used (LRU), most recently used (MRU), and first-in, first-out (FIFO). In some implementations, data from the host (host / user data) is first cached in the cache 606 of the volatile memory device 602 and conditionally flushed to the non-volatile memory device 604 based on the caching algorithm. For example, when the size of the data in the cache 606 reaches a preset threshold (maximum cache size), the data in the cache 606 may be flushed to the non-volatile memory device 604. The cache 606 may be implemented by any suitable type of volatile memory device 602, for example, DRAM 304 and / or SRAM.

[0057] In some implementations, the DSM bitmap may be stored in cache 606, while in some other implementations, the DSM bitmap may be stored in a register (not shown) of memory controller 601. It is understood that the DSM bitmap may also be stored in non-volatile memory device 604, and this is not a limitation herein.

[0058] To enable data retrieval and access, an L2P mapping table 612 may be maintained and stored in the volatile memory device 602 to map logical addresses of data to physical addresses 616 (e.g., PPAs) of memory regions 605 in the non-volatile memory device 604, respectively. The logical addresses may identify host / user data and may be known to the memory controller 601. In some implementations, the logical addresses indicate the basic logical unit of data for each read and write operation, such as a logical block address (LBA). In some implementations, the size of each memory region 605 and the size of the data corresponding to each logical address may be the same. For example, the size of the data corresponding to each logical address may also be 4096 bytes. Because the memory controller 601 operates based on logical addresses, as opposed to physical addresses (e.g., physical addresses 616), the L2P mapping table 612 may be used to enable translation between logical addresses and physical addresses.

[0059] In some implementations, the L2P mapping table 612 may be stored in a non-volatile memory device 604. In some other implementations, the L2P mapping table 612 may be stored in any suitable type of volatile memory device 602, such as the DRAM 304 of FIG. 3. For example, the same volatile memory device 602, such as the DRAM 304 of FIG. 3, includes both the cache 606 and the L2P mapping table 612. It will be appreciated that in some examples, the cache 606 and the L2P mapping table 612 may be included in different volatile memory devices 602. For example, the cache 606 may be included in an SRAM, while the DRAM 304 may include the L2P mapping table 612. Although the L2P mapping table 612 is shown in FIG. 6 as being outside of the cache 606, it will be appreciated that in some examples, the L2P mapping table 612 may also be stored in the cache 606.

[0060] In some implementations, the L2P mapping table 612 may be stored in the volatile memory device 602 using addresses in the volatile memory device 602. For example, as shown in FIG. 7 , the L2P mapping table 612 may include addresses 704 (volatile memory (VM) addresses) in the volatile memory device 602, each associated with a value 706. The values ​​706 may include physical addresses 616 (e.g., PPAs) of memory regions 605 (e.g., PPA1, PPA2, PPA3, PPA4, etc.) in the non-volatile memory device 604. As shown in FIG. 7 , the L2P mapping table 612 may map logical addresses 702 (LBAs) of the host / user data to the physical addresses 616 of the memory regions 605 in the non-volatile memory device 604 through the addresses 704. For example, for each host / user data, a corresponding address 704 for an entry of the L2P mapping table 612 in the volatile memory device 602 may be determined based on the respective LBA 702 associated with that host / user data. In one example as shown in FIG. 7 , each LBA 702 associated with an entry (e.g., 0, 1, 2, 3, 4, 5, 6, etc.) may be multiplied by an entry size Δ and added with an address offset (OFF) to form the entry's corresponding address 704 (e.g., address 704 = OFF + LBA × Δ), where the entry size Δ may represent the length of the value 706 stored in the entry (e.g., Δ = 4 bytes). The address offset may be determined, for example, based on where the L2P mapping table 612 is stored in the volatile memory device 602. Accordingly, the corresponding value 706 at the determined address 704 in the L2P mapping table 612 may be determined, which indicates the physical address 616 of the memory region in the non-volatile memory device 604. Thus, each host / user data LBA 702 may be mapped by the L2P mapping table 612 to multiple physical addresses (e.g., the physical address 616 of the memory region 605 in the non-volatile memory device 604).

[0061] 6, memory controller 601 may include multiple I / O interfaces, including a volatile memory interface 620 operably coupled to volatile memory device 602, a non-volatile memory interface 622 operably coupled to non-volatile memory device 604, and a host interface 618 operably coupled to cache 606 of volatile memory device 602 and a host (not shown). Examples of these I / O interfaces may include DRAM interface 314, non-volatile memory interface 312, and host interface 316 of FIG. 3, which may implement any suitable communication protocol that facilitates data transport, communication, and management, such as the NVMe protocol, PCI-E protocol, DDR protocol, to name a few.

[0062] The host interface 618 may be configured to receive write and read requests from the host. Each write request may indicate a piece of data associated with a logical address (e.g., an LBA) to be written to the memory system 600. Similarly, each read request may indicate a piece of data associated with a logical address (e.g., an LBA) to be read from the memory system 600. In some implementations, in response to receiving a write or read request, the host interface 618 is also configured to fetch data from the host for temporary storage (caching) in the cache 606, or vice versa. For example, the host interface 618 may include a direct memory access (DMA) unit to access data from or to the cache 606.

[0063] In some implementations, the host interface 618 may be configured to receive DSM commands from the host and send the DSM commands to the data classification accelerator 608. The DSM commands may indicate logical ranges to be deallocated. For example, the DSM commands may indicate logical ranges to be deallocated from the logical space of the non-volatile memory device 604. For example, the DSM commands may indicate logical ranges to be invalidated from the logical space of the non-volatile memory device 604 so that the host (or memory controller 601) no longer has access to the invalidated logical addresses within the logical range. In some implementations, the host interface 618 may be configured to receive responses 617 to the DSM commands from the mapping table accelerator 611 and send the responses 617 to the host. The data classification accelerator 608, the mapping table accelerator 611, and the responses 622 are described in more detail below.

[0064] The non-volatile memory interface 622 may be configured to allow the memory controller 601 to access data stored in the non-volatile memory device 604 based on a physical address (e.g., a PPA) of the memory region 605. The volatile memory interface 620 may be configured to allow the memory controller 601 to access data stored in the volatile memory device 602, for example, to manage the L2P mapping table 612 to access data in the cache 606.

[0065] 6, memory controller 601 may further include a data classification accelerator 608, a deallocation accelerator 610, and a mapping table accelerator 611, which are operatively coupled to host interface 618, non-volatile memory interface 622, and volatile memory interface 620, respectively. In some implementations, data classification accelerator 608, deallocation accelerator 610, and mapping table accelerator 611 are firmware modules implemented by firmware codes / instructions stored in a memory (e.g., ROM 311 of FIG. 3 or non-volatile memory device 302 of FIG. 3) and executed by a processing unit (e.g., processing unit 308 of FIG. 3). In some implementations, the data classification accelerator 608, the deallocation accelerator 610, and the mapping table accelerator 611 are implemented in software using code / instructions stored in a memory (e.g., the ROM 311 of FIG. 3 or the non-volatile memory device 302 of FIG. 3) and executed by a processing unit (e.g., the processing unit 308 of FIG. 3). In some implementations, the data classification accelerator 608, the deallocation accelerator 610, and the mapping table accelerator 611 are hardware modules implemented by dedicated circuitry, such as an ASIC, for performing the dedicated functions described herein. A hardware implementation of the data classification accelerator 608, the deallocation accelerator 610, and the mapping table accelerator 611 can reduce firmware overhead, thereby improving the performance of the memory system 600.

[0066] The data classification accelerator 608 may be configured to receive a DSM command from the host interface 618. The DSM command may indicate a logical range to be deallocated (e.g., a logical range to be allocated from the logical space of the non-volatile memory device 604). The data classification accelerator 608 may divide the logical range into a set of deallocation zones. For example, the data classification accelerator 608 may divide the logical range into a set of deallocation zones based on the zoning of the logical space of the non-volatile memory device 604, such that the division of the logical range matches the zoning of the logical space of the non-volatile memory device 604.

[0067] For example, the logical space of the non-volatile memory device 604 may be divided into multiple logical zones (e.g., each logical zone has a size of 16 MiB). The logical range may then be divided into a set of deallocated zones such that each deallocated zone may either be identical to a particular logical zone from the multiple logical zones (e.g., the deallocated zone has the same boundaries as the particular logical zone) or smaller than a particular logical zone from the multiple logical zones (e.g., the deallocated zone is within the boundaries of the particular logical zone). If the deallocated zone is identical to a particular logical zone, the deallocated zone may be classified as an aligned zone, indicating that the deallocated zone is aligned with the particular logical zone. If the deallocated zone is smaller than a particular logical zone and is within the particular logical zone, the deallocated zone may be classified as a non-aligned zone, indicating that the deallocated zone is not aligned with that particular logical zone. Examples of aligned and non-aligned zones are shown below with respect to Figures 8A-8B.

[0068] In some implementations, a set of deallocation zones divided from a logical range may include one or more first deallocation zones that each fall into one or more aligned zones. For example, one or more first deallocation zones may each be equal to one or more first logical zones from multiple logical zones, such that the one or more first deallocation zones may each fall into one or more aligned zones that are aligned with the one or more first logical zones. In some implementations, a set of deallocation zones may include one or more second deallocation zones that each fall into one or more non-aligned zones. For example, one or more second deallocation zones may each be smaller than one or more second logical zones from multiple logical zones, such that the one or more second deallocation zones may each fall into one or more non-aligned zones that are not aligned with the one or more second logical zones from the multiple logical zones. In some other implementations, the set of deallocated zones may include a combination of (1) one or more first deallocated zones that are each classified into one or more alignment zones, and (2) one or more second deallocated zones that are each classified into one or more non-alignment zones.

[0069] The deallocation accelerator 610 may be configured to update a DSM bitmap based on one or more alignment zones. Initially, a DSM bitmap may be generated for multiple logical zones of the non-volatile memory device 604 to begin with. For example, the DSM bitmap may include multiple bits for multiple logical zones, each bit corresponding to a respective logical zone and initially having a first value (e.g., “0”). Next, for each alignment zone, the deallocation accelerator 610 may update the DSM bitmap and modify the corresponding bit of the aligned zone to have a second value (e.g., “1”). The corresponding bit having the second value may indicate that the alignment zone (or equivalently, the same logical zone as the alignment zone) should be deallocated from the logical space of the non-volatile memory device 604. The deallocation accelerator 610 may then send the updated DSM bitmap to the mapping table accelerator 611. Examples of DSM bitmaps are shown below with respect to FIGS. 8A-8B.

[0070] As described in more detail below, the mapping table accelerator 611 may be configured to update the L2P mapping table 612 based on one or more non-aligned zones, the DSM bitmap, or both. Consistent with certain implementations of the present disclosure, a set of deallocation zones divided from a logical range may include one or more first deallocation zones, each of which falls into one or more aligned zones. In this case, the deallocation accelerator 610 may update the DSM bitmap based on the one or more aligned zones and send the DSM bitmap to the mapping table accelerator 611. The mapping table accelerator 611 may generate a response 617 indicating that the logical range is processed in response to the update of the DSM bitmap. For example, the mapping table accelerator 611 may generate a response 617 indicating that the logical range is to be deallocated from the logical range of the non-volatile memory device 604 in response to the update of the DSM bitmap. The mapping table accelerator 611 may forward the response 617 to the host interface 618 and may cause the host interface 618 to send the response 617 to the host.

[0071] The mapping table accelerator 611 may then be configured to update the L2P mapping table 612 based on the DSM bitmap to actually deallocate one or more alignment zones (e.g., to actually deallocate one or more alignment zones from the logical space of the non-volatile memory device 604). That is, the mapping table accelerator 611 may identify one or more alignment zones from the DSM bitmap and update the L2P mapping table 612 based on the one or more alignment zones to deallocate the one or more alignment zones. For example, the mapping table accelerator 611 may identify one or more bits each having a second value from the DSM bitmap and determine the one or more alignment zones as being one or more logical zones corresponding to the one or more bits. The mapping table accelerator 611 may identify a first list of logical addresses within the one or more logical zones and invalidate the first list of logical addresses in the L2P mapping table 612.

[0072] To invalidate the first list of logical addresses in the L2P mapping table 612, the mapping table accelerator 611 may determine a list of entries from the L2P mapping table 612 that correspond to the first list of logical addresses and modify each of the entries to have a predetermined value “X” (e.g., X may be any appropriate value and is not limited herein). By setting the entry of the L2P mapping table 612 as the predetermined value “X,” the logical address corresponding to the entry may be marked as an invalid logical address in the L2P mapping table 612. For example, referring again to FIG. 7 , the value 706 of the first entry of the L2P mapping table 612 is modified from “PPA0” to the predetermined value “X,” indicating that the logical address “0” associated with the first entry of the L2P mapping table 612 is marked as an invalid logical address and is to be deallocated. Similarly, the value 706 of the second entry in the L2P mapping table 612 is modified from “PPA1” to a predetermined value “X,” indicating that the logical address “1” associated with the second entry in the L2P mapping table 612 is marked as an invalid logical address and is deallocated.

[0073] Referring back to FIG. 6 , in some implementations, response 617 may be generated and sent to the host after updating the DSM bitmap but before updating the L2P mapping table based on the DSM bitmap (e.g., before the actual deallocation of one or more alignment zones). In this case, the response time to the DSM command may be shortened because deallocation of one or more alignment zones may be performed in the background after response 617 is sent to the host. The response latency to the DSM command may be reduced, and the impact of DSM operations on host read / write I / O latency may also be reduced. In some other implementations, response 617 may be generated and sent to the host after updating the L2P mapping table based on the DSM bitmap. In this case, one or more alignment zones have already been deallocated when response 617 is sent to the host.

[0074] Consistent with some implementations of the present disclosure, the set of deallocated zones may include one or more second deallocated zones that each fall into one or more non-aligned zones. The mapping table accelerator 611 may update the L2P mapping table 612 based on the one or more non-aligned zones. That is, the mapping table accelerator 611 may identify a second list of logical addresses within the one or more non-aligned zones and invalidate the second list of logical addresses in the L2P mapping table 612. For example, the mapping table accelerator 611 may modify a list of entries in the L2P mapping table 612 that correspond to the second list of logical addresses to have a predetermined value “X.” The mapping table accelerator 611 may then generate a response 617 responsive to the update of the L2P mapping table 612 based on the one or more non-aligned zones. In some implementations, the response 617 may be generated and sent to the host after updating the L2P mapping table 612 based on the one or more non-aligned zones (e.g., after one or more non-aligned zones have already been deallocated).

[0075] Consistent with some implementations of the present disclosure, the set of deallocated zones may include both (1) one or more first deallocated zones that are each classified into one or more aligned zones, and (2) one or more second deallocated zones that are each classified into one or more non-aligned zones. In this case, deallocation accelerator 610 may update the DSM bitmap based on the one or more aligned zones. Mapping table accelerator 611 may update L2P mapping table 612 based on the one or more non-aligned zones so that the one or more non-aligned zones may be deallocated from the logical space of non-volatile memory device 604. Mapping table accelerator 611 may generate response 617 indicating deallocation from the logical space of non-volatile memory device 604 in response to both (1) the update of the DSM bitmap by deallocation accelerator 610 and (2) the update of L2P mapping table 612 based on the one or more non-aligned zones. The mapping table accelerator 611 may forward the response 617 to the host interface 618 and may cause the host interface 618 to send the response 617 to the host. Additionally, the mapping table accelerator 611 may update the L2P mapping table 612 based on the DSM bitmap so that one or more alignment zones may also be deallocated from the logical space of the non-volatile memory device 604.

[0076] In some implementations, response 617 may be generated and sent to the host after (1) the DSM bitmap is updated by deallocation accelerator 610 and (2) the L2P mapping table 612 is updated by mapping table accelerator 611 based on one or more non-aligned zones, but before the L2P mapping table 612 is further updated based on the DSM bitmap. In this case, when response 617 is sent to the host, deallocation of one or more alignment zones (through updating the L2P mapping table based on the DSM bitmap) has not yet been performed. Instead, deallocation of one or more alignment zones may be performed in the background after response 617 is sent to the host. Thus, response time to DSM commands may be shortened. Response latency to DSM commands may be reduced, and the impact of DSM handling on read / write I / O latency may also be reduced. In some other implementations, response 617 may be generated and sent to the host after (1) updating the L2P mapping table based on one or more non-aligned zones and (2) updating the L2P mapping table 612 based on the DSM bitmap. In this case, when response 617 is sent to the host, one or more alignment zones (as well as one or more non-alignment zones) have already been deallocated.

[0077] Referring again to FIG. 6 , an example implementation of the disclosed DSM handling scheme will now be provided. Initially, the memory controller 601 (e.g., the deallocation accelerator 610 of the memory controller 601) may divide the logical space of the non-volatile memory device 604 into multiple logical zones. Each logical zone may have a size of 16 MiB (or any other suitable value). The memory controller 601 (e.g., the deallocation accelerator 610 of the memory controller 601) may generate a DSM bitmap including multiple bits corresponding to the multiple logical zones, respectively. The memory controller 601 (e.g., the deallocation accelerator 610 of the memory controller 601) may initialize the multiple bits in the DSM bitmap to have a first value (e.g., “0”).

[0078] The data classification accelerator 608 may receive, through the host interface 618, a DSM command indicating a logical range to be deallocated. The data classification accelerator 608 may divide the logical range into a set of deallocated zones and classify each deallocated zone as either a non-aligned zone or an aligned zone. If the set of deallocated zones includes one or more non-aligned zones, the mapping table accelerator 611 may update the L2P mapping table 612 directly based on the one or more non-aligned zones and deallocate the one or more non-aligned zones. For example, the mapping table accelerator 611 may identify a logical address within the one or more non-aligned zones and mark the logical address as an invalid logical address in the L2P mapping table 612. The mapping table accelerator 611 may generate a response 617 after updating the L2P mapping table 612 based on the one or more non-aligned zones (e.g., after one or more non-aligned zones are deallocated).

[0079] If the set of deallocation zones includes one or more alignment zones, the deallocation accelerator 610 may update the DSM bitmap based on the one or more alignment zones. For example, for each alignment zone, the deallocation accelerator 610 may identify a logical zone of the non-volatile memory device 604 that corresponds to the alignment zone and update the bit corresponding to that logical zone in the DSM bitmap to have a second value (e.g., “1”). The mapping table accelerator 611 may generate a response 617 in response to updating the DSM bitmap. The mapping table accelerator 611 may then further update the L2P mapping table based on the DSM bitmap to actually deallocate the one or more alignment zones from the logical space of the non-volatile memory device 604. That is, the response 617 may be sent to the host after updating the DSM bitmap but before updating the L2P mapping table 612 based on the one or more alignment zones (e.g., before the actual deallocation of the one or more alignment zones from the logical space of the non-volatile memory device 604). It should be noted that updating the L2P mapping table 612 based on one alignment zone may take approximately 0.5 us, while updating the DSM bitmap for one alignment zone (e.g., setting one bit in the DSM bitmap corresponding to the alignment zone to the second value "1") only takes approximately 2 ns. Thus, the response time to a DSM command can be shortened if the response 617 is generated and sent to the host after updating the DSM bitmap but before updating the L2P mapping table 612 based on one or more alignment zones.

[0080] If the set of deallocated zones includes both non-aligned zones and aligned zones, deallocation accelerator 610 may update the DSM bitmap based on the aligned zones. Mapping table accelerator 611 may update L2P mapping table 612 based on the non-aligned zones and deallocate the non-aligned zones from the logical space of non-volatile memory device 604. Mapping table accelerator 611 may generate a response 617 in response to both (1) the update of the DSM bitmap by deallocation accelerator 610 and (2) the update of L2P mapping table 612 based on the non-aligned zones. Mapping table accelerator 611 may forward response 617 to host interface 618 and cause host interface 618 to send response 617 to the host. Furthermore, mapping table accelerator 611 may update L2P mapping table 612 based on the DSM bitmap so that the aligned zones can be deallocated from the logical space of non-volatile memory device 604 in the background after response 617 is sent. Thus, response time to DSM commands can be reduced because response 617 is generated and sent to the host after (1) updating the DSM bitmap and (2) updating L2P mapping table 612 based on non-aligned zones, but before updating L2P mapping table 612 based on aligned zones.

[0081] 8A illustrates an example of updating a DSM bitmap according to some aspects of the present disclosure. In some implementations, the logical space of a non-volatile memory device may be divided into multiple logical zones (e.g., logical zones 0, 1, 2, ..., M), where M is a positive integer. A DSM bitmap may be generated for multiple logical zones, with each bit corresponding to a respective one of the logical zones that will have a first value of "0."

[0082] As shown in Figure 8A, logical range 802 is to be deallocated from the logical space of the non-volatile memory device. Because logical range 802 is within (e.g., smaller than) a first logical zone (e.g., logical zone 0) of multiple logical zones, logical range 802 does not need to be divided and is classified as a non-aligned zone. Because the L2P mapping table can be directly updated based on the non-aligned zone, the DSM bitmap in Figure 8A does not need to be updated for the non-aligned zone.

[0083] Another logical range 804 is also to be deallocated from the logical space of the non-volatile memory device. The logical range 804 may be divided into four deallocated zones to match the zoning of the logical space of the non-volatile memory device. The four deallocated zones are classified into two non-aligned zones 806, 808 and two aligned zones 810, 812. For example, the non-aligned zone 806 is within a second logical zone (e.g., logical zone 1) of the plurality of logical zones. The aligned zone 810 is identical to a third logical zone (e.g., logical zone 2) of the plurality of logical zones. The aligned zone 812 is identical to a fourth logical zone (e.g., logical zone 3) of the plurality of logical zones. The non-aligned zone 808 is within a fifth logical zone (e.g., logical zone 4) of the plurality of logical zones. The DSM bitmap may be updated based on the aligned zones 810, 812. For example, bit 813 corresponding to alignment zone 810 (equivalently logical zone 2) may be set to have a second value of "1", and bit 814 corresponding to alignment zone 812 (equivalently logical zone 3) may be set to have a second value of "1".

[0084] 8B shows another example of updating a DSM bitmap according to some aspects of the present disclosure. Similar to FIG. 8A, the logical space of a non-volatile memory device may be divided into multiple logical zones (e.g., logical zones 0, 1, 2, ..., M). A DSM bitmap is generated for the multiple logical zones, with each bit corresponding to a respective one of the logical zones that will have a first value of "0."

[0085] The logical range 820 is to be deallocated from the logical space of the non-volatile memory device. The logical range 820 may be divided into two deallocated zones to match the zoning of the logical space of the non-volatile memory device. The two deallocated zones are classified into two non-aligned zones 822, 824. The non-aligned zone 822 is within a first logical zone (e.g., logical zone 0) of the multiple logical zones, and the non-aligned zone 824 is within a second logical zone (e.g., logical zone 1) of the multiple logical zones. The DSM bitmap does not need to be updated for the non-aligned zones 822, 824 because the L2P mapping table can be updated directly based on the non-aligned zones 822, 824.

[0086] Another logical range 830 is also to be deallocated from the logical space of the non-volatile memory device. The logical range 830 may be divided into two deallocated zones to match the zoning of the logical space of the non-volatile memory device. The two deallocated zones are classified into two aligned zones 832, 834. For example, the aligned zone 832 is identical to a third logical zone (e.g., logical zone 2) of the plurality of logical zones. The aligned zone 834 is identical to a fourth logical zone (e.g., logical zone 3) of the plurality of logical zones. The DSM bitmap may be updated based on the aligned zones 832, 834. For example, the bit 835 corresponding to the aligned zone 832 (equivalently, logical zone 2) may be set to have a second value of “1,” and the bit 836 corresponding to the aligned zone 834 (equivalently, logical zone 3) may be set to have a second value of “1.”

[0087] 9 illustrates a flowchart of a method 900 for operating a memory controller according to some aspects of the present disclosure. The memory controller may be any suitable memory controller disclosed herein, such as memory controller 601. It is understood that the operations illustrated in method 900 may not be exhaustive, and that other operations may be performed before, after, or between any of the operations illustrated. Additionally, some of the operations may be performed simultaneously or in a different order than that illustrated in FIG. 9.

[0088] 9, method 900 begins at operation 902, where a deallocated logical range (e.g., a logical range to be deallocated from the logical space of a non-volatile memory device) is divided into a set of deallocated zones. The deallocated zones include one or more first deallocated zones, which are each classified into one or more alignment zones. For example, data classification accelerator 608 may divide the logical range into a set of deallocated zones, which may include one or more alignment zones.

[0089] 9, method 900 proceeds to operation 904, where the DSM bitmap is updated based on one or more alignment zones. For example, deallocation accelerator 610 may update the DSM bitmap based on one or more alignment zones.

[0090] 9, method 900 proceeds to operation 906, where a response indicating that the deallocated logical range is to be processed is generated in response to updating the DSM bitmap. For example, mapping table accelerator 611 may generate a response indicating that the deallocated logical range is to be deallocated from the logical space of the non-volatile memory device in response to updating the DSM bitmap.

[0091] 9, the method 900 proceeds to operation 908, where the response is sent to the host. For example, the mapping table accelerator 611 may forward the response to the host interface 618 and cause the host interface 618 to send the response to the host.

[0092] 10 illustrates a flowchart of another method 1000 for operating a memory controller in accordance with some aspects of the present disclosure. The memory controller may be any suitable memory controller disclosed herein, such as memory controller 601. It is understood that the operations illustrated in method 1000 may not be exhaustive, and that other operations may be performed before, after, or between any of the illustrated operations. Furthermore, some of the operations may be performed simultaneously or in a different order than that illustrated in FIG. 10.

[0093] Referring to FIG. 10, method 1000 begins at operation 1002, where a DSM command is received indicating a logical range to be deallocated.

[0094] As shown in FIG. 10 , method 1000 proceeds to operation 1004, where the logical range is divided into a set of deallocated zones including (1) one or more first deallocated zones that are classified into one or more aligned zones, and (2) one or more second deallocated zones that are classified into one or more non-aligned zones.

[0095] As shown in FIG. 10, the method 1000 proceeds to operation 1006, where the DSM bitmap is updated based on the one or more alignment zones.

[0096] As shown in FIG. 10, the method 1000 proceeds to operation 1008, where the L2P mapping table is updated based on the one or more non-aligned zones.

[0097] 10, method 1000 proceeds to operation 1010, where a response to the DSM command is generated. For example, the response may be generated in response to both updating the L2P mapping table based on one or more non-aligned zones and updating the DSM bitmap. The response may be sent to the host.

[0098] 10, method 1000 proceeds to operation 1012, where the L2P mapping table is updated based on the DSM bitmap. It will be understood that operation 1012 may be performed before or after operation 1010, and this is not a limitation herein. In some implementations, operation 1012 may be performed in the background after the response is sent to the host.

[0099] In various aspects of the present disclosure, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as instructions on a non-transitory computer-readable medium. Computer-readable media include computer storage media. The storage medium may be any available medium that can be accessed by a memory controller, such as memory controller 601 of FIG. 6. By way of example and not limitation, such computer-readable media may include RAM, ROM, Electrically Erasable Programmable ROM (EEPROM), Compact Disc Read-Only Memory (CD-ROM) or other optical disk storage, hard disk drives (HDDs) such as magnetic disk storage or other magnetic storage devices, flash drives, SSDs, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a processing system, such as a mobile device or a computer. As used herein, disk and disc include CDs, laser discs, optical discs, digital video discs (DVDs), and floppy disks, where disks typically reproduce data magnetically and discs reproduce data optically with a laser. Combinations of the above should also be included within the scope of computer-readable media.

[0100] The foregoing description of specific implementations may be readily modified and / or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

[0101] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.

[0102] While specific configurations and ranges are discussed, it should be understood that this is done for illustrative purposes only. Accordingly, other configurations and arrangements may be used without departing from the scope of the present disclosure. The subject matter as described in this disclosure may also be used in a variety of other applications. The functional and structural features as described in this disclosure may be combined, adjusted, modified, and rearranged in a manner consistent with each other and with the scope of the present disclosure. [Explanation of symbols]

[0103] 100 systems 102 Memory System 104 Memory Devices 106 Memory Controller 108 Host 202 Memory Card 204 memory card connector 206 SSD 208 SSD connector 300 Memory Controller 302 Non-volatile memory 304 DRAM 306 Host 308 Processing Unit 310 Cache 311 ROM 312 Non-volatile Memory Interface 314 DRAM interface 316 Host Interface 400 NAND flash memory devices 401 Memory Cell Array 402 Peripheral Circuit 404 Block 406 memory cells 408 Memory String 410 SSG transistor 412 DSG transistor 413 DSG line 414 Source Line 415 SSG Line 416 bit lines 418 Word Line 420 physical pages 500 DRAM devices 501 memory cell array 502 Peripheral Circuit 503 memory cells 504 Word Line 505 Transistor 506 bit lines 507 Capacitor 600 Memory System 601 Memory Controller 602 Volatile Memory Devices 604 NV memory device 606 Cache 608 Data Classification Accelerator 610 Deallocation Accelerator 611 Mapping Table Accelerator 612 L2P Mapping Table 616 physical address 617 Responses 618 Host Interface 620 Volatile Memory Interface 622 NV memory interface 702 physical address 706 Value 802 Logical Range 804 Logical Range 806 Unaligned Zone 808 Unaligned Zone 810 Alignment Zone 812 Alignment Zone 813 bits 814 bits 820 Logical Range 822 Unaligned Zone 824 Unaligned Zone 830 Logical Range 832 Alignment Zone 834 Alignment Zone 835 bits 836 bits

Claims

1. a data sorting accelerator configured to divide the deallocated logical range into a set of deallocated zones, the set of deallocated zones comprising one or more first deallocated zones each sorted into one or more alignment zones; a deallocation accelerator operatively coupled to the data classification accelerator and configured to update a dataset management (DSM) bitmap based on the one or more alignment zones; operatively coupled to the data classification accelerator and the deallocation accelerator; generating a response in response to the updating of the DSM bitmap indicating that the deallocated logical range is to be processed; A mapping table accelerator configured as follows: A memory controller comprising:

2. 2. The memory controller of claim 1, wherein the mapping table accelerator is further configured to update a logical-to-physical (L2P) mapping table based on the DSM bitmap.

3. the mapping table accelerator for updating the L2P mapping table based on the DSM bitmap; identifying the one or more alignment zones from the DSM bitmap; updating the L2P mapping table based on the one or more alignment zones; The memory controller of claim 2 , further configured to:

4. to update the L2P mapping table based on the one or more alignment zones, the mapping table accelerator identifying a first list of logical addresses within the one or more alignment zones; invalidating the first list of logical addresses in the L2P mapping table; The memory controller of claim 3 , further configured to:

5. the set of deallocated zones further comprising one or more second deallocated zones each classified as one or more non-aligned zones; the mapping table accelerator: updating the L2P mapping based on the one or more non-alignment zones; generating the response responsive to both the update of the DSM bitmap and the update of the L2P mapping table based on the one or more non-aligned zones; The memory controller of claim 2 , further configured to:

6. to update the L2P mapping table based on the one or more unaligned zones, the mapping table accelerator identifying a second list of logical addresses within the one or more unaligned zones; invalidating the second list of logical addresses in the L2P mapping table; The memory controller of claim 5 , further configured to:

7. 7. The memory controller of claim 5, wherein the data classification accelerator is configured to divide the deallocated logical ranges into the set of deallocated zones based on a zoning of the logical space of the non-volatile memory device coupled to the memory controller, such that the division of the deallocated logical ranges matches a zoning of the logical space of the non-volatile memory device.

8. The logical space of the non-volatile memory device is divided into a plurality of logical zones; the one or more first deallocated zones are equal to the one or more first logical zones from the plurality of logical zones, respectively, such that the one or more first deallocated zones are grouped into the one or more aligned zones that are aligned with the one or more first logical zones from the plurality of logical zones, respectively; 8. The memory controller of claim 7, wherein the one or more second deallocated zones are smaller than the one or more second logical zones from the plurality of logical zones, respectively, such that the one or more second deallocated zones are classified into the one or more unaligned zones that are not aligned with the one or more second logical zones from the plurality of logical zones, respectively.

9. 9. The memory controller of claim 7, wherein the non-volatile memory device comprises a NAND flash memory.

10. a non-volatile memory device; a memory controller operably coupled to the non-volatile memory device and configured to control the non-volatile memory device, the memory controller comprising: a data sorting accelerator configured to divide the deallocated logical range into a set of deallocated zones, the set of deallocated zones comprising one or more first deallocated zones each sorted into one or more alignment zones; a deallocation accelerator operatively coupled to the data classification accelerator and configured to update a dataset management (DSM) bitmap based on the one or more alignment zones; operatively coupled to the data classification accelerator and the deallocation accelerator; generating a response in response to the updating of the DSM bitmap indicating that the deallocated logical range is to be processed; A mapping table accelerator configured as follows: A memory system comprising:

11. 11. The memory system of claim 10, wherein the mapping table accelerator is further configured to update a logical-to-physical (L2P) mapping table based on the DSM bitmap.

12. the mapping table accelerator for updating the L2P mapping table based on the DSM bitmap; identifying the one or more alignment zones from the DSM bitmap; updating the L2P mapping table based on the one or more alignment zones; The memory system of claim 11 further configured to:

13. to update the L2P mapping table based on the one or more alignment zones, the mapping table accelerator identifying a first list of logical addresses within the one or more alignment zones; invalidating the first list of logical addresses in the L2P mapping table; The memory system of claim 12 further configured to:

14. the set of deallocated zones further comprising one or more second deallocated zones each classified with one or more non-aligned zones; the mapping table accelerator: updating the L2P mapping table based on the one or more non-alignment zones; generating the response responsive to both the update of the DSM bitmap and the update of the L2P mapping table based on the one or more non-aligned zones; 14. The memory system of claim 11, further configured to:

15. to update the L2P mapping table based on the one or more unaligned zones, the mapping table accelerator identifying a second list of logical addresses within the one or more unaligned zones; invalidating the second list of logical addresses in the L2P mapping table; 15. The memory system of claim 14, further configured to:

16. 16. The memory system of claim 14, wherein the data classification accelerator is configured to divide the deallocated logical ranges into the set of deallocated zones based on a zoning of the logical space of the non-volatile memory device coupled to the memory controller, such that the division of the deallocated logical ranges matches a zoning of the logical space of a non-volatile memory device.

17. The logical space of the non-volatile memory device is divided into a plurality of logical zones; the one or more first deallocated zones are equal to the one or more first logical zones from the plurality of logical zones, respectively, such that the one or more first deallocated zones are grouped into the one or more aligned zones that are aligned with the one or more first logical zones from the plurality of logical zones, respectively; 17. The memory system of claim 16, wherein the one or more second deallocated zones are smaller than the one or more second logical zones from the plurality of logical zones, respectively, such that the one or more second deallocated zones are classified into the one or more unaligned zones that are not aligned with the one or more second logical zones from the plurality of logical zones, respectively.

18. 18. The memory system of claim 16 or 17, wherein the non-volatile memory device comprises a NAND flash memory.

19. 1. A method for operating a memory controller, comprising: dividing the deallocated logical range into a set of deallocated zones, said set of deallocated zones comprising one or more first deallocated zones each grouped into one or more alignment zones; updating a dataset management (DSM) bitmap based on the one or more alignment zones; generating a response in response to the updating of the DSM bitmap indicating that the deallocated logical range is to be processed; A method comprising:

20. 20. The method of claim 19, further comprising updating a logical-to-physical (L2P) mapping table based on the DSM bitmap.

21. updating the L2P mapping table based on the DSM bitmap, identifying the one or more alignment zones from the DSM bitmap; updating the L2P mapping table based on the one or more alignment zones; 21. The method of claim 20, comprising:

22. updating the L2P mapping table based on the one or more alignment zones, identifying a first list of logical addresses within the one or more alignment zones; invalidating the first list of logical addresses in the L2P mapping table; 22. The method of claim 21, comprising:

23. the set of deallocated zones further comprising one or more second deallocated zones each classified with one or more non-aligned zones; The method comprises: updating the L2P mapping table based on the one or more non-alignment zones; generating the response responsive to both the update of the DSM bitmap and the update of the L2P mapping table based on the one or more non-aligned zones; 23. The method of any one of claims 20 to 22, further comprising:

24. updating the L2P mapping table based on the one or more non-alignment zones, identifying a second list of logical addresses within the one or more unaligned zones; invalidating the second list of logical addresses in the L2P mapping table; 24. The method of claim 23, comprising:

25. dividing the deallocated logical range into the set of deallocated zones, 25. The method of claim 23 or 24, comprising dividing the deallocated logical range into the set of deallocated zones based on a zoning of the logical space of the non-volatile memory device coupled to the memory controller, such that the division of the deallocated logical ranges matches the zoning of the logical space of the non-volatile memory device.

26. The logical space of the non-volatile memory device is divided into a plurality of logical zones; the one or more first deallocated zones are equal to the one or more first logical zones from the plurality of logical zones, respectively, such that the one or more first deallocated zones are grouped into the one or more aligned zones that are aligned with the one or more first logical zones from the plurality of logical zones, respectively; 26. The method of claim 25, wherein the one or more second deallocated zones are smaller than the one or more second logical zones from the plurality of logical zones, respectively, such that the one or more second deallocated zones are classified into the one or more unaligned zones that are not aligned with the one or more second logical zones from the plurality of logical zones, respectively.

27. 27. The method of claim 25 or 26, wherein the non-volatile memory device comprises a NAND flash memory.

28. 1. A non-transitory computer-readable storage medium storing instructions that, when executed by a memory controller of a memory system, cause the memory controller to: dividing the deallocated logical range into a set of deallocated zones, said set of deallocated zones comprising one or more first deallocated zones each grouped into one or more alignment zones; updating a dataset management (DSM) bitmap based on the one or more alignment zones; generating a response in response to the updating of the DSM bitmap indicating that the deallocated logical range is to be processed; A non-transitory computer-readable storage medium for performing a method comprising:

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