System and method for implementing optimized rate recovery and HARQ combining in a network - Patents.com

Abstract

A system and method for implementing optimized rate recovery and HARQ combining within a network is provided. The present disclosure provides a system and method for implementing rate recovery in the PUSCH and PDCH bit rate processing chains of a network. The system packs log-likelihood ratio (LLR) data equalized for each phase and quadrature (IQ) symbol such that a predetermined number of LLRs are packed, equal to the modulation order. The system deinterleaves the packed LLRs by reading most significant bit (MSB) LLRs row by row, for a number of columns equal to the modulation order. The system uses a single buffer for the deinterleaving, bit deselection, and filler bit addition stages, thereby reducing the system's memory requirements. To optimize memory and reduce latency, the system processes only a predetermined number of LLRs for the HARQ combining stage.

Description

[Technical Field]

[0001] Reservation of Rights Portions of the disclosure of this patent document contain material that is subject to intellectual property rights owned by Jio Platforms Limited (JPL) or its affiliates (collectively, the Patent Holder), including, but not limited to, copyright, design, trademark, integrated circuit (IC) layout design, and / or trade dress protection. The Patent Holder does not object to the reproduction by any third party of the patent document or the patent disclosure as contained in the Patent and Trademark Office patent file or records, but otherwise reserves all rights. All rights to such intellectual property are fully reserved by the Patent Holder.

[0002] FIELD Embodiments of the present disclosure relate generally to systems and methods for wireless communication systems. More particularly, the present disclosure relates to systems and methods for implementing rate recovery and hybrid automatic repeat request (HARQ) combining in a network. [Background technology]

[0003] The following description of related art is intended to provide background information related to the field of the present disclosure. This section may include specific aspects of technology that may be related to various aspects of the present disclosure. However, this section is intended solely to enhance the reader's understanding of the present disclosure and is not an admission of prior art.

[0004] Rate matching at the transmitter side is responsible for bit selection and bit interleaving of low-density parity-check (LDPC)-encoded code blocks. The physical layer performs base graph selection for LDPC channel coding. This selection is necessary before the channel coding itself, because the base graph selection determines the maximum code block size, which affects the code block segmentation requirements. The maximum code block size is the maximum number of bits that the LDPC channel encoder can accept. Data blocks larger than this upper limit must be segmented before channel coding. Channel coding is then applied to each code block segment separately. Limiting the code block size processed by the channel coding algorithm helps limit the encoding complexity at the user equipment (UE). The base graph selection uses a combination of coding rate and transport block size thresholds. The output from the LDPC channel encoder is forwarded to the rate matching function.

[0005] The rate matching function processes each code block independently. Rate matching is completed in two stages: bit selection and bit interleaving. The bit selection process reduces or repeats the number of channel coding bits to fit the capacity of the allocated air interface resources. Bit selection extracts "E" bits from the LDPC-encoded code block bit stream in a circular buffer of size N. The size of the circular buffer may also depend on the UE capabilities. Limited buffer rate matching (LBRM) is a feature to accommodate devices with limited capacity for buffering large code blocks. In the bit interleaving stage, the stream of bits is read into a table row by row, and then read from the table column by column. The number of rows belonging to the table is set to be equal to the modulation order.

[0006] On the receive side, the rate recovery and HARQ combining stages of the 5G New Radio Physical Downlink Shared Channel (PDSCH) and Physical Uplink Shared Channel (PUSCH) receive chains are responsible for performing the inverse operation of rate matching at the transmit side. These require buffering soft bits (called log-likelihood ratios, or LLRs) in memory for separate substages: deinterleaving, deselection, and incremental redundancy-based hybrid automatic repeat request (Hybrid ARQ or HARQ). Each LLR is typically represented in n-bit fixed-point format, so the memory requirement for processing G LLRs at any substage is nG bits. Therefore, compared to the transmitter, each reciprocal stage at the receiver requires n times more memory. Memory is a scarce resource in systems such as field-programmable gate arrays (FPGAs), eASICs, and digital signal processor (DSP) chipsets, so it must be allocated wisely.

[0007] Therefore, there is a need in the art to provide a system and method that can alleviate the problems associated with the prior art. Object of the invention

[0008] Some of the objectives of the present disclosure that are met by at least one embodiment herein are listed below.

[0009] An object of the present disclosure is to provide a system and method that uses an optimized rate recovery and hybrid automatic repeat request (HARQ) combining method for physical downlink shared channel (PDSCH) and physical uplink shared channel (PUSCH) receiver bit rate processing chains.

[0010] The objective of this disclosure is to use a single buffer for all three rate recovery sub-stages: deinterleaving, bit deselection, and filler bit addition stages.

[0011] An objective of the present disclosure is to provide a system and method for deinterleaving LLRs received from a descrambler of a rate recovery module by storing packed LLRs row-by-row in a buffer and reading out most significant bit (MSB) LLRs across all rows until a limited number of LLR columns have been read out.

[0012] An object of the present disclosure is to provide a system and method that reduces latency and power consumption by using only a finite "length" number of LLRs during the HARQ combining stage instead of the full "N" number of LLRs.

[0013] An object of the present disclosure is to provide a system and method in which the data length number of an LLR is based on a starting offset that is based on the base graph and redundancy version (RV) index used for a particular code block. Summary of the Invention [Means for solving the problem]

[0014] Some of the objectives of the present disclosure that are met by at least one embodiment herein are listed below: This summary is not intended to identify key features or the scope of the claimed subject matter.

[0015] In one aspect, the present disclosure relates to a system for optimizing memory utilization during decoding of uplink data at a base station. The system includes a processor and a memory operatively coupled to the processor, the memory storing instructions executed by the processor. The processor receives a request from a computing device associated with one or more users. The input is based on one or more Orthogonal Frequency Division Multiplexing (OFDM) subcarriers transmitted by the computing device over a Physical Uplink Shared Channel (PUSCH). The processor determines in-phase and quadrature (IQ) data symbols associated with the one or more OFDM subcarriers. The processor generates one or more log-likelihood ratios (LLRs) based on the one or more IQ data symbols. The processor optimizes memory utilization by utilizing a predetermined number of LLR data bits associated with one or more LLR data bits for each of the one or more IQ data symbols.

[0016] In one embodiment, the predetermined number of LLR data bits may be determined based on a starting offset derived from a low-density parity-check (LDPC) base graph and a redundancy version (RV) index associated with the PUSCH processing.

[0017] In one embodiment, the processor may generate a rate recovery output based on one or more LLR data bits.

[0018] In one embodiment, the processor may generate the rate recovery output by buffering the LLR data bits row by row and streaming out the most significant bit (MSB) LLR data bits across all rows until a limited number of LLR data bit sequences have been streamed, where the limited number of LLR data bit sequences may be based on the modulation order of one or more IQ data symbols.

[0019] In one aspect, the present disclosure relates to a method for optimizing memory utilization during decoding of uplink data at a base station. The method includes receiving, by a processor associated with a system, a request from a computing device associated with one or more users. The input is based on one or more OFDM subcarriers transmitted by the computing device via a PUSCH. The method includes determining, by the processor, one or more IQ data symbols associated with the one or more OFDM subcarriers. The method includes generating, by the processor, one or more LLR data bits based on the one or more IQ data symbols. The method includes optimizing memory utilization by utilizing, by the processor, a predetermined number of LLR data bits associated with the one or more LLR data bits for each of the one or more IQ data symbols.

[0020] In one embodiment, the predetermined number of LLR data bits is based on a starting offset derived from the LDPC base graph and an RV index associated with the PUSCH processing.

[0021] In one embodiment, the method may include generating, by a processor, a rate recovery output based on the one or more LLR data bits.

[0022] In one embodiment, the method may include generating, by a processor, a rate recovery output by buffering LLR data bits row by row and streaming out MSBLLR data bits across all rows until a limited number of LLR data bit sequences have been streamed, where the limited number of LLR data bit sequences may be based on a modulation order of one or more IQ data symbols.

[0023] In one aspect, a non-transitory computer-readable medium comprises a processor with executable instructions, the executable instructions causing the processor to perform steps of receiving a signal from an NR PHY with OFDM. The input is based on one or more OFDM subcarriers transmitted by the computing device via a PUSCH. The processor determines one or more IQ data symbols associated with the one or more OFDM subcarriers. The processor generates one or more LLR data bits based on the one or more IQ data symbols. The processor utilizes a predetermined number of LLR data bits associated with the one or more LLR data bits for each of the one or more IQ data symbols to optimize memory utilization.

[0024] In one aspect, the present disclosure relates to a user equipment (UE). The system includes a processor and a memory operatively coupled to the processor, the memory storing instructions executed by the processor. The processor receives a request from a computing device associated with one or more users. The input is based on one or more OFDM subcarriers received by the computing device via a physical downlink shared channel (PDSCH). The processor determines one or more IQ data symbols associated with the one or more OFDM subcarriers. The processor generates one or more LLRs based on the one or more IQ data symbols. The processor optimizes memory utilization by utilizing a predetermined number of LLR data bits associated with one or more LLR data bits for each of the one or more IQ data symbols.

[0025] In one embodiment, the predetermined number of LLR data bits is based on a starting offset derived from the LDPC base graph and an RV index associated with the PDSCH processing.

[0026] In one embodiment, the processor may generate a rate recovery output based on one or more LLR data bits.

[0027] In one embodiment, the processor may generate the rate recovery output by buffering the LLR data bits row by row and streaming out the MSBLLR data bits across all rows until a limited number of LLR data bit sequences have been streamed, where the limited number of LLR data bit sequences may be based on the modulation order of one or more IQ data symbols.

[0028] In one aspect, the present disclosure relates to a method for optimizing memory utilization during decoding of downlink data at a UE. The method includes receiving, by a processor associated with a system, a request from a computing device associated with one or more users. The input is based on one or more OFDM subcarriers received by the UE via a PDSCH. The method includes determining, by the processor, one or more IQ data symbols associated with the one or more OFDM subcarriers. The method includes generating, by the processor, one or more LLR data bits based on the one or more IQ data symbols. The method includes optimizing memory utilization by utilizing, by the processor, a predetermined number of LLR data bits associated with the one or more LLR data bits for each of the one or more IQ data symbols. [Brief explanation of the drawings]

[0029] The accompanying drawings, which are incorporated herein and constitute a part of this disclosure, illustrate exemplary embodiments of the disclosed methods and systems, with like reference numerals referring to like parts between the different drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the disclosure. Some drawings use block diagrams to illustrate components and may not depict the internal circuitry of each component. Those skilled in the art will appreciate that the disclosure of such drawings includes disclosure of electrical or electronic components or circuits commonly used to implement such components. [Figure 1] 1 illustrates an exemplary network architecture (100) for implementing the proposed system (108) according to an embodiment of the present disclosure. [Figure 2] 1 shows an exemplary block diagram (200) of a proposed system (108) according to an embodiment of the present disclosure. [Figure 3] 3 illustrates an exemplary block diagram (300) of base graph selection during channel encoding according to one embodiment of the present disclosure. [Figure 4] 4 shows a block diagram of an example bit selection process (400) according to one embodiment of the present disclosure. [Figure 5] 5 illustrates an example architecture diagram (500) of bit rate processing in a Physical Uplink Shared Channel (PUSCH) receiver incorporating optimized rate recovery and Hybrid Automatic Repeat Request (HARQ) combining, according to an embodiment of the present disclosure. [Figure 6] 4 illustrates an example block diagram (400) of a bit selection process for a PUSCH receiver incorporating optimized rate recovery and HARQ combining in accordance with an embodiment of the present disclosure. [Figure 7] 1 shows an exemplary block diagram (200) of a proposed system (108) according to an embodiment of the present disclosure. [Figure 8]An exemplary computer system 400 is shown, and an embodiment of the present disclosure can be implemented in or by the computer system 400. The foregoing will become more apparent from the more detailed description of the disclosure below. DETAILED DESCRIPTION OF THE INVENTION

[0030] For purposes of explanation, numerous specific details are set forth below to provide a thorough understanding of embodiments of the present disclosure. However, it will be apparent that embodiments of the present disclosure may be practiced without these specific details. Some of the features described below may be used independently or in combination with other features. Individual features may not address all of the problems described above, or may only address some of the problems described above. Some of the aforementioned challenges may not be completely resolved by any of the features described below.

[0031] The following description provides exemplary embodiments only and is not intended to limit the scope, applicability, or configuration of the present disclosure. Rather, it is intended to provide those skilled in the art with a useful description for implementing exemplary embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the spirit and scope of the disclosure as described.

[0032] In the following description, specific details are provided to provide a thorough understanding of the embodiments. However, it will be understood by those skilled in the art that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form so as not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail so as not to obscure the embodiments.

[0033] It should be noted that particular embodiments may be described as a process that is depicted as a flowchart, flow diagram, data flow diagram, structure diagram, or block diagram. While a flowchart describes operations as a sequential process, many of the operations may be performed in parallel or simultaneously. Also, the order of operations may be changed. A process terminates when the operations are completed, but there may be additional steps not included in the diagram. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process refers to a function, its termination refers to the return of the function to the calling function or the main function.

[0034] As used herein, the words "exemplary" and / or "demonstrative" mean an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. Moreover, any aspect or design described herein as "exemplary" and / or "demonstrative" should not necessarily be construed as preferred or advantageous over other aspects or designs, nor is it intended to exclude equivalent exemplary structures and techniques known to those skilled in the art. Furthermore, to the extent that the terms "includes," "has," "contains," and other similar words are used in either the detailed description or the claims, such terms are intended to be inclusive in the same manner as the open conjunction "comprising," without excluding additional or other elements.

[0035] References throughout this specification to "one embodiment" or "embodiment" or "instance" or "one instance" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0036] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context indicates otherwise. Furthermore, as used herein, the terms "comprises" and / or "comprising" specify the presence of stated features, integers, steps, operations, elements, and / or components, but are understood not to exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0037] Various embodiments throughout this disclosure are described in more detail with reference to FIGS.

[0038] FIG. 1 illustrates an exemplary network architecture (100) for implementing the proposed system (108) according to an embodiment of the present disclosure.

[0039] As shown in FIG. 1 , the network architecture 100 may include a system 108. The system 108 may be connected to one or more computing devices 104-1, 104-2, ... 104-N via a network 106. The one or more computing devices 104-1, 104-2, ... 104-N may be interchangeably designated as user equipment (UE) 104 and operated by one or more users 102-1, 102-2, ... 102-N. Furthermore, the one or more users 102-1, 102-2, ... 102-N may be interchangeably referred to as users 102 or users 102. In one embodiment, the computing devices 104 may be connected to a base station 110 via the network 106. Furthermore, the system 108 may be connected to the base station 110.

[0040] In one embodiment, the computing device (104) may include, but is not limited to, a mobile device, a laptop, etc. Furthermore, the computing device (104) may include a smartphone, a virtual reality (VR) device, an augmented reality (AR) device, a general-purpose computer, a desktop, a personal digital assistant, a tablet computer, and a mainframe computer. Furthermore, an input device for receiving input from the user (102), such as a touchpad, a touch-enabled screen, or an electronic pen, may be used. Those skilled in the art will understand that the computing device (104) is not limited to the aforementioned devices, and various other devices may be used.

[0041] In one embodiment, the network (106) may include, by way of example and not limitation, at least a portion of one or more networks having one or more nodes that transmit, receive, forward, generate, buffer, store, route, switch, process, or combinations thereof, one or more messages, packets, signals, waves, voltage or current levels, combinations thereof, etc. The network (106) may include, but is not limited to, one or more of a wireless network, a wired network, the Internet, an intranet, a public network, a private network, a packet-switched network, a circuit-switched network, an ad-hoc network, an infrastructure network, a public switched telephone network (PSTN), a cable network, a cellular network, a satellite network, a fiber optic network, or combinations thereof.

[0042] In one embodiment, the computing device (104) may include a central processing unit (CPU) / digital signal processor (DSP) / field programmable gate array (FPGA) / electronic application specific integrated circuit (eASIC), or any silicon device with a PUSCH / PDSCH bit rate processing (BRP) receiver chain.

[0043] In one embodiment, the system 108 may receive a request from a computing device 104 associated with one or more users 102. The input may be based on one or more orthogonal frequency division multiplexing (OFDM) subcarriers transmitted by the computing device 104 over a physical uplink shared channel (PUSCH).

[0044] In one embodiment, the system 108 may generate a rate recovery output based on one or more LLR data bits. The system 108 may generate the rate recovery output by buffering the LLR data bits row by row and streaming out the most significant bit (MSB) LLR data bits across all rows until a limited number of LLR data bit sequences have been streamed, where the limited number of LLR data bit sequences may be based on modulation orders of one or more IQ data symbols.

[0045] In one embodiment, the system (108) may determine one or more in-phase quadrature (IQ) data symbols associated with one or more OFDM subcarriers.

[0046] In one embodiment, the system (108) may generate one or more log-likelihood ratio (LLR) data bits based on one or more IQ data symbols, where the predetermined number of LLR data bits is based on a starting offset derived from a low-density parity-check (LDPC) base graph and a redundancy version (RV) index associated with the PUSCH processing.

[0047] In one embodiment, the predetermined number of LLR data bits may be determined based on a starting offset derived from the LDPC base graph and an RV index associated with the PUSCH processing.

[0048] In one embodiment, the system 108 may receive requests from computing devices 104 associated with one or more users 102. The input may be based on one or more OFDM subcarriers transmitted by a base station 110 over a physical downlink shared channel (PDSCH).

[0049] In one embodiment, the system 108 may generate a rate recovery output based on one or more LLR data bits. The system 108 may generate the rate recovery output by buffering the LLR data bits row by row and streaming out the MSBLLR data bits across all rows until a limited number of LLR data bit sequences have been streamed, where the limited number of LLR data bit sequences may be based on a modulation order of one or more IQ data symbols.

[0050] In one embodiment, the system (108) may determine one or more in-phase quadrature (IQ) data symbols associated with one or more OFDM subcarriers.

[0051] In one embodiment, the system (108) may generate one or more LLR data bits based on one or more IQ data symbols.

[0052] In one embodiment, the system (108) may utilize only a predetermined number of LLR data bits associated with one or more LLR data bits for decoding at the UE (102). In one embodiment, the predetermined number of LLR data bits may be determined based on a starting offset derived from the LDPC base graph and an RV index associated with PDSCH processing.

[0053] Although Figure 1 illustrates exemplary components of network architecture (100), in other embodiments, network architecture (100) may have a different number, type, or arrangement of components than Figure 1, or may include additional functionality not present in Figure 1. Additionally or alternatively, functions described herein as being performed by one or more components of network architecture (100) may be performed by one or more other components of network architecture (100).

[0054] FIG. 2 illustrates an exemplary block diagram (200) of a proposed system (108) according to an embodiment of the present disclosure.

[0055] According to FIG. 2 , the system (108) may include one or more processor(s) (202), which may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, logic circuits, and / or any device that processes data based on operational instructions. Among other functions, the one or more processor(s) (202) may be configured to retrieve and execute computer-readable instructions stored in the memory (204) of the system (108). The memory (204) may be configured to store one or more computer-readable instructions or routines on a non-transitory computer-readable storage medium, which may be retrieved and executed to create or share data packets via a network service. The memory (204) may include any non-transitory storage device, including, for example, volatile memory, such as random access memory (RAM), or non-volatile memory, such as erasable programmable read-only memory (EPROM), flash memory, etc.

[0056] In one embodiment, the system 108 may include, but is not limited to, interface(s) 206. The interface(s) 206 may include various interfaces, such as for data input / output (I / O) devices and storage devices. The interface(s) 206 may also provide communication paths to one or more components of the system 108. Examples of such components include, but are not limited to, processing engine(s) 208 and databases 210, including, but not limited to, a data ingestion engine 212, a policy engine 214, and other engine(s) 216. In one embodiment, the other engine(s) 214 may include, but are not limited to, a data management engine, an input / output engine, a notification engine, and the like.

[0057] In one embodiment, the processing engine(s) (208) may be implemented as a combination of hardware and programming (e.g., programmable instructions) to implement one or more functions of the processing engine(s) (208). In the examples described herein, such a combination of hardware and programming may be implemented in several different ways. For example, the programming of the processing engine(s) (208) may be processor-executable instructions stored on a non-transitory machine-readable storage medium, and the hardware of the processing engine(s) (208) may include processing resources (e.g., one or more processors) for executing such instructions. In this example, the machine-readable storage medium may store instructions that, when executed by the processing resources, implement the processing engine(s) (208). In such an example, the system (108) may include a machine-readable storage medium that stores instructions and the processing resources for executing the instructions, or the machine-readable storage medium may be separate but accessible to the system (108) and the processing resources. In other examples, the processing engine(s) (208) may be implemented by electronic circuitry.

[0058] In one embodiment, the processor 202 may receive a request via the data ingestion engine 212. The request may be received from a computing device associated with one or more users 102. The processor 202 may store the request in the database 210. The input may be based on OFDM subcarriers transmitted via a PUSCH by the computing device 104.

[0059] In one embodiment, the processor (202) may generate a rate recovery output based on one or more LLR data bits. The processor (202) may generate the rate recovery output by buffering the LLR data bits row by row and streaming out the MSBLLR data bits across all rows until a limited number of LLR data bit sequences have been streamed, where the limited number of LLR data bit sequences may be based on the modulation order of one or more IQ data symbols.

[0060] In one embodiment, the processor (202) may determine one or more IQ data symbols associated with one or more OFDM subcarriers.

[0061] In one embodiment, the processor (202) may generate one or more LLR data bits based on one or more IQ data symbols.

[0062] In one embodiment, the processor (202) may utilize only a predetermined number of LLR data bits associated with one or more LLR data bits for each of one or more IQ data symbols for decoding at the base station. In one embodiment, the predetermined number of LLR data bits may be determined based on a starting offset derived from the LDPC base graph and an RV index associated with the PUSCH processing.

[0063] In one embodiment, the processor (202) may receive input via a data ingestion engine (212), which may be based on one or more OFDM subcarriers transmitted by the base station (110) via a physical downlink shared channel (PDSCH).

[0064] In one embodiment, the processor (202) may generate a rate recovery output based on one or more LLR data bits. The processor (202) may generate the rate recovery output by buffering the LLR data bits row by row and streaming out the MSBLLR data bits across all rows until a limited number of LLR data bit sequences have been streamed, where the limited number of LLR data bit sequences is based on the modulation order of the one or more IQ data symbols.

[0065] In one embodiment, the processor (202) may determine one or more IQ data symbols associated with one or more OFDM subcarriers.

[0066] In one embodiment, the processor (202) may generate one or more LLR data bits associated with the base station (110) based on one or more IQ data symbols. In one embodiment, the processor (202) may utilize only a predetermined number of LLR data bits associated with the one or more LLR data bits during decoding at the UE (102). The predetermined number of LLR data bits may be determined based on a starting offset derived from the LDPC base graph and an RV index associated with the PDSCH processing.

[0067] Although FIG. 2 illustrates components of system (108), in other embodiments, system (108) may have a different number, type, or arrangement of components than FIG. 2 or may include additional functionality not present in FIG. 2, including, but not limited to, functions described herein as being performed by one or more components of system (108) may also or alternatively be performed by one or more other components of system (108).

[0068] FIG. 3 illustrates an example block diagram (300) of base graph selection during channel encoding according to one embodiment of the present disclosure.

[0069] As shown in FIG. 3, channel coding may be applied to each segment separately. Limiting the code block size processed by the channel coding algorithm may limit the coding complexity at the UE (102). Base graph selection may use a combination of coding rate and transport block size thresholds. Base graph 2 may be selected if the target coding rate is less than 0.25, or if the transport block size is less than 292 bits, or if the transport block size is less than 3824 bits and the target coding rate is less than 0.67. Otherwise, base graph I may be selected. The output from the channel coding may be forwarded to a rate matching function. The rate matching function may process the coded segments of each channel separately. Rate matching may be completed by a bit selection process and a bit interleaving process. Filler bits may be added as the first stage to align the code block lengths according to the standard.

[0070] Furthermore, the bit selection process reduces or repeats the number of channel coding bits to fit the capacity of the allocated air interface resources. Bit selection extracts "E" bits from the LDPC encoded code block bit stream in a circular buffer of size N. The size of the circular buffer may also depend on the UE capabilities. Limited Buffer Rate Matching (LBRM) is a feature to accommodate devices with limited capacity for buffering large code blocks. FIG. 4 illustrates an example block diagram (400) of a bit selection process according to one embodiment of the present disclosure.

[0071] As shown in Figure 4, the bit selection process may use a specific starting position to extract a subset of bits from the circular buffer. The starting position may vary depending on the redundancy version (RV). The starting positions for RV0, RV1, and RV2 are 0, 25, and 50% of the circumference of the circular buffer. The starting position for RV3 is approximately 85% of the circumference of the circular buffer. The starting position of RV3 may be moved toward the starting position of RV0 to increase the number of systematic bits captured by the RV3 transmission. This approach may be employed to enable self-decoding when either RV0 or RV3 is transmitted; that is, the receiver can decode the original transport block after receiving only a single standalone transmission of RV0 or RV3. Self-decoding is not permitted for RVI and RV2. These RVs require another transmission using a different RV to enable decoding of the transport block.

[0072] Furthermore, once the set of bits is extracted from the circular buffer, bit interleaving may be applied, where the stream of bits may be read into a table row by row and then read from the table column by column, with the number of rows in the table set equal to the modulation order, and each column may correspond to a single modulation symbol.

[0073] FIG. 5 illustrates an example architecture diagram (500) of bit rate processing in a Physical Uplink Shared Channel (PUSCH) receiver with optimized rate recovery and Hybrid Automatic Repeat Request (HARQ) combining, in accordance with an embodiment of the present disclosure.

[0074] In one embodiment, the rate recovery and HARQ combining process in the PUSCH may require a large memory buffer to store and process input data. The maximum number of input data that needs to be processed depends on the resource allocation (nRE), the number of layers (n layers), and the modulation order (Qm). The maximum allowable channel bandwidths for FR1 and FR2 may include 100 MHz and 400 MHz for a single carrier, respectively. As an example, FR1 may include the maximum number of physical resource blocks (PRBs). In fifth-generation (5G) new radio (NR) systems, each domain slot may include 14 symbols. Furthermore, the standard also specifies the maximum number of resource elements (REs) per slot per PRB as 156. Therefore, a user provided with a full resource allocation will be allocated a maximum of 156 REs per PRB and 273 PRBs per slot, resulting in 42,588 REs per slot. Therefore, the number of LLRs (G) received at the input of the rate recovery module may be derived using the following equation: G = n layers * nRE * Qm * num codewords

[0075] In one embodiment, considering a system 108 with n layers <= 4 as an example, the number of codewords may be limited to 1. Therefore, the maximum value of G may correspond to n layers = 4, nRE = 42588, and Qm = 8 (8 bits per symbol using 256-QAM), which corresponds to 1,362,816 LLRs. Assuming each LLR is represented using an 8-bit fixed-point format, the maximum number of input bits received at the input of the rate recovery block may be 10,902,528 bits, which is approximately 10 gigabytes (GB).

[0076] In one embodiment, for incremental redundancy-based HARQ, the process of combining the output (N bits) from the previous transmission with the current retransmission input may depend on a start offset, which may vary based on the redundancy version (RV). To achieve this type of combining process in fewer processing cycles, the rate recovery block may stream the output taking into account the start offset.

[0077] Furthermore, embodiments may specify low-density parity check (LDPC) coding for the PUSCH. LDPC may be selected as an alternative to turbo coding, which is used for the PUSCH in 4G. LDPC channel coding may be characterized by a sparse parity check matrix. This means that the matrix used to generate the set of parity bits may contain a relatively small number of I's, meaning that the I's density is low. The low-density characteristic may help reduce both encoding and decoding complexity. Reduced complexity may also result in reduced power consumption and silicon area. The selected LDPC solution may be scalable to support a wide range of code block sizes and a wide range of coding rates. LDPC and turbo coding may provide similar performance in terms of error correction capabilities. The soft-combined code blocks may be fed to the LDPC decoder via an LDPC HARQ interconnection block. The LDPC HARQ interconnection block may ensure an additional 2Zc sample at the beginning of each code block, in accordance with the requirements of the Xilinx LDPC decoder. The decoded samples from the LDPC decoder may be cyclic redundancy check (CRC) checked by the CRC decoding block, and the final transport block along with the CRC status may be passed to a Functional Application Program Interface (FAPI) parser.

[0078] As shown in Figure 5, an embodiment may describe the implementation of an optimized rate recovery and HARQ combining method for a PUSCH bit rate processing chain on a Xilinx ZCU111 FPGA chip, in which the main memory component is a block random access memory (BRAM), and each 36 kilobyte (K) sized BRAM stores 36 kilobytes (Kb) of data.

[0079] In one embodiment, inputs may be received from various users (102) (user 0...user K). The inputs may be processed by a memory interface generator (MIG) controller (502) and an HRQ gateway (504). The PUSCH controller (506) may include various processes, such as PUSCH service redundancy protocol (SRP) processing by a user separation block (508), followed by soft decoding (510), descrambling (512), rate recovery (514), code block (CB) concatenation (516), HARQ combining (518), LDPCHARQ interconnection (520), decoding by an LDPC decoder (522), and CB de-segmentation (524). The output from the CB de-segmentation (524) may be provided to the PUSCH payload, and the CRC status may be provided to the HARQ gateway (504).

[0080] In one embodiment, the system (108) may use channel estimation to equalize the PUSCH data symbols (reverse imperfections induced by the wireless channel as much as possible). The channel estimation output may resemble the original in-phase and quadrature (IQ) constellation diagram sent by the transmitter, but the channel estimation output may include bit errors that are corrected in the bit rate processing stage. The equalized IQ data is stored in a buffer, from which the user separation block (502) may select equalized IQ samples for a particular user. The equalized data for a particular user is converted from complex IQ samples (typically represented using 32 bits) to LLRs.

[0081] In one embodiment, the QAM demodulator block may demodulate complex data symbols into data bits or LLR values ​​based on the modulation type supported by the 5G NR standard. The LLR block may perform demodulation assuming that the input constellation power normalization conforms to the NR standard. The normalization value is determined based on the modulation type. 1 / √2 for BPSK, QPSK, and pi / 2-BPSK ● 1 / √10 for 16-QAM ● 1 / √42 for 64-QAM ● 1 / √170 for 256-QAM

[0082] In one embodiment, there may be two types of decoding: hard-decision decoding and soft-decision decoding. In soft decoding, data symbols may be demapped to LLR values. The LLR value of each bit indicates the likelihood that the bit is 1 or 0. Furthermore, hard decoding may demap data symbols to bits 1 or 0.

[0083] In one embodiment, the LLR block / soft decoding block (504) performs soft demodulation of data symbols and may be designed to operate with four different modulation techniques: QPSK, 16 QAM, 64 QAM, and 256 QAM. Each input to the block carries 48 bits, including data bits as well as channel state information (CSI) bits. The width of each output sample varies depending on the QAM order, with the maximum output width being 64 bits. The LLR block (504) may be designed to generate soft output bits according to the QAM order, and subsequent blocks (descrambler and rate recovery) may process the input bits based on the QAM order. For QPSK IQ symbols, the LLR block (504) may pack two LLRs (2 x 8 bits per LLR) into the MSB of the 64-bit output of the LLR block. Similarly, IQ samples corresponding to 16 QAM, 64 QAM, and 256 QAM may be packed with 4 LLRs (32 bits), 6 LLRs (48 bits), and 8 LLRs (64 bits), respectively, which may then be processed by the descrambling block (506).

[0084] In one embodiment, a common method of descrambling may involve changing the signs of the soft bits after LLR demodulation. The descrambling operation may not change the order of the bits. Instead, the descrambling operation may switch some 1s to 0s and some 0s to 1s. The switching may be performed using a modular sum of 2 between the original bit stream and a pseudorandom sequence. Descrambling may include reducing interference between neighboring cells and randomizing interfering signals.

[0085] In one embodiment, the input data to the descrambling block (506) is received from the soft decoder as 64 bits (8 soft LLR bits), 48 bits (6 soft LLR bits), 32 bits (4 soft LLR bits), or 16 bits (2 soft LLR bits) when the Qm order (QAM modulation order) is 8 (256 QAM), 6 (64 QAM), 4 (16 QAM), or 2 (QPSK), respectively. In addition to the QAM order, the descrambling process is controlled by parameters G_d, a descrambling identification (ID), and a radio network temporary identifier (RNTI). Two 31-bit integers may be used as a linear feedback shift register (LFSR) and shifted using left / right shift operators to meet timing specifications. The pseudo noise (PN) sequence generator may be designed to provide an 8-bit PN sequence to process 64 bits (maximum) of data per cycle. For descrambling, the same PN sequence may be generated in the same way as for scrambling. The unscrambled sequence is written as Y. Y=LLR*(1-2c)

[0086] The sign of the LLR can be changed using Equation 1-2c (c is 0 or 1, i.e., the PN sequence data). If the symbol generated from the PN sequence is 1, the polarity of the received data byte can be inverted, and if the symbol is 0, the data can be bypassed.

[0087] FIG. 6 illustrates a block diagram (400) of an example bit selection process for a PUSCH receiver incorporating optimized rate recovery and HARQ combining in accordance with an embodiment of the present disclosure.

[0088] As shown in Figure 6, in one embodiment, rate recovery at the receiver side may perform the exact reverse of the process performed at the transmitter side. Thus, channel decoding may perform base graph selection and code block decoupling. For further processing of the code block-by-block, CB decoupling may be implemented according to the standard.

[0089] In one embodiment, the optimized rate recovery block input may receive a 64-bit wide data input from the descrambler (for the highest QAM order of 256, all 64 bits of data are valid). Each code block data may first be bit-deinterleaved. Deinterleaving may be performed using only a single buffer with sufficient storage capacity to store the maximum data input of the code block. For a 64-bit wide data input, the packing of LLRs may depend on the Qm order. If the length of the data input per code block is E and the maximum value of E is Emax (corresponding to the smallest MCS index with the largest repetition, Qm is always 2 for Emax), the size of the buffer may be derived as Emax / 2 (for Qm=2, there are two LLRs for each data input). Therefore, the buffer dimension may be represented as BRAM storage with (Emax / 2) row elements and one column element, i.e., an (Ema × / 2) × 1 vector.

[0090] In one embodiment, the actual data received from the descrambler may be stored in a buffer as an (E / Qm) x 1 vector. Because each data input may contain Qm LLRs, the stored data may be viewed as an (E / Qm) x Qm vector, and each stored LLR may be considered a column of the vector. Furthermore, the deinterleaving process may be simplified by performing a read operation on the first MSB LLR (first column) of each data input up to the E / Qm row, then the second MSB LLR (second column), and so on, until Qm columns of LLRs have been read.

[0091] In one embodiment, in the bit selection and filler bit addition stage, the value of the start offset, the size (numf), and the position (numk) of the filler bits may be calculated based on the RV index and the target code rate. numk (the position index of the filler bits) and numf (the number of filler bits added to each code block) may be managed according to the start offsets of different RVs. The rate recovery block may be designed to process the input bits according to the start offset, and the output may be streamed in a similar manner. Depending on the target code rate, E may be greater than N (the LDPC codeword size) when the code rate is low, and E may be smaller than N when the code rate is high. For higher code rates, E may be less than one-third of N. Therefore, to improve processing latency, the rate recovery block may send an indication data length to the HARQ combining block, indicating that the rate recovery block can stream only LLRs of the number of data lengths to the HARQ combining block. In this step, HARQ combining is performed only for LLRSs of the number of data lengths, rather than the full N-size LLRs as conventionally done, thereby reducing processing latency and power consumption.

[0092] In one embodiment, in an incremental redundancy type HARQ, each retransmission may be identical. If a retransmission is necessary, the retransmission may typically use a different set of coded bits than the previous transmission. The receiver may combine the retransmission with previous transmission attempts of the same packet. Various redundancy versions (RVs) may be generated by puncturing the output of the encoder based on a low-rate code. Only a limited number of bits are transmitted in the first transmission, which may effectively be a high-rate code. In retransmissions, additional coded bits may be transmitted. Instead of a non-functional HARQ combining block in conventional designs, the HARQ combining block described in this disclosure may be provided with intelligence to limit combining to only the data length number of LLRs and adjust the input from the rate recovery block according to the start offset.

[0093] In one embodiment, the start offsets for different RVs 0, 2, 3, and 1 are 0, 33*Zc, 56*Zc, and 17*Zc, respectively, for base graph 1, and 0, 25*Zc, 43*Zc, and 0, 25*Zc, respectively, for base graph 2. Previous RV outputs stored in double data rate (DDR) memory may be loaded in combination with the rate recovery output. The proposed combined rate recovery and HARQ block may reuse memory buffers of each code block to reduce memory consumption.

[0094] FIG. 7 shows an exemplary block diagram (700) of a HARQ buffer according to an embodiment of the present invention.

[0095] As shown in FIG. 7, in an embodiment, the HARQ gateway may maintain a DDR bank for storing soft bits corresponding to multiple users (up to 50 active users), and each user (102) may have multiple HARQ process IDs (maximum process ID 4). Furthermore, the PUSCH chain may support HARQ combining using incremental redundancy and support all four possible RVs. If a transmission for this process ID with RV index 0 is received for the first time and the network device interface (NDI) is 1 in the HARQ control information, the transmission may be considered a new transmission. Otherwise, the transmission may be considered a retransmission. For a new transmission, the HARQ process may replace the old contents of the associated HARQ buffer in the DDR bank with the new contents. If decoding of this data block is successful, the data is passed to L2 and the current HARQ memory session may be cleared. If decoding fails, the data may be saved in the HARQ buffer. For a retransmission, the retransmitted data may be soft-combined with the old buffer contents by the HARQ combining block to increase the decoding probability and improve system performance.

[0096] FIG. 8 illustrates an exemplary computer system (800) in which embodiments of the present invention may be implemented or by which they may be implemented.

[0097] As shown in FIG. 8 , the computer system (800) may include an external storage device (810), a bus (820), a main memory (830), a read-only memory (840), a mass storage device (850), communication port(s) (860), and a processor (870). Those skilled in the art will appreciate that the computer system (800) may include multiple processors and communication ports. The processor (870) may include various modules relevant to embodiments of the present disclosure. The communication port(s) (860) may be an RS-232 port for use with a modem-based dial-up connection, a 10 / 100 Ethernet port, a Gigabit or 10 Gigabit port using copper or fiber optics, a serial port, a parallel port, or any other existing or future port. The communication port(s) (860) may be selected depending on the network, such as a local area network (LAN), a wide area network (WAN), or any network to which the computer system (800) connects.

[0098] In one embodiment, main memory (830) may be random access memory (RAM) or any other dynamic storage device(s) commonly known in the art. Read-only memory (840) may be any static storage device(s), such as, but not limited to, programmable read-only memory (PROM) chips for storing static information such as processor (870) boot or basic input / output system (BIOS) instructions. Mass storage device (850) may be any current or future mass storage device solution that can be used to store information and / or instructions. Exemplary mass storage solutions include, but are not limited to, parallel advanced technology attachment (PATA) or serial advanced technology attachment (SATA) hard disk drives, or solid-state drives (internal or external, e.g., with universal serial bus (USB) and / or Firewire interfaces).

[0099] In one embodiment, the bus (820) may communicatively couple the processor(s) (870) with other memory, storage, and communication blocks. The bus (820) may be, for example, a Peripheral Component Interconnect (PCI) / PCI Expansion (PCI-X) bus, a Small Computer System Interface (SCSI), USB, etc. for connecting expansion cards, drives, and other subsystems, or other buses such as a Front Side Bus (FSB) that connects the processor(s) (870) to the computer system (800).

[0100] In another embodiment, operator and administrative interfaces, such as a display, keyboard, and cursor control device, are also coupled to bus (820) to support direct operator interaction with computer system (800). Other operator and administrative interfaces may be provided through a network connection connected via communications port(s) (860). The above components are intended only to illustrate various possibilities. The foregoing exemplary computer system (800) in no way limits the scope of the present disclosure.

[0101] In the embodiments, exemplary implementations of a PUSCH BRP chain receiver on the network side have been shown, but essentially the same applies to implementations of a PDSCH BRP chain receiver on the UE side.

[0102] Although considerable emphasis has been placed in this disclosure on preferred embodiments, the present invention may take on many embodiments without departing from the principles of the disclosure. It is understood that many modifications may be made to the preferred embodiments. These and other modifications in the preferred embodiments of the present disclosure will be apparent to those skilled in the art from the disclosure herein, and it is expressly understood that the foregoing description is merely illustrative of the present disclosure and is not intended to be limiting.

[0103] The present disclosure provides systems and methods for using optimized rate recovery and hybrid automatic repeat request (HARQ) combining methods for physical uplink shared channel (PUSCH) and physical downlink shared channel (PDSCH) bit rate processing chains.

[0104] This disclosure provides a system and method in which the LLR soft bits are efficiently packed such that for each equalized IQ symbol, Qm LLRs are packed from MSB to LSB within a storage element.

[0105] The present disclosure provides a system and method for deinterleaving received LLRs from a descrambler in a rate recovery stage by buffering the bit-packed LLRs row by row and reading out most significant bit (MSB) LLRs across all rows until a limited number of LLR columns (equal to the modulation order) have been read out.

[0106] The present disclosure provides systems and methods that use only the LLRs of the data length during the HARQ combining stage to reduce latency and power consumption.

[0107] The present disclosure provides a system and method in which the data length number of LLRs processed by a HARQ block is based on a base graph and a starting offset derived from an RV index.

[0108] The present invention provides a system and method that uses a single buffer for all three rate recovery sub-stages, including the deinterleaving stage, the bit deselection stage, and the filler bit addition stage of the PUSCH and PDSCH bit rate processing chains.

[0109] The present disclosure provides systems and methods that reduce latency and power consumption by the data length number of LLRs in the HARQ combining stage instead of the full "N" LLRs in the PUSCH and PDSCH bit rate processing chains.

Claims

1. 1. A system (108) for optimizing memory utilization during decoding of uplink data at a base station, said system (108) comprising: a processor (202); a memory (204) operably coupled to the processor (202), the memory (204) storing instructions that, when executed by the processor (202), receiving input from a computing device (104) associated with one or more users (102), the input being based on one or more Orthogonal Frequency Division Multiplexing (OFDM) subcarriers transmitted by the computing device (104) over a Physical Uplink Shared Channel (PUSCH); determining one or more in-phase orthogonal (IQ) data symbols associated with the one or more OFDM subcarriers; generating one or more log-likelihood ratio (LLR) data bits associated with the computing device (104) based on the one or more IQ data symbols; and optimizing memory utilization by utilizing a predetermined number of LLR data bits associated with the one or more LLR data bits for each of the one or more IQ data symbols.

2. 2. The system of claim 1, wherein the predetermined number of LLR data bits is based on a starting offset derived from a low-density parity-check (LDPC) base graph and a redundancy version (RV) index associated with a PUSCH process.

3. The system of claim 1 , wherein the processor generates a rate recovery output based on the one or more LLR data bits.

4. 4. The system of claim 3, wherein the processor generates the rate-recovered output by buffering LLR data bits row by row and streaming out most significant bit (MSB) LLR data bits across all rows until a limited number of LLR sequences have been streamed, the limited number of LLR data sequence being based on a modulation order of the one or more IQ data symbols.

5. 1. A method for optimizing memory utilization during decoding of uplink data at a base station, the method comprising: receiving, by a processor (202) associated with the system (108), input from a computing device (104) associated with one or more users (102), the input being based on one or more Orthogonal Frequency Division Multiplexing (OFDM) subcarriers transmitted by the computing device (104) over a Physical Uplink Shared Channel (PUSCH); determining, by the processor (202), one or more in-phase orthogonal (IQ) data symbols associated with the one or more OFDM subcarriers; generating, by the processor (202), one or more log-likelihood ratio (LLR) data bits associated with the computing device (104) based on the one or more IQ data symbols; and optimizing memory utilization by the processor (202) for each of the one or more IQ data symbols by utilizing a predetermined number of LLR data bits associated with the one or more LLR data bits.

6. 6. The method of claim 5, wherein the predetermined number of LLR data bits is based on a starting offset derived from a low-density parity-check (LDPC) base graph and a redundancy version (RV) index associated with a PUSCH process.

7. The method of claim 5 , comprising generating, by the processor (202), a rate recovery output based on the one or more LLR data bits.

8. 8. The method of claim 7, further comprising: generating a rate-recovered output by the processor (202) by buffering the LLR data bits row by row and streaming out most significant bit (MSB) LLR data bits across all rows until a limited number of LLR sequences have been streamed, the limited number of LLR data sequence being based on a modulation order of one or more IQ data symbols.

9. A non-transitory computer-readable medium having a processor with executable instructions, the instructions comprising: receiving input from a computing device (104) associated with one or more users (102), the input being based on one or more Orthogonal Frequency Division Multiplexing (OFDM) subcarriers transmitted by the computing device (104) over a Physical Uplink Shared Channel (PUSCH); determining one or more in-phase orthogonal (IQ) data symbols associated with the one or more OFDM subcarriers; generating one or more log-likelihood ratio (LLR) data bits associated with the computing device (104) based on the one or more IQ data symbols; and optimizing memory utilization by utilizing a predetermined number of LLR data bits associated with the one or more LLR data bits for each of the one or more IQ data symbols.

10. A user equipment (UE) system (108) for optimizing memory utilization, comprising: a processor; a memory operatively coupled to the processor, the memory storing instructions that, when executed by the processor, receiving an input from a base station associated with one or more users, the input being based on one or more Orthogonal Frequency Division Multiplexing (OFDM) subcarriers transmitted by the base station over a Physical Downlink Shared Channel (PDSCH); determining one or more in-phase orthogonal (IQ) data symbols associated with the one or more OFDM subcarriers; generating one or more log-likelihood ratio (LLR) data bits based on the one or more IQ data symbols; and optimizing memory utilization by utilizing a predetermined number of LLR data bits associated with the one or more LLR data bits for each of the one or more IQ data symbols.

11. 11. The UE of claim 10, wherein the predetermined number of LLR data bits is based on a starting offset derived from a low-density parity check (LDPC) base graph and a redundancy version (RV) index associated with the PDSCH processing.

12. The UE of claim 10 , wherein the processor (202) generates a rate recovery output based on the one or more LLR data bits.

13. 13. The UE of claim 12, wherein the processor generates a rate recovery output by buffering LLR data bits row by row and streaming out most significant bit (MSB) LLR data bits across all rows until a limited number of LLR sequences have been streamed, the limited number of LLR data sequence being based on a modulation order of the one or more IQ data symbols.

14. 1. A method for optimizing memory utilization during decoding of downlink data in a user equipment (UE), the method comprising: receiving, by a processor (202), an input from a base station (110) associated with one or more users (102), the input being based on one or more Orthogonal Frequency Division Multiplexing (OFDM) subcarriers transmitted by a computing device (104) over a Physical Downlink Shared Channel (PDSCH); determining, by the processor (202), one or more in-phase orthogonal (IQ) data symbols associated with the one or more OFDM subcarriers; generating, by the processor (202), one or more log-likelihood ratio (LLR) data bits associated with the base station (110) based on the one or more IQ data symbols; and optimizing memory utilization by the processor (202) for each of the one or more LLR data bits by utilizing a predetermined number of LLR data bits associated with the one or more LLR data bits.

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