Pixel circuit, pixel driving circuit and display device

Abstract

The present disclosure provides a pixel circuit, a pixel driving circuit, and a display device. The pixel circuit includes a first light-emitting control circuit, a light-emitting element, a driving circuit, and a light-emitting gating circuit, wherein the light-emitting gating circuit controls, under control of a first control signal and in accordance with a light-emitting data voltage, to generate a current path between a second end of the driving circuit and the light-emitting element under control of a light-emitting control voltage in a light-emitting stage, so that the driving circuit can control the light-emitting element to emit light, or controls, under control of a first control signal and in accordance with a light-emitting data voltage, to generate a current path between the second end of the driving circuit and the light-emitting element in a light-emitting stage, so that the driving circuit can control the light-emitting element to emit light. The pixel circuit described in the embodiments of the present disclosure can perform PWM (pulse-width modulation) dimming and improve low-gradation brightness control ability, addressing problems of light-emitting elements such as poor brightness uniformity at low current density and insufficient low-gradation control ability.

Description

[Technical Field]

[0001] The present disclosure relates to the field of display technology, and in particular to pixel circuits, pixel driving circuits and display devices. [Background technology]

[0002] The light-emitting element (which may be, for example, a mini light-emitting diode or a micro light-emitting diode) has problems such as poor brightness uniformity at low current density and insufficient low-gradation control ability, and the brightness control ability at low gradation is poor. Summary of the Invention

[0003] In a first aspect, an embodiment of the present disclosure provides a pixel circuit including a first light-emitting control circuit, a light-emitting element, a driving circuit, and a light-emitting gating circuit, the first light-emitting control circuit is electrically connected to a first light-emitting control end, a first voltage end and the first end of the driving circuit respectively, and is used to control the first voltage end and the first end of the driving circuit to communicate with each other under the control of a first light-emitting control signal provided by the first light-emitting control end in a light-emitting stage; a second end of the driving circuit electrically connected to a first electrode of the light-emitting element, the driving circuit being used to drive the light-emitting element; The light emitting gating circuit is controlled to generate a current path between the second end of the driving circuit and the light emitting element under the control of the light emitting control voltage supplied by the light emitting control voltage terminal in a light emitting stage according to the light emitting data voltage supplied by the light emitting data voltage terminal under the control of the first control signal supplied by the first control terminal, so that the driving circuit can control the light emitting element to emit light, or to generate a current path between the second end of the driving circuit and the light emitting element in the light emitting stage, so that the driving circuit can control the light emitting element to emit light, providing a pixel circuit.

[0004] Optionally, the light emission gating circuit includes a second light emission control circuit and a first gating control circuit; the first gating control circuit is electrically connected to the first control terminal, the light-emitting data voltage terminal, the gating control terminal, the second light-emitting control terminal, the light-emitting control voltage terminal and the first light-emitting control terminal, and is used to write the light-emitting data voltage provided by the light-emitting data voltage terminal into the gating control terminal under the control of the first control signal, and to control the second light-emitting control terminal and the light-emitting control voltage terminal to communicate with each other or the second light-emitting control terminal and the first light-emitting control terminal to communicate with each other under the control of the potential of the gating control terminal; the second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the second terminal of the driving circuit, and the first electrode of the light-emitting element, respectively, and is used to control the communication between the second terminal of the driving circuit and the first electrode of the light-emitting element under the control of the potential of the second light-emitting control terminal; The second electrode of the light emitting device is electrically connected to a second voltage terminal.

[0005] Optionally, the light emission gating circuit further includes a first capacitance; A first end of the first capacitor is electrically connected to the gating control end, and a second end of the first capacitor is electrically connected to a first initial voltage end.

[0006] Optionally, the first gating control circuit includes a first transistor, a second transistor, and a third transistor; a control electrode of the first transistor electrically connected to the first control end, a first electrode of the first transistor electrically connected to the light-emitting data voltage end, and a second electrode of the first transistor electrically connected to the gating control end; a control electrode of the second transistor is electrically connected to the gating control terminal, a first electrode of the second transistor is electrically connected to the light-emitting control voltage terminal, and a second electrode of the second transistor is electrically connected to the second light-emitting control terminal; A control electrode of the third transistor is electrically connected to the gating control terminal, a first electrode of the third transistor is electrically connected to the first light-emitting control terminal, and a second electrode of the third transistor is electrically connected to the second light-emitting control terminal.

[0007] Optionally, the second light-emitting control circuit includes a fourth transistor; The control electrode of the fourth transistor is electrically connected to the second light-emitting control terminal, the first electrode of the fourth transistor is electrically connected to the second terminal of the driving circuit, and the second electrode of the fourth transistor is electrically connected to the first electrode of the light-emitting element.

[0008] Alternatively, the first transistor is an n-type transistor, the second transistor is a p-type transistor, and the third transistor is an n-type transistor; or the first transistor is an n-type transistor, the second transistor is an n-type transistor, and the third transistor is a p-type transistor; or The first transistor is a p-type transistor, the second transistor is an n-type transistor, and the third transistor is a p-type transistor.

[0009] Optionally, when the second transistor is a p-type transistor and the third transistor is an n-type transistor, the width-to-length ratio of the channel of the third transistor is greater than the width-to-length ratio of the channel of the second transistor.

[0010] Optionally, the light emission gating circuit includes a second gating control circuit, a third light emission control circuit and a fourth light emission control circuit; the second gating control circuit is electrically connected to the first control end, the light emitting data voltage end and the gating control end respectively, and is used to control the light emitting data voltage to be written to the gating control end under the control of the first control signal; the third light-emitting control circuit is electrically connected to the gating control terminal, the second pole and the second voltage terminal of the light-emitting element, respectively, and is used to control the second pole of the light-emitting element to communicate with the second voltage terminal under the control of the potential of the gating control terminal; The fourth light-emitting control circuit is electrically connected to the light-emitting control voltage terminal and the second pole and second voltage terminal of the light-emitting element, respectively, and is used to control the communication between the second pole of the light-emitting element and the second voltage terminal under the control of the light-emitting control voltage supplied by the light-emitting control voltage terminal.

[0011] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a fifth light-emitting control circuit; The fifth light-emitting control circuit is electrically connected to the first light-emitting control terminal, the second terminal of the driving circuit, and the first electrode of the light-emitting element, respectively, and is used to control the communication between the second terminal of the driving circuit and the first electrode of the light-emitting element under the control of the first light-emitting control signal.

[0012] Optionally, the light emission gating circuit further includes a second capacitance; A first end of the second capacitor is electrically connected to the gating control end, and a second end of the second capacitor is electrically connected to a first initial voltage end.

[0013] Optionally, the second gating control circuit includes a fifth transistor, the third light-emitting control circuit includes a sixth transistor, and the fourth light-emitting control circuit includes a seventh transistor; a control electrode of the fifth transistor electrically connected to the first control end, a first electrode of the fifth transistor electrically connected to the light-emitting data voltage end, and a second electrode of the fifth transistor electrically connected to the gating control end; a control electrode of the sixth transistor electrically connected to the gating control terminal, a first electrode of the sixth transistor electrically connected to the second electrode of the light-emitting element, and a second electrode of the sixth transistor electrically connected to the second voltage terminal; The control electrode of the seventh transistor is electrically connected to the light-emitting control voltage terminal, the first electrode of the seventh transistor is electrically connected to the second electrode of the light-emitting element, and the second electrode of the seventh transistor is electrically connected to the second voltage terminal.

[0014] Alternatively, the seventh transistor is a p-type transistor, the sixth transistor is an n-type transistor, and the fifth transistor is an n-type transistor; or the seventh transistor is a p-type transistor, the sixth transistor is an n-type transistor, and the fifth transistor is a p-type transistor; or the seventh transistor is an n-type transistor, the sixth transistor is a p-type transistor, and the fifth transistor is an n-type transistor; or The seventh transistor is an n-type transistor, the sixth transistor is a p-type transistor, and the fifth transistor is a p-type transistor.

[0015] Optionally, the pixel circuit according to at least one embodiment of the present disclosure further includes a data writing circuit, a compensation control circuit, a first initialization circuit, a second initialization circuit, and a third capacitor; the data writing circuit is electrically connected to a second control end, a data line and a first end of the driving circuit respectively, and is used to control, under the control of a second control signal provided by the second control end, the data voltage provided by the data line to be written into the first end of the driving circuit; The compensation control circuit is electrically connected to a third control end, a control end of the driving circuit, and a second end of the driving circuit, respectively, and is used to control the communication between the control end of the driving circuit and the second end of the driving circuit under the control of a third control signal provided by the third control end; the first initialization circuit is electrically connected to a first reset control terminal, a control terminal of the driving circuit and a third initial voltage terminal respectively, and is used to control, under the control of a first reset control signal provided by the first reset control terminal, to write the third initial voltage provided by the third initial voltage terminal into the control terminal of the driving circuit; The second initialization circuit is electrically connected to a second reset control terminal, a first pole of the light emitting element, and a fourth initial voltage terminal, respectively, and is used to control, under the control of a second reset control signal provided by the second reset control terminal, to write a fourth initial voltage provided by the fourth initial voltage terminal to the first pole of the light emitting element; A first end of the third capacitance is electrically connected to the control end of the driving circuit, and a second end of the third capacitance is electrically connected to the first voltage end.

[0016] Optionally, the first initialization circuit includes an eighth transistor, the compensation control circuit includes a ninth transistor, the data write circuit includes a tenth transistor, and the second initialization circuit includes an eleventh transistor; a control electrode of the eighth transistor electrically connected to the first reset control terminal, a first electrode of the eighth transistor electrically connected to the third initial voltage terminal, and a second electrode of the eighth transistor electrically connected to the control terminal of the driving circuit; a control pole of the ninth transistor electrically connected to the third control end, a first pole of the ninth transistor electrically connected to the control end of the driving circuit, and a second pole of the ninth transistor electrically connected to the second end of the driving circuit; a control electrode of the tenth transistor is electrically connected to the second control end, a first electrode of the tenth transistor is electrically connected to the data line, and a second electrode of the tenth transistor is electrically connected to a first end of a driving circuit; or a control electrode of the tenth transistor is electrically connected to the first reset control end, a first electrode of the tenth transistor is electrically connected to a light-emitting data voltage end, and a second electrode of the tenth transistor is electrically connected to a first end of a driving circuit; A control electrode of the eleventh transistor is electrically connected to the second reset control terminal or the first reset control terminal, a first electrode of the eleventh transistor is electrically connected to the fourth initial voltage terminal, and a second electrode of the eleventh transistor is electrically connected to the first electrode of the light-emitting element.

[0017] Optionally, the eighth transistor and the ninth transistor are oxide thin film transistors.

[0018] Optionally, the eleventh transistor is an oxide thin film transistor, and a control electrode of the eleventh transistor is electrically connected to the first reset control terminal.

[0019] Optionally, at least one of the eighth transistor and the ninth transistor is a double-gate transistor.

[0020] Optionally, the light emitting element is a micro light emitting diode or a mini light emitting diode.

[0021] In a second aspect, an embodiment of the present disclosure is a pixel driving method applied to the pixel circuit described above, the pixel driving method comprising: The first light-emitting control circuit controls the first voltage terminal and the first terminal of the driving circuit to communicate with each other under the control of the first light-emitting control signal in the light-emitting stage; The pixel driving method includes: controlling the light emitting gating circuit to generate a current path between the second end of the driving circuit and the light emitting element under control of a light emitting control voltage supplied by a light emitting control voltage terminal under control of a first control signal according to a light emitting data voltage in a light emitting stage, so that the driving circuit can control the light emitting element to emit light; or controlling the light emitting gating circuit to generate a current path between the second end of the driving circuit and the light emitting element in a light emitting stage, so that the driving circuit can control the light emitting element to emit light.

[0022] Optionally, the light emitting gating circuit includes a second light emitting control circuit and a first gating control circuit, and the pixel driving method includes: The first gating control circuit writes the light-emitting data voltage into the gating control terminal under the control of the first control signal, and controls the second light-emitting control terminal to communicate with the light-emitting control voltage terminal or the second light-emitting control terminal to communicate with the first light-emitting control terminal under the control of the potential of the gating control terminal; The second light-emitting control circuit controls the second end of the driving circuit to communicate with the first electrode of the light-emitting element under the control of the potential of the second light-emitting control end.

[0023] Optionally, the light emitting gating circuit includes a second gating control circuit, a third light emitting control circuit and a fourth light emitting control circuit, and the pixel driving method includes: The second gating control circuit controls the light emitting control voltage to be written to the gating control terminal under the control of the first control signal; The third light-emitting control circuit controls the second pole of the light-emitting element to communicate with the second voltage terminal under the control of the potential of the gating control terminal; The fourth light-emitting control circuit controls the second electrode of the light-emitting element to communicate with the second voltage terminal under the control of a light-emitting control voltage.

[0024] In a third aspect, an embodiment of the present disclosure further provides a display device including the pixel circuit described above. [Brief explanation of the drawings]

[0025] [Figure 1] FIG. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 2] FIG. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 3] FIG. 10 is a waveform diagram of the potential at the second light-emitting control end EM2 in at least one embodiment of the present disclosure. [Figure 4]FIG. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 5] FIG. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 6] FIG. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 7A] FIG. 1 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 7B] FIG. 1 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 8] 7B is a timing diagram illustrating an operation of at least one embodiment of the pixel circuit shown in FIG. 7A. [Figure 9] 7B is a simulated operational timing diagram of at least one embodiment of the pixel circuit shown in FIG. 7A. [Figure 10] FIG. 1 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 11] 11 is an operation timing chart of at least one embodiment of the pixel circuit shown in FIG. 10. [Figure 12] FIG. 1 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 13] FIG. 1 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 14] FIG. 1 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 15] FIG. 1 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 16] 16 is an operation timing chart of at least one embodiment of the pixel circuit shown in FIG. 15. [Figure 17] 10 is a waveform diagram of the potential of the gating control terminal ch and the second light-emitting control signal provided by the second light-emitting control terminal EM2 in at least one embodiment of the present disclosure. FIG. [Figure 18] 16 is a simulation operation timing chart of at least one embodiment of the pixel circuit shown in FIG. 15. [Figure 19]FIG. 1 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 20] 20 is an operation timing chart of at least one embodiment of the pixel circuit shown in FIG. 19. [Figure 21] FIG. 1 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 22] FIG. 1 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 23] FIG. 1 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 24] 24 is an operation timing chart of at least one embodiment of the pixel circuit shown in FIG. 23. [Figure 25] FIG. 1 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 26] 26 is an operation timing chart of at least one embodiment of the pixel circuit shown in FIG. 25. [Figure 27] FIG. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 28] FIG. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 29] FIG. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 30] FIG. 1 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 31] 31 is an operation timing chart of at least one embodiment of the pixel circuit shown in FIG. 30. [Figure 32] FIG. 1 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 33] FIG. 1 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. [Figure 34] 34 is an operation timing chart of at least one embodiment of the pixel circuit shown in FIG. 33. [Figure 35] FIG. 1 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0026] Hereinafter, the technical aspects of the embodiments of the present disclosure will be clearly and completely described with reference to the drawings in the embodiments of the present disclosure, but it should be apparent that the described embodiments are only some of the embodiments of the present disclosure, and are not all of the embodiments. Based on the embodiments of the present disclosure, other embodiments obtained by those skilled in the art without paying creative labor shall all fall within the scope of protection of the present disclosure.

[0027] The transistors used in all the embodiments of the present disclosure may be triodes, thin film transistors, field effect transistors, or other devices with similar characteristics. In the embodiments of the present disclosure, in order to distinguish between the two poles other than the control pole of the transistor, one pole will be referred to as a first pole and the other pole will be referred to as a second pole.

[0028] In actual operation, if the transistor is a triode, the control pole may be the base, the first pole may be the collector, and the second pole may be the emitter, or the control pole may be the base, the first pole may be the emitter, and the second pole may be the collector.

[0029] In actual operation, if the transistor is a thin film transistor or a field effect transistor, the control electrode may be the gate, the first electrode may be the drain, and the second electrode may be the source, or the control electrode may be the gate, the first electrode may be the source, and the second electrode may be the drain.

[0030] The pixel circuit according to the embodiment of the present disclosure includes a first light-emitting control circuit, a light-emitting element, a driving circuit, and a light-emitting gating circuit; the first light-emitting control circuit is electrically connected to a first light-emitting control end, a first voltage end and the first end of the driving circuit respectively, and is used to control the first voltage end and the first end of the driving circuit to communicate with each other under the control of a first light-emitting control signal provided by the first light-emitting control end in a light-emitting stage; a second end of the driving circuit electrically connected to a first electrode of the light-emitting element, the driving circuit being used to drive the light-emitting element; The light-emitting gating circuit is used to control, under the control of the first control signal provided by the first control end, according to the light-emitting data voltage provided by the light-emitting data voltage end, to form a current path between the second end of the driving circuit and the light-emitting element under the control of the light-emitting control voltage provided by the light-emitting control voltage end in a light-emitting stage, so that the driving circuit can control the light-emitting element to emit light, or to control, under the control of the light-emitting state, to form a current path between the second end of the driving circuit and the light-emitting element, so that the driving circuit can control the light-emitting element to emit light.

[0031] In at least one embodiment of the present disclosure, the light-emitting control voltage may be, but is not limited to, a PWM (pulse width modulation) signal, and the light-emitting control voltage may be a high-frequency signal.

[0032] During operation of the pixel circuit according to the embodiment of the present disclosure, in the light-emitting stage, the light-emitting gating circuit forms a current path between the second end of the driving circuit and the light-emitting element under the control of the first control signal according to the light-emitting data voltage, and in the light-emitting stage, under the control of the light-emitting control voltage, to control the light-emitting element to emit light at high frequency for a short time, using a PWM dimming method to achieve low gradation, or to control the light-emitting element to emit light for a long time during the light-emitting stage ("causing the light-emitting element to emit light for a long time" may refer to causing the light-emitting element to emit light for the entire time during the light-emitting stage, in which case the gradation is determined entirely by the data voltage), using a PAM (pulse amplitude modulation) dimming method to achieve high gradation. The embodiment of the present disclosure can improve the brightness control ability of high and low gradation.

[0033] In at least one embodiment of the present disclosure, the light-emitting control voltage may be a high-frequency PWM signal, and in the light-emitting stage, when the light-emitting gating circuit forms a current path between the second end of the driving circuit and the light-emitting element under the control of the light-emitting control voltage, the light-emitting element will emit light for a short period of time multiple times, and the higher the frequency of the light-emitting control voltage, the less the human eye will perceive flickering, and the shorter the light-emitting time, so that a low gradation can be achieved.

[0034] The pixel circuit described in the embodiments of the present disclosure can perform PWM dimming to address problems of light-emitting elements, such as poor luminance uniformity at low current densities and insufficient low-gradation control capability, and can improve low-gradation luminance control capability.

[0035] An embodiment of the present disclosure is a pixel circuit with a PWM dimming function that solves the problem of non-uniform light emission brightness at low current densities, and uses PAM mode for long-term light emission at high gradations, and PWM mode for short-term, high-frequency light emission at low gradations.

[0036] In at least one embodiment of the present disclosure, the light emission gating circuit includes a second light emission control circuit and a first gating control circuit; the first gating control circuit is electrically connected to the first control terminal, the light-emitting data voltage terminal, the gating control terminal, the second light-emitting control terminal, the light-emitting control voltage terminal and the first light-emitting control terminal, and is used to write the light-emitting data voltage provided by the light-emitting data voltage terminal into the gating control terminal under the control of the first control signal, and to control the second light-emitting control terminal and the light-emitting control voltage terminal to communicate with each other or the second light-emitting control terminal and the first light-emitting control terminal to communicate with each other under the control of the potential of the gating control terminal; the second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the second terminal of the driving circuit, and the first electrode of the light-emitting element, respectively, and is used to control the communication between the second terminal of the driving circuit and the first electrode of the light-emitting element under the control of the potential of the second light-emitting control terminal; The second electrode of the light emitting device is electrically connected to a second voltage terminal.

[0037] In a specific implementation, the light-emitting gating circuit may include a second light-emitting control circuit and a first gating control circuit, and the first gating control circuit controls the second light-emitting control terminal to communicate with the light-emitting control voltage terminal, or controls the second light-emitting control terminal to communicate with the first light-emitting control terminal, and the second light-emitting control circuit controls the second terminal of the driving circuit to communicate with the first electrode of the light-emitting element under the control of the potential of the second light-emitting control terminal.

[0038] Optionally, the first voltage end may be a high voltage end, and the second voltage end may be a low voltage end, but is not limited thereto.

[0039] As shown in FIG. 1, a pixel circuit according to at least one embodiment of the present disclosure includes: a first light-emitting control circuit 11, a light-emitting element E1, a driving circuit 10, and a light-emitting gating circuit; the first light-emitting control circuit 11 is electrically connected to a first light-emitting control end EM1, a first voltage end V1 and a first end of the driving circuit 10, and is used to control the communication between the first voltage end V1 and the first end of the driving circuit 10 under the control of a first light-emitting control signal provided by the first light-emitting control end EM1 in a light-emitting stage; a second end of the driving circuit 10 electrically connected to a first electrode of the light-emitting element E1, and the driving circuit 10 is used to drive the light-emitting element E1; The light emitting gating circuit includes a second light emitting control circuit 121 and a first gating control circuit 122; The first gating control circuit 122 is electrically connected to the first control end G1, the light emitting data voltage end DT, the gating control end ch, the second light emitting control end EM2, the light emitting control voltage end VF and the first light emitting control end EM1, and is used to write the light emitting data voltage provided by the light emitting data voltage end DT to the gating control end ch under the control of the first control signal provided by the first control end G1, and to control the second light emitting control end EM2 and the light emitting control voltage end VF to be connected to each other or the second light emitting control end EM2 and the first light emitting control end EM1 to be connected to each other under the control of the potential of the gating control end ch; The second light-emitting control circuit 121 is electrically connected to the second light-emitting control end EM2, the second end of the driving circuit 10, and the first electrode of the light-emitting element E1, respectively, and is used to control the communication between the second end of the driving circuit 10 and the first electrode of the light-emitting element E1 under the control of the potential of the second light-emitting control end EM2; The second electrode of the light emitting element E1 is electrically connected to a second voltage terminal V2.

[0040] In operation of at least one embodiment of the pixel circuit as shown in FIG. 1 of the present disclosure, a display period may include a data writing phase and a light emitting phase set in sequence; In a data writing step, the first gating control circuit 122 writes a light emitting data voltage to the gating control terminal ch under the control of a first control signal, and controls the second light emitting control terminal EM2 to communicate with the light emitting control voltage terminal VF or controls the second light emitting control terminal EM2 to communicate with the first light emitting control terminal EM1 under the control of the potential of the gating control terminal ch; In the light-emitting stage, the second light-emitting control circuit 121 controls the potential of the second light-emitting control terminal EM2 to connect the second end of the driving circuit 10 to the first electrode of the light-emitting element E1; In the light emitting stage, when the second light emitting control terminal EM2 and the light emitting control voltage terminal VF are connected, the light emitting element E1 emits light at a high frequency for a short time, thereby realizing a low gradation display; and when the second light emitting control terminal EM2 and the first light emitting control terminal EM1 are connected, in the light emitting stage, the light emitting element E1 emits light for a long time, thereby realizing a high gradation display.

[0041] Optionally, the light emission gating circuit further includes a first capacitance; A first end of the first capacitor is electrically connected to the gating control end, and a second end of the first capacitor is electrically connected to a first initial voltage end.

[0042] Optionally, the first gating control circuit includes a first transistor, a second transistor, and a third transistor; a control electrode of the first transistor electrically connected to the first control end, a first electrode of the first transistor electrically connected to the light-emitting data voltage end, and a second electrode of the first transistor electrically connected to the gating control end; a control electrode of the second transistor is electrically connected to the gating control terminal, a first electrode of the second transistor is electrically connected to the light-emitting control voltage terminal, and a second electrode of the second transistor is electrically connected to the second light-emitting control terminal; A control electrode of the third transistor is electrically connected to the gating control terminal, a first electrode of the third transistor is electrically connected to the first light-emitting control terminal, and a second electrode of the third transistor is electrically connected to the second light-emitting control terminal.

[0043] Optionally, the second light-emitting control circuit includes a fourth transistor; The control electrode of the fourth transistor is electrically connected to the second light-emitting control terminal, the first electrode of the fourth transistor is electrically connected to the second terminal of the driving circuit, and the second electrode of the fourth transistor is electrically connected to the first electrode of the light-emitting element.

[0044] Alternatively, the first transistor is an n-type transistor, the second transistor is a p-type transistor, and the third transistor is an n-type transistor; or the first transistor is an n-type transistor, the second transistor is an n-type transistor, and the third transistor is a p-type transistor; or The first transistor is a p-type transistor, the second transistor is an n-type transistor, and the third transistor is a p-type transistor, but is not limited thereto.

[0045] As shown in FIG. 2 , in addition to at least one embodiment of the pixel circuit shown in FIG. 1 of the present disclosure, the light emission gating circuit further includes a first capacitance C1; a first end of the first capacitance C1 electrically connected to the gating control end ch, and a second end of the first capacitance C1 electrically connected to a first initial voltage end I1, which is used to supply a first initial voltage Vini1; The first gating control circuit 122 includes a first transistor T1, a second transistor T2, and a third transistor T3; The gate of the first transistor T1 is electrically connected to the first control end G1, the source of the first transistor T1 is electrically connected to the light-emitting data voltage end DT, and the drain of the first transistor T1 is electrically connected to the gating control end ch; The gate of the second transistor T2 is electrically connected to the gating control terminal ch, the source of the second transistor T2 is electrically connected to the light-emitting control voltage terminal VF, and the drain of the second transistor T2 is electrically connected to the second light-emitting control terminal EM2, and the light-emitting control voltage terminal VF is used to supply the light-emitting control voltage HF; The gate of the third transistor T3 is electrically connected to the gating control end ch, the source of the third transistor T3 is electrically connected to the first light-emitting control end EM1, and the drain of the third transistor T3 is electrically connected to the second light-emitting control end EM2; The second light-emitting control circuit 121 includes a fourth transistor T4, The gate of the fourth transistor T4 is electrically connected to the second light-emitting control end EM2, the source of the fourth transistor T4 is electrically connected to the second end of the driving circuit 10, and the drain of the fourth transistor T4 is electrically connected to the first electrode of the light-emitting element E1.

[0046] In at least one embodiment of the pixel circuit shown in FIG. 2, T1 is an n-type transistor, T2 is a p-type transistor, T3 is an n-type transistor, and T4 is a p-type transistor, but is not limited to this.

[0047] In operation of at least one embodiment of the pixel circuit as shown in FIG. 2 of the present disclosure, a display period may include a data writing phase and a light emitting phase set in sequence; In the data writing stage, G1 supplies a high voltage signal, EM1 supplies a high voltage signal, and T1 is turned on, so that the light-emitting data voltage supplied by DT is written to the gating control terminal ch, and C1 maintains the potential of the gating control terminal ch. When the light-emitting data voltage is a high voltage, T3 can be turned on in the data writing stage and the light-emitting stage; when the light-emitting data voltage is a low voltage, T2 can be turned on in the data writing stage and the light-emitting stage; In the light-emitting stage, when T3 is turned on, EM2 and EM1 are connected, and the light-emitting element E1 emits light for a long time. When T2 is turned on, EM2 and VF are connected, and the light-emitting control voltage HF is input to EM2, and the light-emitting element E1 emits light at high frequency for a short time.

[0048] 2 of the present disclosure, in the case of long-term emission by PAM, the high-voltage signal provided by DT is input to the gate of T3 via T1, which turns on T3 and allows the high-voltage or low-voltage signal provided by EM1 to pass through. When the high-voltage signal provided by EM1 is passed through, a high turn-on voltage is required, which increases the requirements for the first control signal provided by G1. This can be solved in the following manner: When DT provides a high-voltage signal, the emission data voltage provided by DT can be a low voltage; the emission data voltage can turn on T2 when HF is high, and provide a high-voltage signal to EM2 via HF, while turning off T2 when HF is low; and at the same time, when EM1 provides a high-voltage signal, T3 can be turned off, and when EM1 provides a low-voltage signal, T3 can be turned on. According to this configuration, the following design is required. That is, by making the width W3 of T3 larger than the width W2 of T2, the width-to-length ratio of T3's channel is larger than the width-to-length ratio of T2's channel, so that EM1 supplies a low voltage signal, HF becomes a high voltage, and the potential of EM2 becomes a low voltage. In actual operation, the larger W3 is than W2, when EM1 supplies a low voltage signal, HF becomes a high voltage, the potential of EM2 becomes closer to the low voltage signal supplied by EM1, and conversely, the potential of EM2 becomes closer to the high voltage of HF, as shown in Figure 3.

[0049] Optionally, W3 may be, but is not limited to, twice W2.

[0050] At least one embodiment of the pixel circuit as shown in FIG. 4 of the present disclosure differs from at least one embodiment of the pixel circuit as shown in FIG. 2 of the present disclosure in that the second transistor T2 is an n-type transistor and the third transistor T3 is a p-type transistor.

[0051] In operation of at least one embodiment of the pixel circuit as shown in FIG. 4 of the present disclosure, a display period may include a data writing phase and a light emitting phase set in sequence; In the data writing stage, G1 supplies a high voltage signal, EM1 supplies a high voltage signal, and T1 is turned on, so that the light-emitting data voltage supplied by DT is written to the gating control terminal ch, and C1 maintains the potential of the gating control terminal ch. When the light-emitting data voltage is a low voltage, T3 can be turned on in the data writing stage and the light-emitting stage. When the light-emitting data voltage is a high voltage, T2 can be turned on in the data writing stage and the light-emitting stage. In the light-emitting stage, when T3 is turned on, EM2 and EM1 are connected, and the light-emitting element E1 emits light for a long time. When T2 is turned on, EM2 and VF are connected, and the light-emitting control voltage HF is input to EM2, and the light-emitting element E1 emits light at high frequency for a short time.

[0052] During operation of at least one embodiment of the pixel circuit as shown in FIG. 4 of the present disclosure, if DT provides a low voltage signal in the data writing stage, then in the light emitting stage, it is necessary to turn on T3 to pass the low voltage signal provided by EM1; if DT provides a high voltage signal in the data writing stage, it is necessary to turn on T2 to pass HF; since the span between the high and low voltages provided by DT is large, the requirement for the potential of the high voltage signal provided by G1 is also large; in addition, when the potential of the gating control terminal ch is maintained at a low voltage, T1 requires a lower turn-off voltage, so the span between the high and low voltages of the first control signal provided by G1 is large.

[0053] During operation of at least one embodiment of the pixel circuit as shown in FIG. 4 of the present disclosure, if the potential of ch is low during the data writing stage, T3 is turned on. After the light-emitting stage begins, the potential of ch must be maintained at the voltage value of the low-voltage signal supplied by DT (this voltage value may be, for example, −9V) to ensure that T3 is turned on. However, if the voltage value of the low-voltage signal supplied by G1 is −7V, the potential of ch is likely to increase due to reverse leakage of T1. Therefore, the voltage value of the low-voltage signal supplied by G1 must be adjusted from −12V to −9V. (If it is necessary to completely turn off T1 and eliminate reverse leakage of ch, the voltage value of the low-voltage signal supplied by G1 must be reduced to −12V, but it may also be reduced to −9V if necessary.)

[0054] At least one embodiment of the pixel circuit as shown in FIG. 5 of the present disclosure differs from at least one embodiment of the pixel circuit as shown in FIG. 4 of the present disclosure in that T1 is a p-type transistor.

[0055] In operation of at least one embodiment of the pixel circuit as shown in FIG. 5 of the present disclosure, a display period may include a data writing stage and a light emitting stage set sequentially; In the data writing stage, G1 supplies a low voltage signal, EM1 supplies a high voltage signal, and T1 is turned on, so that the light-emitting data voltage supplied by DT is written to the gating control terminal ch, and C1 maintains the potential of the gating control terminal ch. When the light-emitting data voltage is a low voltage, T3 can be turned on in the data writing stage and the light-emitting stage. When the light-emitting data voltage is a high voltage, T2 can be turned on in the data writing stage and the light-emitting stage. In the light-emitting stage, when T3 is turned on, EM2 and EM1 are connected, and the light-emitting element E1 emits light for a long time. When T2 is turned on, EM2 and VF are connected, and the light-emitting control voltage HF is input to EM2, and the light-emitting element E1 emits light at high frequency for a short time.

[0056] In at least one embodiment of the present disclosure, when T2 is an n-type transistor, T3 is a p-type transistor, and when T2 is a p-type transistor, T3 is an n-type transistor, in a CMOS (complementary metal oxide semiconductor) or LTPO (low temperature polycrystalline oxide) structure.

[0057] In a specific implementation, if T2 is an oxide transistor, the channel width of T2 may be larger than the channel width of T3, but is not limited thereto.

[0058] The pixel circuit according to at least one embodiment of the present disclosure may further include a data writing circuit, a compensation control circuit, a first initialization circuit, a second initialization circuit, and a third capacitance; the data writing circuit is electrically connected to a second control end, a data line and a first end of the driving circuit respectively, and is used to write the data voltage provided by the data line to the first end of the driving circuit under the control of a second control signal provided by the second control end, and is for writing the data voltage; the compensation control circuit is electrically connected to a third control end, a control end of the driving circuit, and a second end of the driving circuit, respectively, and is used to control the communication between the control end of the driving circuit and the second end of the driving circuit under the control of a third control signal provided by the third control end, and is used to compensate for the threshold voltage of a driving transistor included in the driving circuit; the first initialization circuit is electrically connected to a first reset control terminal, a control terminal of the driving circuit and a third initial voltage terminal respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the control terminal of the driving circuit under the control of a first reset control signal provided by the first reset control terminal, to initialize the potential of the control terminal of the driving circuit; the second initialization circuit is electrically connected to a second reset control terminal, a first pole of the light emitting device, and a fourth initial voltage terminal, respectively, and is used to write a fourth initial voltage provided by the fourth initial voltage terminal to the first pole of the light emitting device under the control of a second reset control signal provided by the second reset control terminal, to initialize the potential of the first pole of the light emitting device; A first end of the third capacitance is electrically connected to the control end of the driving circuit, and a second end of the third capacitance is electrically connected to the first voltage end.

[0059] Optionally, the first initial voltage terminal, the third initial voltage terminal, and the fourth initial voltage terminal may be the same voltage terminal, but are not limited thereto.

[0060] In at least one embodiment of the present disclosure, the third control end and the first control end may be, but are not limited to, the same control end.

[0061] Optionally, the first initialization circuit includes an eighth transistor, the compensation control circuit includes a ninth transistor, the data write circuit includes a tenth transistor, and the second initialization circuit includes an eleventh transistor; a control electrode of the eighth transistor electrically connected to the first reset control terminal, a first electrode of the eighth transistor electrically connected to the third initial voltage terminal, and a second electrode of the eighth transistor electrically connected to the control terminal of the driving circuit; a control pole of the ninth transistor electrically connected to the third control end, a first pole of the ninth transistor electrically connected to the control end of the driving circuit, and a second pole of the ninth transistor electrically connected to the second end of the driving circuit; a control electrode of the tenth transistor electrically connected to the second control end, a first electrode of the tenth transistor electrically connected to the data line, and a second electrode of the tenth transistor electrically connected to a first end of the driving circuit; A control electrode of the eleventh transistor is electrically connected to the second reset control terminal, a first electrode of the eleventh transistor is electrically connected to the fourth initial voltage terminal, and a second electrode of the eleventh transistor is electrically connected to the first electrode of the light-emitting element.

[0062] Optionally, the eighth and ninth transistors are oxide thin film transistors to reduce leakage.

[0063] In at least one embodiment of the present disclosure, at least one of the eighth transistor and the ninth transistor may be a double-gate transistor to reduce leakage.

[0064] Optionally, the light emitting element is, but not limited to, a micro light emitting diode or a mini light emitting diode.

[0065] In at least one embodiment of the present disclosure, the first light-emitting control circuit includes a twelfth transistor; a control electrode of the twelfth transistor electrically connected to the first light-emitting control end, a first electrode of the twelfth transistor electrically connected to the first voltage end, and a second electrode of the twelfth transistor electrically connected to the first end of the driving circuit; the drive circuit includes a drive transistor; The control pole of the driving transistor is electrically connected to the control end of the driving circuit, the first pole of the driving transistor is electrically connected to the first end of the driving circuit, and the second pole of the driving transistor is electrically connected to the second end of the driving circuit.

[0066] As shown in FIG. 6, in addition to at least one embodiment of the pixel circuit shown in FIG. 1 of the present disclosure, the pixel circuit according to at least one embodiment of the present disclosure may further include a data writing circuit 51, a compensation control circuit 52, a first initialization circuit 53, a second initialization circuit 54 and a third capacitance C3, and the light-emitting element is a micro light-emitting diode M1; The data write circuit 51 is electrically connected to a second control end G2, a data line D1 and a first end of the driving circuit 10, respectively, and is used to write the data voltage Vdata provided by the data line D1 to the first end of the driving circuit 10 under the control of a second control signal provided by the second control end G2; The compensation control circuit 52 is electrically connected to a third control end G3, a control end of the driving circuit 10, and a second end of the driving circuit 10, and is used to control the communication between the control end of the driving circuit 10 and the second end of the driving circuit 10 under the control of a third control signal provided by the third control end G3; the first initialization circuit 53 is electrically connected to the first reset control terminal R1, the control terminal of the driving circuit 10 and the third initial voltage terminal I3 respectively, and is used to write the third initial voltage provided by the third initial voltage terminal I3 into the control terminal of the driving circuit 10 under the control of the first reset control signal provided by the first reset control terminal R1, to initialize the potential of the control terminal of the driving circuit 10; The second initialization circuit 54 is electrically connected to the second reset control terminal R2, the anode of the micro LED M1 and the fourth initial voltage terminal I4, and is used to write the fourth initial voltage provided by the fourth initial voltage terminal I4 to the anode of the micro LED M1 under the control of the second reset control signal provided by the second reset control terminal R2; A first end of the third capacitor C3 is electrically connected to the control end of the driving circuit 10, and a second end of the third capacitor C3 is electrically connected to the first voltage end V1.

[0067] In at least one embodiment of the pixel circuit shown in FIG. 6, the first initial voltage end, the third initial voltage end and the fourth initial voltage end may be the same voltage end, the first voltage end may be a high voltage end, and the first control end and the third control end may be the same control end, but are not limited thereto.

[0068] As shown in FIG. 7A, in addition to at least one embodiment of the pixel circuit shown in FIG. 6, the light emission gating circuit further includes a first capacitance C1, and the driving circuit 10 includes a driving transistor T0; a first end of the first capacitance C1 electrically connected to the gating control end ch, and a second end of the first capacitance C1 electrically connected to a first initial voltage end I1, which is used to supply a first initial voltage Vini1; The first gating control circuit 122 includes a first transistor T1, a second transistor T2, and a third transistor T3; The gate of the first transistor T1 is electrically connected to the first control end G1, the source of the first transistor T1 is electrically connected to the light-emitting data voltage end DT, and the drain of the first transistor T1 is electrically connected to the gating control end ch; The gate of the second transistor T2 is electrically connected to the gating control terminal ch, the source of the second transistor T2 is electrically connected to the light-emitting control voltage terminal VF, and the drain of the second transistor T2 is electrically connected to the second light-emitting control terminal EM2, and the light-emitting control voltage terminal VF is used to supply the light-emitting control voltage HF; The gate of the third transistor T3 is electrically connected to the gating control end ch, the source of the third transistor T3 is electrically connected to the first light-emitting control end EM1, and the drain of the third transistor T3 is electrically connected to the second light-emitting control end EM2; The second light-emitting control circuit 121 includes a fourth transistor T4, The gate of the fourth transistor T4 is electrically connected to the second light-emitting control end EM2, the source of the fourth transistor T4 is electrically connected to the second end of the driving circuit 10, the drain of the fourth transistor T4 is electrically connected to the anode of the micro light-emitting diode M1, and the cathode of the micro light-emitting diode M1 is electrically connected to the low voltage end VSS; The first initialization circuit 53 includes an eighth transistor T8, the compensation control circuit 52 includes a ninth transistor T9, the data write circuit 51 includes a tenth transistor T10, and the second initialization circuit 54 includes an eleventh transistor T11. The gate of the eighth transistor T8 is electrically connected to the first reset control end R1, the source of the eighth transistor T8 is electrically connected to the first initial voltage end I1, and the drain of the eighth transistor T8 is electrically connected to the gate of the driving transistor T0; The gate of the ninth transistor T9 is electrically connected to the first control end G1, the source of the ninth transistor T9 is electrically connected to the gate of the driving transistor T0, and the drain of the ninth transistor T9 is electrically connected to the drain of the driving transistor T0; The gate of the tenth transistor T10 is electrically connected to the second control end G2, the source of the tenth transistor T10 is electrically connected to the data line D1, and the gate of the tenth transistor T10 is electrically connected to the source of the driving transistor T0; The gate of the eleventh transistor T11 is electrically connected to the second reset control end R2, the source of the eleventh transistor T11 is electrically connected to the first initial voltage end I1, and the drain of the eleventh transistor T11 is electrically connected to the anode of the micro light-emitting diode M1; The first light-emitting control circuit 11 includes a twelfth transistor T12, The gate of the twelfth transistor T12 is electrically connected to the first light-emitting control end EM1, the source of the twelfth transistor T12 is electrically connected to the high-voltage end VDD, and the drain of the twelfth transistor T12 is electrically connected to the source of the driving transistor T0.

[0069] In FIG. 7A, symbol N1 is a first node, and the first node N1 is electrically connected to the gate of T0.

[0070] In at least one embodiment of the pixel circuit shown in FIG. 7A, T1 is an n-type transistor, T2 is a p-type transistor, T3 is an n-type transistor, and T4 is a p-type transistor, but is not limited to this.

[0071] In at least one embodiment of the pixel circuit shown in FIG. 7A, the first voltage end is a high voltage end VDD, the second voltage end is a low voltage end VSS, the first control end and the third control end are the same control end, and the first initial voltage end, the third initial voltage end and the fourth initial voltage end are the same voltage end.

[0072] In at least one embodiment of the pixel circuit shown in FIG. 7A, T12, T0, T10, and T11 are p-type transistors, T8 and T9 are n-type transistors, and T12, T0, T10, and T11 are low-temperature polysilicon thin-film transistors, but are not limited to such.

[0073] In at least one embodiment shown in FIG. 7A, T8 and T9 are oxide thin film transistors to reduce leakage and facilitate maintaining the potential on the gate of T0.

[0074] In at least one embodiment of the pixel circuit shown in FIG. 7A, T2 and T3 form an inverter-like structure, and the first light-emitting control signal and light-emitting control voltage HF provided by EM1 are respectively input signals to both sides of the inverter-like structure.

[0075] In at least one embodiment of the pixel circuit shown in FIG. 7A, T8 may be replaced with a p-type transistor, T9 may be replaced with a p-type transistor, and T10 may be replaced with an n-type transistor, but is not limited to this.

[0076] In at least one embodiment of the pixel circuit shown in FIG. 7A, T1 may be replaced with a p-type transistor, in which case the signal applied to the gate of T1 may be inverted, without limitation.

[0077] In at least one embodiment of the present disclosure, T0 is a driving transistor, and the channel length of T0 may be increased, for example, the channel length of T0 may be 10 um or more and 30 um or less, and since T4 and T12 are on the light-emitting current path, the channel width of T4 and the channel width of T12 may be appropriately increased, for example, the channel width of T4 and the channel width of T12 may be 5 um or more and 10 um or less.

[0078] In at least one embodiment of the pixel circuit shown in FIG. 7A of the present disclosure, except for T0, T4, and T12, the other transistors are all switch transistors, and if the switch transistor is a low-temperature polysilicon thin-film transistor, the channel width-to-length ratio of the switch transistor may be 3 um / 3 um, and if the switch transistor is an oxide thin-film transistor, the channel width-to-length ratio of the switch transistor may be within a variation range centered around 5 um / 5 um, but is not limited thereto.

[0079] 7B, in addition to at least one embodiment of the pixel circuit shown in FIG. 7A, the coupling capacitance may include: a first coupling capacitance Co1 between the gate of T0 and the signal line; a second coupling capacitance Co2 between the gate of T4 and the signal line; A third coupling capacitance Co3 between the gate of T2 and the signal line is increased. The signal line may be at least one of a data line, a first control end, a second control end, a first reset control end, and a second reset control end.

[0080] As shown in FIG. 8, during operation of at least one embodiment of the pixel circuit shown in FIG. 7A of the present disclosure, a first display period includes a first initialization step S11, a first data writing step S12, and a first light-emitting step S13, which are sequentially set, In the first initialization step S11, R1 supplies a high voltage signal, R2 supplies a low voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a high voltage signal, T8 and T11 are turned on, and the first initial voltage terminal I1 supplies a first initial voltage Vini1 to the gate of T0 and the anode of M1, so that at the start of the first data writing step S12, T0 is turned on to remove residual charge from the anode of M1; In the first initialization step S11, T9 is turned off, T10 is turned off, and T12 is turned off. In the first data write step S12, R1 provides a low voltage signal, R2 provides a high voltage signal, G1 provides a high voltage signal, G2 provides a low voltage signal, EM1 provides a high voltage signal, D1 provides a data voltage Vdata, DT provides a high voltage signal, and T10 turns on, so that Vdata is written into the source of T0; At the beginning of the first data writing step S12, T0 is turned on, T9 is turned on, and C3 is charged by Vdata, thereby changing the potential of the gate of T0 until T0 is turned off, and the gate potential of T0 is related to the threshold voltage of T0; In the first data write step S12, T8 and T11 are turned off, T12 is turned off, and T1 is turned on, so that DT and ch are connected, and the potential of ch becomes a high voltage. T3 is turned on, and T2 is turned off, so that EM1 and EM2 are connected. In the first light-emitting stage S13, R1 supplies a low voltage signal, R2 supplies a high voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a low voltage signal, T12 is turned on, C1 maintains the potential of ch at a high voltage, T2 is turned off, and T3 is turned on, thereby controlling the communication between EM1 and EM2, the potential of EM2 becomes a low voltage signal, T4 is turned on, and T0 drives M1 to emit light, thereby performing long-term light emission by PAM; The second display period includes a second initialization step S21, a second data writing step S22, and a second light-emitting step S23, which are set in sequence. In the second initialization step S21, R1 supplies a high voltage signal, R2 supplies a low voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a high voltage signal, T8 and T11 are turned on, and the first initial voltage terminal I1 supplies a first initial voltage Vini1 to the gate of T0 and the anode of M1, so that at the start of the first data writing step S12, T0 is turned on and the residual charge on the anode of M1 can be removed; In the second initialization step S21, T9 is turned off, T10 is turned off, and T12 is turned off; In the second data write step S22, R1 provides a low voltage signal, R2 provides a high voltage signal, G1 provides a high voltage signal, G2 provides a low voltage signal, EM1 provides a high voltage signal, D1 provides a data voltage Vdata, DT provides a low voltage signal, and T10 turns on, so that Vdata is written into the source of T0; At the start of the second data write step S22, T0 is turned on, T9 is turned on, and C3 is charged by Vdata, thereby changing the potential of the gate of T0 until T0 is turned off, and the gate potential of T0 is related to the threshold voltage of T0; In the second data write step S22, T8 and T11 are turned off, T12 is turned off, and T1 is turned on, so that DT and ch are connected, and the potential of ch becomes a low voltage. T2 is turned on, and T3 is turned off, so that HF ​​is input to EM2. In the second light-emitting stage S23, R1 supplies a low voltage signal, R2 supplies a high voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a low voltage signal, T12 turns on, C1 maintains the potential of ch at a low voltage, T2 turns on, and T3 turns off, thereby controlling HF to be input to EM2, and when the voltage value of HF is low voltage, T4 turns on, and when T4 turns on, T0 drives M1 to emit light, thereby performing high-frequency short-time light emission by PWM and displaying low gradations.

[0081] As shown in FIG. 8, the pulse width of the first reset control signal supplied by R1, the pulse width of the second reset control signal supplied by R2, the pulse width of the first control signal supplied by G1, and the pulse width of the second control signal supplied by G2 may be the same, and the pulse width of the data voltage supplied by D1 and the pulse width of the light-emitting data voltage supplied by DT are the same, and at the rising edge of the second control signal supplied by G2, D1 supplies the data voltage, and at the falling edge of the first control signal supplied by G1, DT supplies the light-emitting data voltage.

[0082] As shown in FIG. 8, when the first reset control signal supplied by R1 is a high voltage, the second reset control signal supplied by R2 is a low voltage, G1 supplies a high voltage, and G2 supplies a low voltage, the potential of HF becomes a high voltage.

[0083] FIG. 9 is a simulated operational timing diagram of at least one embodiment of the pixel circuit shown in FIG. 7A of the present disclosure. In FIG. 9, the symbol Ie denotes the current flowing through M1.

[0084] At least one embodiment of the pixel circuit shown in FIG. 10 of the present disclosure differs from at least one embodiment of the pixel circuit shown in FIG. 6 of the present disclosure in that the source of T10 is electrically connected to DT and the gate of T1 is electrically connected to R1.

[0085] 10 of the present disclosure, the data voltage and the light-emitting data voltage may be combined into one voltage signal. During operation of at least one embodiment of the pixel circuit shown in FIG. 10 of the present disclosure, R1 first supplies a high-voltage signal, and ch is charged by the light-emitting data voltage supplied by DT, and then G2 supplies a low-voltage signal, T10 turns on, and C3 is charged by the data voltage supplied by DT.

[0086] As shown in FIG. 11 , during operation of at least one embodiment of the pixel circuit shown in FIG. 10 of the present disclosure, a first display period includes a first initialization step S11, a first data writing step S12, and a first light-emitting step S13, which are sequentially set, In the first initialization step S11, R1 supplies a high voltage signal, R2 supplies a low voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a high voltage signal, T8 and T11 are turned on, and the first initial voltage terminal I1 supplies a first initial voltage Vini1 to the gate of T0 and the anode of M1, so that at the start of the first data writing step S12, T0 is turned on to remove the residual charge of the anode of M1, T1 is turned on, DT supplies a light-emitting data voltage, and the light-emitting data voltage supplied by DT becomes a high voltage, and C1 is charged by the light-emitting data voltage, so that the potential of ch becomes a high voltage, T3 is turned on, and T2 is turned off, so that EM1 and EM2 are communicated with each other; In the first initialization step S11, T9 is turned off, T10 is turned off, and T12 is turned off. In the first data write step S12, R1 provides a low voltage signal, R2 provides a high voltage signal, G1 provides a high voltage signal, G2 provides a low voltage signal, EM1 provides a high voltage signal, DT provides a data voltage Vdata, T10 turns on, so that Vdata is written to the source of T0, and T1 turns off; At the beginning of the first data writing step S12, T0 is turned on, T9 is turned on, and C3 is charged by Vdata, thereby changing the potential of the gate of T0 until T0 is turned off, and the gate potential of T0 is related to the threshold voltage of T0; In the first light-emitting stage S13, R1 supplies a low voltage signal, R2 supplies a high voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a low voltage signal, T12 is turned on, C1 maintains the potential of ch at a high voltage, T2 is turned off, and T3 is turned on, thereby controlling the communication between EM1 and EM2, the potential of EM2 becomes a low voltage signal, T4 is turned on, and T0 drives M1 to emit light, thereby performing long-term light emission by PAM; The second display period includes a second initialization step S21, a second data writing step S22, and a second light-emitting step S23, which are set in sequence. In the second initialization step S21, R1 supplies a high voltage signal, R2 supplies a low voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a high voltage signal, T8 and T11 are turned on, the first initial voltage terminal I1 supplies a first initial voltage Vini1 to the gate of T0 and the anode of M1, so that at the start of the third write time step S221, T0 is turned on to remove the residual charge of the anode of M1, DT supplies a light-emitting data voltage, and the light-emitting data voltage supplied by DT becomes a low voltage, T8 and T11 are turned off, T12 is turned off, and T1 is turned on to connect DT to ch, and the potential of ch becomes a low voltage, T2 is turned on, and T3 is turned off to input HF to EM2, In the second initialization step S21, T9 is turned off, T10 is turned off, and T12 is turned off; In the second data write step S22, R1 provides a low voltage signal, R2 provides a high voltage signal, G1 provides a high voltage signal, G2 provides a low voltage signal, EM1 provides a high voltage signal, DT provides a data voltage Vdata, and T10 turns on, so that Vdata is written to the source of T0; At the start of the second data write step S221, T0 is turned on, T9 is turned on, and C3 is charged by Vdata, thereby changing the potential of the gate of T0 until T0 is turned off, and the gate potential of T0 is related to the threshold voltage of T0; In the second light-emitting stage S23, R1 supplies a low voltage signal, R2 supplies a high voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a low voltage signal, T12 turns on, C1 maintains the potential of ch at a low voltage, T2 turns on, and T3 turns off, thereby controlling HF to be input to EM2, and when the voltage value of HF is low voltage, T4 turns on, and when T4 turns on, T0 drives M1 to emit light, thereby performing high-frequency short-time light emission by PWM and displaying low gradations.

[0087] At least one embodiment of the pixel circuit shown in FIG. 12 of the present disclosure differs from at least one embodiment of the pixel circuit shown in FIG. 10 of the present disclosure in that T11 is an n-type transistor and the gate of T11 is electrically connected to R1.

[0088] In at least one embodiment of the pixel circuit shown in FIG. 12 of the present disclosure, if T9, T8, and T11 are connected in series with each other and T9, T8, and T11 are all oxide thin film transistors, the fabrication process may be relatively simple.

[0089] At least one embodiment of the pixel circuit shown in FIG. 13 of the present disclosure differs from at least one embodiment of the pixel circuit shown in FIG. 7A of the present disclosure in that T8 and T9 are both double-gate transistors to reduce leakage and facilitate maintaining the potential of the gate of T0, and T8 and T9 are oxide thin-film transistors.

[0090] At least one embodiment of the pixel circuit shown in FIG. 14 of the present disclosure differs from at least one embodiment of the pixel circuit shown in FIG. 7A of the present disclosure in that T8 and T9 are both double-gate transistors to reduce leakage and facilitate maintaining the potential of the gate of T0, and T8 and T9 are low-temperature polysilicon thin-film transistors.

[0091] At least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure differs from at least one embodiment of the pixel circuit shown in FIG. 7A of the present disclosure in that T2 is an n-type transistor and T3 is a p-type transistor.

[0092] In at least one embodiment of the pixel circuit shown in FIG. 15, T8 may be replaced with a p-type transistor, T9 may be replaced with a p-type transistor, and T10 may be replaced with an n-type transistor, but is not limited to this.

[0093] As shown in FIG. 16 , during operation of at least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure, a first display period includes a first initialization step S11, a first data writing step S12, and a first light-emitting step S13, which are sequentially set, In the first initialization step S11, R1 supplies a high voltage signal, R2 supplies a low voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a high voltage signal, T8 and T11 are turned on, and the first initial voltage terminal I1 supplies a first initial voltage Vini1 to the gate of T0 and the anode of M1, so that at the start of the first data writing step S12, T0 is turned on to remove residual charge from the anode of M1; In the first initialization step S11, T9 is turned off, T10 is turned off, and T12 is turned off. In the first data write step S12, R1 provides a low voltage signal, R2 provides a high voltage signal, G1 provides a high voltage signal, G2 provides a low voltage signal, EM1 provides a high voltage signal, D1 provides a data voltage Vdata, DT provides a low voltage signal, and T10 turns on, so that Vdata is written into the source of T0; At the beginning of the first data writing step S12, T0 is turned on, T9 is turned on, and C3 is charged by Vdata, thereby changing the potential of the gate of T0 until T0 is turned off, and the gate potential of T0 is related to the threshold voltage of T0; In the first data write step S12, T8 and T11 are turned off, T12 is turned off, and T1 is turned on, so that DT and ch are connected, the potential of ch becomes a low voltage, T3 is turned on, and T2 is turned off, so that EM1 and EM2 are connected, In the first light-emitting stage S13, R1 supplies a low voltage signal, R2 supplies a high voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a low voltage signal, T12 turns on, C1 maintains the potential of ch at a low voltage, T2 turns off, and T3 turns on, thereby controlling communication between EM1 and EM2, the potential of EM2 becomes a low voltage signal, T4 turns on, and T0 drives M1 to emit light, thereby performing long-term light emission by PAM; The second display period includes a second initialization step S21, a second data writing step S22, and a second light-emitting step S23, which are set in sequence. In the second initialization step S21, R1 supplies a high voltage signal, R2 supplies a low voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a high voltage signal, T8 and T11 are turned on, and the first initial voltage terminal I1 supplies a first initial voltage Vini1 to the gate of T0 and the anode of M1, so that at the start of the first data writing step S12, T0 is turned on and the residual charge on the anode of M1 can be removed; In the second initialization step S21, T9 is turned off, T10 is turned off, and T12 is turned off; In the second data write step S22, R1 supplies a low voltage signal, R2 supplies a high voltage signal, G1 supplies a high voltage signal, G2 supplies a low voltage signal, EM1 supplies a high voltage signal, D1 supplies a data voltage Vdata, DT supplies a high voltage signal, and T10 turns on, so that Vdata is written to the source of T0; At the start of the second data write step S22, T0 is turned on, T9 is turned on, and C3 is charged by Vdata, thereby changing the potential of the gate of T0 until T0 is turned off, and the gate potential of T0 is related to the threshold voltage of T0; In the second data write step S22, T8 and T11 are turned off, T12 is turned off, and T1 is turned on, so that DT and ch are connected, and the potential of ch becomes a high voltage; T2 is turned on, and T3 is turned off, so that HF ​​is input to EM2; In the second light-emitting stage S23, R1 supplies a low voltage signal, R2 supplies a high voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a low voltage signal, T12 turns on, C1 maintains the potential of ch at a high voltage, T2 turns on, and T3 turns off, thereby controlling HF to be input to EM2, and when the voltage value of HF is low voltage, T4 turns on, and when T4 turns on, T0 drives M1 to emit light, thereby performing high-frequency short-time emission by PWM and displaying low gradations.

[0094] 15 of the present disclosure, when the potential of ch is a low voltage in the first data write stage, T3 is turned on, and after the first light-emitting stage is entered, the potential of ch needs to be maintained at the voltage value of the low-voltage signal supplied by DT (this voltage value may be, for example, −9V) to ensure that T3 is turned on. In this case, if the voltage value of the low-voltage signal supplied by G1 is −7V, the potential of ch is likely to increase due to reverse leakage of T1. Therefore, the voltage value of the low-voltage signal supplied by G1 needs to be adjusted from −12V to −9V (if it is necessary to completely turn off T1 and eliminate reverse leakage of ch, the voltage value of the low-voltage signal supplied by G1 needs to be reduced to −12V, but it may also be reduced to −9V in consideration of meeting needs).

[0095] As shown in FIG. 17, during operation of at least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure, the lower the potential of ch, the lower the potential of EM2.

[0096] FIG. 18 is a simulated operational timing diagram of at least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure. In FIGS. 9 and 18, the symbol Ie denotes the current flowing through M1.

[0097] At least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure differs from at least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure in that the source of T10 is electrically connected to DT and the gate of T1 is electrically connected to R1.

[0098] In at least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure, the data voltage and the light emission data voltage may be combined into one voltage signal.

[0099] As shown in FIG. 20 , during operation of at least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure, a first display period includes a first initialization step S11, a first data writing step S12, and a first light-emitting step S13, which are sequentially set, In the first initialization step S11, R1 supplies a high voltage signal, R2 supplies a low voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a high voltage signal, T8 and T11 are turned on, and the first initial voltage terminal I1 supplies a first initial voltage Vini1 to the gate of T0 and the anode of M1, so that at the start of the first data writing step S121, T0 is turned on to remove the residual charge of the anode of M1; In the first initialization step S11, T9 is turned off, T10 is turned off, and T12 is turned off. In the first initialization step S11, T1 is turned on, DT supplies a light emitting data voltage, the light emitting data voltage supplied by DT becomes a low voltage, T8 and T11 are turned off, T12 is turned off, and T1 is turned on, thereby controlling the communication between DT and ch, the potential of ch becomes a low voltage, T3 is turned on, and T2 is turned off, thereby controlling the communication between EM1 and EM2, In the first data write step S12, R1 provides a low voltage signal, R2 provides a high voltage signal, G1 provides a low voltage signal, G2 provides a low voltage signal, EM1 provides a high voltage signal, DT provides a data voltage Vdata, T10 turns on, so that Vdata is written to the source of T0, and T1 turns off; At the beginning of the first data writing step S12, T0 is turned on, T9 is turned on, and C3 is charged by Vdata, thereby changing the potential of the gate of T0 until T0 is turned off, and the gate potential of T0 is related to the threshold voltage of T0; In the first light-emitting stage S13, R1 supplies a low voltage signal, R2 supplies a high voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a low voltage signal, T12 is turned on, C1 maintains the potential of ch at a high voltage, T2 is turned off, and T3 is turned on, thereby controlling the communication between EM1 and EM2, the potential of EM2 becomes a low voltage signal, T4 is turned on, and T0 drives M1 to emit light, thereby performing long-term light emission by PAM; The second display period includes a second initialization step S21, a second data writing step S22, and a second light-emitting step S23, which are set in sequence. In the second initialization stage S21, R1 supplies a high voltage signal, R2 supplies a low voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a high voltage signal, T8 and T11 are turned on, and the first initial voltage terminal I1 supplies a first initial voltage Vini1 to the gate of T0 and the anode of M1, so that at the beginning of the third write time stage S221, T0 is turned on to remove the residual charge on the anode of M1; In the second initialization step S21, T9 is turned off, T10 is turned off, and T12 is turned off; In the second initialization step S21, T1 is turned on, DT supplies the light emission data voltage, the light emission data voltage supplied by DT becomes a high voltage, T8 and T11 are turned off, T12 is turned off, and T1 is turned on, so that DT and ch are connected, and the potential of ch becomes a high voltage, T2 is turned on, and T3 is turned off, so that HF ​​is input to EM2, In the second data write step S22, R1 provides a low voltage signal, R2 provides a high voltage signal, G1 provides a low voltage signal, G2 provides a low voltage signal, EM1 provides a high voltage signal, DT provides a data voltage Vdata, and T10 turns on, so that Vdata is written to the source of T0; At the start of the second data write step S22, T0 is turned on, T9 is turned on, and C3 is charged by Vdata, thereby changing the potential of the gate of T0 until T0 is turned off, and the gate potential of T0 is related to the threshold voltage of T0; In the second light-emitting stage S23, R1 supplies a low voltage signal, R2 supplies a high voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a low voltage signal, T12 turns on, C1 maintains the potential of ch at a low voltage, T2 turns on, and T3 turns off, thereby controlling HF to be input to EM2, and when the voltage value of HF is low voltage, T4 turns on, and when T4 turns on, T0 drives M1 to emit light, thereby performing high-frequency short-time light emission by PWM and displaying low gradations.

[0100] At least one embodiment of the pixel circuit shown in FIG. 21 of the present disclosure differs from at least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure in that T8 and T9 are both double-gate transistors to reduce leakage and facilitate maintaining the potential of the gate of T0, and T8 and T9 are oxide thin-film transistors.

[0101] At least one embodiment of the pixel circuit shown in FIG. 22 of the present disclosure differs from at least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure in that T8 and T9 are both double-gate transistors to reduce leakage and facilitate maintaining the potential of the gate of T0, and T8 and T9 are low-temperature polysilicon thin-film transistors.

[0102] At least one embodiment of the pixel circuit shown in FIG. 23 of the present disclosure differs from at least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure in that T1 is a p-type transistor, and the gate of T1 is electrically connected to the second control end G2.

[0103] In at least one embodiment of the pixel circuit shown in FIG. 23, the first control terminal and the second control terminal are the same control terminal, and the gate of T0 and the gating control terminal ch are simultaneously charged by D1 and DT, respectively.

[0104] In at least one embodiment of the pixel circuit shown in FIG. 23, T8 may be replaced with a p-type transistor, T9 may be replaced with a p-type transistor, and T10 may be replaced with an n-type transistor, but is not limited to this.

[0105] As shown in FIG. 24 , during operation of at least one embodiment of the pixel circuit shown in FIG. 23 of the present disclosure, a first display period includes a first initialization step S11, a first data writing step S12, and a first light-emitting step S13, which are sequentially set, In the first initialization step S11, R1 supplies a high voltage signal, R2 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a high voltage signal, T8 and T11 are turned on, and the first initial voltage terminal I1 supplies a first initial voltage Vini1 to the gate of T0 and the anode of M1, so that at the start of the first data writing step S12, T0 is turned on to remove the residual charge on the anode of M1; In the first initialization step S11, T9 is turned off, T10 is turned off, and T12 is turned off. In the first data write step S12, R1 provides a low voltage signal, R2 provides a high voltage signal, G2 provides a low voltage signal, EM1 provides a high voltage signal, D1 provides a data voltage Vdata, DT provides a low voltage signal, and T10 turns on, so that Vdata is written into the source of T0; At the beginning of the first data writing step S12, T0 is turned on, T9 is turned on, and C3 is charged by Vdata, thereby changing the potential of the gate of T0 until T0 is turned off, and the gate potential of T0 is related to the threshold voltage of T0; In the first data write step S12, T8 and T11 are turned off, T12 is turned off, and T1 is turned on, so that DT and ch are connected, the potential of ch becomes a low voltage, T3 is turned on, and T2 is turned off, so that EM1 and EM2 are connected, In the first light-emitting stage S13, R1 supplies a low voltage signal, R2 supplies a high voltage signal, G2 supplies a high voltage signal, EM1 supplies a low voltage signal, T12 turns on, C1 maintains the potential of ch at a low voltage, T2 turns off, and T3 turns on, thereby controlling the communication between EM1 and EM2, the potential of EM2 becomes a low voltage signal, T4 turns on, and T0 drives M1 to emit light, thereby performing long-term light emission by PAM; The second display period includes a second initialization step S21, a second data writing step S22, and a second light-emitting step S23, which are set in sequence. In the second initialization step S21, R1 supplies a high voltage signal, R2 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a high voltage signal, T8 and T11 are turned on, and the first initial voltage terminal I1 supplies a first initial voltage Vini1 to the gate of T0 and the anode of M1, so that at the start of the first data writing step S12, T0 is turned on and the residual charge on the anode of M1 can be removed; In the second initialization step S21, T9 is turned off, T10 is turned off, and T12 is turned off; In the second data write step S22, R1 provides a low voltage signal, R2 provides a high voltage signal, G2 provides a low voltage signal, EM1 provides a high voltage signal, D1 provides a data voltage Vdata, DT provides a high voltage signal, and T10 turns on, so that Vdata is written into the source of T0; At the start of the second data write step S22, T0 is turned on, T9 is turned on, and C3 is charged by Vdata, thereby changing the potential of the gate of T0 until T0 is turned off, and the gate potential of T0 is related to the threshold voltage of T0; In the second data write step S22, T8 and T11 are turned off, T12 is turned off, and T1 is turned on, so that DT and ch are connected, and the potential of ch becomes a high voltage; T2 is turned on, and T3 is turned off, so that HF ​​is input to EM2; In the second light-emitting stage S23, R1 supplies a low voltage signal, R2 supplies a high voltage signal, G2 supplies a high voltage signal, EM1 supplies a low voltage signal, T12 turns on, C1 maintains the potential of ch at a high voltage, T2 turns on, and T3 turns off, thereby controlling HF to be input to EM2, and when the voltage value of HF is low voltage, T4 turns on, and when T4 turns on, T0 drives M1 to emit light, thereby performing high-frequency short-time light emission by PWM and displaying low gradations.

[0106] At least one embodiment of the pixel circuit shown in FIG. 25 of the present disclosure differs from at least one embodiment of the pixel circuit shown in FIG. 23 of the present disclosure in that the gate of T1 is electrically connected to R2 and the source of T10 is electrically connected to DT.

[0107] As shown in FIG. 26 , during operation of at least one embodiment of the pixel circuit shown in FIG. 25 of the present disclosure, the first display period includes a first initialization stage S11, a first data writing stage S12, and a first light-emitting stage S13, which are set in sequence; In the first initialization step S11, R1 supplies a high voltage signal, R2 supplies a low voltage signal, G1 supplies a high voltage signal, G2 supplies a high voltage signal, EM1 supplies a high voltage signal, T8 and T11 are turned on, and the first initial voltage terminal I1 supplies a first initial voltage Vini1 to the gate of T0 and the anode of M1, so that at the start of the first data writing step S12, T0 is turned on to remove the residual charge of the anode of M1; In the first initialization stage S11, DT supplies a light emitting data voltage, the light emitting data voltage supplied by DT becomes a low voltage, T8 and T11 are turned off, T12 is turned off, and T1 is turned on, so that DT and ch are connected to each other, the potential of ch becomes a low voltage, T3 is turned on, and T2 is turned off, so that EM1 and EM2 are connected to each other, In the first initialization step S11, T9 is turned off, T10 is turned off, and T12 is turned off. In the first data write step S12, R1 provides a low voltage signal, R2 provides a high voltage signal, G1 provides a high voltage signal, G2 provides a low voltage signal, EM1 provides a high voltage signal, DT provides a data voltage Vdata, T10 turns on, so that Vdata is written to the source of T0, and T1 turns off; At the beginning of the first data writing step S12, T0 is turned on, T9 is turned on, and C3 is charged by Vdata, thereby changing the potential of the gate of T0 until T0 is turned off, and the gate potential of T0 is related to the threshold voltage of T0; In the first light-emitting stage S13, R1 supplies a low voltage signal, R2 supplies a high voltage signal, G1 supplies a high voltage signal, G2 supplies a high voltage signal, EM1 supplies a low voltage signal, T12 turns on, C1 maintains the potential of ch at a high voltage, T2 turns off, and T3 turns on, thereby controlling the communication between EM1 and EM2, the potential of EM2 becomes a low voltage signal, T4 turns on, and T0 drives M1 to emit light, thereby performing long-term light emission by PAM; The second display period includes a second initialization step S21, a second data writing step S22, and a second light-emitting step S23, which are set in sequence. In the second initialization stage S21, R1 supplies a high voltage signal, R2 supplies a low voltage signal, G1 supplies a high voltage signal, G2 supplies a high voltage signal, EM1 supplies a high voltage signal, T8 and T11 are turned on, and the first initial voltage terminal I1 supplies a first initial voltage Vini1 to the gate of T0 and the anode of M1, so that at the beginning of the third write time stage S221, T0 is turned on to remove the residual charge on the anode of M1; In the second initialization step S21, T9 is turned off, T10 is turned off, and T12 is turned off; In the second initialization step S21, DT supplies a light emission data voltage, the light emission data voltage supplied by DT becomes a high voltage, T8 and T11 are turned off, T12 is turned off, and T1 is turned on, so that DT and ch are connected, the potential of ch becomes a high voltage, T2 is turned on, and T3 is turned off, so that HF ​​is input to EM2, In the second data write step S22, R1 provides a low voltage signal, R2 provides a high voltage signal, G1 provides a high voltage signal, G2 provides a low voltage signal, EM1 provides a high voltage signal, DT provides a data voltage Vdata, and T10 turns on, so that Vdata is written to the source of T0; At the start of the second data write step S22, T0 is turned on, T9 is turned on, and C3 is charged by Vdata, thereby changing the potential of the gate of T0 until T0 is turned off, and the gate potential of T0 is related to the threshold voltage of T0; In the second light-emitting stage S23, R1 supplies a low voltage signal, R2 supplies a high voltage signal, G1 supplies a high voltage signal, G2 supplies a high voltage signal, EM1 supplies a low voltage signal, T12 turns on, C1 maintains the potential of ch at a low voltage, T2 turns on, and T3 turns off, thereby controlling HF to be input to EM2, and when the voltage value of HF is low voltage, T4 turns on, and when T4 turns on, T0 drives M1 to emit light, thereby performing high-frequency short-time emission by PWM and displaying low gradations.

[0108] In at least one embodiment of the pixel circuit described in the present disclosure, the capacitance value of C1 electrically connected to the drain of T1 may be reduced or C1 may be removed, which is advantageous for achieving a high PPI (Pixels Per Inch).

[0109] In at least one embodiment of the present disclosure, when T1 is an n-type transistor, T2 is a p-type transistor, and T3 is an n-type transistor, the voltage values ​​of the first initial voltage Vini1 and the low voltage signal provided by VSS may be −2V, the voltage value of the high voltage signal provided by VDD may be 8V, the high voltage value of the first control signal provided by G1 may be 7V, the low voltage value of the first control signal provided by G1 may be −9V, the high voltage value of the first light-emitting control signal provided by EM1 may be 7V, the low voltage value of the first light-emitting control signal provided by EM1 may be −7V, the high voltage value of HF may be 7V, the low voltage value of HF may be −7V, the voltage value of the data voltage provided by D1 may be between 4V and 6V, the high voltage value of the light-emitting data voltage provided by DT may be 5V, and the low voltage value of the light-emitting data voltage provided by DT may be −8V. During the light-emitting phase, DT may provide a voltage signal of 0V, but is not limited thereto.

[0110] In at least one embodiment of the present disclosure, when T1 is an n-type transistor, T2 is an n-type transistor, and T3 is a p-type transistor, the voltage values ​​of the first initial voltage Vini1 and the low voltage signal provided by VSS may be −2V, the voltage value of the high voltage signal provided by VDD may be 8V, the high voltage value of the first control signal provided by G1 may be 10V, the low voltage value of the first control signal provided by G1 may be −12V, the high voltage value of the first light-emitting control signal provided by EM1 may be 7V, the low voltage value of the first light-emitting control signal provided by EM1 may be −7V, the high voltage value of HF may be 7V, the low voltage value of HF may be −7V, the voltage value of the data voltage provided by D1 may be between 4V and 6V, the high voltage value of the light-emitting data voltage provided by DT may be 9V, and the low voltage value of the light-emitting data voltage provided by DT may be −8V. During the light-emitting phase, DT may provide a voltage signal of 0V, but is not limited thereto.

[0111] In at least one embodiment of the present disclosure, when T1 is a p-type transistor, T2 is an n-type transistor, and T3 is a p-type transistor, the voltage values ​​of the first initial voltage Vini1 and the low voltage signal provided by VSS may be −2V, the voltage value of the high voltage signal provided by VDD may be 8V, the high voltage value of the first control signal provided by G1 may be 10V, the low voltage value of the first control signal provided by G1 may be −7V, the high voltage value of the first light-emitting control signal provided by EM1 may be 7V, the low voltage value of the first light-emitting control signal provided by EM1 may be −7V, the high voltage value of HF may be 7V, the low voltage value of HF may be −7V, the voltage value of the data voltage provided by D1 may be between 4V and 6V, the high voltage value of the light-emitting data voltage provided by DT may be 9V, and the low voltage value of the light-emitting data voltage provided by DT may be −7V. During the light-emitting phase, DT may provide a voltage signal of 0V, but is not limited thereto.

[0112] In specific implementation, if the light emitting data voltage provided by DT needs to be a positive value, In at least one embodiment of the present disclosure, when T1 is an n-type transistor, T2 is a p-type transistor, and T3 is an n-type transistor, the voltage values ​​of the first initial voltage Vini1 and the low voltage signal provided by VSS may be -2V, the voltage value of the high voltage signal provided by VDD may be 8V, the high voltage value of the first control signal provided by G1 may be 15V, the low voltage value of the first control signal provided by G1 may be -1V, the high voltage value of the first light-emitting control signal provided by EM1 may be 15V, the low voltage value of the first light-emitting control signal provided by EM1 may be 1V, the high voltage value of HF may be 15V, the low voltage value of HF may be 1V, the voltage value of the data voltage provided by D1 may be between 12V and 14V, the high voltage value of the light-emitting data voltage provided by DT may be 13V, and the low voltage value of the light-emitting data voltage provided by DT may be 0V, but is not limited thereto.

[0113] In specific implementation, if the light emitting data voltage provided by DT needs to be a positive value, In at least one embodiment of the present disclosure, when T1 is an n-type transistor, T2 is an n-type transistor, and T3 is a p-type transistor, the voltage values ​​of the first initial voltage Vini1 and the low voltage signal provided by VSS may be -2V, the voltage value of the high voltage signal provided by VDD may be 8V, the high voltage value of the first control signal provided by G1 may be 18V, the low voltage value of the first control signal provided by G1 may be -4V, the high voltage value of the first light-emitting control signal provided by EM1 may be 15V, the low voltage value of the first light-emitting control signal provided by EM1 may be 1V, the high voltage value of HF may be 15V, the low voltage value of HF may be 1V, the voltage value of the data voltage provided by D1 may be between 12V and 14V, the high voltage value of the light-emitting data voltage provided by DT may be 17V, and the low voltage value of the light-emitting data voltage provided by DT may be 0V, but is not limited thereto.

[0114] In specific implementation, if the light emitting data voltage provided by DT needs to be a positive value, When T1 is a p-type transistor, T2 is an n-type transistor, and T3 is a p-type transistor, the voltage values ​​of the first initial voltage Vini1 and the low voltage signal provided by VSS may be -2V, the voltage value of the high voltage signal provided by VDD may be 8V, the high voltage value of the first control signal provided by G1 may be 17V, the low voltage value of the first control signal provided by G1 may be 0V, the high voltage value of the first light-emitting control signal provided by EM1 may be 15V, the low voltage value of the first light-emitting control signal provided by EM1 may be 1V, the high voltage value of HF may be 15V, the low voltage value of HF may be 1V, the voltage value of the data voltage provided by D1 may be between 12V and 14V, the high voltage value of the light-emitting data voltage provided by DT may be 16V, and the low voltage value of the light-emitting data voltage provided by DT may be 0V, but is not limited thereto.

[0115] In at least one embodiment of the present disclosure, when T1 is an n-type transistor, T2 is a p-type transistor, and T3 is an n-type transistor, In PWM dimming mode, during the low voltage maintenance phase of ch, T1 requires a lower turn-off voltage, so the low voltage value of the first control signal provided by G1 needs to be adjusted lower; In PAM dimming mode, the high voltage of HF can be input to EM2 instead of the high voltage of EM1, which is advantageous in reducing the high voltage value of the first control signal provided by G1 and the high voltage value of the light emission data voltage provided by DT.

[0116] In at least one embodiment of the present disclosure, when T1 is an n-type transistor, T2 is an n-type transistor, and T3 is a p-type transistor, When the light-emitting data voltage provided by DT is low voltage, it needs to turn on T3 to meet the requirement of passing the low-voltage signal provided by EM1; When the light-emitting data voltage provided by DT is a high voltage, turning on T2 must meet the requirement of passing the high voltage of HF, so the span between the high voltage and the low voltage of the light-emitting data voltage provided by DT becomes large. The requirement for the high voltage value of the first control signal provided by G1 is also large, and in addition, in the low voltage maintaining phase of ch, the low voltage value of the first control signal provided by G1 needs to be lower to turn off T1, so the span between the high voltage and the low voltage of the first control signal provided by G1 becomes large.

[0117] In at least one embodiment of the present disclosure, when T1 is a p-type transistor, T2 is an n-type transistor, and T3 is a p-type transistor, In PWM dimming mode, during the high voltage maintenance phase of channel, T1 requires a higher turn-off voltage, Increasing the turn-off voltage of the first control signal provided by G1 increases the stress experienced by T1 during the PAM light-emitting phase.

[0118] In at least one embodiment of the present disclosure, the light-emitting gating circuit includes a second gating control circuit, a third light-emitting control circuit and a fourth light-emitting control circuit; the second gating control circuit is electrically connected to the first control end, the light emitting data voltage end and the gating control end respectively, and is used to control the light emitting data voltage to be written to the gating control end under the control of the first control signal; the third light-emitting control circuit is electrically connected to the gating control terminal, the second pole and the second voltage terminal of the light-emitting element, respectively, and is used to control the second pole of the light-emitting element to communicate with the second voltage terminal under the control of the potential of the gating control terminal; The fourth light-emitting control circuit is electrically connected to the light-emitting control voltage terminal and the second pole and second voltage terminal of the light-emitting element, respectively, and is used to control the communication between the second pole of the light-emitting element and the second voltage terminal under the control of the light-emitting control voltage supplied by the light-emitting control voltage terminal.

[0119] During operation of the pixel circuit described in at least one embodiment of the present disclosure, the second gating control circuit writes an emission data voltage to the gating control terminal under the control of the first control signal; during the emission stage, the third emission control circuit controls the potential of the gating control terminal to connect the second pole of the light-emitting element to the second voltage terminal, thereby realizing long-term emission by PAM; and during the emission stage, the fourth emission control circuit controls the emission control voltage (the emission control voltage is a high-frequency PWM signal) to realize high-frequency short-term emission, thereby performing low-gradation display.

[0120] As shown in FIG. 27, a pixel circuit according to at least one embodiment of the present disclosure includes a first light-emitting control circuit 11, a light-emitting element E1, a driving circuit 10, and a light-emitting gating circuit; the first light-emitting control circuit 11 is electrically connected to a first light-emitting control end EM1, a first voltage end V1 and a first end of the driving circuit 10, and is used to control the communication between the first voltage end V1 and the first end of the driving circuit 10 under the control of a first light-emitting control signal provided by the first light-emitting control end EM1 in a light-emitting stage; a second end of the driving circuit 10 electrically connected to a first electrode of the light-emitting element E1, and the driving circuit 10 is used to drive the light-emitting element E1; The light-emitting gating circuit includes a second gating control circuit 61, a third light-emitting control circuit 63, and a fourth light-emitting control circuit 64; The second gating control circuit 61 is electrically connected to the first control end G1, the light emitting data voltage end DT and the gating control end ch, and is used to write the light emitting data voltage provided by the light emitting data voltage end DT to the gating control end ch under the control of the first control signal provided by the first control end G1; the third light-emitting control circuit 63 is electrically connected to the gating control terminal ch, the second pole of the light-emitting element E1, and the second voltage terminal V2, respectively, and is used to control the communication between the second pole of the light-emitting element E1 and the second voltage terminal V2 under the control of the potential of the gating control terminal ch; The fourth light-emitting control circuit 64 is electrically connected to the light-emitting control voltage terminal VF, the second pole of the light-emitting element E1, and the second voltage terminal V2, respectively, and is used to control the communication between the second pole of the light-emitting element E1 and the second voltage terminal V2 under the control of the light-emitting control voltage HF supplied by the light-emitting control voltage terminal VF.

[0121] In at least one embodiment of the present disclosure, the first voltage end may be a high voltage end, and the second voltage end may be a low voltage end, but is not limited thereto.

[0122] As shown in FIG. 28 , in addition to at least one embodiment of the pixel circuit shown in FIG. 27 , the pixel circuit according to at least one embodiment of the present disclosure may further include a fifth light-emitting control circuit 65, The fifth light-emitting control circuit 65 is electrically connected to the first light-emitting control terminal EM1, the second terminal of the driving circuit 10, and the first terminal of the light-emitting element E1, respectively, and is used to control the communication between the second terminal of the driving circuit 10 and the first terminal of the light-emitting element E1 under the control of the first light-emitting control signal.

[0123] Optionally, the light emission gating circuit further includes a second capacitance; A first end of the second capacitance is electrically connected to the gating control end, and a second end of the second capacitance is electrically connected to a first initial voltage end, and the second capacitance can be used to maintain the potential of the gating control end.

[0124] Optionally, the second gating control circuit includes a fifth transistor, the third light-emitting control circuit includes a sixth transistor, and the fourth light-emitting control circuit includes a seventh transistor; a control electrode of the fifth transistor electrically connected to the first control end, a first electrode of the fifth transistor electrically connected to the light-emitting data voltage end, and a second electrode of the fifth transistor electrically connected to the gating control end; a control electrode of the sixth transistor electrically connected to the gating control terminal, a first electrode of the sixth transistor electrically connected to the second electrode of the light-emitting element, and a second electrode of the sixth transistor electrically connected to the second voltage terminal; The control electrode of the seventh transistor is electrically connected to the light-emitting control voltage terminal, the first electrode of the seventh transistor is electrically connected to the second electrode of the light-emitting element, and the second electrode of the seventh transistor is electrically connected to the second voltage terminal.

[0125] Alternatively, the seventh transistor is a p-type transistor, the sixth transistor is an n-type transistor, and the fifth transistor is an n-type transistor; or the seventh transistor is a p-type transistor, the sixth transistor is an n-type transistor, and the fifth transistor is a p-type transistor; or the seventh transistor is an n-type transistor, the sixth transistor is a p-type transistor, and the fifth transistor is an n-type transistor; or The seventh transistor is an n-type transistor, the sixth transistor is a p-type transistor, and the fifth transistor is a p-type transistor.

[0126] Optionally, the fifth light-emitting control circuit may include a thirteenth transistor; A control electrode of a thirteenth transistor is electrically connected to the first light-emitting control terminal, a first electrode of the thirteenth transistor is electrically connected to the second end of the driving circuit, and a second electrode of the thirteenth transistor is electrically connected to the first electrode of the light-emitting element.

[0127] As shown in FIG. 29, in addition to at least one embodiment of the pixel circuit shown in FIG. 28, the pixel circuit according to at least one embodiment of the present disclosure may further include a data writing circuit 51, a compensation control circuit 52, a first initialization circuit 53, a second initialization circuit 54 and a third capacitance C3, and the light-emitting element is a micro light-emitting diode M1; The data write circuit 51 is electrically connected to a second control end G2, a data line D1 and a first end of the driving circuit 10, respectively, and is used to write the data voltage Vdata provided by the data line D1 to the first end of the driving circuit 10 under the control of a second control signal provided by the second control end G2; The compensation control circuit 52 is electrically connected to a third control end G3, a control end of the driving circuit 10, and a second end of the driving circuit 10, and is used to control the communication between the control end of the driving circuit 10 and the second end of the driving circuit 10 under the control of a third control signal provided by the third control end G3; the first initialization circuit 53 is electrically connected to the first reset control terminal R1, the control terminal of the driving circuit 10 and the third initial voltage terminal I3 respectively, and is used to write the third initial voltage provided by the third initial voltage terminal I3 into the control terminal of the driving circuit 10 under the control of the first reset control signal provided by the first reset control terminal R1, to initialize the potential of the control terminal of the driving circuit 10; The second initialization circuit 54 is electrically connected to the second reset control terminal R2, the anode of the micro LED M1 and the fourth initial voltage terminal I4, and is used to write the fourth initial voltage provided by the fourth initial voltage terminal I4 to the anode of the micro LED M1 under the control of the second reset control signal provided by the second reset control terminal R2; A first end of the third capacitor C3 is electrically connected to the control end of the driving circuit 10, and a second end of the third capacitor C3 is electrically connected to the first voltage end V1.

[0128] In at least one embodiment of the pixel circuit shown in FIG. 29, the first initial voltage end, the third initial voltage end and the fourth initial voltage end may be the same voltage end, the first voltage end may be a high voltage end, and the first control end and the third control end may be the same control end, but are not limited thereto.

[0129] As shown in FIG. 30 , in addition to at least one embodiment of the pixel circuit shown in FIG. 29 , the second gating control circuit includes a fifth transistor T5, the third light-emitting control circuit includes a sixth transistor T6, the fourth light-emitting control circuit includes a seventh transistor T7, the light-emitting element is a micro light-emitting diode M1, and the driving circuit 10 includes a driving transistor T0; The gate of the fifth transistor T5 is electrically connected to the first control end G1, the source of the fifth transistor T5 is electrically connected to the light-emitting data voltage end DT, and the drain of the fifth transistor T5 is electrically connected to the gating control end ch; The gate of the sixth transistor T6 is electrically connected to the gating control terminal ch, the source of the sixth transistor T6 is electrically connected to the cathode of the micro light emitting diode M1, and the drain of the sixth transistor T6 is electrically connected to the low voltage terminal VSS; The gate of the seventh transistor T7 is electrically connected to the light-emitting control voltage end VF, the source of the seventh transistor T7 is electrically connected to the cathode of the micro light-emitting diode M1, and the drain of the seventh transistor T7 is electrically connected to the low-voltage end VSS, and the light-emitting control voltage end VF is used to supply the light-emitting control voltage HF; the light emission gating circuit further includes a second capacitor C2; A first end of the second capacitor C2 is electrically connected to the gating control terminal ch, and a second end of the second capacitor C2 is electrically connected to a first initial voltage terminal I1; The first initialization circuit 53 includes an eighth transistor T8, the compensation control circuit 52 includes a ninth transistor T9, the data write circuit 51 includes a tenth transistor T10, and the second initialization circuit 54 includes an eleventh transistor T11. The gate of the eighth transistor T8 is electrically connected to the first reset control end R1, the source of the eighth transistor T8 is electrically connected to the first initial voltage end I1, and the drain of the eighth transistor T8 is electrically connected to the gate of the driving transistor T0; The gate of the ninth transistor T9 is electrically connected to the first control end G1, the source of the ninth transistor T9 is electrically connected to the gate of the driving transistor T0, and the drain of the ninth transistor T9 is electrically connected to the drain of the driving transistor T0; The gate of the tenth transistor T10 is electrically connected to the second control end G2, the source of the tenth transistor T10 is electrically connected to the data line D1, and the gate of the tenth transistor T10 is electrically connected to the source of the driving transistor T0; The gate of the eleventh transistor T11 is electrically connected to the second reset control end R2, the source of the eleventh transistor T11 is electrically connected to the first initial voltage end I1, and the drain of the eleventh transistor T11 is electrically connected to the anode of the micro light-emitting diode M1; The first light-emitting control circuit 11 includes a twelfth transistor T12, The gate of the twelfth transistor T12 is electrically connected to the first light-emitting control end EM1, the source of the twelfth transistor T12 is electrically connected to the high-voltage end VDD, and the drain of the twelfth transistor T12 is electrically connected to the source of the driving transistor T0; The fifth light-emitting control circuit 65 may include a thirteenth transistor T13; The gate of the thirteenth transistor M13 is electrically connected to the first light-emitting control end EM1, the source of the thirteenth transistor M13 is electrically connected to the drain of the driving transistor T0, and the drain of the thirteenth transistor M13 is electrically connected to the anode of the micro light-emitting diode M1.

[0130] In at least one embodiment of the pixel circuit shown in FIG. 30, T5 is an n-type transistor, T6 is an n-type transistor, and T7 is a p-type transistor, but is not limited to this.

[0131] In at least one embodiment of the pixel circuit shown in FIG. 30, T8 and T9 are oxide thin film transistors, and T0, T10, T11, T12, and T13 may be, but are not limited to, low-temperature polysilicon thin film transistors.

[0132] In at least one embodiment of the pixel circuit shown in FIG. 30, T6 and T7 form a structure similar to a transfer gate, and the light-emitting data voltage and light-emitting control voltage HF provided by DT are respectively input to both sides of the transfer gate-like structure, and HF is a high-frequency PWM signal. When T6 is turned off, the light-emitting current path between VDD and VSS is controlled by HF, causing high-frequency short-time conduction, thereby realizing high-frequency short-time light emission; when T6 is turned on, the light-emitting current path between VDD and VSS is no longer controlled by HF, causing the cathode of M1 to be long-time conductive to VSS, thereby realizing long-time light emission.

[0133] In at least one embodiment of the pixel circuit shown in Figure 30, T6 is an n-type transistor, T7 is a p-type transistor, and the transfer gate-like structure is a CMOS structure or an LTPO structure.

[0134] A pixel circuit described in at least one embodiment of the present disclosure can perform PWM dimming to address problems of light-emitting elements, such as poor luminance uniformity at low current densities and insufficient low-gradation control capability, and can improve low-gradation luminance control capability.

[0135] At least one embodiment of the present disclosure is an LTPO pixel circuit with PWM dimming functionality that solves the problem of non-uniform light emission brightness at low current densities, using PAM mode for long-term light emission at high gradations and PWM mode for short-term, high-frequency light emission at low gradations.

[0136] As shown in FIG. 31 , during operation of at least one embodiment of the pixel circuit as shown in FIG. 30 of the present disclosure, a first display period includes a first initialization step S11, a first data writing step S12, and a first light-emitting step S13, which are set in sequence; In the first initialization step S11, R1 supplies a high voltage signal, R2 supplies a low voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a high voltage signal, T8 and T11 are turned on, and the first initial voltage terminal I1 supplies a first initial voltage Vini1 to the gate of T0 and the anode of M1, so that at the start of the first data writing step S12, T0 is turned on to remove residual charge from the anode of M1; In the first initialization step S11, T9 is turned off, T10 is turned off, T12 is turned off, and T13 is turned off. In the first data write step S12, R1 provides a low voltage signal, R2 provides a high voltage signal, G1 provides a high voltage signal, G2 provides a low voltage signal, EM1 provides a high voltage signal, D1 provides a data voltage Vdata, DT provides a high voltage signal, and T10 turns on, so that Vdata is written into the source of T0; At the beginning of the first data writing step S12, T0 is turned on, T9 is turned on, and C3 is charged by Vdata, thereby changing the potential of the gate of T0 until T0 is turned off, and the gate potential of T0 is related to the threshold voltage of T0; In the first data writing step S12, T8 and T11 are turned off, T12 is turned off, T13 is turned off, and T5 is turned on, so that DT and ch are connected, the potential of ch becomes high voltage, and T6 is turned on; In the first light-emitting stage S13, R1 supplies a low voltage signal, R2 supplies a high voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a low voltage signal, T12 turns on, T13 turns on, the potential of the C2 sustain channel becomes high voltage, T6 turns on, T4 turns on, and T0 drives M1 to emit light, thereby performing long-term light emission by PAM; The second display period includes a second initialization step S21, a second data writing step S22, and a second light-emitting step S23, which are set in sequence. In the second initialization step S21, R1 supplies a high voltage signal, R2 supplies a low voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a high voltage signal, T8 and T11 are turned on, and the first initial voltage terminal I1 supplies a first initial voltage Vini1 to the gate of T0 and the anode of M1, so that at the start of the first data writing step S12, T0 is turned on and the residual charge on the anode of M1 can be removed; In the second initialization step S21, T9 is turned off, T10 is turned off, T12 is turned off, and T13 is turned off; In the second data write step S22, R1 provides a low voltage signal, R2 provides a high voltage signal, G1 provides a high voltage signal, G2 provides a low voltage signal, EM1 provides a high voltage signal, D1 provides a data voltage Vdata, DT provides a low voltage signal, and T10 turns on, so that Vdata is written into the source of T0; At the start of the second data write step S22, T0 is turned on, T9 is turned on, and C3 is charged by Vdata, thereby changing the potential of the gate of T0 until T0 is turned off, and the gate potential of T0 is related to the threshold voltage of T0; In the second data writing step S22, T8 and T11 are turned off, T12 is turned off, T13 is turned off, and T5 is turned on, so that DT and ch are connected, the potential of ch becomes low, and T6 is turned off; In the second light-emitting stage S23, R1 supplies a low voltage signal, R2 supplies a high voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a low voltage signal, T12 turns on, T13 turns on, C1 maintains the potential of ch at a low voltage, T6 turns off, when the voltage value of HF is a low voltage, T7 turns on, and when T7 turns on, T0 drives M1 to emit light, thereby performing high-frequency short-time light emission by PWM and displaying low gradations.

[0137] During operation of at least one embodiment of the pixel circuit shown in FIG. 30 of the present disclosure, the voltage value of the first initial voltage Vini1 and the voltage value of the low voltage signal provided by VSS may be −2V, the voltage value of the high voltage signal provided by VDD may be 8V, the high voltage value of the first control signal provided by G1 may be 7V, the low voltage value of the first control signal provided by G1 may be −8V, the high voltage value of the first light-emitting control signal provided by EM1 may be 7V, the low voltage value of the first light-emitting control signal provided by EM1 may be −7V, the high voltage value of the light-emitting control voltage HF may be 7V, the low voltage value of the light-emitting control voltage HF may be −7V, the voltage value of the data voltage Vdata may be between 4V and 6V, the high voltage value of the light-emitting data voltage provided by DT may be 7V, the low voltage value of the light-emitting data voltage provided by DT may be −7V, and in the light-emitting stage, DT may supply a voltage signal of 0V, but is not limited to this.

[0138] In operation of at least one embodiment of the pixel circuit shown in FIG. 30 of the present disclosure, In PWM dimming mode, the potential of ch is maintained at a low voltage, and T5 needs a lower turn-off voltage. In this case, the low voltage value of the first control signal provided by G1 may be -8V or less; If T7 has tailing, it is necessary to select an appropriate voltage for HF, which will prevent T7 from turning off improperly and generating nA (nanoampere) level current noise due to leakage from T7 during the period when EM1 supplies a low voltage signal and the HF voltage is high in PWM dimming mode.

[0139] 30 of the present disclosure, in PWM dimming mode, when the potential of ch is maintained at a low voltage, reverse leakage is likely to occur due to a turn-off failure of T5, which reduces the potential of ch and therefore reduces the turn-off capability of T6. Therefore, a low-leakage oxide thin-film transistor may be used as T5 to be more advantageous in maintaining the low potential of ch.

[0140] At least one embodiment of the pixel circuit shown in FIG. 32 of the present disclosure differs from at least one embodiment of the pixel circuit shown in FIG. 30 of the present disclosure in that T5 is a p-type transistor and T5 is a low-temperature polysilicon thin-film transistor.

[0141] At least one embodiment of the pixel circuit shown in FIG. 33 of the present disclosure differs from at least one embodiment of the pixel circuit shown in FIG. 30 of the present disclosure in that T6 is a p-type transistor and T7 is an n-type transistor.

[0142] As shown in FIG. 34, during operation of at least one embodiment of the pixel circuit shown in FIG. 33 of the present disclosure: The first display period includes a first initialization step S11, a first data writing step S12, and a first light-emitting step S13, which are sequentially set. In the first initialization step S11, R1 supplies a high voltage signal, R2 supplies a low voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a high voltage signal, T8 and T11 are turned on, and the first initial voltage terminal I1 supplies a first initial voltage Vini1 to the gate of T0 and the anode of M1, so that at the start of the first data writing step S12, T0 is turned on to remove residual charge from the anode of M1; In the first initialization step S11, T9 is turned off, T10 is turned off, T12 is turned off, and T13 is turned off. In the first data write step S12, R1 provides a low voltage signal, R2 provides a high voltage signal, G1 provides a high voltage signal, G2 provides a low voltage signal, EM1 provides a high voltage signal, D1 provides a data voltage Vdata, DT provides a low voltage signal, and T10 turns on, so that Vdata is written into the source of T0; At the beginning of the first data writing step S12, T0 is turned on, T9 is turned on, and C3 is charged by Vdata, thereby changing the potential of the gate of T0 until T0 is turned off, and the gate potential of T0 is related to the threshold voltage of T0; In the first data writing step S12, T8 and T11 are turned off, T12 is turned off, T13 is turned off, and T5 is turned on, so that DT and ch are connected, the potential of ch becomes low, and T6 is turned on; In the first light-emitting stage S13, R1 supplies a low voltage signal, R2 supplies a high voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a low voltage signal, T12 turns on, T13 turns on, the potential of the C2 sustain channel becomes low voltage, T6 turns on, T4 turns on, and T0 drives M1 to emit light, thereby performing long-term light emission by PAM; The second display period includes a second initialization step S21, a second data writing step S22, and a second light-emitting step S23, which are set in sequence. In the second initialization step S21, R1 supplies a high voltage signal, R2 supplies a low voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a high voltage signal, T8 and T11 are turned on, and the first initial voltage terminal I1 supplies a first initial voltage Vini1 to the gate of T0 and the anode of M1, so that at the start of the first data writing step S12, T0 is turned on and the residual charge on the anode of M1 can be removed; In the second initialization step S21, T9 is turned off, T10 is turned off, T12 is turned off, and T13 is turned off; In the second data write step S22, R1 supplies a low voltage signal, R2 supplies a high voltage signal, G1 supplies a high voltage signal, G2 supplies a low voltage signal, EM1 supplies a high voltage signal, D1 supplies a data voltage Vdata, DT supplies a high voltage signal, and T10 turns on, so that Vdata is written to the source of T0; At the start of the second data write step S22, T0 is turned on, T9 is turned on, and C3 is charged by Vdata, thereby changing the potential of the gate of T0 until T0 is turned off, and the gate potential of T0 is related to the threshold voltage of T0; In the second data writing step S22, T8 and T11 are turned off, T12 is turned off, T13 is turned off, and T5 is turned on, so that DT and ch are connected, the potential of ch becomes high voltage, and T6 is turned off; In the second light-emitting stage S23, R1 supplies a low voltage signal, R2 supplies a high voltage signal, G1 supplies a low voltage signal, G2 supplies a high voltage signal, EM1 supplies a low voltage signal, T12 turns on, T13 turns on, C1 maintains the potential of ch at a high voltage, T6 turns off, when the voltage value of HF is a low voltage, T7 turns on, and when T7 turns on, T0 drives M1 to emit light, thereby performing high-frequency short-time light emission by PWM and displaying low gradations.

[0143] At least one embodiment of the pixel circuit shown in FIG. 35 of the present disclosure differs from at least one embodiment of the pixel circuit shown in FIG. 33 of the present disclosure in that T5 is a p-type transistor.

[0144] In at least one embodiment of the pixel circuits shown in Figures 30, 32, 33, and 35 of the present disclosure, D1 and DT may be shared, and the gate of T0 and the gating control terminal ch are charged in succession by the second control signal and the first control signal which are turned on in succession.

[0145] In at least one embodiment of the pixel circuit shown in Figures 30, 32, 33, and 35 of the present disclosure, if the type of T5 and the type of T10 are the same, that is, if both T5 and T10 are p-type transistors or both are n-type transistors, the control signal input to the gate of T5 and the control signal input to the gate of T10 may be shared, and the gate of T0, the gating control terminal ch, will be charged simultaneously with different data voltages and light-emitting data voltages.

[0146] In at least one embodiment of the present disclosure, C2 may not be provided, and if the leakage of T5 is small and the voltage stability of the gating control terminal ch can satisfy the gate switching condition of T6, C2 may be removed.

[0147] In at least one embodiment of the pixel circuits shown in Figures 30, 32, 33, and 35 of the present disclosure, T8 may be replaced with a p-type transistor, T9 may be replaced with a p-type transistor, and T10 may be replaced with an n-type transistor, but is not limited to this.

[0148] In at least one embodiment of the pixel circuits shown in Figures 30, 32, 33, and 35 of the present disclosure, T8 and T9 may be double-gate transistors, in which case T8 and T9 may be oxide thin-film transistors, or T8 and T9 may be low-temperature polysilicon thin-film transistors.

[0149] In at least one embodiment of the pixel circuit shown in Figures 30, 32, 33, and 35 of the present disclosure, since T6 and T7 are on the light-emitting current path, the channel width of T6 and the channel width of T7 may be appropriately increased, for example, but not limited to, the channel width of T6 and the channel width of T7 may be 5 um or more and 10 um or less.

[0150] In at least one embodiment of the present disclosure, when T7 is a p-type transistor, T6 is an n-type transistor, and T5 is an n-type transistor, the voltage values ​​of the first initial voltage Vini1 and the low voltage signal provided by VSS may be −2V, the voltage value of the high voltage signal provided by VDD may be 8V, the high voltage value of the first control signal provided by G1 may be 7V, the low voltage value of the first control signal provided by G1 may be −8V, the high voltage value of the first light-emitting control signal provided by EM1 may be 7V, the low voltage value of the first light-emitting control signal provided by EM1 may be −7V, the high voltage value of HF may be 7V, the low voltage value of HF may be −7V, the voltage value of the data voltage provided by D1 may be between 4V and 6V, the high voltage value of the light-emitting data voltage provided by DT may be 7V, and the low voltage value of the light-emitting data voltage provided by DT may be −7V. During the light-emitting phase, DT may provide a voltage signal of 0V, but is not limited thereto.

[0151] In at least one embodiment of the present disclosure, when T7 is an n-type transistor, T6 is a p-type transistor, and T5 is an n-type transistor, the voltage values ​​of the first initial voltage Vini1 and the low voltage signal provided by VSS may be −2V, the voltage value of the high voltage signal provided by VDD may be 8V, the high voltage value of the first control signal provided by G1 may be 7V, the low voltage value of the first control signal provided by G1 may be −8V, the high voltage value of the first light-emitting control signal provided by EM1 may be 7V, the low voltage value of the first light-emitting control signal provided by EM1 may be −7V, the high voltage value of HF may be 7V, the low voltage value of HF may be −7V, the voltage value of the data voltage provided by D1 may be between 4V and 6V, the high voltage value of the light-emitting data voltage provided by DT may be 7V, and the low voltage value of the light-emitting data voltage provided by DT may be −7V. During the light-emitting phase, DT may provide a voltage signal of 0V, but is not limited thereto.

[0152] In at least one embodiment of the present disclosure, when T7 is a p-type transistor, T6 is an n-type transistor, and T5 is a p-type transistor, the voltage values ​​of the first initial voltage Vini1 and the low voltage signal provided by VSS may be −2V, the voltage value of the high voltage signal provided by VDD may be 8V, the high voltage value of the first control signal provided by G1 may be 8V, the low voltage value of the first control signal provided by G1 may be −8V, the high voltage value of the first light-emitting control signal provided by EM1 may be 7V, the low voltage value of the first light-emitting control signal provided by EM1 may be −7V, the high voltage value of HF may be 7V, the low voltage value of HF may be −7V, the voltage value of the data voltage provided by D1 may be between 4V and 6V, the high voltage value of the light-emitting data voltage provided by DT may be 7V, and the low voltage value of the light-emitting data voltage provided by DT may be −7V. During the light-emitting phase, DT may provide a voltage signal of 0V, but is not limited thereto.

[0153] In at least one embodiment of the present disclosure, when T7 is an n-type transistor, T6 is a p-type transistor, and T5 is a p-type transistor, the voltage values ​​of the first initial voltage Vini1 and the low voltage signal provided by VSS may be −2V, the voltage value of the high voltage signal provided by VDD may be 8V, the high voltage value of the first control signal provided by G1 may be 8V, the low voltage value of the first control signal provided by G1 may be −8V, the high voltage value of the first light-emitting control signal provided by EM1 may be 7V, the low voltage value of the first light-emitting control signal provided by EM1 may be −7V, the high voltage value of HF may be 7V, the low voltage value of HF may be −7V, the voltage value of the data voltage provided by D1 may be between 4V and 6V, the high voltage value of the light-emitting data voltage provided by DT may be 7V, and the low voltage value of the light-emitting data voltage provided by DT may be −7V. During the light-emitting phase, DT may provide a voltage signal of 0V, but is not limited thereto.

[0154] In specific implementation, if the light emitting data voltage provided by DT needs to be a positive value, When T7 is a p-type transistor, T6 is an n-type transistor, and T5 is an n-type transistor, the voltage values ​​of the first initial voltage Vini1 and the low voltage signal provided by VSS may be -2V, the voltage value of the high voltage signal provided by VDD may be 8V, the high voltage value of the first control signal provided by G1 may be 14V, the low voltage value of the first control signal provided by G1 may be -1V, the high voltage value of the first light-emitting control signal provided by EM1 may be 7V, the low voltage value of the first light-emitting control signal provided by EM1 may be -7V, the high voltage value of HF may be 7V, the low voltage value of HF may be -7V, the voltage value of the data voltage provided by D1 may be between 4V and 6V, the high voltage value of the light-emitting data voltage provided by DT may be 14V, and the low voltage value of the light-emitting data voltage provided by DT may be 0V, but is not limited thereto.

[0155] In specific implementation, if the light emitting data voltage provided by DT needs to be a positive value, When T7 is an n-type transistor, T6 is a p-type transistor, and T5 is an n-type transistor, the voltage values ​​of the first initial voltage Vini1 and the low voltage signal provided by VSS may be -2V, the voltage value of the high voltage signal provided by VDD may be 8V, the high voltage value of the first control signal provided by G1 may be 14V, the low voltage value of the first control signal provided by G1 may be -1V, the high voltage value of the first light-emitting control signal provided by EM1 may be 7V, the low voltage value of the first light-emitting control signal provided by EM1 may be -7V, the high voltage value of HF may be 7V, the low voltage value of HF may be -7V, the voltage value of the data voltage provided by D1 may be between 4V and 6V, the high voltage value of the light-emitting data voltage provided by DT may be 14V, and the low voltage value of the light-emitting data voltage provided by DT may be 0V, but is not limited thereto.

[0156] In specific implementation, if the light emitting data voltage provided by DT needs to be a positive value, When T7 is a p-type transistor, T6 is an n-type transistor, and T5 is a p-type transistor, the voltage values ​​of the first initial voltage Vini1 and the low voltage signal provided by VSS may be -2V, the voltage value of the high voltage signal provided by VDD may be 8V, the high voltage value of the first control signal provided by G1 may be 15V, the low voltage value of the first control signal provided by G1 may be -1V, the high voltage value of the first light-emitting control signal provided by EM1 may be 7V, the low voltage value of the first light-emitting control signal provided by EM1 may be -7V, the high voltage value of HF may be 7V, the low voltage value of HF may be -7V, the voltage value of the data voltage provided by D1 may be between 4V and 6V, the high voltage value of the light-emitting data voltage provided by DT may be 14V, and the low voltage value of the light-emitting data voltage provided by DT may be 0V, but is not limited thereto.

[0157] In specific implementation, if the light emitting data voltage provided by DT needs to be a positive value, When T7 is an n-type transistor, T6 is a p-type transistor, and T5 is a p-type transistor, the voltage values ​​of the first initial voltage Vini1 and the low voltage signal provided by VSS may be -2V, the voltage value of the high voltage signal provided by VDD may be 8V, the high voltage value of the first control signal provided by G1 may be 15V, the low voltage value of the first control signal provided by G1 may be -1V, the high voltage value of the first light-emitting control signal provided by EM1 may be 7V, the low voltage value of the first light-emitting control signal provided by EM1 may be -7V, the high voltage value of HF may be 7V, the low voltage value of HF may be -7V, the voltage value of the data voltage provided by D1 may be between 4V and 6V, the high voltage value of the light-emitting data voltage provided by DT may be 14V, and the low voltage value of the light-emitting data voltage provided by DT may be 0V, but is not limited thereto.

[0158] In at least one embodiment of the present disclosure, when T7 is a p-type transistor, T6 is an n-type transistor, and T5 is an n-type transistor, In PWM dimming mode, during the low voltage maintaining stage of ch, T5 requires a lower turn-off voltage, so the low voltage value of the first control signal provided by G1 needs to be adjusted lower.

[0159] In at least one embodiment of the present disclosure, when T7 is an n-type transistor, T6 is a p-type transistor, and T5 is an n-type transistor, In PAM dimming mode, when the potential of ch is maintained at high voltage, the high voltage value of the first control signal provided by G1 must be 8V or more; In PWM dimming mode, when the potential of the first control signal provided by G1 is low voltage, T5 is turned on, and ch is charged to low voltage by the light emission data voltage provided by DT, and the low voltage value of the first control signal provided by G1 must be less than -8V.

[0160] In at least one embodiment of the present disclosure, when T7 is a p-type transistor, T6 is an n-type transistor, and T5 is a p-type transistor, In PAM dimming mode, during the low voltage hold phase of ch, the first control signal provided by G1 needs to be at a low potential to ensure the turn-off ability of T5.

[0161] In at least one embodiment of the present disclosure, when T7 is an n-type transistor, T6 is a p-type transistor, and T5 is a p-type transistor, In PAM dimming mode, during the low voltage hold phase of ch, the first control signal provided by G1 needs to be at a low potential to ensure the turn-off ability of T5.

[0162] A pixel driving method according to at least one embodiment of the present disclosure is applied to the pixel circuit described above, and the pixel driving method includes: The first light-emitting control circuit controls the first voltage terminal and the first terminal of the driving circuit to communicate with each other under the control of the first light-emitting control signal in the light-emitting stage; The light emitting gating circuit, under the control of the first control signal and according to the light emitting data voltage, controls, in the light emitting stage, to generate a current path between the second end of the driving circuit and the light emitting element under the control of the light emitting control voltage supplied by the light emitting control voltage terminal, so that the driving circuit can control the light emitting element to emit light, or controls, in the light emitting stage, to generate a current path between the second end of the driving circuit and the light emitting element, so that the driving circuit can control the light emitting element to emit light.

[0163] In at least one embodiment of the present disclosure, the light-emitting gating circuit includes a second light-emitting control circuit and a first gating control circuit, and the pixel driving method includes: The first gating control circuit writes the light-emitting data voltage to the gating control terminal under the control of the first control signal, and controls the second light-emitting control terminal to communicate with the light-emitting control voltage terminal or the second light-emitting control terminal to communicate with the first light-emitting control terminal under the control of the potential of the gating control terminal; The second light-emitting control circuit controls the second end of the driving circuit to communicate with the first electrode of the light-emitting element under the control of the potential of the second light-emitting control end.

[0164] In at least one embodiment of the present disclosure, the light-emitting gating circuit includes a second gating control circuit, a third light-emitting control circuit and a fourth light-emitting control circuit, and the pixel driving method includes: The second gating control circuit controls the light emitting control voltage to be written to the gating control terminal under the control of the first control signal; The third light-emitting control circuit controls the second pole of the light-emitting element to communicate with the second voltage terminal under the control of the potential of the gating control terminal; The fourth light-emitting control circuit controls the second electrode of the light-emitting element to communicate with the second voltage terminal under the control of a light-emitting control voltage.

[0165] A display device according to an embodiment of the present disclosure includes the pixel circuit described above.

[0166] The display device according to the embodiment of the present disclosure may be any product or component having a display function, such as a wearable device, a mobile phone, a tablet PC, a television, a display, a notebook PC, a digital photo frame, or a navigator.

[0167] The above is a preferred embodiment of the present disclosure, and it should be noted that those skilled in the art may further make some improvements and modifications without departing from the principles described in the present disclosure, and these improvements and modifications should also be considered to be within the scope of protection of the present disclosure.

Claims

1. A pixel circuit including a first light-emitting control circuit, a light-emitting element, a drive circuit, and a light-emitting gating circuit, the first light-emitting control circuit is electrically connected to a first light-emitting control end, a first voltage end and the first end of the driving circuit respectively, and is used to control the first voltage end and the first end of the driving circuit to communicate with each other under the control of a first light-emitting control signal provided by the first light-emitting control end in a light-emitting stage; a second end of the driving circuit electrically connected to a first electrode of the light-emitting element, the driving circuit being used to drive the light-emitting element; The light-emitting gating circuit is used to control, under control of a first control signal provided by a first control end, according to a light-emitting data voltage provided by a light-emitting data voltage end, to generate a current path between the second end of the driving circuit and the light-emitting element under control of a light-emitting control voltage provided by a light-emitting control voltage end in a light-emitting stage, so that the driving circuit can control the light-emitting element to emit light, or to control, under control of a first control signal provided by a first control end, according to a light-emitting data voltage provided by a light-emitting data voltage end, so that the driving circuit can control the light-emitting element to emit light, so that the driving circuit can control the light-emitting element to emit light in the light-emitting stage, so that the driving circuit can control the light-emitting element to emit light.

2. the light emission gating circuit includes a second light emission control circuit and a first gating control circuit; the first gating control circuit is electrically connected to the first control terminal, the light-emitting data voltage terminal, the gating control terminal, the second light-emitting control terminal, the light-emitting control voltage terminal and the first light-emitting control terminal, and is used to write the light-emitting data voltage provided by the light-emitting data voltage terminal into the gating control terminal under the control of the first control signal, and to control the second light-emitting control terminal and the light-emitting control voltage terminal to communicate with each other or the second light-emitting control terminal and the first light-emitting control terminal to communicate with each other under the control of the potential of the gating control terminal; the second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the second terminal of the driving circuit, and the first electrode of the light-emitting element, respectively, and is used to control the communication between the second terminal of the driving circuit and the first electrode of the light-emitting element under the control of the potential of the second light-emitting control terminal; The pixel circuit according to claim 1 , wherein the second electrode of the light-emitting element is electrically connected to a second voltage terminal.

3. the light emission gating circuit further includes a first capacitance; The pixel circuit according to claim 2 , wherein a first end of the first capacitance is electrically connected to the gating control end, and a second end of the first capacitance is electrically connected to a first initial voltage end.

4. the first gating control circuit includes a first transistor, a second transistor, and a third transistor; a control electrode of the first transistor electrically connected to the first control end, a first electrode of the first transistor electrically connected to the light-emitting data voltage end, and a second electrode of the first transistor electrically connected to the gating control end; a control electrode of the second transistor is electrically connected to the gating control terminal, a first electrode of the second transistor is electrically connected to the light-emitting control voltage terminal, and a second electrode of the second transistor is electrically connected to the second light-emitting control terminal; 3. The pixel circuit of claim 2, wherein a control electrode of the third transistor is electrically connected to the gating control terminal, a first electrode of the third transistor is electrically connected to the first light-emitting control terminal, and a second electrode of the third transistor is electrically connected to the second light-emitting control terminal.

5. the second light-emitting control circuit includes a fourth transistor; 3. The pixel circuit of claim 2, wherein a control electrode of the fourth transistor is electrically connected to the second light-emitting control terminal, a first electrode of the fourth transistor is electrically connected to the second end of the driving circuit, and a second electrode of the fourth transistor is electrically connected to the first electrode of the light-emitting element.

6. the first transistor is an n-type transistor, the second transistor is a p-type transistor, and the third transistor is an n-type transistor; or the first transistor is an n-type transistor, the second transistor is an n-type transistor, and the third transistor is a p-type transistor; or 5. The pixel circuit of claim 4, wherein the first transistor is a p-type transistor, the second transistor is an n-type transistor, and the third transistor is a p-type transistor.

7. 7. The pixel circuit of claim 6, wherein when the second transistor is a p-type transistor and the third transistor is an n-type transistor, a width-to-length ratio of a channel of the third transistor is greater than a width-to-length ratio of a channel of the second transistor.

8. the light-emitting gating circuit includes a second gating control circuit, a third light-emitting control circuit and a fourth light-emitting control circuit; the second gating control circuit is electrically connected to the first control end, the light emitting data voltage end and the gating control end respectively, and is used to control the light emitting data voltage to be written to the gating control end under the control of the first control signal; the third light-emitting control circuit is electrically connected to the gating control terminal, the second pole and the second voltage terminal of the light-emitting element, respectively, and is used to control the second pole of the light-emitting element to communicate with the second voltage terminal under the control of the potential of the gating control terminal; 3. The pixel circuit according to claim 2, wherein the fourth light-emitting control circuit is electrically connected to the light-emitting control voltage terminal, the second pole and the second voltage terminal of the light-emitting element, respectively, and is used to control communication between the second pole of the light-emitting element and the second voltage terminal under control of the light-emitting control voltage supplied by the light-emitting control voltage terminal.

9. Further including a fifth light-emitting control circuit; 9. The pixel circuit of claim 8, wherein the fifth light-emitting control circuit is electrically connected to a first light-emitting control terminal, a second terminal of the driving circuit, and a first electrode of the light-emitting element, respectively, and is used to control communication between the second terminal of the driving circuit and the first electrode of the light-emitting element under control of the first light-emitting control signal.

10. the light emission gating circuit further includes a second capacitor; The pixel circuit according to claim 8 , wherein a first end of the second capacitance is electrically connected to the gating control end, and a second end of the second capacitance is electrically connected to a first initial voltage end.

11. the second gating control circuit includes a fifth transistor, the third light-emitting control circuit includes a sixth transistor, and the fourth light-emitting control circuit includes a seventh transistor; a control electrode of the fifth transistor electrically connected to the first control end, a first electrode of the fifth transistor electrically connected to the light-emitting data voltage end, and a second electrode of the fifth transistor electrically connected to the gating control end; a control electrode of the sixth transistor electrically connected to the gating control terminal, a first electrode of the sixth transistor electrically connected to the second electrode of the light-emitting element, and a second electrode of the sixth transistor electrically connected to the second voltage terminal; 9. The pixel circuit of claim 8, wherein a control electrode of the seventh transistor is electrically connected to the light-emitting control voltage terminal, a first electrode of the seventh transistor is electrically connected to a second electrode of the light-emitting element, and a second electrode of the seventh transistor is electrically connected to the second voltage terminal.

12. the seventh transistor is a p-type transistor, the sixth transistor is an n-type transistor, and the fifth transistor is an n-type transistor; or the seventh transistor is a p-type transistor, the sixth transistor is an n-type transistor, and the fifth transistor is a p-type transistor; or the seventh transistor is an n-type transistor, the sixth transistor is a p-type transistor, and the fifth transistor is an n-type transistor; or 12. The pixel circuit of claim 11, wherein the seventh transistor is an n-type transistor, the sixth transistor is a p-type transistor, and the fifth transistor is a p-type transistor.

13. further comprising a data write circuit, a compensation control circuit, a first initialization circuit, a second initialization circuit, and a third capacitor; the data writing circuit is electrically connected to a second control end, a data line and a first end of the driving circuit respectively, and is used to control, under the control of a second control signal provided by the second control end, the data voltage provided by the data line to be written into the first end of the driving circuit; The compensation control circuit is electrically connected to a third control end, a control end of the driving circuit, and a second end of the driving circuit, respectively, and is used to control the communication between the control end of the driving circuit and the second end of the driving circuit under the control of a third control signal provided by the third control end; the first initialization circuit is electrically connected to a first reset control terminal, a control terminal of the driving circuit and a third initial voltage terminal respectively, and is used to control, under the control of a first reset control signal provided by the first reset control terminal, to write the third initial voltage provided by the third initial voltage terminal into the control terminal of the driving circuit; The second initialization circuit is electrically connected to a second reset control terminal, a first pole of the light emitting element, and a fourth initial voltage terminal, respectively, and is used to control, under the control of a second reset control signal provided by the second reset control terminal, to write a fourth initial voltage provided by the fourth initial voltage terminal to the first pole of the light emitting element; 13. The pixel circuit according to claim 1, wherein a first terminal of the third capacitance is electrically connected to a control terminal of the driving circuit, and a second terminal of the third capacitance is electrically connected to a first voltage terminal.

14. the first initialization circuit includes an eighth transistor, the compensation control circuit includes a ninth transistor, the data write circuit includes a tenth transistor, and the second initialization circuit includes an eleventh transistor; a control electrode of the eighth transistor electrically connected to the first reset control terminal, a first electrode of the eighth transistor electrically connected to the third initial voltage terminal, and a second electrode of the eighth transistor electrically connected to the control terminal of the driving circuit; a control pole of the ninth transistor electrically connected to the third control end, a first pole of the ninth transistor electrically connected to the control end of the driving circuit, and a second pole of the ninth transistor electrically connected to the second end of the driving circuit; a control electrode of the tenth transistor is electrically connected to the second control end, a first electrode of the tenth transistor is electrically connected to the data line, and a second electrode of the tenth transistor is electrically connected to a first end of a driving circuit; or a control electrode of the tenth transistor is electrically connected to the first reset control end, a first electrode of the tenth transistor is electrically connected to a light-emitting data voltage end, and a second electrode of the tenth transistor is electrically connected to a first end of a driving circuit; 14. The pixel circuit of claim 13, wherein a control electrode of the eleventh transistor is electrically connected to a second reset control terminal or a first reset control terminal, a first electrode of the eleventh transistor is electrically connected to the fourth initial voltage terminal, and a second electrode of the eleventh transistor is electrically connected to a first electrode of the light-emitting element.

15. The pixel circuit of claim 14 , wherein the eighth transistor and the ninth transistor are oxide thin film transistors.

16. 16. The pixel circuit according to claim 15, wherein the eleventh transistor is an oxide thin film transistor, and a control electrode of the eleventh transistor is electrically connected to the first reset control terminal.

17. The pixel circuit of claim 14 , wherein at least one of the eighth transistor and the ninth transistor is a double-gate transistor.

18. The pixel circuit according to any one of claims 1 to 12, wherein the light emitting element is a micro light emitting diode or a mini light emitting diode.

19. A pixel driving method applied to a pixel circuit according to any one of claims 1 to 18, the pixel driving method comprising: The first light-emitting control circuit controls the first voltage terminal and the first terminal of the driving circuit to communicate with each other under the control of the first light-emitting control signal in the light-emitting stage; a light-emitting gating circuit, under control of a first control signal and according to a light-emitting data voltage, controls, in a light-emitting stage, to generate a current path between the second end of the driving circuit and the light-emitting element under control of a light-emitting control voltage supplied by a light-emitting control voltage terminal, so that the driving circuit is controlled to be able to control the light-emitting element to emit light; or, in a light-emitting stage, controls to generate a current path between the second end of the driving circuit and the light-emitting element, so that the driving circuit is controlled to be able to control the light-emitting element to emit light.

20. the light-emitting gating circuit includes a second light-emitting control circuit and a first gating control circuit, and the pixel driving method includes: The first gating control circuit writes the light-emitting data voltage into the gating control terminal under the control of the first control signal, and controls the second light-emitting control terminal to communicate with the light-emitting control voltage terminal or the second light-emitting control terminal to communicate with the first light-emitting control terminal under the control of the potential of the gating control terminal; 20. The pixel driving method of claim 19, further comprising: controlling the second light-emitting control circuit to communicate between the second end of the driving circuit and the first electrode of the light-emitting element under control of the potential of the second light-emitting control terminal.

21. the light-emitting gating circuit includes a second gating control circuit, a third light-emitting control circuit and a fourth light-emitting control circuit, and the pixel driving method includes: The second gating control circuit controls the light emitting control voltage to be written to the gating control terminal under the control of the first control signal; The third light-emitting control circuit controls the second pole of the light-emitting element to communicate with the second voltage terminal under the control of the potential of the gating control terminal; 20. The pixel driving method of claim 19, further comprising: controlling the fourth light-emitting control circuit to communicate between the second pole of the light-emitting element and the second voltage terminal under the control of a light-emitting control voltage.

22. A display device comprising the pixel circuit according to any one of claims 1 to 18.

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