Display device

Abstract

The display device of the present invention includes a base layer, a 1-1 pixel circuit, and a 1-2 pixel circuit, and a circuit layer disposed on the base layer, the circuit layer including a first light-emitting element and a second light-emitting element, each including a first electrode, a light-emitting layer, a second electrode, and a pixel defining layer defining a pixel opening exposing a portion of the first electrode, and a light-emitting element layer disposed on the circuit layer, the 1-1 pixel circuit and the 1-2 pixel circuit each including a driving transistor including a source, a drain, an active layer, and a gate, and a gate conductive layer including the gate, and the area where the first electrode of the first light-emitting element overlaps with the gate conductive layer of the 1-1 pixel circuit in a plane is the same as the area where the first electrode of the second light-emitting element overlaps with the gate conductive layer of the 1-2 pixel circuit in a plane, thereby improving display quality.

Description

[Technical Field]

[0001] The present invention relates to a display device, and more particularly to a display device comprising an oxide transistor. [Background technology]

[0002] The display device includes a plurality of pixels and driving circuits (e.g., a scan driving circuit and a data driving circuit) that control the plurality of pixels. Each of the plurality of pixels includes a display element and a pixel driving circuit that controls the display element. The pixel driving circuit may include a plurality of organically coupled transistors.

[0003] The scan driving circuit and / or the data driving circuit may be formed by the same process as the plurality of pixels, and may include a plurality of organically connected transistors. Summary of the Invention [Problem to be solved by the invention]

[0004] Embodiments of the present invention provide a display device with improved display quality. [Means for solving the problem]

[0005] A display device of the present invention includes a base layer, a 1-1 pixel circuit, and a 1-2 pixel circuit, and a circuit layer disposed on the base layer, the circuit layer including a first light-emitting element and a second light-emitting element, each including a first electrode, a light-emitting layer, a second electrode, and a pixel defining film that defines a pixel opening that exposes a portion of the first electrode, and a light-emitting element layer disposed on the circuit layer, wherein the 1-1 pixel circuit and the 1-2 pixel circuit each include a driving transistor including a source, a drain, an active, and a gate, and a gate conductive layer including the gate, and the area where the first electrode of the first light-emitting element overlaps with the gate conductive layer of the 1-1 pixel circuit on a plane is the same as the area where the first electrode of the second light-emitting element overlaps with the gate conductive layer of the 1-2 pixel circuit on a plane.

[0006] The first electrode and the gate conductive layer of the first light-emitting element may define a first electrode and a second electrode of a first capacitor, respectively, and the first electrode and the gate conductive layer of the second light-emitting element may define a first electrode and a second electrode of a second capacitor, respectively.

[0007] The capacitance of the first capacitor may be substantially the same as the capacitance of the second capacitor.

[0008] In a plane, the pixel opening of the first light-emitting element may overlap the upper side of the gate conductive layer of the 1-1 pixel circuit, and the pixel opening of the second light-emitting element may overlap the lower side of the gate conductive layer of the 1-2 pixel circuit.

[0009] The driving transistor may include an oxide semiconductor.

[0010] the 1-1 pixel circuit is disposed above the 1-2 pixel circuit in a first direction, the circuit layer further includes a 1-3 pixel circuit adjacent to the 1-1 pixel circuit in a second direction intersecting the first direction, and a 1-4 pixel circuit adjacent to the 1-2 pixel circuit in the second direction, the light emitting element layer includes a third light emitting element disposed above the 1-3 pixel circuit and a fourth light emitting element disposed above the 1-4 pixel circuit, each of the third light emitting element and the fourth light emitting element including a first electrode, a light emitting layer, a second electrode, and a pixel defining film defining a pixel opening exposing a portion of the first electrode; The -3 pixel circuit and the 1-4 pixel circuit each include a first portion, a second portion, and a third portion separated in the first direction, and on a plane, the first electrode of the third light-emitting element overlaps the first to third portions of the 1-3 pixel circuit, the first electrode of the fourth light-emitting element overlaps the first to third portions of the 1-4 pixel circuit, the pixel opening of the third light-emitting element overlaps the second and third portions of the 1-3 pixel circuit, and the pixel opening of the fourth light-emitting element overlaps the first and second portions of the 1-4 pixel circuit.

[0011] The first light emitting element and the second light emitting element may emit a first light.

[0012] The first light emitting element may be electrically connected to the 1-1 pixel circuit, and the second light emitting element may be electrically connected to the 1-2 pixel circuit.

[0013] The light emitting device layer may further include a fifth light emitting device that emits a second light different from the first light and is adjacent to the first light emitting device, and the first light emitting device may be connected to the fifth light emitting device.

[0014] A display device according to the present invention includes a base layer, a 1-1 pixel circuit, and a 1-2 pixel circuit adjacent to the 1-1 pixel circuit in a first direction, and a circuit layer disposed on the base layer, and a light emitting element layer disposed on the circuit layer, the light emitting element layer including a first light emitting element disposed on the 1-1 pixel circuit and a second light emitting element disposed on the 1-2 pixel circuit, wherein each of the first light emitting element and the second light emitting element includes a first electrode, a light emitting layer, a second electrode, and a pixel defining layer defining a pixel opening exposing a portion of the first electrode, and the 1-1 pixel circuit and the 1-2 pixel circuit are disposed on the circuit layer. Each pixel circuit includes a first portion, a second portion, and a third portion divided in the first direction, and on a plane, the first electrode of the first light-emitting element overlaps the first to third portions of the 1-1 pixel circuit, on a plane, the first electrode of the second light-emitting element overlaps the first to third portions of the 1-2 pixel circuit, on a plane, the pixel opening of the first light-emitting element overlaps the first and second portions of the 1-1 pixel circuit, and on a plane, the pixel opening of the second light-emitting element overlaps the second and third portions of the 1-2 pixel circuit.

[0015] The pixel opening of the first light-emitting element may not overlap the third portion of the 1-1 pixel circuit on a plane, and the pixel opening of the second light-emitting element may not overlap the first portion of the 1-2 pixel circuit on a plane.

[0016] Each of the 1-1 pixel circuit and the 1-2 pixel circuit includes a driving transistor including a source, a drain, an active layer, and a gate, and a gate conductive layer including the gate, at least a portion of the gate conductive layer is included in the first to third portions, and an area in a plane where the first electrode of the first light-emitting element overlaps with the gate conductive layer of the 1-1 pixel circuit may be the same as an area in a plane where the first electrode of the second light-emitting element overlaps with the gate conductive layer of the 1-2 pixel circuit.

[0017] The driving transistor may be an oxide semiconductor.

[0018] the 1-1 pixel circuit is disposed above the 1-2 pixel circuit in the first direction, the circuit layer further includes a 1-3 pixel circuit adjacent to the 1-1 pixel circuit in a second direction intersecting the first direction, and a 1-4 pixel circuit adjacent to the 1-2 pixel circuit in the second direction, the light emitting element layer includes a third light emitting element disposed above the 1-3 pixel circuit and a fourth light emitting element disposed above the 1-4 pixel circuit, each of the third light emitting element and the fourth light emitting element including a first electrode, a light emitting layer, a second electrode, and a pixel defining film defining a pixel opening exposing a portion of the first electrode; The 1-3 pixel circuit and the 1-4 pixel circuit each include a first portion, a second portion, and a third portion separated in the first direction, and on a plane, the first electrode of the third light-emitting element overlaps the first to third portions of the 1-3 pixel circuit, the first electrode of the fourth light-emitting element overlaps the first to third portions of the 1-4 pixel circuit, the pixel opening of the third light-emitting element overlaps the second and third portions of the 1-3 pixel circuit, and the pixel opening of the fourth light-emitting element overlaps the first and second portions of the 1-4 pixel circuit.

[0019] The first light emitting element and the second light emitting element may emit a first light.

[0020] The first light emitting element may be electrically connected to the 1-1 pixel circuit, and the second light emitting element may be electrically connected to the 1-2 pixel circuit.

[0021] The light emitting device layer may further include a fifth light emitting device that emits a second light different from the first light and is adjacent to the first light emitting device, and the first light emitting device may be connected to the fifth light emitting device.

[0022] A display device according to the present invention includes a base layer, first to fourth pixel circuit units arranged in one direction, and first to fourth light emitting units arranged in the one direction and disposed on the first to fourth pixel circuit units, respectively, wherein each of the first to fourth light emitting units includes a 1-1 light emitting element, a 1-2 light emitting element, a 1-3 light emitting element, and a 1-4 light emitting element, and each of the 1-1 to 1-4 light emitting elements includes a first electrode, a light emitting layer, a second electrode, and a pixel defining film defining a pixel opening exposing a portion of the first electrode, and each of the first to fourth pixel circuit units includes the 1-1 light emitting element, a 1-2 light emitting element, a 1-3 light emitting element, and a 1-4 light emitting element, and and a first pixel circuit electrically connected to the 1-2 light emitting element, a second pixel circuit electrically connected to the 1-2 light emitting element, and a third pixel circuit electrically connected to the 1-3 light emitting element, each of the first to third pixel circuits including a driving transistor including a source, a drain, an active, and a gate, and a gate conductive layer including the gate, and the area where the first electrodes of the 1-1 light emitting element and the 1-2 light emitting element overlap the gate conductive layer of the first pixel circuit in a plane is the same in the first pixel circuit unit and the fourth pixel circuit unit.

[0023] The pixel openings of the 1-1th light emitting element and the 1-2th light emitting element may be disposed at different positions in the first pixel circuit unit and the fourth pixel circuit unit.

[0024] The 1-1 light-emitting element and the 1-2 light-emitting element may emit a first light, the 1-3 light-emitting element may emit a second light different from the first light, and the 1-4 light-emitting element may emit a third light different from the first light and the second light. [Effects of the Invention]

[0025] The display device of the embodiment can improve the display quality. [Brief explanation of the drawings]

[0026] [Figure 1] 1 is a block diagram of a display device according to an embodiment of the present invention; [Figure 2] FIG. 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. [Figure 3] 3 is a waveform diagram of a driving signal for driving the pixel shown in FIG. 2. FIG. [Figure 4] 1 is a diagram illustrating a display panel according to an embodiment of the present invention; [Figure 5] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention. [Figure 6] 1 is a plan view of a display panel according to an embodiment of the present invention; [Figure 7] FIG. 2 is a plan view of a pixel circuit according to an embodiment of the present invention. [Figure 8] 2 is a plan view showing a part of a pattern included in a pixel circuit according to an embodiment of the present invention; [Figure 9a] 1 is a plan view showing a partial configuration of a display panel according to an embodiment of the present invention. [Figure 9b] 1 is a plan view showing a partial configuration of a display panel according to an embodiment of the present invention. [Figure 10] FIG. 10 is a plan view of a display panel according to a comparative example. [Figure 11a] FIG. 10 is a plan view showing a partial configuration of a display panel according to a comparative example. [Figure 11b] FIG. 10 is a plan view showing a partial configuration of a display panel according to a comparative example. [Figure 12] FIG. 2 is a plan view of a pixel according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0027] Because the present invention can be modified in various ways and can take various forms, specific embodiments are shown by way of example in the drawings and described in detail herein, but it is to be understood that this is not intended to limit the invention to the particular disclosed form, but rather to include all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention.

[0028] As used herein, when a component (or region, layer, portion, etc.) is referred to as being "on" or "coupled" to another component, it means that it may be directly positioned, coupled, or connected to the other component, or that a third component may be disposed therebetween.

[0029] On the other hand, in this application, "directly disposed" may mean that there is no additional layer, film, region, plate, etc. between one layer, film, region, plate, etc. and another. For example, "directly disposed" may mean that two layers or two components are disposed without using an additional member such as an adhesive member between them.

[0030] The same reference numerals refer to the same elements. In the drawings, the thickness, proportions, and dimensions of the elements are exaggerated for the purpose of effectively explaining the technical content. "And / or" includes all combinations of one or more elements defined by the associated elements.

[0031] Terms such as "first" and "second" are used to describe various components, but the components are not limited to these terms. These terms are used only to distinguish one component from another. For example, a first component may be called a "second component" without departing from the scope of the present invention, and similarly, a second component may be called a "first component." The singular "a" includes plural expressions unless the context clearly dictates otherwise.

[0032] Furthermore, terms such as "under," "below," "on," and "above" are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings. In this specification, "disposed above" refers to being disposed not only above but also below any one component.

[0033] It should be understood that the terms "comprise" or "have" and the like specify the presence of any feature, number, step, operation, component, part, or combination thereof set forth above in the specification, but do not preclude the presence or possible addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present invention belongs. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted to have a meaning consistent with the meaning they have in the context of the relevant art, and should not be interpreted in an overly ideal or formal sense unless explicitly defined herein.

[0035] A display panel according to an embodiment of the present invention will now be described with reference to the accompanying drawings.

[0036] 1 is a block diagram of a nail display device DD according to an embodiment of the present invention. The display device DD includes a timing controller TC, a scan driver circuit SDC, a data driver circuit DDC, and a display panel DP. In this embodiment, the display panel DP is described as an emissive display panel. The emissive display panel may include an organic light-emitting display panel or an inorganic light-emitting display panel.

[0037] The timing controller TC receives the input video signal, converts the timing format of the input video signal to match the interface specifications with the scan driver circuit SDC, and generates video data D-RGB. The timing controller TC outputs the video data D-RGB and various control signals DCS and SCS.

[0038] The scan driving circuit SDC receives a scan control signal SCS from the timing controller TC. The scan control signal SCS may include a vertical start signal that initiates the operation of the scan driving circuit SDC and a clock signal that determines the output timing of the signal. The scan driving circuit SDC generates a plurality of scan signals and sequentially outputs them to corresponding scan signal lines SL11 to SL1n. In addition, the scan driving circuit SDC generates a plurality of light emitting control signals in response to the scan control signal SCS and outputs the plurality of light emitting control signals to corresponding light emitting signal lines EL1 to ELn.

[0039] 1 shows that a plurality of scan signals and a plurality of light emission control signals are output from one scan driving circuit SDC, but the present invention is not limited thereto. In one embodiment of the present invention, the display device DD may include a plurality of scan driving circuits. In another embodiment of the present invention, the driving circuit that generates and outputs a plurality of scan signals and the driving circuit that generates and outputs a plurality of light emission control signals are formed separately.

[0040] The data driving circuit DDC receives a data control signal DCS and video data D-RGB from the timing controller TC. The data driving circuit DDC converts the video data D-RGB into data signals and outputs the data signals to a plurality of data lines DL1 to DLm (described later). The data signals are analog voltages corresponding to the grayscale values ​​of the video data D-RGB.

[0041] The display panel DP may include multiple groups of scan lines. A first group of scan signal lines SL11 to SL1n is shown in FIG. 1 as an example. The display panel DP includes light emitting signal lines EL1 to ELn, data lines DL1 to DLm, a first voltage line VL1, a second voltage line VL2, a third voltage line VL3, a fourth voltage line VL4, and a plurality of pixels PX.

[0042] The first group of scan signal lines SL1 to SLn may extend in a first direction DR1 and be arranged in a second direction DR2, and the data lines DL1 to DLm may cross the first group of scan signal lines SL11 to SL1n.

[0043] The first voltage line VL1 receives the first power supply voltage ELVSS. The second voltage line VL2 receives the second power supply voltage ELVDD. The second power supply voltage ELVDD has a higher level than the first power supply voltage ELVSS. The third voltage line VL3 receives a reference voltage Vref (hereinafter referred to as the first voltage). The fourth voltage line VL4 receives an initialization voltage Vint (hereinafter referred to as the second voltage). The first voltage Vref has a lower level than the second power supply voltage ELVDD. The second voltage Vint has a lower level than the second power supply voltage ELVDD. In this embodiment, the second voltage Vint may have a lower level than the first voltage Vref and the first power supply voltage ELVSS.

[0044] At least one of the first voltage line VL1, the second voltage line VL2, the third voltage line VL3, and the fourth voltage line VL4 may include at least one of a line extending in a first direction DR1 and a line extending in a second direction DR2. The voltage lines extending in the first direction DR1 and the voltage lines extending in the second direction DR2 may be electrically connected to each other even if they are disposed on different layers among the plurality of insulating layers 10 to 40 shown in FIG.

[0045] Although the display device DD according to one embodiment has been described with reference to FIG. 1, the display device DD of the present invention is not limited thereto. Signal lines may be added or omitted depending on the configuration of the pixel driving circuit. Furthermore, the electrical connection relationship between one pixel PX and the signal lines may be changed.

[0046] The plurality of pixels PX may include a plurality of groups that generate light of different colors. For example, the plurality of pixels PX may include a red pixel that generates red light, a green pixel that generates green light, and a blue pixel that generates blue light. The light emitting diodes of the red pixels, the green pixel light emitting diodes, and the blue pixel light emitting diodes may include light emitting layers made of different materials.

[0047] The pixel driving circuit may include a plurality of transistors and at least one capacitor. At least one of the scan driving circuit SDC and the data driving circuit DDC may include a plurality of transistors formed by the same process as the pixel driving circuit.

[0048] The above-mentioned signal lines, the plurality of pixels PX, the scan driving circuit SDC, and the data driving circuit DDC can be formed on the base substrate by performing photolithography and etching processes multiple times.

[0049] A plurality of insulating layers may be formed on the base substrate through a plurality of deposition or coating processes. The plurality of insulating layers may include organic layers and / or inorganic layers. Any one of the plurality of insulating layers may include a plurality of insulating patterns. Each of the plurality of insulating layers may overlap a plurality of pixels PX. Contact holes may be formed in the plurality of insulating layers. The plurality of contact holes may be arranged in a predetermined pattern for each of the plurality of pixels PX.

[0050] Fig. 2 is an equivalent circuit diagram of a pixel PXij according to an embodiment of the present invention, and Fig. 3 is a waveform diagram of a driving signal for driving the pixel PXij shown in Fig. 2.

[0051] 2 shows a pixel PXij connected to the ith scan line SL1i of the first group of scan lines SL11 to SL1n (see FIG. 1) and the jth data line DLj of the plurality of data lines DL1 to DLm (see FIG. 1). The pixel PXij is connected to the ith scan line SL2i of the second group of scan lines and the ith scan line SL3i of the third group of scan lines.

[0052] In this embodiment, the driving circuit may include first to fifth transistors T1 to T5, a storage capacitor Cst, a hold capacitance Chold, and a light emitting diode OLED. In this embodiment, the first to fifth transistors T1 to T5 are described as N-type. However, this is not limited thereto, and at least one of the first to fifth transistors T1 to T5 may be a P-type transistor. In another embodiment of the present invention, at least one of the first to fifth transistors T1 to T4 may be omitted, or an additional transistor may be further included in the pixel PXij.

[0053] In this embodiment, although each of the first to fifth transistors T1 to T5 is shown to include a gate, at least one of the transistors may include only one gate. Although the upper gates G2-1, G3-1, G4-1, and G5-1 and the lower gates G2-2, G3-2, G4-2, and G5-2 of the second to fifth transistors T2 to T5 are shown to be electrically connected to each other, this is not limitative. The lower gates G2-2, G3-2, G4-2, and G5-2 of the second to fifth transistors T2 to T5 may be floating electrodes.

[0054] In this embodiment, the first transistor T1 may be a driving transistor, and the second transistor T2 may be a switching transistor. A node to which the gate G1-1 of the first transistor T1 is connected may be defined as a first node ND1, and a node to which the source S1 of the first transistor T1 is connected may be defined as a second node ND2.

[0055] The light emitting diode OLED includes a first electrode electrically connected to the first node ND1, a second electrode receiving the first power supply voltage ELVSS, and a light emitting layer disposed between the first electrode and the second electrode. The light emitting diode OLED will be described in detail later.

[0056] The first transistor T1 is electrically connected between a second power line VL2 receiving a second power voltage ELVDD and a second node ND2. The first transistor T1 may include a source S1 (hereinafter, first source) connected to the second node ND2, a drain D1 (hereinafter, first drain), a semiconductor region, and a gate G1-1 (hereinafter, upper gate) electrically connected to the second node ND2. The first transistor T1 may further include a gate G1-2 (hereinafter, lower gate) connected to the second node ND2.

[0057] The second transistor T2 is electrically connected between the first data line DLj and the first node ND1. The second transistor T2 may include a source S2 connected to the first node ND1, a drain (hereinafter referred to as the second drain) connected to the first data line DLj, a semiconductor region, and a gate G2-1 (hereinafter referred to as the second upper gate) connected to the i-th scan line SL1i of the first group. The second transistor T2 may further include a gate G2-2 electrically connected to the second upper gate G2-1. The third to fifth transistors T3 to T4, which will be described later, include upper gates G3-1, G4-1, and G5-1 and lower gates G3-2, G4-2, and G5-2 corresponding to the second upper gate G2-1 and the second lower gate G2-2.

[0058] The third transistor T3 is electrically connected between the first node ND1 and a third voltage line VL3 receiving the first voltage Vref. The third transistor T3 may include a drain D3 (hereinafter, a third drain) connected to the first node ND1, a source S3 (hereinafter, a third source) connected to the third voltage line VL3, a semiconductor region, and a third upper gate G3-1 connected to the i-th scan line SL2i of the second group.

[0059] The fourth transistor T4 is electrically connected between a first voltage line VL4 receiving a second voltage Vint and a second node ND2, and may include a drain D4 (hereinafter, a fourth drain) connected to the second node ND2, a source S4 (hereinafter, a fourth source) connected to the fourth voltage line VL4, a semiconductor region, and a fourth upper gate G4-1 connected to the i-th scan line SL3i of the third group.

[0060] The fifth transistor T5 is electrically connected between the second voltage line VL2 and the first drain D1 or the first source S1. In this embodiment, the fifth transistor T5 may include a source S5 (hereinafter referred to as a fifth source) connected to the second power line VL2, a drain D5 (hereinafter referred to as a fifth drain) connected to the first drain D1, a semiconductor region, and a fifth upper gate G5-1 connected to the i-th light-emitting signal line ELi.

[0061] The storage capacitor Cst is electrically connected between the first node ND1 and the second node ND2, and includes a first electrode E1-1 connected to the first node ND1 and a second electrode E1-2 connected to the second node ND2.

[0062] The hold capacitor Chold is electrically connected between the second voltage line VL2 and the second node ND2, and includes a first electrode E2-1 connected to the second voltage line VL2 and a second electrode E2-2 connected to the second node ND2.

[0063] Meanwhile, a gap capacitor Cga, which is a parasitic capacitor, may be formed between the upper gate G1-1 of the first transistor T1 and the anode electrode of the light emitting diode OLED. The gap capacitor Cga may have the upper gate G1-1 of the first transistor T1 as a first electrode E3-1 and the anode electrode of the light emitting diode OLED as a second electrode E3-2. That is, the gap capacitor Cga may be electrically connected between the first node ND1 and the second node ND2. As a result, the gap capacitor Cga may be connected in parallel with the storage capacitor Cst, and the capacitance of the gap capacitor Cga may be added to the capacitance of the storage capacitor Cst.

[0064] The operation of pixel PXij will be described in more detail with reference to Figures 2 and 3. The display device DD (see Figure 1) displays an image every frame period. The first group of scan lines, the second group of scan lines, the third group of scan lines, and the light-emitting signal lines are sequentially scanned during the frame period. Figure 3 shows a portion of the frame period.

[0065] 3, each of the signals Ei, GRi, GWi, and GIi may have a high level (V-HIGH) for a certain period and a low level V-LOW for a certain period, and the first to fifth N-type transistors T1 to T5 are turned on when the corresponding control signal has a high level V-HIGH.

[0066] During the initialization period IP, the third transistor T3 and the fourth transistor T4 are turned on. The first node ND1 is initialized to the first voltage Vref. The second node ND2 is initialized to the second voltage Vint. The storage capacitor Cst is initialized to the difference between the first voltage Vref and the second voltage Vint. The hold capacitor Chold is initialized to the difference between the second power supply voltage ELVDD and the second voltage Vint.

[0067] During the compensation period CP, the third transistor T3 and the fifth transistor T5 are turned on, and the storage capacitor Cst is compensated with a voltage equivalent to the threshold voltage of the first transistor T1.

[0068] During the write period WP, ​​the second transistor T2 is turned on. The second transistor T2 outputs a voltage corresponding to the data signal DS. As a result, the storage capacitor Cst is charged with a voltage corresponding to the data signal DS. The storage capacitor Cst is charged with the data signal DS, which is compensated for by the threshold of the first transistor T1. Although the threshold of the drive transistor varies for each pixel PX (see FIG. 1), the pixel PXij shown in FIGS. 2 and 3 can supply a current proportional to the data signal DS to the light emitting diode OLED, regardless of the deviation in the threshold of the drive transistor.

[0069] Next, during the light-emitting period, the fifth transistor T5 is turned on. The first transistor T1 provides a current corresponding to the voltage stored in the storage capacitor Cst to the light-emitting diode OLED. The light-emitting diode OLED can emit light with a brightness corresponding to the data signal DS.

[0070] In the present invention, the value of the gap capacitor Cga generated for each pixel PXij is adjusted in the same way, and the value of the capacitance formed between the first node ND1 and the second node ND2, i.e., the sum of the capacitance of the storage capacitor Cst and the capacitance of the gap capacitor Cga, can be controlled in the same way for each pixel, thereby improving the display quality of the display device DD (see FIG. 1) including a plurality of pixels PXij.

[0071] FIG. 4 is a diagram showing a simplified display panel DP according to an embodiment of the present invention.

[0072] FIG. 4 shows the light emitting element layer DP-OLED and the circuit layer DP-CL included in the display panel DP.

[0073] The light-emitting element layer DP-OLED may include a plurality of light-emitting element units EDU. In one embodiment, the plurality of light-emitting element units EDU may include first to fourth light-emitting element units EDU1, EDU2, EDU3, and EDU4 adjacent to each other. The light-emitting element layer DP-OLED may have a structure in which the illustrated first to fourth light-emitting element units EDU1, EDU2, EDU3, and EDU4 are repeatedly arranged on a plane.

[0074] In the first direction DR1, the second light-emitting element unit EDU2 may be arranged below the first light-emitting element unit EDU1, and the fourth light-emitting element unit EDU4 may be arranged below the third light-emitting element unit EDU3.

[0075] In the second direction DR2, the third light-emitting element unit EDU3 can be arranged below the first light-emitting element unit EDU1, and the fourth light-emitting element unit EDU4 can be arranged below the second light-emitting element unit EDU2.

[0076] Each of the first to fourth light-emitting element units EDU1, EDU2, EDU3, and EDU4 may include a first light-emitting element ED1-1, ED2-1, ED3-1, and ED4-1 that emits a first light, a second light-emitting element ED1-2, ED2-2, ED3-2, and ED4-2 that emits a second light different from the first light, and a third light-emitting element ED1-3, ED2-3, ED3-3, and ED4-3 that emits a third light different from the first light and the second light. In Figure 4, the shapes of the first to third light-emitting elements ED1-1, ED2-1, ED3-1, ED4-1, ED1-2, ED2-2, ED3-2, ED4-2, ED1-3, ED2-3, ED3-3, and ED4-3 are shown based on the light-emitting area.

[0077] In the first light-emitting device unit EDU1 according to the embodiment, the first light-emitting device ED1-1 may have a shape extending in the first direction DR1, and the second and third light-emitting devices ED1-2 and ED1-3 may be disposed on one side of the first light-emitting device ED1-1 in the second direction DR2. The same explanation applies to the second to fourth light-emitting device units EDU2, EDU3, and EDU4.

[0078] Meanwhile, in the first direction DR1, the first light-emitting element ED1-1 of the first light-emitting element unit EDU1 may face the first light-emitting element ED2-1 of the second light-emitting element unit EDU2, and the first light-emitting element ED3-1 of the third light-emitting element unit EDU3 may face the first light-emitting element ED4-1 of the fourth light-emitting element unit EDU4.

[0079] In this case, a distance LL1 between the first light emitting element ED1-1 of the first light emitting element unit EDU1 and the first light emitting element ED2-1 of the second light emitting element unit EDU2 may be shorter than a distance LL2 between the first light emitting element ED3-1 of the third light emitting element unit EDU3 and the first light emitting element ED4-1 of the fourth light emitting element unit EDU4. By including the above-mentioned structure, the display panel DP of the present invention can improve visibility by arranging the first light emitting elements ED1-1, ED2-1, ED3-1, and ED4-1 in the same positions for each of the first to fourth light emitting units EDU1, EDU2, EDU3, and EDU4.

[0080] Meanwhile, the second light emitting elements ED1-2, ED2-2, ED3-2, and ED4-2 and the third light emitting elements ED1-3, ED2-3, ED3-3, and ED4-3 may be arranged at the same positions for each of the first to fourth light emitting element units EDU, but this is not limited to this embodiment.

[0081] The circuit layer DP-CL may be disposed below the light-emitting element layer DP-OLED. The circuit layer DP-CL may include a plurality of pixel circuit units PCU. Each of the pixel circuit units PCU is connected to a corresponding one of the light-emitting element units EDU and drives the connected light-emitting element units EDU. FIG. 4 illustrates first to third pixel transistors T_B, T_G, and T_R as part of the pixel circuit unit PCU. The first to third pixel transistors T_B, T_G, and T_R may be electrically connected to the first to third light-emitting elements ED1-1, ED1-2, and ED1-3, respectively. Each of the first to third pixel transistors T_B, T_G, and T_R may be a driving transistor. That is, in one embodiment, each of the first to third pixel transistors T_B, T_G, and T_R may correspond to the first transistor T1 described above in FIG. 1.

[0082] The first pixel transistor T_B and the first light emitting element ED1-1 connected thereto may constitute one pixel. The second pixel transistor T_G and the second light emitting element ED1-2 connected thereto may constitute one pixel. The third pixel transistor T_R and the third light emitting element ED1-3 connected thereto may constitute one pixel. However, embodiments are not limited thereto, and the first light emitting element unit EDU1 and one pixel circuit unit PCU connected thereto may be defined as one pixel.

[0083] 5 is a cross-sectional view of a display panel DP according to an embodiment of the present invention, including a first light-emitting element ED1-1 (hereinafter referred to as the first light-emitting element) of the first light-emitting element unit EDU1 and a first light-emitting element ED2-1 (hereinafter referred to as the second light-emitting element) of the second light-emitting element unit EDU2, as described above in FIG.

[0084] Two first transistors T1 may be disposed below the first light emitting element ED1-1 and the second light emitting element ED2-1. In a plan view, the first light emitting element ED1-1 and the second light emitting element ED2-1 may be disposed to overlap the first transistor T1.

[0085] In one embodiment, two first transistors T1 may be electrically connected to the first light emitting element ED1-1 and the second light emitting element ED2-1. In this case, each of the two first transistors T1 may be the first pixel transistor T_B described above in FIG. 4. That is, in another portion of the display panel DP, the sources S1 of the two first transistors T1 may be electrically connected to the anode electrodes AE (or first electrodes) of the first light emitting element ED1-1 and the second light emitting element ED2-1.

[0086] However, embodiments are not limited thereto. For example, at least one of the two first transistors T1 may not be connected to the first light emitting element ED1-1 or the second light emitting element ED2-1, but may be connected to the second light emitting element ED1-2, ED2-2, or the third light emitting element ED1-3, ED2-3. For example, the first light emitting element ED1-1 may overlap in a planar view with the second pixel transistor T_G connected to the second light emitting element ED1-2 arranged adjacent to the first light emitting element ED1-1 in FIG. 4. Alternatively, the first light emitting element ED1-1 may overlap in a planar view with the third pixel transistor T_R connected to the third light emitting element ED1-3 arranged adjacent to the first light emitting element ED1-1 in FIG. 4.

[0087] As described above, the first transistor T1 shown in FIG. 5 does not necessarily need to be electrically connected to the first light-emitting element ED1-1 or the second light-emitting element ED2-1, and the following description may apply if one first transistor T1 overlaps one light-emitting element ED1-1.

[0088] 5, the display panel DP may include a base layer BS, a circuit layer DP-CL disposed on the base layer BD, a display element layer DP-OLED, and a thin-film encapsulation layer TFE. The display panel DP may further include a functional layer such as an anti-reflection layer or a refractive index adjustment layer. The circuit layer DP-CL may include at least a plurality of insulating layers, semiconductor patterns, conductive patterns, and signal lines. The insulating layers described below may include an organic layer and / or an inorganic layer.

[0089] The base layer BS may be a synthetic resin layer containing a synthetic resin. The synthetic resin film may include a thermosetting resin. In particular, the synthetic resin layer is a polyimide-based resin layer, but the material is not particularly limited. The synthetic resin layer may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene-based resin, a vinyl resin, an epoxy resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a ferylene-based resin. Alternatively, the base layer BS may include a glass substrate, a metal substrate, an organic / inorganic composite material substrate, or the like.

[0090] At least one inorganic layer is formed on the upper surface of the base layer BS. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be composed of multiple layers. The multiple inorganic layers may constitute a barrier layer BRL and / or a buffer layer BFL, which will be described later. The barrier layer BRL and the buffer layer BFL may be selectively disposed.

[0091] The barrier layer BRL may prevent foreign substances from entering from the outside. The barrier layer BRL may include a silicon oxide layer and a silicon nitride layer. A plurality of each of these may be provided, and the silicon oxide layers and the silicon nitride layers may be stacked alternately.

[0092] A conductive layer (hereinafter referred to as the first conductive layer) is disposed on the barrier layer BRL. The first conductive layer may include a plurality of conductive patterns. FIG. 5 shows a partial pattern of the first conductive layer. The lower gate G1-2 is shown as an example of the conductive pattern of the first conductive layer.

[0093] A buffer layer BFL may be disposed on the barrier layer BRL to cover the lower gate G1-2. The buffer layer BFL improves the bonding strength between the base layer BS and the semiconductor pattern and / or the conductive pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0094] A semiconductor layer is disposed on the buffer layer BFL. The semiconductor layer may include a plurality of semiconductor patterns. The semiconductor patterns may include a metal oxide. The metal oxide semiconductor may include a crystalline or amorphous oxide semiconductor. For example, the oxide semiconductor may include a metal oxide including zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), etc., or a mixture of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), etc. and these oxides. The oxide semiconductor may include indium-tin oxide (ITO), indium-gallium-zinc oxide (IGZO), zinc oxide (ZnO), indium-zinc oxide (IZnO), zinc-indium oxide (ZnO), titanium oxide (TiO), indium-zinc-tin oxide (IZTO), zinc-tin oxide (ZTO), etc.

[0095] The semiconductor pattern may include multiple regions that are distinguished by whether or not the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter referred to as the reduced region) has higher conductivity than the region where it is not reduced (hereinafter referred to as the non-reduced region). The reduced region essentially functions as the source / drain or signal line of the transistor. The non-reduced region essentially corresponds to the semiconductor region (or channel) of the transistor. In other words, one part of the semiconductor pattern may be the semiconductor region of the transistor, another part may be the source / drain of the transistor, and still another part may be the signal transmission region.

[0096] The source S1, semiconductor region A1, and drain D1 of the first transistor T1 are formed of semiconductor patterns, and extend in opposite directions from the semiconductor region A1.

[0097] The lower gate G1-2 described above functions as a light-shielding pattern. The lower gate G1-2 is disposed under the semiconductor region A1 of the first transistor T1 and blocks external light from entering the first transistor T1. The light-shielding pattern prevents external light from changing the voltage-current characteristics of the first transistor T1.

[0098] A first insulating layer 10 is disposed on the buffer layer BFL. In this embodiment, the first insulating layer 10 is not formed over the entire display panel DP, but overlaps only specific conductive patterns, which will be described later. The first insulating layer 10 includes a plurality of insulating patterns. FIG. 4 exemplarily shows a first insulating pattern 10-1 and a second insulating pattern 10-2.

[0099] The first insulating pattern 10-1 overlaps the lower gate G1-2 and the upper gate G1-1 (described later), and the second insulating pattern 10-2 overlaps the first conductive pattern P1 (or gate conductive layer) (described later).

[0100] A conductive layer (hereinafter, referred to as the second conductive layer) is disposed on the first insulating layer 10. The second conductive layer may include a plurality of conductive patterns overlapping the insulating patterns 10-1 and 10-2 of the first insulating layer 10, respectively. In FIG. 5, an upper gate G1-1 and a first conductive pattern P1 are shown as examples of the conductive patterns of the second conductive layer. Because the second conductive layer and the first insulating layer are etched using the same process, the conductive pattern of the second conductive layer and the insulating pattern of the first insulating layer have substantially the same shape.

[0101] The first conductive pattern P1 defines the first electrode E1-1 of the storage capacitor Cst shown in FIG. 2. Although the first conductive pattern P1 is shown as being separated from the upper gate G1-1 of the first transistor T1 in cross section, the first conductive pattern P1 may have an integral shape with the upper gate G1-1 of the first transistor T1. That is, a first portion of any one conductive pattern may correspond to the upper gate G1-1 of the first transistor T1, and a second portion may correspond to the first conductive pattern P1.

[0102] A second insulating layer 20 is disposed on the buffer layer BFL, covering the upper gate G1-1 and the first conductive pattern P1. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure.

[0103] A conductive layer (hereinafter referred to as the third conductive layer) is disposed on the second insulating layer 20. The third conductive layer may include a plurality of conductive patterns. In Figure 5, the second conductive pattern P2 is shown as an example of the conductive pattern of the third conductive layer.

[0104] A second conductive pattern P2 overlapping the first conductive pattern P1 may be disposed on the second insulating layer 20. The second conductive pattern P2 defines the second electrode E1-2 of the storage capacitor Cst and the second electrode E2-2 of the hold capacitor Chold shown in FIG.

[0105] A third insulating layer 30 covering the third conductive pattern P2 is disposed on the second insulating layer 20. In this embodiment, the third insulating layer 30 may be an organic layer and may have a single-layer structure, but is not limited thereto.

[0106] A conductive layer (hereinafter, referred to as a fourth conductive layer) is disposed on the third insulating layer 30. The fourth conductive layer may include a plurality of conductive patterns. The fourth conductive layer includes a third conductive pattern P3 that defines a first electrode E2-1 of the hold capacitor Chold shown in FIG. 2. An opening P3-OP may be defined in the third conductive pattern P3.

[0107] The fourth conductive layer may further include a plurality of connecting electrodes. First and second connecting electrodes CNE1 and CNE2 are shown in FIG. 4 as an example. The first connecting electrode CNE1 is connected to the first source S1 through a contact hole H1 that penetrates the second and third insulating layers 20 and 30, and the second connecting electrode CNE2 is connected to the second conductive pattern P2 through a contact hole H2 that penetrates the third insulating layer 30.

[0108] A fourth insulating layer 40 covering the third conductive layer is disposed on the third insulating layer 30. In this embodiment, the fourth insulating layer 40 may be an organic layer and may have a single-layer structure, but is not particularly limited thereto.

[0109] A conductive layer (hereinafter, referred to as a fifth conductive layer) is disposed on the fourth insulating layer 40. The fifth conductive layer may include a plurality of conductive patterns. The fifth conductive layer includes a third connecting electrode CNE3. The third connecting electrode CNE3 is connected to the second connecting electrode CNE2 via a contact hole H3 that penetrates the fourth insulating layer 40.

[0110] A fifth insulating layer 50 covering the fourth conductive layer is disposed on the fourth insulating layer 40. In this embodiment, the fifth insulating layer 50 may be an organic layer and may have a single-layer structure, but is not particularly limited thereto.

[0111] Anode electrodes AE-1 and AE-2 of the light emitting diode OLED are disposed on the fifth insulating layer 50. A pixel defining layer PDL is disposed on the fifth insulating layer 50. The anode electrodes AE-1 and AE-2 are connected to the third connecting electrode CNE3 via a contact hole H4 that penetrates the fifth insulating layer 50.

[0112] In one embodiment, the first light-emitting element ED1-1 and the second light-emitting element ED2-1 may each include an anode electrode AE-1, AE-2, a hole control layer HCL, an emitting layer EML, an electron control layer ECL, and a cathode electrode CE (or a second electrode).

[0113] The pixel definition layer PDL may expose at least a portion of the anode electrodes AE-1 and AE-2 to define the light emitting areas PXA-1 and PXA-2. The non-display area NPXA may surround the light emitting areas PXA-1 and PXA-2 on a plane.

[0114] For example, the first pixel opening PDL-OP1 of the pixel defining layer PDL may expose a first region AR1 of the anode electrode AE-1 of the first light emitting element ED1-1 to define a light emitting region PXA-1. The second pixel opening PDL-OP2 of the pixel defining layer PDL may expose a second region AR2 of the anode electrode AE-2 of the second light emitting element ED2-1 to define a light emitting region PXA-2. The anode electrode AE-1 of the first light emitting element ED1-1 and the anode electrode AE-2 of the second light emitting element ED2-1 may have the same area, and the first region AR1 and the second region AR2 within each anode electrode AE-1, AE-2 may be different areas. For example, the first region AR1 may not overlap the upper gate G1-1 of the first transistor T1 in a planar view, and the second region AR2 may overlap the upper gate G1-1 of the first transistor T1 in a planar view.

[0115] Meanwhile, the anode electrodes AE-1 and AE-2 of the light emitting elements ED1-1 and ED1-2 may form a gap capacitor Gga together with the upper gate G1-1 of the first transistor T1 disposed thereunder. More specifically, the anode electrode AE-1 of the first light emitting element ED1-1 may form a first gap capacitor C1 together with the upper gate G1-1 of the first transistor T1, and the anode electrode AE-2 of the second light emitting element ED2-1 may form a second gap capacitor C2 together with the upper gate G1-1 of the first transistor T1. The first gap capacitor C1 and the second gap capacitor C2 may each correspond to the gap capacitor Cga described above with reference to FIG. 2.

[0116] In the present invention, the overlapping area between the anode electrode AE-1 and the upper gate G1-1 of the first light emitting element ED1-1 may be the same as the overlapping area between the anode electrode AE-2 and the upper gate G1-1 of the second light emitting element ED2-1, and therefore the size of the first gap capacitor C1 may be substantially the same as the size of the second gap capacitor C2, and the deviation of the gap capacitors C1 and C2 between adjacent light emitting elements ED1-1 and ED2-1 may be substantially zero.

[0117] The hole control layer HCL may be disposed on the anode electrodes AE-1 and AE-2. The hole control layer HCL may be disposed in common in the light-emitting region PXA and the non-light-emitting region NPXA. In one embodiment, the hole control layer HCL may include a hole transport layer and a hole injection layer.

[0118] An emitting layer EML is disposed on the hole control layer HCL. The emitting layer EML may be disposed only in the regions corresponding to the pixel openings PDL-OP1 and PDL-OP2. The emitting layer EML may be formed separately for each of the light-emitting elements ED1-1 and ED1-2. In this embodiment, a patterned emitting layer EML is illustrated as an example, but the emitting layer EML may be disposed in common for a plurality of light-emitting elements ED1-1 and ED1-2. The emitting layer EML disposed in common may generate white light or blue light. The emitting layer EML may also have a multilayer structure.

[0119] An electronic control layer ECL is disposed on the light-emitting layer EML. In one embodiment, the electronic control layer ECL may include an electron transport layer and an electron injection layer. A cathode electrode CE is disposed on the electronic control layer ECL. The electronic control layer ECL and the cathode electrode CE are disposed in common to the light-emitting elements ED1-1 and ED1-2.

[0120] A thin film encapsulation layer TFE is disposed on the cathode electrode CE. The thin film encapsulation layer TFE is disposed in common to the light emitting elements ED1-1 and ED1-2. In this embodiment, the thin film encapsulation layer TFE directly covers the cathode electrode CE. In one embodiment of the present invention, a capping layer directly covering the cathode electrode CE may be further disposed. The thin film encapsulation layer TFE includes at least an inorganic layer or an organic layer. In one embodiment of the present invention, the thin film encapsulation layer TFE may include two inorganic layers and an organic layer disposed therebetween. In one embodiment of the present invention, the thin film encapsulation layer TFE may include multiple inorganic layers and multiple organic layers that are alternately stacked.

[0121] FIG. 6 is a plan view of a display panel DP according to an embodiment of the present invention.

[0122] Figure 6 shows a partial configuration of the display panel DP shown in Figure 4. Figure 6 shows first to fourth pixel circuit units PCU1, PCU2, PCU3, and PCU4 and first to fourth anode electrodes AE-1, AE-2, AE-3, and AE-4.

[0123] The first to fourth pixel circuit units PCU1, PCU2, PCU3, and PCU4 may be electrically connected to the four light emitting device units EDU1, EDU2, EDU3, and EDU4 described above with reference to FIG. 4, respectively.

[0124] Each of the first to fourth pixel circuit units PCU1, PCU2, PCU3, and PCU4 may include a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3. The first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 may be circuits for driving the first to third light emitting elements ED1-1, ED1-2, and ED1-3, respectively, described in FIG. 4. That is, the first pixel circuit PC1, the second pixel circuit PC2, and the third pixel circuit PC3 may include the first to third pixel transistors T_B, T_G, and T_R, respectively, described in FIG. 4. Meanwhile, the first pixel circuit PC1 included in the first pixel circuit unit PCU1 may be the 1-1 pixel circuit. The first pixel circuit PC1 included in the second pixel circuit unit PCU2 may be the 1-2 pixel circuit. The first pixel circuit PC1 included in the third pixel circuit unit PCU3 may be the 1-3 pixel circuit. The first pixel circuit PC1 included in the fourth pixel circuit unit PCU4 may be a first to fourth pixel circuit.

[0125] The first to fourth anode electrodes AE-1, AE-2, AE-3, and AE-4 may be included in the first light-emitting elements ED1-1, ED2-1, ED3-1, and ED4-1 (see FIG. 4) described above in FIG. 6. In FIG. 6, first to third light-emitting regions PXA-B, PXA-G, and PXA-R are shown instead of the first to third light-emitting elements ED1-1, ED1-2, and ED1-3. In one embodiment, the first light-emitting region PXA-B may emit blue light, the second light-emitting region PXA-G may emit green light, and the third light-emitting region PXA-R may emit red light. However, embodiments are not limited thereto.

[0126] The first to third light-emitting regions PXA-B, PXA-G, and PXA-R may be defined by pixel openings. For example, the first light-emitting region PXA-B may be defined corresponding to the shapes of the first to fourth pixel openings PDL-OP1, PDL-OP2, PDL-OP3, and PDL-OP4. The first to fourth pixel openings PDL-OP1, PDL-OP2, PDL-OP3, and PDL-OP4 may at least partially expose the first to fourth anode electrodes AE-1, AE-2, AE-3, and AE-4, respectively.

[0127] The first anode electrode AE-1 may be similarly described with respect to the anode electrode AE-1 of the first light emitting element ED1-1 described above in connection with Fig. 5. The second anode electrode AE-2 may be similarly described with respect to the anode electrode AE-2 of the second light emitting element ED2-1 described above in connection with Fig. 5. The first and second pixel openings PDL-OP1 and PDL-OP2 may be similarly described with respect to the first and second pixel openings PDL-OP1 and PDL-OP2 described above in connection with Fig. 5.

[0128] Furthermore, the description of the second anode electrode AE-2 and second pixel opening PDL-OP2 in the second pixel circuit unit PCU2 can be applied to the description of the third anode electrode AE-3 and third pixel opening PDL-OP3 in the third pixel circuit unit PCU3. The description of the first anode electrode AE-1 and first pixel opening PDL-OP1 in the first pixel circuit unit PCU1 can be applied to the description of the fourth anode electrode AE-4 and fourth pixel opening PDL-OP4 in the fourth pixel circuit unit PCU4.

[0129] As described above with reference to FIG. 4, one pixel may include one light-emitting element and a pixel circuit connected to the light-emitting element. For example, a first pixel may include a first light-emitting element ED1-1 (see FIG. 5) including a first anode electrode AE-1 and a first pixel circuit PC1 connected to the first light-emitting element ED1-1 (see FIG. 5). A second pixel may include a second light-emitting element ED2-1 (see FIG. 5) including a second anode electrode AE-2 and a first pixel circuit PC1 connected to the second light-emitting element ED2-1 (see FIG. 5). A third pixel may include a second light-emitting element ED2-1 (see FIG. 5) including a third anode electrode AE-3 and a first pixel circuit PC1 connected to the second light-emitting element ED2-1 (see FIG. 5).

[0130] In the first to fourth pixels, the positions and areas of the first to fourth anode electrodes AE-1, AE-2, AE-3, and AE-4 are the same, so that the overlapping areas of the first to fourth anode electrodes AE-1, AE-2, AE-3, and AE-4 and the first pixel circuit PC1 in the first to fourth pixels may be the same.

[0131] In contrast, the areas of the first to fourth pixel openings PDL-OP1, PDL-OP2, PDL-OP3, and PDL-OP4 are the same, but the positions of the first to fourth pixel openings PDL-OP1, PDL-OP2, PDL-OP3, and PDL-OP4 in the first to fourth pixels may be different from each other.

[0132] For example, in the first pixel, the first pixel opening PDL-OP1 may be adjacent to the lower end of the first pixel circuit PC1, in the second pixel, the second pixel opening PDL-OP2 may be adjacent to the upper end of the first pixel circuit PC1, in the third pixel, the third pixel opening PDL-OP3 may be adjacent to the upper end of the first pixel circuit PC1, and in the fourth pixel, the fourth pixel opening PDL-OP4 may be adjacent to the lower end of the first pixel circuit PC1. Thus, the distance LL1 between the first pixel opening PDL-OP1 and the second pixel opening PDL-OP2 may be smaller than the distance LL2 between the third pixel opening PDL-OP3 and the fourth pixel opening PDL-OP4.

[0133] Therefore, the area where a specific configuration included in the first pixel circuit PC1 and the first pixel opening PDL-OP1 overlap in a plane may be different from the area where a specific configuration included in the first pixel circuit PC1 and the second pixel opening PDL-OP2 overlap in a plane. For this, see Figures 7 and 9b.

[0134] Fig. 7 is a plan view of a pixel circuit PC1 according to an embodiment of the present invention. Fig. 8 is a plan view showing a portion of a pattern included in a pixel circuit PC1 according to an embodiment of the present invention. Figs. 7 and 8 are enlarged plan views showing a first pixel circuit PC1 according to an embodiment included in the first to fourth pixel circuit units PCU1, PCU2, PCU3, and PCU4 shown in Fig. 6.

[0135] 7, the first pixel circuit PC1 according to an embodiment may include multiple conductive layers. For example, the first pixel circuit PC1 may include the first to fifth conductive layers described above in FIG. 7 shows, as an example, first to fifth transistors T1, T2, T3, T4, and T5, a data line DLj, a first voltage line VL1, and a third voltage line VL3.

[0136] 8 shows a second conductive layer of the plurality of conductive layers included in the first pixel circuit PC1 shown in FIG. 7. The second conductive layer may include a plurality of conductive patterns, for example, the second conductive layer may include upper gates G1-1, G1-2, G1-3, G1-4, and G1-5 of the first, second, third, fourth, and fifth transistors T1 to T5 and a first conductive pattern P1. The first conductive pattern P1 may have a shape integral with the upper gate G1-1 of the first transistor T1.

[0137] Meanwhile, the first pixel circuit PC1 of the embodiment may include a first portion PT1, a second portion PT2, and a third portion PT3.

[0138] 9a and 9b are plan views showing a partial configuration of a display panel according to one embodiment of the invention. Specifically, Fig. 9a is a plan view of one embodiment in which the first pixel circuit PC1, first anode electrode AE-1, and first pixel opening PDL-OP1 of the first pixel circuit unit PCU1 shown in Fig. 6 are enlarged. Specifically, Fig. 9b is a plan view of one embodiment in which the first pixel circuit PC1, second anode electrode AE-2, and second pixel opening PDL-OP2 of the second pixel circuit unit PCU2 shown in Fig. 6 are enlarged.

[0139] 6 and 9a, in one embodiment, the first anode electrode AE-1 and the first pixel opening PDL-OP1 may overlap the first pixel circuit PC1 in a plan view. More specifically, the first anode electrode AE-1 may be disposed overlapping the first portion PT1, the second portion PT2, and the third portion PT3 of the first pixel circuit PC1. For example, the first anode electrode AE-1 may include a first electrode portion AE-PT1 overlapping the first portion PT1, a second electrode portion AE-PT2 overlapping the second portion PT2, and a third electrode portion AE-PT3 overlapping the third portion PT3.

[0140] In contrast to this, the first pixel opening portion PDL-OP1 can be arranged so as to overlap the first portion PT1 and the second portion PT2 of the first pixel circuit PC1, but not to overlap the third portion PT3.

[0141] 6 and 9b, in one embodiment, the second anode electrode AE-2 and the second pixel opening PDL-OP2 may overlap the first pixel circuit PC1 in a plan view. Specifically, the second anode electrode AE-2 may be arranged to overlap the first portion PT1, the second portion PT2, and the third portion PT3 of the first pixel circuit PC1. In contrast, the second pixel opening PDL-OP2 may be arranged to overlap the second portion PT2 and the third portion PT3 of the first pixel circuit PC1, but not overlap the first portion PT1.

[0142] 6 and 9b, the first pixel opening PDL-OP1 and the second pixel opening PDL-OP2 overlap different portions of the upper gate G1-1 of the first transistor T1, so that the overlapping area between the first pixel opening PDL-OP1 and the upper gate G1-1 of the first transistor T1 may be different from the overlapping area between the second pixel opening PDL-OP2 and the upper gate G1-1 of the first transistor T1.

[0143] However, because the first anode electrode AE-1 and the second anode electrode AE-2 are disposed in the same position in the first pixel circuit PC1, the overlapping area between the first anode electrode AE-1 and the upper gate G1-1 of the first transistor T1 is the same as the overlapping area between the second anode electrode AE-2 and the upper gate G1-1 of the first transistor T1, and therefore the sizes of the first gap capacitor C1 and the second gap capacitor C2 described in FIG.

[0144] 6, the display panel DP of the present invention has first and second pixel openings PDL-OP1 and PDL-OP2, but the overlapping area between the first anode electrode AE-1 and the upper gate G1-1 of the first transistor T1 and the overlapping area between the second anode electrode AE-2 and the upper gate G1-1 of the first transistor T1 are the same, so that the size of the gap capacitor Cga (see FIG. 2) between adjacent pixels can be substantially the same. Therefore, even if the gap capacitor Cga (see FIG. 2) is generated, the deviation of the storage capacitor Cst (see FIG. 2) between adjacent pixels can be substantially zero.

[0145] Fig. 10 is a plan view of a display panel according to a comparative example, and Fig. 11a and Fig. 11b are plan views showing a partial configuration of a display panel according to a comparative example.

[0146] 10, the sizes and positions of the first to fourth anode electrodes AE-1, AE-2, AE-3, and AE-4 are changed compared to the embodiment of FIG. 6. Specifically, the first to fourth anode electrodes AE-1, AE-2, AE-3, and AE-4 may have shapes that surround the first to fourth pixel openings PDL-OP1, PDL-OP2, PDL-OP3, and PDL-OP4, respectively. As a result, compared to the first to fourth anode electrodes AE-1, AE-2, AE-3, and AE-4 shown in FIG. 6, the first and fourth anode electrodes AE-1 and AE-4 may be arranged at the lower end of the first pixel circuit PC1, and the second and third anode electrodes AE-2 and AE-3 may be arranged at the upper end of the first pixel circuit PC1.

[0147] Fig. 11a is an enlarged plan view of one embodiment of the first pixel circuit PC1, first anode electrode AE-1, and first pixel opening PDL-OP1 of the first pixel circuit unit PCU1 shown in Fig. 10. Fig. 11b is an enlarged plan view of one embodiment of the first pixel circuit PC1, second anode electrode AE-2, and second pixel opening PDL-OP2 of the second pixel circuit unit PCU2 shown in Fig. 10.

[0148] 10 and 11a, in one embodiment, the first anode electrode AE-1 and the first pixel opening PDL-OP1 may overlap the first pixel circuit PC1 in a plan view. Specifically, the first anode electrode AE-1 and the first pixel opening PDL-OP1 may be arranged to overlap the first portion PT1 and the second portion PT2 of the first pixel circuit PC1, respectively, but not overlap the third portion PT3.

[0149] 10 and 11b, in one embodiment, the second anode electrode AE-2 and the second pixel opening PDL-OP2 may overlap the first pixel circuit PC1 in a plan view. Specifically, the second anode electrode AE-2 and the second pixel opening PDL-OP2 may be arranged to overlap the second portion PT2 and the third portion PT3 of the first pixel circuit PC1, respectively, but not overlap the first portion PT1.

[0150] The same applies to the configurations other than those shown in FIGS. 10, 11a, and 11b as described above with reference to FIGS. 1 to 9b.

[0151] 11a and 11b, the first anode electrode AE-1 and the second anode electrode AE-2 overlap different portions of the upper gate G1-1 of the first transistor T1. As a result, the overlapping area between the first anode electrode AE-1 and the upper gate G1-1 of the first transistor T1 may differ from the overlapping area between the second anode electrode AE-2 and the upper gate G1-1 of the first transistor T1. As a result, the sizes of the first gap capacitor C1 and the second gap capacitor C2 described in FIG. 5 may differ from each other. That is, a deviation in the size of the gap capacitors between adjacent pixels may occur, resulting in a problem of degraded display quality.

[0152] On the other hand, the shapes of the light-emitting regions PXA-B, PXA-G, and PXA-R of the present invention are not limited to those shown in FIG.

[0153] FIG. 12 is a plan view of a pixel according to one embodiment of the present invention.

[0154] 12, a display panel according to one embodiment may include first to fourth pixel rows PXL1, PXL2, PXL3, and PXL4 arranged in order in a first direction DR1. The first to fourth pixel rows PXL1, PXL2, PXL3, and PXL4 each include first to fourth pixel circuit units PCU1, PCU2, PCU3, and PCU4 arranged in order in a second direction DR2. The first to fourth pixel circuit units PCU1, PCU2, PCU3, and PCU4 may each include first to third pixel circuits PC1, PC2, and PC3.

[0155] First to fourth light-emitting element units electrically connected to the first to fourth pixel circuit units PCU1, PCU2, PCU3, and PCU4, respectively, may be arranged along the second direction DR2 above the first to fourth pixel circuit units PCU1, PCU2, PCU3, and PCU4 arranged in one row. Each of the first to fourth light-emitting element units may include a 1-1 light-emitting element, a 1-2 light-emitting element, a 1-3 light-emitting element, and a 1-4 light-emitting element.

[0156] FIG. 12 shows first to fourth light-emitting regions PXA-Ba, PXA-Bb, PXA-G, and PXA-R representing the first to fourth light-emitting elements PXA-1, PXA-2, PXA-3, and PXA-4. The first and second light-emitting elements PXA-Ba and PXA-Bb, respectively, may be driven by a first pixel circuit PC1. For example, the anode electrodes included in the first and second light-emitting elements PXA-Ba and PXA-Bb may be electrically connected or integrally formed. FIG. 12 illustrates an example in which a first anode electrode AE-1 is provided in common to the first and second light-emitting elements PXA-Ba and PXA-Bb. That is, the first and second light-emitting regions PXA-Ba and PXA-Bb may overlap the first anode electrode AE-1 in a plan view. The third light-emitting element, including the third light-emitting region PXA-G, may be driven by a second pixel circuit PC2. The fourth light-emitting element including the fourth light-emitting region PXA-R may be driven by the third pixel circuit PC3. In one embodiment, the first light-emitting region PXA-Ba and the second light-emitting region PXA-Bb may emit blue light, the third light-emitting region PXA-G may emit green light, and the fourth light-emitting region PXA-R may emit red light. However, embodiments are not limited thereto.

[0157] Referring to the first pixel circuit unit PCU1 arranged in the first pixel row PXL1 and the first to fourth light-emitting regions PXA-Ba, PXA-Bb, PXA-G, and PXA-R arranged on the first pixel circuit unit PCU1, the first anode electrode AE-1 may be arranged to overlap the first to third pixel circuits PC1, PC2, and PC3. The pixel opening PDL-OPa may expose a portion of the first anode electrode AE-1 to define the first light-emitting region PXA-Ba, and the pixel opening PDL-OPb may expose another portion of the first anode electrode AE-1 to define the second light-emitting region PXA-Bb. In one embodiment, the first and second light-emitting regions PXA-Ba and PXA-Bb may be arranged adjacent to one right side of the first pixel circuit unit PCU1.

[0158] With reference to the fourth pixel circuit unit PCU4 arranged in the first pixel row PXL1 and the first to fourth light-emitting regions PXA-Ba, PXA-Bb, PXA-G, and PXA-R arranged above the fourth pixel circuit unit PCU4, the fourth anode electrode AE-4 may be arranged to overlap the first to third pixel circuits PC1, PC2, and PC3. The pixel opening 1a PDL-OPa may expose a portion of the fourth anode electrode AE-4 to define the first light-emitting region PXA-Ba, and the pixel opening 1b PDL-OPb may expose another portion of the fourth anode electrode AE-4 to define the second light-emitting region PXA-Bb. In one embodiment, the first and second light-emitting regions PXA-Ba and PXA-Bb may be arranged adjacent to one left side of the fourth pixel circuit unit PCU4.

[0159] In the first pixel circuit unit PCU1 and the fourth pixel circuit unit PCU4 of the first pixel row PXL1, the positions of the first anode electrode AE-1 and the fourth anode electrode AE-4 do not have to be exactly the same. However, the first anode electrode AE-1 and the fourth anode electrode AE-4 are arranged in the first pixel row PXL1 so that the area where the first anode electrode AE-1 overlaps with the first conductive pattern P1 (see FIG. 8) included in the first pixel circuit PC1 is the same as the area where the fourth anode electrode AE-4 overlaps with the first conductive pattern P1 (see FIG. 8) included in the first pixel circuit PC1.

[0160] Thereby, in the first pixel row PXL1, the deviation of the gap capacitor Cga (see FIG. 2) between the first pixel circuit unit PCU1 and the fourth pixel circuit unit PCU4 can be substantially zero.

[0161] On the other hand, the structure of the second pixel row PXL2 may be different from the structure of the first pixel row PXL1.

[0162] With reference to the second pixel circuit unit PCU2 arranged in the second pixel row PXL2 and the first to fourth light-emitting regions PXA-Ba, PXA-Bb, PXA-G, and PXA-R arranged over the second pixel circuit unit PCU2, the second anode electrode AE-2 may be arranged to overlap the first to third pixel circuits PC1, PC2, and PC3. In one embodiment, the first and second light-emitting regions PXA-Ba and PXA-Bb may be arranged adjacent to one left side of the second pixel circuit unit PCU2.

[0163] With reference to the third pixel circuit unit PCU3 arranged in the second pixel row PXL2 and the first to fourth light-emitting regions PXA-Ba, PXA-Bb, PXA-G, and PXA-R arranged over the third pixel circuit unit PCU3, the third anode electrode AE-3 may be arranged to overlap the first to third pixel circuits PC1, PC2, and PC3. In one embodiment, the first and second light-emitting regions PXA-Ba and PXA-Bb may be arranged adjacent to one right side of the third pixel circuit unit PCU3.

[0164] In the second pixel circuit unit PCU2 and the third pixel circuit unit PCU3 of the second pixel row PXL2, the positions of the second anode electrode AE-2 and the third anode electrode AE-3 may not be exactly the same. However, the second anode electrode AE-2 and the third anode electrode AE-3 are arranged in the second pixel row PXL2 such that the area where the second anode electrode AE-2 overlaps with the first conductive pattern P1 (see FIG. 8) included in the first pixel circuit PC1 is the same as the area where the third anode electrode AE-3 overlaps with the first conductive pattern P1 (see FIG. 8) included in the first pixel circuit PC1.

[0165] Thereby, in the second pixel row PXL2, the deviation of the gap capacitor Cga (see FIG. 2) between the second pixel circuit unit PCU2 and the third pixel circuit unit PCU3 can be substantially zero.

[0166] Meanwhile, the structure of the third pixel row PXL3 may be the same as that of the first pixel row PXL1, and the structure of the fourth pixel row PXL4 may be the same as that of the second pixel row PXL2.

[0167] The display device of the present invention includes two adjacent pixels, each including a light-emitting element and a pixel circuit. The portions of the anode electrodes exposed by the pixel openings in the two pixels may be different. However, the anode electrodes included in the light-emitting elements are disposed at the same positions in the two pixels. Therefore, the size of the gap capacitors formed between the anodes and the gate electrodes included in the pixel circuits is substantially the same in the two pixels. This can improve the display quality of the display device.

[0168] Although the present invention has been described above with reference to preferred embodiments, it will be understood by those skilled in the art or those with ordinary knowledge in the art that various modifications and variations can be made to the present invention without departing from the spirit and technical scope of the present invention as set forth in the claims below.

[0169] Therefore, the technical scope of the present invention should be determined by the claims, not by the contents of the detailed description of the specification. [Industrial Applicability]

[0170] The present invention, which provides a display device with improved display quality, has high industrial applicability.

Claims

1. A base layer; a circuit layer including a first pixel circuit and a second pixel circuit and disposed on the base layer; a light emitting element layer disposed on the circuit layer, including a first light emitting element and a second light emitting element each including a first electrode, a light emitting layer, a second electrode, and a pixel defining layer defining a pixel opening exposing a portion of the first electrode; Each of the first-1st pixel circuit and the first-2nd pixel circuit includes a driving transistor including a source, a drain, an active layer, and a gate, and a gate conductive layer including the gate; A display device in which an area in a plane where the first electrode of the first light-emitting element overlaps with the gate conductive layer of the 1-1 pixel circuit is the same as an area in a plane where the first electrode of the second light-emitting element overlaps with the gate conductive layer of the 1-2 pixel circuit.

2. the first electrode and the gate conductive layer of the first light emitting device define a first electrode and a second electrode of a first capacitor, respectively; The display device of claim 1 , wherein the first electrode and the gate conductive layer of the second light emitting element define a first electrode and a second electrode of a second capacitor, respectively.

3. 3. The display device according to claim 2, wherein the capacitance of the first capacitor is substantially the same as the capacitance of the second capacitor.

4. the pixel opening of the first light-emitting element overlaps an upper side of the gate conductive layer of the 1-1th pixel circuit in a plan view; 2. The display device according to claim 1, wherein the pixel opening of the second light-emitting element overlaps a lower side of the gate conductive layer of the first-second pixel circuit in a plan view.

5. The display device according to claim 1 , wherein the driving transistor includes an oxide semiconductor.

6. the first-1 pixel circuit is disposed above the first-2 pixel circuit in a first direction; the circuit layer further includes a 1-3 pixel circuit adjacent to the 1-1 pixel circuit in a second direction intersecting the first direction, and a 1-4 pixel circuit adjacent to the 1-2 pixel circuit in the second direction; the light-emitting element layer includes a third light-emitting element disposed on the first-third pixel circuit and a fourth light-emitting element disposed on the first-fourth pixel circuit; Each of the third light emitting element and the fourth light emitting element includes a first electrode, a light emitting layer, a second electrode, and a pixel defining layer defining a pixel opening that exposes a portion of the first electrode; each of the first to third pixel circuits and the first to fourth pixel circuits includes a first portion, a second portion, and a third portion that are divided in the first direction; the first electrode of the third light-emitting element overlaps the first to third portions of the first-third pixel circuit in a plan view; the first electrode of the fourth light-emitting element overlaps the first to third portions of the first to fourth pixel circuits in a plan view; the pixel opening of the third light-emitting element overlaps the second portion and the third portion of the first-third pixel circuit in a plan view; 2. The display device according to claim 1, wherein the pixel opening of the fourth light-emitting element overlaps the first portion and the second portion of the first to fourth pixel circuits in a plan view.

7. The display device according to claim 1 , wherein the first light emitting element and the second light emitting element emit a first light.

8. 8. The display device of claim 7, wherein the first light emitting element is electrically connected to the first pixel circuit, and the second light emitting element is electrically connected to the second pixel circuit.

9. the light-emitting element layer further includes a fifth light-emitting element that emits a second light different from the first light and is adjacent to the first light-emitting element; The display device of claim 7 , wherein the first light emitting element is connected to the fifth light emitting element.

10. A base layer; a circuit layer including a first pixel circuit and a second pixel circuit adjacent to the first pixel circuit in a first direction, the circuit layer being disposed on the base layer; a light emitting element layer including a first light emitting element disposed on the 1-1 pixel circuit and a second light emitting element disposed on the 1-2 pixel circuit, and disposed on the circuit layer; Each of the first light emitting element and the second light emitting element includes a first electrode, a light emitting layer, a second electrode, and a pixel defining layer defining a pixel opening that exposes a portion of the first electrode; Each of the first-1 pixel circuit and the second-2 pixel circuit includes a first portion, a second portion, and a third portion that are separated in the first direction, the first electrode of the first light-emitting element overlaps the first to third portions of the 1-1th pixel circuit on a plane; the first electrode of the second light-emitting element overlaps the first to third portions of the first-2 pixel circuit on a plane; the pixel opening of the first light-emitting element overlaps the first portion and the second portion of the 1-1th pixel circuit on a plane; The display device in which the pixel opening of the second light-emitting element overlaps the second portion and the third portion of the first-second pixel circuit on a plane.

11. the pixel opening of the first light-emitting element does not overlap the third portion of the 1-1th pixel circuit on a plane; 11. The display device according to claim 10, wherein the pixel opening of the second light-emitting element does not overlap the first portion of the first-second pixel circuit on a plane.

12. Each of the first-1st pixel circuit and the first-2nd pixel circuit includes a driving transistor including a source, a drain, an active layer, and a gate, and a gate conductive layer including the gate; At least a portion of the gate conductive layer is included in the first to third portions, 11. The display device according to claim 10, wherein the area in a plane where the first electrode of the first light-emitting element overlaps with the gate conductive layer of the 1-1 pixel circuit is the same as the area in a plane where the first electrode of the second light-emitting element overlaps with the gate conductive layer of the 1-2 pixel circuit.

13. The display device according to claim 12 , wherein the driving transistor is an oxide semiconductor.

14. the first-1 pixel circuit is disposed above the first-2 pixel circuit in the first direction; the circuit layer further includes a 1-3 pixel circuit adjacent to the 1-1 pixel circuit in a second direction intersecting the first direction, and a 1-4 pixel circuit adjacent to the 1-2 pixel circuit in the second direction; the light-emitting element layer includes a third light-emitting element disposed on the first-third pixel circuit and a fourth light-emitting element disposed on the first-fourth pixel circuit; Each of the third light emitting element and the fourth light emitting element includes a first electrode, a light emitting layer, a second electrode, and a pixel defining layer defining a pixel opening that exposes a portion of the first electrode; Each of the first to third pixel circuits and the first to fourth pixel circuits includes a first portion, a second portion, and a third portion that are separated in the first direction, the first electrode of the third light-emitting element overlaps the first to third portions of the first-third pixel circuit in a plan view; the first electrode of the fourth light-emitting element overlaps the first to third portions of the first to fourth pixel circuits in a plan view; the pixel opening of the third light-emitting element overlaps the second portion and the third portion of the first-third pixel circuit in a plan view; 11. The display device according to claim 10, wherein the pixel opening of the fourth light-emitting element overlaps the first portion and the second portion of the first to fourth pixel circuits in a plan view.

15. The display device of claim 10 , wherein the first light emitting element and the second light emitting element emit a first light.

16. 16. The display device of claim 15, wherein the first light emitting element is electrically connected to the first pixel circuit, and the second light emitting element is electrically connected to the second pixel circuit.

17. the light-emitting element layer further includes a fifth light-emitting element that emits a second light different from the first light and is adjacent to the first light-emitting element; The display device of claim 15 , wherein the first light emitting element is connected to the fifth light emitting element.

18. A base layer; first to fourth pixel circuit units arranged in one direction; first to fourth light emitting units arranged in the one direction and above the first to fourth pixel circuit units, respectively; Each of the first to fourth light emitting units includes a 1-1 light emitting element, a 1-2 light emitting element, a 1-3 light emitting element, and a 1-4 light emitting element, Each of the 1-1 to 1-4 light emitting elements includes a first electrode, a light emitting layer, a second electrode, and a pixel defining layer defining a pixel opening that exposes a portion of the first electrode; Each of the first to fourth pixel circuit units includes a first pixel circuit electrically connected to the 1-1 light emitting element and the 1-2 light emitting element, a second pixel circuit electrically connected to the 1-2 light emitting element, and a third pixel circuit electrically connected to the 1-3 light emitting element, and each of the first to third pixel circuits includes a driving transistor including a source, a drain, an active layer, and a gate, and a gate conductive layer including the gate; A display device wherein the areas where the first electrodes of the 1-1 light-emitting element and the 1-2 light-emitting element overlap the gate conductive layer of the first pixel circuit in a plane are the same for the first pixel circuit unit and the fourth pixel circuit unit.

19. 19. The display device according to claim 18, wherein the pixel openings of the 1-1st light emitting element and the 1-2nd light emitting element are arranged at different positions in the first pixel circuit unit and the fourth pixel circuit unit.

20. the first-1 light emitting element and the first-2 light emitting element emit first light, the first to third light emitting elements emit second light different from the first light, 19. The display device according to claim 18, wherein the first to fourth light emitting elements emit third light different from the first light and the second light.

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