Encoding method, decoding method, communication device, and computer-readable storage medium

Abstract

Embodiments of the present application disclose an encoding method, a decoding method, a communication device, and a computer-readable storage medium. The application is applicable to wireless local area network systems supporting the IEEE 802.11be Wi-Fi protocol, Wi-Fi 8, and other 802.11 family protocols, and may also be applicable to UWB-based wireless personal local area network systems. The method includes: performing LDPC coding on a bit sequence based on a parity check matrix set to obtain a coded sequence, the parity check matrix set including a first parity check matrix and a second parity check matrix, the first parity check matrix being obtained by extending a base matrix using a first set of cyclic shift values; the second parity check matrix being obtained by extending a base matrix using a second set of cyclic shift values; and transmitting a data packet obtained based on the coded sequence, which can reduce the cyclic shift values ​​stored by the transmitting end.

Description

[Technical Field]

[0001] The present application relates to the field of communication technology, and in particular to an encoding method, a decoding method, a communication device, and a computer-readable storage medium. [Background technology]

[0002] This application claims priority to Chinese Patent Application No. 202211110834.9, entitled "ENCODING METHOD, DECODING METHOD, COMMUNICATION APPARATUS, AND COMPUTER-READABLE STORAGE MEDIUM," filed with the State Intellectual Property Office of China on September 13, 2022, which is incorporated herein by reference in its entirety.

[0003] Wireless local area network (WLAN) transmission standards such as IEEE 802.11n / ac / ax / be are primarily focused on improving user experience in high-bandwidth scenarios, including improving average user throughput and energy utilization efficiency for battery-powered devices. In 60 GHz high-bandwidth scenarios, high-speed and reliable transmission of services such as data and video over limited frequency and power resources must be supported. Therefore, reliable and efficient channel coding / decoding schemes are required. In the field of channel coding, turbo codes and low-density parity-check (LDPC) codes are currently the two most mature and widely used channel coding methods, and both codes have performance close to the Shannon limit. Compared to turbo codes, LDPC codes have the following advantages: good bit error performance achieved without deep interleavers, better frame error rate performance, significantly reduced error floor, supported parallel decoding, and short decoding latency.

[0004] LDPC codes are widely used in WLAN standards to improve the transmission reliability of wireless transmission systems. Compared with the IEEE 802.15.4z standard, the new IEEE 802.15ab standard may introduce new LDPC coding techniques to significantly improve the data transmission reliability of wireless transmission systems. Based on this, new LDPC code encoding and decoding methods may be designed for next-generation WLAN standards or ultra wide band (UWB) to further improve the system performance of next-generation WLAN systems or UWB systems. Summary of the Invention

[0005] SUMMARY OF THE INVENTION Embodiments of the present application disclose an encoding method, a decoding method, a communication device, and a computer-readable storage medium for improving system performance of next-generation WLAN or UWB systems.

[0006] According to a first aspect, an embodiment of the present application provides a coding method, which includes: performing low-density parity check (LDPC) coding on a bit sequence based on a parity check matrix set to obtain a coded sequence, where the parity check matrix set includes a first parity check matrix and a second parity check matrix, a first extension coefficient corresponding to the first parity check matrix is ​​different from a second extension coefficient corresponding to the second parity check matrix, the first parity check matrix is ​​obtained by extending a base matrix using a first set of circular shift values, the second parity check matrix is ​​obtained by extending a base matrix using a second set of circular shift values, and the second set of circular shift values ​​are circular shift values ​​obtained by using the first set of circular shift values; and transmitting a data packet obtained based on the coded sequence.

[0007] In this embodiment of the present application, the first check matrix is ​​a check matrix obtained by extending a base matrix using a first set of circular shift values, and the second check matrix is ​​a check matrix obtained by extending a base matrix using a second set of circular shift values. Since the second set of circular shift values ​​can be obtained by using the first set of circular shift values, the transmitting end only needs to store the first set of circular shift values ​​and does not need to store the second set of circular shift values. In this way, the circular shift values ​​stored by the transmitting end can be reduced.

[0008] According to a second aspect, an embodiment of the present application provides a decoding method, the method including: obtaining an LDPC coded sequence; and decoding the coded sequence based on a parity check matrix set, the parity check matrix set including a first parity check matrix and a second parity check matrix, a first extension coefficient corresponding to the first parity check matrix is ​​different from a second extension coefficient corresponding to the second parity check matrix, the first parity check matrix is ​​a parity check matrix obtained by extending a base matrix using a first set of circular shift values, the second parity check matrix is ​​a parity check matrix obtained by extending a base matrix using a second set of circular shift values, and the second set of circular shift values ​​are circular shift values ​​obtained by using the first set of circular shift values.

[0009] In this embodiment of the present application, the first check matrix is ​​a check matrix obtained by extending a base matrix using a first set of circular shift values, and the second check matrix is ​​a check matrix obtained by extending a base matrix using a second set of circular shift values. Since the second set of circular shift values ​​can be obtained by using the first set of circular shift values, the receiving end only needs to store the first set of circular shift values ​​and does not need to store the second set of circular shift values. In this way, the circular shift values ​​stored by the receiving end can be reduced.

[0010] In a possible implementation of the first or second aspect, each circular shift value of the first set of circular shift values ​​and the second set of circular shift values ​​satisfies the same modulo arithmetic relationship.

[0011] In this implementation, each circular shift value of both the first set of circular shift values ​​and the second set of circular shift values ​​satisfies the same modulo arithmetic relationship, and the second set of circular shift values ​​can be quickly and accurately obtained by using the arithmetic relationship and the first set of circular shift values.

[0012] In a possible implementation of the first or second aspect, the second set of circular shift values ​​are circular shift values ​​obtained by performing a modulo operation on the first set of circular shift values ​​and the second extension factor. In this implementation, the second set of circular shift values ​​used to expand the basis matrix can be quickly obtained.

[0013] In a possible implementation of the first or second aspect, the check matrix set further includes a third check matrix, the first extension coefficient is K times the third extension coefficient corresponding to the third check matrix, K is an odd number greater than 1, the third check matrix is ​​a check matrix obtained by extending the base matrix using a third set of circular shift values, the third set of circular shift values ​​are circular shift values ​​obtained by using the first set of circular shift values, and the third set of circular shift values ​​is different from the second set of circular shift values.

[0014] The extension factor corresponding to the first parity check matrix is ​​K times the extension factor corresponding to the third parity check matrix, which indicates that the code length of the codeword obtained by encoding using the first parity check matrix is ​​K times the code length of the codeword obtained by encoding using the third parity check matrix. If the extension factors corresponding to the two parity check matrices are even multiples, there may be a problem that codewords of appropriate code lengths cannot be obtained by encoding using the parity check matrix, thereby causing resource waste. In this implementation, the transmitting end may select parity check matrices as needed to perform LDPC coding, so as to obtain codewords of different code lengths through encoding, thereby reducing resource overhead. In a possible implementation of the first or second aspect, the second expansion factor is F times the third expansion factor, where F is an even number greater than one.

[0015] In this implementation, the transmitting end may select a check matrix as needed to perform LDPC encoding, so as to obtain codewords of different code lengths through encoding, thereby reducing resource overhead. In a possible implementation of the first or second aspect, the first expansion factor is 102, the second expansion factor is 68 and the third expansion factor is 34.

[0016] In this implementation, the first extension factor is 102, and a long code can be obtained by performing LDPC coding based on the first check matrix, the second extension factor is 68, and a medium code can be obtained by performing LDPC coding based on the second check matrix, and the third extension factor is 34, and a short code can be obtained by performing LDPC coding based on the third check matrix. Therefore, short codes, medium codes, and long codes can be generated accordingly as needed.

[0017] In a possible implementation of the first or second aspect, the coding sequence corresponding to the first check matrix includes codewords having a code length of 2040 bits, the coding sequence corresponding to the second check matrix includes codewords having a code length of 1360 bits, and the coding sequence corresponding to the third check matrix includes codewords having a code length of 680 bits.

[0018] In this implementation, the transmitting end can generate codewords with code lengths of 2040 bits, 1360 bits, or 680 bits by using different check matrices as needed.

[0019] In a possible implementation of the first or second aspect, the method is applied to a wireless local area network system and / or a UWB-based wireless personal local area network system.

[0020] In this implementation, the method provided in this embodiment of the present application is applied to wireless local area network systems and / or UWB-based wireless personal local area network systems to improve the encoding / decoding performance of these systems. In a possible implementation of the first or second aspect, the basis matrix comprises H rows or M columns of the following (12×22) matrix:

[0021] 1 1 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

[0022] H is an integer from 1 to 12, and M is an integer from 1 to 22.

[0023] In this implementation, the design of the basis matrix allows the check matrix according to the basis matrix to have information quickly transmitted and exchanged, decoded and updated between the codeword bits corresponding to the columns of the check matrix, thereby accelerating the overall decoding convergence speed of the system. In a possible implementation of the first or second aspect, the first check matrix includes H rows or M columns of the following (12×22) matrix:

[0024] 19 64 -1 42 -1 -1 61 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 37 32 -1 32 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 11 -1 -1 -1 3 -1 8 13 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 7 24 4 7 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 29 38 53 -1 40 16 -1 30 15 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 7 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 12 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 -1 61 -1 11 -1 -1 -1 -1 -1 24 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 -1 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 24 -1 -1 -1 36 -1 -1 -1 61 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 58 24 -1 50 -1 -1 -1 -1 -1 -1 -1 -1 26 -1 -1 -1 10 -1 -1 -1 -1 0 -1 -1 4 -1 60 61 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0025] A -1 in the first check matrix represents an all-zero matrix of size (K×K), a 0 in the first check matrix represents an identity matrix of size (K×K), an element greater than 0 in the first check matrix represents a CPM of size (K×K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

[0026] In this implementation, a codeword obtained by performing LDPC encoding based on a parity check matrix in the parity check matrix set has better error control performance and packet error rate performance than a codeword of a corresponding code length in the WLAN LDPC. In a possible implementation of the first or second aspect, the first check matrix includes H rows or M columns of the following (12×22) matrix:

[0027] 53 64 -1 42 -1 -1 61 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 24 -1 -1 61 37 66 -1 32 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 45 -1 -1 -1 37 -1 8 13 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 41 24 38 7 54 -1 -1 62 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 63 38 19 -1 40 16 -1 64 15 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 41 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 5 46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 61 -1 45 -1 -1 -1 -1 -1 58 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 58 -1 -1 -1 36 -1 -1 -1 27 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 24 58 -1 50 -1 -1 -1 -1 -1 -1 -1 60 -1 -1 -1 10 -1 -1 -1 -1 0 -1 -1 38 -1 60 61 14 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0028] A -1 in the first check matrix represents an all-zero matrix of size (K×K), a 0 in the first check matrix represents an identity matrix of size (K×K), an element greater than 0 in the first check matrix represents a CPM of size (K×K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

[0029] In this implementation, a codeword obtained by performing LDPC encoding based on a parity check matrix in the parity check matrix set has better error control performance and packet error rate performance than a codeword of a corresponding code length in the WLAN LDPC. In a possible implementation of the first or second aspect, the first check matrix includes H rows or M columns of the following (12×22) matrix:

[0030] 19 64 -1 42 -1 -1 27 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 3 66 -1 66 15 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 0 45 -1 -1 -1 37 -1 42 13 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 7 24 38 41 20 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 29 38 53 -1 40 50 -1 64 49 33 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 41 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 -1 61 -1 45 -1 -1 -1 -1 -1 24 -1 17 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 -1 39 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 24 -1 -1 -1 2 -1 -1 -1 27 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 24 58 -1 16 -1 -1 -1 -1 -1 -1 -1 -1 26 -1 -1 -1 44 -1 -1 -1 -1 0 -1 -1 38 -1 60 61 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0031] A -1 in the first check matrix represents an all-zero matrix of size (K×K), a 0 in the first check matrix represents an identity matrix of size (K×K), an element greater than 0 in the first check matrix represents a CPM of size (K×K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

[0032] In this implementation, a codeword obtained by performing LDPC encoding based on a parity check matrix in the parity check matrix set has better error control performance and packet error rate performance than a codeword of a corresponding code length in the WLAN LDPC. In a possible implementation of the first or second aspect, the first check matrix includes H rows or M columns of the following (12×22) matrix:

[0033] 53 30 -1 42 -1 -1 27 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 3 32 -1 66 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 45 -1 -1 -1 3 -1 8 47 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 21 41 24 38 7 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 63 38 19 -1 6 50 -1 64 15 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 7 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 5 12 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 -1 61 -1 45 -1 -1 -1 -1 -1 24 -1 17 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 -1 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 24 -1 -1 -1 2 -1 -1 -1 61 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 24 24 -1 50 -1 -1 -1 -1 -1 -1 -1 -1 60 -1 -1 -1 10 -1 -1 -1 -1 0 -1 -1 38 -1 60 61 14 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0034] A -1 in the first check matrix represents an all-zero matrix of size (K×K), a 0 in the first check matrix represents an identity matrix of size (K×K), an element greater than 0 in the first check matrix represents a CPM of size (K×K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

[0035] In this implementation, a codeword obtained by performing LDPC encoding based on a parity check matrix in the parity check matrix set has better error control performance and packet error rate performance than a codeword of a corresponding code length in the WLAN LDPC. In a possible implementation of the first or second aspect, the first check matrix includes H rows or M columns of the following (12×22) matrix:

[0036] 19 64 -1 8 -1 -1 61 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 61 37 32 -1 32 15 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 45 -1 -1 -1 3 -1 8 47 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 21 7 58 38 7 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 29 4 53 -1 40 50 -1 30 49 33 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 7 -1 -1 0 -1 -1 -1 18 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 27 -1 11 -1 -1 -1 -1 -1 58 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 50 -1 -1 -1 -1 -1 -1 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 24 -1 -1 -1 36 -1 -1 -1 61 -1 -1 -1 -1 -1 22 -1 -1 -1 -1 0 -1 -1 24 24 -1 16 -1 -1 -1 -1 -1 -1 -1 60 -1 -1 -1 44 -1 -1 -1 -1 0 -1 -1 38 -1 26 27 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0037] A -1 in the first check matrix represents an all-zero matrix of size (K×K), a 0 in the first check matrix represents an identity matrix of size (K×K), an element greater than 0 in the first check matrix represents a CPM of size (K×K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

[0038] In this implementation, a codeword obtained by performing LDPC encoding based on a parity check matrix in the parity check matrix set has better error control performance and packet error rate performance than a codeword of a corresponding code length in the WLAN LDPC. In a possible implementation of the first or second aspect, the first check matrix includes H rows or M columns of the following (12×22) matrix:

[0039] 87 64 -1 42 -1 -1 61 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 37 100 -1 32 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 11 -1 -1 -1 71 -1 8 13 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 7 24 4 75 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 97 38 53 -1 40 84 -1 30 83 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 7 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 80 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 -1 61 -1 79 -1 -1 -1 -1 -1 24 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 -1 73 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 92 -1 -1 -1 36 -1 -1 -1 61 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 58 24 -1 50 -1 -1 -1 -1 -1 -1 -1 -1 26 -1 -1 -1 10 -1 -1 -1 -1 0 -1 -1 4 -1 60 61 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0040] A -1 in the first check matrix represents an all-zero matrix of size (K×K), a 0 in the first check matrix represents an identity matrix of size (K×K), an element greater than 0 in the first check matrix represents a CPM of size (K×K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

[0041] In this implementation, a codeword obtained by performing LDPC encoding based on a parity check matrix in the parity check matrix set has better error control performance and packet error rate performance than a codeword of a corresponding code length in the WLAN LDPC. In a possible implementation of the first or second aspect, the first check matrix includes H rows or M columns of the following (12×22) matrix:

[0042] 19 64 -1 42 -1 -1 61 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 37 100 -1 32 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 11 -1 -1 -1 71 -1 8 13 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 7 24 72 75 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 97 38 53 -1 40 84 -1 30 83 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 75 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 12 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 -1 61 -1 79 -1 -1 -1 -1 -1 24 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 -1 73 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 24 -1 -1 -1 36 -1 -1 -1 61 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 58 92 -1 50 -1 -1 -1 -1 -1 -1 -1 -1 26 -1 -1 -1 78 -1 -1 -1 -1 0 -1 -1 72 -1 60 61 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0043] A -1 in the first check matrix represents an all-zero matrix of size (K×K), a 0 in the first check matrix represents an identity matrix of size (K×K), an element greater than 0 in the first check matrix represents a CPM of size (K×K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

[0044] In this implementation, a codeword obtained by performing LDPC encoding based on a parity check matrix in the parity check matrix set has better error control performance and packet error rate performance than a codeword of a corresponding code length in the WLAN LDPC. In a possible implementation of the first or second aspect, the first check matrix includes H rows or M columns of the following (12×22) matrix:

[0045] 53 64 -1 42 -1 -1 61 -1 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 92 -1 -1 61 37 66 -1 100 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 45 -1 -1 -1 37 -1 76 81 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 41 92 38 75 54 -1 -1 62 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 63 38 87 -1 40 16 -1 64 83 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 41 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 73 46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 -1 61 -1 45 -1 -1 -1 -1 -1 58 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 -1 73 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 58 -1 -1 -1 36 -1 -1 -1 95 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 24 58 -1 50 -1 -1 -1 -1 -1 -1 -1 -1 60 -1 -1 -1 78 -1 -1 -1 -1 0 -1 -1 38 -1 60 61 14 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0046] A -1 in the first check matrix represents an all-zero matrix of size (K×K), a 0 in the first check matrix represents an identity matrix of size (K×K), an element greater than 0 in the first check matrix represents a CPM of size (K×K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

[0047] In this implementation, a codeword obtained by performing LDPC encoding based on a parity check matrix in the parity check matrix set has better error control performance and packet error rate performance than a codeword of a corresponding code length in the WLAN LDPC. In a possible implementation of the first or second aspect, the first check matrix includes H rows or M columns of the following (12×22) matrix:

[0048] 87 64 -1 42 -1 -1 27 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 3 66 -1 66 83 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 0 45 -1 -1 -1 37 -1 42 81 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 75 92 38 41 20 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 97 38 53 -1 40 50 -1 64 49 33 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 41 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 -1 61 -1 45 -1 -1 -1 -1 -1 24 -1 85 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 -1 39 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 92 -1 -1 -1 70 -1 -1 -1 27 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 92 58 -1 16 -1 -1 -1 -1 -1 -1 -1 -1 26 -1 -1 -1 44 -1 -1 -1 -1 0 -1 -1 38 -1 60 61 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0049] A -1 in the first check matrix represents an all-zero matrix of size (K×K), a 0 in the first check matrix represents an identity matrix of size (K×K), an element greater than 0 in the first check matrix represents a CPM of size (K×K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

[0050] In this implementation, a codeword obtained by performing LDPC encoding based on a parity check matrix in the parity check matrix set has better error control performance and packet error rate performance than a codeword of a corresponding code length in the WLAN LDPC. In a possible implementation of the first or second aspect, the first check matrix includes H rows or M columns of the following (12×22) matrix:

[0051] 53 30 -1 42 -1 -1 27 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 71 100 -1 66 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 45 -1 -1 -1 71 -1 76 47 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 21 41 24 38 75 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 63 38 19 -1 6 50 -1 64 83 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 7 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 73 80 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 -1 61 -1 45 -1 -1 -1 -1 -1 24 -1 17 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 -1 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 24 -1 -1 -1 70 -1 -1 -1 61 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 24 24 -1 50 -1 -1 -1 -1 -1 -1 -1 -1 60 -1 -1 -1 78 -1 -1 -1 -1 0 -1 -1 38 -1 60 61 82 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0052] A -1 in the first check matrix represents an all-zero matrix of size (K×K), a 0 in the first check matrix represents an identity matrix of size (K×K), an element greater than 0 in the first check matrix represents a CPM of size (K×K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

[0053] In this implementation, a codeword obtained by performing LDPC encoding based on a parity check matrix in the parity check matrix set has better error control performance and packet error rate performance than a codeword of a corresponding code length in the WLAN LDPC. In a possible implementation of the first or second aspect, the first check matrix includes H rows or M columns of the following (12×22) matrix:

[0054] 87 64 -1 8 -1 -1 61 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 61 37 32 -1 100 83 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 45 -1 -1 -1 71 -1 8 47 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 21 75 58 38 75 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 29 4 53 -1 40 50 -1 30 49 101 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 7 -1 -1 0 -1 -1 -1 18 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 -1 27 -1 79 -1 -1 -1 -1 -1 58 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 50 -1 -1 -1 -1 -1 -1 -1 73 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 92 -1 -1 -1 36 -1 -1 -1 61 -1 -1 -1 -1 -1 22 -1 -1 -1 -1 0 -1 -1 24 24 -1 16 -1 -1 -1 -1 -1 -1 -1 -1 60 -1 -1 -1 44 -1 -1 -1 -1 0 -1 -1 38 -1 26 95 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0055] A -1 in the first check matrix represents an all-zero matrix of size (K×K), a 0 in the first check matrix represents an identity matrix of size (K×K), an element greater than 0 in the first check matrix represents a CPM of size (K×K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

[0056] In this implementation, a codeword obtained by performing LDPC encoding based on a parity check matrix in the parity check matrix set has better error control performance and packet error rate performance than a codeword of a corresponding code length in the WLAN LDPC. In a possible implementation of the first or second aspect, the basis matrix comprises D rows or E columns of the following (12×24) matrix:

[0057] 1 0 0 0 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1

[0058] D is an integer from 1 to 12, and E is an integer from 1 to 24. In a possible implementation of the first or second aspect, the first check matrix includes D rows or E columns of the following (12×24) matrix:

[0059] 0 -1 -1 -1 0 0 -1 -1 0 -1 -1 0 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 49 0 -1 -1 44 -1 0 0 39 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 0 -1 37 -1 -1 -1 51 -1 0 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 0 47 -1 -1 -1 52 0 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 23 -1 -1 -1 30 -1 -1 -1 0 -1 36 11 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 51 -1 23 28 17 -1 30 -1 37 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 52 -1 -1 -1 35 -1 -1 -1 7 45 -1 -1 0 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 13 51 -1 -1 0 -1 8 -1 33 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 7 20 -1 16 22 37 -1 -1 23 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 38 -1 -1 -1 19 -1 -1 -1 13 -1 3 17 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 25 -1 35 -1 23 45 -1 41 9 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 3 -1 -1 -1 16 -1 -1 2 25 32 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0060] A -1 in the first check matrix represents an all-zero matrix of size (L×L), a 0 in the first check matrix represents an identity matrix of size (L×L), an element greater than 0 in the first check matrix represents a CPM of size (L×L), D is an integer from 1 to 12, and E is an integer from 1 to 24.

[0061] In this implementation, a codeword obtained by performing LDPC encoding based on a parity check matrix in the parity check matrix set has better error control performance and packet error rate performance than a codeword of a corresponding code length in the WLAN LDPC. In a possible implementation of the first or second aspect, the first check matrix includes D rows or E columns of the following (12×24) matrix:

[0062] 0 -1 -1 -1 0 0 -1 -1 0 -1 -1 0 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 49 0 -1 -1 44 -1 0 0 39 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 60 -1 0 -1 37 -1 -1 -1 51 -1 0 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 56 -1 -1 0 47 -1 -1 -1 52 0 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 77 -1 -1 -1 30 -1 -1 -1 0 -1 36 11 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 51 -1 77 28 17 -1 30 -1 37 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 52 -1 -1 -1 35 -1 -1 -1 7 45 -1 -1 0 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 67 51 -1 -1 0 -1 8 -1 33 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 61 74 -1 70 22 37 -1 -1 23 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 38 -1 -1 -1 73 -1 -1 -1 67 -1 57 71 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 25 -1 35 -1 77 45 -1 41 9 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 57 -1 -1 -1 16 -1 -1 56 25 32 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0063] A -1 in the first check matrix represents an all-zero matrix of size (L×L), a 0 in the first check matrix represents an identity matrix of size (L×L), an element greater than 0 in the first check matrix represents a CPM of size (L×L), D is an integer from 1 to 12, and E is an integer from 1 to 24.

[0064] In this implementation, a codeword obtained by performing LDPC encoding based on a parity check matrix in the parity check matrix set has better error control performance and packet error rate performance than a codeword of a corresponding code length in the WLAN LDPC. In a possible implementation of the first or second aspect, the first expansion factor is 81, the second expansion factor is 54 and the third expansion factor is 27.

[0065] In a possible implementation of the first or second aspect, the coding sequence corresponding to the first check matrix includes codewords having a code length of 1944 bits, the coding sequence corresponding to the second check matrix includes codewords having a code length of 1296 bits, and the coding sequence corresponding to the third check matrix includes codewords having a code length of 648 bits.

[0066] According to a third aspect, an embodiment of the present application provides another encoding method. The method includes: performing LDPC coding on a bit sequence based on a check matrix to obtain a coded sequence; and transmitting a data packet obtained based on the coded sequence. The check matrix may be the first check matrix, the second check matrix, or the third check matrix in the first or second aspect. Alternatively, the check matrix may be a check matrix obtained by performing a modulo operation on the first check matrix in the first or second aspect. Specifically, the check matrix is ​​any one of Matrices 1 to 5 below. Specifically, the check matrix is ​​any one of Matrices 21 to 26 below.

[0067] In this embodiment of the present application, the codeword obtained by performing LDPC coding based on the check matrix has better error control performance and packet error rate performance than the codeword of the corresponding code length in WLAN LDPC.

[0068] According to a fourth aspect, an embodiment of the present application provides another decoding method. The method includes the steps of obtaining an LDPC-coded sequence and performing decoding on the LDPC-coded sequence based on a check matrix. The check matrix may be the first check matrix, the second check matrix, or the third check matrix in the first or second aspect. Alternatively, the check matrix is ​​a check matrix obtained by performing a modulo operation on the first check matrix in the first or second aspect. Specifically, the check matrix is ​​any one of Matrices 1 to 5 below. Specifically, the check matrix is ​​any one of Matrices 21 to 26 below.

[0069] In this embodiment of the present application, compared with decoding based on the existing WLAN LDPC check matrix, decoding based on the check matrix provided in this embodiment of the present application has better error control performance and better packet error rate performance.

[0070] According to a fifth aspect, an embodiment of the present application provides a communication device. The communication device has a function for implementing the behavior in the method embodiment in the first aspect. The communication device may be a communication device, or may be a component of the communication device (e.g., a processor, a chip, or a chip system), or may be a logic module or software capable of implementing all or part of the functionality of the communication device. The functionality of the communication device may be implemented by hardware, or may be implemented by hardware executing corresponding software. The hardware or software includes one or more modules or units corresponding to the above functions. In a possible implementation, the communication device includes an interface module and a processing module. The processing module is configured to perform low-density parity check (LDPC) coding on the bit sequence based on the check matrix set to obtain a coded sequence, the check matrix set including a first check matrix and a second check matrix, a first extension coefficient corresponding to the first check matrix being different from a second extension coefficient corresponding to the second check matrix, the first check matrix being a check matrix obtained by extending a base matrix using a first set of circular shift values, the second check matrix being a check matrix obtained by extending a base matrix using a second set of circular shift values, and the second set of circular shift values ​​being circular shift values ​​obtained by using the first set of circular shift values. The transceiver module is configured to transmit a data packet obtained based on the coded sequence. For possible implementations of the communication device in the fifth aspect, please refer to the possible implementations of the first aspect. For technical effects achieved by possible implementations of the fifth aspect, please refer to the description of the technical effects of the first aspect or possible implementations of the first aspect.

[0071] According to a sixth aspect, an embodiment of the present application provides a communication device. The communication device has a function of implementing the behavior of the method embodiment in the second aspect. The communication device may be a communication device, or may be a component of the communication device (e.g., a processor, a chip, or a chip system), or may be a logic module or software capable of implementing all or part of the functionality of the communication device. The functionality of the communication device may be implemented by hardware or by hardware executing corresponding software. The hardware or software may include one or more modules or units corresponding to the above functions. In a possible implementation, the communication device includes a transceiver module and a processing module. The transceiver module is configured to receive a signal carrying a data packet obtained based on an LDPC coding sequence. The processing module is configured to obtain an LDPC coding sequence based on a received signal carrying a data packet obtained based on the LDPC coding sequence, and decode the coding sequence based on a check matrix set, where the check matrix set includes a first check matrix and a second check matrix, a first extension coefficient corresponding to the first check matrix is ​​different from a second extension coefficient corresponding to the second check matrix, the first check matrix is ​​a check matrix obtained by extending a base matrix using a first set of circular shift values, the second check matrix is ​​a check matrix obtained by extending a base matrix using a second set of circular shift values, and the second set of circular shift values ​​are circular shift values ​​obtained by using the first set of circular shift values. For possible implementations of the communication device in the sixth aspect, please refer to the possible implementations of the second aspect. For technical effects achieved by possible implementations of the sixth aspect, please refer to the description of the technical effects of the second aspect or possible implementations of the second aspect.

[0072] According to a seventh aspect, an embodiment of the present application provides a communication device. The communication device has a function of implementing the behavior of the method embodiment of the third aspect. The communication device may be a communication device, or may be a component of the communication device (e.g., a processor, a chip, or a chip system), or may be a logic module or software capable of implementing all or part of the functions of the communication device. The functions of the communication device may be implemented by hardware or by hardware executing corresponding software. The hardware or software may include one or more modules or units corresponding to the above functions. In a possible implementation, the communication device includes a transceiver module and a processing module. The processing module is configured to perform LDPC coding on a bit sequence based on a check matrix to obtain a coded sequence. The transceiver module is configured to transmit a data packet obtained based on the coded sequence. The check matrix may be the first check matrix, the second check matrix, or the third check matrix in the first or second aspect. Alternatively, the check matrix is ​​a check matrix obtained by performing modulo processing on the first check matrix in the first aspect or the second aspect. In particular, the check matrix is ​​any one of the following matrices 1 to 5. In particular, the check matrix is ​​any one of the following matrices 21 to 26. For technical effects achieved by possible implementations of the seventh aspect, please refer to the description of the technical effects of the third aspect or possible implementations of the third aspect.

[0073] According to an eighth aspect, an embodiment of the present application provides a communication device. The communication device has a function of implementing the behavior of the method embodiment of the fourth aspect. The communication device may be a communication device, or may be a component of the communication device (e.g., a processor, a chip, or a chip system), or may be a logic module or software capable of implementing all or part of the functionality of the communication device. The functionality of the communication device may be implemented by hardware, or by hardware executing corresponding software. The hardware or software may include one or more modules or units corresponding to the above functionality. In a possible implementation, the communication device includes a transceiver module and a processing module. The transceiver module is configured to receive a signal carrying a data packet obtained based on an LDPC coding sequence. The processing module is configured to obtain an LDPC coding sequence based on the received signal carrying the data packet obtained based on the LDPC coding sequence, and to perform decoding on the LDPC coding sequence based on a check matrix. The check matrix may be the first check matrix, the second check matrix, or the third check matrix in the first or second aspect. Alternatively, the check matrix is ​​a check matrix obtained by performing modulo processing on the first check matrix in the first aspect or the second aspect. In particular, the check matrix is ​​any one of the following matrices 1 to 5. In particular, the check matrix is ​​any one of the following matrices 21 to 26. For technical effects achieved by possible implementations of the eighth aspect, please refer to the description of the technical effects of the fourth aspect or possible implementations of the fourth aspect.

[0074] According to a ninth aspect, an embodiment of the present application provides another communication device. The communication device includes a processor. The processor is coupled to a memory. The memory is configured to store a program or instructions. When the program or instructions are executed by the processor, the communication device is capable of performing a method according to any one of the first to fourth aspects.

[0075] In this embodiment of the present application, the bit sequence to be encoded can be a first bit sequence, a second bit sequence, or a third bit sequence, and the basis matrix can be a first basis matrix or a second basis matrix.

[0076] In this embodiment of the present application, in the process of performing the method, the process of transmitting information (or a signal) in the method may be understood as the process of outputting information according to the instruction of a processor. When information is output, the processor outputs the information to the transceiver so that the transceiver transmits the information. After the information is output by the processor, the information may further require other processing and then reach the transceiver. Similarly, when the processor receives input information, the transceiver receives the information and inputs the information to the processor. Furthermore, after the transceiver receives information, other processing may need to be performed on the information before the information is input to the processor.

[0077] Operations such as sending and / or receiving involving a processor may generally be understood as instructions output by the processor unless otherwise stated or if the operations do not contradict the actual function or internal logic of the operations in the relevant description.

[0078] In the implementation process, the processor may be a processor specially configured to perform these methods, or may be a processor, such as a general-purpose processor, that executes computer instructions in a memory to perform these methods. For example, the processor may be further configured to execute a program stored in the memory. When the program is executed, the communication device is enabled to perform a method according to the first aspect or any one of the possible implementations of the first aspect. In a possible implementation, the memory is located external to the communication device. In a possible implementation, the memory is located within the communication device.

[0079] In a possible implementation, the processor and memory may alternatively be integrated into one device, ie, the processor and memory may alternatively be integrated with each other. In a possible implementation, the communication device further includes a transceiver, the transceiver being configured to receive signals, send signals, etc.

[0080] According to a tenth aspect, the present application provides another communication device. The communication device includes a processing circuit and an interface circuit. The interface circuit is configured to acquire data or output data. The processing circuit is configured to perform the method described in any one of the first to fourth aspects.

[0081] According to an eleventh aspect, the present application provides a computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed, enable a computer to perform a method as set forth in any one of the first to fourth aspects.

[0082] According to a twelfth aspect, the present application provides a computer program product, the computer program product comprising a computer program, the computer program comprising program instructions that, when executed, enable a computer to perform a method as set forth in any one of the first to fourth aspects.

[0083] According to a thirteenth aspect, the present application provides a communication system including a communication device according to the fifth aspect or any one of the possible implementations of the fifth aspect, and a communication device according to the sixth aspect or any one of the possible implementations of the sixth aspect. According to a fourteenth aspect, the present application provides a communication system including a communication device according to the seventh aspect and a communication device according to the eighth aspect.

[0084] According to a fifteenth aspect, the present application provides a chip including a processor and a communication interface, wherein the processor reads instructions stored in a memory through the communication interface to execute a method according to any one of the first to fourth aspects. [Brief explanation of the drawings]

[0085] In order to more clearly describe the technical solutions in the embodiments or background art of the present application, the following briefly describes the accompanying drawings for describing the embodiments or background art of the present application. [Figure 1] FIG. 2 is a diagram illustrating an example of a check matrix H of an LDPC code. [Figure 2] 1 is a Tanner graph of a check matrix H of an LDPC code. [Figure 3] FIG. 10 is a diagram illustrating an example of an LDPC code encoding process. [Figure 4] FIG. 1 is a diagram illustrating a shortened calculation portion in LDPC encoding processing. [Figure 5] FIG. 10 is a diagram showing an example of a mother matrix obtained by extending HMC. [Figure 6] FIG. 1 illustrates an example of four (4×4) CPMs according to the present application. [Figure 7] FIG. 2 is a diagram illustrating an example of a check matrix obtained by expanding a base matrix 1 of size (12×22) according to an embodiment of the present application. [Figure 8] 1 is a diagram illustrating an example of a wireless communication system to which the technical solution according to the present application can be applied; [Figure 9] 1 is an interactive flowchart of an LDPC code encoding and decoding method according to an embodiment of the present application; [Figure 10A] 1 is an interactive flowchart of another LDPC code encoding and decoding method according to an embodiment of the present application. [Figure 10B] 1 is an interactive flowchart of another LDPC code encoding and decoding method according to an embodiment of the present application. [Figure 11] FIG. 1 illustrates an example of a basis matrix according to the present application. [Figure 12] FIG. 10 is a diagram illustrating an example of a check matrix. [Figure 13] FIG. 1 is a diagram of tree expansion according to an embodiment of the present application. [Figure 14A] FIG. 1 is a diagram of a PER simulation performance comparison for LDPC codes according to an embodiment of the present application. [Figure 14B] FIG. 1 is a diagram of a PER simulation performance comparison for LDPC codes according to an embodiment of the present application. [Figure 15] 15 is a diagram of the structure of a communication device 1500 according to an embodiment of the present application. [Figure 16] FIG. 1 is a diagram of the structure of another communication device 160 according to an embodiment of the present application. [Figure 17] FIG. 1 is a diagram of the structure of another communication device 170 according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0086] Terms such as "first," "second," and the like in the specification, claims, and accompanying drawings of this application are used merely to distinguish between different objects and are not used to describe a particular order. In addition, terms such as "comprise" and "have," as well as any other variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but instead optionally includes further steps or units that are not listed, or optionally includes further steps or units that are inherent to the process, method, product, or device.

[0087] In this application, terms such as "example," "for example," and the like are used to denote providing an example, illustration, or explanation. Any embodiment or design manner described in this application using "example," "in one example," or "for example" should not be described as preferred or having more advantages over another embodiment or design manner. Rather, use of terms such as "example," "in one example," "for example," and the like is intended to present the relevant concept in a particular way.

[0088] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the present application. Phrases appearing in various places in this specification may not necessarily refer to the same embodiment, and are not an optional embodiment independent of or exclusive of another embodiment. Those skilled in the art may explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.

[0089] The terms used in the following embodiments of the present application are intended to describe particular embodiments only and are not intended to limit the present application. As used in this specification and the appended claims of the present application, the singular forms "one," "a," "an," "the," and "this" are also intended to include the plural forms unless the context clearly dictates otherwise. The term "and / or," as used in the present application, means and should also be understood to include any or all possible combinations of one or more listed items. For example, "A and / or B" can represent three cases: when only A is present, when only B is present, and when both A and B are present, and A and B can be singular or plural. As used in the present application, the term "plurality" means two or more.

[0090] In the embodiments of the present application, it can be understood that "B corresponding to A" indicates that there is a correspondence between A and B, and that B can be determined based on A. However, it should also be understood that determining (or generating) B based on (or on the basis of) A does not mean that B is determined (or generated) based on (or on) A only, and that B can alternatively be determined (or generated) based on (or on) A and / or other information. To facilitate understanding of the solution in this application, the relevant concept of LDPC codes in this application will be explained first.

[0091] LDPC code is an abbreviation for low-density parity-check code. Literally, LDPC code is a parity-check code with low density. In this specification, low density means that the check matrix of the LDPC code is low-density. Therefore, to understand what an LDPC code is, it is first necessary to understand three concepts: parity-check code, check matrix, and low density. 1. Parity Check Codes

[0092] A parity check code is a coding method that adds redundant bits to ensure that the number of 1s in a codeword is always odd or even. Parity check codes are error-detecting codes. Parity check codes are typically used for digital coding of binary fields of 0s and 1s. One or more bits (check bits) are added to the end of the codeword. By determining whether the number of 1s in the codeword is odd or even, it is determined whether an error occurred in the codeword before or after transmission. For example, if the codeword 100 uses a parity check, the check bit may be 1. In this case, the value s of the sum (exclusive or) of the entire codeword is 0, i.e., 1001. If the codeword changes to 1101 after transmission, one information bit (sometimes called a bit) is incorrect. In this case, s = 1, and it can be determined that a transmission error occurred. It should be understood that if an even number of information bits are incorrect, the algorithm failed. Therefore, more than one check bit may be set. For example, a 4-bit codeword 1101 may be grouped, and the first bit of the check bits may be used to check the first and second bits of the information bits (i.e., the first two bits of the information bits, 11). For example, if the sum of the first two bits of the information bits is 0, then the first bit of the check bits should be set to 0. Similarly, the second bit of the check bits may be used to check the last two information bits of the codeword 1101, and then the second bit of the check bits is set to 1. Thus, the encoded codeword is 110101. This is actually the idea behind the check of LDPC codes, i.e., the meaning of "PC." It can be seen that LDPC codes are block codes and actually use parity check. If a low-density feature is added, an LDPC code can be obtained. 2.Low density of LDPC code

[0093] The low density of an LDPC code means that the number of 1s in the check matrix of the LDPC code is extremely small. LDPC codes are linear block codes, and the check matrix of an LDPC code is a sparse matrix. The number of zero elements in the check matrix of an LDPC code is much greater than the number of non-zero elements. In other words, the row weight (i.e., the number of 1s in each row) and column weight (i.e., the number of 1s in each column) of the check matrix are much smaller than the code length of the LDPC code. 3. Check matrix and generator matrix of LDPC code

[0094] Codeword 1101 is used as an example. The check relationship between the information bits and check bits of the codeword can be expressed in the form of a matrix. The information bits are denoted as c1, c2, c3, and c4, and the check bits are denoted as p1 and p2. c = [c1, c2, c3, c4], x = [c1, c2, c3, c4, p1, p2]. c and x are the codeword before and after encoding, respectively. In the example of codeword 1101, the check relationship between the information bits and check bits of codeword 1101 can be expressed as the following linear relationship: c1 + c2 + p1 = 0, and c3 + c4 + p2 = 0. The linear relationship can be expressed as the following equation: x·H T =s=0 (1) where H is

[0095]

number

[0096] and s=(0,0). H is the check matrix, s is the syndrome, and H T represents the transpose of H. The idea of ​​equation (1) is that after the original codeword (uncoded codeword) c is encoded by using a generator matrix G (G is determined by H), the obtained transmitted codeword x is x H T= 0. To easily determine whether the result is 0, the concept of syndrome s is introduced. As long as s is all 0, there is no problem with transmission. In this application, "·" represents a matrix multiplication operation, and "A·B" represents the product of the matrix multiplication of matrix A and matrix B. The transmit codeword x obtained by encoding c using the generator matrix G may satisfy the following equation: x=c·G (2)

[0097] where c represents the unencoded codeword (or bit sequence) and G represents the generator matrix. T are orthogonal to each other, i.e., G H T =0. The generator matrix can be obtained by transforming the check matrix. That is, when the check matrix is ​​known, the generator matrix corresponding to the check matrix can be obtained. c may be called an information codeword, and x may be called a transmission codeword. Equation (2) shows that the transmission codeword is obtained by multiplying the information codeword by the generator matrix. 4. Tanner Graph

[0098] In 1981, Tanner represented the codewords of an LDPC code in the form of a graph. Nowadays, such graphs are called Tanner graphs and have a one-to-one correspondence with check matrices. A Tanner graph contains two types of vertices. One type of vertex is a variable node, which represents a codeword bit. The other type of vertex is a check node, which represents a check constraint relation. Each check node represents a check constraint relation, which will be described later with reference to Figures 1 and 2.

[0099] Please refer to Fig. 1. Fig. 1 shows an example of a check matrix H of an LDPC code according to the present application. In Fig. 1, {V i} denotes a variable node set, and {C i} denotes a check node set. Each row of the check matrix H corresponds to one check formula, and each column of the check matrix H corresponds to one codeword bit. In FIG. 1, there are eight variable nodes and four check nodes. If a codeword bit is included in the corresponding check formula, a connection line is used to connect the associated variable node and the associated check node to obtain a Tanner graph.

[0100] Please refer to Figure 2. Figure 2 is a Tanner graph of a parity check matrix H of an LDPC code according to an embodiment of the present application. As shown in Figure 2, the Tanner graph represents the parity check matrix of the LDPC code. For example, for a parity check matrix H having a size of m rows and n columns, the Tanner graph includes two types of nodes: n variable nodes (also called information nodes or bit nodes) and m check nodes, where both m and n are integers greater than 0. The n variable nodes correspond to the n columns of the parity check matrix H, and the m check nodes correspond to the m rows of the parity check matrix H. A closed path in a Tanner graph consists of connected vertices. A closed path uses one of the vertices as both the start and end point and passes through each node exactly once. The length of a closed path is defined as the number of connecting lines included in the closed path. The girth of a graph, sometimes called the size of the graph, is defined as the length of the shortest closed path in the graph. In Figure 2, the girth is 6, as indicated by the thick connecting lines in Figure 2. 5.LDPC code encoding

[0101] From the above description, it can be seen that the transmission codeword is obtained by multiplying the information codeword by a generator matrix, and the generator matrix can be obtained by transforming the check matrix. Therefore, the whole LDPC code encoding process is actually a process of constructing a check matrix. Please refer to Figure 3. Figure 3 shows an example of the LDPC code encoding process according to the present application. As shown in Figure 3, the check matrix H can be changed to H=[IP] only through Gaussian elimination, and the generator matrix G=[-P T I] is G·H T= 0, and the information codeword c is encoded by using a generator matrix G to obtain the transmitted codeword x, i.e., x = c G. I represents the information bit portion, P represents the check bit portion, and x is the transmitted codeword. 6.LDPC code decoding

[0102] In the LDPC code decoding process, x H T Message iteration is continuously performed between the variable node and the check node according to the check rule between the check bits (or called parity elements) and the information bits (or called information elements) until a codeword satisfying = is found, and the output x is the decoded codeword. LDPC code decoding algorithms include the following three categories: hard-decision decoding, soft-decision decoding, and hybrid decoding. 7. LDPC Coding in WLAN Scenarios

[0103] Some WLAN standards (e.g., IEEE 802.11n / ac) use orthogonal frequency division multiplexing (OFDM) technology. The LDPC encoding module needs to encode data bits (sometimes called information bits) and arrange the encoded data bits into an integer number of OFDM symbols, and these encoded bits also need to be able to be accurately arranged into an integer number of LDPC codewords. To perform the above steps, the transmitting end first determines the minimum number N of OFDM symbols required for the current transmission. SYM Calculate and then N SYM and the total number of coded bits N that can be placed in all OFDM symbols according to the current modulation and coding scheme. TCB Calculate N TCB =N CBPS *N SYM and N CBPSis the number of bits that can be stored in each OFDM symbol. Then, the transmitting end calculates the code length of the LDPC code used in the current transmission and the number of codewords required based on the obtained result. For most combinations of the bit length of the data to be encoded and the modulation and coding scheme, there are insufficient data bits to fill the data bit portion in the LDPC codeword, so a shortening operation needs to be performed before the check bits are generated. The data bit portion in the LDPC codeword only includes information bits (or data bits) and does not include check bits (or check bits).

[0104] In the present application, shortened operation means that before check bits are generated through LDPC encoding, a certain amount of 0 is filled into the data bit part of the code word information, and these 0 are deleted after check bits are generated through encoding. Figure 4 is a diagram of the shortened operation part in the LDPC encoding process according to an embodiment of the present application. As shown in FIG. 4, 401 represents data bits (payload bits) to be encoded, step 1 is to calculate the length of the LDPC codeword and the amount of codewords needed to send the data bits to be encoded, 402 represents the length of the LDPC codeword and the amount of codewords, step 2 is to perform a shortening operation on the data bits to be encoded, 403 represents a codeword including data bits and shortening zero bits, step 3 is to generate check bits (parity bits) by using the data bits and shortening zero bits, 404 represents a codeword including data bits, shortening zero bits, and check bits, and these shortening zero bits are then deleted (discarding the shortening bits), and 405 represents a codeword including only data bits and check bits. 8. Obtain the mother matrix by expanding the check matrix

[0105] The mother matrix is ​​a larger matrix, and check matrices of different sizes can be read from the mother matrix. The check matrices of different sizes read from the mother matrix correspond to different code rates. The mother matrix can be obtained by expanding the check matrix (sometimes called a base matrix). For example, when the base matrix is ​​read from the mother matrix, the base matrix is ​​a check matrix. In this case, the code rate corresponding to the check matrix is ​​the largest. When the entire mother matrix is ​​read, the mother matrix is ​​a check matrix. In this case, the code rate corresponding to the check matrix is ​​the smallest. Below, a method for obtaining the mother matrix by expanding the check matrix will be described with reference to an example.

[0106] H MC represents a basis matrix of size (4 × 24) (e.g., a WLAN LDPC check matrix with code length 1944 and code rate 5 / 6), and 0 4×100 represents an all-zero matrix of size (4 × 100), and I 100×100 If represents an identity matrix of size (100×100), then matrix H of size (100×24) IR is H MC , 0 4×100 , and I 100×100 is defined to form the expanded mother matrix H using

[0107]

number

[0108] From the equation, 0 4×100 and I 100×100 are fixed matrices, the key to the rate compatibility of the mother matrix (i.e., check matrices with different code rates can be read from the mother matrix) is MC and H IR It can be seen that the incremental redundant bits corresponding to the lower code rates are H MC If it is expected through extending H MC needs to be extended by the required number of columns based on the required code rate. For example, if the code rate is H MC, or 324 new incremental redundant bits corresponding to the four columns are added to H MC If it needs to be added to MC should be extended downward and left based on H, i.e., 4 rows downward and 4 rows to the right.

[0109] See Figure 5. Figure 5 shows the H MC As shown in Figure 5, the rectangular box in the upper left corner of the mother matrix is ​​the matrix H MC and H MC is extended four columns to the right, and H MC is expanded downward by four rows to obtain the mother matrix shown in Figure 5. Each blank cell in Figure 5 represents an all-zero matrix of size (81 × 81), and the upper left corner of the mother matrix is ​​a matrix H MC The upper right corner of the mother matrix is ​​the first fixed matrix, and the first fixed matrix is ​​0 4×100 The bottom left corner of the generating matrix is ​​the matrix H IR The bottom right corner of the mother matrix is ​​the second fixed matrix, and the fixed matrix is ​​a large I 100×100 is.

[0110] H MC The size of the matrix obtained by extending H is (8x28), as shown by the entire matrix in Figure 5. Each element of the mother matrix (excluding blank cells) is a cyclic permutation matrix of size (81x81). It should be understood that the size of the entire mother matrix is ​​(8x28), and the final size of the mother matrix obtained by extending each entry is (648x2268). If the remaining amount of remaining code rates or incremental redundancy bits needs to be obtained, the required portion can be selected from the upper left part of H as a check matrix according to the method described above. The original H MC If it is necessary to generate (81 j) incremental redundancy check bits in addition to the codeword bits corresponding to H, then the check matrix selected is the upper left part of H, size (4 + j) × (24 + j), where j is a positive integer.

[0111] The above is the check matrix H MC The process of extending a base matrix into a mother matrix has been described using the above as an example. Obtaining a mother matrix by extending another check matrix is ​​based on a similar design idea. 9. Obtaining a check matrix by expanding the base matrix

[0112] The base matrix of an LDPC code can be extended to check matrices of LDPC codes of various code lengths as needed. The base matrix of an LDPC code contains only two types of elements: 0 and 1. In the present application, 0 in the base matrix can be replaced by a blank, "-", "-1", or another number or symbol. This is not limited in the present application. In the present application, when a check matrix is ​​obtained by extending a base matrix, 1 in the base matrix can be extended to a non-all-zero square matrix (sometimes referred to as a non-all-zero square matrix), and 0 elements in the base matrix can be extended to an all-zero square matrix (sometimes referred to as an all-zero square matrix). In the present application, an all-zero square matrix is ​​a square matrix in which all elements are 0, for example, a square matrix of size (27 × 27). In the present application, a non-all-zero square matrix is ​​a square matrix containing at least one non-zero element, for example, a circulant permutation matrix (CPM). CPM is a circular shift of an identity matrix. In other words, the circular shift of an identity matrix is ​​called CPM. All subsequent CPMs have the same meaning and will not be explained again later. In this application, any CPM may be represented by one value and one expansion factor. In other words, any CPM corresponds to one value and one expansion factor. Different sizes of two CPMs mean that the two CPMs correspond to different expansion factors. In this application, a value corresponding to a CPM may be referred to as a specific expansion factor value, expansion factor value, specific expansion factor, circular shift factor, circular shift factor, etc. The expansion factor corresponding to a CPM represents the size of the CPM; that is, CPMs of different sizes have different expansion factors. For example, the expansion factor of a CPM of size (27 x 27) is 27. In other words, if the expansion factor of a CPM is 27, it indicates that the size of the CPM is (27 x 27). In another example, the expansion factor of a CPM of size (54 x 54) is 54. The meaning of all subsequent CPM extension coefficients is the same and will not be explained again later. Note that the CPM extension coefficients in the parity check matrix are the same. Each CPM extension coefficient in the parity check matrix can be considered as the extension coefficient corresponding to the parity check matrix.For example, the size of the basis matrix is ​​(12×22), and the basis matrix is ​​extended by using an extension coefficient Z=27 to obtain a parity check matrix. The extension coefficient of each CPM in the parity check matrix is ​​Z, and the extension coefficient corresponding to the parity check matrix is ​​Z.

[0113] In the present application, the value (integer) corresponding to a CPM represents the number of bits to be circularly shifted to the right in an identity matrix. FIG. 6 shows an example of four (4×4) CPMs according to the present application. As shown in FIG. 6, P0 represents a (4×4) identity matrix, and P0 may be considered as a CPM whose expansion factor is 4 and whose corresponding value is 0; P1 is a CPM whose expansion factor is 4 and whose corresponding value is 1; P2 is a CPM whose expansion factor is 4 and whose corresponding value is 2; and P3 is a CPM whose expansion factor is 4 and whose corresponding value is 3. FIG. 6 shows an example of four CPMs according to an embodiment of the present application. It should be understood that any CPM can be obtained by circularly shifting the corresponding identity matrix to the right. Details will not be described again here. It can be understood that a 1 in a base matrix can be expanded to a CPM of any size, and a 0 in a base matrix can be expanded to an all-zero square matrix of any size. The meaning or function of 1 or 0 in the subsequent basis matrices is consistent with the meaning or function in the preceding explanation and will not be explained again.

[0114] The method for obtaining a check matrix by expanding a base matrix may be as follows: 1 in the base matrix is ​​replaced by CPM, and 0 in the base matrix is ​​replaced by an all-zero square matrix of corresponding size. For example, each element in the base matrix is ​​0 or 1. To obtain a check matrix by expanding a base matrix, each 0 in the base matrix is ​​expanded into a (Z×Z) all-zero matrix, and each 1 in the base matrix is ​​expanded into a (Z×Z) CPM, where Z is the expansion coefficient corresponding to CPM, and the values ​​corresponding to different CPMs are the same or different. Therefore, a series of check matrices for an LDPC code can be obtained based on the base matrix. Although the sizes of these check matrices and the expansion coefficients of CPM may be different, the check matrix and CPM correspond to or follow the same base matrix. The following is an example of a check matrix obtained by expanding a base matrix: An example of a base matrix of size (12×22) is as follows:

[0115] 1 1 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

[0116] Please refer to Figure 7. Figure 7 shows an example of a check matrix (hereinafter referred to as check matrix 1) obtained by extending a base matrix 1 of size (12x22) according to an embodiment of the present application. As shown in Figure 7, "-1" in the check matrix represents an all-zero matrix of size (KxK), 0 in the check matrix represents an identity matrix (also called an identity matrix) of size (KxK), and elements greater than 0 in the check matrix represent corresponding values ​​that are CPMs and elements of size (KxK), where K represents an extension coefficient corresponding to the check matrix. In the present application, -1 (representing an all-zero matrix) in the check matrix can be replaced by a blank, "-", or another number or symbol. This is not limited in the present application. The meaning or function of "-" or 0 in the subsequent check matrix is ​​the same as the meaning or function in the preceding description and will not be described again. Obtaining a check matrix by extending a base matrix may be extending the base matrix by using a set of extension coefficients to obtain a check matrix. For example, parity check matrix 1 is obtained by extending base matrix 1 using a set of extension coefficients, and the set of extension coefficients may be a (12×22) two-dimensional matrix shown in Figure 7. That is, parity check matrix 1 is obtained by extending base matrix 1 using a (12×22) two-dimensional matrix shown in Figure 7. When the matrix shown in Figure 7 represents parity check matrix 1, "-1" in the matrix shown in Figure 7 represents an all-zero matrix of size (K×K), "0" in the matrix shown in Figure 7 represents an identity matrix (also called an identity matrix) of size (K×K), and elements greater than 0 in the matrix shown in Figure 7 represent corresponding values ​​which are CPM and elements of size (K×K), where K represents an extension coefficient corresponding to parity check matrix 1. In fact, parity check matrix 1 is not a (12×22) two-dimensional matrix shown in Figure 7, but a (12×K)×(22×K) two-dimensional matrix extended from the matrix shown in Figure 7. When the matrix shown in Figure 7 represents a set of expansion coefficients, each element in the matrix shown in Figure 7 is a particular value of an expansion coefficient in the set of expansion coefficients. In this example, the set of expansion coefficients may be a matrix of the same size as base matrix 1, i.e., a two-dimensional matrix of (12 x 22) shown in Figure 7.A specific value of an extension coefficient in the set of extension coefficients has a one-to-one correspondence with an element in base matrix 1. It should be understood that when the set of extension coefficients used to extend an arbitrary base matrix is ​​a two-dimensional matrix, the element in the two-dimensional matrix has a one-to-one correspondence with the element at the same position in base matrix 1. A possible implementation of extending a base matrix by using a set of extension coefficients to obtain a check matrix is ​​to use a two-dimensional matrix (having the same size as the base matrix) corresponding to the set of extension coefficients as the check matrix, where "-1" in the check matrix represents an all-zero matrix of size (K x K), "0" in the check matrix represents an identity matrix of size (K x K), and an element greater than 0 in the check matrix represents a corresponding value that is a CPM and element of size (K x K). It should be noted that the set of extension coefficients used to obtain a check matrix by extending a base matrix is ​​not limited to the form of a matrix, and may alternatively be in another form, for example, an array.

[0117] The process of extending a base matrix into a check matrix has been described above by using an example.It should be understood that any base matrix can be extended in the same way to obtain the check matrix of required code length.In this application, it can be understood that when a check matrix is ​​extended from a base matrix, the check matrix follows (or satisfies) the base matrix, or the check matrix corresponds to the base matrix.

[0118] LDPC codes are widely used in WLAN standards to improve the transmission reliability of wireless transmission systems. Compared with the IEEE 802.15.4z standard, the new IEEE 802.15ab standard may introduce new LDPC coding techniques to significantly improve the data transmission reliability of the system. Therefore, it is possible that new LDPC codes will be designed for next-generation WLAN or UWB standards to further improve the reliability and system performance of next-generation WLAN or UWB systems.

[0119] In order to improve the reliability and system performance of next-generation WLAN or UWB systems, this application proposes a design for obtaining check matrices of different code lengths through extension using a single basis matrix and a set (or set) of extension coefficients for next-generation WLAN or UWB systems.The solution provided in this application for obtaining check matrices of different code lengths through extension using a single basis matrix and a set of extension coefficients is applicable to transmission scenarios in which both medium packets and long packets exist, and provides relatively good error control performance.In other words, compared with encoding and decoding using existing check matrices of corresponding code lengths, encoding and decoding using check matrices obtained through extension using the solution provided in this application provides better error control performance.

[0120] The technical solutions of the present application are mainly applicable to wireless communication systems. The wireless communication systems may comply with the wireless communication standards of the Third Generation Partnership Project (3GPP) or may comply with other wireless communication standards, such as the 802 family (e.g., 802.11, 802.15, or 802.20) of the Institute of Electrical and Electronics Engineers (IEEE). The technical solutions of the present application are further applicable to wireless local area network systems, such as Internet of Things (IoT) networks, UWB systems, or Vehicle to Everything (V2X) networks. Certainly, embodiments of the present application are further applicable to other possible communication systems, such as long term evolution (LTE) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, universal mobile telecommunication system (UMTS), worldwide interoperability for microwave access (WiMAX) communication systems, fifth generation (5G) communication systems, and future sixth generation (6G) communication systems.

[0121] The embodiments of the present application are primarily described using networks in which WLAN or UWB systems are deployed, particularly networks to which the IEEE 802.11 standard is applied, as an example. Those skilled in the art will readily understand that aspects of the present application can be extended to other networks using various standards or protocols, such as Bluetooth®, high performance radio LAN (HIPERLAN) (a wireless standard similar to the IEEE 802.11 standard, primarily used in Europe), wide area networks (WANs), personal area networks (PANs), or other networks now known or developed in the future. Therefore, various aspects provided in the present application are applicable to any suitable wireless network, regardless of the coverage area and wireless access protocol used.

[0122] The above-mentioned communication systems applicable to the present application are merely examples for explanation, and the communication systems applicable to the present application are not limited thereto, which are uniformly described in this specification and will not be described again in detail below.

[0123] Please refer to Figure 8. Figure 8 shows an example of a wireless communication system to which the technical solution according to the present application can be applied. The communication system includes an access point (AP) and one or more STAs (only STA1 and STA2 are shown). Both the access point and the STAs support the WLAN protocol. The WLAN protocol may include IEEE 802.11be (also called Wi-Fi 7, EHT protocol), and may further include protocols such as IEEE 802.15ab, IEEE 802.11ax, and IEEE 802.11ac. Indeed, with the continuous evolution and development of communication technologies, the WLAN protocol may further include next-generation protocols such as IEEE 802.11be. WLAN is used as an example. An apparatus for implementing the method in the present application may be an access point or STA in the WLAN, or a chip or processing system installed in the access point or STA.

[0124] An access point is a device having wireless communication capabilities, supports communication according to a WLAN protocol, and has the capability of communicating with other devices (e.g., stations or other access points) in a WLAN network. An access point may also have the capability of communicating with other devices. A WLAN system includes one or more access point (AP) stations and one or more non-AP stations (STAs). For ease of explanation, an access point station will be referred to herein as an access point (AP), and a non-AP station will be referred to as a station (STA).

[0125] An access point may be a standalone device, or may be a chip, processing system, etc. installed in a standalone device. A device having a chip or processing system installed therein may implement the methods and functions in the embodiments of the present application under the control of the chip or processing system (i.e., AP). An AP in the embodiments of the present application is a device that provides services to stations (STAs) and may support 802.11 family protocols, such as 802.15ab, 802.11ac, 802.11n, 802.11g, 802.11b, 802.11a, 802.11be, Wi-Fi 8, or their next generation. For example, an AP may be a communication entity such as a communication server, a router, a switch, or a bridge. The AP may include a macro base station, a micro base station (also called a small cell), a pico base station, a femto base station, a relay station, an access point, a gNB, a transmission reception point (TRP), an evolved NodeB (eNB), a radio network controller (RNC), a home base station (e.g., a home evolved NodeB or home NodeB (HNB)), a baseband unit (BBU), a Wi-Fi access point (AP), an integrated access and backhaul (IAB), etc. Indeed, the AP may alternatively be a chip and processing system in various forms of devices for implementing the methods and functions in the embodiments of the present application.

[0126] A station is a device having wireless communication capabilities, supports communication according to a WLAN protocol, and has the ability to communicate with other stations or access points in a WLAN network. For example, a STA is any communication device that allows a user to communicate with an AP and further with a WLAN. A communication device may be a standalone device, or may be a chip, processing system, etc. installed in a standalone device. A device with a chip or processing system installed may implement the methods and functions in the embodiments of the present application under the control of the chip or processing system (i.e., a station). An STA may include a mobile phone, a mobile station (MS), a tablet computer (PAD), a computer with wireless transceiver capabilities (e.g., a notebook computer), a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, a subscriber unit, a cellular phone, a wireless data card, a personal digital assistant (PDA) computer, a tablet computer, a laptop computer, a machine type communication (MTC) terminal, etc. A station may include various handheld devices, in-vehicle devices, wearable devices, or computing devices with wireless communication capabilities, or other processing devices connected to a wireless modem.Optionally, the station may be a handheld device (handset) having wireless communication capabilities, an in-vehicle device, a wearable device, a terminal in the Internet of Things or a vehicle-to-everything network, any form of terminal in 5G and post-5G evolved communication systems, etc. This is not limited in this application. The station may support multiple WLAN standards such as 802.11 family protocols, for example, 802.15ab, 802.11ac, 802.11n, 802.11g, 802.11b, 802.11a, 802.11be, Wi-Fi 8, or their next generations. The LDPC code encoding method according to the present application will be described below with reference to the accompanying drawings.

[0127] 9 is an interactive flowchart of an LDPC code encoding and decoding method according to an embodiment of the present application. The method process shown in FIG. 9 can be applied to a wireless local area network system and / or an ultra-wideband (UWB)-based wireless personal local area network system. As shown in FIG. 9, the method includes the following steps: 901: The transmitting end performs LDPC coding on a bit sequence to be coded based on a parity check matrix set to obtain a coded sequence.

[0128] In the embodiment of the present application, the transmitting end may be a station or an access point. The transmitting end in the embodiment of the present application is a coding device. In a possible implementation, the check matrix of the LDPC code may be shortened or decimated to obtain a different code rate. See FIG. 4 for the shortening operation.

[0129] In an embodiment of the present application, the parity check matrix set includes a first parity check matrix and a second parity check matrix. A first extension coefficient corresponding to the first parity check matrix is ​​different from a second extension coefficient corresponding to the second parity check matrix. For example, the first extension coefficient may be 1.5 times, 2 times, etc., of the second extension coefficient. For example, the first extension coefficient is 102 and the second extension coefficient is 68. In another example, the first extension coefficient is 68 and the second extension coefficient is 34. In another example, the first extension coefficient is 81 and the second extension coefficient is 54. In another example, the first extension coefficient is 54 and the second extension coefficient is 27. The first parity check matrix is ​​a parity check matrix obtained by extending a base matrix using a first set of circular shift values, and the second parity check matrix is ​​a parity check matrix obtained by extending a base matrix using a second set of circular shift values. The base matrices will be described later and will not be described here. The second set of cyclic shift values ​​is a set of cyclic shift values ​​obtained by using the first set of cyclic shift values. Both the first and second parity check matrices are obtained by extending a base matrix. In other words, both the first and second parity check matrices follow the base matrix. The parity check matrix set may further include a third parity check matrix that follows the base matrix. That is, the parity check matrix set includes two or more parity check matrices that follow the base matrix. In other words, the parity check matrix set includes two or more parity check matrices that are obtained by extending a base matrix. Any two parity check matrices in the parity check matrix set correspond to different extension coefficients. In the following description, the parity check matrix set includes, for example, a first parity check matrix and a second parity check matrix.

[0130] The transmitting end performing LDPC coding on the bit sequence to be coded based on the parity check matrix set to obtain a coded sequence can be understood as the transmitting end performing LDPC coding on the bit sequence to be coded based on any parity check matrix in the parity check matrix set to obtain a coded sequence. A possible implementation of step 901 is as follows: The transmitting end performs LDPC coding on the bit sequence to be coded based on a first parity check matrix in the parity check matrix set to obtain a coded sequence. For example, the transmitting end performs LDPC coding on the bit sequence to be coded by using a generator matrix corresponding to the first parity check matrix to obtain a coded sequence. Another possible implementation of step 901 is as follows: The transmitting end performs LDPC coding on the bit sequence to be coded based on a second parity check matrix in the parity check matrix set to obtain a coded sequence. For example, the transmitting end performs LDPC coding on the bit sequence to be coded by using a generator matrix corresponding to the second parity check matrix to obtain a coded sequence. In a possible implementation, the transmitting end determines to perform LDPC coding on the bit sequence to be coded by using a submatrix of the parity check matrix based on the code rate of a codeword to be generated. That is, the transmitting end may perform LDPC coding on the bit sequence to be coded based on a submatrix formed by some rows or columns of the check matrix according to the code rate of the codeword to be generated. For example, the transmitting end may perform LDPC coding on the bit sequence to be coded based on a submatrix of the first check matrix or the second check matrix to obtain a coded sequence. It can be understood that the transmitting end may perform LDPC coding on the bit sequence to be coded by using any one of two or more check matrices included in the check matrix set according to requirements or a preset rule. For specific processing, please refer to the LDPC code coding and LDPC coding in WLAN described above.The specific method for performing LDPC coding on a bit sequence to be coded based on a check matrix set is not limited in this application.

[0131] It should be noted that the transmitting end may use one check matrix to perform LDPC coding on bit sequences to be coded at the same time, and may use different check matrices to perform LDPC coding on bit sequences to be coded at different time points. Here, the transmitting end performing LDPC coding on the bit sequence to be coded based on a check matrix set to obtain a coded sequence is intended to indicate that the transmitting end may select different check matrices according to actual requirements to perform LDPC coding on the bit sequence to be coded. For example, the transmitting end selects a corresponding check matrix from the check matrix set based on a code rate and / or code length for transmitting data.

[0132] In a possible implementation, since the second set of cyclic shift values ​​is obtained by using the first set of cyclic shift values, the transmitting end may only store the first set of cyclic shift values ​​and does not need to store the second set of cyclic shift values. The transmitting end may directly obtain the first check matrix through extension using the stored first set of cyclic shift values. When it is necessary to use the second check matrix, the transmitting end first obtains the second set of cyclic shift values ​​through processing using the stored first set of cyclic shift values, and then obtains the second check matrix through extension using the second set of cyclic shift values. In this implementation, the stored cyclic shift values ​​can be reduced.

[0133] In a possible implementation, the respective circular shift values ​​of both the first set of circular shift values ​​and the second set of circular shift values ​​satisfy the same modulo operation relationship. For example, the circular shift values ​​in the first set of circular shift values ​​have a one-to-one correspondence with the circular shift values ​​in the second set of circular shift values. The transmitting end may perform the same modulo operation on the circular shift values ​​in the first set of circular shift values ​​to obtain the second set of circular shift values. For example, the second set of circular shift values ​​may be obtained by performing a modulo operation on the first set of circular shift values ​​and a second extension coefficient corresponding to a second check matrix. For example, the first set of circular shift values ​​and the second set of circular shift values ​​are different two-dimensional matrices, and elements in the first set of circular shift values ​​have a one-to-one correspondence with elements at the same positions in the second set of circular shift values. The element at the ith row and jth column in the first set of circular shift values ​​is Z1(i,j), and the element at the ith row and jth column in the second set of circular shift values ​​is Z2(i,j), where Z2(i,j) = Z1(i,j)%Z2, where Z2 is an extension coefficient corresponding to the second check matrix, and both i and j are integers greater than 0. Z2(i,j) can be an element at any position in the second set of circular shift values. % represents a modulo or remainder operation. The modulo operation a%p (or a mod p) represents the remainder when a is divided by p. For example, 58%34 = 24. Note that if Z1(i,j) = -1, then Z2(i,j) = -1, or if Z1(i,j) = 0, then Z2(i,j) = 0. In this implementation, each circular shift value of both the first set of circular shift values ​​and the second set of circular shift values ​​satisfies the same modulo arithmetic relationship, and the second set of circular shift values ​​can be quickly and accurately obtained by using the arithmetic relationship and the first set of circular shift values.

[0134] In a possible implementation, the parity check matrix further includes a third parity check matrix, and the first extension factor corresponding to the first parity check matrix is ​​K times the third extension factor corresponding to the third parity check matrix, where K is an odd number greater than 1, for example, 3. The third parity check matrix is ​​a parity check matrix obtained by extending a base matrix using a third set of circular shift values. The third set of circular shift values ​​is a set of circular shift values ​​obtained by using the first set of circular shift values. The third set of circular shift values ​​is different from the second set of circular shift values. In a possible implementation, the second extension factor is F times the third extension factor, where F is an even number greater than 1, for example, F is 2. For example, the first extension factor is 102, the second extension factor is 68, and the third extension factor is 34. In another example, the first extension factor is 81, the second extension factor is 54, and the third extension factor is 27. In this implementation, the extension factor corresponding to the first check matrix is ​​K times that corresponding to the third check matrix, that is, the code length of the codeword obtained by encoding using the first check matrix is ​​K times that of the codeword obtained by encoding using the third check matrix. The transmitting end may select the check matrix according to the requirements for performing LDPC coding, thereby obtaining codewords with different code lengths and reducing resource overhead.

[0135] In a possible implementation, the coding sequence corresponding to the first check matrix includes codewords having a code length of 2040 bits, the coding sequence corresponding to the second check matrix includes codewords having a code length of 1360 bits, and the coding sequence corresponding to the third check matrix includes codewords having a code length of 680 bits. An coding sequence corresponding to any check matrix in the check matrix set includes one or more codewords obtained by encoding based on the check matrix. The coding sequence corresponding to the first check matrix includes codewords having a code length of 2040 bits, which can be understood as the first check matrix being used for encoding to obtain codewords having a code length of 2040 bits. The coding sequence corresponding to the second check matrix includes codewords having a code length of 1360 bits, which can be understood as the second check matrix being used for encoding to obtain codewords having a code length of 1360 bits. The coding sequence corresponding to the third check matrix includes codewords having a code length of 680 bits, which can be understood as the third check matrix being used for encoding to obtain codewords having a code length of 680 bits. The transmitting end selects a corresponding check matrix from the check matrix set according to the code length for transmitting data, so that codewords of different code lengths can be transmitted.

[0136] In a possible implementation, the coding sequence corresponding to the first check matrix includes codewords having a code length of 1944 bits, the coding sequence corresponding to the second check matrix includes codewords having a code length of 1296 bits, and the coding sequence corresponding to the third check matrix includes codewords having a code length of 648 bits. An coding sequence corresponding to any check matrix in the check matrix set includes one or more codewords obtained by encoding based on the check matrix. The coding sequence corresponding to the first check matrix includes codewords having a code length of 1944 bits, which can be understood as the first check matrix being used for encoding to obtain codewords having a code length of 1944 bits. The coding sequence corresponding to the second check matrix includes codewords having a code length of 1296 bits, which can be understood as the second check matrix being used for encoding to obtain codewords having a code length of 1296 bits. The coding sequence corresponding to the third check matrix includes codewords having a code length of 648 bits, which can be understood as the third check matrix being used for encoding to obtain codewords having a code length of 648 bits. The transmitting end selects a corresponding check matrix from the check matrix set according to the code length for transmitting data, so that codewords of different code lengths can be transmitted. 902: The transmitting end transmits a data packet obtained based on the coded sequence. Correspondingly, the receiving end receives a signal from the transmitting end carrying a data packet obtained based on the coded sequence. In one possible implementation, the transmitting end is a station and the receiving end is an access point. In another possible implementation, the transmitting end is an access point and the receiving end is a station.

[0137] In detail, the transmitting step may include, but is not limited to, performing processing such as stream parsing (stream parser), constellation mapping (constellation mapper), LDPC carrier mapping, etc., by the transmitting end based on the LDPC-encoded bits (i.e., the first data packet) for transmitting on a channel, or in some cases including inverse discrete Fourier transform (IDFT). Obtaining a corresponding data packet based on coding information such as a coding sequence is a conventional technical means in the art, so details will not be described herein.

[0138] A possible implementation of step 902 is as follows: The transmitting end broadcasts a data packet (hereinafter referred to as the first data packet) obtained based on the coding sequence. A possible implementation of step 902 is as follows: The transmitting end sends the first data packet to the receiving end (corresponding to the unicast mode). 903: The receiving end obtains an LDPC coding sequence based on a received signal carrying a data packet obtained based on the coding sequence.

[0139] The LDPC coding sequence is a coding sequence obtained by the transmitting end through LDPC coding. A possible implementation of step 903 is as follows: The receiving end uses a first log likelihood ratio (LLR) sequence corresponding to the received first channel receiving sequence as the coding sequence. The first channel receiving sequence corresponds to a signal received by the receiving end and carrying a data packet obtained based on the coding sequence. It should be understood that the receiving end may also obtain the coding sequence by using another receiving signal carrying a data packet obtained based on the coding sequence. This is not limited in the present application. 904: The receiving end performs decoding on the LDPC coded sequence based on the parity check matrix set to obtain a decoding result. The check matrix set includes a first check matrix and a second check matrix.

[0140] The receiving end decoding the coded sequence based on the parity check matrix set to obtain a decoded result can be understood as the receiving end decoding the coded sequence based on any parity check matrix in the parity check matrix set to obtain a decoded result. A possible implementation of step 904 is as follows: the receiving end decodes the coded sequence based on a first parity check matrix in the parity check matrix set to obtain a decoded result. Another possible implementation of step 901 is as follows: the receiving end decodes the coded sequence based on a second parity check matrix in the parity check matrix set to obtain a decoded result.

[0141] It should be understood that when the transmitting end performs LDPC coding on a bit sequence to be coded based on a first check matrix, the receiving end decodes the coded sequence based on the first check matrix. When the transmitting end performs LDPC coding on a bit sequence to be coded based on a second check matrix, the receiving end decodes the coded sequence based on the second check matrix. The receiving end may learn the check matrix used to decode the coded sequence based on control information from the transmitting end. The receiving end may also learn the check matrix used to decode the coded sequence in another manner. This is not limited in the present application.

[0142] It should be noted that the receiving end decodes the coded sequence at the same time by using one check matrix, and the receiving end may decode the coded sequence to be decoded at different time by using different check matrices. Here, the receiving end decoding the coded sequence based on the check matrix set is intended to indicate that the receiving end may select different check matrices according to actual requirements to decode the coded sequence to be decoded.

[0143] The receiving end may decode the coded sequence based on any check matrix in the check matrix set by using any one of hard-decision decoding, soft-decision decoding, or hybrid decoding, which is not limited in this specification. 905: If the decoding is successful, the receiving end outputs the decoding result.

[0144] Step 905 is optional and not required. The decoding result may be output by the receiving end through an output device such as a display, a display screen, or an audio device. Optionally, if the receiving end decoding is incorrect (or the decoding fails), the receiving end sends retransmission indication information to the transmitting end to request the transmitting end to perform retransmission. In addition, if the decoding fails, the receiving end may store the first LLR sequence and combine the first LLR sequence with the subsequently received retransmitted LLR sequence for decoding.

[0145] In this embodiment of the present application, the first check matrix is ​​a check matrix obtained by extending a base matrix using a first set of circular shift values, and the second check matrix is ​​a check matrix obtained by extending a base matrix using a second set of circular shift values. Since the second set of circular shift values ​​can be obtained by using the first set of circular shift values, the transmitting end only needs to store the first set of circular shift values ​​and does not need to store the second set of circular shift values. In this way, the circular shift values ​​stored by the transmitting end can be reduced. Similarly, the receiving end also only needs to store the first set of circular shift values ​​and does not need to store the second set of circular shift values. In this way, the circular shift values ​​stored by the receiving end can be reduced.

[0146] 10A and 10B are interactive flowcharts of another LDPC code encoding and decoding method according to an embodiment of the present application. The interactive process of the method in FIG. 10A and 10B is a possible implementation of the method described in FIG. 9. In this implementation, the transmitting end performs LDPC encoding on bit sequences of different lengths by using different check matrices, so that codewords of different code lengths can be obtained through encoding. As shown in FIG. 10A and 10B, the method includes the following steps: 1001: A transmitting end performs LDPC coding on a first bit sequence based on a first check matrix to obtain a first coded sequence.

[0147] The transmitting end stores a first set of cyclic shift values. Before performing step 1001, the transmitting end may perform the following operation: extend a basis matrix by using the stored first set of cyclic shift values ​​to obtain a first check matrix. The above describes a method for extending a basis matrix by using a set of cyclic shift values ​​to obtain a check matrix, with reference to an example of obtaining check matrix 1 by extending basis matrix 1. It should be understood that the transmitting end may employ a similar method to extend a basis matrix by using a set of cyclic shift values ​​to obtain a corresponding check matrix. The method for extending a basis matrix by using the first set of cyclic shift values ​​or another set of cyclic shift values ​​will not be described again in this specification.

[0148] Before performing step 1001, the transmitting end may perform the following operation: when LDPC coding is to be performed on a first bit sequence by using a first check matrix, extend a basis matrix by using a first set of cyclic shift values ​​to obtain a first check matrix. The first bit sequence is a bit sequence to be currently sent by the transmitting end. When LDPC coding is to be performed on the first bit sequence by using the first check matrix, the length of the first bit sequence may be within a first interval. The first interval may be an interval configured as needed, which is not limited in the present application. For example, the first interval may be equal to or greater than P bits, where P is 680, 1020, 648, 1296, etc. When the length of the bit sequence to be coded (e.g., the first bit sequence) is within the first interval, the transmitting end performs LDPC coding on the bit sequence based on the first check matrix, and the first check matrix is ​​used for coding to obtain a codeword of a first code length. The first code length may be 1360 bits, 2040 bits, 1296 bits, 1944 bits, etc. The length of the first bit sequence to be encoded being within the first interval may be understood as a condition that needs to be met to obtain the first check matrix by extending based on a basis matrix. In other words, the length of the first bit sequence to be encoded being within the first interval is a condition for triggering the transmitting end to obtain the first check matrix by extending based on a basis matrix. It should be understood that the transmitting end may also obtain the first check matrix by extending based on a basis matrix when another condition is met. For example, when it is determined that the bit sequence to be encoded needs to be coded as a codeword of the first code length, the transmitting end obtains the first check matrix by extending based on a basis matrix.

[0149] The first check matrix is ​​used for encoding to obtain a codeword having a code length of the first code length. The first encoding sequence (i.e., the encoding sequence corresponding to the first check matrix) includes one or more codewords of the first code length. The first code length may be 2040 bits, 1360 bits, 1296 bits, 1944 bits, etc. The codewords may be classified into short codes, medium codes, and long codes based on their code lengths. The code length of a short code is shorter than that of a medium code, which is shorter than that of a long code. A codeword having a code length of the first code length is a long code or a medium code. 1002: A transmitting end transmits a first data packet obtained based on a first encoding sequence.

[0150] Correspondingly, the receiving end receives a signal from the transmitting end carrying a first data packet obtained based on the first encoding sequence. For step 1002, please refer to step 902. 1003: The receiving end obtains a first coded sequence based on a received signal carrying a first data packet. For step 1003, please refer to step 903. 1004: The receiving end performs decoding on the first coded sequence based on the first parity check matrix to obtain a first decoding result.

[0151] The receiving end may learn the check matrix used to decode the first coded sequence based on the control information from the transmitting end. The receiving end may also learn the check matrix used to decode the first coded sequence in another manner, which is not limited in this application. 1005: If the decoding is successful, the receiving end outputs the first decoding result. Step 1005 is optional and not required. For step 1005, please refer to step 905. 1006: The transmitting end performs LDPC coding on the second bit sequence based on the second parity check matrix to obtain a second coded sequence.

[0152] Before performing step 1006, the transmitting end may perform the following operations: obtain a second set of circular shift values ​​by using the stored first set of circular shift values; and extend the basis matrix by using the second set of circular shift values ​​to obtain a second check matrix. In a possible implementation, the second set of circular shift values ​​is obtained by performing a modulo operation on the first set of circular shift values ​​and an extension coefficient corresponding to the second check matrix. The above has described the method of obtaining the second set of circular shift values ​​by performing a modulo operation on the first set of circular shift values ​​and an extension coefficient corresponding to the second check matrix. Therefore, the details will not be described again here.

[0153] Before performing step 1006, the transmitting end may perform the following operation: when LDPC coding is to be performed on a second bit sequence by using a second check matrix, extend the basis matrix by using a second set of cyclic shift values ​​to obtain a second check matrix. The second bit sequence is the bit sequence currently to be sent by the transmitting end. When LDPC coding is to be performed on the second bit sequence by using the second check matrix, the length of the second bit sequence may be within a second interval. The second interval may be configured as needed, which is not limited in the present application. For example, the second interval may be smaller than P bits and larger than Q bits, where F is 680, 1020, 648, 972, etc., and Q is 340, 324, etc. When the length of any bit sequence to be coded (e.g., a second bit sequence) is within the second interval, the transmitting end performs LDPC coding on the bit sequence based on a second check matrix, and the second check matrix is ​​used for coding to obtain a codeword of a second code length. The second code length may be 680 bits, 1360 bits, 648 bits, 1296 bits, etc. The length of the second bit sequence to be coded being within the second interval may be understood as a condition that needs to be met to obtain the second check matrix by extending based on a basis matrix. In other words, the length of the second bit sequence to be coded being within the second interval is a condition that triggers the transmitting end to obtain the second check matrix by extending based on a basis matrix. It should be understood that the transmitting end may also obtain the second check matrix by extending based on a basis matrix when another condition is met. For example, when it is determined that the bit sequence to be coded needs to be coded as a codeword of a second code length, the transmitting end obtains the second check matrix by extending based on a basis matrix.

[0154] The second check matrix is ​​used for encoding to obtain codewords having a code length of the second code length. The second encoding sequence (i.e., the encoding sequence corresponding to the second check matrix) includes one or more codewords having a second code length. The second code length may be 1360 bits, 680 bits, 1296 bits, 648 bits, etc. The codewords having a code length of the second code length are medium codes or short codes. Optionally, the codewords having the first code length are medium codes, and the codewords having the second code length are short codes. For example, the first code length is 1360 bits, and the second code length is 680 bits. Optionally, the codewords having the first code length are long codes, and the codewords having the second code length are medium codes. For example, the first code length is 2040 bits, and the second code length is 1360 bits. The length of the first bit sequence is different from the length of the second bit sequence. The first bit sequence and the second bit sequence need to be LDPC coded by using check matrices corresponding to different extension coefficients. In other words, the first bit sequence and the second bit sequence need to be coded as codewords with different code lengths. For example, the first bit sequence includes 1600 bits, and the second bit sequence includes 500 bits. The transmitting end performs LDPC coding on the first bit sequence based on the first check matrix to obtain a first codeword having a first code length, i.e., a first coded sequence. The transmitting end performs LDPC coding on the second bit sequence based on the second check matrix to obtain a second codeword having a second code length, i.e., a second coded sequence. From this example, it can be seen that when transmitting codewords with different code lengths, the transmitting end needs to perform LDPC coding on the bit sequences to be coded based on different check matrices. 1007: The transmitting end transmits a second data packet obtained based on the second encoding sequence.

[0155] Correspondingly, the receiving end receives a signal from the transmitting end carrying a second data packet obtained based on the second encoding sequence. For step 1007, please refer to step 902. 1008: The receiving end obtains a second coded sequence based on the received signal carrying the second data packet. For step 1008, see step 903. 1009: The receiving end performs decoding on the second coded sequence based on the second parity check matrix to obtain a second decoding result.

[0156] The receiving end may learn the check matrix used to decode the second coded sequence based on the control information from the transmitting end. The receiving end may also learn the check matrix used to decode the second coded sequence in another manner, which is not limited in this application. 1010: If the decoding is successful, the receiving end outputs the second decoding result. Step 1010 is optional and not required. For step 1010, please refer to step 905.

[0157] It should be noted that the transmitting end and the receiving end may first perform steps 1001 to 1005 and then perform steps 1006 to 1010, or may first perform steps 1006 to 1010 and then perform steps 1001 to 1005.

[0158] Steps 1001 to 1005 indicate a process in which the transmitting end and the receiving end perform encoding and decoding by using a first check matrix, and steps 1006 to 1010 indicate a process in which the transmitting end and the receiving end perform encoding and decoding by using a second check matrix, i.e., steps 1001 to 1010 indicate a process in which the transmitting end and the receiving end perform encoding and decoding by using check matrices with different code lengths. 1011: The transmitting end performs LDPC encoding on the third bit sequence according to the third parity check matrix to obtain a third encoded sequence.

[0159] Before performing step 1011, the transmitting end may perform the following operations: obtain a third set of circular shift values ​​by using the stored first set of circular shift values; and extend a basis matrix by using the third set of circular shift values ​​to obtain a third check matrix. In a possible implementation, the third set of circular shift values ​​is obtained by performing a modulo operation on the first set of circular shift values ​​and a third extension coefficient corresponding to the third check matrix. For example, the first set of circular shift values ​​and the third set of circular shift values ​​are different two-dimensional matrices, and elements in the first set of circular shift values ​​have a one-to-one correspondence with elements at the same position in the third set of circular shift values. The element at the ith row and jth column in the first set of circular shift values ​​is Z1(i,j), and the element at the ith row and jth column in the third set of circular shift values ​​is Z3(i,j), where Z3(i,j) = Z1(i,j)%Z3, where Z3 is an extension coefficient corresponding to the third parity check matrix, and both i and j are integers greater than 0. Z3(i,j) can be an element at any position in the third set of circular shift values. Note that if Z1(i,j) = -1, then Z3(i,j) = -1, or if Z1(i,j) = 0, then Z3(i,j) = 0. In this implementation, the third set of circular shift values ​​can be quickly and accurately obtained by performing modulo processing on the first set of circular shift values ​​and the third extension coefficient corresponding to the third parity check matrix.

[0160] Before performing step 1011, the transmitting end may perform the following operation: when LDPC coding is to be performed on a third bit sequence by using a third check matrix, extend the basis matrix by using a third set of cyclic shift values ​​to obtain a third check matrix. The third bit sequence is the bit sequence currently to be sent by the transmitting end. When LDPC coding is to be performed on the third bit sequence by using a third check matrix, the length of the third bit sequence may be within a third interval. The third interval may be configured as needed, which is not limited in the present application. For example, the third interval may be equal to or less than Q bits, where Q is 340, 324, etc. When the length of any bit sequence to be coded (e.g., the third bit sequence) is within the second interval, the transmitting end performs LDPC coding on the bit sequence based on the third check matrix, and the third check matrix is ​​used for coding to obtain a codeword of a third code length. The third code length may be 680 bits or 648 bits. The length of the third bit sequence to be encoded being within the third interval is a condition for triggering the transmitting end to obtain the third check matrix by extending based on the basis matrix. It should be understood that the transmitting end may also obtain the third check matrix by extending based on the basis matrix when another condition is met. For example, when it is determined that the bit sequence to be encoded needs to be encoded as a codeword of a third code length, the transmitting end obtains the third check matrix by extending based on the basis matrix.

[0161] The third check matrix is ​​used for encoding to obtain codewords having a code length of the third code length. The third encoding sequence (i.e., the encoding sequence corresponding to the third check matrix) includes one or more codewords having a third code length. The third code length may be 680 bits, 648 bits, etc. The codewords having a code length of the third code length are short codes. Optionally, the codewords having the first code length are long codes, the codewords having the second code length are medium codes, and the codewords having the third code length are short codes. For example, the first code length is 2040 bits, the second code length is 1360 bits, and the third code length is 680 bits. In another example, the first code length is 1944 bits, the second code length is 1296 bits, and the third code length is 648 bits. The first, second, and third bit sequences need to be coded as codewords with different code lengths, and therefore, the LDPC coding needs to be performed using different check matrices. 1012: The transmitting end transmits a third data packet obtained based on the third encoding sequence.

[0162] Correspondingly, the receiving end receives a signal from the transmitting end carrying a third data packet obtained based on the third encoding sequence. For step 1012, please refer to step 902. 1013: The receiving end obtains a third coded sequence based on the received signal carrying the third data packet. For step 1013, see step 903. 1014: The receiving end performs decoding on the third coded sequence according to the third parity check matrix to obtain a third decoded result.

[0163] The receiving end may learn the check matrix used to decode the third coded sequence based on the control information from the transmitting end. The receiving end may also learn the check matrix used to decode the third coded sequence in another manner, which is not limited in this application. 1015: If the decoding is successful, the receiving end outputs the third decoding result. Steps 1011 to 1015 are optional and not required.

[0164] When the check matrix set includes only the first check matrix and the second check matrix, the transmitting end and the receiving end do not perform steps 1011 to 1015. That is, the transmitting end performs LDPC coding on the bit sequence to be coded by using the first check matrix or the second check matrix.

[0165] When the check matrix set includes a first check matrix, a second check matrix, and a third check matrix, the transmitting end and the receiving end may perform steps 1011 to 1015.

[0166] Steps 1001 to 1005 are processes in which the transmitting end and the receiving end use a first check matrix to perform encoding and decoding. Steps 1006 to 1010 are processes in which the transmitting end and the receiving end use a second check matrix to perform encoding and decoding. Steps 1011 to 1015 are processes in which the transmitting end and the receiving end use a third check matrix to perform encoding and decoding. The order of the three processes is not limited.

[0167] In an embodiment of the present application, the transmitting end performs LDPC encoding on bit sequences of different lengths by using different check matrices, so that codewords of different code lengths are obtained through encoding, thereby reducing resource overhead.

[0168] Figure 9, and Figures 10A and 10B describe the process in which the transmitting end and the receiving end use the check matrix in the check matrix set to perform encoding and decoding.The examples of the base matrix and the check matrix in the check matrix set are not shown in the above description.Therefore, the following describes an example of a base matrix and some possible examples of the first check matrix according to an embodiment of the present application.The base matrix can be the first base matrix or the second base matrix. In a possible implementation, the first basis matrix is ​​a (12×22) matrix shown as follows:

[0169] 1 1 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

[0170] When an extension factor Z=34 is used to extend the first basis matrix, the size of the check matrix (i.e., the third check matrix) actually obtained for the LDPC code is (12×34)×(22×34). When this check matrix is ​​used for encoding at a code rate of 1 / 2, 10×34=340 information bits are encoded to obtain a codeword sequence, i.e., an encoded sequence, with a code length of (22-2)×34=680 bits. If the information bits are less than 340 bits, 0 may be added to the end of the information bits according to industry practice, and then encoding is performed. In addition, after encoding, the check bits obtained through encoding may be thinned out to obtain a higher code rate or a shorter code length.

[0171] In this implementation, the design of the first basis matrix enables the check matrix according to the first basis matrix to have information quickly transmitted and exchanged, decoded and updated between the codeword bits corresponding to the columns of the check matrix, thereby accelerating the overall decoding convergence speed of the system. In a possible implementation, the second basis matrix is ​​a (12×24) matrix shown as follows:

[0172] 1 0 0 0 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 1 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1

[0173] D is an integer from 1 to 12, and E is an integer from 1 to 24. The second basis matrix is ​​a basis matrix corresponding to a parity check matrix having a code length n=648 bits and a code rate R=1 / 2 in 802.11n LDPC.

[0174] It should be noted that a first base matrix obtained by performing various row and column permutations on a first base matrix (or a second base matrix) provided in this application is equivalent to the first base matrix provided in this application. That is, a first base matrix obtained by performing row and column permutations on a first base matrix provided in this application also belongs to the base matrices protected in this application. Various row and column permutations of a first base matrix mean that one or more elements in the first base matrix are replaced by one or more other elements. That is, a first base matrix in which one or more elements are replaced by one or more other elements is equivalent to the first base matrix. In other words, a first base matrix in which one or more elements are replaced by one or more other elements can still be considered a first base matrix. In this application, the row and column permutations of a first base matrix may include any one of the following: One or more elements in a row of the first base matrix are replaced by one or more other elements, one or more elements in a column of the first base matrix are replaced by one or more other elements, multiple elements in different rows of the first base matrix are replaced by other elements, multiple elements in different columns of the first base matrix are replaced by other elements, the positions of multiple rows of the first base matrix are changed, and the positions of multiple columns of the first base matrix are changed. For example, the positions of two columns of the first base matrix are swapped. Replacing an element with another element may be understood as replacing the element with any element different from the element. For example, one or more elements "0" in the base matrix are replaced with elements "1". In another example, one or more elements "1" in the first base matrix are replaced with elements "0".

[0175] The first basis matrix is ​​a (12 × 22) two-dimensional matrix, i.e., a matrix with 12 rows and 22 columns. Here, the specific parameter selection of 12 rows and 22 columns is a trade-off between the implementation complexity and the decoding performance of the basis matrix. Generally, a smaller basis matrix indicates lower implementation complexity, but the degree of freedom in designing the basis matrix is ​​also affected.

[0176] 11 shows an example of a first basis matrix according to the present application. In a possible implementation, as shown in FIG. 11, the matrix within the rectangular box 1101 is the core matrix of the first basis matrix, i.e., H MC and the matrix in the rectangular box 1102 is an extension matrix of the first base matrix, i.e., H IR where the matrix in rectangular box 1103 is a submatrix of the first base matrix, and the lower right corner of the first base matrix is ​​an identity matrix. The present application further protects local matrices (i.e., submatrices) of the first base matrix provided in the present application, such as the matrix in rectangular box 1101, the matrix in rectangular box 1102, or the matrix in rectangular box 1103. That is, the first base matrix may be a rate-compatible base matrix. If incremental redundant bits corresponding to a lower code rate are to be obtained by performing rate compatibility on the first base matrix, the matrix H MC can be extended by the number of columns required based on the required code rate.

[0177] In a possible implementation, the first two columns of the first basis matrix are decimated columns, i.e., the first two columns are involved in encoding but are not actually transmitted. Here, decimation is a common operation in channel coding, in which the corresponding bits are not transmitted after encoding. Details will not be described here. For example, parity check matrix 1 is a parity check matrix obtained by expanding the first basis matrix. The first two columns of the first basis matrix correspond to the first 68 columns of the parity check matrix. The first 68 columns of parity check matrix 1 are involved in encoding, but the first 68 columns of the codeword obtained through encoding are not transmitted. The first two columns of the first basis matrix are directly decimated and are not involved in transmission. This is because the two columns have heavy weights, allowing information to be quickly transmitted and exchanged between codeword bits corresponding to the columns of the matrix, and decoded and updated, thereby accelerating the overall decoding convergence speed of the system. However, because the column weights of the two columns are heavy, if they are involved in transmission and an error occurs in each of their bits, the error will quickly propagate to other codeword bits. This has a negative impact on decoding. Therefore, although the two columns are involved in the actual encoding, the corresponding bits are not transmitted and are thinned out. In addition, the two columns are combined with the seventh row (which has only one 1 except for the corresponding positions of the two thinned columns) and the seventeenth column (which has only one 1) of the first basis matrix, resulting in a significant improvement in decoding performance. The specific design principle for the first two columns of the basis matrix being thinned columns is as follows: A heavier weight in the thinned column indicates better performance of the thinned column in long codes. However, in the case of short codes, if the column weight is too heavy, a subgraph structure, such as a short ring or trap set, may appear in the corresponding factor graph, causing a loss in decoding performance. The weight and sparsity of the first two columns are controlled by using the design shown in the matrix, and a trade-off is made between the performance of short codes and the performance of long codes.

[0178] In a possible implementation, the columns corresponding to information bits in the first basis matrix are the first 10 columns, and the subsequent columns are all columns corresponding to check bits. Therefore, the minimum code rate of the first basis matrix is ​​R = 10 / (22-2) = 1 / 2. For a code rate R = 2 / 3, the corresponding check matrix is ​​the upper left corner part of the entire first basis matrix, i.e., the part within the rectangular box 1101, that is, R = 10 / (17-2) = 2 / 3. In addition to the two code rates mentioned above, the first basis matrix can also work with other code rates, which in particular depend on the number of rows and columns of the first basis matrix being coded. For example, if the first 9 rows and first 19 columns of the first basis matrix are used, a code rate R = 10 / (17-2+2) = 10 / 17 can be obtained.

[0179] In a possible implementation, during a specific encoding, the transmitting end may first divide the information bit sequence into sub-information sequences of size (10 × Z), and any portion less than (10 × Z) may be padded with zeros at any position within the sub-information sequence. Typically, zeros are padded at the end of the sub-information sequence (i.e., a shortening operation in conventional channel coding). Then, regardless of the code rate required by the transmitting end, encoding is first performed by using the portion of the extended basis matrix (i.e., the check matrix) corresponding to the rectangular box 1103, and the encoding method is similar to the LDPC encoding method in 802.11n. Subsequently, the remaining check bit sequence may continue to be encoded based on the required code rate or the number of bits to be transmitted and the encoded codeword sequence by using the remaining portion of the extended basis matrix. The remaining check bit sequence may be encoded through recursive operations, and the specific method is similar to the existing 5G NR LDPC encoding method. Finally, the information bits corresponding to the first two columns of the basis matrix are decimated without being transmitted, and then the bits padded with 0 during encoding are removed, and finally the codeword bit sequence required for system transmission is obtained. A part of the specific encoding process is shown in Figure 4. The information bits corresponding to the first two columns of the basis matrix are obtained by encoding the extended parts of the first two columns of the basis matrix.

[0180] The first base matrix provided in this application can be expanded into a check matrix used for encoding to obtain codewords of different code lengths as needed.As described above, the 1s in the first base matrix are replaced by CPMs of various cyclic shift values, and the 0s are all-0 square matrices of corresponding sizes.Therefore, a series of check matrices for LDPC codes can be obtained based on the first base matrix.The expansion coefficients corresponding to these check matrices may be different from the cyclic shift values ​​of each CPM, but they correspond to the same base matrix.

[0181] The examples of the first check matrix are classified into four types based on the expansion coefficients corresponding to the first check matrix: the first type corresponds to the expansion coefficient 68, the second type corresponds to the expansion coefficient 102, the third type corresponds to the expansion coefficient 54, and the fourth type corresponds to the expansion coefficient 81. These cases will be described separately below. In the following, an example in which the extension coefficient corresponding to the first parity check matrix is ​​68 will be described.

[0182] In a possible implementation, the check matrix set includes a first check matrix and a second check matrix, the first extension factor corresponding to the first check matrix is ​​68, the extension factor corresponding to the second check matrix is ​​34, the first check matrix is ​​any one of matrices 1 to 5 below, and the second check matrix is ​​matrix 6 shown below.

[0183] Matrix 1: 19 64 -1 42 -1 -1 61 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 37 32 -1 32 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 11 -1 -1 -1 3 -1 8 13 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 7 24 4 7 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 29 38 53 -1 40 16 -1 30 15 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 7 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 12 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 -1 61 -1 11 -1 -1 -1 -1 -1 24 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 -1 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 24 -1 -1 -1 36 -1 -1 -1 61 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 58 24 -1 50 -1 -1 -1 -1 -1 -1 -1 -1 26 -1 -1 -1 10 -1 -1 -1 -1 0 -1 -1 4 -1 60 61 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0184] Matrix 2: 53 64 -1 42 -1 -1 61 -1 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 24 -1 -1 61 37 66 -1 32 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 45 -1 -1 -1 37 -1 8 13 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 41 24 38 7 54 -1 -1 62 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 63 38 19 -1 40 16 -1 64 15 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 41 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 5 46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 -1 61 -1 45 -1 -1 -1 -1 -1 58 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 -1 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 58 -1 -1 -1 36 -1 -1 -1 27 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 24 58 -1 50 -1 -1 -1 -1 -1 -1 -1 -1 60 -1 -1 -1 10 -1 -1 -1 -1 0 -1 -1 38 -1 60 61 14 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0185] Matrix 3: 19 64 -1 42 -1 -1 27 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 3 66 -1 66 15 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 0 45 -1 -1 -1 37 -1 42 13 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 7 24 38 41 20 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 29 38 53 -1 40 50 -1 64 49 33 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 41 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 -1 61 -1 45 -1 -1 -1 -1 -1 24 -1 17 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 -1 39 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 24 -1 -1 -1 2 -1 -1 -1 27 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 24 58 -1 16 -1 -1 -1 -1 -1 -1 -1 -1 26 -1 -1 -1 44 -1 -1 -1 -1 0 -1 -1 38 -1 60 61 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0186] Matrix 4: 53 30 -1 42 -1 -1 27 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 3 32 -1 66 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 45 -1 -1 -1 3 -1 8 47 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 21 41 24 38 7 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 63 38 19 -1 6 50 -1 64 15 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 7 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 5 12 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 -1 61 -1 45 -1 -1 -1 -1 -1 24 -1 17 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 -1 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 24 -1 -1 -1 2 -1 -1 -1 61 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 24 24 -1 50 -1 -1 -1 -1 -1 -1 -1 -1 60 -1 -1 -1 10 -1 -1 -1 -1 0 -1 -1 38 -1 60 61 14 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0187] Matrix 5: 19 64 -1 8 -1 -1 61 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 61 37 32 -1 32 15 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 45 -1 -1 -1 3 -1 8 47 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 21 7 58 38 7 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 29 4 53 -1 40 50 -1 30 49 33 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 7 -1 -1 0 -1 -1 -1 18 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 -1 27 -1 11 -1 -1 -1 -1 -1 58 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 50 -1 -1 -1 -1 -1 -1 -1 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 24 -1 -1 -1 36 -1 -1 -1 61 -1 -1 -1 -1 -1 22 -1 -1 -1 -1 0 -1 -1 24 24 -1 16 -1 -1 -1 -1 -1 -1 -1 -1 60 -1 -1 -1 44 -1 -1 -1 -1 0 -1 -1 38 -1 26 27 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0188] Matrix 6: 19 30 -1 8 -1 -1 27 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 24 -1 -1 27 3 32 -1 32 15 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 0 11 -1 -1 -1 3 -1 8 13 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 21 7 24 4 7 20 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 29 4 19 -1 6 16 -1 30 15 33 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 7 -1 -1 0 -1 -1 -1 18 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 5 12 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 -1 27 -1 11 -1 -1 -1 -1 -1 24 -1 17 10 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 -1 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 24 -1 -1 -1 2 -1 -1 -1 27 -1 -1 -1 -1 -1 22 -1 -1 -1 -1 0 -1 -1 24 24 -1 16 -1 -1 -1 -1 -1 -1 -1 -1 26 -1 -1 -1 10 -1 -1 -1 -1 0 -1 -1 4 -1 26 27 14 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0189] When -1 in matrix 1 represents an all-zero matrix of (68×68), 0 represents a unit matrix of size (68×68), and elements greater than 0 represent the CPM of the cyclic shift value of the element of size (68×68), matrix 1 is an example of a first parity check matrix.Similarly, matrix 2, matrix 3, matrix 4, and matrix 5 are all examples of first parity check matrices.When -1 in matrix 6 represents an all-zero matrix of (34×34), 0 represents a unit matrix of size (34×34), and elements greater than 0 represent the CPM of the cyclic shift value of the element of size (34×34), matrix 6 is an example of a second parity check matrix.When matrix 1 to matrix 5 each represent a two-dimensional matrix of (12×22), each element of matrix 1 to matrix 5 is an example of a first set of cyclic shift values. When matrix 6 represents a (12×22) two-dimensional matrix, the elements in matrix 6 are examples of a second set of circular shift values. In the following, an example in which the extension coefficient corresponding to the first parity check matrix is ​​102 will be described.

[0190] In a possible implementation, the check matrix set includes a first check matrix, a second check matrix, and a third check matrix, where the first extension factor corresponding to the first check matrix is ​​102, the second extension factor corresponding to the second check matrix is ​​68, and the extension factor corresponding to the third check matrix is ​​34, where the first check matrix is ​​matrix 21 or matrix 22 below, the second check matrix is ​​matrix 1 above, and the third check matrix is ​​matrix 6 above.

[0191] Queue 21: 87 64 -1 42 -1 -1 61 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 37 100 -1 32 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 11 -1 -1 -1 71 -1 8 13 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 7 24 4 75 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 97 38 53 -1 40 84 -1 30 83 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 7 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 80 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 -1 61 -1 79 -1 -1 -1 -1 -1 24 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 -1 73 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 92 -1 -1 -1 36 -1 -1 -1 61 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 58 24 -1 50 -1 -1 -1 -1 -1 -1 -1 -1 26 -1 -1 -1 10 -1 -1 -1 -1 0 -1 -1 4 -1 60 61 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0192] Queue 22: 19 64 -1 42 -1 -1 61 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 37 100 -1 32 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 11 -1 -1 -1 71 -1 8 13 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 7 24 72 75 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 97 38 53 -1 40 84 -1 30 83 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 75 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 12 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 -1 61 -1 79 -1 -1 -1 -1 -1 24 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 -1 73 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 24 -1 -1 -1 36 -1 -1 -1 61 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 58 92 -1 50 -1 -1 -1 -1 -1 -1 -1 -1 26 -1 -1 -1 78 -1 -1 -1 -1 0 -1 -1 72 -1 60 61 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0193] In a possible implementation, the check matrix set includes a first check matrix, a second check matrix, and a third check matrix, where the first extension factor corresponding to the first check matrix is ​​102, the second extension factor corresponding to the second check matrix is ​​68, and the extension factor corresponding to the third check matrix is ​​34, where the first check matrix is ​​matrix 23 below, the second check matrix is ​​matrix 2 above, and the third check matrix is ​​matrix 6 above.

[0194] Queue 23: 53 64 -1 42 -1 -1 61 -1 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 92 -1 -1 61 37 66 -1 100 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 45 -1 -1 -1 37 -1 76 81 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 41 92 38 75 54 -1 -1 62 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 63 38 87 -1 40 16 -1 64 83 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 41 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 73 46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 -1 61 -1 45 -1 -1 -1 -1 -1 58 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 -1 73 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 58 -1 -1 -1 36 -1 -1 -1 95 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 24 58 -1 50 -1 -1 -1 -1 -1 -1 -1 -1 60 -1 -1 -1 78 -1 -1 -1 -1 0 -1 -1 38 -1 60 61 14 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0195] In a possible implementation, the check matrix set includes a first check matrix, a second check matrix, and a third check matrix, where the first extension factor corresponding to the first check matrix is ​​102, the second extension factor corresponding to the second check matrix is ​​68, and the extension factor corresponding to the third check matrix is ​​34, where the first check matrix is ​​matrix 24 below, the second check matrix is ​​matrix 3 above, and the third check matrix is ​​matrix 6 above.

[0196] Queue 24: 87 64 -1 42 -1 -1 27 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 3 66 -1 66 83 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 0 45 -1 -1 -1 37 -1 42 81 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 75 92 38 41 20 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 97 38 53 -1 40 50 -1 64 49 33 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 41 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 -1 61 -1 45 -1 -1 -1 -1 -1 24 -1 85 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 -1 39 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 92 -1 -1 -1 70 -1 -1 -1 27 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 92 58 -1 16 -1 -1 -1 -1 -1 -1 -1 -1 26 -1 -1 -1 44 -1 -1 -1 -1 0 -1 -1 38 -1 60 61 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0197] In a possible implementation, the check matrix set includes a first check matrix, a second check matrix, and a third check matrix, where the first extension factor corresponding to the first check matrix is ​​102, the second extension factor corresponding to the second check matrix is ​​68, and the extension factor corresponding to the third check matrix is ​​34, where the first check matrix is ​​matrix 25 below, the second check matrix is ​​matrix 4 above, and the third check matrix is ​​matrix 6 above.

[0198] Queue 25: 53 30 -1 42 -1 -1 27 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 71 100 -1 66 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 45 -1 -1 -1 71 -1 76 47 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 21 41 24 38 75 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 63 38 19 -1 6 50 -1 64 83 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 7 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 73 80 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 61 -1 45 -1 -1 -1 -1 -1 24 -1 17 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 24 -1 -1 -1 70 -1 -1 -1 61 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 24 24 -1 50 -1 -1 -1 -1 -1 -1 -1 60 -1 -1 -1 78 -1 -1 -1 -1 0 -1 -1 38 -1 60 61 82 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0199] In a possible implementation, the check matrix set includes a first check matrix, a second check matrix, and a third check matrix, where the first extension factor corresponding to the first check matrix is ​​102, the second extension factor corresponding to the second check matrix is ​​68, and the extension factor corresponding to the third check matrix is ​​34, where the first check matrix is ​​matrix 26 below, the second check matrix is ​​matrix 5 above, and the third check matrix is ​​matrix 6 above.

[0200] Queue 26: 87 64 -1 8 -1 -1 61 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 61 37 32 -1 100 83 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 45 -1 -1 -1 71 -1 8 47 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 21 75 58 38 75 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 29 4 53 -1 40 50 -1 30 49 101 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 7 -1 -1 0 -1 -1 -1 18 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 -1 27 -1 79 -1 -1 -1 -1 -1 58 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 50 -1 -1 -1 -1 -1 -1 -1 73 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 92 -1 -1 -1 36 -1 -1 -1 61 -1 -1 -1 -1 -1 22 -1 -1 -1 -1 0 -1 -1 24 24 -1 16 -1 -1 -1 -1 -1 -1 -1 -1 60 -1 -1 -1 44 -1 -1 -1 -1 0 -1 -1 38 -1 26 95 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0201] When -1 in matrix 21 represents a (68x68) all-zero matrix, 0 represents a (68x68) identity matrix, and an element greater than 0 represents a CPM of a cyclic shift value of element size (68x68), matrix 21 is an example of a first parity check matrix. Similarly, matrices 22, 23, 24, 25, and 26 are all examples of first parity check matrices. When matrices 21 to 26 each represent a (12x22) two-dimensional matrix, each element of matrices 21 to 26 is an example of a first set of cyclic shift values. In the following, an example in which the extension coefficient corresponding to the first parity check matrix is ​​54 will be described.

[0202] In a possible implementation, the parity check matrix set includes a first parity check matrix and a second parity check matrix, the first extension coefficient corresponding to the first parity check matrix is ​​54, the second extension coefficient corresponding to the second parity check matrix is ​​27, the first parity check matrix is ​​the following matrix 31, and the second parity check matrix is ​​a (12×24) two-dimensional matrix shown in Figure 12. Figure 12 shows an example of a parity check matrix.

[0203] Queue 31: 0 -1 -1 -1 0 0 -1 -1 0 -1 -1 0 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 49 0 -1 -1 44 -1 0 0 39 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 0 -1 37 -1 -1 -1 51 -1 0 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 0 47 -1 -1 -1 52 0 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 23 -1 -1 -1 30 -1 -1 -1 0 -1 36 11 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 51 -1 23 28 17 -1 30 -1 37 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 52 -1 -1 -1 35 -1 -1 -1 7 45 -1 -1 0 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 13 51 -1 -1 0 -1 8 -1 33 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 7 20 -1 16 22 37 -1 -1 23 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 38 -1 -1 -1 19 -1 -1 -1 13 -1 3 17 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 25 -1 35 -1 23 45 -1 41 9 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 3 -1 -1 -1 16 -1 -1 2 25 32 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0204] In the following, an example in which the extension coefficient corresponding to the first parity check matrix is ​​81 will be described.

[0205] In a possible implementation, the check matrix set includes a first check matrix, a second check matrix, and a third check matrix, where the first extension factor corresponding to the first check matrix is ​​81, the second extension factor corresponding to the second check matrix is ​​54, and the third extension factor corresponding to the third check matrix is ​​27, where the first check matrix is ​​the following matrix 32, the second check matrix is ​​the above matrix 31, and the third check matrix is ​​a two-dimensional matrix of (12×24) as shown in FIG. 12.

[0206] Matrix 32: 0 -1 -1 -1 0 0 -1 -1 0 -1 -1 0 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 49 0 -1 -1 44 -1 0 0 39 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 60 -1 0 -1 37 -1 -1 -1 51 -1 0 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 56 -1 -1 0 47 -1 -1 -1 52 0 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 77 -1 -1 -1 30 -1 -1 -1 0 -1 36 11 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 51 -1 77 28 17 -1 30 -1 37 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 52 -1 -1 -1 35 -1 -1 -1 7 45 -1 -1 0 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 67 51 -1 -1 0 -1 8 -1 33 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 61 74 -1 70 22 37 -1 -1 23 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 38 -1 -1 -1 73 -1 -1 -1 67 -1 57 71 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 25 -1 35 -1 77 45 -1 41 9 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 57 -1 -1 -1 16 -1 -1 56 25 32 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0

[0207] Matrices 1 to 5, matrices 21 to 26, and matrices 31 and 32 are only some examples, not all, of the first check matrices provided in the present application. The first check matrices provided in the present application may include some rows or columns of any check matrix in matrices 1 to 5, matrices 21 to 26, and matrices 31 and 32. That is, the present application protects not only the entire first base matrix and check matrix provided, but also some rows and columns of the first base matrix and some rows and columns of the check matrix.

[0208] It should be noted that the first check matrix obtained by performing various row and column permutations on the first check matrix provided in the present application is equivalent to the first check matrix provided in the present application, that is, the first check matrix obtained by performing row and column permutations on the first check matrix provided in the present application also belongs to the base matrix protected in the present application. The design principle of the first check matrix will be explained below.

[0209] In a possible implementation, the first set of circular shift values ​​is a set of circular shift values ​​obtained by extending the second set of circular shift values. In other words, the extended first set of shift values ​​is obtained by first extending the circular shift values ​​in the second set of circular shift values. The second set of circular shift values ​​can be any existing set of circular shift values. To satisfy the nesting relationship between the first set of circular shift values ​​and the second set of circular shift values, a modulo arithmetic relationship between the first set of circular shift values ​​and the second set of circular shift values, i.e., Z2(i,j) = Z1(i,j) % Z2, must be satisfied. For example, the circular shift value Z2(2,1) in the second set of circular shift values ​​is 24. If the corresponding circular shift value Z1(2,1) in the first set of circular shift values ​​is 58, then 58%34 = 24, and therefore Z2(2,1) and Z1(2,1) satisfy the modulo arithmetic relationship. If the first set of circular shift values ​​and the second set of circular shift values ​​satisfy a modulo operation relationship, only the first set of circular shift values ​​is needed, and the second set of circular shift values ​​can be calculated by performing a modulo operation on the first set of circular shift values ​​and Z2. In this way, only one set of extension coefficients can be stored to obtain two check matrices.

[0210] In the first expansion, to ensure the above modulo arithmetic relationship, there are two options for each non-negative 1 circular shift value in the second set of circular shift values. If any one of the second set of circular shift values ​​is Z2(i,j)=s, the first expansion of the entry can be Z1(i,j)=s (unchanged) or Z1(i,j)=s+Z2. Z2 is the expansion coefficient corresponding to the second parity check matrix. That is, Z2(i,j)=s in the second set of circular shift values ​​is expanded to Z1(i,j)=s (unchanged) or Z1(i,j)=s+Z2. In a possible implementation, the node to be selected corresponding to Z1(i,j) can be expanded according to the tree, and a circular shift value with a relatively deep depth can be selected. That is, the node to be selected corresponding to Z1(i,j) can be used as the root node for expanding the current Tanner graph into a tree graph. Figure 13 is a diagram of tree expansion according to one embodiment of the present application. As shown in Figure 13, circles represent variable nodes and squares represent check nodes. The deeper the tree expansion depth of the node to be selected, the fewer short rings the corresponding matrix contains, but short rings have a negative impact on performance.

[0211] In a possible implementation, the second set of circular shift values ​​is a set of circular shift values ​​obtained by extending the third set of circular shift values, and the first set of circular shift values ​​is a set of circular shift values ​​obtained by extending the second set of circular shift values. In other words, the second set of extended shift values ​​is obtained by first extending the circular shift values ​​in the third set of circular shift values, and the first set of extended shift values ​​is obtained by secondly extending the circular shift values ​​in the second set of circular shift values. The third set of circular shift values ​​can be any existing set of circular shift values. To satisfy the nesting relationship among the first set of circular shift values, the second set of circular shift values, and the third set of circular shift values, modulo arithmetic relationships, i.e., Z2(i,j) = Z1(i,j) % Z2 and Z3(i,j) = Z1(i,j) % Z3, must be satisfied. For example, the circular shift value Z3(1,1) in the third set of circular shift values ​​is 19. If the corresponding circular shift value Z1(1,1) in the first set of circular shift values ​​is 87, then 87%68=19, and therefore Z2(1,1) and Z1(1,1) satisfy a modulo arithmetic relationship. If the first set of circular shift values ​​and the second set of circular shift values ​​satisfy a modulo arithmetic relationship, and the first set of circular shift values ​​and the third set of circular shift values ​​satisfy a modulo arithmetic relationship, only the first set of circular shift values ​​is needed, and the second set of circular shift values ​​can be calculated by performing a modulo arithmetic on the first set of circular shift values ​​and Z2, and the third set of circular shift values ​​can be calculated by performing a modulo arithmetic on the first set of circular shift values ​​and Z3. In this way, only one set of extension coefficients can be stored to obtain three check matrices.

[0212] Regarding the first extension, to ensure the above modulo arithmetic relationship, there are two options for each non-negative 1 circular shift value in the third set of circular shift values. If any one of the third set of circular shift values ​​is Z3(i,j)=s, the first extension of the entry can be Z2(i,j)=s (unchanged) or Z2(i,j)=s+Z3. Z3 is the extension coefficient corresponding to the third parity check matrix. That is, Z3(i,j)=s in the third set of circular shift values ​​is extended to Z2(i,j)=s (unchanged) or Z2(i,j)=s+Z3. In a possible implementation, the node to be selected corresponding to Z2(i,j) is extended according to the tree, and a circular shift value with a relatively deep depth can be selected.

[0213] Regarding the second extension, to ensure the above modulo arithmetic relationship, each non-negative 1 circular shift value in the second set of circular shift values ​​may be selected based on two cases, namely, whether Z2(i,j) is less than Z3: if Z2(i,j)≧Z3, it is Case A; otherwise, it is Case B.

[0214] For case A, there is only one extension method, i.e., the circular shift value (Z1(i,j) = Z2(i,j)) remains unchanged. In this way, it can be ensured that the modulo arithmetic relationship between Z1(i,j) and Z2(i,j) is maintained after extension.

[0215] For case B, there are two expansion methods. When Z2(i,j)=s, the entry can be expanded to Z1(i,j)=s (unchanged) or Z1(i,j)=s+Z2. In this way, it can be ensured that the modulo arithmetic relationship between the second expansion coefficient and the first expansion coefficient is maintained after expansion. In a possible implementation, the node to be selected corresponding to Z1(i,j) can be expanded according to the tree, and a cyclic shift value with a relatively deep depth can be selected. In the following, the performance of the coding scheme provided in this application will be explained with reference to the accompanying drawings.

[0216] 14A is a diagram of a packet error rate (PER) simulation performance comparison for LDPC codes according to an embodiment of the present application. As shown in FIG. 14A, 1401 represents the PER of an LDPC code having a code length of 1460 bits obtained by encoding using the check matrix provided in an embodiment of the present application (i.e., matrix 2 above), 1402 represents the PER of an LDPC code having a code length of 2040 bits obtained by encoding using the check matrix provided in an embodiment of the present application (i.e., matrix 23 above), 1403 represents the PER of an existing LDPC code having a code length of 1296 bits, and 1404 represents the PER of an existing LDPC code having a code length of 1944 bits. All codes in the simulation are not shortened or thinned, that is, the code rate of all codes is R=½. The simulation results show that all LDPC codes obtained by encoding using the check matrix designed in the present application are better than existing LDPC codes of corresponding code lengths. Here, only the PER of the LDPC code obtained by performing LDPC encoding based on the above matrix 2 and the PER of the LDPC code obtained by performing LDPC encoding based on the above matrix 23 are shown. The LDPC code obtained by performing LDPC encoding based on another check matrix provided in an embodiment of the present application is also better than the existing LDPC code of the corresponding code length.

[0217] FIG. 14B is another PER simulation performance comparison diagram for LDPC codes according to one embodiment of the present application. As shown in FIG. 14B, 1401 represents the PER of an LDPC code having a code length of 1360 bits obtained by encoding using a check matrix provided in one embodiment of the present application (i.e., the above matrix 2), 1402 represents the PER of an LDPC code having a code length of 2040 bits obtained by encoding using a check matrix provided in one embodiment of the present application (i.e., the above matrix 23), 1403 represents the PER of an existing LDPC code having a code length of 1296 bits, 1404 represents the PER of an existing LDPC code having a code length of 1944 bits, 1405 represents the PER of an LDPC code having a code length of 1296 bits obtained by encoding using a check matrix provided in one embodiment of the present application (i.e., the above matrix 31), and 1406 represents the PER of an LDPC code having a code length of 1944 bits obtained by encoding using a check matrix provided in one embodiment of the present application (i.e., the above matrix 32). All codes in the simulation are not shortened or decimated, that is, the code rate of all codes is R=1 / 2.The simulation results show that the LDPC code obtained by performing LDPC encoding based on the check matrix provided in one embodiment of the present application is almost identical to the PER of the 11n LDPC code of the corresponding code length.However, the transmitting end and receiving end only need to implement a short code with an 11n LDPC code length of 648 bits, and by using the short code, it is possible to easily implement intermediate code lengths (1296 bits) and long codes (1944 bits). The following describes the structure of a communication device that can implement the communication method provided in the embodiments of the present application with reference to the accompanying drawings.

[0218] FIG. 15 is a diagram of a structure of a communication device 1500 according to an embodiment of the present application. The communication device 1500 may correspondingly implement the functions or steps implemented by the transmitting end in the above method embodiments, or may correspondingly implement the functions or steps implemented by the receiving end in the above method embodiments. The communication device may include a processing module 1510 and a transceiver module 1520. In a possible implementation, the device may further include a storage unit. The storage unit may be configured to store instructions (codes or programs) and / or data. The processing module 1510 and the transceiver module 1520 may be coupled to the storage unit. For example, the processing module 1510 may read the instructions (codes or programs) and / or data in the storage unit to perform the corresponding method. The above units may be independently located or may be partially or fully integrated. For example, the transceiver module 1520 may include a transmitting module and a receiving module. The transmitting module may be a transmitter, and the receiving module may be a receiver. An entity corresponding to the transceiver module 1520 may be a transceiver or a communication interface.

[0219] In some possible implementations, the communication device 1500 can correspondingly implement the behavior and functions of the transmitting end in the above method embodiments. For example, the communication device 1500 may be the transmitting end or a component (e.g., a chip or circuit) used in the transmitting end. The transceiver module 1520 may be configured to perform all receiving or transmitting operations performed by the transmitting end in the embodiments of FIG. 9 and FIG. 10A and FIG. 10B, for example, step 902 in the embodiment shown in FIG. 9 and steps 1002, 1007, and 1012 in the embodiments shown in FIG. 10A and FIG. 10B, and / or to support other processing of the techniques described herein. The processing module 1510 is configured to perform all operations except the receiving and transmitting operations performed by the transmitting end in the embodiments shown in Figure 9 and Figures 10A and 10B, for example, step 901 in the embodiment shown in Figure 9 and steps 1001, 1006, and 1011 in the embodiments shown in Figures 10A and 10B.

[0220] In some possible implementations, the communication device 1500 can correspondingly implement the behavior and functions of the receiving end in the above method embodiments. For example, the communication device 1500 may be the receiving end or a component (e.g., a chip or circuit) used in the receiving end. The transceiver module 1520 may be configured to perform all receiving or transmitting operations performed by the transmitting end in the embodiments of FIG. 9 and FIG. 10A and FIG. 10B, for example, step 902 in the embodiment shown in FIG. 9 and steps 1002, 1007, and 1012 in the embodiments shown in FIG. 10A and FIG. 10B, and / or to support other processing of the techniques described herein. The processing module 1510 is configured to perform all operations except for the receiving and transmitting operations performed by the receiving end, for example, steps 903, 904, and 905 in the embodiment shown in FIG. 9, and steps 1003, 1004, 1005, 1008, 1009, 1010, 1013, 1014, and 1015 in the embodiment shown in FIGS. 10A and 10B.

[0221] 16 is a diagram of the structure of another communication device 160 according to an embodiment of the present application. The communication device of FIG. 16 can be the above-mentioned transmitting end or can be the above-mentioned receiving end. As shown in FIG. 16, the communications device 160 includes at least one processor 1610 and a transceiver 1620.

[0222] In some embodiments of the present application, the processor 1610 and the transceiver 1620 may be configured to perform functions, operations, etc. performed by the transmitting end. The transceiver 1620 performs all receiving or transmitting operations performed by the transmitting end in the embodiments of, for example, Figure 9 and Figures 10A and 10B. The processor 1610 is configured to perform all operations except for receiving and transmitting operations performed by the transmitting end in the embodiments of, for example, Figure 9 and Figures 10A and 10B.

[0223] In some embodiments of the present application, the processor 1610 and the transceiver 1620 may be configured to perform functions, operations, etc. performed by the receiving end. The transceiver 1620 performs all receiving or transmitting operations performed by the receiving end, for example, in the embodiments of Figure 9 and Figures 10A and 10B. The processor 1610 is configured to perform all operations except for receiving and transmitting operations performed by the receiving end.

[0224] The transceiver 1620 is configured to communicate with another device / apparatus through a transmission medium. The processor 1610 is configured to receive or transmit data and / or signaling through the transceiver 1620 and to implement the methods in the above method embodiments. The processor 1610 may implement the functionality of the processing module 1510, and the transceiver 1620 may implement the functionality of the transceiver module 1520.

[0225] Optionally, the transceiver 1620 may include a radio frequency circuit and an antenna. The radio frequency circuit is primarily configured to convert between baseband signals and radio frequency signals and process the radio frequency signals. The antenna is primarily configured to receive and transmit radio frequency signals in the form of electromagnetic waves. The input / output device, such as a touch screen, display, or keyboard, is primarily configured to receive data entered by a user and output data to the user.

[0226] Optionally, the communication device 160 may further include at least one memory 1630 configured to store program instructions and / or data. The memory 1630 is coupled to the processor 1610. The coupling in the embodiments of the present application may be an indirect coupling or communication connection between devices, units, or modules in an electrical, mechanical, or other form, and is used for information exchange between the devices, units, or modules. The processor 1610 may cooperate with the memory 1630. The processor 1610 may execute program instructions stored in the memory 1630. At least one of the at least one memory may be included in the processor.

[0227] The processor 1610 may read the software program in the memory 1630, interpret and execute the instructions of the software program, and process data of the software program. When data needs to be sent wirelessly, the processor 1610 performs baseband processing on the data to be sent and then outputs the baseband signal to the radio frequency circuit. The radio frequency circuit performs radio frequency processing on the baseband signal and then sends the radio frequency signal in the form of an electromagnetic wave by using an antenna. When data is sent to a communication device, the radio frequency circuit receives the radio frequency signal through the antenna, converts the radio frequency signal to a baseband signal, and outputs the baseband signal to the processor 1610. The processor 1610 converts the baseband signal to data and processes the data.

[0228] In another implementation, the radio frequency circuitry and antenna may be located independently of the processor that performs the baseband processing, e.g., in a distributed scenario, the radio frequency circuitry and antenna may be located independently and remotely from the communication device.

[0229] The specific connection medium between the transceiver 1620, the processor 1610, and the memory 1630 is not limited in the embodiment of the present application. In this embodiment of the present application, the memory 1630, the processor 1610, and the transceiver 1620 are connected through the bus 1640 in FIG. 16. In FIG. 16, the bus is represented by using a thick line. The method of connection between the other components is merely an example for explanation and is not intended to be limiting. The bus may be categorized as an address bus, a data bus, a control bus, etc. For ease of explanation, the bus in FIG. 16 is represented by only one thick line, but this does not indicate that only one bus or one type of bus is present.

[0230] In the embodiments of the present application, the processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and may implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed with respect to the embodiments of the present application may be performed directly by a hardware processor, or may be performed by using a combination of hardware and software modules in a processor.

[0231] FIG. 17 is a diagram of the structure of another communication device 170 according to an embodiment of the present application. As shown in FIG. 17, the communication device shown in FIG. 17 includes a logic circuit 1701 and an interface 1702. The processing module 1510 of FIG. 15 may be implemented by the logic circuit 1701, and the transceiver module 1520 of FIG. 15 may be implemented by the interface 1702. The logic circuit 1701 may be a chip, a processing circuit, an integrated circuit, a system on chip (SoC), etc. The interface 1702 may be a communication interface, an input / output interface, etc. In this embodiment of the present application, the logic circuit and the interface may be coupled to each other. The specific manner of connection between the logic circuit and the interface is not limited in this embodiment of the present application. In some embodiments of the present application, the logic circuitry and interface may be configured to perform functions, operations, etc. performed by the transmitting end. In some embodiments of the present application, the logic circuitry and interface may be configured to perform functions, operations, etc. performed by the receiving end.

[0232] The present application further provides a computer-readable storage medium, which stores a computer program or instruction, which, when executed on a computer, enables the computer to perform the method in the above-described embodiments.

[0233] The present application further provides a computer program product, which includes instructions or a computer program, which, when executed on a computer, performs the methods in the above embodiments. The present application further provides a communication system including a transmitting end and a receiving end.

[0234] The present application further provides a chip, which includes a communication interface and a processor. The communication interface is configured to receive / transmit signals from / to the chip. The processor executes computer program instructions, so that a communication device including the chip is configured to perform the method in the above embodiment.

[0235] The above description is merely a specific implementation of the present application and is not intended to limit the scope of protection of the present application. Any variations or substitutions that are easily understood by those skilled in the art within the technical scope disclosed in the present application shall fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the scope of protection of the claims.

Claims

1. performing low-density parity check (LDPC) coding on a bit sequence based on a parity check matrix set to obtain a coded sequence, wherein the parity check matrix set includes a first parity check matrix and a second parity check matrix, a first extension coefficient corresponding to the first parity check matrix is ​​different from a second extension coefficient corresponding to the second parity check matrix, the first parity check matrix is ​​a parity check matrix obtained by extending a base matrix using a first set of circular shift values, the second parity check matrix is ​​a parity check matrix obtained by extending the base matrix using a second set of circular shift values, and the second set of circular shift values ​​are circular shift values ​​obtained by using the first set of circular shift values; transmitting data packets obtained based on the coding sequence; 10. An encoding method comprising:

2. obtaining a low density parity check (LDPC) coded sequence; decoding the coded sequence based on a parity check matrix set, the parity check matrix set including a first parity check matrix and a second parity check matrix, a first extension coefficient corresponding to the first parity check matrix being different from a second extension coefficient corresponding to the second parity check matrix, the first parity check matrix being a parity check matrix obtained by extending a base matrix using a first set of circular shift values, the second parity check matrix being a parity check matrix obtained by extending the base matrix using a second set of circular shift values, and the second set of circular shift values ​​being circular shift values ​​obtained by using the first set of circular shift values; A decoding method comprising:

3. The method of claim 1 or 2, wherein each circular shift value of the first set of circular shift values ​​and the second set of circular shift values ​​satisfies the same modulo arithmetic relationship.

4. 4. The method of claim 3, wherein the second set of circular shift values ​​are circular shift values ​​obtained by performing a modulo operation on the first set of circular shift values ​​and the second expansion factor.

5. 5. The method of claim 1, wherein the check matrix set further includes a third check matrix, the first extension factor is K times a third extension factor corresponding to the third check matrix, K is an odd number greater than 1, the third check matrix is ​​a check matrix obtained by extending the base matrix using a third set of circular shift values, the third set of circular shift values ​​are circular shift values ​​obtained by using the first set of circular shift values, and the third set of circular shift values ​​is different from the second set of circular shift values.

6. The method of claim 5 , wherein the second expansion factor is F times the third expansion factor, where F is an even integer greater than 1.

7. 7. The method of claim 6, wherein the first expansion factor is 102, the second expansion factor is 68, and the third expansion factor is 34.

8. 8. The method according to claim 6 or 7, wherein the coding sequence corresponding to the first check matrix includes code words having a code length of 2040 bits, the coding sequence corresponding to the second check matrix includes code words having a code length of 1360 bits, and the coding sequence corresponding to the third check matrix includes code words having a code length of 680 bits.

9. The method according to any one of claims 1 to 8, applied in a wireless local area network system and / or an ultra-wideband (UWB) based wireless personal local area network system.

10. The basis matrix is ​​the following (12×22) matrix: 1 1 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 10. The method of claim 1, wherein H is an integer from 1 to 12 and M is an integer from 1 to 22.

11. The first check matrix is ​​the following (12×22) matrix: 19 64 -1 42 -1 -1 61 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 37 32 -1 32 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 11 -1 -1 -1 3 -1 8 13 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 7 24 4 7 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 29 38 53 -1 40 16 -1 30 15 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 7 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 12 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 61 -1 11 -1 -1 -1 -1 -1 24 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 24 -1 -1 -1 36 -1 -1 -1 61 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 58 24 -1 50 -1 -1 -1 -1 -1 -1 -1 26 -1 -1 -1 10 -1 -1 -1 -1 0 -1 -1 4 -1 60 61 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 wherein -1 in the first parity check matrix represents an all-zero matrix of size (K × K), 0 in the first parity check matrix represents an identity matrix of size (K × K), and elements greater than 0 in the first parity check matrix represent CPM of size (K × K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

12. The first check matrix is ​​the following (12×22) matrix: 53 64 -1 42 -1 -1 61 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 24 -1 -1 61 37 66 -1 32 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 45 -1 -1 -1 37 -1 8 13 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 41 24 38 7 54 -1 -1 62 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 63 38 19 -1 40 16 -1 64 15 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 41 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 5 46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 61 -1 45 -1 -1 -1 -1 -1 58 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 58 -1 -1 -1 36 -1 -1 -1 27 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 24 58 -1 50 -1 -1 -1 -1 -1 -1 -1 60 -1 -1 -1 10 -1 -1 -1 -1 0 -1 -1 38 -1 60 61 14 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 wherein -1 in the first parity check matrix represents an all-zero matrix of size (K × K), 0 in the first parity check matrix represents an identity matrix of size (K × K), and elements greater than 0 in the first parity check matrix represent CPM of size (K × K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

13. The first check matrix is ​​the following (12×22) matrix: 19 64 -1 42 -1 -1 27 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 3 66 -1 66 15 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 0 45 -1 -1 -1 37 -1 42 13 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 7 24 38 41 20 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 29 38 53 -1 40 50 -1 64 49 33 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 41 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 61 -1 45 -1 -1 -1 -1 -1 24 -1 17 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 39 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 24 -1 -1 -1 2 -1 -1 -1 27 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 24 58 -1 16 -1 -1 -1 -1 -1 -1 -1 26 -1 -1 -1 44 -1 -1 -1 -1 0 -1 -1 38 -1 60 61 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 wherein -1 in the first parity check matrix represents an all-zero matrix of size (K × K), 0 in the first parity check matrix represents an identity matrix of size (K × K), and elements greater than 0 in the first parity check matrix represent CPM of size (K × K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

14. The first check matrix is ​​the following (12×22) matrix: 53 30 -1 42 -1 -1 27 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 3 32 -1 66 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 45 -1 -1 -1 3 -1 8 47 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 21 41 24 38 7 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 63 38 19 -1 6 50 -1 64 15 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 7 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 5 12 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 61 -1 45 -1 -1 -1 -1 -1 24 -1 17 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 24 -1 -1 -1 2 -1 -1 -1 61 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 24 24 -1 50 -1 -1 -1 -1 -1 -1 -1 60 -1 -1 -1 10 -1 -1 -1 -1 0 -1 -1 38 -1 60 61 14 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 wherein -1 in the first parity check matrix represents an all-zero matrix of size (K × K), 0 in the first parity check matrix represents an identity matrix of size (K × K), and elements greater than 0 in the first parity check matrix represent CPM of size (K × K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

15. The first check matrix is ​​the following (12×22) matrix: 19 64 -1 8 -1 -1 61 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 61 37 32 -1 32 15 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 45 -1 -1 -1 3 -1 8 47 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 21 7 58 38 7 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 29 4 53 -1 40 50 -1 30 49 33 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 7 -1 -1 0 -1 -1 -1 18 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 27 -1 11 -1 -1 -1 -1 -1 58 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 50 -1 -1 -1 -1 -1 -1 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 24 -1 -1 -1 36 -1 -1 -1 61 -1 -1 -1 -1 -1 22 -1 -1 -1 -1 0 -1 -1 24 24 -1 16 -1 -1 -1 -1 -1 -1 -1 60 -1 -1 -1 44 -1 -1 -1 -1 0 -1 -1 38 -1 26 27 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 wherein -1 in the first parity check matrix represents an all-zero matrix of size (K × K), 0 in the first parity check matrix represents an identity matrix of size (K × K), and elements greater than 0 in the first parity check matrix represent CPM of size (K × K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

16. The first check matrix is ​​the following (12×22) matrix: 87 64 -1 42 -1 -1 61 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 37 100 -1 32 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 11 -1 -1 -1 71 -1 8 13 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 7 24 4 75 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 97 38 53 -1 40 84 -1 30 83 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 7 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 80 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 61 -1 79 -1 -1 -1 -1 -1 24 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 73 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 92 -1 -1 -1 36 -1 -1 -1 61 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 58 24 -1 50 -1 -1 -1 -1 -1 -1 -1 26 -1 -1 -1 10 -1 -1 -1 -1 0 -1 -1 4 -1 60 61 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 wherein -1 in the first parity check matrix represents an all-zero matrix of size (K × K), 0 in the first parity check matrix represents an identity matrix of size (K × K), and elements greater than 0 in the first parity check matrix represent CPM of size (K × K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

17. The first check matrix is ​​the following (12×22) matrix: 19 64 -1 42 -1 -1 61 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 37 100 -1 32 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 11 -1 -1 -1 71 -1 8 13 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 7 24 72 75 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 97 38 53 -1 40 84 -1 30 83 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 75 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 12 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 61 -1 79 -1 -1 -1 -1 -1 24 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 73 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 24 -1 -1 -1 36 -1 -1 -1 61 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 58 92 -1 50 -1 -1 -1 -1 -1 -1 -1 26 -1 -1 -1 78 -1 -1 -1 -1 0 -1 -1 72 -1 60 61 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 wherein -1 in the first parity check matrix represents an all-zero matrix of size (K × K), 0 in the first parity check matrix represents an identity matrix of size (K × K), and elements greater than 0 in the first parity check matrix represent CPM of size (K × K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

18. The first check matrix is ​​the following (12×22) matrix: 53 64 -1 42 -1 -1 61 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 92 -1 -1 61 37 66 -1 100 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 45 -1 -1 -1 37 -1 76 81 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 41 92 38 75 54 -1 -1 62 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 63 38 87 -1 40 16 -1 64 83 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 41 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 73 46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 61 -1 45 -1 -1 -1 -1 -1 58 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 73 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 58 -1 -1 -1 36 -1 -1 -1 95 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 24 58 -1 50 -1 -1 -1 -1 -1 -1 -1 60 -1 -1 -1 78 -1 -1 -1 -1 0 -1 -1 38 -1 60 61 14 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 wherein -1 in the first parity check matrix represents an all-zero matrix of size (K × K), 0 in the first parity check matrix represents an identity matrix of size (K × K), and elements greater than 0 in the first parity check matrix represent CPM of size (K × K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

19. The first check matrix is ​​the following (12×22) matrix: 87 64 -1 42 -1 -1 27 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 3 66 -1 66 83 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 0 45 -1 -1 -1 37 -1 42 81 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 55 75 92 38 41 20 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 97 38 53 -1 40 50 -1 64 49 33 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 41 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 61 -1 45 -1 -1 -1 -1 -1 24 -1 85 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 39 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 92 -1 -1 -1 70 -1 -1 -1 27 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 92 58 -1 16 -1 -1 -1 -1 -1 -1 -1 26 -1 -1 -1 44 -1 -1 -1 -1 0 -1 -1 38 -1 60 61 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 wherein -1 in the first parity check matrix represents an all-zero matrix of size (K × K), 0 in the first parity check matrix represents an identity matrix of size (K × K), and elements greater than 0 in the first parity check matrix represent CPM of size (K × K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

20. The first check matrix is ​​the following (12×22) matrix: 53 30 -1 42 -1 -1 27 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 27 71 100 -1 66 49 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 45 -1 -1 -1 71 -1 76 47 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 21 41 24 38 75 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 63 38 19 -1 6 50 -1 64 83 67 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 7 -1 -1 0 -1 -1 -1 52 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 73 80 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 61 -1 45 -1 -1 -1 -1 -1 24 -1 17 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 16 -1 -1 -1 -1 -1 -1 5 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 24 -1 -1 -1 70 -1 -1 -1 61 -1 -1 -1 -1 -1 56 -1 -1 -1 -1 0 -1 -1 24 24 -1 50 -1 -1 -1 -1 -1 -1 -1 60 -1 -1 -1 78 -1 -1 -1 -1 0 -1 -1 38 -1 60 61 82 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 wherein -1 in the first parity check matrix represents an all-zero matrix of size (K × K), 0 in the first parity check matrix represents an identity matrix of size (K × K), and elements greater than 0 in the first parity check matrix represent CPM of size (K × K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

21. The first check matrix is ​​the following (12×22) matrix: 87 64 -1 8 -1 -1 61 -1 -1 -1 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 58 -1 -1 61 37 32 -1 100 83 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 47 0 45 -1 -1 -1 71 -1 8 47 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 21 75 58 38 75 54 -1 -1 28 0 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 29 4 53 -1 40 50 -1 30 49 101 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 7 -1 -1 0 -1 -1 -1 18 -1 -1 1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 39 46 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 -1 -1 -1 27 -1 79 -1 -1 -1 -1 -1 58 -1 51 44 -1 -1 -1 -1 0 -1 -1 -1 -1 0 50 -1 -1 -1 -1 -1 -1 73 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -1 92 -1 -1 -1 36 -1 -1 -1 61 -1 -1 -1 -1 -1 22 -1 -1 -1 -1 0 -1 -1 24 24 -1 16 -1 -1 -1 -1 -1 -1 -1 60 -1 -1 -1 44 -1 -1 -1 -1 0 -1 -1 38 -1 26 95 48 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 wherein -1 in the first parity check matrix represents an all-zero matrix of size (K × K), 0 in the first parity check matrix represents an identity matrix of size (K × K), and elements greater than 0 in the first parity check matrix represent CPM of size (K × K), H is an integer from 1 to 12, and M is an integer from 1 to 22.

22. The first check matrix is ​​the following (12×24) matrix: 0 -1 -1 -1 0 0 -1 -1 0 -1 -1 0 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 49 0 -1 -1 44 -1 0 0 39 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 6 -1 0 -1 37 -1 -1 -1 51 -1 0 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 2 -1 -1 0 47 -1 -1 -1 52 0 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 23 -1 -1 -1 30 -1 -1 -1 0 -1 36 11 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 51 -1 23 28 17 -1 30 -1 37 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 52 -1 -1 -1 35 -1 -1 -1 7 45 -1 -1 0 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 13 51 -1 -1 0 -1 8 -1 33 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 7 20 -1 16 22 37 -1 -1 23 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 38 -1 -1 -1 19 -1 -1 -1 13 -1 3 17 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 25 -1 35 -1 23 45 -1 41 9 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 3 -1 -1 -1 16 -1 -1 2 25 32 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 wherein -1 in the first check matrix represents an all-zero matrix of size (L × L), 0 in the first check matrix represents an identity matrix of size (L × L), and an element greater than 0 in the first check matrix represents a CPM of size (L × L), D is an integer from 1 to 12, and E is an integer from 1 to 24.

23. The first check matrix is ​​the following (12×24) matrix: 0 -1 -1 -1 0 0 -1 -1 0 -1 -1 0 1 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 49 0 -1 -1 44 -1 0 0 39 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 -1 60 -1 0 -1 37 -1 -1 -1 51 -1 0 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 -1 56 -1 -1 0 47 -1 -1 -1 52 0 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 -1 77 -1 -1 -1 30 -1 -1 -1 0 -1 36 11 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 -1 51 -1 77 28 17 -1 30 -1 37 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 -1 52 -1 -1 -1 35 -1 -1 -1 7 45 -1 -1 0 -1 -1 -1 -1 -1 0 0 -1 -1 -1 -1 67 51 -1 -1 0 -1 8 -1 33 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 -1 61 74 -1 70 22 37 -1 -1 23 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 -1 38 -1 -1 -1 73 -1 -1 -1 67 -1 57 71 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 -1 25 -1 35 -1 77 45 -1 41 9 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 0 57 -1 -1 -1 16 -1 -1 56 25 32 -1 -1 1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 wherein -1 in the first check matrix represents an all-zero matrix of size (L × L), 0 in the first check matrix represents an identity matrix of size (L × L), and an element greater than 0 in the first check matrix represents a CPM of size (L × L), D is an integer from 1 to 12, and E is an integer from 1 to 24.

24. 24. The method of claim 22 or 23, wherein the first expansion factor is 81, the second expansion factor is 54, and the third expansion factor is 27.

25. 25. The method of claim 24, wherein the coding sequence corresponding to the first check matrix includes code words having a code length of 1944 bits, the coding sequence corresponding to the second check matrix includes code words having a code length of 1296 bits, and the coding sequence corresponding to the third check matrix includes code words having a code length of 648 bits.

26. A communication device comprising a module or unit configured to implement a method according to any one of claims 1 to 25.

27. 26. A computer readable storage medium storing a computer program, the computer program including program instructions that, when executed, enable a computer to perform the method of any one of claims 1 to 25.

28. 26. A communications device comprising a processor, the processor coupled to a memory, the memory storing computer program instructions, the processor configured to execute the computer program instructions such that the communications device performs a method according to any one of claims 1 to 25.

29. A chip, a communication interface configured to receive / transmit signals to / from the chip; a processor configured to execute computer program instructions so that a communications device comprising said chip performs the method of any one of claims 1 to 25; A chip comprising:

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