Display device

Abstract

The display device includes pixels. The pixels are electrically connected to a first power supply line, a second power supply line, and a data line. The pixels include a first transistor and a capacitor electrically connected between a gate electrode of the first transistor and one electrode of the first transistor. In a plan view, the data line extends in a second direction. The first power supply line extends in a first direction intersecting the second direction and overlaps with the data line and the gate electrode of the first transistor. The second power supply line extends in the second direction and overlaps with the data line and the gate electrode of the first transistor.

Description

[Technical Field]

[0001] The present invention relates to a display device. [Background technology]

[0002] The display device includes pixels, each of which emits light based on a corresponding one of the data signals provided via the data lines. Summary of the Invention [Problem to be solved by the invention]

[0003] Parasitic capacitance exists between the components in a pixel (e.g., the gate electrode and source electrode of a driving transistor) and the data line, and this parasitic capacitance can cause the pixel to emit light at a brightness different from the desired brightness. This can cause defects such as unevenness in the image displayed on the display device, and can degrade display quality.

[0004] An object of the present invention is to provide a display device with improved display quality.

[0005] The problems to be solved by the present invention are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] According to one embodiment of the present invention, a display device may include a pixel electrically connected to a first power line, a second power line, and a data line. The pixel may include a first transistor and a capacitor electrically connected between a gate electrode of the first transistor and one electrode of the first transistor. In a plan view, the data line may extend in a second direction. In a plan view, the first power line may extend in a first direction intersecting the second direction and overlap with the data line and the gate electrode of the first transistor. In a plan view, the second power line may extend in the second direction and overlap with the data line and the gate electrode of the first transistor.

[0007] In a plan view, each of the first power supply line and the second power supply line can overlap a channel region of the first transistor.

[0008] In a plan view, the first power line may extend in the second direction in a region adjacent to the first transistor.

[0009] In the plan view, the second power line may extend in the first direction in a region adjacent to the first transistor.

[0010] The first power line and the second power line are electrically connected to each other, and a constant voltage may be applied to the first power line and the second power line.

[0011] The first power line and the second power line are electrically separated from each other, and different constant voltages may be applied to the first power line and the second power line.

[0012] The pixel may further include a second transistor electrically connected between the data line and the gate electrode of the first transistor, and in a plan view, the first power line and the second power line may not overlap with the second transistor.

[0013] The capacitor may include a first electrode, where the first electrode and the first power line are arranged on the same layer, a second electrode arranged on the first electrode, and a third electrode, where the third electrode and the gate electrode of the first transistor are arranged on the same layer, a fourth electrode arranged on the third electrode and electrically connected to the one electrode of the first transistor.

[0014] A first capacitor may be disposed between the first electrode and the second electrode, a second capacitor may be disposed between the second electrode and the third electrode, and a third capacitor may be disposed between the third electrode and the fourth electrode, and the first capacitor, the second capacitor, and the third capacitor may be electrically connected in parallel to each other to form the capacitor.

[0015] The third electrode can be electrically connected to the first electrode through a first opening arranged in the second electrode, and the fourth electrode can be electrically connected to the second electrode through a second opening arranged in the third electrode.

[0016] In a plan view, the second electrode of the capacitor overlaps with the semiconductor layer of the first transistor, and the second electrode of the capacitor can form a lower electrode of the first transistor.

[0017] The pixel may further include a hold capacitor disposed between the first power line and the second electrode of the capacitor.

[0018] The data line and the fourth electrode may be disposed on the same layer, and the second power line may be disposed on the fourth electrode.

[0019] The pixel further includes a light emitting element, and the second power line is disposed between the capacitor and the anode electrode of the light emitting element to shield the capacitor.

[0020] According to one embodiment of the present invention, a display device may include a pixel electrically connected to a first power line, a second power line, a third power line, and a data line. The pixel may include a first transistor and a capacitor disposed between a gate electrode of the first transistor and one electrode of the first transistor. The first power line may extend in a first direction, and the data line, the second power line, and the third power line may extend in a second direction intersecting the first direction. In a plan view, the first power line, the second power line, and the third power line may cover the data line and the capacitor.

[0021] The second power supply line and the third power supply line are arranged on the same layer, and in a plan view, the second power supply line can overlap a portion of the capacitor, and the third power supply line can overlap the remaining portion of the capacitor.

[0022] The first power line and the second power line are electrically connected to each other, and a constant voltage may be applied to the first power line and the second power line.

[0023] The capacitor may include a first electrode, where the first electrode and the first power line are arranged on the same layer, a second electrode arranged on the first electrode, and a third electrode, where the third electrode and the gate electrode of the first transistor are arranged on the same layer, a fourth electrode arranged on the third electrode and electrically connected to the one electrode of the first transistor.

[0024] The third electrode can be electrically connected to the first electrode through a first opening arranged in the second electrode, and the fourth electrode can be electrically connected to the second electrode through a second opening arranged in the third electrode.

[0025] The data line and the fourth electrode may be disposed on the same layer, and the second power line may be disposed on the fourth electrode.

[0026] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0027] In a display device according to an embodiment of the present invention, a first power line may be disposed below a data line and a first transistor (or a source node) to shield the first transistor and the adjacent data line. A second power line may be disposed above a data line and a first transistor (or a source node) to shield the data line and the first transistor. For example, the first power line and the second power line may shield the data line and the first transistor (or the source node) in both upward and downward directions. Therefore, an accurate data signal may be maintained in the first transistor (or between the gate electrode and source electrode of the first transistor), and the sub-pixel may accurately emit light at a target brightness, thereby improving the display quality of the display device.

[0028] The effects of one embodiment are not limited to the above examples, and various other effects are included within the present specification.

[0029] The above and other features of the present invention will become more apparent from a more detailed description of one embodiment of the present invention with reference to the accompanying drawings. [Brief explanation of the drawings]

[0030] [Figure 1] 1 is a schematic plan view showing a display device according to an embodiment. [Figure 2] 2 is a schematic circuit diagram illustrating one embodiment of a subpixel included in the display device of FIG. 1. FIG. [Figure 3] 2 is a schematic circuit diagram illustrating one embodiment of a subpixel included in the display device of FIG. 1. FIG. [Figure 4] 2 is a schematic plan view illustrating an embodiment of the subpixel of FIG. 1. FIG. [Figure 5] 5 is a schematic plan view illustrating an embodiment of a semiconductor layer included in the first sub-pixel of FIG. 4. FIG. [Figure 6] 5 is a schematic plan view showing an enlarged first region of FIG. 4. FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view showing an embodiment of a first sub-pixel taken along line II' in FIG. 6. [Figure 8] 7 is a schematic cross-sectional view showing an embodiment of a first sub-pixel taken along line II-II' in FIG. 6. FIG. [Figure 9] 2 is a schematic plan view illustrating an embodiment of the subpixel of FIG. 1. FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a comparative example of a sub-pixel. DETAILED DESCRIPTION OF THE INVENTION

[0031] Since the present invention can be modified in various ways and can have various forms, specific embodiments are illustrated in the drawings and will be described in detail herein. In the following description, the singular expression also includes the plural expression unless the context clearly indicates the singular expression only.

[0032] The term "and / or" in the specification and claims is intended to include any combination of the terms "and" and "or" for the purposes of its meaning and interpretation. For example, "A and / or B" can be understood to mean any combination including "A, B, or A and B." The terms "and" and "or" may be used in a conjunctive or disjunctive sense and can be understood to be equivalent to "and / or."

[0033] For purposes of the present invention, the phrase "at least one of A and B" can be interpreted as A alone, B alone, or any combination of A and B. Alternatively, "X, Y, Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as X alone, Y alone, Z alone, or any combination of two or more of X, Y, and Z.

[0034] A "connection" between two components can refer to both an electrical connection and a physical connection inclusively. For example, a "connection" used based on a circuit diagram can refer to an electrical connection.

[0035] Although terms such as "first" and "second" are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, it goes without saying that the first component referred to below may also be the second component within the technical concept of the present invention.

[0036] The term "overlapping" or "overlapping" means that a first object can be above, below, or to the side of a second object, or vice versa. Furthermore, the term "overlapping" may include layer, stack, face or facing, extending over, covering, or partially covering, or any other suitable term understood by one of ordinary skill in the art.

[0037] When an element is described as "not overlapping" or "non-overlapping" another element, it can mean that the elements are spaced apart from one another, offset from one another, separate from one another, or any other suitable terminology that one of ordinary skill in the art would recognize and understand.

[0038] However, the present invention is not limited to the embodiments disclosed below and may be modified and implemented in various forms. In addition, each embodiment disclosed below may be implemented alone or in combination with at least one other embodiment.

[0039] In the drawings, some components not directly related to the features of the present invention may be omitted in order to clearly illustrate the present invention. Also, some components in the drawings may be slightly exaggerated in size and proportion. The same or similar components throughout the drawings will be given the same reference numerals and symbols as much as possible, even if they appear in different drawings, and duplicate descriptions will be omitted.

[0040] As used herein, "about" or "approximately" means inclusive of the stated value and within an acceptable range of deviation from a particular value as determined by one of ordinary skill in the art taking into account the error associated with measuring the particular quantity (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0041] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this invention belongs. Terms as defined in commonly used dictionaries should be interpreted to have a meaning consistent with the meaning in the context of the relevant art, and should not be interpreted as idealized or overly formal.

[0042] Fig. 1 is a schematic plan view showing a display device according to an embodiment, which shows a display device as an example of an electronic device, and in particular a display panel PNL provided in the display device.

[0043] For convenience of explanation, the structure of the display panel PNL is simply shown with the display area DA at the center in Fig. 1. However, depending on the embodiment, at least one driving circuit unit (e.g., at least one of a scan driver and a data driver), wiring, and / or pads (not shown) may be further arranged on the display panel PNL.

[0044] The present invention can be applied to any electronic device having a display surface on at least one side, such as a smartphone, television, tablet PC, mobile phone, video phone, e-book reader, desktop computer, laptop computer, netbook computer, workstation, server, PDA, PMP (portable multimedia player), MP3 player, medical device, camera, or wearable device.

[0045] Referring to FIG. 1, the display panel PNL may include a substrate SUB and pixels PXL arranged on the substrate SUB.

[0046] The substrate SUB constitutes a base member of the display panel PNL and may be a rigid or flexible substrate or film. For example, the substrate SUB may be a rigid substrate made of glass or tempered glass, a flexible substrate (or thin film) made of plastic or metal, and / or at least one insulating layer. The material and / or physical properties of the substrate SUB are not particularly limited. The substrate SUB may be transparent or opaque. According to an embodiment, the substrate SUB may include a reflective material.

[0047] The display panel PNL and the substrate SUB for forming it may include a display area DA for displaying an image and a non-display area NDA other than the display area DA.

[0048] The pixels PXL may be arranged in the display area DA, and various wirings, pads and / or built-in circuits connected to the pixels PXL of the display area DA may be arranged in the non-display area NDA.

[0049] The pixel PXL may include sub-pixels SPXL1 to SPXL3. For example, the pixel PXL may include a first sub-pixel SPXL1, a second sub-pixel SPXL2, and a third sub-pixel SPXL3.

[0050] The sub-pixels SPXL1 to SPXL3 can each emit light of a predetermined or selectable color. According to an embodiment, the sub-pixels SPXL1 to SPXL3 can emit light of different colors. For example, the first sub-pixel SPXL1 can emit light of a first color, the second sub-pixel SPXL2 can emit light of a second color, and the third sub-pixel SPXL3 can emit light of a third color. For example, the first sub-pixel SPXL1 can be a red pixel that emits red light, the second sub-pixel SPXL2 can be a green pixel that emits green light, and the third sub-pixel SPXL3 can be a blue pixel that emits blue light, but is not limited thereto.

[0051] In one embodiment, the first subpixel SPXL1, the second subpixel SPXL2, and the third subpixel SPXL3 include a first-color light-emitting element, a second-color light-emitting element, and a third-color light-emitting element as light sources, respectively, and can emit light of the first color, the second color, and the third color, respectively. In another embodiment, the first subpixel SPXL1, the second subpixel SPXL2, and the third subpixel SPXL3 include light-emitting elements that emit light of the same color, but can also include color conversion layers and / or color filters of different colors disposed on the respective light-emitting elements, thereby emitting light of the first color, the second color, and the third color, respectively. However, the colors, types, and / or numbers of the subpixels SPXL1 to SPXL3 that constitute each pixel PXL are not particularly limited. For example, the color of light emitted by each pixel PXL may vary.

[0052] The sub-pixels SPXL1 to SPXL3 may be regularly arranged in a stripe or PENTILE (registered trademark) arrangement structure. For example, the first, second, and third sub-pixels SPXL1, SPXL2, and SPXL3 may be sequentially and repeatedly arranged along the first direction DR1 and repeatedly arranged along the second direction DR2. At least one of the first, second, and third sub-pixels SPXL1, SPXL2, and SPXL3 arranged adjacent to each other may constitute one pixel PXL that can emit light of various colors. However, the arrangement structure of the sub-pixels SPXL1 to SPXL3 is not limited thereto, and the sub-pixels SPXL1 to SPXL3 may be arranged in the display area DA in various structures and / or manners.

[0053] In one embodiment, each of the subpixels SPXL1 to SPXL3 may be an active pixel. For example, each of the subpixels SPXL1 to SPXL3 may include at least one light source (e.g., a light-emitting element) driven by a control signal (e.g., a scan signal and a data signal) and / or a predetermined or selectable power supply (e.g., a first power supply and a second power supply). However, the type, structure, and / or driving method of the subpixels SPXL1 to SPXL3 applied to the display device are not particularly limited.

[0054] Figure 2 is a schematic circuit diagram showing one embodiment of a subpixel included in the display device of Figure 1. Since the subpixels SPXL1 to SPXL3 included in the display device of Figure 1 are substantially identical or similar to one another, the subpixel SPXL will be described below collectively as the subpixels SPXL1 to SPXL3.

[0055] 1 and 2, the sub-pixel SPXL may be connected to a scan line SL (or a gate line), an emission control line ECL (or a first emission control line), and a data line DL. The scan lines SL may include a first scan line SL1, a second scan line SL2, and a third scan line SL3. A driving signal DRS may be applied to the scan line SL, the emission control line ECL, and the data line DL. A first scan signal GW may be applied to the first scan line SL1, a second scan signal GR may be applied to the second scan line SL2, and a third scan signal GI may be applied to the third scan line SL3. An emission control signal EM (or a first emission control signal) may be applied to the emission control line ECL, and a data signal Vdata (or a data voltage) may be applied to the data line DL.

[0056] The pixel PXL may further be connected to a first power line PL1, a second power line PL2, a reference power line RFL, and an initialization power line INL (or a first initialization power line). A first power supply voltage VDD may be applied to the first power line PL1, a second power supply voltage VSS may be applied to the second power line PL2, a reference power supply voltage VREF may be applied to the reference power line RFL, and an initialization power supply voltage VINT (or a first initialization power supply voltage) may be applied to the initialization power line INL. Each of the first power supply voltage VDD, the second power supply voltage VSS, and the initialization power supply voltage VINT may be a constant voltage. The voltage levels of the first power supply voltage VDD, the second power supply voltage VSS, and the initialization power supply voltage VINT may be different from each other.

[0057] The pixel PXL may include a pixel circuit PXC and a light emitting element LD.

[0058] The pixel circuit PXC may include a first transistor T1 (or drive transistor), a second transistor T2, and a first capacitor Cst (or storage capacitor). In one embodiment, the pixel circuit PXC may further include a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a second capacitor Chold (or hold capacitor).

[0059] The first transistor T1 may be connected between the first power line PL1 and a second node N2 (or a source node). For example, a first electrode (e.g., a drain electrode) of the first transistor T1 may be connected to the first power line PL1 via the fifth transistor T5, and a second electrode (e.g., a source electrode) of the first transistor T1 may be connected to the second node N2. The gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 may further include a bottom electrode, which may be connected to the second node N2. The first transistor T1 may supply a driving current to the light emitting element LD. For example, the first transistor T1 may supply a driving current corresponding to the voltage of the first node N1 to the light emitting element LD.

[0060] The second transistor T2 may be connected between the data line DL and the first node N1. The gate electrode of the second transistor T2 may be connected to the first scan line SL1. The second transistor T2 may be turned on in response to a first scan signal GW on the first scan line SL1. When the second transistor T2 is turned on, the data signal Vdata on the data line DL may be transmitted to the first node N1.

[0061] The third transistor T3 may be connected between the reference power line RFL and the first node N1. A gate electrode of the third transistor T3 may be connected to the second scan line SL2. The third transistor T3 may be turned on in response to a second scan signal GR of the second scan line SL2. When the third transistor T3 is turned on, the reference power voltage VREF may be transferred to the first node N1. The first node N1 may be initialized by the reference power voltage VREF.

[0062] The fourth transistor T4 may be connected between the second node N2 and the initialization power line INL. A gate electrode of the fourth transistor T4 may be connected to the third scan line SL3. The fourth transistor T4 may be turned on in response to a third scan signal GI on the third scan line SL3. When the fourth transistor T4 is turned on, the initialization power voltage VINT may be transferred to the second node N2. The second node N2 may be initialized by the initialization power voltage VINT.

[0063] The fifth transistor T5 may be connected between the first power line PL1 and the first transistor T1. A gate electrode of the fifth transistor T5 may be connected to the emission control line ECL. The fifth transistor T5 may be turned on in response to an emission control signal EM on the emission control line ECL. When the fifth transistor T5 is turned on, a current path through which a driving current flows from the first power line PL1 to the second power line PL2 via the pixel circuit PXC and the light emitting element LD may be formed.

[0064] The first capacitor Cst may be formed or connected between the first node N1 and the second node N2, and may store a voltage corresponding to the data voltage Vdata.

[0065] The second capacitor Chold may be formed or connected between the first power line PL1 and the second node N2, and may stabilize the voltage of the second node N2.

[0066] The light emitting element LD may be connected between the second node N2 and the second power line PL2. For example, the light emitting element LD may be connected in a forward direction between the second node N2 and the second power line PL2. When a driving current is supplied from the first transistor T1, the light emitting element LD may emit light at a brightness corresponding to the driving current.

[0067] In one embodiment, the light-emitting element LD may include an organic light-emitting diode. In other embodiments, the light-emitting element LD may include at least one inorganic light-emitting diode. The type, size, and / or number of the light-emitting element LD may vary depending on the embodiment.

[0068] The first to fifth transistors T1 to T5 may be, but are not limited to, n-type transistors. For example, at least one of the first to fifth transistors T1 to T5 may be changed to a p-type transistor. The voltage level of the drive signal DRS for controlling the operation of each transistor can be set according to the type of each transistor.

[0069] In one embodiment, at least one of the first to fifth transistors T1 to T5 may include an oxide semiconductor. For example, at least one of the transistors including the first transistor T1 may be an oxide semiconductor transistor including an oxide semiconductor.

[0070] The structure and driving method of the sub-pixel SPXL may be variously modified. For example, the pixel circuit PXC may be a pixel circuit with a variety of structures and / or driving methods other than the embodiment shown in FIG.

[0071] FIG. 3 is a schematic circuit diagram illustrating one embodiment of a subpixel included in the display device of FIG.

[0072] 2 and 3, the sub-pixel SPXL may be further connected to a second light-emitting control line ECL2 and a second initialization power line INL2. A second light-emitting control signal EMB may be applied to the second light-emitting control line ECL2, and a second initialization power voltage VAINT may be applied to the second initialization power line INL2. The second initialization power voltage VAINT may be a constant voltage. The second initialization power voltage VAINT may be different from the initialization power voltage VINT of the initialization power line INL, but is not limited to this.

[0073] The pixel circuit PXC may further include a sixth transistor T6 and a seventh transistor T7.

[0074] The sixth transistor T6 may be connected between the second node N2 and the anode electrode of the light emitting element LD. The gate electrode of the sixth transistor T6 may be connected to the second light emitting control line ECL2. The sixth transistor T6 may be turned on in response to the second light emitting control signal EMB of the second light emitting control line ECL2. When the sixth transistor T6 is turned on, a current path may be formed through which a driving current flows from the first power line PL1 to the second power line PL2 via the pixel circuit PXC and the light emitting element LD.

[0075] The seventh transistor T7 may be connected between the anode electrode of the light emitting element LD and the second initialization power line INL2. The gate electrode of the seventh transistor T7 may be connected to the third scan line SL3. The seventh transistor T7 may be turned on in response to a third scan signal GI on the third scan line SL3. When the seventh transistor T7 is turned on, the second initialization power voltage VAINT may be applied to the anode electrode of the light emitting element LD.

[0076] The light-emitting element LD may have a capacitance, which may be represented as a third capacitor CLD. In the pixel circuit PXC of FIG. 2, the second node N2 is initialized by the initialization voltage VINT, and the third capacitor CLD may be fully charged when a driving current is supplied to the light-emitting element LD. This allows the light-emitting element LD of FIG. 2 to emit light with a brightness slightly different from the desired brightness. In the pixel circuit PXC of FIG. 3, the second node N2 is initialized by the initialization voltage VINT, and the light-emitting element LD (e.g., the light-emitting element LD separated from the second node N2 by the sixth transistor T6) may be initialized by the second initialization power supply voltage VAINT. For example, the third capacitor CLD of the light-emitting element LD is charged by the second initialization power supply voltage VAINT, and the driving current is not used to charge the third capacitor CLD. This allows the light-emitting element LD to accurately emit light with the desired brightness.

[0077] FIG. 4 is a schematic plan view showing an embodiment of the subpixel of FIG. 1. FIG. 4 shows subpixels SPXL1 to SPXL3 with the pixel circuit PXC of FIG. 3 at the center. For convenience of explanation, the subpixels SPXL1 to SPXL3 (or the subpixel regions in which the subpixels SPXL1 to SPXL3 are arranged) are separated from one another in the plan view based on the pixel circuits. FIG. 5 is a schematic plan view showing an embodiment of a semiconductor layer included in the first subpixel of FIG. 4. FIG. 6 is a schematic plan view enlarging the first region of FIG. 4. FIG. 7 is a schematic cross-sectional view showing an embodiment of the first subpixel taken along line II' of FIG. 6. FIG. 8 is a schematic cross-sectional view showing an embodiment of the first subpixel taken along line II' of FIG. 6. Compared to FIG. 7, FIG. 8 further shows a first light-emitting element LD1.

[0078] Although the sub-pixels are shown in a simplified manner in FIGS. 4 to 8, with each electrode being shown as a single-film electrode and each insulating layer being shown as a single-film insulating layer, the present invention is not limited to this.

[0079] In describing embodiments of the present invention, "formed and / or provided in the same layer" may mean formed in the same process, and "formed and / or provided in different layers" may mean formed in different processes.

[0080] In Figures 4 to 8, the lateral direction (or horizontal direction) on the plane is represented as the first direction DR1, the longitudinal direction (or vertical direction) on the plane is represented as the second direction DR2, and the thickness direction of the substrate SUB on the cross section is represented as the third direction DR3.

[0081] Referring to Figures 4 to 8, the first subpixel SPXL1, the second subpixel SPXL2, and the third subpixel SPXL3 have pixel circuits (or circuit structures) that are substantially identical or similar to one another. Therefore, the common configurations of the first subpixel SPXL1, the second subpixel SPXL2, and the third subpixel SPXL3 will be described based on the first subpixel SPXL1, and redundant descriptions will be omitted.

[0082] Hereinafter, the components will be described in the order in which they are stacked on the substrate SUB with reference to FIG.

[0083] The eleventh conductive pattern BML11 (or the first horizontal power line), the twelfth conductive pattern BML12, and the repair line DML may be disposed on the substrate SUB.

[0084] In a central region of the first sub-pixel SPXL1 based on the second direction DR2, the eleventh conductive pattern BML11 may extend in the first direction DR1. The eleventh conductive pattern BML11 may cross or intersect the first sub-pixel SPXL1, the second sub-pixel SPXL2, and the third sub-pixel SPXL3. In a region where the eleventh conductive pattern BML11 and the first power line PL1 overlap, the eleventh conductive pattern BML11 may be electrically connected to the first power line PL1 via the first bridge pattern BRP1 and the fifth bridge pattern BRP5. The eleventh conductive pattern BML11 is not connected to the initialization power line INL or the second power line PL2.

[0085] The width of the eleventh conductive pattern BML11 in the second direction DR2 may vary depending on the position. The eleventh conductive pattern BML11 may extend in the direction opposite to the second direction DR2 in a region adjacent to the data line DL and the first transistor T1. As will be described later, the eleventh conductive pattern BML11 overlaps the gate electrode (and channel region) and source electrode (or second electrode, source node) of the first transistor T1 and the data line DL, and may shield the gate electrode and second electrode of the first transistor T1 and the data line DL. For example, the eleventh conductive pattern BML11 may prevent the gate electrode and source electrode (or source node) of the first transistor T1 from being affected (or coupled) by signal transmission of the adjacent data line DL (see FIGS. 7 and 8). Therefore, an accurate data signal is maintained between the gate electrode and source electrode of the first transistor T1, and the subpixel may accurately emit light at a target brightness.

[0086] The twelfth conductive pattern BML12 may be arranged in correspondence with a section where the width of the eleventh conductive pattern BML11 is relatively small. The twelfth conductive pattern BML12 may be arranged in an island shape.

[0087] The repair line DML may be located adjacent to a lower side of the first subpixel SPXL1 and extend in the first direction DR1. The repair line DML may be configured to connect the first subpixel SPXL1 (or the light-emitting element of the first subpixel SPXL1) to a dummy pixel (or a dummy pixel circuit) when the pixel circuit of the first subpixel SPXL1 is defective. According to an embodiment, the repair line DML may be omitted.

[0088] The eleventh conductive pattern BML11, the twelfth conductive pattern BML12, and the repair line DML may include a conductive material. For example, the conductive material may include copper (Cu), molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and / or alloys thereof. The eleventh conductive pattern BML11, the twelfth conductive pattern BML12, and the repair line DML may have a single-layer, double-layer, or multi-layer structure.

[0089] The buffer layer BFL may be provided on the substrate SUB so as to cover the eleventh conductive pattern BML11, the twelfth conductive pattern BML12, and the repair line DML. The buffer layer BFL may be an inorganic insulating film containing an inorganic material. For example, the inorganic material may be silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x The buffer layer BFL may include at least one of metal oxides such as SiO 2 , SiO 3 , SiO 4 , SiO 5 , SiO 6 , SiO 7 , SiO 8 , SiO 9 , SiO 2 , SiO 4 , SiO 2 , SiO 3 , SiO 4 , SiO 5 , SiO 6 , SiO 2 , SiO 2 , SiO 3 , SiO 4 ...

[0090] The second conductive pattern BML2 is disposed on the buffer layer BFL and can overlap with the eleventh conductive pattern BML11 and the twelfth conductive pattern BML12. The second conductive pattern BML2 may be disposed in an island shape. The second conductive pattern BML2 may include a conductive material.

[0091] 7 and 8, the second conductive pattern BML2 may overlap with the eleventh conductive pattern BML11 to form the second capacitor Chold. For example, the second capacitor Chold may be formed between the second conductive pattern BML2 and the eleventh conductive pattern BML11. The second conductive pattern BML2 may overlap with the first semiconductor pattern SCL1 to form the bottom electrode of the first transistor T1. The second conductive pattern BML2 may overlap with the twelfth conductive pattern BML12 to form the first sub-capacitor Cst1. The first sub-capacitor Cst1 may form the first capacitor Cst together with the second sub-capacitor Cst2 and the third sub-capacitor Cst3. The capacitance (or capacity) of the first capacitor Cst may be increased or maximized.

[0092] The first gate insulating layer GI1 may be disposed on the second conductive pattern BML2. The first gate insulating layer GI1 may include an inorganic material. Various materials that provide insulating properties to the first gate insulating layer GI1 may be applied. For example, the first gate insulating layer GI1 may include an organic material. The first gate insulating layer GI1 may be formed as a single layer or may be formed as a multi-layer structure of at least two layers.

[0093] The semiconductor patterns SCL1 to SCL4 may be disposed on the first gate insulating layer GI1 and may be semiconductor patterns made of amorphous silicon, polysilicon, low temperature polysilicon, oxide semiconductor, organic semiconductor, or the like.

[0094] The first semiconductor pattern SCL1 may extend in the second direction DR2. The first semiconductor pattern SCL1 overlapping with the first capacitor electrode CE1 may form a channel region of the first transistor T1, and the first semiconductor pattern SCL1 overlapping with the emission control line ECL may form a channel region of the fifth transistor T5. The channel region may be, for example, a semiconductor pattern not doped with impurities and may be an intrinsic semiconductor. The remaining region excluding the channel region (for example, the remaining region of the first semiconductor pattern SCL1) may be a semiconductor pattern doped with impurities.

[0095] The second semiconductor pattern SCL2 may be located above the first semiconductor pattern SCL1. The second semiconductor pattern SCL2 overlapping the second gate electrode GE2 may form a channel region of the second transistor T2, and the second semiconductor pattern SCL2 overlapping the second scan line SL2 may form a channel region of the third transistor T3.

[0096] The third semiconductor pattern SCL3 and the fourth semiconductor pattern SCL4 may be located under the first semiconductor pattern SCL1. The third semiconductor pattern SCL3 overlapping the third scan line SL3 may form a channel region of the fourth transistor T4. The fourth semiconductor pattern SCL4 overlapping the second emission control line ECL2 may form a channel region of the sixth transistor T6, and the fourth semiconductor pattern SCL4 overlapping the third scan line SL3 may form a channel region of the seventh transistor T7. According to an embodiment, for example, the fourth semiconductor pattern SCL4 may be omitted in the subpixel SPXL of FIG. 2.

[0097] The second gate insulating layer GI2 may be disposed on the semiconductor patterns SCL1 to SCL4. The second gate insulating layer GI2 may include an inorganic material or an organic material and may be formed as a single layer or multiple layers.

[0098] The first capacitor electrode CE1 (or the first gate electrode GE1), the second gate electrode GE2, the first scan line SL1, the horizontal reference power line RFL_H, the second scan line SL2, the light emitting control line ECL, the first bridge pattern BRP1, the second light emitting control line ECL2, the third scan line SL3, the horizontal initialization power line INL_H, and the second initialization power line INL2 may be disposed on the second gate insulating layer GI2 (or the first gate insulating layer GI1). The first capacitor electrode CE1, the second gate electrode GE2, the first scan line SL1, the horizontal reference power line RFL_H, the second scan line SL2, the light emitting control line ECL, the first bridge pattern BRP1, the second light emitting control line ECL2, the third scan line SL3, the horizontal initialization power line INL_H, and the second initialization power line INL2 may include a conductive material.

[0099] The first capacitor electrode CE1 may overlap with the second conductive pattern BML2. A majority of the first capacitor electrode CE1 may overlap with the second conductive pattern BML2. The first capacitor electrode CE1 overlapping with the first semiconductor pattern SCL1 may form the gate electrode of the first transistor T1.

[0100] 7 and 8, the first capacitor electrode CE1 may overlap the second conductive pattern BML2 to form the second sub-capacitor Cst2. The first capacitor electrode CE1 may be connected to the twelfth conductive pattern BML12 through a first opening OP1 that penetrates the second conductive pattern BML2. As a result, the second sub-capacitor Cst2 and the first sub-capacitor Cst1 may be connected in parallel with each other.

[0101] The second gate electrode GE2 may overlap the second semiconductor pattern SCL2 to form the gate electrode of the second transistor T2.

[0102] The first bridge pattern BRP1 overlaps the eleventh conductive pattern BML11 and can be connected to the eleventh conductive pattern BML11 via a contact hole.

[0103] The first scan line SL1, the horizontal reference power line RFL_H, the second scan line SL2, the light emitting control line ECL, the second light emitting control line ECL2, the third scan line SL3, the horizontal initialization power line INL_H, and the second initialization power line INL2 can extend in the first direction DR1 and be arranged along the second direction DR2.

[0104] The first scan line SL1 may be electrically connected to the second gate electrode GE2 through the second bridge pattern BRP2.

[0105] The horizontal reference power line RFL_H may be connected to an upper end of the second semiconductor pattern SCL2 via the third bridge pattern BRP3, for example, the horizontal reference power line RFL_H may be electrically connected to one electrode of the third transistor T3.

[0106] The second scan line SL2 may overlap the second semiconductor pattern SCL2 to form the gate electrode of the third transistor T3.

[0107] The light emitting control line ECL may overlap the first semiconductor pattern SCL1 to form the gate electrode of the fifth transistor T5.

[0108] The light emitting control line ECL may overlap the first semiconductor pattern SCL1 to form the gate electrode of the fifth transistor T5.

[0109] The second light emission control line ECL2 may overlap the fourth semiconductor pattern SCL4 to form the gate electrode of the sixth transistor T6.

[0110] The third scan line SL3 overlaps with the fourth semiconductor pattern SCL4 to form the gate electrode of the seventh transistor T7, and the third scan line SL3 overlaps with the third semiconductor pattern SCL3 to form the gate electrode of the fourth transistor T4.

[0111] The horizontal initialization power line INL_H may be connected to a lower end of the third semiconductor pattern SCL3 through the fourth bridge pattern BRP4, for example, the horizontal initialization power line INL_H may be electrically connected to one electrode of the fourth transistor T4.

[0112] The second initialization power line INL2 may be connected to a lower end of the fourth semiconductor pattern SCL4 via the seventh bridge pattern BRP7, for example, the second initialization power line INL2 may be electrically connected to one electrode of the seventh transistor T7.

[0113] The first interlayer insulating layer ILD1 may be disposed on the first capacitor electrode CE1, the second gate electrode GE2, the first scan line SL1, the horizontal reference power line RFL_H, the second scan line SL2, the light emitting control line ECL, the first bridge pattern BRP1, the second light emitting control line ECL2, the third scan line SL3, the horizontal initialization power line INL_H, and the second initialization power line INL2. The first interlayer insulating layer ILD1 may include an inorganic material or an organic material and may be formed as a single layer or multiple layers.

[0114] The second capacitor electrode CE2, the data line DL, the second bridge pattern BRP2, the third bridge pattern BRP3, the fourth bridge pattern BRP4, the fifth bridge pattern BRP5, the sixth bridge pattern BRP6, the seventh bridge pattern BRP7, and the dummy bridge pattern BRPD may be disposed on the first interlayer insulating layer ILD1. The second capacitor electrode CE2, the data line DL, the second bridge pattern BRP2, the third bridge pattern BRP3, the fourth bridge pattern BRP4, the fifth bridge pattern BRP5, the sixth bridge pattern BRP6, the seventh bridge pattern BRP7, and the dummy bridge pattern BRPD may include a conductive material.

[0115] The second capacitor electrode CE2 may overlap the first capacitor electrode CE1. A majority of the first capacitor electrode CE1 may overlap the second capacitor electrode CE2. The second capacitor electrode CE2 may extend in the second direction DR2 and be connected to upper ends of the third semiconductor pattern SCL3 and the fourth semiconductor pattern SCL4 through contact holes. For example, the second capacitor electrode CE2 may be electrically connected to one electrode of the fourth transistor T4 and one electrode of the sixth transistor T6.

[0116] 7 and 8, the second capacitor electrode CE2 may overlap the first capacitor electrode CE1 to form a third sub-capacitor Cst3. The second capacitor electrode CE2 may be connected to the first semiconductor pattern SCL1 (or the source region of the first semiconductor pattern SCL1) through a second opening OP2 that penetrates the first capacitor electrode CE1. For example, the second capacitor electrode CE2 may be electrically connected to one electrode (e.g., a source electrode) of the first transistor T1.

[0117] The second capacitor electrode CE2 may be connected to the second conductive pattern BML2 through the second opening OP2, so that the third sub-capacitor Cst3 and the second sub-capacitor Cst2 may be connected in parallel with each other.

[0118] The data lines DL may extend in the second direction DR2 and be repeatedly arranged along the first direction DR1. The data lines DL may be connected to the left end of the second semiconductor pattern SCL2 through contact holes. For example, the data lines DL may be electrically connected to one electrode of the second transistor T2.

[0119] In one embodiment, the data line DL may not include a bent portion and may have a constant line width along the second direction DR2. To prevent the data line DL from affecting adjacent components, the data line DL may have a partially bent shape, but in this case, the resistance of the data line DL may increase. In an embodiment of the present invention, the data line DL may not include a bent portion because the data line DL and adjacent components (e.g., the first transistor T1) are shielded by the eleventh conductive pattern BML11 and a power line (e.g., the first power line PL1, etc.) described below.

[0120] The second bridge pattern BRP2 overlaps the first scan line SL1 and the second gate electrode GE2, and can electrically connect the first scan line SL1 and the second gate electrode GE2 through a contact hole.

[0121] The third bridge pattern BRP3 may electrically connect one electrode of the third transistor T3 to the horizontal reference power line RFL_H through a contact hole.

[0122] The fourth bridge pattern BRP4 overlaps the horizontal initialization power line INL_H and a lower end of the third semiconductor pattern SCL3 and can electrically connect the horizontal initialization power line INL_H to the lower end of the third semiconductor pattern SCL3 (e.g., one electrode of the fourth transistor T4) through a contact hole.

[0123] The fifth bridge pattern BRP5 overlaps with a lower end of the first semiconductor pattern SCL1 and the first bridge pattern BRP1, and may be connected to the first bridge pattern BRP1 and the lower end of the first semiconductor pattern SCL1 (e.g., one electrode of the fifth transistor T5). The fifth bridge pattern BRP5 may be connected to a first power line PL1, which will be described later. The first power line PL1 may be electrically connected to one electrode of the fifth transistor T5 via the fifth bridge pattern BRP5, and the first power line PL1 may be electrically connected to the eleventh conductive pattern BML11 via the fifth bridge pattern BRP5 and the first bridge pattern BRP1.

[0124] The sixth bridge pattern BRP6 overlaps the second semiconductor pattern SCL2 and the first capacitor electrode CE1 and can electrically connect the second semiconductor pattern SCL2 (e.g., the node between the second transistor T2 and the third transistor T3) and the first capacitor electrode CE1.

[0125] The seventh bridge pattern BRP7 overlaps a lower end of the third semiconductor pattern SCL3 and the horizontal initialization power line INL_H and electrically connects the lower end of the third semiconductor pattern SCL3 (e.g., one electrode of the fourth transistor T4) to the horizontal initialization power line INL_H. The seventh bridge pattern BRP7 may be connected to an initialization power line INL, which will be described later. The initialization power line INL may be electrically connected to the horizontal initialization power line INL_H via the seventh bridge pattern BRP7.

[0126] The dummy bridge pattern BRPD may overlap the fourth semiconductor pattern SCL4 and the repair line DML. The dummy bridge pattern BRPD may be connected to the fourth semiconductor pattern SCL4 (e.g., a node between the sixth transistor T6 and the seventh transistor T7). The dummy bridge pattern BRPD may not be connected to the repair line DML. In another embodiment, when the dummy bridge pattern BRPD is connected to the repair line DML, the dummy bridge pattern BRPD may electrically connect the dummy line to a node between the sixth transistor T6 and the seventh transistor T7.

[0127] The second interlayer insulating layer ILD2 may be disposed on the second capacitor electrode CE2, the data line DL, the second bridge pattern BRP2, the third bridge pattern BRP3, the fourth bridge pattern BRP4, the fifth bridge pattern BRP5, the sixth bridge pattern BRP6, the seventh bridge pattern BRP7, and the dummy bridge pattern BRPD. The second interlayer insulating layer ILD2 may include an inorganic material or an organic material and may be formed as a single layer or multiple layers.

[0128] The first power line PL1, the initialization power line INL, the second power line PL2, the reference power line RFL, and the eighth bridge pattern BRP8 may be disposed on the second interlayer insulating layer ILD2. The first power line PL1, the initialization power line INL, the second power line PL2, the reference power line RFL, and the eighth bridge pattern BRP8 may include a conductive material.

[0129] The first power line PL1, the initialization power line INL, the second power line PL2, and the reference power line RFL may extend approximately in the second direction DR2, and the first power line PL1, the initialization power line INL, the second power line PL2, and the reference power line RFL may be arranged along the first direction DR1. The first power line PL1 may be arranged adjacent to the left side of the first subpixel SPXL1, the initialization power line INL may be arranged corresponding to the boundary between the first subpixel SPXL1 and the second subpixel SPXL2, the second power line PL2 may be arranged corresponding to the boundary between the second subpixel SPXL2 and the third subpixel SPXL3, and the reference power line RFL may be arranged adjacent to the right side of the first subpixel SPXL1.

[0130] The first power line PL1, the initialization power line INL, and the second power line PL2 each overlap with the data line DL to shield the data line DL. The reference power line RFL does not overlap with the data line DL. If the reference power line RFL overlaps with the data line DL, the reference power voltage VREF of the reference power line RFL (and the voltage at the gate electrode of the first transistor T1 that controls the drive current) may be changed by the data signal on the data line DL.

[0131] The first power line PL1 overlaps the fifth bridge pattern BRP5 and may be connected to the fifth bridge pattern BRP5 through a contact hole. The first power line PL1 may be electrically connected to the eleventh conductive pattern BML11 through the fifth bridge pattern BRP5 and the first bridge pattern BRP1. The eleventh conductive pattern BML11 and the first power line PL1 may form a mesh structure over the entire display device.

[0132] The first power line PL1 may partially overlap the second capacitor electrode CE2. The first power line PL1 overlaps the gate electrode (and channel region) of the first transistor T1, shielding the gate electrode and source electrode (or the second capacitor electrode CE2 connected to the source electrode, or source node) of the first transistor T1 and preventing the gate electrode and source electrode (or source node) of the first transistor T1 from being affected by signal transmission on the data line DL (see FIGS. 7 and 8). For this reason, the first power line PL1 may extend in the first direction DR1 in a region adjacent to the first transistor T1. The first power line PL1 may not overlap the second to seventh transistors T2 to T7, but is not limited to this.

[0133] In an area where the initialization power line INL and the horizontal initialization power line INL_H intersect, the initialization power line INL may be electrically connected to the horizontal initialization power line INL_H via a fourth bridge pattern BRP4. The initialization power line INL and the horizontal initialization power line INL_H may form a mesh structure over the entire display device.

[0134] The initialization power line INL extends in the first direction DR1 in a region adjacent to the first transistor T1 (or the first transistor T1 of the second subpixel SPXL2) and may partially overlap the second capacitor electrode CE2. For example, the initialization power line INL may overlap the second capacitor electrode CE2 of the first subpixel SPXL1 (e.g., the remaining portion of the second capacitor electrode CE2 not covered by the first power line PL1). For example, the second capacitor electrode CE2 of the first subpixel SPXL1 may be mostly shielded by the initialization power line INL and the first power line PL1. Similar to the first power line PL1, the initialization power line INL may partially overlap the second capacitor electrode CE2 of the second subpixel SPXL2.

[0135] Similar to the first power supply line PL1 and the initialization power supply line INL, the second power supply line PL2 may partially overlap the second capacitor electrode CE2. For example, the second power supply line PL2 may overlap the second capacitor electrode CE2 of the second subpixel SPXL2 (e.g., the remaining portion of the second capacitor electrode CE2 not covered by the initialization power supply line INL). For example, the second capacitor electrode CE2 of the second subpixel SPXL2 may be mostly shielded by the second power supply line PL2 and the initialization power supply line INL. The second power supply line PL2 may partially overlap the second capacitor electrode CE2 of the third subpixel SPXL3.

[0136] In the region where the reference power line RFL and the horizontal reference power line RFL_H intersect, the reference power line RFL may be electrically connected to the horizontal reference power line RFL_H through a bridge pattern (e.g., a bridge pattern corresponding to the third bridge pattern BRP3). The reference power line RFL and the horizontal reference power line RFL_H may form a mesh structure across the entire display device. The reference power line RFL may overlap with the second capacitor electrode CE2 of the third subpixel SPXL3 (e.g., the remaining portion of the second capacitor electrode CE2 not covered by the second power line PL2). For example, the second capacitor electrode CE2 of the third subpixel SPXL3 may be mostly shielded by the reference power line RFL and the second power line PL2.

[0137] The eighth bridge pattern BRP8 may overlap the dummy bridge pattern BRPD. The eighth bridge pattern BRP8 may be electrically connected to the fourth semiconductor pattern SCL4 (e.g., a node between the sixth transistor T6 and the seventh transistor T7) via the dummy bridge pattern BRPD. The eighth bridge pattern BRP8 may be connected to a light emitting element (see FIGS. 8 and 9). For example, the eighth bridge pattern BRP8 may electrically connect the light emitting element to a node between the sixth transistor T6 and the seventh transistor T7.

[0138] The protective layer PSV may be disposed on the first power line PL1, the initialization power line INL, the second power line PL2, the reference power line RFL, and the eighth bridge pattern BRP8. The protective layer PSV may include an organic material and / or an inorganic material. For example, the organic material may include an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and / or a benzocyclobutene resin.

[0139] A light emitting element may be disposed on the protective layer PSV.

[0140] In one embodiment, in the first sub-pixel SPXL1, a first light-emitting element LD1 is disposed on the protective layer PSV, and the first light-emitting element LD1 may be an organic light-emitting diode. The first light-emitting element LD1 may include a first pixel electrode AND (or an anode electrode), an emission layer EML, and a second pixel electrode CAD (or a cathode electrode).

[0141] A first pixel electrode AND may be disposed on the protective layer PSV, and the first pixel electrode AND may be electrically connected to the eighth bridge pattern BRP8 through a contact hole penetrating the protective layer PSV (see FIG. 9).

[0142] The pixel defining layer PDL may include an opening through which at least a portion of the first pixel electrode AND is exposed. The pixel defining layer PDL may include an organic material.

[0143] An emission layer EML may be disposed on the first pixel electrode AND, and a second pixel electrode CAD may be disposed on the emission layer EML.

[0144] At least one of the first pixel electrode AND and the second pixel electrode CAD may be a transmissive electrode. For example, if the display device is a top-emitting display device, the first pixel electrode AND may be a reflective electrode and the second pixel electrode CAD may be a transmissive electrode.

[0145] The light-emitting layer EML may be disposed on the exposed surface of the first pixel electrode AND. The light-emitting layer EML may have a multilayer thin film structure including at least a light-generation layer. For example, the light-emitting layer EML may include a hole injection layer that injects holes, a hole transport layer that has excellent hole transport properties and suppresses the movement of electrons that cannot be combined in the light-generation layer, thereby increasing the chance of hole and electron recombination, a light-generation layer that emits light by recombining the injected electrons and holes, a hole blocking layer that suppresses the movement of holes that cannot be combined in the light-generation layer, an electron transport layer that smoothly transports electrons to the light-generation layer, and an electron injection layer that injects electrons.

[0146] The hole injection layer, the hole transport layer, the hole blocking layer, the electron transport layer, and the electron injection layer may each be a common film connected to adjacent sub-pixels (or sub-pixel regions).

[0147] The second pixel electrode CAD can be disposed on the light-emitting layer EML. The second pixel electrode CAD can be a semi-transmissive reflective film. For example, the second pixel electrode CAD can be a thin metal layer having a thickness sufficient to transmit light. The second pixel electrode CAD can transmit a portion of the light generated by the light-generating layer and reflect the remainder of the light generated by the light-generating layer.

[0148] A portion of the light emitted from the light-emitting layer EML cannot pass through the second pixel electrode CAD, and the light reflected by the second pixel electrode CAD can be reflected again by the first pixel electrode AND. For example, the light emitted from the light-emitting layer EML can resonate between the first pixel electrode AND and the second pixel electrode CAD. The light resonance can improve the light extraction efficiency of the first light-emitting element LD1.

[0149] A thin film encapsulation layer TFE may be disposed on the first light emitting element LD1.

[0150] The thin film encapsulation layer TFE may be disposed on the second pixel electrode CAD, may be disposed in common to the sub-pixels SPXL, or may directly cover the second pixel electrode CAD.

[0151] The thin film encapsulation layer TFE may include a first inorganic film, an organic film, and a second inorganic film stacked on the second pixel electrode CAD.

[0152] As described above, the eleventh conductive pattern BML11 is disposed below the data line DL and the second conductive pattern BML2, and can shield the data line DL and the second conductive pattern BML2 (or the source node). The first power line PL1, the initialization power line INL, and the second power line PL2 are disposed on the second capacitor electrode CE2, and can shield the data line DL and the second capacitor electrode CE2 (or the source node). Therefore, an accurate data signal is maintained between the gate electrode and the source electrode of the first transistor T1, and the sub-pixel accurately emits light at a target brightness, thereby improving the display quality of the display device.

[0153] The embodiments of Figures 4 to 8 can also be applied to the sub-pixel SPXL of Figure 2. For example, in the embodiments of Figures 4 to 8, the sixth transistor T6 and the seventh transistor T7 (and the second initialization power line VAINT and the second control line EMB) can be removed to implement the sub-pixel SPXL of Figure 3.

[0154] FIG. 9 is a schematic plan view showing one embodiment of the subpixel of FIG.

[0155] 4, 8 and 9, except for the light emitting elements LD1 to LD3, the subpixels SPXL1 to SPXL3 in FIG. 9 are substantially the same as the subpixels SPXL1 to SPXL3 in FIG. 4, and therefore a duplicated description will be omitted.

[0156] The first light emitting element LD1 may overlap the second capacitor electrode CE2 of the first sub-pixel SPXL1. The first light emitting element LD1 (or the first pixel electrode AND of the first light emitting element LD1, see FIG. 8) may be connected to the eighth bridge pattern BRP8 of the first sub-pixel SPXL1.

[0157] In a region where the first light emitting element LD1 and the second capacitor electrode CE2 of the first sub-pixel SPXL2 overlap, most of the second capacitor electrode CE2 may be covered or shielded by the first power line PL1 and the initialization power line INL. With respect to the data line DL, the first power line PL1 and the initialization power line INL may shield the first light emitting element LD1 (or the anode electrode of the first light emitting element LD1).

[0158] The second light emitting element LD2 may be disposed below the first light emitting element LD1. The second light emitting element LD2 (or the first pixel electrode AND of the second light emitting element LD2, see FIG. 8) may be connected to the bridge pattern of the second sub-pixel SPXL2 (e.g., a bridge pattern corresponding to the eighth bridge pattern BRP8).

[0159] The third light emitting element LD3 may partially overlap the pixel circuit of the second sub-pixel SPXL2 and the pixel circuit of the third sub-pixel SPXL3. A second power line PL2 is disposed under the third light emitting element LD3, and the second power line PL2 may cover or shield components (e.g., the first transistor and the storage capacitor) under the third light emitting element LD3. With respect to the data line DL, the second power line PL2 may shield the third light emitting element LD3 (or the anode electrode of the third light emitting element LD3).

[0160] The arrangement of the light emitting elements LD1 to LD3 shown in Fig. 9 is merely an example and is not limited to Fig. 9, and the arrangement of the light emitting elements LD1 to LD3 may be variously changed. For example, each of the light emitting elements LD1 to LD3 may be arranged on the pixel circuit of the corresponding sub-pixel.

[0161] Fig. 10 is a schematic cross-sectional view showing a comparative example of a subpixel. Fig. 10 can correspond to Fig. 7. Components similar to those in Fig. 4 are given similar reference numerals, and duplicated explanations will be omitted.

[0162] 7 and 10, the sub-pixel SPXL_C of FIG. 10 may include a first conductive pattern BML1_C, a second conductive pattern BML2_C, a second capacitor electrode CE2, a data line DL, and a first power line PL1_C.

[0163] The second conductive pattern BML2_C and the first capacitor electrode CE1, which are spaced apart with the buffer layer BFL and the second gate insulating layer GI2 interposed therebetween, may form a second capacitor Cst2_C. The first capacitor electrode CE1 and the second capacitor electrode CE2 may form a third capacitor Cst3_C. The second capacitor electrode CE2 and the second conductive pattern BML2 may be electrically connected, and the second capacitor Cst2_C and the third capacitor Cst3_C may be connected in parallel.

[0164] The first conductive pattern BML1_C may be disposed on the same layer as the second conductive pattern BML2_C. The second conductive pattern BML2_C is not shielded by the first conductive pattern BML1_C. Therefore, the second conductive pattern BML2_C (or the source node) may be coupled to the data line DL or may be affected by the signal transmission of the data line DL.

[0165] The first power supply line PL1_C is disposed on the data line DL but may not overlap the second capacitor electrode CE2. The second capacitor electrode CE2 is not shielded by the first power supply line PL1_C. Therefore, the second capacitor electrode CE2 (or source node) of the subpixel SPXL_C can be coupled to the data line DL or affected by signal transmission of the data line DL.

[0166] Compared with the subpixel SPXL_C of FIG. 10, the first subpixel SPXL1 (see FIGS. 7 and 8) according to an embodiment of the present invention has an eleventh conductive pattern BML11 disposed below the second conductive pattern BML2, thereby shielding the second conductive pattern BML2 (e.g., a source node). The twelfth conductive pattern BML12 disposed in the same layer as the eleventh conductive pattern BML11 constitutes the first sub-capacitor Cst1, thereby increasing or maximizing the capacitance of the first capacitor Cst. Furthermore, the first power supply line PL1 and the initialization power supply line INL (and the second power supply line PL2 and the reference power supply line RFL) are also disposed on the second capacitor electrode CE2, thereby shielding the second capacitor electrode CE2 (or a source node). This prevents the first transistor (or source node) from being affected (or coupled) by signal transmission of the adjacent data line DL, allowing an accurate data signal to be written and maintained between the gate electrode and source electrode of the first transistor, thereby enabling the subpixel to accurately emit light at a target brightness.

[0167] Although embodiments are disclosed and terms are used herein, they should be construed in a generic and descriptive sense only and not for purposes of limitation. In some cases, unless specifically indicated otherwise, features, characteristics, and / or elements described in connection with an embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Thus, it will be apparent to those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention.

Claims

1. a pixel electrically connected to a first power supply line, a second power supply line, and a data line; The pixel includes a first transistor and a capacitor electrically connected between a gate electrode of the first transistor and one electrode of the first transistor; On the floor plan, the data lines extend in a second direction; the first power supply line extends in a first direction intersecting the second direction and overlaps with the data line and the gate electrode of the first transistor; the second power supply line extends in the second direction, overlaps with the data line, and overlaps with the gate electrode of the first transistor.

2. The display device according to claim 1 , wherein, in a plan view, the first power supply line and the second power supply line each overlap a channel region of the first transistor.

3. The display device according to claim 2 , wherein, in a plan view, the first power supply line extends in the second direction in a region adjacent to the first transistor.

4. The display device according to claim 2 , wherein, in the plan view, the second power supply line extends in the first direction in a region adjacent to the first transistor.

5. the first power supply line and the second power supply line are electrically connected to each other; The display device of claim 1 , wherein a constant voltage is applied to the first power line and the second power line.

6. the first power supply line and the second power supply line are electrically isolated from each other; The display device of claim 1 , wherein different constant voltages are applied to the first power line and the second power line.

7. the pixel further includes a second transistor electrically connected between the data line and the gate electrode of the first transistor; The display device according to claim 1 , wherein the first power supply line and the second power supply line do not overlap the second transistor in a plan view.

8. The capacitor is a first electrode disposed in the same layer as the first power line; a second electrode disposed on the first electrode; a third electrode disposed in the same layer as the gate electrode of the first transistor; The display device according to claim 1 , further comprising: a fourth electrode disposed on the third electrode and electrically connected to the one electrode of the first transistor.

9. a first capacitor disposed between the first electrode and the second electrode; a second capacitor disposed between the second electrode and the third electrode; a third capacitor is disposed between the third electrode and the fourth electrode; The display device according to claim 8 , wherein the first capacitor, the second capacitor, and the third capacitor are electrically connected in parallel to each other to form the capacitor.

10. the third electrode is electrically connected to the first electrode through a first opening disposed in the second electrode; The display device according to claim 8 , wherein the fourth electrode is electrically connected to the second electrode through a second opening disposed in the third electrode.

11. In a plan view, the second electrode of the capacitor overlaps with a semiconductor layer of the first transistor; 9. The display device according to claim 8, wherein the second electrode of the capacitor constitutes a lower electrode of the first transistor.

12. The display device of claim 11 , wherein the pixel further comprises a hold capacitor disposed between the first power line and the second electrode of the capacitor.

13. the data line and the fourth electrode are disposed in the same layer; The display device according to claim 8 , wherein the second power supply line is disposed on the fourth electrode.

14. The pixel further includes a light-emitting element, The display device according to claim 13 , wherein the second power line is disposed between the capacitor and the anode electrode of the light-emitting element to shield the capacitor.

15. a pixel electrically connected to a first power supply line, a second power supply line, a third power supply line, and a data line; The pixel includes a first transistor and a capacitor disposed between a gate electrode of the first transistor and one electrode of the first transistor; the first power supply line extends in a first direction, and the data line, the second power supply line, and the third power supply line extend in a second direction intersecting the first direction; A display device, wherein the first power supply line, the second power supply line, and the third power supply line cover the data line and the capacitor in a plan view.

16. the second power supply line and the third power supply line are arranged in the same layer, 16. The display device according to claim 15, wherein, in a plan view, the second power supply line overlaps a part of the capacitor, and the third power supply line overlaps a remaining part of the capacitor.

17. the first power supply line and the second power supply line are electrically connected to each other; The display device of claim 16 , wherein a constant voltage is applied to the first power line and the second power line.

18. The capacitor is a first electrode disposed in the same layer as the first power line; a second electrode disposed on the first electrode; a third electrode disposed in the same layer as the gate electrode of the first transistor; The display device according to claim 15 , further comprising: a fourth electrode disposed on the third electrode and electrically connected to the one electrode of the first transistor.

19. the third electrode is electrically connected to the first electrode through a first opening disposed in the second electrode; The display device according to claim 18 , wherein the fourth electrode is electrically connected to the second electrode through a second opening disposed in the third electrode.

20. the data line and the fourth electrode are disposed in the same layer; The display device according to claim 18 , wherein the second power supply line is disposed on the fourth electrode.

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