Field emission device and manufacturing method thereof

Abstract

A method for manufacturing a field emission device is disclosed, which includes the steps of forming a primary epitaxial layer on a substrate, forming a plurality of secondary epitaxial structures on the primary epitaxial layer, forming an emitter electrode layer and a dielectric layer located on the primary epitaxial layer between the emitter electrode layer and the plurality of secondary epitaxial structures, sequentially forming a protective layer, an insulating layer, a gate electrode layer, and a planarization layer on the dielectric layer and the plurality of secondary epitaxial structures, etching the planarization layer to expose the dielectric layer and some of the gate electrode layers in some of the secondary epitaxial structures, etching and removing some of the protective layer, the insulating layer, and the exposed gate electrode layer in some of the secondary epitaxial structures to expose some of the secondary epitaxial structures, forming a gate connection electrode layer on the exposed gate electrode layer in the dielectric layer, and forming an anode facing the exposed secondary epitaxial structures and spaced a predetermined distance from the exposed secondary epitaxial structures.

Description

[Technical Field]

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a field emission device and a method for manufacturing the same. [Background technology]

[0002] Field emission devices (FEs) are vacuum transistors based on the field emission phenomenon. Their high radiation resistance and lack of scattered electron transport make them suitable for use in harsh environments and high-frequency electronic devices. Currently, silicon (Si)-based FEs are the most developed. To reduce the operating voltage of FEs, a sharp tip or a narrow gate-emitter electrode gap is generally required. III-nitride semiconductor materials offer tunable electron affinities (e.g., Al doping of GaN allows for controlled Al composition adjustment) and are easy to achieve n-type doping. This could further improve the performance of FEs and reduce their on-state voltage. First, as electron affinity decreases, electrons can tunnel more easily from the semiconductor surface into vacuum, resulting in lower operating voltages.

[0003] Currently, there is little research into III-nitride-based field emission devices, and the reported devices generally have an on-state voltage greater than 100 V. Because field emission devices typically have feature sizes smaller than 100 nm, their fabrication processes often rely on cutting-edge lithography and etching techniques, such as electron beam lithography and wet digital etching. The main problems encountered include low current density, poor device stability, high manufacturing difficulty, and poor on-chip uniformity. Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE INVENTION In order to solve the above-mentioned technical problems in the prior art, the present invention provides a field emission device and a method for manufacturing the same. [Means for solving the problem]

[0005] A method for manufacturing a field emission device according to one aspect of the present invention includes the steps of: forming a primary epitaxial layer on a substrate; forming a plurality of secondary epitaxial structures on the primary epitaxial layer, with a gap between adjacent secondary epitaxial structures; forming an emitter electrode layer on the primary epitaxial layer, and a dielectric layer positioned between the emitter electrode layer and the plurality of secondary epitaxial structures; sequentially forming a protective layer, an insulating layer, a gate electrode layer, and a planarization layer on the dielectric layer and the plurality of secondary epitaxial structures; the step of etching the dielectric layer and a part of the gate electrode layer in the part of the secondary epitaxial structure to expose the part of the secondary epitaxial structure; the step of etching and removing the protective layer, the insulating layer and a part of the exposed gate electrode layer in the part of the secondary epitaxial structure to expose the part of the secondary epitaxial structure; the step of forming a gate connection electrode layer on the exposed gate electrode layer in the dielectric layer; and the step of forming an anode facing the exposed secondary epitaxial structure and having a predetermined distance from the exposed secondary epitaxial structure.

[0006] In one example of the manufacturing method according to the above aspect, the secondary epitaxial structures are secondary epitaxial bumps arranged in an array and having a truncated cone shape or a truncated quadrangular pyramid shape.

[0007] In one example of the manufacturing method according to the above aspect, the secondary epitaxial structures are secondary epitaxial ridges arranged in sequence at intervals, with the length extending direction perpendicular to the arrangement direction.

[0008] In one example of the manufacturing method according to the above aspect, the predetermined distance is 1 to 10 mm.

[0009] In one example of the manufacturing method according to the above aspect, before forming an emitter electrode layer and a dielectric layer located between the emitter electrode layer and the plurality of secondary epitaxial structures on the primary epitaxial layer, the manufacturing method further includes a step of forming a depletion layer on the top surface and side surfaces of the secondary epitaxial structure to form a depletion region between the side surfaces and the depletion layer.

[0010] In one example of the manufacturing method according to the above aspect, before forming the primary epitaxial layer on the substrate, the manufacturing method further includes a step of forming a buffer layer on the substrate, and the epitaxial layer is formed on the buffer layer.

[0011] In one example of the manufacturing method according to the above aspect, the method for forming a plurality of secondary epitaxial structures in the primary epitaxial layer specifically includes the steps of: forming a mask layer on the primary epitaxial layer; performing a patterning process on the mask layer to form a plurality of via holes arranged in an array in the mask layer; performing secondary epitaxial growth on the primary epitaxial layer exposed by each of the via holes to form a plurality of secondary epitaxial structures; and removing the remaining mask layer.

[0012] In one example of the manufacturing method according to the above aspect, the method for forming a plurality of secondary epitaxial structures in the primary epitaxial layer specifically includes the steps of: forming a mask layer on the primary epitaxial layer; performing a patterning process on the mask layer to form a plurality of via holes in the mask layer that are arranged at intervals in sequence and whose longitudinal extension direction is perpendicular to the arrangement direction; performing secondary epitaxial growth on the primary epitaxial layer exposed by each of the via holes to form a plurality of secondary epitaxial structures; and removing the remaining mask layer.

[0013] A method for manufacturing a field emission device according to another aspect of the present invention includes the steps of: forming a laminated primary epitaxial layer and an aluminum oxide layer in this order on a substrate; forming a plurality of via holes by patterning the aluminum oxide layer; forming a plurality of secondary epitaxial structures on the primary epitaxial layer exposed by the via holes; forming an emitter electrode layer on the primary epitaxial layer, and a dielectric layer located between the emitter electrode layer and the plurality of secondary epitaxial structures; and forming an insulating layer laminated on the dielectric layer, the plurality of secondary epitaxial structures, and the remaining aluminum oxide layer. the step of etching the planarization layer to expose the dielectric layer and a portion of the gate electrode layer in the portion of the secondary epitaxial structure; the step of etching and removing the insulating layer in the portion of the secondary epitaxial structure and a portion of the exposed gate electrode layer to expose the portion of the secondary epitaxial structure; the step of forming a gate connecting electrode layer on the exposed gate electrode layer in the dielectric layer; and the step of forming an anode facing the exposed secondary epitaxial structure and having a predetermined distance from the exposed secondary epitaxial structure.

[0014] According to another aspect of the present invention, there is provided a field emission device manufactured by the above manufacturing method. [Effects of the Invention]

[0015] As a beneficial effect, the field emission device and the manufacturing method thereof of the present invention can provide device performance such as low on-state voltage and high gain. Since the primary epitaxial layer and the secondary epitaxial structure are formed by direct epitaxial deposition without etching, the on-chip uniformity of the device is improved, the production efficiency of the device is improved, and the reliability of the device is improved. [Brief explanation of the drawings]

[0016] The description of the embodiments of the present invention and other aspects, features and advantages will become more apparent from the following description taken in conjunction with the drawings. [Figure 1A] 3A to 3C are diagrams illustrating a manufacturing process of a field emission device according to an embodiment of the present invention; [Figure 1B] 3A to 3C are diagrams illustrating a manufacturing process of a field emission device according to an embodiment of the present invention; [Figure 1C] 3A to 3C are diagrams illustrating a manufacturing process of a field emission device according to an embodiment of the present invention; [Figure 1D] 3A to 3C are diagrams illustrating a manufacturing process of a field emission device according to an embodiment of the present invention; [Figure 1E] 3A to 3C are diagrams illustrating a manufacturing process of a field emission device according to an embodiment of the present invention; [Figure 1F] 3A to 3C are diagrams illustrating a manufacturing process of a field emission device according to an embodiment of the present invention; [Figure 1G] 3A to 3C are diagrams illustrating a manufacturing process of a field emission device according to an embodiment of the present invention; [Figure 1H] 3A to 3C are diagrams illustrating a manufacturing process of a field emission device according to an embodiment of the present invention; [Figure 2A] 1 is a manufacturing process diagram for fabricating a secondary epitaxial structure according to an embodiment of the present invention. [Figure 2B] 1 is a manufacturing process diagram for fabricating a secondary epitaxial structure according to an embodiment of the present invention. [Figure 2C] 1 is a manufacturing process diagram for fabricating a secondary epitaxial structure according to an embodiment of the present invention. [Figure 2D] 1 is a manufacturing process diagram for fabricating a secondary epitaxial structure according to an embodiment of the present invention. [Figure 2E] FIG. 10 is a manufacturing process diagram for fabricating a secondary epitaxial structure according to another embodiment of the present invention. [Figure 2F] FIG. 10 is a manufacturing process diagram for fabricating a secondary epitaxial structure according to another embodiment of the present invention. [Figure 2G] FIG. 10 is a manufacturing process diagram for fabricating a secondary epitaxial structure according to another embodiment of the present invention. [Figure 2H] FIG. 10 is a manufacturing process diagram for fabricating a secondary epitaxial structure according to another embodiment of the present invention. [Figure 3] FIG. 1 is a perspective view showing a configuration of a secondary epitaxial structure according to an embodiment of the present invention. [Figure 4] FIG. 10 is a perspective view showing the configuration of a secondary epitaxial structure according to another embodiment of the present invention. [Figure 5] FIG. 2 is a schematic diagram of a depletion region according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0017] Specific embodiments of the present invention will now be described in detail with reference to the drawings. However, the present invention can be embodied in many different forms, and the present invention should not be construed as being limited to the specific embodiments described herein. On the contrary, these embodiments are provided to illustrate the principles of the present invention and its practical application, thereby enabling those skilled in the art to understand various embodiments of the present invention and various modifications suitable for particular anticipated applications.

[0018] As used herein, the term "comprises" and variations thereof are open terms and mean "including, but not limited to." The terms "based on," "follows," etc. mean "based at least in part on" or "follows at least in part." The terms "one embodiment" and "an embodiment" mean "at least one embodiment." The term "another embodiment" means "at least one other embodiment." The terms "first," "second," etc. may refer to different or the same subject matter. Other definitions may be included hereinafter, whether explicitly or implicitly. Unless otherwise indicated by context, the definition of a term is consistent throughout the entire specification.

[0019] 1A to 1H are manufacturing process diagrams of a method for manufacturing a field emission device according to an embodiment of the present invention.

[0020] 1A, in manufacturing process 1, a buffer layer 2 and a primary epitaxial layer 3 are sequentially formed on a substrate 1. In other embodiments, the buffer layer 2 may be omitted, and the primary epitaxial layer 3 may be formed directly on the substrate.

[0021] Here, the buffer layer 2 may be made of GaN or AlGaN, for example, and the primary epitaxial layer 3 may be made of unintentionally doped GaN (U-GaN), for example.

[0022] As shown in FIG. 1B, in manufacturing step 2, a plurality of secondary epitaxial structures 5 are formed on the primary epitaxial layer 3, with adjacent secondary epitaxial structures 5 having a gap therebetween.

[0023] Here, the secondary epitaxial structure 5 may be manufactured using GaN or AlGaN, etc. Furthermore, the secondary epitaxial structure 5 may be N-type doped. In this embodiment, a specific formation process of the secondary epitaxial structure 5 is shown in FIGS. 2A to 2D and will be described in detail below.

[0024] 2A-2D are diagrams of a manufacturing process for fabricating a secondary epitaxial structure according to an embodiment of the present invention.

[0025] 2A, a mask layer 4 is formed on the primary epitaxial layer 3. Here, the material of the mask layer 4 may be silica (SiO2) or the like.

[0026] Next, as shown in Fig. 2B, the mask layer 4 is patterned to form a plurality of via holes 41 arranged in an array in the mask layer 4. The via holes 41 expose corresponding portions of the primary epitaxial layer 3 underneath. Here, the upper view in Fig. 2B is a side view of the patterned mask layer 4, and the lower left view and the lower right view are plan views of two different patterns of the patterned mask layer 4.

[0027] Next, as shown in FIG. 2C, a secondary epitaxial growth is performed on the primary epitaxial layer 3 exposed by each of the via holes 41, thereby forming a plurality of secondary epitaxial structures 5.

[0028] Finally, as shown in FIG. 2D, the remaining mask layer 4 is removed.

[0029] 2A to 2D are arranged in an array and are secondary epitaxial bumps in the shape of a truncated cone or a truncated pyramid (as shown in FIG. 3). In this case, the angle between the side surface of the secondary epitaxial structure 5 and the plane on which the primary epitaxial layer 3 is located may be, for example, between 58° and 60°.

[0030] 2E-2H are fabrication process diagrams for fabricating a secondary epitaxial structure according to another embodiment of the present invention.

[0031] First, as shown in Fig. 2E, a mask layer 4 is formed on the primary epitaxial layer 3. Here, the material of the mask layer 4 may be silica (SiO2) or the like.

[0032] Next, as shown in Fig. 2F, the mask layer 4 is patterned to form a plurality of via holes 42 arranged in the mask layer 4 at intervals and extending perpendicularly to the arrangement direction. The via holes 42 expose corresponding portions of the primary epitaxial layer 3 underneath. The left side of Fig. 2F is a side view of the patterned mask layer 4, and the right side is a plan view of the patterned mask layer 4.

[0033] Next, as shown in FIG. 2G, secondary epitaxial growth is performed on the primary epitaxial layer 3 exposed by each of the via holes 41 to form a plurality of secondary epitaxial structures 5'.

[0034] Finally, as shown in FIG. 2H, the remaining mask layer 4 is removed.

[0035] The secondary epitaxial structures 5′ formed by the manufacturing process of FIGS. 2E to 2H are arranged in sequence at intervals and are secondary epitaxial ridges whose longitudinal direction is perpendicular to the arrangement direction (as shown in FIG. 4). Furthermore, the cross-sectional shape of the secondary epitaxial ridges is an isosceles trapezoid.

[0036] 2D and 2H may be omitted if the material of the mask layer 4 is, for example, aluminum oxide (Al2O3). That is, the remaining mask layer 4 may be present, and the specific effects will be described below.

[0037] After completing fabrication step 2 and before fabrication step 3, the fabrication method according to the present invention further includes forming depletion layers 14 on the top and side surfaces of the secondary epitaxial structure 5, thereby forming a depletion region between the side surfaces and the depletion layer 14, as shown in FIG. 5. The depletion layer 14 may be epitaxial p-GaN. Because the epitaxial growth rate of the thin, sloped side surfaces is much faster than that of the top surface, the thickness of the p-GaN on the top surface is negligible, and its impact on device performance is minimal. By achieving the depletion regions on the side surfaces in this way, the actual size of the top surface can be further reduced, and the depletion regions formed on the side surfaces can significantly reduce the leakage current of the device.

[0038] In this embodiment, the size of the upper surface (width from left to right on the page) may be smaller than 50 nm.

[0039] As shown in FIG. 1C, in manufacturing step 3, an emitter electrode layer 6 and a dielectric layer 7 located between the emitter electrode layer 6 and the plurality of secondary epitaxial structures 5 are formed on the primary epitaxial layer 3.

[0040] Here, the emitter electrode layer 6 may be composed of a Ti / Al / Ni / Au multilayer metal layer, and the dielectric layer 7 may be composed of an aluminum layer and a silica layer laminated and coated on the aluminum layer.

[0041] As shown in FIG. 1D, in manufacturing step 4, a protective layer 8, an insulating layer 9, a gate electrode layer 10 and a planarization layer 11 are sequentially formed on the dielectric layer 7 and the plurality of secondary epitaxial structures 5.

[0042] Here, the protective layer 8 may be made of aluminum oxide, the insulating layer 9 and the planarizing layer 11 may be made of tetraethyl orthosilicate (TEOS), and the gate electrode layer 10 may be made of metallic chromium (Cr).

[0043] In another embodiment of the present invention, as described above, if the material of the mask layer 4 is, for example, aluminum oxide (Al2O3), the protective layer 8 may be omitted. In this case, in the manufacturing process 4, an insulating layer 9, a gate electrode layer 10 and a planarization layer 11 are sequentially formed on the dielectric layer 7, the plurality of secondary epitaxial structures 5 and the remaining aluminum trioxide layer 4.

[0044] As shown in FIG. 1E, in manufacturing step 5, the planarization layer 11 is etched to expose the dielectric layer 7 and a portion of the gate electrode layer 10 in a portion of the secondary epitaxial structure 5.

[0045] As shown in FIG. 1F, in manufacturing process 6, a portion of the secondary epitaxial structure 5 is exposed by etching away the protective layer 8, the insulating layer 9, and a portion of the exposed gate electrode layer 10 in the secondary epitaxial structure 5.

[0046] In another embodiment of the present invention, as described above, when the material of the mask layer 4 is, for example, aluminum oxide (Al2O3), the protective layer 8 may be omitted. In this case, in the manufacturing process 6, the insulating layer 9 in a part of the secondary epitaxial structure 5 and a part of the exposed gate electrode layer 10 are etched and removed to expose a part of the secondary epitaxial structure 5.

[0047] As shown in FIG. 1G, in manufacturing step 7, a gate connection electrode layer 12 is formed on the gate electrode layer 10 exposed in the dielectric layer 7.

[0048] Here, the gate connection electrode layer 12 may be made of a Ni / Au multilayer metal layer.

[0049] 1H, in manufacturing step 8, an anode 13 is formed facing the exposed secondary epitaxial structure 5 and having a predetermined distance therebetween. In one example, the predetermined distance d AE is 1 to 10 mm.

[0050] 1H, the anode 13 is shown hanging down, but in an actual process, the anode 13 is supported by a support member. For example, when packaging is performed, the anode 13 may be formed on an inner wall of the package that faces the members from the substrate 1 to the gate connection electrode layer 12, in order to realize an opposing arrangement of the anode 13 and the secondary epitaxial structure 5.

[0051] According to yet another embodiment of the present invention, there is further provided a field emission device manufactured by the above manufacturing method.

[0052] As described above, the field emission device and the manufacturing method thereof according to each embodiment of the present invention can provide device performance such as low on-state voltage and high gain. Since the primary epitaxial layer and the secondary epitaxial structure are formed by direct epitaxial deposition without etching, the on-chip uniformity of the device is improved, the production efficiency of the device is improved, and the reliability of the device is improved.

[0053] While specific embodiments of the present invention have been described above, other embodiments are within the scope of the following claims.

[0054] As used herein, the terms "exemplary," "example," and the like mean "serving as an example, instance, or illustration," and do not mean "preferred" or "advantageous" over other examples. For the purpose of providing an understanding of the described technology, specific embodiments include specific details. However, these technologies can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0055] Although the preferred embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the specific contents of the above embodiments, and various simple modifications can be made to the technical means of the embodiments of the present invention within the scope of the technical idea of ​​the embodiments of the present invention, and all of these simple modifications fall within the protection scope of the embodiments of the present invention.

[0056] The above description of the contents of this specification is provided to enable those skilled in the art to realize or use the contents of this specification. Various modifications made to the contents of this specification will be obvious to those skilled in the art, and the general principles defined in this specification can be applied to other variations without departing from the scope of protection of the contents of this specification. Therefore, the contents of this specification are not limited to the examples and designs described in this specification, but are accorded the widest scope consistent with the principles and novel features disclosed in this specification.

Claims

1. forming a primary epitaxial layer on a substrate; forming a plurality of secondary epitaxial structures in the primary epitaxial layer, the secondary epitaxial structures having spaces between adjacent secondary epitaxial structures; forming an emitter electrode layer on the primary epitaxial layer and a dielectric layer positioned between the emitter electrode layer and a plurality of the secondary epitaxial structures; forming a protective layer, an insulating layer, a gate electrode layer, and a planarization layer, stacked in sequence, on the dielectric layer and the plurality of secondary epitaxial structures; performing an etching process on the planarization layer to expose the dielectric layer and a portion of the gate electrode layer in a portion of the secondary epitaxial structure; etching and removing a portion of the protective layer, the insulating layer, and the exposed portion of the gate electrode layer in the portion of the secondary epitaxial structure to expose the portion of the secondary epitaxial structure; forming a gate connection electrode layer on the gate electrode layer exposed at the dielectric layer; and forming an anode facing the exposed secondary epitaxial structure and having a predetermined distance therebetween.

2. 2. The manufacturing method according to claim 1, wherein the plurality of secondary epitaxial structures are secondary epitaxial bumps arranged in an array and each having a truncated cone shape or a truncated pyramid shape.

3. 2. The manufacturing method according to claim 1, wherein the plurality of secondary epitaxial structures are arranged in sequence at intervals, and are secondary epitaxial ridges whose length extending direction is perpendicular to the arrangement direction.

4. 2. The manufacturing method according to claim 1, wherein the predetermined distance is 1 to 10 mm.

5. before forming an emitter electrode layer on the primary epitaxial layer and a dielectric layer positioned between the emitter electrode layer and the plurality of secondary epitaxial structures; 2. The method of claim 1, further comprising the step of forming a depletion layer on the top and side surfaces of the secondary epitaxial structure, thereby forming a depletion region between the side surfaces and the depletion layer.

6. Before forming the primary epitaxial layer on the substrate, 2. The method of claim 1, further comprising the step of forming a buffer layer on the substrate, wherein the epitaxial layer is formed on the buffer layer.

7. The method for forming a plurality of secondary epitaxial structures on the primary epitaxial layer specifically includes: forming a mask layer on the primary epitaxial layer; performing a patterning process on the mask layer to form a plurality of via holes arranged in an array in the mask layer; performing secondary epitaxial growth on the primary epitaxial layer exposed by each of the via holes to form a plurality of secondary epitaxial structures; 2. The method of claim 1, further comprising the step of: removing the remaining mask layer.

8. The method for forming a plurality of secondary epitaxial structures on the primary epitaxial layer specifically includes: forming a mask layer on the primary epitaxial layer; performing a patterning process on the mask layer to form a plurality of via holes arranged in an array in the mask layer; performing secondary epitaxial growth on the primary epitaxial layer exposed by each of the via holes to form a plurality of secondary epitaxial structures; 3. The method of claim 2, further comprising the step of: removing the remaining mask layer.

9. The method for forming a plurality of secondary epitaxial structures on the primary epitaxial layer specifically includes: forming a mask layer on the primary epitaxial layer; performing a patterning process on the mask layer to form a plurality of via holes in the mask layer, the via holes being arranged in a sequentially spaced relationship and having a length extending direction perpendicular to the arrangement direction; performing secondary epitaxial growth on the primary epitaxial layer exposed by each of the via holes to form a plurality of secondary epitaxial structures; 2. The method of claim 1, further comprising the step of: removing the remaining mask layer.

10. The method for forming a plurality of secondary epitaxial structures on the primary epitaxial layer specifically includes: forming a mask layer on the primary epitaxial layer; performing a patterning process on the mask layer to form a plurality of via holes in the mask layer, the via holes being arranged in a sequentially spaced relationship and having a length extending direction perpendicular to the arrangement direction; performing secondary epitaxial growth on the primary epitaxial layer exposed by each of the via holes to form a plurality of secondary epitaxial structures; and removing the remaining mask layer.

11. forming a stacked primary epitaxial layer and an aluminum oxide layer, in sequence, on a substrate; patterning the aluminum oxide layer to form a plurality of via holes; forming a plurality of secondary epitaxial structures on the primary epitaxial layer exposed by the via holes; forming an emitter electrode layer on the primary epitaxial layer and a dielectric layer positioned between the emitter electrode layer and a plurality of the secondary epitaxial structures; forming, in sequence, an insulating layer, a gate electrode layer, and a planarization layer on the dielectric layer, the plurality of secondary epitaxial structures, and the remaining aluminum oxide layer; performing an etching process on the planarization layer to expose the dielectric layer and a portion of the gate electrode layer in a portion of the secondary epitaxial structure; etching and removing a portion of the insulating layer and the exposed portion of the gate electrode layer in the portion of the secondary epitaxial structure to expose the portion of the secondary epitaxial structure; forming a gate connection electrode layer on the gate electrode layer exposed at the dielectric layer; and forming an anode facing the exposed secondary epitaxial structure and having a predetermined distance therebetween.

12. A field emission device manufactured by the manufacturing method according to claim 1.

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