Joint Timing Recovery and Decision Feedback Equalizer Adaptation in Wired Network Receivers

Abstract

A network communications receiver and method for operating the same for symbol timing recovery and equalization adaptation. A data converter (308) converts a received analog signal (AIN) to an initialization frequency (f) higher than the symbol frequency of the received signal. init ) and converts the samples into a digital sample stream. A decision feedback equalizer (320) including a digital filter (325) with one or more tap weights is applied, and an error measure (MSE) is obtained from the output of the decision feedback equalizer. In response to the error measure crossing an error threshold (ALSEnir seq), a timing loop including timing error detection (350) is initiated to adjust the phase of a sampling clock (SCLK) applied to the data converter.

Description

[Technical Field]

[0001] TECHNICAL FIELD This specification relates to establishing network communication channels, and more particularly to timing recovery and adaptive equalizer adaptation in wired network receivers. [Background technology]

[0002] In the field of network communications, a common reference model used to describe the architecture of communications protocols is the Open Systems Interconnection (OSI) layered reference model. This reference model includes a stack of abstraction layers, the "bottom layer" of which is commonly referred to as the physical layer or "PHY." The OSI physical layer defines the electrical, timing, and other interfaces through which data bits are communicated over a communications link, whether wired (e.g., Ethernet) or wireless (e.g., cellular telephony, wireless local area network, or WiFi). Communication elements such as electrical signals, signaling rates, media and connector types, and network topology are contained within the PHY abstraction layer.

[0003] From a hardware perspective, the term "PHY" refers to an electronic circuit, typically implemented as one or more integrated circuits, that implements the physical layer functions of the OSI model in a network interface controller or other network node. For example, "PHY" is often used to refer to the transceiver circuitry within a network node that transmits and receives signals to and from another network node. Within a network node, the PHY connects link layer devices (often referred to as "MAC," an abbreviation for Medium Access Control) to the physical medium, such as optical fiber or copper cable. A PHY device may include functionality at both the Physical Coding Sublayer (PCS) and the Physical Medium Dependent (PMD) layers.

[0004] In the Ethernet context, a PHY can refer to a physical layer transceiver device for transmitting and receiving Ethernet frames in accordance with the Ethernet physical layer portion of the IEEE Ethernet wired packet transmission standard applicable to a particular network, such as the 1000BASE-T (1000 Mbps), 100BASE-TX (100 Mbps over copper), and 10BASE-T (10 Mbps) standards. In these implementations, the Ethernet PHY provides physical access for analog signals on the link. Because the PHY typically does not handle MAC addressing, it interfaces with a MAC chip in a microcontroller or another system that performs higher-layer functions using a media-independent interface (MII).

[0005] In many network interface card (NIC) implementations, the Ethernet PHY is realized as an integrated circuit that implements the hardware transmission and reception of Ethernet frames and the interface between the Ethernet analog domain and the digital domain of link layer packet signaling. A NIC may combine the PHY, MAC, and other functions into a single integrated circuit, or they may be separate integrated circuits. Examples of modern Ethernet transceivers include the DP838xx, DP83TGxxx, and DP83TMxxx device families available from Texas Instruments, Incorporated.

[0006] One function of Ethernet and some other wired PHYs is called clock and data recovery. Clock recovery involves the PHY receiver deriving the symbol timing of a received signal stream from the signal stream itself. To do this, some PHY receivers include a timing loop function that detects timing errors in sampling the received signal and adjusts the phase of the sampling clock to optimize the sampling point. Clock and data recovery also typically involves the adaptation of one or more equalizers in the PHY receiver, generally including adaptive decision feedback equalizers (DFEs) to optimize compensation for the effects of channel distortions in the received signal. Such channel distortions in the Ethernet context are mostly seen as inter-symbol interference (ISI), which tends to spread to higher frequencies over time.

[0007] Timing error detection in an Ethernet PHY is typically performed according to the method described by Muller et al., "Timing Recovery in Digital Synchronous Data Receivers," Trans. on Comms., Vol. COM-24, No. 5 (IEEE, 1976), pp. 516-31, which is incorporated herein by reference. Generally, this technique involves adjusting the sampling phase to detect symbol precursor ISI (P -1 The adaptation of the DFE in the Ethernet PHY is performed to minimize the amplitude of both the pre-cursor ISI and the post-cursor ISI. [Non-Patent Document 1] Mueller et al., “Timing Recovery in Digital Synchronous Data Receivers,” Trans. on Comms., Vol. COM-24, No.5( IEEE, 1976), pp. 516-31

[0008] In connection with the examples described herein, it has been observed that timing error detection loop ("timing loop") adjustment and DFE adaptation are interconnected in that both are involved in monitoring and optimizing post-cursor ISI (P1). As a result, adjusting the sampling phase by the timing loop can cause the DFE to adapt its coefficients, or tap weights, which in turn can cause the timing loop to adjust the sampling phase again, and so on. In some situations, this dependency between the timing loop and the DFE can result in long link-up times before convergence, or else the timing loop fails to converge, or a "deadlock" condition in which the DFE converges to incorrect but stable coefficient values. These problems have been observed to occur particularly in short channels, where ISI is relatively low and therefore the timing error detection gain is low, and for certain types of modifications (e.g., MLT-3) that have relatively few symbol transitions and therefore exhibit low ISI.

[0009] It is within this context that the examples described herein occur. Summary of the Invention

[0010] According to one aspect, a method for symbol timing recovery and equalization of a signal having a symbol frequency received by a physical layer transceiver includes initially sampling with a sampling clock at a frequency greater than the symbol frequency, converting the sampled signal to a digital sample stream, and equalizing the digital sample stream with a decision feedback equalizer to generate an output digital stream. The method further includes adapting at least one tap weight of the decision feedback equalizer and calculating an error measurement from the output sample stream. The phase of the sampling clock is adjusted in response to the error measurement crossing an error threshold.

[0011] According to another aspect, a network communications receiver has an input for receiving an analog signal having a symbol frequency and a data converter for sampling the analog signal in response to a sampling clock signal and converting the sampled signal into a digital sample stream. Clock generation circuitry is configured to generate the sampling clock signal at a phase responsive to a clock control signal generated by clock control circuitry in digital receiver circuitry of the receiver. The digital receiver circuitry has an input coupled to receive the digital sample stream from the data converter and further includes a decision feedback equalizer including a digital filter with one or more tap weights that generates an output digital stream from the digital sample stream. The digital receiver circuitry also includes error measurement circuitry that measures an error in samples of the output sample stream and clock control circuitry configured to generate a clock control signal to the clock generation circuitry. Sequencer logic controls operation of the circuitry to control the clock generation circuitry to generate the sampling clock signal at an initialization frequency above the symbol frequency, adapt at least one tap weight of the decision feedback equalizer, and calculate an error measurement from the output sample stream. In response to the error measurement crossing an error threshold, the clock control signal adjusts the phase of the sampling clock.

[0012] Technical advantages enabled by one or more of these aspects include rapid and accurate joint convergence of equalization and sample timing in a network receiver, even in implementations where the equalization and timing loops are interdependent.

[0013] Other technical advantages enabled by the presently described embodiments will become apparent to those skilled in the art by reference to the following description taken in conjunction with the drawings. [Brief explanation of the drawings]

[0014] [Figure 1]FIG. 2 is an electrical diagram in block form of a network node constructed in accordance with some examples.

[0015] [Figure 2] 1 is an electrical schematic diagram in block form of a physical layer transceiver (PHY) constructed in accordance with some examples.

[0016] [Figure 3A] 3 is an electrical diagram in block form of circuit elements in the receive path of the PHY of FIG. 2, according to some examples.

[0017] [Figure 3B] 3B is an electrical circuit diagram in block form of a decision feedback equalizer according to the example of FIG. 3A.

[0018] [Figure 3C] FIG. 3B is an electrical schematic diagram in block form of error calculation circuitry according to the example of FIG. 3A.

[0019] [Figure 4] 3B is a flowchart illustrating the operation of the receive path according to the example of FIG. 3A.

[0020] [Figure 5A] 5 is a plot of decision feedback equalizer coefficient values ​​during adaptation in an example of operation according to the example of FIG. 4.

[0021] [Figure 5B] 5 is a plot of mean squared error during adaptation in operation according to the example of FIG. 4;

[0022] [Figure 6A] 3 is an electrical diagram, in block form, of circuit elements in the receive path of the PHY of FIG. 2 according to another example.

[0023] [Figure 6B] 6B is an electrical schematic diagram, in block form, of error calculation circuitry in the receive path circuitry according to the example of FIG. 6A.

[0024] [Figure 7] 6B is a flowchart illustrating the operation of receive path circuitry according to the example of FIG. 6A.

[0025] The same reference numerals or other reference designators are used to illustrate identical or similar features (in function and / or structure). DETAILED DESCRIPTION OF THE INVENTION

[0026] One or more examples described herein are described as being implemented in a physical layer transceiver device in a high-speed Ethernet-type network because such implementation is contemplated to be particularly advantageous in such applications. However, it is contemplated that aspects of these examples may be beneficially applied in other applications, for example, in connection with other wired network technologies. Accordingly, the following description is provided by way of example only and does not limit the true scope of the invention as claimed.

[0027] 1 illustrates an example of a network node 100 in which some examples may be implemented. Network node 100 may be implemented as any of a number of network functions, such as a computing device in either or both roles of a network server or client, a peripheral device such as an input / output function, a sensor or controller, a router, a switch, or another network function. Network node 100 is coupled to a network communication medium 102 over which it receives and transmits data and control information. In this particular example, in which network communications occur over an Ethernet network, network communication medium 102 is implemented as CAT6 copper cabling or the like. In other implementations, network communication medium 102 may be implemented as optical fiber or the like.

[0028] In the example of FIG. 1 , network node 100 includes an Ethernet physical layer transceiver (PHY) 106 constructed in accordance with an example. For an example in which network communication medium 102 is a copper wired Ethernet connection, PHY 106 is coupled to medium 102 by a magnetic coupling interface 104. Magnetic coupling interface 104 is provided to galvanically isolate medium 102 from PHY 106 while providing a signal path. For example, magnetic coupling interface 104 may be implemented as a separate Ethernet magnetic module provided with a connector jack in the signal path to PHY 106 for physically coupling to network communication medium 102. Alternatively, magnetic coupling interface 104 may be integrated into the same housing or package as the Ethernet connector jack. In either case, interface 122 between PHY 106 and magnetic coupling interface 104 in this implementation is referred to in the Ethernet context as a medium dependent interface (MDI), in that its specifications depend on the particular medium used for network communication medium 102.

[0029] The Ethernet PHY 106 in this example includes appropriate circuitry for transmitting and receiving data and control information between upstream functions and the network communication medium 102. In the context of Ethernet, the PHY 106 receives digital data in the form of Ethernet frames from a medium access controller (MAC) 108 and generates analog signals corresponding to these frames for transmission over the medium 102. In its receive function, the PHY 106 processes the analog signals received over the medium 102, digitizing and formatting the digital data into Ethernet frames for consumption and processing by the MAC 108 and further upstream functions for these signals representing data to the network node 100. In this manner, the PHY 106 acts as an interface between the Ethernet analog domain of the medium 102 and the digital domain of link layer packet signaling for the network node 100, as implemented by the MAC 108. The construction and operation of the PHY 106 according to several examples is described in further detail below.

[0030] According to this example, PHY 106 is coupled to MAC 108 by interface 124, which in this implementation, in the Ethernet context, is referred to as a Media Independent Interface (MII) or Reduced Gigabit Media Independent Interface (RGMII) in that the interface's specifications are independent of the physical implementation of the network communication medium 102. Media Access Controller (MAC) 108 in network node 100 includes appropriate circuitry for processing data received from the network via PHY 106 and communicated to PHY 106 for transmission. This processing may include, for example, managing frame buffering in both the transmit and receive directions, packet formatting and recognition, timer functions, and other operations involved in the Data Link Layer or MAC Layer portions of the OSI model. MAC 108 may be integrated with a processor, a field-programmable gate array (FPGA), digital circuitry, memory, an application-specific integrated circuit (ASIC), software, or a combination thereof. The MAC 108 may be implemented within the same integrated circuit as the PHY 106 and the MII interface 124 or as one or more integrated circuits separate from the PHY 106 .

[0031] 1, network node processor 110 is coupled to MAC 108 via interface 126. Network node processor 110 provides data processing and control capabilities appropriate to perform the functions of network node 100 within the network. Network node processor 110 may be implemented as a microprocessor, microcontroller, FPGA or other switch fabric, and / or other circuit elements appropriate for that function. Network node processor 110 may be implemented within the same integrated circuit as MAC 108 or as one or more separate integrated circuits.

[0032] 2 illustrates the architecture of PHY 106 according to one example. As described above, PHY 106 has the general function of interfacing communications between the Ethernet analog domain of network communication medium 102 and the digital domain of link layer packet signaling for network node 100, as implemented by MAC 108. Thus, PHY 106 in this example includes MII interface circuitry 200 through which digital signals processed by or to be processed by PHY 106 are communicated to or received by MAC 108, respectively, via interface 124, in accordance with the appropriate RGMII or MII protocol. In the latter case, MAC 108, PHY 106, and magnetic coupling interface 104 may be implemented in a network interface card (NIC) to which network processor 110 is coupled via interface 126.

[0033] For processing digital data communicated to and received from MAC 108, PHY 106 includes one or more communication processing blocks. In this example, PHY 106 includes a transmit processing block 202TX for processing data received from upstream functions in network node 100 for transmission from PHY 106 to the network, and a receive processing block 202RX for processing data received from the network for forwarding to upstream functions in network node 100. In this example, where PHY 106 is operable to process communications according to any of three Ethernet industrial protocols, processing blocks 202TX, 202RX (collectively or individually referred to as "processing blocks 202") may each include a 100BASE-TX processing block, a 10BASE-Te processing block, and a 1000BASE-T processing block. Alternatively, if network node 100 is implemented in the context of an in-vehicle network, processing block 202 of PHY 106 may be configured to process communications according to the applicable automotive Ethernet protocol. The processing blocks 202TX, 202RX are each coupled on one side to the MII interface circuitry 200 and on the other side to the hybrid block 210 for communication with the network communication medium 102 via the magnetic coupling interface 104. The processing blocks 202TX, 202RX each include digital logic circuitry (or other circuitry, memory, and / or software) configured and operable to process digital data appropriately for the particular protocol involved. For example, the digital logic circuitry included in the processing blocks 202TX, 202RX may be implemented at least in part in a digital signal processor, as a stand-alone processor, or embedded in a larger integrated circuit, and / or as sequencer logic in the form of one or more state machines. The PHY control block 208 includes appropriate logic and configuration registers for controlling the processing blocks 202TX, 202RX and other functions of the PHY 106 to operate in a selected one of several operating modes.

[0034] In the Ethernet context of this example, the digital logic circuit elements in processing blocks 202TX, 202RX are configured to implement one or more sublayers in the applicable Ethernet protocol, such as one or more of the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA) sublayer, and Physical Medium Dependent (PMD) sublayer (in order from the MII side to the Ethernet media side), depending on the mode of operation (e.g., 100BASE-TX, 10BASE-Te, and 1000BASE-T).

[0035] In this implementation, the hybrid block 210 is configured and operable to convert signals between the digital domain of the processing blocks 202TX, 202RX and the analog domain (for communication over the network communication medium 102). As such, the converter block 210 includes driver and receiver circuitry coupled to the magnetic coupling interface 104, as well as digital-to-analog (DAC) and analog-to-digital (ADC) conversion functionality. The circuitry and functionality of the hybrid block 210 involved in transmitting digital data to the network communication medium 102, including, for example, a DAC for converting digital data from the transmit processing block 202TX to the analog domain using appropriate filters and amplifiers, is illustrated in FIG. 2 by the transmit subsystem block 214. For receiving signals from the network communication medium 102, the hybrid block 210 includes a receiver analog front end (AFE) 216. The AFE 216 includes appropriate circuitry involved in receiving analog signals from the medium 102 and converting those received signals into digital data and control symbols for communication to the receiving processing block 202RX under an operating protocol. In this regard, as described in more detail below, AFE 216 may include analog filters, level shifters, one or more programmable gain amplifiers, ADC functionality, and other circuit elements for performing these operations.

[0036] PHY 106 also includes clock generation circuitry 220, which in this example is constructed and operable to provide appropriate clock signals to hybrid block 210, and for purposes of the examples described herein, specifically to receiver AFE 216. Clock generation circuitry 220 may generate these clocks based on a received master clock signal (e.g., from a crystal oscillator or bulk acoustic wave device external to PHY 106 and coupled at terminal REFCLK) or based on a master clock signal generated external to or within PHY 106. Clock generation circuitry 220 may also receive control signals from receive processing block 202RX and / or PHY control block 208, as shown in FIG. 2.

[0037] Certain additional functionality is also provided in PHY 106 in accordance with this example. As noted above, and as shown in FIG. 2, PHY 106 includes PHY control block 208, which includes management and control circuitry constructed and operable to perform appropriate operations for controlling PHY 106 as an integrated circuit device, including reset, interrupt generation and handling, circuitry for receiving and communicating status and control information from external circuitry, etc. For example, MII registers 222 may be provided to store configuration and status information related to MII interface 200 and communications with upstream functions. Other functionality not shown in FIG. 2 may also be provided in PHY 106, including power management, "Wake on LAN" circuitry, auto-negotiation circuitry, etc.

[0038] 3A illustrates example circuitry in the receive path of PHY 106, including AFE 216, clock generation circuitry 220, and a portion of receive processing block 202RX, according to some examples. AFE 216 includes an analog high-pass filter 302 having an input coupled to interface 122 for receiving an input signal from network communication facility 102 via magnetic coupling interface 104. The output of high-pass filter 302 is coupled to a programmable gain amplifier 304 and an analog low-pass filter 306, the output of which is coupled to an input of ADC 308. In this example, high-pass filter 302 and low-pass filter 306 provide signal conditioning to the signal received from interface 122, and programmable gain amplifier (PGA) 304 applies automatic gain control (AGC) to the conditioned input signal.

[0039] The ADC 308 samples the conditioned and amplified analog signal at the phase and frequency of a sampling clock SCLK from the clock generation circuitry 220 and converts each sample of the signal into a digital symbol. In this implementation in the Ethernet PHY 106, the sampling rate of the ADC 308 is one sample per symbol (1 Sps), and thus the frequency of the sampling clock SCLK is at the symbol rate of the received analog signal. This symbol frequency may be set by an applicable standard (e.g., IEEE Standard 802.3ab for "Gigabit Ethernet"), negotiated between the network node 100 and the connected network, or otherwise communicated to the PHY 106 and applied to the clock generation circuitry 220. The phase of the sampling clock SCLK within each symbol period is controlled and adjusted by the clock generation circuitry 220 in response to observed signal quality, for example, as described below. The symbol stream generated by the ADC 308 in the AFE 216 is forwarded to the receive processing block 202RX.

[0040] 3A illustrates the architecture of symbol timing recovery and equalization circuitry 300, which forms part of the circuitry of receive processing block 202RX. In particular, symbol timing recovery and equalization circuitry 300 illustrated in FIG. 3A operates as part of the clock and data recovery operation performed on the symbol stream from AFE 216, along with adaptation for equalization of the symbol timing recovery operation from the symbol stream generated by AFE 216. The symbol timing recovery and equalization circuitry of FIG. 3A may be implemented as a digital signal processor (DSP) integrated as an embedded processor in a single integrated circuit with other circuitry of PHY 106, as a standalone processor, or as programmable or hardwired custom, semi-custom, application-specific, or other logic circuitry, etc.

[0041] 3A, the symbol stream received from AFE 216 is applied to a digital automatic gain control (AGC) function 310, which dynamically adjusts the gain applied to the received symbol stream in a conventional manner. In this example, a feed-forward equalizer (FFE) 312 receives the output of AGC function 310 and operates as a preset (e.g., non-adaptive) equalizer filter. The coefficients or tap weights of FFE 312 are set by a channel AGC function 314, which derives a coarse channel estimate from the symbol stream received from AFE 216.

[0042] After amplification by AGC 310 and equalization by FFE 312, the received symbol stream, according to this example, is applied to decision feedback equalizer (DFE) 320. In this implementation, DFE 320 is an adaptive equalizer whose coefficients or tap weights (such terms are used interchangeably in this description) are dynamically adapted to reduce residual post-cursor ISI from the symbol stream.

[0043] 3A, DFE 320 can be thought of as a summer function 322 having one input that receives the symbol stream from the output of FFE 312 and a second input that receives a feedback signal, which summer 322 subtracts from the symbol stream and outputs the remainder as residual samples x(n) to decision slicer 324. Slicer 324 quantizes the residual samples from summer 322 to generate output symbols x(n) for processing by other circuit elements in receive processing block 302RX before forwarding them to upstream functions in network node 100. The digital filter 325 generates the output symbols from the slicer 324. A digital filter function is applied to TIFF2025531505000003.tif814 to generate feedback, which is subtracted from the input symbol stream by summer 322. In a general sense for this exemplary implementation, digital filter 325 is adapted such that the feedback signal applied to summer 322 removes one or more residual post-cursors to compensate for ISI resulting from channel distortion.

[0044] 3B illustrates the configuration of DFE 320, with digital filter 325 shown in more detail. In this example, digital filter 325 includes one or more delay stages 326 connected in series, with the output of each delay stage 326 being fed to a corresponding one of multipliers 327 with tap weight w k and the resulting products are summed in summer 328 to generate a feedback signal that is applied as a subtrahend to summer 322. Adaptation logic 329 is provided to DFE 320 (or anywhere else in DSP 300) to adjust the tap weights w applied by multiplier 327 according to an adaptive formula. k For example, the adaptation logic 329 adapts the m tap weights w in the example of FIG. k Each of the variables may be adapted according to the recursive least squares method: where n and n-1 are the indices of the nth and (n-1)th samples, respectively, in the digital symbol stream processed by DFE 320, μ is a learning constant between 0 and 1, TIFF2025531505000005.tif1018 refers to the output of slicer 324 for the (n-1)th sample, and err refers to the sample x(n) at the input of slicer 324 and the slicer output for that nth sample. This represents the difference between TIFF2025531505000006.tif812. The number of tap weights m in digital filter 325, and therefore the order of digital filter 325, can vary according to the particular implementation. The adaptive logic 329 adjusts the tap weight w after each sample. k may operate to adapt

[0045] DFE 320 may alternatively be implemented according to any approach to decision feedback equalizer.

[0046] The symbol timing recovery and equalization circuitry 300 according to the example architecture of FIG. 3A also extracts a symbol stream from the output of the slicer 324. JPEG2025531505000008.jpg34 and an input that receives the residual samples x(n) from summer 322 at the input of slicer 324, and calculates an error measure based on these samples. This error measure is a measure of noise, including ISI, in slicer 324. For example, MSE calculation circuitry 340 may calculate a mean squared error measure MSE according to the following equation: TIFF2025531505000009.tif9114 where the sum in equation (3) corresponds to a weighted sum of squared differences obtained over a preselected number of samples, for example over a sliding window of samples in the symbol stream.

[0047] 3A, timing error detection (TED) circuitry 350 is also included in this example in symbol timing recovery and equalization circuitry 300. TED circuitry 300 receives residual samples x(n) and a symbol stream x(n) from the input and output of slicer 324, respectively. TIFF2025531505000010.tif813 and includes logic and memory circuitry configured to generate a timing error signal ted indicative of an estimated error in the phase of a sampling clock SCLK applied to the ADC 308 relative to an optimal point in time within a symbol period. The TED circuitry 350 may generate the timing error signal ted, for example, according to the techniques described in the above-incorporated Muller et al. publication. According to this technique, the timing error signal ted is calculated by the TED circuitry according to: TIFF2025531505000011.tif9123The first term on the right hand side of equation (4) corresponds to the first ISI post-cursor P1, and the second term corresponds to the first ISI precursor P -1 Corresponds to.

[0048] The symbol timing recovery and equalization circuitry 300 according to this example, in conjunction with the clock generation circuitry 220, implements a timing loop configured to adjust the phase of the sampling clock SCLK in response to a timing error detected by the TED circuitry 350. In this example, the timing loop operates to adjust the sampling phase to minimize the timing error signal ted generated by the TED circuitry 350. As shown in FIG. 3A, the timing error signal ted is applied to a loop filter 352, which is a digital filter that applies a transfer function with appropriate response and stability for adjusting the sampling phase, and the filtered error signal is applied to one input of a summer 354. The output of the summer 354 is the combination of the filtered timing error signal ted and an initialization frequency f initand applied to a numerically controlled oscillator (NCO) 356 which, in response to the output of summer 354, generates a control signal UP / DN for application to clock generation circuitry 220.

[0049] 3A, clock generation circuit element 220 includes a phase-locked loop (LLP) 360. PLL 360 generates a clock signal based on a reference clock REFCLK, which may be a reference clock signal generated external to clock generation circuit element 220. Alternatively, clock generation circuit element 220 may include an oscillator that generates reference clock REFCLK based on an external clock reference, such as a crystal oscillator. PLL 360 applies its output clock to a phase interpolator (PI) 362, which receives a control signal UP / DN from NC 356 in symbol timing recovery and equalization circuit element 300 and generates a sampling clock SCLK in response.

[0050] In this example, PI 362 is configured to advance the phase of sampling clock SCLK in response to an "up" pulse on control signal UP / DN, and to delay the phase of sampling clock SCLK in response to a "down" pulse on control signal UP / DN. TED circuitry 350, in turn, along with loop filter 352, summer 354, and NCO 356, determines when timing error signal ted indicates that the current sampling phase is lagging behind the optimal point (e.g., when post-cursor P1 is lagging behind precursor P2). -1 Conversely, the NCO 356 is configured to issue an "up" pulse in the control signal UP / DN in response to the timing error signal ted indicating that the current sampling phase is ahead of the optimum point (e.g., post-cursor P1 is ahead of precursor P2). -1, ted is negative (because ted is less than 0.001), the timing loop of symbol timing recovery and equalization circuitry 300 therefore operates to minimize the amplitude of timing error signal ted.

[0051] Continually adjusting (advancing or retarding) the phase of the sampling clock SCLK in the same direction over multiple sampling periods can have the effect of adjusting the frequency of the sampling clock SCLK. As such, the phase adjustments or adjustments described herein can also be considered as frequency adjustments or adjustments of the sampling clock SCLK.

[0052] 3A is controlled by sequencer logic 330. Sequencer logic 330 may be implemented as programmable or hardwired sequencer logic and is configured to enable the functions of symbol timing recovery and equalization circuitry 300 to perform the desired operation of various functions, including DFE 320, MSE calculation circuitry 340, and TED circuitry 350. In particular, according to this example, a mean squared error signal MSE from MSE calculation circuitry 340 is applied to sequencer logic 330, which in response issues a control signal TLOOP_STRT to TED circuitry 350 to initiate operation of the timing loop of symbol timing recovery and equalization circuitry 300.

[0053] 3C illustrates, according to an example, the implementation of MSE computation circuitry 340 and related functionality, such as may be included in sequencer logic 330. MSE computation circuitry 340 has one input that receives one residual sample x(n) at the input of slicer 324, and one symbol stream from the output of slicer 324. and another input that receives TIFF2025531505000012.tif713. The adder 370 calculates for each sample the slicer output symbol TIFF2025531505000013.tif713 is subtracted from the residual x(n) and the resulting difference is provided to a squaring function 372, which calculates the squared error for each sample TIFF2025531505000014.tif840. The squared error from squaring function 372 is forwarded to the input of infinite impulse response (IIR) filter 374, which generates an error measure MSE from a weighted sum of the squared error calculations over a sliding window of one or more samples.

[0054] The error measure MSE as output by the MSE calculation circuitry 340 is the minimum MSE of the error measures MSE generated by the MSE calculation circuitry 340 min and maximum MSE max The minimum error value MSE is forwarded to min / max estimation logic 380, which is implemented as logic circuit elements or functionality configured to identify the minimum error value MSE. min and maximum error value MSE max 3C is forwarded to MSE monitoring logic 382. MSE monitoring logic 382 also receives the error measure MSE from MSE calculation circuitry 340. MSE monitoring logic 382 calculates the error measure MSE as a function of the minimum error value MSE min or in some implementations, the minimum error value MSE min Together with the maximum error value MSE max is configured to monitor via the sample stream against a threshold determined by the MSE monitoring logic 382 based on the error measure MSE. Based on monitoring the error measure MSE, the MSE monitoring logic 382 is further configured to initiate operation of the timing loop by generating a start signal TLOOP_STRT to the TED circuit element 350.

[0055] 3A, min / max estimation logic 380 and MSE monitoring logic 382 are shown as being contained within sequencer logic 330. Alternatively, these logic functions and circuit elements may be incorporated within MSE calculation circuit element 340 itself, or elsewhere within symbol timing recovery and equalizer circuit element 300, as appropriate for a particular implementation.

[0056] 4, the operation of the receive path of PHY 106, including AFE 216, clock generation circuitry 220, and symbol timing recovery and equalizer circuitry 300 according to the architecture of FIG. 3A, will be described in connection with an example. According to this approach, the initiation of a timing loop for adjusting the phase of sampling clock SCLK is controlled to occur when DFE 320 converges to a low error condition to facilitate the cooperative convergence of sampling timing and receive path equalization.

[0057] Operation begins with the receive path in an idle state, as indicated by state 400 in Figure 4. Upon powering up the PHY 106 for receipt of an incoming communication from the network, process 402 is first performed to set the gain of the programmable gain amplifier 304 in the AFE 216, followed by process 404 to set the digital AGC 310 based on measurements of the channel conditions by the CAGC 314. The tap weights within the FFE 312 in the symbol timing recovery and equalization circuitry 300 may also be set in process 404 if not pre-selected or otherwise established.

[0058] In process 406, the sequencer logic 330 in the symbol timing recovery and equalization circuitry 300 sets the frequency of the sampling clock SCLK to an initialized frequency f init Initialize to the initialization frequency f initis selected to be slightly higher than the symbol frequency of the signal received at AFE 216 from the network, e.g., a frequency set according to some network standard. In the example of "Gigabit Ethernet" over copper wireline, operating according to IEEE standard 802.3ab for the physical layer, the symbol frequency is at a nominal frequency of 125 MHz, with a tolerance of ±200 ppm. In that example, the initialization frequency f init may be set to a frequency slightly higher than the tolerance band, for example, +400 ppm from the nominal frequency of 125 MHz, and the initialization frequency f init 3A, process 406 ensures that sequencer logic 330 supplies an appropriate initialization frequency signal f to adder 354. init In response, adder 354 controls NCO 356 to issue the appropriate "up" pulse of control signal UP / DN to phase interpolator 362 in clock generation circuitry 220. init , phase interpolator 362 advances the phase of sampling clock SCLK in each sample period, resulting in a sampling frequency slightly higher than the symbol frequency of the received signal. The timing loop including TED circuitry 350 is disabled or in some other manner inoperative at this point, and causes clock generation circuitry 220 to advance the phase of sampling clock SCLK in each symbol period to the initialization frequency f init As a result, the sampling points advance with each symbol period, eventually wrapping around periodically over the symbol interval.

[0059] In process 406, the initialization frequency f init After being set, in process 408, the coefficients of the DFE 320 are adjusted to the initialization frequency f init For example, the operation and adaptation process 408 may be adapted over multiple samples obtained from a signal received at a higher initialization frequency f initcontinues at least once, and preferably more than once, for a number of sample periods sufficient to complete one symbol interval. Figure 5A illustrates the behavior of adaptation process 408 for an example implementation in which digital filter 325 is second order and adapts two tap weights w1 and w2. As shown in Figure 5A for this example, after process 408 has been performed for approximately 4600 samples, the values ​​of tap weights w1 and w2 are adjusted to the initialization frequency f init The phase of the sampling clock SCLK at the initialization frequency f init is at least about 200 ppm higher than the symbol frequency of the received signal.

[0060] In process 410, MSE calculation circuitry 340 in symbol timing recovery and equalization circuitry 300 calculates and monitors the error measure MSE from the output of DFE 320. The MSE monitoring process 410 may begin with the first sample obtained in process 408, or may begin later in process 408, recognizing that DFE 320 typically does not adapt well early on. As shown in the example of FIG. 5A, as the values ​​of tap weights w1 and w2 oscillate, the initialization frequency f init The error measure MSE oscillates as the phase of the sampling clock SCLK at cycles through a symbol interval. Figure 5B illustrates an example of the calculation of the error measure MSE in process 410 during operation and adaptation process 410. In this example, the error measure MSE has a local minimum at approximately 4600 samples, with deeper local minima occurring at approximately 5600 samples, 6400 samples, 7200 samples, etc.

[0061] Process 410 in the method of FIG. 4 further comprises a threshold error measure MSE thr In the example of FIGS. 3A-3C, the error measurement threshold MSE in process 410 is determined. thr is determined by measuring at least the minimum error measure MSE observed by min / max estimation logic 380 via samples processed during adaptation of DFE 320 in process 408.min For example, the error measurement threshold MSE is implemented by the MSE monitoring logic 382 of the sequencer logic 330 based on thr is the minimum error measure MSE observed over multiple samples min may be calculated by adding the difference Δ from the minimum value to the thr =MSE min +Δ). The difference Δ can be a fixed value or can be calculated as the minimum error measure MSE observed during the adaptation of the DFE 320, as follows: min and the maximum error measure MSE max It may be based on the difference between TIFF2025531505000015.tif8120 where δ is the selected fraction.

[0062] Error measurement threshold MSE in process 410 thr Following this determination, the MSE monitoring logic 382 continues to monitor the error measure MSE each time the symbol timing recovery and equalization circuitry 300 receives an additional input symbol. During this monitoring, in decision 411, the MSE monitoring logic 382 determines whether the most recent error measure MSE(n) is greater than or equal to the error measure threshold MSE determined in process 410. thr If not (decision 411 is "no"), the DFE 320 is again adapted based on that symbol and monitoring continues.

[0063] The error measurement value MSE(n) is the error measurement threshold MSE thr , (decision 411 returns "yes"), sequencer logic 330 initiates operation of the timing loop, e.g., by MSE monitor logic 382 issuing a control signal TLOOP_START to TED circuit element 350 in the example architecture of FIG. 3A. In response to control signal TLOOP_START, TED circuit element 350 operates to generate timing error signal ted. In the example implementation of FIGS. 3A-3C, timing error signal ted is derived from residual samples x(n) and symbol streams from the input and output, respectively, of slicer 324 of DFE 320, e.g., according to equation (4) above. TIFF2025531505000016.tif713. The timing loop operation of TED circuitry 350, loop filter 352, summer 354, NCO 356, and PI 362 may adjust the phase of sampling clock SCLK, first coarsely and then finely, in response to timing error signal ted to achieve faster convergence. As shown in FIG. 4 , a coarse adjustment of the sampling phase is first performed in process 414, followed by a fine adjustment of the sampling phase in process 416. Continuous adaptation of DFE 320 may be performed cooperatively with the timing loop adjustments in processes 414, 416 as needed, given that the error measure MSE is near a minimum at this point in the process.

[0064] Following the fine tuning of the timing loop in process 416 , steady-state operation of the receive path of PHY 106 , including AFE 216 and symbol timing recovery and equalization circuitry 300 , occurs in state 420 .

[0065] Following this example, joint convergence of equalization and sample timing in a network receiver is achieved quickly and accurately, even in implementations where the equalization and timing loops are interdependent. This convergence is achieved by using a higher initialization frequency f init This is achieved by applying the Δt(t) value during equalizer adaptation to identify equalizer tap weights that result in a relatively low error and starting the timing loop with the equalizer in that low error condition. In other words, the sampling phase adjustment begins at a point when the equalizer is close to convergence on the correct coefficient values, which reduces the time required for the timing loop to converge as well as the precision in that convergence.

[0066] According to an alternative example, the periodicity of the oscillation error measurement as the phase of the sampling clock cycles through the symbol interval of the input analog signal is used to provide an initial phase adjustment at the start of the timing loop adjustment. As shown in FIG. 5B, the ADC 308 clocks the received signal at an initialization frequency f init The oscillation error measurement MSE obtained while sampling at period T MSEIn relation to these examples, the initialization frequency f init and the frequency offset f between the symbol frequency of the input signal received from the network. delta is used to derive the initial phase correction for the sampling clock. MSE It has been observed that the periodicity in

[0067] FIG. 6A illustrates the architecture of certain circuit elements in the receive path of PHY 106 according to this alternative example. In FIG. 6A, the same reference numerals are used to illustrate the same or similar features or functions shown in the configuration of FIG. 3A, and the above descriptions of those same features and functions also pertain to the implementation of FIG. 6A. In this alternative implementation, symbol timing recovery and equalization circuitry 600 of FIG. 6A performs a symbol timing recovery operation from the symbol stream generated by AFE 216, along with adaptation for equalization, as part of the clock and data recovery operation performed on the symbol stream from AFE 216. As in the architecture of FIG. 3A, symbol timing recovery and equalization circuitry 600 forms part of the circuitry in receive processing block 202RX of PHY 106, which in turn may be implemented as an embedded or stand-alone processor, or as programmable or hardwired custom, semi-custom, application-specific, or other logic circuitry.

[0068] The digitized symbol stream produced by AFE 216 and applied to digital AGC function 310 and FFE 312 is then applied to DFE 620. DFE 620 in this alternative implementation is configured similarly to DFE 320 described above, but in this example, its primary tap weight w1 (tap 625a) is scaled to include higher tap weights w2 through w m (tap 625b) is configured to allow selective adaptation.

[0069] Each of the TED circuitry 350, loop filter 352, and NCO 356 in timing loop symbol timing recovery and equalization circuitry 600 according to this alternative implementation is constructed and configured similarly to those described above with respect to Figure 3A. Sequencer logic 630 is configured similarly to sequencer logic 330 described above, and thus includes MSE monitoring logic for monitoring the error measure MSE as produced by MSE calculation circuitry 640. However, according to the alternative implementation of Figure 6A, MSE calculation circuitry 640 is configured differently than MSE calculation circuitry 340 described above.

[0070] 6B illustrates the configuration of MSE computation circuitry 640 in an example implementation of symbol timing recovery and equalization circuitry 600. MSE computation circuitry 640 includes a summer 670 whose input is coupled to DFE 620 to compute the residual samples x(n) and the symbol stream at the input and output of slicer 624 in DFE 620. TIFF2025531505000017.tif713. The adder 670 receives each symbol TIFF2025531505000018.tif713 from the corresponding residual x(n) and provide the difference to squaring function 672. Squaring function 672 outputs the squared difference from summer 670 for application to IIR 674, which generates an error measure MSE as a weighted sum of the squared differences over a sliding window of sample periods. The error measure MSE for each sample is forwarded to MSE monitoring logic in sequencer logic 630, as described above.

[0071] 6B, MSE calculation circuit element 640 also includes min / max estimation logic 680, a counter 682, and a look-up table (LUT) 684. Alternatively, some or all of min / max estimation logic 680, counter 682, and LUT 684 may be implemented in sequencer logic 630, or may be implemented in separate logic or other circuit elements included in symbol timing recovery and equalization circuit element 600.

[0072] The min / max estimation logic 680 in this example is implemented as logic circuit elements or functionality configured to identify some measure of error from the value of the error measure MSE. In this example, the min / max estimation logic 680 is implemented as an error measure threshold MSE Thr_seq and configured to calculate an error measurement threshold Thr_seq The timing loop is started based on the minimum error measure MSE min and maximum error measure MSE max The median error MSE corresponding to the arithmetic mean of mid The error measurement threshold MSE is generated. Thr_seq is forwarded to the sequencer logic 630 in this implementation (FIG. 6A) and the midpoint error value MSE mid is transferred to a counter 682 in the MSE calculation circuit element 640. The counter 682 also receives the error measure MSE at an input.

[0073] Counter 682 in this example counts, for example, the cycles of the clock signal between midpoint crossings and transfers the count or time measurement to LUT 684 to generate a midpoint error value MSE mid In this implementation, the LUT 684 is operable to measure the time between crossings of the frequency offset f delta A memory resource that stores a mapping of count values ​​corresponding to the period of error measurement to values ​​of .times. ... θ=2π(f delta T SYM ) (6) where θ is the frequency offset f delta The sample period T obtained from SYM Therefore, the frequency offset f delta Correcting for the phase offset in can place the sampling clock at the correct frequency to coincide with the symbol period. In this example, the count output by counter 682 is applied as an address to LUT 684, which in response matches the mapping stored at that address to the frequency offset f deltaAs shown in FIG. 6A, the frequency offset f delta is the output of the loop filter 352 and the initialized frequency f from the sequencer logic 630 init are applied to the input of adder 654 together with

[0074] According to this alternative example, the frequency offset f determined by the MSE calculation circuitry 640 delta is the phase of the sampling clock SCLK relative to the initialization frequency f init This frequency offset f determined by MSE calculation circuitry 640 corresponds to the periodicity of the minimum of the error measure MSE as it progresses through each symbol period according to delta is used to derive the frequency correction for the sampling clock SCLK.

[0075] 7 illustrates a method of timing recovery and equalization adaptation based on this observation, according to this alternative example. In this method, processes 402-408 adjust the initialization frequency f during operation of the symbol timing recovery and equalization circuitry 600. init 4, including adaptation of the DFE 620 at idle state 400.

[0076] According to this example implementation, the DFE adaptation process 408 may use higher order tap weights w2 through w1 instead of the first order tap weight w1 when the network channel is short, e.g., 10 meters or less. m The DFE adaptation for short channels is based on the fact that the ISI post-cursor P1 is generally very small in short channels and may be negative due to the effect of the HPF 302 in the AFE 216. In connection with this implementation, it has been observed that adaptation of the primary tap weight w1 during timing loop adjustment may be advantageous in such situations.

[0077] In process 710, MSE calculation circuitry 640 generates an error measure MSE for each sample, as described above in connection with Figure 4. In this implementation, min / max estimation logic 680 calculates the observed minimum MSE of the error measure MSE values ​​generated by MSE calculation circuitry 640. min and maximum MSE max From either or both of the error measurement threshold MSE thr_seq For example, the min / max estimation logic 680 may be configured to calculate the minimum error measure MSE observed over multiple samples. min By adding the difference Δ to thr_seq This difference Δ may be a fixed value or may be a minimum error measure MSE observed during the adaptation of the DFE 620. min and the maximum error measure MSE max Once calculated, the error measurement threshold MSE thr_seq is forwarded to the sequencer logic 630.

[0078] In process 712, the MSE calculation circuitry 640 calculates the initial frequency f init Based on the periodicity of the error measure MSE for the samples obtained in delta In this example, this periodicity is expressed as the median error MSE mid The counter 682 counts the clock cycles between crossings of , and the count is applied to a LUT 684 to determine the offset frequency f delta is obtained.

[0079] In process 714, the offset frequency f determined in process 712 is delta is the initialization frequency f init together with the sum of the received signal to the adder 654. The sum output by the adder 654 is applied to the NCO 356 which applies the control signal UP / DN to the PI 362 accordingly to adjust the frequency of the sampling clock SCLK so that samples of the received signal are obtained at the ADC 308.

[0080] The MSE monitoring logic in the sequencer logic 630 continues to monitor the error measure MSE as the symbol timing recovery and equalization circuitry 600 receives additional input symbols and sets the new value of the error measure MSE as the error measure threshold MSE thr_seq At decision 715, the sequencer logic 630 compares the most recent error measure MSE(n) with the error measure threshold MSE determined in process 710. thr_seq If not (decision 715 is "no"), then in process 716 the DFE 620 is re-adapted based on that symbol and continues monitoring.

[0081] The error measurement value MSE is the error measurement threshold MSE thr_seq , (decision 715 is "YES"), sequencer logic 630 initiates operation of the timing loop by issuing a control signal TLOOP_START to TED circuitry 350 in the example architecture of FIG. 6A, for example, as described above. In response to control signal TLOOP_START, TED circuitry 350 operates to generate a timing error signal ted via loop filter 352 for application to summer 654. TED circuitry 350 in this implementation generates the residual samples x(n) and the symbol stream at the input and output, respectively, of slicer 624 of DFE 620. TIFF2025531505000019.tif34, and operates in the same manner as described above with respect to FIGS. 3A-3C.

[0082] The operation of the timing loop of the symbol timing recovery and equalization circuit element 300 may be performed in stages to achieve faster convergence, beginning with a coarse timing adjustment in process 720. As shown in FIG. 7, a fine adjustment or adjustment of the sampling phase is then performed in process 722, with such adjustment being based on the timing error detected after the coarse timing adjustment process 720. If the network channel is such that the required gain in the PGA 304 can be determined from measurements, etc., the primary tap weight w1 (tap 625a) of the DFE 620 may only be adapted during the fine adjustment process 720 to the extent that it has not previously been adapted in process 408, as described above.

[0083] In either case, following the fine tuning in process 722, steady-state operation of the receive path of PHY 106, including AFE 216 and symbol timing recovery and equalization circuitry 600, may be performed in state 730.

[0084] According to this alternative example, joint convergence of equalization and sample timing in a network receiver can be achieved quickly and accurately, even in implementations where the equalization and timing loops are interdependent. delta Convergence is facilitated by determining σ from the periodicity of the error measure MSE over multiple cycles and incorporating that frequency offset into the phase adjustment of the sampling clock SCLK. The coefficients of the decision feedback equalizer are then adapted to values ​​that indicate a relatively low error, so that timing loop correction can begin at a point closer to convergence on the correct value, reducing the time required for timing loop convergence.

[0085] As used herein, the terms "terminal," "node," "interconnect," and "pin" are used interchangeably. Unless specifically stated to the contrary, these terms are used generally to refer to an interconnection or termination between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0086] Unless otherwise stated, the words "about," "approximately," or "substantially" preceding a value means ±10 percent of the stated value. Variations in the described examples are possible, and other examples are possible, within the scope of the claims.

[0087] A device that is "configured to" perform a certain task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform that function and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0088] A circuit or device described as including certain components may instead be adapted to be coupled to those components to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may instead include only the semiconductor elements (e.g., a semiconductor die and / or integrated circuit (IC) package) within a single physical device and be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure during or after manufacture, e.g., by an end user and / or a third party. In some examples, some elements are included in an integrated circuit and others are external to the integrated circuit, while in other examples, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features illustrated as being external to the integrated circuit may be included within the integrated circuit, and / or some features illustrated as being internal to the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are (1) integrated in / on a semiconductor substrate, (2) integrated in a single semiconductor package, (3) integrated in the same module, and / or (4) integrated in / on the same printed circuit board.

[0089] The circuits described herein are reconfigurable to include replaced components to provide functionality at least partially similar to that available prior to the component replacement. A component shown as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the depicted resistor, unless otherwise noted. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as a single resistor or capacitor.

[0090] While some elements are described above as being included in an integrated circuit and other elements are external to the integrated circuit, in other instances, additional or fewer features may be incorporated into the integrated circuit. Also, some or all of the features illustrated as being external to the integrated circuit may be included within the integrated circuit, and / or some features illustrated as being internal to the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that are (1) incorporated within or on a semiconductor substrate, (2) incorporated in a single semiconductor package, (3) incorporated within the same module, and / or (4) incorporated within or on the same printed circuit board.

[0091] Use of the term "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of the present description. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means ±10 percent of the stated value, or, if the value is zero, a reasonable range around the zero.

[0092] While one or more examples have been described herein, it is of course contemplated that modifications and alternatives to these examples, which will achieve one or more of the technical advantages of these examples, will be apparent to those skilled in the art having reference to this specification and its drawings. Such modifications and alternatives are contemplated to be within the scope of the claims presented herein.

Claims

1. 1. A method comprising: sampling an input analog signal having a symbol frequency in response to a sampling clock initially at a frequency greater than said symbol frequency; converting the sampled input analog signal into a digital sample stream; equalizing the digital sample stream with a decision feedback equalizer to generate an output digital stream; adapting at least one tap weight of the decision feedback equalizer; calculating an error measure from the output sample stream; adjusting a phase of the sampling clock in response to the error measurement crossing an error threshold; A method comprising:

2. 2. The method of claim 1, wherein calculating the error measure comprises calculating a mean squared error for each of a plurality of samples.

3. 3. The method of claim 2, wherein the equalizing comprises: applying a digital filter to samples in the output digital stream, the digital filter including at least one tap weight to generate a feedback signal; subtracting the feedback signal from samples of the digital sample stream to generate a stream of post-cursor filtered samples; slicing the post-cursor filtered samples to generate the output digital stream; Including, The method, wherein calculating the mean squared error includes generating the mean squared error from a difference between the post-cursor filtered sample and the output digital stream for each of a plurality of samples.

4. 2. The method of claim 1, wherein said adjusting comprises adjusting the phase of the sampling clock to minimize a timing error function of the output digital stream.

5. 5. The method of claim 4, wherein calculating the error measure comprises: calculating a mean squared error for each of the plurality of samples; observing a periodicity of the mean squared error over the plurality of samples; calculating the error threshold for the identified minimum value of the mean squared error measure; Including, The method, wherein the adjusting adjusts the phase of the sampling clock in response to the error measurement being below the error threshold.

6. 2. The method of claim 1, wherein calculating the error measure comprises: calculating a mean squared error for each of the plurality of samples; observing a periodicity of the mean squared error over the plurality of samples; Including, The adjusting step comprises: calculating a frequency offset corresponding to a minimum of the observed periodicity; adjusting the phase of the sampling clock according to the frequency offset; A method comprising:

7. 7. The method of claim 6, wherein calculating the adjusted sampling frequency comprises: identifying a minimum and a maximum of the mean squared error; identifying a mean squared error threshold based on the minimum and maximum values; measuring the time interval between crossings of the threshold by the mean square error; mapping the measured time interval to the frequency offset; A method comprising:

8. 8. The method of claim 7, further comprising: receiving the input analog signal from a communication channel; The adjusting step further comprises: after adjusting the phase of the sampling clock according to the adjusted sampling frequency, further adjusting the phase of the sampling clock to minimize a timing error function of the output digital stream with a first adjustment step size; thereafter, further adjusting the phase of the sampling clock to minimize a timing error function of the output digital stream with a second adjustment step size that is smaller than the first adjustment step size; A method comprising:

9. 9. The method of claim 8, determining whether the communication channel has a length below a length threshold; the adjusting is in response to the communication channel having a length below the length threshold; after adjusting the phase of the sampling clock in accordance with the adjusted sampling frequency, further adjusting the phase of the sampling clock by only the second adjustment step size to minimize a timing error function of the output digital stream.

10. 1. A network communication receiver, comprising: a data converter adapted to receive an analog signal at its input and to output a digital sample stream at its output, the analog signal having a symbol frequency, the data converter sampling the analog signal in response to a sampling clock signal and converting the sampled signal to the digital sample stream; a clock generation circuit element coupled to the data converter, the clock generation circuit element configured to generate the sampling clock signal at a phase and frequency responsive to a clock control signal; digital receiver circuitry having an input coupled to the output of the data converter for receiving the digital sample stream; Including, the digital receiver circuitry comprising: a decision feedback equalizer (DFE) including a digital filter having one or more tap weights and configured to generate an output digital stream from the digital sample stream; error measurement circuitry coupled to the DFE and configured to measure an error in samples of the output digital stream; a clock control circuitry coupled to the DFE and configured to generate the clock control signal; sequencer logic coupled to the DFE, the error measurement circuitry, and the clock control circuitry; Including, the sequencer logic is configured to control operation of the decision feedback equalizer, the error measurement circuitry, and the clock control circuitry according to a plurality of operations; The plurality of operations: generating a clock control signal in response to an initialization frequency signal corresponding to a frequency above the symbol frequency of the received analog signal; adapting at least one of the tap weights of the adaptive equalizer; calculating an error measure from the output sample stream; adjusting the clock control signal in response to the error measurement crossing an error threshold; Including, Network communication receiver.

11. 11. The receiver of claim 10, wherein the digital receiver circuitry further comprises: timing error detection circuitry configured to calculate a timing error signal from the output digital stream; the sequencer logic is configured to control the timing error detection circuit to generate a clock control adjustment to the clock control signal in response to the error measurement value crossing the error threshold. Receiver.

12. 12. The receiver of claim 11, wherein the error measurement circuitry comprises: calculating a mean squared error in samples of the output sample stream; configured to identify a minimum of a mean squared error over a plurality of samples of the output sample stream; The receiver, wherein the sequencer logic is further configured to generate a start signal to the timing error detection circuitry in response to the error measurement being below an error threshold determined from a minimum of the mean squared errors.

13. 11. The receiver of claim 10, wherein the error measurement circuitry comprises: calculating a mean squared error in samples of the output sample stream; identifying a periodicity of the mean squared error across a plurality of samples of the output sample stream; calculating a frequency offset corresponding to the identified periodicity of the mean squared error; It is configured as follows: the clock control circuitry configured to adjust the clock control signal in response to the frequency offset; Receiver.

14. 14. The receiver of claim 13, wherein the error measurement circuitry comprises: identifying a minimum and a maximum of the mean squared error; identifying a mean squared error threshold based on the minimum and maximum values; measuring the time interval between crossings of the threshold by the mean square error; mapping the measured time interval to the frequency offset; and configured to calculate the adjusted sampling frequency by Receiver.

15. 11. The receiver of claim 10, wherein the digital receiver circuitry further comprises a feed-forward equalizer configured to equalize the digital sample stream prior to the decision feedback equalizer.

16. 11. The receiver of claim 10, wherein the clock generation circuitry comprises: a phase-locked loop configured to generate a clock signal at a frequency based on a reference clock; a phase interpolator having an input for receiving the clock control signal and an input for receiving the clock signal from the phase locked loop; Including, The receiver, wherein the phase interpolator is configured to generate the sampling clock signal at a phase responsive to the clock signal and the clock control signal.

17. 1. A physical layer transceiver comprising: a media independent interface; a medium dependent interface; a transmit processing block coupled to the media independent interface; a transmitter subsystem coupled between the transmit processing block and the medium dependent interface, the transmitter subsystem configured to communicate analog signals corresponding to data from the transmit processing block via the medium dependent interface; a data converter coupled to the media dependent interface and adapted to receive an analog signal having a symbol frequency from the media dependent interface, the data converter configured to sample the analog signal in response to a sampling clock signal and convert the sampled signal into the digital sample stream; a clock generation circuit element coupled to the data converter and configured to generate the sampling clock signal at a phase and frequency responsive to a clock control signal; a receive processing block coupled to the media independent interface; Including, the receive processing block includes symbol timing recovery and equalization circuitry; the symbol timing recovery and equalization circuitry comprising: a decision feedback equalizer including a digital filter having one or more tap weights, the decision feedback equalizer configured to generate an output digital stream from the digital sample stream; error measurement circuitry coupled to the decision feedback equalizer and configured to measure an error in samples of the output digital stream; clock control circuitry coupled to the error measurement circuitry and configured to generate the clock control signal; sequencer logic coupled to the decision feedback equalizer, the error measurement circuitry, and the clock control circuitry; Including, the sequencer logic is configured to control operation of the decision feedback equalizer, the error measurement circuitry, and the clock control circuitry according to a plurality of operations, the plurality of operations comprising: generating a clock control signal in response to an initialization frequency signal corresponding to a frequency above the symbol frequency of the received analog signal; adapting at least one of the tap weights of the adaptive equalizer; calculating an error measure from the output sample stream; adjusting the clock control signal in response to the error measurement crossing an error threshold; a physical layer transceiver including:

18. 18. The transceiver of claim 17, wherein the error measurement circuitry comprises: calculating a mean squared error in samples of the output sample stream; configured to identify a minimum of a mean squared error over a plurality of samples of the output sample stream; the sequencer logic is further configured to generate a start signal to the timing error detection circuitry in response to the error measurement being below an error threshold determined from the minimum of the mean squared error.

19. 18. The transceiver of claim 17, wherein the error measurement circuitry comprises: calculating a mean squared error in samples of the output sample stream; identifying a periodicity of the mean squared error across a plurality of samples of the output sample stream; calculating a frequency offset corresponding to the identified periodicity of the mean squared error; It is configured as follows: The transceiver, wherein the clock control circuitry is configured to adjust the clock control signal in response to the frequency offset.

20. 20. The transceiver of claim 19, wherein the error measurement circuitry comprises: The adjusted sampling frequency is identifying a minimum and a maximum of the mean squared error; identifying the mean squared error threshold based on the minimum and maximum values; measuring the time interval between crossings of the threshold by the mean square error; mapping the measured time interval to the frequency offset; The transceiver is configured to calculate

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