Indication device

Abstract

A display device is provided. The display device includes: (1) a light-emitting element disposed on a substrate; (2) a first transistor that controls a drive current flowing through the light-emitting element; (3) a second transistor that supplies a data voltage to a source electrode of the first transistor; (4) a 3-1 transistor and a 3-2 transistor that are connected in series between a gate electrode of the first transistor and a drain electrode of the first transistor; (5) a first metal layer that is disposed on the substrate and includes a gate electrode of the 3-1 transistor and a gate electrode of the 3-2 transistor; (6) a hydrogen passivation layer that is disposed on the first metal layer; (7) semiconductor regions of the first transistor, the 3-1 transistor, and the 3-2 transistor that are disposed on the hydrogen passivation layer; (8) a capping layer that is disposed on the semiconductor region of the first transistor; (9) a gate electrode of the first transistor that is disposed on the capping layer; (10) a first bias electrode that is disposed in the same layer as the gate electrode of the first transistor and overlaps with the semiconductor region of the 3-1 transistor; and (11) a second bias electrode that is disposed in the same layer as the first bias electrode and overlaps with the semiconductor region of the 3-2 transistor.

Description

[Technical Field]

[0001] The present invention relates to a display device. [Background technology]

[0002] With the development of an information society, the demands for display devices for displaying images are becoming increasingly diverse. For example, display devices are applied to a variety of electronic devices, such as smartphones, digital cameras, notebook computers, navigation systems, and smart TVs. Display devices can display images without a backlight unit that provides light to the display panel by including light-emitting elements in each pixel of the display panel that can emit light themselves.

[0003] The display device includes a plurality of pixels, data lines and gate lines connected to the plurality of pixels, a data driver for supplying a data voltage to the data lines, and a gate driver for supplying a gate signal to the gate lines, and the data driver and the gate driver can drive the plurality of pixels according to a predetermined frequency. Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide a display device that can improve the driving range of a first transistor and improve the leakage current characteristics and low-frequency characteristics of a transistor electrically connected to the gate electrode of the first transistor.

[0005] The problems to be solved by the present invention are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0006] A display device according to one embodiment for solving the above problems includes: (1) a light-emitting element disposed on a substrate; (2) a first transistor for controlling a drive current flowing through the light-emitting element; (3) a second transistor for supplying a data voltage to a source electrode of the first transistor; (4) a 3-1 transistor and a 3-2 transistor connected in series between a gate electrode of the first transistor and a drain electrode of the first transistor; (5) a first metal layer disposed on the substrate and including a gate electrode of the 3-1 transistor and a gate electrode of the 3-2 transistor; and (6) a hydrogen passivation layer disposed on the first metal layer. (7) a hydrogen passivation layer, (8) a capping layer disposed on the semiconductor region of the first transistor, (9) a gate electrode of the first transistor disposed on the capping layer, (10) a first bias electrode disposed in the same layer as the gate electrode of the first transistor and overlapping the semiconductor region of the (3-1) transistor, and (11) a second bias electrode disposed in the same layer as the first bias electrode and overlapping the semiconductor region of the (3-2) transistor.

[0007] The hydrogen passivation layer may be in direct contact with the lower surface of each of the semiconductor regions of the first transistor, the 3-1 transistor, and the 3-2 transistor.

[0008] The first and second bias electrodes may be electrically connected to a driving voltage line to receive a driving voltage.

[0009] The display device may further include (1) a 4-1 transistor and a 4-2 transistor connected in series between the gate electrode of the first transistor and a first initialization voltage line, and (2) a second metal layer arranged in the same layer as the first metal layer and including the gate electrode of the 4-1 transistor and the gate electrode of the 4-2 transistor.

[0010] The gate electrode of the second transistor may receive a first gate signal from a first gate line, and the first metal layer may receive a second gate signal different from the first gate signal from a second gate line.

[0011] The second metal layer may receive a third gate signal from a third gate line, the third gate signal being different from the first and second gate signals.

[0012] The display device may further include (1) a third bias electrode arranged in the same layer as the second bias electrode and overlapping with a semiconductor region of the 4-1 transistor, and (2) a fourth bias electrode arranged in the same layer as the third bias electrode and overlapping with a semiconductor region of the 4-2 transistor.

[0013] The third and fourth bias electrodes may be electrically connected to a driving voltage line to receive a driving voltage.

[0014] The display device may further include (1) a fifth transistor arranged between the source electrode of the first transistor and a driving voltage line, (2) a sixth transistor arranged between the drain electrode of the first transistor and the light-emitting element, and (3) a seventh transistor arranged between the first electrode of the light-emitting element and a second initialization voltage line.

[0015] The display device may further include an eighth transistor disposed between the source electrode of the first transistor and a bias voltage line.

[0016] The first transistor may include a protrusion formed on a semiconductor region, a source electrode, and a drain electrode of the first transistor, and the capping layer may cover the protrusion of the first transistor.

[0017] The display device may further include a gate insulating film disposed between the capping layer and the gate electrode of the first transistor, wherein the capping layer may include a silicon oxide layer or an amorphous silicon layer, and the gate insulating film may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0018] A display device according to one embodiment for solving the above problems includes: (1) a light-emitting element disposed on a substrate; (2) a first transistor for controlling a drive current flowing through the light-emitting element; (3) a second transistor for supplying a data voltage to a source electrode of the first transistor; (4) a 3-1 transistor and a 3-2 transistor connected in series between a gate electrode of the first transistor and a drain electrode of the first transistor; (5) a first metal layer disposed on the substrate and including a gate electrode of the 3-1 transistor and a gate electrode of the 3-2 transistor; (6) a hydrogen passivation layer disposed on the first metal layer; (8) a capping layer disposed on the semiconductor region of the first transistor; (9) a gate electrode of the first transistor disposed on the capping layer; (10) a first bias electrode disposed in the same layer as the gate electrode of the first transistor and overlapping the semiconductor region of the 3-1 transistor; and (11) a second bias electrode disposed in the same layer as the first bias electrode, overlapping the semiconductor region of the 3-2 transistor, and electrically connected to the first metal layer.

[0019] The first bias electrode may be electrically connected to a driving voltage line to receive a driving voltage.

[0020] A gate electrode of the second transistor may receive a first gate signal from a first gate line, and the first metal layer and the second bias electrode may receive a second gate signal different from the first gate signal from a second gate line.

[0021] The display device may further include a second metal layer disposed in the same layer as the first metal layer and overlapping a semiconductor region of the first transistor.

[0022] The second metal layer may be electrically connected to a driving voltage line to receive a driving voltage.

[0023] In one embodiment of the display device for solving the above problem, the display device includes: (1) a light-emitting element arranged on a substrate; (2) a first transistor that controls a drive current flowing through the light-emitting element; (3) a second transistor that supplies a data voltage to a source electrode of the first transistor; (4) a 3-1 transistor and a 3-2 transistor that are connected in series between a gate electrode of the first transistor and a drain electrode of the first transistor; (5) a first metal layer arranged on the substrate and including a gate electrode of the 3-1 transistor and a gate electrode of the 3-2 transistor; (6) semiconductor regions of the first transistor, the 3-1 transistor, and the 3-2 transistor that are arranged on the first metal layer; (7) a gate electrode of the first transistor that is arranged on the semiconductor region of the first transistor; and (8) a first bias electrode that is arranged in the same layer as the gate electrode of the first transistor, overlaps with the semiconductor region of the 3-1 transistor, and is electrically connected to a drive voltage line, and the gate electrode of the first transistor is electrically connected to a source electrode of the 3-1 transistor that is arranged in the same layer as the semiconductor region of the 3-1 transistor.

[0024] (1) a 4-1 transistor and a 4-2 transistor connected in series between the gate electrode of the first transistor and a first initialization voltage line, and (2) a second metal layer arranged in the same layer as the first metal layer and including a gate electrode of the 4-1 transistor and a gate electrode of the 4-2 transistor, wherein the gate electrode of the first transistor may be electrically connected to a source electrode of the 4-1 transistor arranged in the same layer as a semiconductor region of the 4-1 transistor.

[0025] The display device may further include a third metal layer disposed in the same layer as the first metal layer, overlapping a semiconductor region of the first transistor, and electrically connected to a driving voltage line.

[0026] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0027] According to the display device of the embodiment, the display device includes a capping layer covering the protrusion of the first transistor, thereby improving the driving range of the first transistor. The transistor electrically connected to the gate electrode of the first transistor may include a gate electrode disposed below the semiconductor region and a bias electrode disposed on the semiconductor region, and the hydrogen passivation layer may directly contact the underside of the semiconductor region. Therefore, by including the hydrogen passivation layer, the display device can eliminate interface defects in the transistor electrically connected to the gate electrode of the first transistor, thereby improving leakage current characteristics and low-frequency characteristics.

[0028] The effects of the embodiments are not limited to the above examples, and a wider variety of effects are included in this specification. [Brief explanation of the drawings]

[0029] [Figure 1] 1 is a perspective view illustrating a display device according to an embodiment. [Figure 2] 1 is a cross-sectional view showing a display device according to an embodiment. [Figure 3] 1 is a plan view showing a display unit of a display device according to an embodiment; [Figure 4] 1 is a block diagram illustrating a display panel and a display driver according to an embodiment. [Figure 5] 1 is a circuit diagram illustrating a pixel of a display device according to an embodiment. [Figure 6] 6 is a waveform diagram of a signal supplied to the pixel shown in FIG. 5. [Figure 7] 1 is a cross-sectional view showing a part of a display device according to an embodiment. [Figure 8] FIG. 4 is a cross-sectional view showing another part of the display device according to the embodiment. [Figure 9] 10 is a graph showing transfer characteristics of first and second test transistors in a display device according to an embodiment. [Figure 10] FIG. 10 is a circuit diagram illustrating a pixel of a display device according to another embodiment. [Figure 11] FIG. 10 is a cross-sectional view showing a part of a display device according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0030] The advantages and features of the present invention, as well as methods for achieving them, will become clearer with reference to the following detailed embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be realized in various different forms. The present embodiments are provided solely for the purpose of complete disclosure of the present invention and to fully convey the scope of the invention to those skilled in the art to which the present invention pertains. The present invention is defined solely by the scope of the claims.

[0031] When elements or layers are referred to as being "on" other elements or layers, this includes all cases where other layers or elements are directly on or between the other elements. The same reference numerals refer to the same components throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are merely examples, and the present invention is not limited to the illustrated matters.

[0032] Although terms such as "first" and "second" are used to describe various components, it is understood that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it is understood that a "first" component referred to below may be a "second" component within the technical concept of the present invention.

[0033] The features of the various embodiments of the present invention may be partially or fully combined or combined with one another, may be technically interlocked and driven in various ways, and may be implemented independently of one another or in conjunction with one another.

[0034] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0035] FIG. 1 is a perspective view showing a display device according to an embodiment.

[0036] Referring to FIG. 1, the display device 10 may be applied to portable electronic devices such as a mobile phone, a smartphone, a tablet PC (Tablet Personal Computer), a mobile communication terminal, an electronic organizer, an electronic book, a PMP (Portable Multimedia Player), a navigation system, an UMPC (Ultra Mobile PC), etc. For example, the display device 10 may be applied to a television, a notebook computer, a monitor, a billboard, or a display unit of an Internet of Things (IoT). As another example, the display device 10 may be applied to a wearable device such as a smart watch, a watch phone, a glasses-type display, or a head-mounted display (HMD).

[0037] The display device 10 has a planar shape similar to a rectangle. For example, the display device 10 may have a planar shape similar to a rectangle, with a short side in the X-axis direction and a long side in the Y-axis direction. The corner where the short side in the X-axis direction and the long side in the Y-axis direction intersect may be rounded or formed at a right angle to have a predetermined curvature. The planar shape of the display device 10 is not limited to a rectangle, and may be formed in various shapes such as other polygons, circles, or ellipses.

[0038] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , a touch driver 400 , and a power supply 500 .

[0039] The display panel 100 may include a main area MA and a sub-area SBA.

[0040] The main area MA may include a display area DA having pixels for displaying images, and a non-display area NDA arranged around the display area DA. The display area DA can emit light from a plurality of light-emitting areas or a plurality of aperture areas. For example, the display panel 100 may include pixel circuits including switching elements, pixel defining films that define the light-emitting areas or aperture areas, and self-light-emitting elements.

[0041] For example, the light-emitting element may include at least one of an organic light-emitting diode (OLED) including an organic light-emitting layer, a quantum dot LED including a quantum dot emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0042] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as a peripheral area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver (not shown) that supplies gate signals to the gate lines and fan-out lines (not shown) that connect the display driver 200 to the display area DA.

[0043] The sub-region SBA may extend from one side of the main region MA. The sub-region SBA may include a flexible material that allows bending, folding, rolling, etc. For example, when the sub-region SBA is bent, the sub-region SBA overlaps the main region MA in the thickness direction (Z-axis direction). The sub-region SBA may include the display driver 200 and a pad unit connected to the circuit board 300. Alternatively, the sub-region SBA may be omitted, and the display driver 200 and the pad unit may be disposed in the non-display region NDA.

[0044] The display driver 200 outputs signals and voltages for driving the display panel 100. The display driver 200 supplies data voltages to data lines. The display driver 200 supplies power supply voltages to power lines and gate control signals to the gate driver. The display driver 200 is formed as an integrated circuit (IC) and is mounted on the display panel 100 using a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 may be disposed in the sub-region SBA and may overlap the main region MA in the thickness direction (Z-axis direction) by bending the sub-region SBA. As another example, the display driver 200 may be mounted on a circuit board 300.

[0045] The circuit board 300 can be attached onto the pad portion of the display panel 100 using an anisotropic conductive film (ACF). Lead wires of the circuit board 300 can be electrically connected to the pad portion of the display panel 100. The circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0046] The touch driver 400 is mounted on the circuit board 300. The touch driver 400 may be electrically connected to a touch sensing unit of the display panel 100. The touch driver 400 supplies touch driving signals to a plurality of touch electrodes of the touch sensing unit and senses changes in capacitance between the plurality of touch electrodes. For example, the touch driving signal may be a pulse signal having a predetermined frequency. The touch driver 400 may calculate the presence or absence of an input and the input coordinates based on the changes in capacitance between the plurality of touch electrodes. The touch driver 400 may be formed as an integrated circuit (IC).

[0047] The power supply unit 500 is disposed on the circuit board 300 and supplies power supply voltages to the display driver 200 and the display panel 100. The power supply unit 500 generates a driving voltage and supplies it to a driving voltage line, generates an initialization voltage and supplies it to an initialization voltage line, and generates a common voltage and supplies it to a common electrode common to light-emitting elements of a plurality of pixels. For example, the driving voltage may be a high potential voltage for driving the light-emitting elements, and the common voltage may be a low potential voltage for driving the light-emitting elements.

[0048] FIG. 2 is a cross-sectional view showing a display device according to an embodiment.

[0049] 2, the display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin film transistor layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0050] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that allows bending, folding, rolling, etc. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited to this. As another example, the substrate SUB may include a glass material or a metal material.

[0051] The thin film transistor layer TFTL is disposed on the substrate SUB. The thin film transistor layer TFTL may include a plurality of thin film transistors that constitute pixel circuits of pixels. The thin film transistor layer TFTL may further include gate lines, data lines, power lines, gate control lines, fan-out lines connecting the display driver 200 to the data lines, and lead lines connecting the display driver 200 to the pad unit. Each thin film transistor may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, if the gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a thin film transistor.

[0052] The thin film transistor layer TFTL may be arranged in the display area DA, the non-display area NDA, and the sub-area SBA. The thin film transistors, gate lines, data lines, and power supply lines of the pixels of the thin film transistor layer TFTL may be arranged in the display area DA. The gate control lines and fan-out lines of the thin film transistor layer TFTL may be arranged in the non-display area NDA. The lead lines of the thin film transistor layer TFTL may be arranged in the sub-area SBA.

[0053] The light-emitting element layer EML may be disposed on the thin film transistor layer TFTL. The light-emitting element layer EML may include a plurality of light-emitting elements each having a pixel electrode, a light-emitting layer, and a common electrode stacked in sequence to emit light, and a pixel defining film that defines a pixel. The plurality of light-emitting elements of the light-emitting element layer EML may be disposed in the display area DA.

[0054] For example, the light-emitting layer may be an organic light-emitting layer containing an organic material. The light-emitting layer may include a hole transporting layer, an organic light-emitting layer, and an electron transporting layer. When the pixel electrode receives a predetermined voltage through the thin film transistor of the thin film transistor layer TFTL and the common electrode receives a cathode voltage, holes and electrons may move to the organic light-emitting layer through the hole transporting layer and the electron transporting layer, respectively, and combine with each other in the organic light-emitting layer to emit light. For example, the pixel electrode may be an anode electrode and the common electrode may be a cathode electrode, but is not limited to this.

[0055] As another example, the plurality of light emitting elements may include quantum dot light emitting diodes including a quantum dot light emitting layer, inorganic light emitting diodes including an inorganic semiconductor, or micro light emitting diodes.

[0056] The encapsulation layer TFEL may cover the top and side surfaces of the light-emitting element layer EML to protect the light-emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic film and at least one organic film for encapsulating the light-emitting element layer EML.

[0057] The touch sensing unit TSU is disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a plurality of touch electrodes for sensing a user's touch in a capacitive manner and touch lines connecting the plurality of touch electrodes to the touch driver 400. For example, the touch sensing unit TSU may sense a user's touch in a mutual capacitance manner or a self-capacitance manner.

[0058] As another example, the touch sensing unit TSU may be disposed on a separate substrate disposed on the display unit DU. In this case, the substrate supporting the touch sensing unit TSU may be a base member that seals the display unit DU.

[0059] The touch electrodes of the touch sensing unit TSU are arranged in a touch sensor area overlapping the display area DA, and the touch lines of the touch sensing unit TSU are arranged in a touch peripheral area overlapping the non-display area NDA.

[0060] The color filter layer CFL is disposed on the touch sensing unit TSU. The color filter layer CFL may include a plurality of color filters corresponding to the plurality of light-emitting regions. Each color filter may selectively transmit light of a specific wavelength and block or absorb light of other wavelengths. The color filter layer CFL may absorb a portion of light entering from outside the display device 10 to reduce reflected light due to external light. Therefore, the color filter layer CFL may prevent color distortion due to external light reflection.

[0061] Since the color filter layer CFL is disposed directly on the touch sensing unit TSU, the display device 10 does not require a separate substrate for the color filter layer CFL, and therefore the thickness of the display device 10 can be relatively reduced.

[0062] The sub-region SBA of the display panel 100 may extend from one side of the main region MA. The sub-region SBA may include a flexible material that allows bending, folding, rolling, etc. For example, when the sub-region SBA is bent, the sub-region SBA overlaps the main region MA in the thickness direction (Z-axis direction). The sub-region SBA may include pads electrically connected to the display driver 200 and the circuit board 300.

[0063] FIG. 3 is a plan view showing a display unit of a display device according to an embodiment, and FIG. 4 is a block diagram showing a display panel and a display driver according to an embodiment.

[0064] 3 and 4, the display panel 100 may include a display area DA and a non-display area NDA.

[0065] The display area DA may include a plurality of pixels SP, a plurality of drive voltage lines VDDL connected to the plurality of pixels SP, a plurality of gate lines GL, a plurality of light emission control lines EML, and a plurality of data lines DL.

[0066] Each of the pixels SP may be connected to a gate line GL, a data line DL, an emission control line EML, and a driving voltage line VDDL. Each of the pixels SP may include at least one transistor, a light emitting element, and a capacitor.

[0067] The gate lines GL extend in the X-axis direction and are spaced apart from one another in the Y-axis direction that intersects with the X-axis direction. The gate lines GL can sequentially supply gate signals to a plurality of pixels SP.

[0068] The light-emission control lines EML extend in the X-axis direction and are spaced apart from one another in the Y-axis direction. The light-emission control lines EML can sequentially supply light-emission signals to the plurality of pixels SP.

[0069] The data lines DL extend in the Y-axis direction and are spaced apart from one another in the X-axis direction. The data lines DL supply data voltages to the pixels SP. The data voltages can determine the luminance of each of the pixels SP.

[0070] The driving voltage lines VDDL extend in the Y-axis direction and are spaced apart from one another in the X-axis direction. The driving voltage lines VDDL supply driving voltages to the pixels SP. The driving voltages may be high potential voltages for driving the light-emitting elements of the pixels SP.

[0071] The non-display area NDA may surround the display area DA and may include a gate driver 610, a light-emitting control driver 620, a fan-out line FL, a first gate control line GSL1, and a second gate control line GSL2.

[0072] The fan-out lines FL extend from the display driver 200 to the display area DA. The fan-out lines FL can supply the data voltages received from the display driver 200 to the plurality of data lines DL.

[0073] The first gate control line GSL1 extends from the display driver 200 to the gate driver 610. The first gate control line GSL1 may provide the gate control signal GCS received from the display driver 200 to the gate driver 610.

[0074] The second gate control line GSL2 may extend from the display driver 200 to the light emission control driver 620. The second gate control line GSL2 may supply the light emission control signal ECS received from the display driver 200 to the light emission control driver 620.

[0075] The sub-area SBA may extend from one side of the non-display area NDA. The sub-area SBA may include a display driver 200 and a pad unit DP. The pad unit DP is disposed adjacent to one side edge of the sub-area SBA from the display driver 200. The pad unit DP may be electrically connected to the circuit board 300 via an anisotropic conductive film (ACF).

[0076] The display driver 200 may include a timing controller 210 and a data driver 220 .

[0077] The timing control unit 210 may receive digital video data DATA and timing signals from the circuit board 300. The timing control unit 210 may generate a data control signal DCS based on the timing signals to control the operation timing of the data driver 220, generate a gate control signal GCS to control the operation timing of the gate driver 610, and generate an emission control signal ECS to control the operation timing of the emission control driver 620. The timing control unit 210 may supply the gate control signal GCS to the gate driver 610 via a first gate control line GSL1. The timing control unit 210 may supply the emission control signal ECS to the emission control driver 620 via a second gate control line GSL2. The timing control unit 210 may supply the digital video data DATA and the data control signal DCS to the data driver 220.

[0078] The data driver 220 converts the digital video data DATA into analog data voltages and supplies them to the data lines DL via the fan-out lines FL. The gate signals of the gate driver 610 can select the pixels SP to which the data voltages are supplied, and the selected pixels SP can receive the data voltages via the data lines DL.

[0079] The power supply unit 500 is disposed on the circuit board 300 and supplies a power supply voltage to the display driver 200 and the display panel 100. The power supply unit 500 generates a driving voltage and supplies it to a driving voltage line VDDL, generates an initialization voltage and supplies it to an initialization voltage line, and may generate a common voltage and supply it to a common electrode common to light emitting elements of a plurality of pixels.

[0080] The gate driver 610 may be disposed outside one side of the display area DA or on one side of the non-display area NDA, and the light emission control driver 620 may be disposed outside the other side of the display area DA or on the other side of the non-display area NDA, but is not limited thereto. As another example, the gate driver 610 and the light emission control driver 620 may be disposed on either one side or the other side of the non-display area NDA.

[0081] The gate driver 610 may include a plurality of transistors that generate gate signals based on the gate control signal GCS. The light emission control driver 620 may include a plurality of transistors that generate light emission signals based on the light emission control signal ECS. For example, the transistors of the gate driver 610 and the light emission control driver 620 may be formed in the same layer as the respective transistors of the pixel SP. The gate driver 610 may supply gate signals to the gate lines GL, and the light emission control driver 620 may supply light emission signals to the light emission control lines EML.

[0082] FIG. 5 is a circuit diagram showing a pixel of a display device according to an embodiment, and FIG. 6 is a waveform diagram of a signal supplied to the pixel shown in FIG.

[0083] 5 and 6, the display panel 100 may include a plurality of pixels SP arranged along p rows (p is a natural number) and q columns (q is a natural number). Each of the plurality of pixels SP may be connected to a first gate line GWL, a second gate line GCL, a third gate line GIL, a fourth gate line GBL, an emission control line EML, a data line DL, a driving voltage line VDDL, a first initialization voltage line VIL1, a second initialization voltage line VIL2, and a bias voltage line VBL.

[0084] The pixel SP may include a pixel circuit and a light-emitting element ED. The pixel circuit may include a first transistor ST1, a second transistor ST2, a third-first transistor ST3-1, a third-second transistor ST3-2, a fourth-first transistor ST4-1, a fourth-second transistor ST4-2, a fifth transistor ST5, a sixth transistor ST6, a seventh transistor ST7, an eighth transistor ST8, and a storage capacitor CST.

[0085] The first transistor ST1 may include a gate electrode, a source electrode, and a drain electrode. The first transistor ST1 may control a source-drain current (Isd, hereinafter referred to as "drive current") in response to a data voltage applied to the gate electrode. The drive current (Isd) flowing through the channel of the first transistor ST1 is proportional to the square of the difference between the voltage (Vsg) between the source electrode and gate electrode of the first transistor ST1 and the threshold voltage (Vth) of the first transistor ST1 (Isd=k×(Vsg−Vth)). 2 ) where k is a proportionality coefficient determined by the structure and physical characteristics of the first transistor ST1, Vsg is the source-gate voltage of the first transistor ST1, and Vth is the threshold voltage of the first transistor ST1.

[0086] The light emitting element ED receives a driving current (Isd) to emit light, and the amount of light emitted or the brightness of the light emitting element ED is proportional to the magnitude of the driving current (Isd).

[0087] The light-emitting element ED may be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first and second electrodes. As another example, the light-emitting element ED may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first and second electrodes. As yet another example, the light-emitting element ED may be a quantum dot light-emitting element including a first electrode, a second electrode, and a quantum dot light-emitting layer disposed between the first and second electrodes. As yet another example, the light-emitting element ED may be a micro light-emitting diode.

[0088] A first electrode of the light-emitting element ED may be electrically connected to the fourth node N4. The first electrode of the light-emitting element ED may be connected to the drain electrode of the sixth transistor ST6 and the source electrode of the seventh transistor ST7 via the fourth node N4. A second electrode of the light-emitting element ED may be connected to the low potential line VSSL. The second electrode of the light-emitting element ED may receive a low potential voltage from the low potential line VSSL.

[0089] The second transistor ST2 may be turned on by a first gate signal GW[n] from the first gate line GWL to electrically connect the data line DL to a first node N1, which is the source electrode of the first transistor ST1. The second transistor ST2 may be turned on based on the first gate signal GW[n] to supply a data voltage to the first node N1. The gate electrode of the second transistor ST2 may be electrically connected to the first gate line GWL, the source electrode may be electrically connected to the data line DL, and the drain electrode may be electrically connected to the first node N1.

[0090] The 3-1 transistor ST3-1 and the 3-2 transistor ST3-2 may be turned on by a second gate signal GC[n] from the second gate line GCL to electrically connect the second node N2, which is the drain electrode of the first transistor ST1, to the third node N3, which is the gate electrode of the first transistor ST1. The 3-1 transistor ST3-1 and the 3-2 transistor ST3-2 may be connected in series between the second node N2 and the third node N3. The gate electrode of the 3-1 transistor ST3-1 may be electrically connected to the second gate line GCL, the source electrode may be electrically connected to the third node N3, and the drain electrode may be electrically connected to the source electrode of the 3-2 transistor ST3-2. The gate electrode of the 3-2 transistor ST3-2 may be electrically connected to the second gate line GCL, the source electrode may be electrically connected to the drain electrode of the 3-1 transistor ST3-1, and the drain electrode may be electrically connected to the second node N2. The gate electrode of the 3-1st transistor ST3-1 and the gate electrode of the 3-2nd transistor ST3-2 may be integrally formed.

[0091] The 3-1 transistor ST3-1 and the 3-2 transistor ST3-2 may each include a bias electrode. The bias electrode of the 3-1 transistor ST3-1 may overlap the semiconductor region of the 3-1 transistor ST3-1, and the bias electrode of the 3-2 transistor ST3-2 may overlap the semiconductor region of the 3-2 transistor ST3-2. The bias electrodes of the 3-1 transistor ST3-1 and the 3-2 transistor ST3-2 may be electrically connected to a drive voltage line VDDL and may receive a drive voltage from the drive voltage line VDDL. Therefore, the bias electrodes of the 3-1 transistor ST3-1 and the 3-2 transistor ST3-2 may stabilize the electric fields of the 3-1 transistor ST3-1 and the 3-2 transistor ST3-2, thereby improving output characteristics.

[0092] The third-1st transistor ST3-1 and the third-2nd transistor ST3-2 have excellent leakage current (Off current) characteristics. Therefore, the third-1st transistor ST3-1 and the third-2nd transistor ST3-2 can prevent leakage current from flowing from the third node N3, which is the gate electrode of the first transistor ST1, and can stably maintain the internal voltage of the pixel SP. The leakage current characteristics of the third-1st transistor ST3-1 and the third-2nd transistor ST3-2 will be described in detail with reference to FIG. 7.

[0093] The 4-1 transistor ST4-1 and the 4-2 transistor ST4-2 may be turned on by a third gate signal GI[n] from the third gate line GIL to electrically connect a third node N3, which is the gate electrode of the first transistor ST1, to the first initialization voltage line VIL1. The 4-1 transistor ST4-1 and the 4-2 transistor ST4-2 may be connected in series between the third node N3 and the first initialization voltage line VIL1. The gate electrode of the 4-1 transistor ST4-1 may be electrically connected to the third gate line GIL, the source electrode may be electrically connected to the third node N3, and the drain electrode may be electrically connected to the source electrode of the 4-2 transistor ST4-2. The gate electrode of the 4-2 transistor ST4-2 may be electrically connected to the third gate line GIL, the source electrode may be electrically connected to the drain electrode of the 4-1 transistor ST4-1, and the drain electrode may be electrically connected to the first initialization voltage line VIL1. The gate electrode of the 4-1st transistor ST4-1 and the gate electrode of the 4-2nd transistor ST4-2 can be integrally formed.

[0094] The 4-1 transistor ST4-1 and the 4-2 transistor ST4-2 may each include a bias electrode. The bias electrode of the 4-1 transistor ST4-1 may overlap the semiconductor region of the 4-1 transistor ST4-1, and the bias electrode of the 4-2 transistor ST4-2 may overlap the semiconductor region of the 4-2 transistor ST4-2. The bias electrodes of the 4-1 transistor ST4-1 and the 4-2 transistor ST4-2 may be electrically connected to a drive voltage line VDDL and may receive a drive voltage from the drive voltage line VDDL. Therefore, the bias electrodes of the 4-1 transistor ST4-1 and the 4-2 transistor ST4-2 may stabilize the electric fields of the 4-1 transistor ST4-1 and the 4-2 transistor ST4-2 and improve output characteristics.

[0095] The 4-1st transistor ST4-1 and the 4-2nd transistor ST4-2 have excellent leakage current (Off current) characteristics. Therefore, the 4-1st transistor ST4-1 and the 4-2nd transistor ST4-2 can prevent leakage current from flowing from the third node N3, which is the gate electrode of the first transistor ST1, and can stably maintain the voltage inside the pixel SP. The leakage current characteristics of the 4-1st transistor ST4-1 and the 4-2nd transistor ST4-2 will be described in detail with reference to FIG. 8.

[0096] The fifth transistor ST5 may be turned on by an emission signal EM[n] of the emission control line EML to electrically connect the driving voltage line VDDL to a first node N1, which is the source electrode of the first transistor ST1. The gate electrode of the fifth transistor ST5 may be electrically connected to the emission control line EML, the source electrode may be electrically connected to the driving voltage line VDDL, and the drain electrode may be electrically connected to the first node N1.

[0097] The sixth transistor ST6 is turned on by an emission signal EM[n] of the emission control line EML to electrically connect the second node N2, which is the drain electrode of the first transistor ST1, to the fourth node N4, which is the first electrode of the light-emitting element ED. The gate electrode of the sixth transistor ST6 is electrically connected to the emission control line EML, the source electrode is electrically connected to the second node N2, and the drain electrode is electrically connected to the fourth node N4.

[0098] When the fifth transistor ST5, the first transistor ST1, and the sixth transistor ST6 are all turned on, a driving current can be supplied to the light emitting element ED.

[0099] The seventh transistor ST7 is turned on by a fourth gate signal GB[n] from the fourth gate line GBL to electrically connect a fourth node N4, which is a first electrode of the light-emitting element ED, to the second initialization voltage line VIL2. The seventh transistor ST7 is turned on based on the fourth gate signal GB[n] to discharge the first electrode of the light-emitting element ED to the second initialization voltage. The gate electrode of the seventh transistor ST7 is electrically connected to the fourth gate line GBL, the source electrode is electrically connected to the fourth node N4, and the drain electrode is electrically connected to the second initialization voltage line VIL2.

[0100] The eighth transistor ST8 may be turned on by a fourth gate signal GB[n] from the fourth gate line GBL to electrically connect the bias voltage line VBL to a first node N1, which is the source electrode of the first transistor ST1. The eighth transistor ST8 may be turned on based on the fourth gate signal GB[n] to supply a bias voltage to the first node N1. The eighth transistor ST8 may improve hysteresis of the first transistor ST1 by supplying a bias voltage to the source electrode of the first transistor ST1. The gate electrode of the eighth transistor ST8 may be electrically connected to the fourth gate line GBL, the source electrode may be electrically connected to the bias voltage line VBL, and the drain electrode may be electrically connected to the first node N1.

[0101] The first transistor ST1, the second transistor ST2, the third-first transistor ST3-1, the third-second transistor ST3-2, the fourth-first transistor ST4-1, the fourth-second transistor ST4-2, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8 may each include a silicon-based active layer. For example, the first transistor ST1, the second transistor ST2, the third-first transistor ST3-1, the third-second transistor ST3-2, the fourth-first transistor ST4-1, the fourth-second transistor ST4-2, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8 may each include an active layer made of low-temperature polycrystalline silicon (LTPS). An active layer made of low-temperature polycrystalline silicon has high electron mobility and excellent turn-on characteristics. Therefore, by including transistors with excellent turn-on characteristics, the display device 10 can stably and efficiently drive the multiple pixels SP.

[0102] The first transistor ST1, the second transistor ST2, the third-first transistor ST3-1, the third-second transistor ST3-2, the fourth-first transistor ST4-1, the fourth-second transistor ST4-2, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8 correspond to p-type transistors. For example, the first transistor ST1, the second transistor ST2, the third-first transistor ST3-1, the third-second transistor ST3-2, the fourth-first transistor ST4-1, the fourth-second transistor ST4-2, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8 can output a current flowing into a source electrode to a drain electrode based on a gate low voltage applied to a gate electrode.

[0103] As another example, at least one of the first transistor ST1, the second transistor ST2, the third-first transistor ST3-1, the third-second transistor ST3-2, the fourth-first transistor ST4-1, the fourth-second transistor ST4-2, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8 may include an oxide-based active layer. The transistor including the oxide-based active layer may have a coplanar structure with a gate electrode disposed thereon. The transistor including the oxide-based active layer corresponds to an n-type transistor and may output a current flowing into the drain electrode to the source electrode based on a gate high voltage applied to the gate electrode.

[0104] The storage capacitor CST may be electrically connected between a third node N3, which is the gate electrode of the first transistor ST1, and the driving voltage line VDDL. For example, a first capacitor electrode of the storage capacitor CST is electrically connected to the third node N3, and a second capacitor electrode of the storage capacitor CST is electrically connected to the driving voltage line VDDL, thereby maintaining a potential difference between the driving voltage line VDDL and the gate electrode of the first transistor ST1.

[0105] 6 in addition to FIG. 5, when the display device 10 is driven at a predetermined driving frequency, one frame period may include at least one scanning interval SCP and at least one blanking interval BLP. The scanning interval SCP may include first to fifth periods t1 to t5, and the blanking interval BLP may include sixth and seventh periods t6 and t7.

[0106] The 4-1st transistor ST4-1 and the 4-2nd transistor ST4-2 may receive a low-level third gate signal GI[n] during the first period t1. The 4-1st transistor ST4-1 and the 4-2nd transistor ST4-2 are turned on based on the low-level third gate signal GI[n] and can discharge the third node N3, which is the gate electrode of the first transistor ST1, to the first initialization voltage. Therefore, the 4-1st transistor ST4-1 and the 4-2nd transistor ST4-2 can initialize the gate electrode of the first transistor ST1 during the first period t1.

[0107] The second transistor ST2 may receive the first gate signal GW[n] at a low level during the second period t2, and may be turned on based on the first gate signal GW[n] at a low level to supply the data voltage to the first node N1, which is the source electrode of the first transistor ST1.

[0108] The third-1 transistor ST3-1 and the third-2 transistor ST3-2 may receive the low-level second gate signal GC[n] during the third period t3, and may be turned on based on the low-level second gate signal GC[n] to electrically connect the second node N2 and the third node N3.

[0109] The seventh transistor ST7 may receive a low-level fourth gate signal GB[n] during the fourth period t4. The fourth gate signal GB[n] may fall stepwise during the fourth period t4. The seventh transistor ST7 is turned on based on the low-level fourth gate signal GB[n] to discharge the first electrode of the light-emitting element ED to the second initialization voltage. Therefore, the seventh transistor ST7 may initialize the first electrode of the light-emitting element ED during the fourth period t4.

[0110] The eighth transistor ST8 may receive a fourth gate signal GB[n] of a low level during a fourth period t4. The eighth transistor ST8 may be turned on based on the fourth gate signal GB[n] of a low level and supply a bias voltage to the first node N1, which is the source electrode of the first transistor ST1. The eighth transistor ST8 may set an operating point or operating conditions of the first transistor ST1 during the fourth period t4. The eighth transistor ST8 may prevent a change in the characteristics of the first transistor ST1 due to bias stress and improve hysteresis.

[0111] When the source electrode of the first transistor ST1 receives the data voltage VDATA, the source-gate voltage Vsg of the first transistor ST1 corresponds to the difference voltage (VDATA-VI1) between the data voltage VDATA and the first initialization voltage VI1. The source-gate voltage Vsg of the first transistor ST1 becomes greater than a threshold voltage (hereinafter referred to as "Vth"), and the first transistor ST1 is turned on (VDATA-VI1>=Vth). Therefore, at the moment when the second transistor ST2 is turned on during the second period t2, the source-drain current (Isd) of the first transistor ST1 is determined according to the data voltage VDATA, the first initialization voltage VI1, and the threshold voltage (Vth) of the first transistor ST1 (Isd=k×(VDATA-VI1-Vth)). 2 The first transistor ST1 may supply a source-drain current (Isd) to the second node N2 until the source-gate voltage Vsg reaches the threshold voltage (Vth) of the first transistor ST1. Then, the third-1st transistor ST3-1 and the third-2nd transistor ST3-2 may be turned on during a third period t3 to supply the voltage of the second node N2 to the third node N3. In this manner, while the first transistor ST1 is turned on, the voltage of the third node N3 and the source-drain current (Isd) of the first transistor ST1 may change, and the voltage of the third node N3 may eventually converge to the difference voltage (VDATA-Vth) between the data voltage VDATA and the threshold voltage (Vth) of the first transistor ST1.

[0112] The light-emitting signal EM[n] may have a gate low voltage during the fifth period t5. The light-emitting signal EM[n] may fall stepwise during the fifth period t5. When the light-emitting signal EM[n] has a low level, the fifth and sixth transistors ST5 and ST6 may be turned on to supply a driving current to the light-emitting element ED.

[0113] The fourth gate signal GB[n] has a gate low voltage during the sixth period t6 of the blanking period BLP. Therefore, the seventh transistor ST7 can initialize the fourth node N4, which is the first electrode of the light emitting element ED, to the second initialization voltage even during the blanking period BLP. The eighth transistor ST8 can supply a bias voltage to the first node N1, which is the source electrode of the first transistor ST1, even during the blanking period BLP, thereby improving hysteresis of the first transistor ST1.

[0114] The light-emitting signal EM[n] has a gate low voltage during the seventh period t7 of the blanking interval BLP. Therefore, when the light-emitting signal EM[n] has a low level, the fifth and sixth transistors ST5 and ST6 are turned on to supply a driving current to the first electrode of the initialized light-emitting element ED.

[0115] FIG. 7 is a cross-sectional view showing a part of a display device according to an embodiment.

[0116] Referring to FIG. 7, the display panel 100 may include a substrate SUB, a barrier layer BR, a first metal layer BML1, a first buffer layer BF1, a second buffer layer BF2, a hydrogen passivation layer HPL, a first transistor ST1, a third-1 transistor ST3-1, a third-2 transistor ST3-2, a capping layer CPL, a first gate insulating film GI1, a first bias electrode BE1, a second bias electrode BE2, a second gate insulating film GI2, a capacitor electrode CPE, an interlayer insulating film ILD, a first connection electrode CNE1, a second connection electrode CNE2, a third connection electrode CNE3, a first via layer VIA1, an anode connection electrode ANE, a second via layer VIA2, a pixel defining layer PDL, a light emitting element ED, and an encapsulating layer TFEL.

[0117] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that allows bending, folding, rolling, etc. For example, the substrate SUB may include, but is not limited to, a glass material or a metal material. As another example, the substrate SUB may include a polymer resin such as polyimide (PI).

[0118] A barrier layer BR may be disposed on the substrate SUB. The barrier layer BR may planarize the surface of the substrate SUB and protect the pixel circuits. The barrier layer BR may include an inorganic insulating material that can prevent the penetration of air or moisture. The barrier layer BR may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited to these.

[0119] The first metal layer BML1 may be disposed on the barrier layer BR. The first metal layer BML1 may overlap the semiconductor region ACT3-1 of the 3-1 transistor ST3-1 and the semiconductor region ACT3-2 of the 3-2 transistor ST3-2. A portion of the first metal layer BML1 may be the gate electrode GE3-1 of the 3-1 transistor ST3-1, and another portion of the first metal layer BML1 may be the gate electrode GE3-2 of the 3-2 transistor ST3-2. The first metal layer BML1 may be electrically connected to the second gate line GCL to receive the second gate signal GC[n]. The first metal layer BML1 may be formed of a single layer or multiple layers (stacked layers) including at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0120] The first buffer layer BF1 is disposed on the first metal layer BML1 and the barrier layer BR. The first buffer layer BF1 may include an inorganic insulating material that can prevent the penetration of air or moisture. The first buffer layer BF1 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited to these.

[0121] The second buffer layer BF2 may be disposed on the first buffer layer BF1. The second buffer layer BF2 may include an inorganic insulating material capable of preventing the penetration of air or moisture. The second buffer layer BF2 may include, but is not limited to, at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer. For example, the first buffer layer BF1 may include a silicon nitride layer, and the second buffer layer BF2 may include, but is not limited to, a silicon oxide layer.

[0122] The hydrogen passivation layer HPL is disposed on the second buffer layer BF2. The thickness of the hydrogen passivation layer HPL may be, but is not limited to, approximately 50 angstroms (Å) or less. The hydrogen passivation layer HPL may be in direct contact with the lower surfaces of the semiconductor region ACT1 of the first transistor ST1, the semiconductor region ACT3-1 of the third-first transistor ST3-1, and the semiconductor region ACT3-2 of the third-second transistor ST3-2. Because no protrusions are formed on the lower surfaces of the semiconductor region ACT1 of the first transistor ST1, the semiconductor region ACT3-1 of the third-first transistor ST3-1, and the semiconductor region ACT3-2 of the third-second transistor ST3-2, the hydrogen passivation layer HPL may have a flat surface.

[0123] The hydrogen passivation layer HPL may have a high hydrogen content. The hydrogen passivation layer HPL may include silicon oxide having a high hydrogen content. For example, the ratio of nitrogen dioxide (N2O) to silane (SiH4) (N2O / SiH4) in the hydrogen passivation layer HPL may be, but is not limited to, 10 to 40. As another example, the hydrogen passivation layer HPL may be formed by hydrogen implantation (H-implantation) or hydrogen plasma treatment (H2 plasma treatment). The hydrogen in the hydrogen passivation layer HPL bonds with silicon on the surfaces of the semiconductor region ACT3-1 of the third-first transistor ST3-1 and the semiconductor region ACT3-2 of the third-second transistor ST3-2, thereby reducing dangling bonds in the semiconductor region ACT3-1 of the third-first transistor ST3-1 and the semiconductor region ACT3-2 of the third-second transistor ST3-2. Therefore, the hydrogen passivation layer HPL can eliminate interface defects between the semiconductor region ACT3-1 of the third-first transistor ST3-1 and the semiconductor region ACT3-2 of the third-second transistor ST3-2, thereby improving leakage current characteristics and low-frequency characteristics. By including the hydrogen passivation layer HPL, the display device 10 can prevent leakage current from flowing through the third-first transistor ST3-1 and the third-second transistor ST3-2, and can stably maintain the voltage inside the pixel SP.

[0124] The semiconductor region ACT1, source electrode SE1, and drain electrode DE1 of the first transistor ST1 may be disposed on the hydrogen passivation layer HPL. The semiconductor region ACT1 of the first transistor ST1 may overlap the gate electrode GE1 in the thickness direction and be insulated from the gate electrode GE1 by the capping layer CPL and the first gate insulating film GI1. The source electrode SE1 and the drain electrode DE1 may be formed by converting the material of the semiconductor region ACT1 into a conductor. The drain electrode DE1 of the first transistor ST1 may be electrically connected to the drain electrode DE3-2 of the third-second transistor ST3-2 via the second node N2 of FIG. 5.

[0125] The semiconductor region ACT3-1, source electrode SE3-1, and drain electrode DE3-1 of the third-first transistor ST3-1 are disposed on the hydrogen passivation layer HPL. A portion of the first metal layer BML1 may be the gate electrode GE3-1 of the third-first transistor ST3-1. The semiconductor region ACT3-1 of the third-first transistor ST3-1 may overlap the gate electrode GE3-1 in the thickness direction and may be insulated from the gate electrode GE3-1 by a first buffer layer BF1 and a second buffer layer BF2. The source electrode SE3-1 and the drain electrode DE3-1 may be formed by converting the material of the semiconductor region ACT3-1 into a conductor. The drain electrode DE3-1 of the third-first transistor ST3-1 may be formed integrally with the source electrode SE3-2 of the third-second transistor ST3-2. The drain electrode DE3-1 of the 3-1st transistor ST3-1 and the source electrode SE3-2 of the 3-2nd transistor ST3-2 may overlap the first metal layer BML1, but this is not limitative.

[0126] The semiconductor region ACT3-2, source electrode SE3-2, and drain electrode DE3-2 of the third-second transistor ST3-2 may be disposed on the hydrogen passivation layer HPL. Another part of the first metal layer BML1 may be the gate electrode GE3-2 of the third-second transistor ST3-2. The semiconductor region ACT3-2 of the third-second transistor ST3-2 may overlap the gate electrode GE3-2 in the thickness direction and be insulated from the gate electrode GE3-2 by the first buffer layer BF1 and the second buffer layer BF2. The source electrode SE3-2 and the drain electrode DE3-2 may be formed by converting the material of the semiconductor region ACT3-2 into a conductor.

[0127] The capping layer CPL may be disposed on the semiconductor region ACT1, source electrode SE1, and drain electrode DE1 of the first transistor ST1, the semiconductor region ACT3-1, source electrode SE3-1, and drain electrode DE3-1 of the third-first transistor ST3-1, and the semiconductor region ACT3-2, source electrode SE3-2, and drain electrode DE3-2 of the third-second transistor ST3-2. The capping layer CPL may have the same planar pattern as the semiconductor region ACT1, source electrode SE1, and drain electrode DE1 of the first transistor ST1, the semiconductor region ACT3-1, source electrode SE3-1, and drain electrode DE3-1 of the third-first transistor ST3-1, and the semiconductor region ACT3-2, source electrode SE3-2, and drain electrode DE3-2 of the third-second transistor ST3-2. The capping layer CPL may cover protrusions formed on the semiconductor region ACT1, source electrode SE1, and drain electrode DE1 of the first transistor ST1. When the semiconductor region ACT1 of the first transistor ST1 includes low-temperature polycrystalline silicon (LTPS), an amorphous silicon layer disposed on the substrate SUB may be melted and crystallized by a laser. In this case, as the amorphous silicon layer is crystallized, grains may grow, and protrusions may be formed at the grain boundaries between the grains. The capping layer CPL covers the protrusions of the first transistor ST1, thereby preventing an electric field from concentrating on the protrusions when the first transistor ST1 is driven, thereby improving the driving range of the first transistor ST1. Therefore, by including the capping layer CPL, the display device 10 can precisely control the grayscale of light emitted from the light emitting element ED. The capping layer CPL may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited to these.

[0128] The first gate insulating film GI1 may be disposed on the capping layer CPL and the hydrogen passivation layer HPL. The first gate insulating film GI1 may insulate the gate electrode GE1 and the semiconductor region ACT1 of the first transistor ST1. The first gate insulating film GI1 may include, but is not limited to, at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer. The first gate insulating film GI1 may include, but is not limited to, the same material as the capping layer CPL.

[0129] When the first gate insulating film GI1 is formed by a deposition process, the thickness of the first gate insulating film GI1 on the hydrogen passivation layer HPL and the thickness of the first gate insulating film GI1 on the capping layer CPL may be substantially the same. The first thickness T1 may be greater than the second thickness T2. Here, the first thickness T1 is the sum of the thicknesses of the capping layer CPL and the first gate insulating film GI1 that overlap each other, and the second thickness T2 may be the thickness of the first gate insulating film GI1 that does not overlap the capping layer CPL. The thickness of the capping layer CPL is determined by the difference between the first thickness T1 and the second thickness T2. The thickness of the capping layer CPL may be about 20 to 200 angstroms (Å), preferably about 100 angstroms (Å). Therefore, even if the first gate insulating film GI1 and the capping layer CPL contain the same material, it can be seen that the capping layer CPL is disposed on the first transistor ST1, the 3-1 transistor ST3-1, and the 3-2 transistor ST3-2 to cover the protrusions of the first transistor ST1, the 3-1 transistor ST3-1, and the 3-2 transistor ST3-2.

[0130] The first bias electrode BE1, the second bias electrode BE2, and the gate electrode GE1 of the first transistor ST1 may be disposed on the first gate insulating film GI1. The first bias electrode BE1, the second bias electrode BE2, and the gate electrode GE1 of the first transistor ST1 may be formed of the same material in the same layer, but are not limited to this.

[0131] The first bias electrode BE1 may be a bias electrode of the third-first transistor ST3-1. The first bias electrode BE1 may overlap the semiconductor region ACT3-1 of the third-first transistor ST3-1. The first bias electrode BE1 may be electrically connected to the driving voltage line VDDL and may receive a driving voltage from the driving voltage line VDDL. Therefore, the first bias electrode BE1 may stabilize the electric field of the third-first transistor ST3-1 and improve the output characteristics.

[0132] The second bias electrode BE2 may be a bias electrode of the 3-2nd transistor ST3-2. The second bias electrode BE2 may overlap the semiconductor region ACT3-2 of the 3-2nd transistor ST3-2. The second bias electrode BE2 may be electrically connected to the driving voltage line VDDL and may receive a driving voltage from the driving voltage line VDDL. Therefore, the second bias electrode BE2 may stabilize the electric field of the 3-2nd transistor ST3-2 and improve the output characteristics.

[0133] The second gate insulating film GI2 may be disposed on the first bias electrode BE1, the second bias electrode BE2, the gate electrode GE1 of the first transistor ST1, and the first gate insulating film GI1. The second gate insulating film GI2 may insulate the capacitor electrode CPE and the gate electrode GE1 of the first transistor ST1. The second gate insulating film GI2 may include contact holes through which the first and second connection electrodes CNE1 and CNE2 pass. The second gate insulating film GI2 may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited to these.

[0134] The capacitor electrode CPE may be disposed on the second gate insulating film GI2 and overlap the gate electrode GE1 of the first transistor ST1. The capacitor electrode CPE and the gate electrode GE1 of the first transistor ST1 may form a capacitance. For example, the storage capacitor CST of FIG. 5 may be formed between the gate electrode GE1 of the first transistor ST1 and the capacitor electrode CPE. The gate electrode GE1 of the first transistor ST1 may be electrically connected to the third node N3 as a first capacitor electrode of the storage capacitor CST, and the capacitor electrode CPE may be electrically connected to the driving voltage line VDDL as a second capacitor electrode of the storage capacitor CST.

[0135] The interlayer insulating film ILD may be disposed on the capacitor electrode CPE and the second gate insulating film GI2. The interlayer insulating film ILD may include contact holes through which the first and second connection electrodes CNE1 and CNE2 pass. The contact holes in the interlayer insulating film ILD may be connected to contact holes in the second gate insulating film GI2.

[0136] The first connection electrode CNE1 may be disposed on the interlayer insulating film ILD. The first connection electrode CNE1 may be inserted into a contact hole formed in the interlayer insulating film ILD and the second gate insulating film GI2 to contact the first bias electrode BE1. The first connection electrode CNE1 may be electrically connected between the first bias electrode BE1 and the driving voltage line VDDL. Therefore, the first connection electrode CNE1 may supply the driving voltage received from the driving voltage line VDDL to the first bias electrode BE1.

[0137] The second connection electrode CNE2 may be disposed on the interlayer insulating film ILD and spaced apart from the first connection electrode CNE1. The second connection electrode CNE2 may be inserted into a contact hole formed in the interlayer insulating film ILD and the second gate insulating film GI2 to contact the second bias electrode BE2. The second connection electrode CNE2 may be electrically connected between the second bias electrode BE2 and the driving voltage line VDDL. Therefore, the second connection electrode CNE2 may supply the driving voltage received from the driving voltage line VDDL to the second bias electrode BE2.

[0138] The third connection electrode CNE3 may be disposed on the interlayer insulating film ILD and spaced apart from the first and second connection electrodes CNE1 and CNE2. The third connection electrode CNE3 may electrically connect the pixel circuit of the pixel SP and the anode connection electrode ANE. For example, the third connection electrode CNE3 may be electrically connected to the fourth node N4 in FIG. 5. Therefore, the third connection electrode CNE3 may supply the driving current received from the pixel circuit of the pixel SP to the light-emitting element ED.

[0139] The first via layer VIA1 may be disposed on the first to third connection electrodes CNE1, CNE2, and CNE3 and the interlayer insulating film ILD. For example, the first via layer VIA1 may include a contact hole through which the anode connection electrode ANE penetrates. For example, the first via layer VIA1 may include, but is not limited to, an organic insulating material such as polyimide (PI).

[0140] The anode connection electrode ANE may be disposed on the first via layer VIA1. The anode connection electrode ANE may electrically connect the pixel electrode PE of the light-emitting element ED and the third connection electrode CNE3. The anode connection electrode ANE may be inserted into a contact hole provided in the first via layer VIA1 and contact the third connection electrode CNE3. Therefore, the anode connection electrode ANE may supply the driving current received from the pixel circuit of the pixel SP to the light-emitting element ED.

[0141] The second via layer VIA2 may be disposed on the anode connection electrode ANE and the second via layer VIA2. For example, the second via layer VIA2 may include a contact hole through which the pixel electrode PE passes. For example, the second via layer VIA2 may include, but is not limited to, an organic insulating material such as polyimide (PI).

[0142] A pixel definition film PDL may be disposed on the second via layer VIA2. The pixel definition film PDL may define a plurality of light-emitting regions or a plurality of opening regions. The pixel definition film PDL may separate and insulate the pixel electrodes PE of the plurality of pixels SP.

[0143] The light-emitting element ED may be disposed on the second via layer VIA2. Each light-emitting element ED of the plurality of pixels SP may include a pixel electrode PE, an emitting layer EL, and a common electrode CE. The pixel electrode PE is disposed on the second via layer VIA2. The pixel electrode PE may overlap one of the plurality of light-emitting areas defined by the pixel defining film PDL. The pixel electrode PE may receive a driving current from the pixel circuit of the pixel SP via the anode connecting electrode ANE and the third connecting electrode CNE3.

[0144] The light-emitting layer EL may be disposed on the pixel electrode PE. For example, the light-emitting layer EL may be, but is not limited to, an organic light-emitting layer made of an organic material. When the light-emitting layer EL corresponds to an organic light-emitting layer, when the pixel circuit of the pixel SP applies a predetermined voltage to the pixel electrode PE and the common electrode CE receives a common voltage or a cathode voltage, holes and electrons can move to the organic light-emitting layer EL via the hole transport layer and the electron transport layer, respectively, and the holes and electrons can combine with each other in the organic light-emitting layer EL to emit light.

[0145] The common electrode CE may be disposed on the light-emitting layer EL. For example, the common electrode CE may be realized as an electrode common to all pixels SP, rather than being divided into sections for each pixel SP. The common electrode CE may be disposed on the light-emitting layer EL in the light-emitting regions, and may be disposed on the pixel defining layer PDL in the region other than the light-emitting regions.

[0146] The encapsulation layer TFEL is disposed on the common electrode CE and can cover the light-emitting elements ED. The encapsulation layer TFEL includes at least one inorganic film to prevent oxygen or moisture from penetrating into the light-emitting elements ED. The encapsulation layer TFEL includes at least one organic film to protect the light-emitting elements ED from foreign matter such as dust.

[0147] 8 is a cross-sectional view showing another part of the display device according to one embodiment. In the following, the same configurations as those described above will be briefly explained or omitted.

[0148] Referring to FIG. 8, the display panel 100 may include a substrate SUB, a barrier layer BR, a second metal layer BML2, a first buffer layer BF1, a second buffer layer BF2, a hydrogen passivation layer HPL, a 4-1 transistor ST4-1, a 4-2 transistor ST4-2, a capping layer CPL, a first gate insulating film GI1, a third bias electrode BE3, a fourth bias electrode BE4, a second gate insulating film GI2, an interlayer insulating film ILD, a fourth connection electrode CNE4, a fifth connection electrode CNE5, a third connection electrode CNE3, a first via layer VIA1, an anode connection electrode ANE, a second via layer VIA2, a pixel defining film PDL, a light-emitting element ED, and an encapsulating layer TFEL.

[0149] The second metal layer BML2 may be disposed on the barrier layer BR. The second metal layer BML2 may overlap the semiconductor region ACT4-1 of the 4-1 transistor ST4-1 and the semiconductor region ACT4-2 of the 4-2 transistor ST4-2. A portion of the second metal layer BML2 may be the gate electrode GE4-1 of the 4-1 transistor ST4-1, and another portion of the second metal layer BML2 may be the gate electrode GE4-2 of the 4-2 transistor ST4-2. The second metal layer BML2 may be electrically connected to the third gate line GIL to receive the third gate signal GI[n]. The second metal layer BML2 may be formed of a single layer or multiple layers including at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), palladium (Pd), indium (In), neodymium (Nd), and copper (Cu).

[0150] The hydrogen passivation layer HPL may be disposed on the second buffer layer BF2. The thickness of the hydrogen passivation layer HPL may be, but is not limited to, approximately 50 angstroms (Å) or less. The hydrogen passivation layer HPL may be in direct contact with the lower surfaces of the semiconductor region ACT4-1 of the 4-1 transistor ST4-1 and the semiconductor region ACT4-2 of the 4-2 transistor ST4-2. Since no protrusions are formed on the lower surfaces of the semiconductor region ACT4-1 of the 4-1 transistor ST4-1 and the semiconductor region ACT4-2 of the 4-2 transistor ST4-2, the hydrogen passivation layer HPL may have a flat surface.

[0151] The hydrogen passivation layer HPL may have a high hydrogen content. The hydrogen passivation layer HPL may include silicon oxide with a high hydrogen content. For example, the ratio of nitrogen dioxide (N2O) to silane (SiH4) (N2O / SiH4) in the hydrogen passivation layer HPL may be, but is not limited to, 10 to 40. As another example, the hydrogen passivation layer HPL may be formed by hydrogen implantation (H-implantation) or hydrogen plasma treatment (H2 plasma treatment).

[0152] The hydrogen in the hydrogen passivation layer HPL bonds with silicon on the surfaces of the semiconductor region ACT4-1 of the 4-1 transistor ST4-1 and the semiconductor region ACT4-2 of the 4-2 transistor ST4-2, thereby reducing dangling bonds in the semiconductor region ACT4-1 of the 4-1 transistor ST4-1 and the semiconductor region ACT4-2 of the 4-2 transistor ST4-2. Therefore, the hydrogen passivation layer HPL eliminates interface defects in the semiconductor region ACT4-1 of the 4-1 transistor ST4-1 and the semiconductor region ACT4-2 of the 4-2 transistor ST4-2, improving leakage current characteristics and low-frequency characteristics. By including the hydrogen passivation layer HPL, the display device 10 can prevent leakage current from flowing through the 4-1 transistor ST4-1 and the 4-2 transistor ST4-2, thereby maintaining a stable voltage within the pixel SP.

[0153] The semiconductor region ACT4-1, source electrode SE4-1, and drain electrode DE4-1 of the 4-1st transistor ST4-1 are disposed on the hydrogen passivation layer HPL. A portion of the second metal layer BML2 may be the gate electrode GE4-1 of the 4-1st transistor ST4-1. The semiconductor region ACT4-1 of the 4-1st transistor ST4-1 may overlap the gate electrode GE4-1 in the thickness direction and may be insulated from the gate electrode GE4-1 by the first buffer layer BF1 and the second buffer layer BF2. The source electrode SE4-1 and the drain electrode DE4-1 may be formed by converting the material of the semiconductor region ACT4-1 into a conductor. The drain electrode DE4-1 of the 4-1st transistor ST4-1 may be formed integrally with the source electrode SE4-2 of the 4-2nd transistor ST4-2. The drain electrode DE4-1 of the 4-1st transistor ST4-1 and the source electrode SE4-2 of the 4-2nd transistor ST4-2 may overlap the second metal layer BML2, but this is not limitative.

[0154] The semiconductor region ACT4-2, source electrode SE4-2, and drain electrode DE4-2 of the 4-2nd transistor ST4-2 may be disposed on the hydrogen passivation layer HPL. Another part of the second metal layer BML2 may be the gate electrode GE4-2 of the 4-2nd transistor ST4-2. The semiconductor region ACT4-2 of the 4-2nd transistor ST4-2 may overlap the gate electrode GE4-2 in the thickness direction and be insulated from the gate electrode GE4-2 by the first buffer layer BF1 and the second buffer layer BF2. The source electrode SE4-2 and the drain electrode DE4-2 may be provided by converting the material of the semiconductor region ACT4-2 into a conductor.

[0155] The capping layer CPL may be disposed on the semiconductor region ACT4-1, source electrode SE4-1, and drain electrode DE4-1 of the 4-1th transistor ST4-1, and on the semiconductor region ACT4-2, source electrode SE4-2, and drain electrode DE4-2 of the 4-2th transistor ST4-2. The capping layer CPL may have the same planar pattern as the semiconductor region ACT4-1, source electrode SE4-1, and drain electrode DE4-1 of the 4-1st transistor ST4-1, and on the semiconductor region ACT4-2, source electrode SE4-2, and drain electrode DE4-2 of the 4-2th transistor ST4-2. The capping layer CPL may include at least one of, but is not limited to, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

[0156] When the first gate insulating film GI1 is formed by a deposition process, the thickness of the first gate insulating film GI1 on the hydrogen passivation layer HPL and the thickness of the first gate insulating film GI1 on the capping layer CPL may be substantially the same. The first thickness T1 may be greater than the second thickness T2. Here, the first thickness T1 is the sum of the thicknesses of the capping layer CPL and the first gate insulating film GI1 that overlap each other, and the second thickness T2 may be the thickness of the first gate insulating film GI1 that does not overlap the capping layer CPL. The thickness of the capping layer CPL is determined by the difference between the first thickness T1 and the second thickness T2. The thickness of the capping layer CPL may be about 20 to 200 angstroms (Å), preferably about 100 angstroms (Å). Therefore, even if the first gate insulating film GI1 and the capping layer CPL contain the same material, it can be seen that the capping layer CPL is disposed on the 4-1 transistor ST4-1 and the 4-2 transistor ST4-2 to cover the protrusions of the 4-1 transistor ST4-1 and the 4-2 transistor ST4-2.

[0157] The third bias electrode BE3 and the fourth bias electrode BE4 may be disposed on the first gate insulating film GI1. The first to fourth bias electrodes BE1, BE2, BE3, and BE4 and the gate electrode GE1 of the first transistor ST1 may be formed of the same material in the same layer, but are not limited thereto.

[0158] The third bias electrode BE3 may be a bias electrode of the 4-1st transistor ST4-1. The third bias electrode BE3 may overlap the semiconductor region ACT4-1 of the 4-1st transistor ST4-1. The third bias electrode BE3 may be electrically connected to the driving voltage line VDDL and may receive a driving voltage from the driving voltage line VDDL. Therefore, the third bias electrode BE3 may stabilize the electric field of the 4-1st transistor ST4-1 and improve the output characteristics.

[0159] The fourth bias electrode BE4 may be a bias electrode of the 4-2nd transistor ST4-2. The fourth bias electrode BE4 may overlap the semiconductor region ACT4-2 of the 4-2nd transistor ST4-2. The fourth bias electrode BE4 may be electrically connected to the drive voltage line VDDL and may receive a drive voltage from the drive voltage line VDDL. Therefore, the fourth bias electrode BE4 can stabilize the electric field of the 4-2nd transistor ST4-2 and improve the output characteristics.

[0160] The fourth connection electrode CNE4 may be disposed on the interlayer insulating film ILD. The fourth connection electrode CNE4 may be inserted into a contact hole formed in the interlayer insulating film ILD and the second gate insulating film GI2 to contact the third bias electrode BE3. The fourth connection electrode CNE4 may be electrically connected between the third bias electrode BE3 and the driving voltage line VDDL. Therefore, the fourth connection electrode CNE4 can supply the driving voltage received from the driving voltage line VDDL to the third bias electrode BE3.

[0161] The fifth connection electrode CNE5 may be disposed on the interlayer insulating film ILD at a distance from the fourth connection electrode CNE4. The fifth connection electrode CNE5 may be inserted into a contact hole formed in the interlayer insulating film ILD and the second gate insulating film GI2 to contact the fourth bias electrode BE4. The fifth connection electrode CNE5 may be electrically connected between the fourth bias electrode BE4 and the driving voltage line VDDL. Therefore, the fifth connection electrode CNE5 may supply the driving voltage received from the driving voltage line VDDL to the fourth bias electrode BE4.

[0162] FIG. 9 is a graph showing transfer characteristics of first and second test transistors in a display device according to an embodiment.

[0163] 9, the first test transistor TR1 may be the third-first transistor ST3-1, the third-second transistor ST3-2, the fourth-first transistor ST4-1, or the fourth-second transistor ST4-2 of the display device 10. The second test transistor TR2 may be a transistor not adjacent to a hydrogen passivation layer.

[0164] The bottom surface of the first test transistor TR1 may be in contact with the hydrogen passivation layer HPL. Because the bottom surface of the first test transistor TR1 does not have any protrusions, the hydrogen passivation layer HPL may have a flat surface. Hydrogen in the hydrogen passivation layer HPL bonds with silicon on the surface of the semiconductor region of the first test transistor TR1, thereby reducing dangling bonds in the first test transistor TR1. Therefore, the hydrogen passivation layer HPL eliminates interface defects in the semiconductor region of the first test transistor TR1 and improves leakage current characteristics and low-frequency characteristics. For example, the first and second test transistors TR1 and TR2 correspond to p-type transistors and can output current flowing into the source electrode to the drain electrode based on a gate low voltage applied to the gate electrode. When the gate-source voltage (Vgs) of a p-type transistor is positive, the drain-source current (Ids) corresponds to leakage current.

[0165] In a section where the gate-source voltage (Vgs) has a positive value, the leakage current of the first test transistor TR1 is smaller than the leakage current of the second test transistor TR2. Therefore, by including the hydrogen passivation layer HPL, the display device 10 can prevent leakage current from flowing through the 3-1 transistor ST3-1, the 3-2 transistor ST3-2, the 4-1 transistor ST4-1, and the 4-2 transistor ST4-2, thereby maintaining a stable voltage within the pixel SP.

[0166] FIG. 10 is a circuit diagram showing a pixel of a display device according to another embodiment.

[0167] 10, the display panel 100 may include a plurality of pixels SP arranged along p rows (p is a natural number) and q columns (q is a natural number), each of which may be connected to a first gate line GWL, a second gate line GCL, a third gate line GIL, a fourth gate line GBL, an emission control line EML, a data line DL, a driving voltage line VDDL, a first initialization voltage line VIL1, a second initialization voltage line VIL2, and a bias voltage line VBL.

[0168] The pixel SP may include a pixel circuit and a light-emitting element ED. The pixel circuit may include a first transistor ST1, a second transistor ST2, a third-first transistor ST3-1, a third-second transistor ST3-2, a fourth-first transistor ST4-1, a fourth-second transistor ST4-2, a fifth transistor ST5, a sixth transistor ST6, a seventh transistor ST7, an eighth transistor ST8, and a storage capacitor CST.

[0169] The first transistor ST1 may include a gate electrode, a source electrode, and a drain electrode. The first transistor ST1 can control a source-drain current (Isd, hereinafter referred to as "drive current") in response to a data voltage applied to the gate electrode. The drive current (Isd) flowing through the channel of the first transistor ST1 is proportional to the square of the difference between the voltage (Vsg) between the source electrode and gate electrode of the first transistor ST1 and the threshold voltage (Vth) of the first transistor ST1 (Isd=k×(Vsg-Vth)). 2 ) where k is a proportionality coefficient determined by the structure and physical characteristics of the first transistor ST1, Vsg is the source-gate voltage of the first transistor ST1, and Vth is the threshold voltage of the first transistor ST1.

[0170] The first transistor ST1 may include a bias electrode. The bias electrode of the first transistor ST1 may overlap a semiconductor region of the first transistor ST1. The bias electrode of the first transistor ST1 may be electrically connected to a drive voltage line VDDL and may receive a drive voltage from the drive voltage line VDDL. Therefore, the bias electrode of the first transistor ST1 may stabilize the electric field of the first transistor ST1 and improve output characteristics.

[0171] The light emitting element ED receives a driving current (Isd) to emit light, and the amount of light emitted or the brightness of the light emitting element ED is proportional to the magnitude of the driving current (Isd).

[0172] The light-emitting element ED may be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first and second electrodes. As another example, the light-emitting element ED may be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first and second electrodes. As yet another example, the light-emitting element ED may be a quantum dot light-emitting element including a first electrode, a second electrode, and a quantum dot light-emitting layer disposed between the first and second electrodes. As yet another example, the light-emitting element ED may be a micro light-emitting diode.

[0173] A first electrode of the light-emitting element ED may be electrically connected to the fourth node N4. The first electrode of the light-emitting element ED may be connected to the drain electrode of the sixth transistor ST6 and the source electrode of the seventh transistor ST7 via the fourth node N4. A second electrode of the light-emitting element ED may be connected to the low potential line VSSL. The second electrode of the light-emitting element ED may receive a low potential voltage from the potential line VSSL.

[0174] The second transistor ST2 may be turned on by a first gate signal GW[n] from the first gate line GWL to electrically connect the data line DL to a first node N1, which is the source electrode of the first transistor ST1. The second transistor ST2 may be turned on based on the first gate signal GW[n] to supply a data voltage to the first node N1. The gate electrode of the second transistor ST2 may be electrically connected to the first gate line GWL, the source electrode may be electrically connected to the data line DL, and the drain electrode may be electrically connected to the first node N1.

[0175] The 3-1 transistor ST3-1 and the 3-2 transistor ST3-2 may be turned on by a second gate signal GC[n] on the second gate line GCL to electrically connect the second node N2, which is the drain electrode of the first transistor ST1, to the third node N3, which is the gate electrode of the first transistor ST1. The gate electrode of the 3-1 transistor ST3-1 may be electrically connected to the second gate line GCL, the source electrode may be electrically connected to the third node N3, and the drain electrode may be electrically connected to the source electrode of the 3-2 transistor ST3-2. The gate electrode of the 3-2 transistor ST3-2 may be electrically connected to the second gate line GCL, the source electrode may be electrically connected to the drain electrode of the 3-1 transistor ST3-1, and the drain electrode may be electrically connected to the second node N2. The gate electrode of the 3-1 transistor ST3-1 and the gate electrode of the 3-2 transistor ST3-2 may be integrally formed.

[0176] The third-first transistor ST3-1 may include a bias electrode. The bias electrode of the third-first transistor ST3-1 may overlap a semiconductor region of the third-first transistor ST3-1. The bias electrode of the third-first transistor ST3-1 may be electrically connected to a drive voltage line VDDL and may receive a drive voltage from the drive voltage line VDDL. The bias electrode of the third-first transistor ST3-1 may provide high-potential characteristics to improve the output characteristics of the third-first transistor ST3-1. Therefore, the bias electrode of the third-first transistor ST3-1 may stabilize the electric field of the third-first transistor ST3-1 and improve the output characteristics.

[0177] The third-second transistor ST3-2 may include a bias electrode. The bias electrode of the third-second transistor ST3-2 may overlap the semiconductor region of the third-second transistor ST3-2. The bias electrode of the third-second transistor ST3-2 may be electrically connected to the gate electrode of the third-second transistor ST3-2 and may receive the second gate signal GC[n] from the second gate line GCL. The bias electrode of the third-second transistor ST3-2 may increase the electric field generated by the second gate signal GC[n] and improve the output characteristics of the third-second transistor ST3-2. Therefore, the bias electrode of the third-second transistor ST3-2 may stabilize the electric field of the third-second transistor ST3-2 and improve the output characteristics.

[0178] The third-1st transistor ST3-1 and the third-2nd transistor ST3-2 have excellent leakage current (Off current) characteristics. Therefore, the third-1st transistor ST3-1 and the third-2nd transistor ST3-2 can prevent leakage current from flowing at the third node N3, which is the gate electrode of the first transistor ST1, and can stably maintain the voltage inside the pixel SP. The leakage current characteristics of the third-1st transistor ST3-1 and the third-2nd transistor ST3-2 will be described in detail with reference to FIG. 11.

[0179] The 4-1 transistor ST4-1 and the 4-2 transistor ST4-2 may be turned on by a third gate signal GI[n] from the third gate line GIL to electrically connect the third node N3, which is the gate electrode of the first transistor ST1, to the first initialization voltage line VIL1. The gate electrode of the 4-1 transistor ST4-1 may be electrically connected to the third gate line GIL, the source electrode may be electrically connected to the third node N3, and the drain electrode may be electrically connected to the source electrode of the 4-2 transistor ST4-2. The gate electrode of the 4-2 transistor ST4-2 may be electrically connected to the third gate line GIL, the source electrode may be electrically connected to the drain electrode of the 4-1 transistor ST4-1, and the drain electrode may be electrically connected to the first initialization voltage line VIL1. The gate electrode of the 4-1 transistor ST4-1 and the gate electrode of the 4-2 transistor ST4-2 may be integrally formed.

[0180] The 4-1st transistor ST4-1 and the 4-2nd transistor ST4-2 may each include a bias electrode. The bias electrode of the 4-1st transistor ST4-1 may overlap the semiconductor region of the 4-1st transistor ST4-1, and the bias electrode of the 4-2nd transistor ST4-2 may overlap the semiconductor region of the 4-2nd transistor ST4-2. The bias electrodes of the 4-1st transistor ST4-1 and the 4-2nd transistor ST4-2 may be electrically connected to a drive voltage line VDDL and may receive a drive voltage from the drive voltage line VDDL. Therefore, the bias electrodes of the 4-1st transistor ST4-1 and the 4-2nd transistor ST4-2 may stabilize the electric fields of the 4-1st transistor ST4-1 and the 4-2nd transistor ST4-2, improving output characteristics.

[0181] The 4-1st transistor ST4-1 and the 4-2nd transistor ST4-2 have excellent leakage current (Off current) characteristics, and therefore, the 4-1st transistor ST4-1 and the 4-2nd transistor ST4-2 can prevent leakage current from flowing at the third node N3, which is the gate electrode of the first transistor ST1, and can stably maintain the voltage inside the pixel SP.

[0182] The fifth transistor ST5 may be turned on by an emission signal EM[n] of the emission control line EML to electrically connect the driving voltage line VDDL to a first node N1, which is the source electrode of the first transistor ST1. The gate electrode of the fifth transistor ST5 may be electrically connected to the emission control line EML, the source electrode may be electrically connected to the driving voltage line VDDL, and the drain electrode may be electrically connected to the first node N1.

[0183] The sixth transistor ST6 may be turned on by an emission signal EM[n] of the emission control line EML to electrically connect the second node N2, which is the drain electrode of the first transistor ST1, to the fourth node N4, which is the first electrode of the light-emitting element ED. The sixth transistor ST6 may have a gate electrode electrically connected to the emission control line EML, a source electrode electrically connected to the second node N2, and a drain electrode electrically connected to the fourth node N4.

[0184] When the fifth transistor ST5, the first transistor ST1, and the sixth transistor ST6 are all turned on, a driving current can be supplied to the light emitting element ED.

[0185] The seventh transistor ST7 is turned on by a fourth gate signal GB[n] from the fourth gate line GBL to electrically connect a fourth node N4, which is a first electrode of the light-emitting element ED, to the second initialization voltage line VIL2. The seventh transistor ST7 is turned on based on the fourth gate signal GB[n] to discharge the first electrode of the light-emitting element ED to the second initialization voltage. The gate electrode of the seventh transistor ST7 is electrically connected to the fourth gate line GBL, the source electrode is electrically connected to the fourth node N4, and the drain electrode is electrically connected to the second initialization voltage line VIL2.

[0186] The eighth transistor ST8 may be turned on by a fourth gate signal GB[n] from the fourth gate line GBL to electrically connect the bias voltage line VBL to a first node N1, which is the source electrode of the first transistor ST1. The eighth transistor ST8 may be turned on based on the fourth gate signal GB[n] to supply a bias voltage to the first node N1. The eighth transistor ST8 may improve hysteresis of the first transistor ST1 by supplying a bias voltage to the source electrode of the first transistor ST1. The gate electrode of the eighth transistor ST8 may be electrically connected to the fourth gate line GBL, the source electrode may be electrically connected to the bias voltage line VBL, and the drain electrode may be electrically connected to the first node N1.

[0187] The first transistor ST1, the second transistor ST2, the third-first transistor ST3-1, the third-second transistor ST3-2, the fourth-first transistor ST4-1, the fourth-second transistor ST4-2, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8 may each include a silicon-based active layer. For example, the first transistor ST1, the second transistor ST2, the third-first transistor ST3-1, the third-second transistor ST3-2, the fourth-first transistor ST4-1, the fourth-second transistor ST4-2, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8 may each include an active layer made of low-temperature polycrystalline silicon (LTPS). An active layer made of low-temperature polycrystalline silicon has high electron mobility and excellent turn-on characteristics. Therefore, by including transistors with excellent turn-on characteristics, the display device 10 can stably and efficiently drive the multiple pixels SP.

[0188] The first transistor ST1, the second transistor ST2, the third-first transistor ST3-1, the third-second transistor ST3-2, the fourth-first transistor ST4-1, the fourth-second transistor ST4-2, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8 correspond to p-type transistors. For example, the first transistor ST1, the second transistor ST2, the third-first transistor ST3-1, the third-second transistor ST3-2, the fourth-first transistor ST4-1, the fourth-second transistor ST4-2, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8 can output a current flowing into a source electrode to a drain electrode based on a gate low voltage applied to a gate electrode.

[0189] As another example, at least one of the first transistor ST1, the second transistor ST2, the third-first transistor ST3-1, the third-second transistor ST3-2, the fourth-first transistor ST4-1, the fourth-second transistor ST4-2, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8 may include an oxide-based active layer. The transistor including the oxide-based active layer may have a coplanar structure with a gate electrode disposed thereon. The transistor including the oxide-based active layer corresponds to an n-type transistor and can output a current flowing into the drain electrode to the source electrode based on a gate high voltage applied to the gate electrode.

[0190] The storage capacitor CST may be electrically connected between a third node N3, which is the gate electrode of the first transistor ST1, and a driving voltage line VDDL. For example, a first capacitor electrode of the storage capacitor CST is electrically connected to the third node N3, and a second capacitor electrode of the storage capacitor CST is electrically connected to the driving voltage line VDDL, thereby maintaining a potential difference between the driving voltage line VDDL and the gate electrode of the first transistor ST1.

[0191] 11 is a cross-sectional view showing a part of a display device according to another embodiment. In the following, the same configuration as that described above will be explained briefly or omitted.

[0192] Referring to FIG. 11, the display panel 100 may include a substrate SUB, a barrier layer BR, a first metal layer BML1, a third metal layer BML3, a first buffer layer BF1, a second buffer layer BF2, a hydrogen passivation layer HPL, a first transistor ST1, a third-1 transistor ST3-1, a third-2 transistor ST3-2, a capping layer CPL, a first gate insulating film GI1, a first bias electrode BE1, a second bias electrode BE2, a second gate insulating film GI2, a capacitor electrode CPE, an interlayer insulating film ILD, a first connection electrode CNE1, a third connection electrode CNE3, a sixth connection electrode CNE6, a first via layer VIA1, an anode connection electrode ANE, a second via layer VIA2, a pixel defining film PDL, a light-emitting element ED, and an encapsulating layer TFEL.

[0193] The first metal layer BML1 may be disposed on the barrier layer BR. The first metal layer BML1 may overlap the semiconductor region ACT3-1 of the 3-1 transistor ST3-1 and the semiconductor region ACT3-2 of the 3-2 transistor ST3-2. A portion of the first metal layer BML1 may be the gate electrode GE3-1 of the 3-1 transistor ST3-1, and another portion of the first metal layer BML1 may be the gate electrode GE3-2 of the 3-2 transistor ST3-2. The first metal layer BML1 may be electrically connected to the second gate line GCL to receive the second gate signal GC[n].

[0194] The third metal layer BML3 may be disposed on the barrier layer BR and spaced apart from the first metal layer BML1. The third metal layer BML3 may overlap the semiconductor region ACT1 of the first transistor ST1. The third metal layer BML3 may be a bias electrode of the first transistor ST1. The third metal layer BML3 may be electrically connected to the driving voltage line VDDL via the sixth connection electrode CNE6 and may receive a driving voltage from the driving voltage line VDDL. Therefore, the third metal layer BML3 may stabilize the electric field of the first transistor ST1 and improve output characteristics.

[0195] The hydrogen passivation layer HPL may be disposed on the second buffer layer BF2. The thickness of the hydrogen passivation layer HPL may be, but is not limited to, about 50 angstroms (Å) or less. The hydrogen passivation layer HPL may be in direct contact with the lower surfaces of the semiconductor region ACT1 of the first transistor ST1, the semiconductor region ACT3-1 of the 3-1 transistor ST3-1, and the semiconductor region ACT3-2 of the 3-2 transistor ST3-2. Because no protrusions are formed on the lower surfaces of the semiconductor region ACT1 of the first transistor ST1, the semiconductor region ACT3-1 of the 3-1 transistor ST3-1, and the semiconductor region ACT3-2 of the 3-2 transistor ST3-2, the hydrogen passivation layer HPL may have a flat surface.

[0196] The hydrogen passivation layer HPL may have a high hydrogen content. The hydrogen passivation layer HPL may include silicon oxide with a high hydrogen content. For example, the ratio of nitrogen dioxide (N2O) to silane (SiH4) (N2O / SiH4) in the hydrogen passivation layer HPL may be, but is not limited to, 10 to 40. As another example, the hydrogen passivation layer HPL may be formed by hydrogen implantation (H-implantation) or hydrogen plasma treatment (H2 plasma treatment).

[0197] The hydrogen in the hydrogen passivation layer HPL bonds with silicon on the surfaces of the semiconductor region ACT3-1 of the third-first transistor ST3-1 and the semiconductor region ACT3-2 of the third-second transistor ST3-2, thereby reducing dangling bonds in the semiconductor region ACT3-1 of the third-first transistor ST3-1 and the semiconductor region ACT3-2 of the third-second transistor ST3-2. Therefore, the hydrogen passivation layer HPL eliminates interface defects in the semiconductor region ACT3-1 of the third-first transistor ST3-1 and the semiconductor region ACT3-2 of the third-second transistor ST3-2, improving leakage current characteristics and low-frequency characteristics. By including the hydrogen passivation layer HPL, the display device 10 can prevent leakage current from flowing through the third-first transistor ST3-1 and the third-second transistor ST3-2, thereby stably maintaining the voltage within the pixel SP.

[0198] The semiconductor region ACT1, source electrode SE1, and drain electrode DE1 of the first transistor ST1 may be disposed on the hydrogen passivation layer HPL. The semiconductor region ACT1 of the first transistor ST1 may overlap the gate electrode GE1 in the thickness direction and be insulated from the gate electrode GE1 by the capping layer CPL and the first gate insulating film GI1. The source electrode SE1 and the drain electrode DE1 may be formed by converting the material of the semiconductor region ACT1 into a conductor. The drain electrode DE1 of the first transistor ST1 may be electrically connected to the drain electrode DE3-2 of the third-second transistor ST3-2 via the second node N2 of FIG. 10.

[0199] The semiconductor region ACT3-1, source electrode SE3-1, and drain electrode DE3-1 of the third-first transistor ST3-1 may be disposed on the hydrogen passivation layer HPL. A portion of the first metal layer BML1 may be the gate electrode GE3-1 of the third-first transistor ST3-1. The semiconductor region ACT3-1 of the third-first transistor ST3-1 may overlap the gate electrode GE3-1 in the thickness direction and may be insulated from the gate electrode GE3-1 by the first buffer layer BF1 and the second buffer layer BF2. The source electrode SE3-1 and the drain electrode DE3-1 may be formed by converting the material of the semiconductor region ACT3-1 into a conductor. The drain electrode DE3-1 of the third-first transistor ST3-1 may be formed integrally with the source electrode SE3-2 of the third-second transistor ST3-2. The drain electrode DE3-1 of the 3-1st transistor ST3-1 and the source electrode SE3-2 of the 3-2nd transistor ST3-2 may overlap the first metal layer BML1, but this is not limitative.

[0200] The semiconductor region ACT3-2, source electrode SE3-2, and drain electrode DE3-2 of the third-second transistor ST3-2 may be disposed on the hydrogen passivation layer HPL. Another part of the first metal layer BML1 may be the gate electrode GE3-2 of the third-second transistor ST3-2. The semiconductor region ACT3-2 of the third-second transistor ST3-2 may overlap the gate electrode GE3-2 in the thickness direction and be insulated from the gate electrode GE3-2 by the first buffer layer BF1 and the second buffer layer BF2. The source electrode SE3-2 and the drain electrode DE3-2 may be formed by converting the material of the semiconductor region ACT3-2 into a conductor.

[0201] The capping layer CPL may be disposed on the semiconductor region ACT1, source electrode SE1, and drain electrode DE1 of the first transistor ST1, the semiconductor region ACT3-1, source electrode SE3-1, and drain electrode DE3-1 of the third-first transistor ST3-1, and the semiconductor region ACT3-2, source electrode SE3-2, and drain electrode DE3-2 of the third-second transistor ST3-2. The capping layer CPL may have the same planar pattern as the semiconductor region ACT1, source electrode SE1, and drain electrode DE1 of the first transistor ST1, the semiconductor region ACT3-1, source electrode SE3-1, and drain electrode DE3-1 of the third-first transistor ST3-1, and the semiconductor region ACT3-2, source electrode SE3-2, and drain electrode DE3-2 of the third-second transistor ST3-2. The capping layer CPL may cover protrusions formed on the semiconductor region ACT1, source electrode SE1, and drain electrode DE1 of the first transistor ST1. When the semiconductor region ACT1 of the first transistor ST1 includes low-temperature polycrystalline silicon (LTPS), an amorphous silicon layer disposed on the substrate SUB may be melted and crystallized by a laser. In this case, as the amorphous silicon layer is crystallized, grains may grow, and protrusions may form at the grain boundaries between the grains. The capping layer CPL covers the protrusions of the first transistor ST1, thereby preventing the electric field from concentrating on the protrusions when the first transistor ST1 is driven, thereby improving the driving range of the first transistor ST1. Therefore, by including the capping layer CPL, the display device 10 can precisely control the grayscale of light emitted from the light-emitting element ED. The capping layer CPL may include at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer, but is not limited to these.

[0202] When the first gate insulating film GI1 is formed by a deposition process, the thickness of the first gate insulating film GI1 on the hydrogen passivation layer HPL and the thickness of the first gate insulating film GI1 on the capping layer CPL may be substantially the same. The first thickness T1 may be greater than the second thickness T2. Here, the first thickness T1 is the sum of the thicknesses of the capping layer CPL and the first gate insulating film GI1 that overlap each other, and the second thickness T2 may be the thickness of the first gate insulating film GI1 that does not overlap the capping layer CPL. The thickness of the capping layer CPL is determined by the difference between the first thickness T1 and the second thickness T2. The thickness of the capping layer CPL may be about 20 to 200 angstroms (Å), preferably about 100 angstroms (Å). Therefore, even if the first gate insulating film GI1 and the capping layer CPL contain the same material, it can be seen that the capping layer CPL is disposed on the first transistor ST1, the 3-1 transistor ST3-1, and the 3-2 transistor ST3-2 to cover the protrusions of the first transistor ST1, the 3-1 transistor ST3-1, and the 3-2 transistor ST3-2.

[0203] The first bias electrode BE1, the second bias electrode BE2, and the gate electrode GE1 of the first transistor ST1 are disposed on the first gate insulating film GI1. The first bias electrode BE1, the second bias electrode BE2, and the gate electrode GE1 of the first transistor ST1 are formed in the same layer and made of the same material, but are not limited to this.

[0204] The first bias electrode BE1 may be a bias electrode of the third-first transistor ST3-1. The first bias electrode BE1 may overlap the semiconductor region ACT3-1 of the third-first transistor ST3-1. The first bias electrode BE1 may be electrically connected to the driving voltage line VDDL and may receive a driving voltage from the driving voltage line VDDL. Therefore, the first bias electrode BE1 may stabilize the electric field of the third-first transistor ST3-1 and improve the output characteristics.

[0205] The second bias electrode BE2 may be a bias electrode of the 3-2 transistor ST3-2. The second bias electrode BE2 may overlap the semiconductor region ACT3-2 of the 3-2 transistor ST3-2. The second bias electrode BE2 may be inserted into a contact hole formed in the first gate insulating film GI1, the hydrogen passivation layer HPL, the second buffer layer BF2, and the first buffer layer BF1 and electrically connected to the first metal layer BML1. The second bias electrode BE2 may receive a second gate signal GC[n] from the second gate line GCL. Therefore, the second bias electrode BE2 may increase the electric field generated by the second gate signal GC[n] and improve the output characteristics of the 3-2 transistor ST3-2.

[0206] The first connection electrode CNE1 may be disposed on the interlayer insulating film ILD. The first connection electrode CNE1 may be inserted into a contact hole formed in the interlayer insulating film ILD and the second gate insulating film GI2 to contact the first bias electrode BE1. The first connection electrode CNE1 may be electrically connected between the first bias electrode BE1 and the driving voltage line VDDL. Therefore, the first connection electrode CNE1 may supply the driving voltage received from the driving voltage line VDDL to the first bias electrode BE1.

[0207] The third connection electrode CNE3 may be disposed on the interlayer insulating film ILD and spaced apart from the first connection electrode CNE1. The third connection electrode CNE3 may electrically connect the pixel circuit of the pixel SP and the anode connection electrode ANE. For example, the third connection electrode CNE3 may be electrically connected to the fourth node N4 in FIG. 10. Therefore, the third connection electrode CNE3 may supply the driving current received from the pixel circuit of the pixel SP to the light-emitting element ED.

[0208] The sixth connection electrode CNE6 may be disposed on the interlayer insulating film ILD at a distance from the first and third connection electrodes CNE1 and CNE3. The sixth connection electrode CNE6 may be inserted into a contact hole formed in the interlayer insulating film ILD, the second gate insulating film GI2, the first gate insulating film GI1, the hydrogen passivation layer HPL, the second buffer layer BF2, and the first buffer layer BF1 to contact the third metal layer BML3. The sixth connection electrode CNE6 may be electrically connected between the third metal layer BML3 and the driving voltage line VDDL. Therefore, the sixth connection electrode CNE6 can supply the driving voltage received from the driving voltage line VDDL to the third metal layer BML3.

[0209] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the above embodiments are illustrative in all respects and are not limiting.

Claims

1. a light emitting element disposed on a substrate; a first transistor for controlling a driving current flowing through the light emitting element; a second transistor for supplying a data voltage to a source electrode of the first transistor; a 3-1 transistor and a 3-2 transistor connected in series between a gate electrode of the first transistor and a drain electrode of the first transistor; a first metal layer disposed on the substrate and including a gate electrode of the third-1 transistor and a gate electrode of the third-2 transistor; a hydrogen passivation layer disposed on the first metal layer; a semiconductor region of each of the first transistor, the third-1 transistor, and the third-2 transistor, the semiconductor region being disposed on the hydrogen passivation layer; a capping layer disposed on the semiconductor region of the first transistor; a gate electrode of the first transistor disposed on the capping layer; a first bias electrode disposed in the same layer as the gate electrode of the first transistor and overlapping with a semiconductor region of the 3-1 transistor; a second bias electrode disposed in the same layer as the first bias electrode and overlapping with a semiconductor region of the third-2 transistor.

2. 2. The display device according to claim 1, wherein the hydrogen passivation layer is in direct contact with the lower surface of each of the semiconductor regions of the first transistor, the 3-1 transistor, and the 3-2 transistor.

3. The display device according to claim 1 , wherein the first and second bias electrodes are electrically connected to a driving voltage line to receive a driving voltage.

4. a fourth-1 transistor and a fourth-2 transistor connected in series between the gate electrode of the first transistor and a first initialization voltage line; 2. The display device according to claim 1, further comprising a second metal layer disposed in the same layer as the first metal layer and including a gate electrode of the 4-1 transistor and a gate electrode of the 4-2 transistor.

5. a gate electrode of the second transistor receives a first gate signal from a first gate line; The display device of claim 4 , wherein the first metal layer receives a second gate signal, different from the first gate signal, from a second gate line.

6. The display device of claim 5 , wherein the second metal layer receives a third gate signal, different from the first and second gate signals, from a third gate line.

7. a third bias electrode disposed in the same layer as the second bias electrode and overlapping with a semiconductor region of the 4-1 transistor; 5. The display device according to claim 4, further comprising a fourth bias electrode arranged in the same layer as the third bias electrode and overlapping with the semiconductor region of the 4-2 transistor.

8. The display device according to claim 7 , wherein the third and fourth bias electrodes are electrically connected to a driving voltage line to receive a driving voltage.

9. a fifth transistor disposed between the source electrode of the first transistor and a driving voltage line; a sixth transistor disposed between the drain electrode of the first transistor and the light-emitting element; The display device according to claim 4 , further comprising: a seventh transistor disposed between the first electrode of the light-emitting element and a second initialization voltage line.

10. The display device according to claim 9 , further comprising an eighth transistor disposed between the source electrode of the first transistor and a bias voltage line.

11. the first transistor includes a protrusion formed on a semiconductor region, a source electrode, and a drain electrode of the first transistor; The display device of claim 1 , wherein the capping layer covers the protrusion of the first transistor.

12. a gate insulating film disposed between the capping layer and the gate electrode of the first transistor; the capping layer comprises a silicon oxide layer or an amorphous silicon layer; 12. The display device of claim 11, wherein the gate insulating film includes at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, and an amorphous silicon layer.

13. a light emitting element disposed on a substrate; a first transistor for controlling a driving current flowing through the light emitting element; a second transistor for supplying a data voltage to a source electrode of the first transistor; a 3-1 transistor and a 3-2 transistor connected in series between a gate electrode of the first transistor and a drain electrode of the first transistor; a first metal layer disposed on the substrate and including a gate electrode of the third-1 transistor and a gate electrode of the third-2 transistor; a hydrogen passivation layer disposed on the first metal layer; a semiconductor region of each of the first transistor, the third-1 transistor, and the third-2 transistor, the semiconductor region being disposed on the hydrogen passivation layer; a capping layer disposed on the semiconductor region of the first transistor; a gate electrode of the first transistor disposed on the capping layer; a first bias electrode disposed in the same layer as the gate electrode of the first transistor and overlapping with a semiconductor region of the 3-1 transistor; a second bias electrode disposed in the same layer as the first bias electrode, overlapping a semiconductor region of the third-2 transistor, and electrically connected to the first metal layer;

14. The display device of claim 13 , wherein the first bias electrode is electrically connected to a driving voltage line to receive a driving voltage.

15. a gate electrode of the second transistor receives a first gate signal from a first gate line; The display device of claim 13 , wherein the first metal layer and the second bias electrode receive a second gate signal different from the first gate signal from a second gate line.

16. The display device according to claim 13 , further comprising a second metal layer disposed in the same layer as the first metal layer and overlapping the semiconductor region of the first transistor.

17. The display device of claim 16 , wherein the second metal layer is electrically connected to a driving voltage line to receive a driving voltage.

18. a light emitting element disposed on a substrate; a first transistor for controlling a driving current flowing through the light emitting element; a second transistor for supplying a data voltage to a source electrode of the first transistor; a 3-1 transistor and a 3-2 transistor connected in series between a gate electrode of the first transistor and a drain electrode of the first transistor; a first metal layer disposed on the substrate and including a gate electrode of the third-1 transistor and a gate electrode of the third-2 transistor; a semiconductor region of each of the first transistor, the third-1 transistor, and the third-2 transistor, which is disposed on the first metal layer; a gate electrode of the first transistor disposed on a semiconductor region of the first transistor; a first bias electrode disposed in the same layer as the gate electrode of the first transistor, overlapping with a semiconductor region of the 3-1 transistor, and electrically connected to a driving voltage line; a gate electrode of the first transistor electrically connected to a source electrode of the third-first transistor arranged in the same layer as a semiconductor region of the third-first transistor;

19. a fourth-1 transistor and a fourth-2 transistor connected in series between the gate electrode of the first transistor and a first initialization voltage line; a second metal layer disposed in the same layer as the first metal layer and including a gate electrode of the 4-1 transistor and a gate electrode of the 4-2 transistor; 19. The display device according to claim 18, wherein a gate electrode of said first transistor is electrically connected to a source electrode of said 4-1st transistor, said source electrode being arranged in the same layer as a semiconductor region of said 4-1st transistor.

20. The display device according to claim 18 , further comprising a third metal layer disposed in the same layer as the first metal layer, overlapping a semiconductor region of the first transistor, and electrically connected to a driving voltage line.

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