Dual Path Charge Pump

Abstract

An example of an improved charge pump is disclosed. In one example, a system includes a first charge path comprising a first stage that boosts an input voltage of the first charge path and a second stage that boosts a voltage received from the first stage of the first charge path, and a second charge path comprising a first stage that boosts an input voltage of the second charge path and a second stage that boosts a voltage received from the first stage of the second charge path, wherein an output of the second stage of the first charge path is coupled to the first stage of the second charge path and an output of the second stage of the second charge path is coupled to the first stage of the first charge path.

Description

[Technical Field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 63 / 427,398, entitled "Dual-Path Charge Pump With Cross-Feedback," filed November 22, 2022, and U.S. Patent Application No. 18 / 109,397, entitled "Dual-Path Charge Pump," filed February 14, 2023.

[0002] FIELD OF THE INVENTION An improved charge pump is disclosed that utilizes dual paths and cross-feedback between stages and paths. [Background technology]

[0003] Nonvolatile memory is well known. For example, U.S. Pat. No. 5,029,130 ​​(the "'130 patent"), incorporated herein by reference, discloses an array of split-gate nonvolatile memory cells, a type of flash memory cell. Such a memory cell 110 is shown in FIG. 1. Each memory cell 110 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed above and insulated from (and controls the conductivity of) a first portion of the channel region 18 and above a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed above and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion extending upward and above the floating gate 20. A floating gate 20 and a wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0004] The memory cell 110 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the word line terminal 22, which causes electrons in the floating gate 20 to tunnel through the intermediate insulator from the floating gate 20 to the word line terminal 22 via Fowler-Nordheim (FN) tunneling.

[0005] The memory cell 110 is programmed by source side injection (SSI) of hot electrons (electrons are added to the floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. An electron current flows from the drain region 16 toward the source region 14. The electrons accelerate and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0006] The memory cell 110 is read by applying a positive read voltage to the drain region 16 and word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased of electrons), the portion of the channel region 18 below the floating gate 20 is also turned on and current flows through the channel region 18, which is sensed as an erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off and no (or very little) current flows through the channel region 18, which is sensed as a programmed or "0" state.

[0007] Table 1 illustrates typical voltage / current ranges that may be applied to the terminals of memory cell 110 to perform read, erase, and program operations. Table 1: Operation of the flash memory cell 110 of FIG. 1 [Table 1]

[0008] Other split-gate memory cell configurations, including other types of flash memory cells, are also known. For example, FIG. 2 depicts a four-gate memory cell 210 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates except the floating gate 20 are non-floating gates, i.e., they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0009] Table 2 illustrates typical voltage / current ranges that may be applied to the terminals of memory cell 210 to perform read, erase, and program operations. Table 2: Operation of flash memory cell 210 of FIG. 2 [Table 2]

[0010] Figure 3 illustrates another type of flash memory cell, a three-gate memory cell 310. Memory cell 310 is identical to memory cell 210 of Figure 2, except that memory cell 310 does not have a separate control gate. Erase and read operations (erasure occurs through the use of an erase gate) are similar to those of Figure 2, except that there is no applied control gate bias. Programming operations are also performed without a control gate bias, and as a result, a higher voltage is applied to the source line during a program operation to compensate for the lack of control gate bias.

[0011] Table 3 illustrates typical voltage / current ranges that may be applied to the terminals of memory cell 310 to perform read, erase, and program operations. Table 3: Operation of flash memory cell 310 of FIG. 3 [Table 3]

[0012] 4 illustrates another type of flash memory cell, a stacked gate memory cell 410. Memory cell 410 is similar to memory cell 110 of FIG. 1, except that the floating gate 20 extends over the entire channel region 18, and a control gate 22 (where it is coupled to a word line) extends over the floating gate 20 separated by an insulating layer (not shown). Erasing is accomplished by FN tunneling of electrons from the FG to the substrate, programming is accomplished by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16, and read operations are accomplished by electrons flowing from the source region 14 toward the drain region 16, similar to the read operation of memory cell 210, which has a higher control gate voltage.

[0013] Table 4 illustrates typical voltage ranges that may be applied to the terminals of memory cell 410 and substrate 12 to perform read, erase, and program operations. Table 4: Operation of flash memory cell 410 of FIG. 4 [Table 4]

[0014] The methods and means described herein may be applied to other non-volatile memory technologies such as, but not limited to, FINFET split-gate flash or stacked-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge traps in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge traps in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), CT (charge trap) memory, CN (carbon-tube) memory, OTP (one time programmable), and CeRAM (correlated electron ram).

[0015] 5 illustrates a block diagram of a prior art memory system 500. The memory 500 comprises an array 501, a row decoder 502, a high voltage decoder 503, a column decoder 504, a bit line driver 505, an input circuit 506, an output circuit 507, control logic 508, and a bias generator 509. The memory system 500 further comprises a high voltage generation block 510, which comprises a charge pump 511, a charge pump regulator 512, and a high voltage level generator 513. The memory system 500 further comprises an algorithm controller (program / erase or weight tuning) 514, analog circuitry 515, a control engine 516 (which may include special functions such as, but not limited to, arithmetic functions, activation functions, embedded microcontroller logic, etc.), test control logic 517, and an SRAM block 518 for storing intermediate data such as for input circuits (e.g., activation data) or output circuits (neuron output data), or data input for programming (such as data input for an entire row or multiple rows).

[0016] Array 501 comprises rows and columns of non-volatile memory cells, such as memory cells 110, 210, 310, or 410 of FIGS. 1-4, respectively.

[0017] The input circuit 506 may include circuits such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter), an AAC (analog-to-analog converter, such as a current-to-voltage converter or a logarithmic converter), a PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 506 may implement one or more of a normalization, a linear or nonlinear up / downscaling function, or an arithmetic function. The input circuit 506 may implement a temperature compensation function for the input level. The input circuit 506 may implement an activation function such as a ReLU or a sigmoid. The input circuit 506 may store digital activation data that is applied as an input signal or combined with an input signal during a program or read operation. The digital activation data may be stored in a register. The input circuitry 506 may include circuitry for driving the array terminals, such as the CG, WL, EG, and SL lines, which may include sample-and-hold circuits and buffers. DACs can be used to convert digital activation data into analog input voltages that are applied to the array.

[0018] The output circuit 507 may include circuits such as a current-to-voltage circuit (ITV), an analog-to-digital converter (ADC), an analog-to-analog converter (AAC), an analog-to-pulse converter (APC), or any other type of converter. The output circuit 507 may convert the array output into activation data. The output circuit 507 may implement an activation function such as a rectified linear activation function (ReLU) or a sigmoid. The output circuit 507 may implement one or more of statistical normalization, regularization, up / downscaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, logarithm) of the neuron output. The output circuit 507 may implement a temperature compensation function for the neuron outputs or array outputs (such as bit line outputs) to keep the power consumption of the array approximately constant over temperature, or to improve the accuracy of the array (neuron) output by keeping the IV slope approximately the same over temperature, etc. The output circuit 507 may include registers to store the output data.

[0019] Charge pump 511 must generate the high voltages required for erase and program operations as shown in Tables 1-4 above from a supply voltage that is typically 1.5-3.0V.

[0020] 6 illustrates a prior art charge pump 600. Prior art charge pump 600 includes i+1 stages: stages 601-0 (stage 0), 601-1 (stage 1), ... 601-(i-1) (pre-out stages), and 601-i (output stages). Prior art charge pump 600 also includes dual paths, specifically path 601 and path 651. Each stage boosts the input voltage it receives and outputs the boosted voltage to the next stage as the input voltage for the next stage, or, in the case of stage 601-i, as the output, Vout, of charge pump 600. Paths 601 and 651 operate out of phase with each other so that the output, Vout, is always at the maximum boosted voltage.

[0021] 7 illustrates an example of a clock timing diagram for clock signals CK1, CK2, CK3, and CK4 used in charge pump 600. Clock signals CK1, CK2, CK3, and CK4 are generated from a common clock signal denoted as CLK. Clock signals CK2 and CK3 are complementary to each other, and clock signals CK1 and CK4 are complementary to each other. Thus, CK2 and CK3 are complementary clock signals, and CK1 and CK4 are complementary clock signals. Each edge of clock signals CK2 and CK3 is delayed from the respective first edge of common clock signal CLK by an amount Tdelay1. Each edge of clock signals CK1 and CK4 is delayed from the respective second edge of common clock signal CLK by an amount Tdelay2.

[0022] FIG. 8 illustrates two exemplary stages for one of the paths of charge pump 600, shown here as stage N and stage N+1. Each stage of each path of charge pump 600 performs a boost operation in the same manner as described with reference to stage N+1. Node C is the input voltage received by stage N+1. CK3 and CK4 are clock signals as shown in FIG. 7 and are coupled to capacitors 804 and 805, respectively. When CK3 goes high, the voltage at node C, the top plate of capacitor 804, is boosted by the amount that CK3 increased in voltage. As shown in FIG. 7, there is a delay period Tdelay2 between the rising edge of CK3 and the rising edge of CK4, which utilizes the higher potential at node C to boost node B through MB_T2 from VOUT to VOUT of MB_T2. TH CK4 goes high, the voltage at the top plate of capacitor 805, at node B, is boosted by the amount that CK4 was increased by. As a result, the potential at node B is now very high due to the precharge period and the boost by CK4. The higher potential at node B helps transfer charge from node C to V through transistor 804. Transistor 806 can be enabled to apply V at an initial voltage of VDD, or can remain enabled throughout the operation of charge pump 600 to provide a floor for the value of V (V is always equal to or greater than VDD).

[0023] One drawback of prior art charge pump 600 is that the body effect increases the threshold voltage V TH Given the configuration of charge pump 600, the voltage provided to the gates of those transistors increases with the increased V TH , and may not be large enough to fully turn on those transistors. This problem becomes more pronounced with each subsequent stage.

[0024] An improved charge pump is needed. Summary of the Invention

[0025] An improved charge pump is disclosed that uses a dual path topology, with cross-feedback provided between the paths so that a high voltage generated by a stage (N+1) in one path is applied to the gate of a transistor in the previous stage (N) of the other path.

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[0035] [Brief explanation of the drawings]

[0036] [Figure 1] 1 depicts a prior art split-gate flash memory cell. [Figure 2] 1 depicts another prior art split-gate flash memory cell. [Figure 3] 1 depicts another prior art split-gate flash memory cell. [Figure 4] 1 depicts another prior art split-gate flash memory cell. [Figure 5] 1 depicts a prior art memory system. [Figure 6] 1 depicts a prior art charge pump. [Figure 7] 7 illustrates the clocking scheme of the prior art charge pump of FIG. 6; [Figure 8] 7 depicts a simplified diagram of the prior art charge pump of FIG. 6; [Figure 9] 1 depicts a charge pump. [Figure 10] 10 illustrates a clocking scheme for the charge pump of FIG. [Figure 11] 7 illustrates a simplified diagram of the charge pump of FIG. 6. DETAILED DESCRIPTION OF THE INVENTION

[0037] FIG. 9 illustrates a charge pump 900. The charge pump 900 includes i+1 stages: stages 901-0 (stage 0), 901-1 (stage 1), ..., 901-(i-1) (pre-out stages), and 901-i (output stages). The charge pump 900 also includes dual paths, specifically paths 901 and 951. Each stage in a path may be referred to as a boost stage. Each boost stage boosts the input voltage it receives and outputs the boosted voltage to the next stage as the input voltage for the next stage, or, in the case of stage 901-i, as the output Vout of the charge pump 900. Paths 901 and 951 operate out of phase with each other so that the output, Vout, is always at the maximum boost voltage. FIG. 10 illustrates an example of a clock timing diagram for CK1, CK2, CK3, and CK4 used in the charge pump 900. Clock signals CK1, CK2, CK3, and CK4 are generated from a common clock signal designated CLK. Clock signals CK1 and CK2 are complementary to each other, and clock signals CK3 and CK4 are complementary to each other. The first edge of each of clock signals CK1 and CK2 is delayed from the first edge of the common clock signal CLK by an amount Tdelay1, and the second edge of each of clock signals CK1 and CK2 is aligned with the second edge of the common clock signal CLK. The first edge of each of clock signals CK3 and CK4 is aligned with the first edge of the common clock signal CLK, and the second edge of each of clock signals CK3 and CK4 is delayed from the second edge of the common clock signal CLK by an amount Tdelay2. Charge pump 900 is improved with respect to the body effect compared to prior art charge pump 600, as discussed in more detail below with reference to FIG. 11 .

[0038] FIG. 11 illustrates three exemplary stages, stages N, N+1, and N+2, for paths 901 and 951 of charge pump 900 (where N ranges from 0 to (i-1), corresponding to stages 901-0, ..., 901-i in FIG. 9). Each boost stage in each path of charge pump 900 performs a boost operation in the same manner as described with reference to the boost stage corresponding to stage N of path 901. Node D is the input voltage received by stage N+1 of path 901. CK2 and CK3 are clock signals as shown in FIG. 10 and are coupled to capacitors 1105 and 1106, respectively. When CK2 goes high, the voltage at the top plate of capacitor 1105, which is node D, is boosted by the amount that CK2 was increased by. As shown in FIG. 10, there is a delay period Tdelay2 between the rising edge of CK2 and the rising edge of CK3, and this delay is achieved by using the higher potential of node D to connect node A through MB_T2 to the V TH CK3 then goes high, the voltage at the top plate of capacitor 1106, node A, is boosted by the amount of voltage that CK3 was increased by. As a result, the potential at node A is now equal to the amount of voltage boosted from CK3 plus the amount of voltage from the precharge time, and charge from node D to node E can now pass more efficiently due to the boosted voltage at node A.

[0039] Referring back to FIG. 8, transistor 806 can be enabled to apply VOUT at an initial voltage of VDD, or can remain enabled throughout operation of charge pump 600 to provide a floor for the value of VOUT (VOUT always equals or exceeds VDD).

[0040] Stage N+2 of path 901, or charge pump 900, includes native NMOS transistor 1103 (first native NMOS transistor) and native NMOS transistor 1104 (second native NMOS transistor), which have a lower threshold voltage than NMOS transistor 806 used in prior art charge pump 600. By using native NMOS transistors 1103 and 1104 instead of NMOS transistors, a higher initial voltage is applied to OUT1 and similar nodes of the other stages, allowing charge pump 900 to hit its target faster. Additionally, signal VGI may provide a gate signal to native NMOS transistor 1103, turning off native NMOS transistor 1103 shortly after charge pump 900 is activated, reducing the likelihood of significant leakage due to the low threshold voltage of native NMOS transistor 1103. Native NMOS transistor 1104 is provided to reduce stress on native NMOS transistor 1103 because the voltage difference between the source and gate of native NMOS transistor 1103 is relatively large (HV-0V) when charge pump 900 is activated, where HV is the high voltage generated by the charge pump.

[0041] Native NMOS transistors 1153 (third native NMOS transistor) and 1154 (fourth native NMOS transistor) perform the same role in stage N+1 of path 951 as native NMOS transistors 1103 and 1104 in stage N+1 of path 901. The other pump stages of charge pump 900 include native NMOS transistors that perform the same role, as shown in FIGS.

[0042] To overcome the body effect on boost transistors 1101 (MB_T2) (which is the first boost transistor) and 1151 (MB_B2) (which is the second boost transistor), charge pump 900 applies a higher voltage to the gates of those transistors than prior art charge pump 600. Specifically, charge pump 900 uses the output voltage (node ​​OUT2) from path 951 of stage N+2 as the gate voltage for transistor 1101 (MB_T2) of stage N+1 of path 901, and uses the output voltage (node ​​OUT1) from path 901 of stage N+2 as the gate voltage for transistor 1151 (MB_B2) of stage N+1 of path 951. Due to the boost provided by the subsequent stages, the gate voltages of transistors 1101 (MB_T2) and 1151 (MB_B2) are larger than in the prior art charge pump 600, and node A and node B can be precharged to a higher level than in the prior art charge pump 600, which means that the gate voltages of transistors 1102 (MS_T2) and 1152 (MS_B2) after being boosted by CK3 and CK1, respectively, are higher than in the prior art charge pump 600, and therefore the increased V TH As a result, boosting is more effective in charge pump 900 than in prior art charge pump 600. Charge pump 900 can provide a higher output voltage than charge pump 600 with greater efficiency and less process temperature variation.

[0043] The boost stages of charge pump 900 include boosting a first voltage (the voltage at node D) by a first stage (stage N+1) of a first charge path (path 901) to generate a second voltage (the voltage at node E); boosting the second voltage by a second stage (stage N+2) of the first charge path (path 901) to generate a third voltage (voltage OUT1); boosting a fourth voltage (the voltage at node C) by a first stage (stage N+1) of a second charge path (path 951) to generate a fifth voltage (the voltage at node F); and boosting a sixth voltage (voltage OUT2) by a first stage (stage N+2) of a second charge path (path 951) to generate a sixth voltage (voltage OUT2). The circuit is operable to perform a method comprising boosting a fifth voltage by a second stage (stage N+2) of a second charging path (path 951), applying a third voltage to a first stage of a second charging path, and applying a sixth voltage to the first stage of a first charging path, wherein applying the sixth voltage to the first stage of the first charging path comprises applying the sixth voltage to a gate of a first boost transistor (1101) of the first stage of the first charging path, and applying the third voltage to the first stage of the second charging path comprises applying the third voltage to a gate of a second boost transistor (1151) of the first stage of the second charging path. The method may further include the steps of applying a first clock signal (CK3) to a first stage of the first charge path and a second stage of the second charge path, applying a second clock signal (CK4) to the first stage of the first charge path and the second stage of the second charge path, applying a third clock signal (CK1) to the first stage of the second charge path and the second stage of the first charge path, and applying a fourth clock signal (CK2) to the first stage of the second charge path and the second stage of the first charge path.

[0044] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (with no intermediate material, element, or gap disposed therebetween) and "indirectly" (with an intermediate material, element, or gap disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed therebetween) and "indirectly adjacent" (with an intermediate material, element, or gap disposed therebetween); "attached" includes "directly attached" (with no intermediate material, element, or gap disposed therebetween) and "indirectly attached" (with an intermediate material, element, or gap disposed therebetween); and "electrically coupled" includes "directly electrically coupled" (with no intermediate material or element disposed therebetween that electrically connects the elements together) and "indirectly electrically coupled" (with an intermediate material or element disposed therebetween that electrically connects the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intermediate materials / elements therebetween, and forming the element indirectly on the substrate with one or more intermediate materials / elements therebetween.

Claims

1. 1. A system comprising: a first charge path comprising: a first stage that boosts an input voltage of the first charge path; and a second stage that boosts a voltage received from the first stage of the first charge path; a second charge path comprising a first stage that boosts an input voltage of the second charge path and a second stage that boosts a voltage received from the first stage of the second charge path; an output of the second stage of the first charge path coupled to the first stage of the second charge path, and an output of the second stage of the second charge path coupled to the first stage of the first charge path.

2. 2. The system of claim 1, wherein the output of the second stage of the second charge path is applied to a gate of a first boost transistor of the first stage of the first charge path.

3. 3. The system of claim 2, wherein the output of the second stage of the first charge path is applied to a gate of a second boost transistor of the first stage of the second charge path.

4. The system of claim 3 , wherein the second boost transistor is an NMOS transistor.

5. The system of claim 4 , wherein the first boost transistor is an NMOS transistor.

6. 4. The system of claim 3, wherein the first stage of the first charge path and the second stage of the second charge path receive a first clock signal and a second clock signal.

7. 7. The system of claim 6, wherein the first stage of the second charge path and the second stage of the first charge path receive a third clock signal and a fourth clock signal.

8. 8. The system of claim 7, wherein the first clock signal and the second clock signal are complementary clock signals.

9. 9. The system of claim 8, wherein the third clock signal and the fourth clock signal are complementary clock signals.

10. The second stage of the first charge path comprises: a first native NMOS transistor having a first terminal coupled to a supply voltage, a second terminal, and a gate for receiving a control signal; a second native NMOS transistor having a first terminal coupled to the second terminal of the first native NMOS transistor, a second terminal coupled to the output of the second stage of the first charge path, and a gate coupled to the supply voltage.

11. The second stage of the second charge path comprises: a third native NMOS transistor having a first terminal coupled to a supply voltage, a second terminal, and a gate for receiving a control signal; a fourth native NMOS transistor having a first terminal coupled to the second terminal of the first native NMOS transistor, a second terminal coupled to the output of the second stage of the second charge path, and a gate coupled to the supply voltage.

12. 1. A method comprising: boosting the first voltage by a first stage of a first charge path to generate a second voltage; boosting the second voltage by a second stage of the first charge path to generate a third voltage; boosting the fourth voltage by a first stage of a second charge path to generate a fifth voltage; boosting the fifth voltage by a second stage of the second charge path to generate a sixth voltage; applying the third voltage to the first stage of the second charge path; applying the sixth voltage to the first stage of the first charge path.

13. 13. The method of claim 12, wherein applying the sixth voltage to the first stage of the first charge path comprises applying the sixth voltage to a gate of a first boost transistor of the first stage of the first charge path.

14. 14. The method of claim 13, wherein applying the third voltage to the first stage of the second charge path comprises applying the third voltage to a gate of a second boost transistor of the first stage of the second charge path.

15. 15. The method of claim 14, wherein the second boost transistor is an NMOS transistor.

16. 16. The method of claim 15, wherein the first boost transistor is an NMOS transistor.

17. applying a first clock signal to the first stage of the first charge path and to the second stage of the second charge path; applying a second clock signal to the first stage of the first charge path and to the second stage of the second charge path.

18. applying a third clock signal to the first stage of the second charge path and to the second stage of the first charge path; applying a fourth clock signal to the first stage of the second charge path and to the second stage of the first charge path.

19. 20. The method of claim 18, wherein the first clock signal and the second clock signal are complementary clock signals.

20. 20. The method of claim 19, wherein the third clock signal and the fourth clock signal are complementary clock signals.

21. 1. A system comprising: a first charge path comprising (i+1) boost stages, where i>1; a second charge path comprising (i+1) boost stages; the first charge path and the second charge path receive an input voltage and generate an output voltage greater than the input voltage; an output of a boost stage (N+1) of the first charge path is coupled to a boost stage N of the second charge path, and an output of a boost stage (N+1) of the second charge path is coupled to a boost stage N of the first charge path, where 1≦N≦i.

22. a first clock signal and a second clock signal provided to the first charge path, the first clock signal and the second clock signal being complementary clock signals; 22. The system of claim 21, comprising: a third clock signal and a fourth clock signal provided to the second charge path, the third clock signal and the fourth clock signal being complementary clock signals.

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