Display substrate and manufacturing method thereof, display device

Abstract

A display substrate, its manufacturing method, and a display device are provided. The display substrate includes a plurality of circuit units Q, each of which includes at least a first circuit unit Q1, a second circuit unit Q2, and a third circuit unit Q3. The first circuit unit Q1 includes at least a first drive transistor DTFT1, the second circuit unit Q2 includes at least a second drive transistor DTFT2, and the third circuit unit Q3 includes at least a third drive transistor DTFT3, the channel width of the first drive transistor DTFT1 being larger than that of the second drive transistor DTFT2 or the third drive transistor DTFT3, and the channel length of the first drive transistor DTFT1 being the same as that of the second drive transistor DTFT2 or the third drive transistor DTFT3.

Description

[Technical Field]

[0001] The present disclosure relates to the field of display technology, but is not limited thereto, and more particularly to a display substrate and a manufacturing method thereof, and a display device. [Background technology]

[0002] Semiconductor light-emitting diode (LED) technology has been developing for nearly 30 years, laying a solid foundation for a wide range of applications, from the first solid-state lighting power source to the backlight source for display areas and even LED displays. With the development of chip manufacturing and packaging technology, mini light-emitting diode (Mini LED) displays and micro light-emitting diode (Micro LED) displays have gradually become a hotspot in display panels, and can be applied in fields such as AR / VR, TV, and outdoor displays.

[0003] The current display market is dominated by two technologies: Liquid Crystal Display (LCD) and Organic Light Emitting Diode (OLED). However, due to limitations in substrate size, manufacturing equipment, and processes, it is difficult for both LCD and OLED to realize large-screen displays, especially those over 110 inches. In contrast, Micro LED displays / Mini LED displays can realize large-screen displays using a splice method, breaking through size limitations. LEDs have advantages such as self-luminance, wide viewing angles, fast response, simple structure, small volume, thin and lightweight, energy-saving, high efficiency, long life, and bright light, making them easy to achieve high resolution (Pixels Per Inch, PPI) and considered the most competitive next-generation display technology. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail in the text, which is not intended to limit the scope of protection of the claims. [Means for solving the problem]

[0005] In one aspect, an embodiment of the present disclosure provides a display substrate, comprising: a driving circuit layer disposed on a base; the driving circuit layer comprising a plurality of circuit units, the plurality of circuit units including at least a first circuit unit, a second circuit unit, and a third circuit unit; the first circuit unit comprising a first pixel driving circuit, the first pixel driving circuit comprising at least a first driving transistor, the second circuit unit comprising a second pixel driving circuit, the second pixel driving circuit comprising at least a second driving transistor, the third circuit unit comprising a third pixel driving circuit, the third pixel driving circuit comprising at least a third driving transistor, a channel width of the first driving transistor being larger than a channel width of the second driving transistor or the third driving transistor, and a channel length of the first driving transistor being the same as a channel length of the second driving transistor or the third driving transistor.

[0006] In an exemplary embodiment, the ratio between the channel width of the first driving transistor and the channel width of the second driving transistor or the third driving transistor is 2-6. In an exemplary embodiment, the channel width of the second drive transistor is approximately the same as the channel width of the third drive transistor, and the channel length of the second drive transistor is approximately the same as the channel length of the third drive transistor.

[0007] In an exemplary embodiment, the first pixel drive circuit further includes a first storage capacitor, the second pixel drive circuit further includes a second storage capacitor, and the third pixel drive circuit further includes a third storage capacitor, and the capacitance value of the first storage capacitor is greater than or equal to the capacitance value of the second storage capacitor or the third storage capacitor.

[0008] In an exemplary embodiment, the area of ​​the orthogonal projection of the first storage capacitor on the base is greater than the area of ​​the orthogonal projection of the second storage capacitor or the third storage capacitor on the base.

[0009] In an exemplary embodiment, a first length of the orthogonal projection of the first storage capacitor at the base is the same as a first length of the orthogonal projection of the second storage capacitor or the third storage capacitor at the base, a second length of the orthogonal projection of the first storage capacitor at the base is equal to or greater than a second length of the orthogonal projection of the second storage capacitor or the third storage capacitor at the base, the first length being a size in a first direction, the second length being a size in a second direction, and the first direction intersecting the second direction.

[0010] In an exemplary embodiment, the ratio between the second length of the orthogonal projection of the first storage capacitor at the base and the second length of the orthogonal projection of the second storage capacitor or the third storage capacitor at the base is 1 to 2.

[0011] In an exemplary embodiment, a first length of the orthogonal projection of the second storage capacitor at the base is approximately the same as a first length of the orthogonal projection of the third storage capacitor at the base, and a second length of the orthogonal projection of the second storage capacitor at the base is approximately the same as a second length of the orthogonal projection of the third storage capacitor at the base.

[0012] In an exemplary embodiment, the display substrate further includes a light-emitting structure layer disposed on a side of the driving circuit layer away from the base, the light-emitting structure layer including a plurality of light-emitting units, the plurality of light-emitting diodes including at least a red light-emitting diode emitting red light, a green light-emitting diode emitting green light, and a blue light-emitting diode emitting blue light, the red light-emitting diodes being connected to the first pixel driving circuit, the green light-emitting diodes being connected to the second pixel driving circuit, and the blue light-emitting diodes being connected to the third pixel driving circuit.

[0013] In an exemplary embodiment, at least one circuit unit includes a high-voltage connecting line extending along a first direction and a high-voltage power supply line extending along a second direction, the high-voltage power supply line being connected to the high-voltage connecting line through a via, forming a net-like communication structure for transmitting a high-voltage power supply signal, and the first direction intersects with the second direction.

[0014] In an exemplary embodiment, at least one circuit unit includes a low-voltage connecting line extending along a first direction and a low-voltage power supply line extending along a second direction, the low-voltage power supply line being connected to the low-voltage connecting line through a via, forming a net-like communication structure for transmitting a low-voltage power supply signal, and the first direction intersects with the second direction.

[0015] In an exemplary embodiment, the low-voltage power supply line includes a first low-voltage power supply line and a second low-voltage power supply line, the first low-voltage power supply line is connected to a red light-emitting diode, and the second low-voltage power supply line is connected to a green light-emitting diode and a blue light-emitting diode.

[0016] In an exemplary embodiment, at least one circuit unit includes a first low-voltage connecting line extending along the first direction, and the first low-voltage power supply line is connected to the first low-voltage connecting line through a via, forming a net-like communication structure that transmits a first low-voltage power supply signal.

[0017] In an exemplary embodiment, at least one circuit unit includes a second low-voltage connecting line extending along the first direction, and the second low-voltage power supply line is connected to the second low-voltage connecting line through a via, forming a net-like communication structure that transmits a second low-voltage power supply signal.

[0018] In an exemplary embodiment, at least one circuit unit includes a high-frequency connecting line extending along a first direction and a high-frequency signal line extending along a second direction, the high-frequency signal line being connected to the high-frequency connecting line through a via to form a net-like communication structure for transmitting high-frequency signals, and the first direction intersects with the second direction.

[0019] In an exemplary embodiment, the display substrate further includes a test circuit and a plurality of data signal lines extending along a unit column direction, the data signal lines being connected to the pixel driving circuit, the detection circuit including at least a plurality of detection units and a plurality of transmission lines, the plurality of detection units being connected to corresponding ones of the plurality of data signal lines via the plurality of transmission lines, and a shielding line being installed between at least one transmission line and an adjacent transmission line, the shielding line being connected to a constant voltage signal line or a ground signal line.

[0020] In an exemplary embodiment, the distance between at least one transmission line and an adjacent shield line is between 10 μm and 20 μm.

[0021] In an exemplary embodiment, the transmission line and the shield line are installed on the same layer.

[0022] In another aspect, the present disclosure further provides a display device, comprising the display substrate described above.

[0023] In another aspect, the present disclosure further provides a method for manufacturing a display substrate, comprising: a driving circuit layer is formed on a base, the driving circuit layer having a plurality of circuit units, the plurality of circuit units including at least a first circuit unit, a second circuit unit, and a third circuit unit, the first circuit unit having a first pixel driving circuit, the first pixel driving circuit having at least a first driving transistor, the second circuit unit having a second pixel driving circuit, the second pixel driving circuit having at least a second driving transistor, the third circuit unit having a third pixel driving circuit, the third pixel driving circuit having at least a third driving transistor, a channel width of the first driving transistor being larger than a channel width of the second driving transistor or the third driving transistor, and a channel length of the first driving transistor being the same as a channel length of the second driving transistor or the third driving transistor.

[0024] Other aspects will be understood after reading and understanding the drawings and detailed description.

[0025] The drawings are intended to provide a further understanding of the technical solution of the present disclosure, to be a part of the specification, and to interpret the technical solution of the present disclosure together with the embodiments of the present disclosure, but are not intended to limit the technical solution of the present disclosure. The shape and size of one or more parts in the drawings do not reflect actual proportions and are intended to schematically explain the contents of the present disclosure. [Brief explanation of the drawings]

[0026] [Figure 1] FIG. 1 is a structural schematic diagram of a display device. [Figure 2] FIG. 2 is a schematic plan view of the structure of a display substrate. [Figure 3] FIG. 2 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. [Figure 4] 1 is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure; [Figure 5A] FIG. 2 is a structural schematic diagram of a first driving transistor of the present disclosure. [Figure 5B] FIG. 2 is a structural schematic diagram of a second driving transistor according to the present disclosure. [Figure 6A] FIG. 2 is a structural schematic diagram of a first storage capacitor of the present disclosure. [Figure 6B] FIG. 2 is a structural schematic diagram of a second storage capacitor of the present disclosure. [Figure 7] 3 is a schematic diagram of a display substrate according to the present disclosure after a first conductive layer pattern has been formed. FIG. [Figure 8A] 3 is a schematic diagram of a display substrate according to the present disclosure after a semiconductor layer pattern is formed on the display substrate. FIG. [Figure 8B] 3 is a schematic diagram of a display substrate according to the present disclosure after a semiconductor layer pattern is formed on the display substrate. FIG. [Figure 9] 3 is a schematic diagram of the display substrate of the present disclosure after a second insulating layer pattern has been formed. FIG. [Figure 10A] 3 is a schematic diagram of a display substrate according to the present disclosure after a second conductive layer pattern has been formed. FIG. [Figure 10B] 3 is a schematic diagram of a display substrate according to the present disclosure after a second conductive layer pattern has been formed. FIG. [Figure 11]10 is a schematic diagram of the display substrate of the present disclosure after a third insulating layer pattern has been formed. FIG. [Figure 12A] 10 is a schematic diagram of a display substrate according to the present disclosure after a third conductive layer pattern has been formed. FIG. [Figure 12B] 10 is a schematic diagram of a display substrate according to the present disclosure after a third conductive layer pattern has been formed. FIG. [Figure 13] 3 is a schematic diagram of a display substrate according to the present disclosure after a first flat layer pattern is formed on the display substrate. FIG. [Figure 14A] 10 is a schematic diagram of the display substrate of the present disclosure after a fourth conductive layer pattern has been formed. FIG. [Figure 14B] 10 is a schematic diagram of the display substrate of the present disclosure after a fourth conductive layer pattern has been formed. FIG. [Figure 15] 3 is a schematic diagram of a display substrate according to the present disclosure after a second flat layer pattern is formed on the display substrate. FIG. [Figure 16] FIG. 10 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure. [Figure 17] FIG. 10 is a structural schematic diagram of another display substrate according to an exemplary embodiment of the present disclosure. [Figure 18A] FIG. 4 is a structural schematic diagram of another first driving transistor of the present disclosure. [Figure 18B] FIG. 10 is a structural schematic diagram of another second driving transistor of the present disclosure. [Figure 19A] FIG. 10 is a structural schematic diagram of another first storage capacitor of the present disclosure. [Figure 19B] FIG. 10 is a structural schematic diagram of another second storage capacitor of the present disclosure. [Figure 20] 10 is a schematic diagram of another display substrate according to the present disclosure after a first conductive layer pattern has been formed. FIG. [Figure 21A] FIG. 10 is a schematic diagram of another display substrate according to the present disclosure after a semiconductor layer pattern is formed on the display substrate. [Figure 21B] FIG. 10 is a schematic diagram of another display substrate according to the present disclosure after a semiconductor layer pattern is formed on the display substrate. [Figure 22A] 10 is a schematic diagram of another display substrate according to the present disclosure after a second conductive layer pattern has been formed. FIG. [Figure 22B] 10 is a schematic diagram of another display substrate according to the present disclosure after a second conductive layer pattern has been formed. FIG. [Figure 23] FIG. 10 is a schematic diagram of another display substrate according to the present disclosure after a third insulating layer pattern has been formed. [Figure 24A] 10 is a schematic diagram of another display substrate according to the present disclosure after a third conductive layer pattern has been formed. FIG. [Figure 24B] 10 is a schematic diagram of another display substrate according to the present disclosure after a third conductive layer pattern has been formed. FIG. [Figure 25] 10 is a schematic diagram of another display substrate according to the present disclosure after a first flat layer pattern is formed on the substrate. FIG. [Figure 26A] 10 is a schematic diagram of another display substrate according to the present disclosure after a fourth conductive layer pattern has been formed. FIG. [Figure 26B] 10 is a schematic diagram of another display substrate according to the present disclosure after a fourth conductive layer pattern has been formed. FIG. [Figure 26C] FIG. 2 is a schematic diagram of power wiring according to an exemplary embodiment of the present disclosure. [Figure 27] 10 is a schematic diagram of another display substrate according to the present disclosure after a second flat layer pattern is formed on the substrate. FIG. [Figure 28] 10A and 10B are structural schematic diagrams of further display substrates according to exemplary embodiments of the present disclosure; [Figure 29] 10 is a schematic diagram of a further display substrate of the present disclosure after a first conductive layer pattern is formed on the substrate. FIG. [Figure 30] 10 is a schematic diagram of a further display substrate of the present disclosure after a semiconductor layer pattern is formed on the substrate; [Figure 31] 10 is a schematic diagram of a further display substrate of the present disclosure after a second conductive layer pattern is formed on the substrate. FIG. [Figure 32] FIG. 10 is a schematic diagram of a further display substrate of the present disclosure after a third insulating layer pattern is formed on the substrate. [Figure 33] 10 is a schematic diagram of a further display substrate of the present disclosure after a third conductive layer pattern is formed on the substrate. FIG. [Figure 34] FIG. 10 is a schematic diagram of a further display substrate of the present disclosure after a first flat layer pattern is formed on the substrate. [Figure 35A] 10 is a schematic diagram of a further display substrate of the present disclosure after a fourth conductive layer pattern is formed on the substrate. FIG. [Figure 35B]FIG. 10 is a schematic diagram of another power wiring arrangement according to an exemplary embodiment of the present disclosure. [Figure 36] FIG. 10 is a schematic diagram of a further display substrate of the present disclosure after a second flat layer pattern is formed on the substrate. [Figure 37] FIG. 10 is a schematic diagram illustrating a display substrate performing CT detection. [Figure 38] FIG. 2 is a structural schematic diagram of a detection circuit according to an exemplary embodiment of the present disclosure. [Figure 39] FIG. 10 is a schematic diagram of a connection between a shielded wire and a constant voltage signal line according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0027] To clarify the objectives, technical solutions, and advantages of the present disclosure, the following detailed description of the embodiments of the present disclosure will be given with reference to the accompanying drawings. It should be noted that the embodiments can be implemented in many different forms. As those skilled in the art can easily understand, the manner and content of the present disclosure can be transformed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the following embodiments. Where there is no conflict, the embodiments and features of the embodiments of the present disclosure can be combined with each other.

[0028] The proportions in the drawings in this disclosure may be used as a reference for actual processes, but are not limited thereto. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line may be adjusted according to actual needs. The number of pixels on the display substrate and the number of subpixels in each pixel are also not limited to the numbers shown in the drawings. The drawings described in this disclosure are merely structural schematic diagrams, and one aspect of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0029] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components and are not intended to limit the number of components.

[0030] For convenience, the positions of components in this specification are described with reference to the drawings using terms indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer." However, this is intended to simplify and explain the specification, and is not intended to indicate or suggest that the described devices or elements have a specific orientation or must be configured and operated in a specific orientation. Therefore, it is not intended to limit the present disclosure. The positional relationships of components may be appropriately changed depending on the direction in which each component is described. Therefore, the terms described in the specification may not be limited and may be appropriately changed as the case may be.

[0031] In this specification, unless otherwise clearly specified and limited, the terms "attached," "coupled," and "connected" should be understood in a broad sense. For example, they may be fixedly connected, detachably connected, or integrally connected. They may be mechanically connected or connected. They may be directly connected, indirectly connected via a linker, or internal communication between two elements. Those skilled in the art can understand the specific meanings of the above terms in the present disclosure according to the specific circumstances.

[0032] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and a current can flow through the drain electrode, channel region, and source electrode. In this specification, the channel region refers to a region through which a current mainly flows.

[0033] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. When using a transistor with opposite polarity, or when the current direction during operation in a circuit changes, the functions of "source electrode" and "drain electrode" may be interchangeable. Therefore, in this specification, "source electrode" and "drain electrode" may be interchangeable, and "source terminal" and "drain terminal" may be interchangeable.

[0034] In this specification, "connection" includes cases where components are connected via an element having a certain electrical function. The "element having a certain electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected components. Examples of the "element having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0035] In this specification, "parallel" refers to a state in which the angle formed by two straight lines is between -10° and 10°, and includes a state in which the angle is between -5° and 5°. "Perpendicular" refers to a state in which the angle formed by two straight lines is between 80° and 100°, and includes a state in which the angle is between 85° and 95°.

[0036] In this specification, the terms "film" and "layer" are interchangeable. For example, a "conductive layer" may be changed to a "conductive film." Similarly, an "insulating film" may be changed to an "insulating layer."

[0037] In this disclosure, the terms "thickness" and "height" refer to the vertical distance from the surface of the membrane layer away from the base to the surface of the membrane layer closer to the base.

[0038] The triangles, rectangles, trapezoids, pentagons, hexagons, etc. in this specification are not intended to be exact, and may be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc., and may have small variations due to tolerances, chamfers, arc edges, and variations.

[0039] In this disclosure, "about" refers to a case where the boundary is not precisely defined, but rather allows for a numerical value within the tolerances of process and measurement.

[0040] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the main body structure of a large-screen display device may include a plurality of display substrates 200 mounted on a motherboard 100, with the plurality of display substrates 100 closely connected to display images. In a plane perpendicular to the display substrates, at least one display substrate 200 may include at least a driving circuit layer 20 mounted on a base 10 and a light-emitting structure layer 30 mounted on the side of the driving circuit layer 20 away from the base. In a plane parallel to the display substrates, the driving circuit layer 20 may include a plurality of circuit units, at least one of which may include a pixel driving circuit and a plurality of signal lines connected to the pixel driving circuit, and the pixel driving circuit is configured to receive a data voltage and output a corresponding current under the control of the signal lines. The light-emitting structure layer 30 may include a plurality of light-emitting units, at least one of which may include a light-emitting diode 40, and the light-emitting diodes 40 in the plurality of light-emitting units are correspondingly connected to pixel driving circuits in the plurality of circuit units, and the light-emitting diodes 40 are configured to emit light rays of corresponding brightness under the driving of the output current of the corresponding pixel driving circuit.

[0041] In an exemplary embodiment, the circuit unit described in the present disclosure refers to an area divided into each pixel driving circuit, and the light-emitting unit described in the present disclosure refers to an area divided into each light-emitting diode. In an exemplary embodiment, the positions of both the light-emitting unit and the circuit unit may correspond to each other, or may not correspond to each other, and the present disclosure is not limited thereto.

[0042] In an exemplary embodiment, the light emitting diode 40 may be a mini light emitting diode (Mini LED) or a micro light emitting diode (Micro LED).

[0043] FIG. 2 is a schematic diagram illustrating the planar structure of a display substrate. As shown in FIG. 2, in a plane parallel to the display substrate, the display substrate may include a first sub-pixel P1 emitting light of a first color, a second sub-pixel P2 emitting light of a second color, and a third sub-pixel P3 emitting light of a third color. In an exemplary embodiment, each sub-pixel may include a circuit unit and a light-emitting unit. The first sub-pixel P1 may include a first circuit unit and a first light-emitting unit, where the first light-emitting unit may include a first light-emitting diode emitting light of at least the first color, and the first circuit unit may include at least a first pixel driving circuit connected to the first light-emitting diode. The second sub-pixel P2 may include a second circuit unit and a second light-emitting unit, where the second light-emitting unit may include at least a second light-emitting diode emitting light of a second color, and the second circuit unit may include at least a second pixel driving circuit connected to the second light-emitting diode. The third subpixel P3 may include a third circuit unit and a third light-emitting unit, the third light-emitting unit may include a third light-emitting diode that emits light of at least a third color, and the third circuit unit may include a third pixel driving circuit connected to at least the third light-emitting diode.

[0044] In an exemplary embodiment, the first sub-pixel P1 may be a red (R) sub-pixel emitting red light, the second sub-pixel P2 may be a green (G) sub-pixel emitting green light, and the third sub-pixel P3 may be a blue (B) sub-pixel emitting blue light, and the R sub-pixel, G sub-pixel, and B sub-pixel may constitute one pixel unit P. In an exemplary embodiment, the three sub-pixels in the pixel unit P may be arranged in a horizontal array, a vertical array, a square array, or the like, and the present disclosure is not limited thereto.

[0045] In an exemplary embodiment, the pixel unit P includes four sub-pixels, and the four sub-pixels may be arranged in a manner such as a horizontal array, a vertical array, a square or a diamond shape, and the present disclosure is not limited thereto.

[0046] Research has shown that mini LEDs (Mini LEDs) and micro LEDs (Micro LEDs) are limited by materials and processes, resulting in large discrepancies in light emission efficiency and yield rates between red LEDs (R chips) and blue and green LEDs (G / B chips). For example, if the white brightness is 1000 nits, the R chip, G chip, and B chip must achieve brightnesses of 300 nits, 600 nits, and 100 nits, respectively. In this case, the R chip's drive current needs to be approximately 20 μA, while the G / B chip's drive current needs to be only 4 μA. If the driver transistor (DTFT) in the pixel driver circuit is designed to meet the current demands of the G / B chip, it can achieve a required current of 4 μA at a gate-source voltage Vgs of 5 V. However, at the same transpanel voltage, the R chip's driver transistor cannot achieve a required current of 20 μA at a gate-source voltage Vgs of 5 V, meaning the R chip cannot meet the brightness demands. If the driving transistor is designed according to the current demand of the R chip, the G / B chip can reach its required current with a small gate-source voltage Vgs, resulting in a smaller data range and inability to achieve more gray scales.

[0047] The present disclosure provides a display substrate, and the pixel driving circuits for driving the red light emitting diode, the green light emitting diode, and the blue light emitting diode adopt different structures to avoid defects such as brightness not meeting requirements or not being able to achieve more gray scales.

[0048] In an exemplary embodiment, the display substrate includes a driving circuit layer disposed on a base and a light-emitting structure layer disposed on a side of the driving circuit layer away from the base, the driving circuit layer including a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, the light-emitting structure layer including a plurality of light-emitting units, the circuit units including at least a pixel driving circuit, and the light-emitting units including at least light-emitting diodes, the plurality of circuit units including at least a first circuit unit having a first pixel driving circuit, a second circuit unit having a second pixel driving circuit, and a third circuit unit having a third pixel driving circuit, the plurality of light-emitting diodes including at least a first light-emitting diode emitting light of a first color, a second light-emitting diode emitting light of a second color, and a third light-emitting diode emitting light of a third color, the first pixel driving circuit connected to the first light-emitting diode, the second pixel driving circuit connected to the second light-emitting diode, and the third pixel driving circuit connected to the third light-emitting diode. The first pixel driving circuit includes at least a first driving transistor and a first storage capacitor, the second pixel driving circuit includes at least a second driving transistor and a second storage capacitor, and the third pixel driving circuit includes at least a third driving transistor and a third storage capacitor, wherein the width-to-length ratio of the first driving transistor is greater than the width-to-length ratio of the second driving transistor or the third driving transistor, and the capacitance value of the first storage capacitor is greater than or equal to the capacitance value of the second storage capacitor or the third storage capacitor.

[0049] In an exemplary embodiment, the channel width of the first drive transistor is larger than the channel width of the second drive transistor or the third drive transistor, and the channel length of the first drive transistor is approximately the same as the channel length of the second drive transistor or the third drive transistor.

[0050] In an exemplary embodiment, the area of ​​the orthogonal projection of the first storage capacitor on the base is greater than the area of ​​the orthogonal projection of the second storage capacitor or the third storage capacitor on the base.

[0051] The display substrate of the present disclosure will be described below using several examples.

[0052] FIG. 3 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure, illustrating the structure of a 12T3C pixel driving circuit. In an exemplary embodiment, the multiple light-emitting diodes on the display substrate may be driven using a current mode. Current-mode light-emitting diodes can suffer from color coordinate drift and reduced external quantum efficiency when driven at low current densities, resulting in poor brightness uniformity, making it difficult to accurately represent low gray scales by simply controlling the current amplitude. The pixel driving circuit according to the exemplary embodiment of the present disclosure includes at least two types of data terminals: a current data terminal and a time length data terminal. The current data terminal is configured to supply current signals with different amplitudes to the light-emitting diodes, and the time length data terminal is configured to supply the time length of the current signal to the light-emitting diodes.

[0053] 3, the pixel driving circuit according to this exemplary embodiment may include at least a current control sub-circuit DK and a time length control sub-circuit SK. The current control sub-circuit DK may include at least a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a twelfth transistor T12, and a storage capacitor Cs, and the time length control sub-circuit SK may include at least an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a first capacitor C1, and a second capacitor C2.

[0054] In an exemplary embodiment, the pixel driving circuit may include at least a first node N1, a second node N2, a third node N3, a fourth node N4, a fifth node N5, a sixth node N6, and a seventh node N7. The first node N1 is connected to the second pole of the ninth transistor T9, the second pole of the eleventh transistor T11, and the gate electrode of the twelfth transistor T12, respectively. The second node N2 is connected to the second pole of the seventh transistor T7, the second pole of the twelfth transistor T12, and the anode of the light-emitting diode EL, respectively. The third node N3 is connected to the second pole of the first transistor T1, the first pole of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor Cs, respectively. The fourth node N4 is connected to the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole of the sixth transistor T6, respectively. The fifth node N5 is connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4, and the second pole of the fifth transistor T5, respectively. The sixth node N6 is connected to the second pole of the eighth transistor T8, the gate electrode of the ninth transistor T9, and the first terminal of the first capacitor C1, and the seventh node N7 is connected to the second pole of the tenth transistor T10, the gate electrode of the eleventh transistor T11, and the first terminal of the second capacitor C2, respectively.

[0055] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the second scanning signal line S2, the first pole of the first transistor T1 is connected to the initial signal line Vint, and the second pole of the first transistor T1 is connected to the third node N3. In an exemplary embodiment, the gate electrode of the second transistor T2 is connected to the first scanning signal line S1, the first pole of the second transistor T2 is connected to the third node N3, and the second pole of the second transistor T2 is connected to the fourth node N4. In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the third node N3, the first pole of the third transistor T3 is connected to the fifth node N5, and the second pole of the third transistor T3 is connected to the fourth node N4.

[0056] In an exemplary embodiment, the gate electrode of the fourth transistor T4 is connected to the first scanning signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line DataI, and the second electrode of the fourth transistor T4 is connected to the fifth node N5. In an exemplary embodiment, the gate electrode of the fifth transistor T5 is connected to the light emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the fifth node N5. In an exemplary embodiment, the gate electrode of the sixth transistor T6 is connected to the light emission signal line EM, the first pole of the sixth transistor T6 is connected to the fourth node N4, and the second pole of the sixth transistor T6 is connected to the first pole of the twelfth transistor T12.

[0057] In an exemplary embodiment, the gate electrode of the seventh transistor T7 is connected to the second scanning signal line S2, the first pole of the seventh transistor T7 is connected to the initial signal line Vint, and the second pole of the seventh transistor T7 is connected to the second node N2. In an exemplary embodiment, the gate electrode of the eighth transistor T8 is connected to the first control line CT1, the first electrode of the eighth transistor T8 is connected to the time-length signal line DataT, and the second electrode of the eighth transistor T8 is connected to the sixth node N6. In an exemplary embodiment, the gate electrode of the ninth transistor T9 is connected to the sixth node N6, the first electrode of the ninth transistor T9 is connected to the light emission signal line EM, and the second electrode of the ninth transistor T9 is connected to the first node N1.

[0058] In an exemplary embodiment, the gate electrode of the tenth transistor T10 is connected to the second control line CT2, the first electrode of the tenth transistor T10 is connected to the time-length signal line DataT, and the second electrode of the tenth transistor T10 is connected to the seventh node N7. In an exemplary embodiment, the gate electrode of the eleventh transistor T11 is connected to the seventh node N7, the first pole of the eleventh transistor T11 is connected to the high-frequency signal line Hf, and the second pole of the eleventh transistor T11 is connected to the first node N1. In an exemplary embodiment, the gate electrode of the twelfth transistor T12 is connected to the first node N1, the first pole of the twelfth transistor T12 is connected to the second pole of the sixth transistor T6, and the second pole of the twelfth transistor T12 is connected to the second node N2.

[0059] In the exemplary embodiment, a first end of the storage capacitor Cs is connected to the third node N3, and a second end of the storage capacitor Cs is connected to the first power supply rail VDD. In the exemplary embodiment, a first end of the first capacitor C1 is connected to the sixth node N6, and a second end of the first capacitor C1 is connected to the initial signal line Vint. In the exemplary embodiment, a first end of the second capacitor C2 is connected to the seventh node N7, and a second end of the second capacitor C2 is connected to the initial signal line Vint.

[0060] In an exemplary embodiment, the first transistor T1, the second transistor T2, the fourth transistor T4 to the twelfth transistor T12 may be switch transistors, and the third transistor T3 may be a drive transistor.

[0061] In an exemplary embodiment, the light emitting diode EL may be a Mini LED or a Micro LED. A first pole of the light emitting diode EL is connected to the second node N2, and a second pole of the light emitting diode EL is connected to a second power supply line VSS, and the signal of the second power supply line VSS is a continuously provided low-level signal, such as a DC low voltage. The signal of the first power supply line VDD is a continuously provided high-level signal, such as a DC high voltage.

[0062] In an exemplary embodiment, the first transistor T1 to the twelfth transistor T12 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the processing difficulty of the display panel, and improve the yield rate of the product. In some possible embodiments, the first transistor T1 to the twelfth transistor T12 may include P-type transistors and N-type transistors.

[0063] In an exemplary embodiment, the first transistor T1 to the twelfth transistor T12 may be low-temperature polysilicon transistors, oxide transistors, or both low-temperature polysilicon transistors and metal oxide transistors. The active layer of the low-temperature polysilicon transistors is low-temperature polysilicon (abbreviated as LTPS), and the active layer of the metal oxide transistors is metal oxide semiconductor (oxide). The low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while the oxide transistors have advantages such as low leakage current. By integrating the low-temperature polysilicon transistors and the metal oxide transistors on one display substrate to form a low-temperature polycrystalline oxide (abbreviated as LTPO) display substrate, the advantages of both can be utilized to realize low-frequency driving, reduce power consumption, and improve display properties.

[0064] In an exemplary embodiment, taking the pixel driving circuit shown in FIG. 3 as an example in which the first transistor T1 and the twelfth transistor T12 are both P-type transistors, the operation process of the pixel driving circuit may include the following:

[0065] In an exemplary embodiment, when the gray scale displayed by the light emitting diode connected to the pixel driving circuit is greater than a threshold gray scale, the operation process of the pixel driving circuit may include an initialization stage, a writing stage, and an emission stage, and the initialization stage may include a first sub-stage and a second sub-stage.

[0066] In the first and second sub-phases, the signals on the first scanning signal line S1 and the light-emitting signal line EM are high, the signal on the second scanning signal line S2 is low, and the first transistor T1 and the seventh transistor T7 are turned on. When the first transistor T1 is turned on, the signal on the initial signal line Vint is written to the third node N3, initializing (resetting) the storage capacitor Cs and clearing any existing charge on the storage capacitor Cs. Because the first end of the storage capacitor Cs is low, the third transistor T3 is turned on. When the seventh transistor T7 is turned on, the signal on the initial signal line Vint is written to the second node N2, initializing (resetting) the first pole of the light-emitting diode EL and clearing the voltage previously stored therein, completing the initialization and ensuring that the light-emitting diode EL does not emit light.

[0067] In the first sub-phase, the signal on the time-long signal line DataT is high, the signal on the second control line CT2 is low, and the tenth transistor T10 is turned on, so that the signal on the time-long signal line DataT is written to the seventh node N7 and charges the second capacitor C2. At this time, because the signal on the time-long signal line DataT is high, the eleventh transistor T11 is turned off, and the signal on the high-frequency signal line Hf is not written to the first node N1.

[0068] In the second sub-phase, the signal on the time-long signal line DataT is low, the signal on the first control line CT1 is low, and the eighth transistor T8 is turned on, so that the signal on the time-long signal line DataT is written to the sixth node N6 and charges the first capacitor C1. At this time, because the signal on the time-long signal line DataT is low, the ninth transistor T9 is turned on, and the signal on the light-emitting signal line EM is written to the first node N1.

[0069] In the write phase, the data signal line DataI outputs a data voltage, the signals on the second scan signal line S2 and the light-emitting signal line E are high, the signal on the first scan signal line S1 is low, and the second transistor T2 and the fourth transistor T4 are turned on. With the second transistor T2 and the fourth transistor T4 turned on, the data voltage output from the data signal line DataI is supplied to the third node N3 via the fifth node N5, the turned-on third transistor T3, the fourth node N4, and the turned-on second transistor T2. The difference between the data voltage Vd output from the data signal line DataI and the threshold voltage Vth of the third transistor T3 is stored in the storage capacitor Cs, and the voltage at the first end (third node N3) of the storage capacitor Cs is Vd-|Vth|. The first capacitor C1 maintains the potential of the signal at the sixth node N6 constant, the ninth transistor T9 remains turned on, and the signal on the light-emitting signal line EM is written to the first node N1.

[0070] In the light-emitting stage, the signal on the light-emitting signal line EM is a low-level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, the first capacitor C1 maintains the potential of the signal on the sixth node N6, the ninth transistor T9 remains turned on, the signal on the light-emitting signal line EM is written to the first node N1, and the twelfth transistor T12 is turned on. The power supply voltage output from the first power supply line VDD supplies a driving voltage to the first electrode of the light-emitting diode EL via the fifth transistor T5, the third transistor T3, the sixth transistor T6, and the twelfth transistor T12, which are turned on, to drive the light-emitting diode EL to emit light.

[0071] In an exemplary embodiment, when the gray scale displayed by the light emitting diode connected to the pixel driving circuit is smaller than the threshold gray scale, the operation process of the pixel driving circuit includes an initialization stage, a writing stage and an emission stage, and the initialization stage may include a first sub-stage and a second sub-stage.

[0072] In the first and second sub-phases, the signals on the first scanning signal line S1 and the light-emitting signal line EM are high, the signal on the second scanning signal line S2 is low, and the first transistor T1 and the seventh transistor T7 are turned on. When the first transistor T1 is turned on, the signal on the initial signal line Vint is written to the third node N3, initializing (resetting) the storage capacitor Cs and clearing any existing charge on the storage capacitor Cs. Because the first end of the storage capacitor Cs is low, the third transistor T3 is turned on. When the seventh transistor T7 is turned on, the signal on the initial signal line Vint is written to the second node N2, initializing (resetting) the first pole of the light-emitting diode EL and clearing the voltage previously stored therein, completing the initialization and ensuring that the light-emitting diode EL does not emit light.

[0073] In the first sub-phase, the signal on the time-long signal line DataT is low, the signal on the second control line CT2 is low, and the tenth transistor T10 is turned on, so that the signal on the time-long signal line DataT is written to the seventh node N7 and charges the second capacitor C2. At this time, because the signal on the time-long signal line DataT is low, the eleventh transistor T11 is turned on, so that the signal on the high-frequency signal line Hf is written to the first node N1.

[0074] In the second sub-phase, the signal on the time-long signal line DataT is high, the signal on the first control line CT1 is low, the eighth transistor T8 is turned on, and the signal on the time-long signal line DataT is written to the sixth node N6 to charge the first capacitor C1. At this time, because the signal on the time-long signal line DataT is high, the ninth transistor T9 is turned off, and the signal on the light-emitting signal line EM is not written to the first node N1.

[0075] During the write phase, the data signal line DataI outputs a data voltage, the signals on the second scan signal line S2 and the light-emitting signal line E are high, the signal on the first scan signal line S1 is low, and the second transistor T2 and the fourth transistor T4 are turned on. With the second transistor T2 and the fourth transistor T4 turned on, the data voltage output from the data signal line DataI is supplied to the third node N3 via the fifth node N5, the turned-on third transistor T3, the fourth node N4, and the turned-on second transistor T2. The difference between the data voltage Vd output from the data signal line DataI and the threshold voltage Vth of the third transistor T3 is stored in the storage capacitor Cs, and the voltage at the first end (third node N3) of the storage capacitor Cs is Vd - |Vth|. The second capacitor C2 maintains the potential of the signal at the seventh node N7 constant, the eleventh transistor T11 is always turned on, and the signal on the high-frequency signal line Hf is written to the first node N1.

[0076] In the light-emitting stage, the signal on the light-emitting signal line EM is a low-level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, the second capacitor C2 maintains the potential of the signal at the seventh node N7 constant, the eleventh transistor T11 is always turned on, the signal on the high-frequency signal line Hf is written to the first node N1, and the twelfth transistor T12 is turned on. The power supply voltage output from the first power supply line VDD supplies a driving voltage to the first electrode of the light-emitting diode EL via the fifth transistor T5, the third transistor T3, the sixth transistor T6, and the twelfth transistor T12, which are turned on, to drive the light-emitting diode EL to emit light.

[0077] In the exemplary embodiment, during the light-emitting stage, the driving current output by the third transistor T3 in the pixel driving circuit is only related to the voltage of the data signal line and the voltage of the first power supply line, without being affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the driving transistor on the driving current, ensuring the uniformity of the display brightness of the display product, and improving the display effect.

[0078] In an exemplary embodiment, when the gray scale displayed by the light emitting diode connected to the pixel driving circuit is greater than a threshold gray scale, a control signal is supplied to the first node N1 via the light emitting signal line, thereby controlling the gray scale of the light emitting diode by the driving current.When the gray scale displayed by the light emitting diode connected to the pixel driving circuit is less than the threshold gray scale, a control signal is supplied to the first node N1 via the high-frequency signal line, thereby controlling the gray scale of the light emitting diode by the driving current and the light emitting time length.

[0079] In an exemplary embodiment, the signal on the high-frequency signal line Hf is a pulse signal, and the signal on the high-frequency signal line Hf has multiple pulses within one image frame. In an exemplary embodiment, the frequency of the signal on the high-frequency signal line Hf may be greater than the frequency of the signal on the light-emitting signal line EM. For example, the frequency of the signal on the high-frequency signal line Hf may be between 3,000 Hz and 60,000 Hz, and the frequency of the light-emitting signal line EM may be between 60 Hz and 120 Hz. In the present disclosure, the high-frequency pulse signal on the high-frequency signal line controls the light-emitting duration, dispersing short light-emitting durations within one frame time. This reduces flashing that occurs when the grayscale displayed by the light-emitting diodes connected to the pixel driving circuit is smaller than the threshold grayscale, thereby improving the display effect of display products.

[0080] 4 is a structural schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure, showing the structure of three circuit units, each including a pixel driving circuit as shown in FIG. 3. In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on a base, and a light-emitting structure layer disposed on a side of the driving circuit layer away from the base. In a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units forming at least a plurality of unit rows and a plurality of unit columns, the circuit unit may include at least a pixel driving circuit, the light-emitting structure layer may include a plurality of light-emitting units, the light-emitting units may include at least a light-emitting diode, the light-emitting diodes in the plurality of light-emitting units are correspondingly connected to the pixel driving circuits in the plurality of circuit units, and the light-emitting diodes emit light of corresponding brightness when driven by the output current of the corresponding pixel driving circuit.

[0081] 4, the plurality of circuit units may include at least a first circuit unit Q1, a second circuit unit Q2, and a third circuit unit Q3 arranged in sequence along a first direction X, and the plurality of light-emitting units may include at least a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit. The first circuit unit Q1 may include at least a first pixel driving circuit, the second circuit unit Q2 may include at least a second pixel driving circuit, and the third circuit unit Q3 may include at least a third pixel driving circuit, and the first light-emitting unit may include at least a first light-emitting diode, the second light-emitting unit may include at least a second light-emitting diode, and the third light-emitting unit may include at least a third light-emitting diode. In an exemplary embodiment, the first pixel driving circuit is configured to be connected to the first light-emitting diode, the second pixel driving circuit is configured to be connected to the second light-emitting diode, and the third pixel driving circuit is configured to be connected to the third light-emitting diode.

[0082] In an exemplary embodiment, the first light emitting diode may be a red light emitting diode, the second light emitting diode may be a green light emitting diode, and the third light emitting diode may be a blue light emitting diode.

[0083] In an exemplary embodiment, the first pixel driving circuit in the first circuit unit Q1 may include at least a first driving transistor DTFT1 and a first storage capacitor Cs1, the second pixel driving circuit in the second circuit unit Q2 may include at least a second driving transistor DTFT2 and a second storage capacitor Cs2, and the third pixel driving circuit in the third circuit unit Q3 may include at least a third driving transistor DTFT3 and a third storage capacitor Cs3.

[0084] In an exemplary embodiment, the width-to-length ratio (W / L) of the first drive transistor DTFT1 may be greater than the width-to-length ratio of the second drive transistor DTFT2, and the width-to-length ratio of the first drive transistor DTFT1 may be greater than the width-to-length ratio of the third drive transistor DTFT3.

[0085] In an exemplary embodiment, the capacitance value of the first storage capacitor Cs1 may be greater than the capacitance value of the second storage capacitor Cs2, and the capacitance value of the first storage capacitor Cs1 may be greater than the capacitance value of the third storage capacitor Cs3.

[0086] In an exemplary embodiment, at least one circuit unit may include a high-voltage connecting line VDD-C extending along a first direction X (unit row direction) and a high-voltage power supply line VDD extending along a second direction Y (unit column direction), where the high-voltage power supply line VDD is connected to a corresponding pixel driving circuit, and the high-voltage power supply line VDD may be connected to the high-voltage connecting line VDD-C through a via, forming a net-like communication structure for transmitting a high-voltage power supply signal, and the first direction X and the second direction Y may intersect.

[0087] In an exemplary embodiment, at least one circuit unit may include a low-voltage connecting line VSS-C extending along a first direction X and a low-voltage power supply line VSS extending along a second direction Y, where the low-voltage power supply line VSS is connected to a corresponding light-emitting diode, and the low-voltage power supply line VSS may be connected to the low-voltage connecting line VSS-C through a via, forming a net-like communication structure for transmitting a low-voltage power supply signal.

[0088] In this disclosure, structure A extending along direction B means that structure A includes a main body portion and a secondary portion connected to the main body portion, the main body portion is elongated and extends along approximately one direction, the secondary portion has no shape limitation, the main body portion accounts for at least 60% of structure A, the main body portion extends along direction B, and the size of the main body portion extending along direction B is larger than the size of the secondary portion extending along other directions. In the following description, "structure A extending along direction B" always means "the main body portion of structure A extends along direction B."

[0089] 5A is a structural schematic diagram of a first drive transistor of the present disclosure, and FIG. 5B is a structural schematic diagram of a second drive transistor of the present disclosure. In an exemplary embodiment, the first drive transistor DTFT1 and the second drive transistor DTFT2 may both include an active layer Active, a gate electrode Gate, a first electrode Source, and a second electrode Drain, where the active layer Active includes a channel region, a source connection region and a drain connection region located on either side of the channel region, the overlapping region of the gate electrode Gate and the active layer Active forms the channel region, the first electrode Source is connected to the source connection region, and the second electrode Drain is connected to the drain connection region. The first drive transistor DTFT1 has a first width-to-length ratio, and the second drive transistor DTFT2 has a second width-to-length ratio, where the first width-to-length ratio may be greater than the second width-to-length ratio.

[0090] As shown in Figures 5A and 5B, the gate electrode Gate, the first electrode Source, and the second electrode Drain of the first drive transistor DTFT1 are all comb-shaped, and the second electrode Drain, the gate electrode Gate, and the first electrode Source are alternately arranged along the extension direction of the active layer Active to form four sub-transistors, where the first sub-transistor has a first channel length L1 and a first sub-width z1, the second sub-transistor has a first channel length L1 and a second sub-width z2, the third sub-transistor has a first channel length L1 and a third sub-width z3, and the fourth sub-transistor has a first channel length L1 and a fourth sub-width z4. Therefore, the first drive transistor DTFT1 has a first channel length L1 and a first channel width W1, and the first channel width W1 is the sum of the first sub-width z1, the second sub-width z2, the third sub-width z3, and the fourth sub-width z4. In an exemplary embodiment, the gate electrode Gate, the first pole Source and the second pole Drain of the second drive transistor DTFT2 are all elongated, so that the second drive transistor DTFT2 has a second channel length L2 and a second channel width W2.

[0091] In an exemplary embodiment, the first channel length L1 and the second channel length L2 may be approximately the same, and the first channel width W1 may be greater than the second channel width W2. In an exemplary embodiment, the ratio between the first channel width W1 and the second channel width W2 may be about 2-6. In an exemplary embodiment, z1=z2=z3=z4=W2, and W1 / W2 may be approximately 4.

[0092] In an exemplary embodiment, the second channel width of the second drive transistor DTFT2 and the third channel width of the third drive transistor DTFT3 may be approximately the same, and the second channel length of the second drive transistor DTFT2 and the third channel length of the third drive transistor DTFT3 may be approximately the same.

[0093] 6A is a structural schematic diagram of a first storage capacitor of the present disclosure, and FIG. 6B is a structural schematic diagram of a second storage capacitor of the present disclosure. As shown in FIG. 6A and FIG. 6B, the first storage capacitor Cs1 has a first area, and the second storage capacitor Cs2 has a second area, and the first area may be larger than the second area.

[0094] In an exemplary embodiment, the first area and the second area may be areas of orthogonal projections of the first storage capacitor Cs1 and the second storage capacitor Cs2 onto the plane of the display substrate. The first storage capacitor Cs1 and the second storage capacitor Cs2 may include multiple plates arranged in a stack, and the first area may be the minimum area of ​​orthogonal projections of the multiple plates of the first storage capacitor Cs1 onto the plane of the display substrate, and the second area may be the minimum area of ​​orthogonal projections of the multiple plates of the second storage capacitor Cs2 onto the plane of the display substrate.

[0095] In an exemplary embodiment, the first storage capacitor Cs1 and the second storage capacitor Cs2 may have a polygonal shape, and the first storage capacitor Cs1 and the second storage capacitor Cs2 have a first length M1 and a second length M2, respectively, where the first length M1 may be the maximum size of the first storage capacitor Cs1 and the second storage capacitor Cs2 in a first direction X, the second length M2 may be the maximum size of the first storage capacitor Cs1 and the second storage capacitor Cs2 in a second direction Y, and the first length M1 and the second length M2 may be the projected lengths of the first storage capacitor Cs1 and the second storage capacitor Cs2 when orthogonally projected onto the display substrate plane.

[0096] In an exemplary embodiment, the first length M1 of the first storage capacitor Cs1 and the first length M1 of the second storage capacitor Cs2 may be approximately the same, and the second length M2 of the first storage capacitor Cs1 may be greater than the second length M2 of the second storage capacitor Cs2.

[0097] In an exemplary embodiment, the ratio between the second length M2 of the first storage capacitor Cs1 and the second length M2 of the second storage capacitor Cs2 may be approximately 1 to 2. For example, the ratio between the second length M2 of the first storage capacitor Cs1 and the second length M2 of the second storage capacitor Cs2 may be approximately 1.3.

[0098] In an exemplary embodiment, the first length M1 of the second storage capacitor Cs2 and the first length M1 of the third storage capacitor Cs3 may be approximately the same, and the second length M2 of the second storage capacitor Cs2 and the second length M2 of the third storage capacitor Cs3 may be approximately the same.

[0099] In an exemplary embodiment, the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be sequentially arranged along the first direction X, and the positions of the first light emitting diode, the second light emitting diode, and the third light emitting diode may or may not correspond to the positions of the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3, and the present disclosure is not limited thereto.

[0100] The manufacturing process of a display substrate is described below by way of example. The "patterning process" described in this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metal, inorganic, or transparent conductive materials, and organic material coating, mask exposure, and development for organic materials. The deposition may be performed by one or more of sputtering, evaporation coating, and chemical vapor deposition. The coating may be performed by one or more of spray coating, spin coating, and inkjet printing. The etching may be performed by one or more of dry etching and wet etching. This disclosure is not limited thereto. A "thin film" refers to a thin film layer fabricated on a base material by deposition, coating, or other process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be referred to as a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is referred to as a "thin film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern." In the present disclosure, "A and B are disposed on the same layer" means that A and B are formed simultaneously by the same patterning process. The "thickness" of a film layer is the size of the film layer in a direction perpendicular to the display substrate. In an exemplary embodiment of the present disclosure, "the orthogonal projection of B is within the range of the orthogonal projection of A" or "the orthogonal projection of A includes the orthogonal projection of B" means that the boundary of the orthogonal projection of B is within the boundary range of the orthogonal projection of A, or the boundary of the orthogonal projection of A overlaps the boundary of the orthogonal projection of B.

[0101] In an exemplary embodiment, taking three circuit units (a first circuit unit Q1, a second circuit unit Q2 and a third circuit unit Q3) as an example, the manufacturing process of the driving circuit layer may include the following operations:

[0102] (11) Form a first conductive layer pattern. In an exemplary embodiment, as shown in FIG. 7, forming the first conductive layer pattern may include depositing a first conductive thin film on the base and patterning the first conductive thin film by a patterning process to form a first conductive layer pattern disposed on the base. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0103] In an exemplary embodiment, the first conductive layer pattern of each circuit unit may include at least a first electrode plate CF1, a second electrode plate CF2, a third electrode plate CF3, and a third bottom gate electrode Gate3-B.

[0104] In an exemplary embodiment, the first plate CF1 may have an L-shape and may be disposed on the side of the circuit unit in the second direction Y. In an exemplary embodiment, the first plate CF1 may be one plate of a first capacitor.

[0105] In an exemplary embodiment, the position, shape and size of the first plate CF1 in the first circuit unit Q1, the second circuit unit Q2 and the third circuit unit Q3 may be substantially the same.

[0106] In an exemplary embodiment, the second plate CF2 may have a rectangular shape, the corners of the rectangle may be chamfered, and the second plate CF2 may be located in the middle of the circuit unit in the second direction Y. In an exemplary embodiment, the second plate CF2 may be one plate of a second capacitor.

[0107] In an exemplary embodiment, the position, shape and size of the second plate CF2 in the first circuit unit Q1, the second circuit unit Q2 and the third circuit unit Q3 may be substantially the same.

[0108] In an exemplary embodiment, the third plate CF3 may have a rectangular shape, the corners of the rectangle may be chamfered, and the third plate CF3 may be located on the opposite side of the circuit unit in the second direction Y. In an exemplary embodiment, the third plate CF3 may be one plate of a storage capacitor.

[0109] In an exemplary embodiment, in the second direction Y, the second plate CF2 may be located between the first plate CF1 and the third plate CF3.

[0110] In an exemplary embodiment, the position, shape and size of the third plate CF3 in the second circuit unit Q2 and the third circuit unit Q3 may be substantially the same, but different from the shape and size of the third plate CF3 in the first circuit unit Q1.

[0111] In an exemplary embodiment, the area of ​​the third plate CF3 in the first circuit unit Q1 may be larger than the area of ​​the third plate CF3 in the second circuit unit Q2, and the area of ​​the third plate CF3 in the first circuit unit Q1 may be larger than the area of ​​the third plate CF3 in the third circuit unit Q3, so that the capacitance value of the storage capacitor in the first circuit unit Q1 is larger than the capacitance values ​​of the storage capacitors in the second circuit unit Q2 and the third circuit unit Q3.

[0112] In an exemplary embodiment, the first lengths M1 of the third plate CF3 in the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be approximately the same, and the second length M2 of the third plate CF3 in the first circuit unit Q1 may be greater than the second lengths M2 of the third plate CF3 in the second circuit unit Q2 and the third circuit unit Q3, such that the area of ​​the third plate CF3 in the first circuit unit Q1 is greater than the area of ​​the third plate CF3 in the second circuit unit Q2 and the third circuit unit Q3. In an exemplary embodiment, the first length M1 may be the maximum size in the first direction X, and the second length M2 may be the maximum size in the second direction Y.

[0113] In an exemplary embodiment, the ratio between the second length M2 of the third electrode plate CF3 in the first circuit unit Q1 and the second length M2 of the third electrode plate CF3 in the second circuit unit Q2 and the third circuit unit Q3 may be about 1 to 2. For example, the ratio may be about 1.3.

[0114] In an exemplary embodiment, the edge of the third plate CF3 in the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 that is closer to the second plate CF2 may be approximately flush, and the distance between the edge of the third plate CF3 in each circuit unit that is closer to the second plate CF2 and the edge of the second plate CF2 that is closer to the third plate CF3 may be approximately the same.

[0115] In an exemplary embodiment, the third bottom gate electrode Gate3-B may be a bottom gate electrode of a third transistor (drive transistor). In the first direction X, the third bottom gate electrode Gate3-B may be located on the opposite side of the first electrode plate CF1 in the first direction X, and in the second direction Y, the third bottom gate electrode Gate3-B may be located on the second electrode plate CF2 side in the second direction Y.

[0116] In an exemplary embodiment, the third bottom gate electrode Gate3-B in the first circuit unit Q1 may include a plurality of sub-electrodes, each of which may be elongated and extending along the first direction X, and the plurality of sub-electrodes may be spaced apart along the second direction Y to form a comb-like structure. The third bottom gate electrodes Gate3-B in the second circuit units Q2 and Q3 may include one sub-electrode and form an L-shaped structure. In an exemplary embodiment, by forming the third bottom gate electrode Gate3-B in the first circuit unit Q1 into a plurality of sub-electrodes structure, the width-to-length ratio of the drive transistor in the first circuit unit Q1 can be made larger than the width-to-length ratio of the drive transistor in the second circuit unit Q2 and Q3.

[0117] In an exemplary embodiment, each sub-electrode in the first circuit unit Q1 forms a first channel length L1 of a transistor, and each sub-electrode in the second circuit unit Q2 forms a second channel length L2 of the transistor, and the first channel length L1 and the second channel length L2 may be approximately the same.

[0118] In an exemplary embodiment, the multiple sub-electrodes in the first circuit unit Q1 form multiple sub-widths z of the transistor, the sub-electrodes in the second circuit unit Q2 form the sub-width z of the transistor, the first channel width of the third transistor in the first circuit unit Q1=4*sub-width z, and the second channel width of the third transistor in the second circuit unit Q2=sub-width z, so that the width-to-length ratio of the third transistor in the first circuit unit Q1 is approximately four times the width-to-length ratio of the third transistor in the second circuit unit Q2.

[0119] In an exemplary embodiment, the edge of the third bottom gate electrode Gate3-B in the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 that is closer to the second electrode plate CF2 may be approximately flush, and the distance between the edge of the third bottom gate electrode Gate3-B in each circuit unit that is closer to the second electrode plate CF2 and the edge of the second electrode plate CF2 that is closer to the third bottom gate electrode Gate3-B may be approximately the same.

[0120] In an exemplary embodiment, a plate electrode connecting wire may be connected to the third plate CF3 on the side in the first direction X or the side opposite to the first direction X, and the plate electrode connecting wire may have an elongated shape extending along the first direction X, with a first end of the plate electrode connecting wire connected to the third plate CF3 of this circuit unit and a second end of the plate electrode connecting wire extending along the first direction X or the direction opposite to the first direction X and then connected to the third plate CF3 of an adjacent circuit unit, thereby connecting the third plates CF3 in one unit row. In an exemplary embodiment, the number of plate electrode connecting wires may be two or three to improve connection reliability.

[0121] In an exemplary embodiment, the plurality of third plates CF3 and the plurality of plate electrode connecting lines in one unit row may be connected to each other in an integrated structure. In the exemplary embodiment, the third plates CF3 in each circuit unit are connected to a high-voltage power supply line to be formed subsequently, so that the third plates CF3 of adjacent circuit units are connected to each other in an integrated structure, and the integrated third plates CF3 can also be used as high-voltage power supply signal lines, ensuring that the plurality of third plates CF3 in one unit row have the same potential, contributing to improving the uniformity of the panel, avoiding display defects on the display substrate, and ensuring the display effect of the display substrate.

[0122] In an exemplary embodiment, the first conductive layer pattern may further include a power electrode 11 disposed on the third circuit unit Q3, and the power electrode 11 may have an elongated shape extending along the second direction Y and may be disposed on the side of the third electrode plate CF3 in the first direction X. In an exemplary embodiment, the power electrode 11 is configured to be connected to a high-voltage power line to be formed later, and to realize a connection between the third electrode plate and the high-voltage power line.

[0123] In an exemplary embodiment, the third plate CF3 and the power electrode 11 may be an integrated structure connected to each other.

[0124] (12) Forming a semiconductor layer pattern. In an exemplary embodiment, as shown in Figures 8A and 8B, forming the semiconductor layer pattern may include sequentially depositing a first insulating thin film and a first semiconductor thin film on a base, and patterning the first semiconductor thin film through a patterning process to form a first insulating layer covering the first conductive layer and a semiconductor layer pattern disposed on the first insulating layer. Figure 8B is a schematic plan view of the semiconductor layer of Figure 8A.

[0125] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit may include at least the first active layer AT1 of the first transistor T1 to the twelfth active layer AT12 of the twelfth transistor T12.

[0126] In an exemplary embodiment, the first active layer AT1, the second active layer AT2, the fourth active layer AT4, the seventh active layer AT7, and the tenth active layer AT10 may have elongated shapes extending along the first direction X, the third active layer AT3, the fifth active layer AT5, the sixth active layer AT6, the eighth active layer AT8, the ninth active layer AT9, and the twelfth active layer AT12 may have elongated shapes extending along the second direction Y, and the eleventh active layer AT11 may have a rectangular shape.

[0127] In an exemplary embodiment, the first active layer AT1 may be located between the second plate CF2 and the third plate CF3, and the first active layer AT1 may be the active layer of the first transistor T1. The second active layer AT2 may be located between the second plate CF2 and the third bottom gate electrode Gate3-B, and the second active layer AT2 may be the active layer of the second transistor T2. The orthogonal projection of the third active layer AT3 at the base at least partially overlaps the orthogonal projection of the third bottom gate electrode Gate3-B at the base, and the third active layer AT3 may be the active layer of the third transistor T3. The fourth active layer AT4 may be located between the second plate CF2 and the third bottom gate electrode Gate3-B, and is located on the opposite side of the second active layer AT2 in the first direction X, and the fourth active layer AT4 may be the active layer of the fourth transistor T4. The fifth active layer AT5 may be located between the third active layer AT3 and the fourth active layer AT4, and may be the active layer of the fifth transistor T5. The sixth active layer AT6 may be located between the first electrode plate CF1 and the third bottom gate electrode Gate3-B, and may be the active layer of the sixth transistor T6. The seventh active layer AT7 may be located on the first direction X side of the first active layer AT1, and may be the active layer of the seventh transistor T7. The eighth active layer AT8 may be located on the opposite side of the first electrode plate CF1 in the second direction Y, and may be the active layer of the eighth transistor T8. The ninth active layer AT9 may be located between the first electrode plate CF1 and the eighth active layer AT8, and may be the active layer of the ninth transistor T9. The tenth active layer AT10 may be located on the second direction Y side of the seventh active layer AT7, and may be used as the active layer of the tenth transistor T10. The eleventh active layer AT11 may be located on the second direction Y side of the tenth active layer AT10, and may be used as the active layer of the eleventh transistor T11. The twelfth active layer AT12 may be located between the second active layer AT2 and the third active layer AT3, and may be located on the first direction X side of the fifth active layer AT5, and may be used as the active layer of the twelfth transistor T12.

[0128] In an exemplary embodiment, the first active layer AT1 and the seventh active layer AT7 may be located on a line extending along the first direction X, the second active layer AT2 and the fourth active layer AT4 may be located on a line extending along the first direction X, and the fifth active layer AT5 and the twelfth active layer AT12 may be located on a line extending along the first direction X.

[0129] In an exemplary embodiment, along the second direction Y, the extension length of the third active layer AT3 in the first circuit unit Q1 may be greater than the extension length of the third active layer AT3 in the second circuit unit Q2 and the third circuit unit Q3, so that the width-to-length ratio of the driving transistor in the first circuit unit Q1 is greater than the width-to-length ratio of the driving transistor in the second circuit unit Q2 and the third circuit unit Q3.

[0130] In an exemplary embodiment, each of the first active layer AT1 to the twelfth active layer AT12 may include a first region, a second region, and a channel region located between the first region and the second region, and the first region and the second region of each of the multiple active layers may be provided separately.

[0131] (13) Forming a second insulating layer pattern. In an exemplary embodiment, as shown in Figure 9, forming the second insulating layer pattern may include depositing a second insulating thin film on the base on which the pattern is formed, and patterning the second insulating thin film through a patterning process to form a second insulating layer covering the semiconductor layer, and a plurality of vias are provided in the second insulating layer.

[0132] In an exemplary embodiment, the plurality of vias in the second insulating layer in each circuit unit may include at least a first via V1, a second via V2, a third via V3, and a fourth via V4.

[0133] In an exemplary embodiment, the orthogonal projection of the base of the first via V1 is within the range of the orthogonal projection of the base of the first electrode plate CF1. The second insulating layer and the first insulating layer within the first via V1 are etched to expose the surface of the first electrode plate CF1. The first via V1 is configured to connect a subsequently formed first connection electrode to the first electrode plate CF1 through the via.

[0134] In the exemplary embodiment, the orthogonal projection of the base of the second via V2 is within the range of the orthogonal projection of the base of the second electrode plate CF2. The second insulating layer and the first insulating layer in the second via V2 are etched to expose the surface of the second electrode plate CF2. The second via V2 is configured to connect a subsequently formed second connection electrode to the second electrode plate CF2 through the via.

[0135] In an exemplary embodiment, the orthogonal projection of the base of the third via V3 is within the range of the orthogonal projection of the base of the third electrode plate CF3. The second insulating layer and the first insulating layer in the third via V3 are etched to expose the surface of the third electrode plate CF3. The third via V3 is configured to connect a subsequently formed third connection electrode to the third electrode plate CF3 through the via.

[0136] In an exemplary embodiment, the orthogonal projection of the base of the fourth via V4 is within the range of the orthogonal projection of the base of the third bottom gate electrode Gate3-B. The second insulating layer and the first insulating layer in the fourth via V4 are etched to expose the surface of the third bottom gate electrode Gate3-B. The fourth via V4 is configured to connect a subsequently formed third top gate electrode to the third bottom gate electrode Gate3-B through the via.

[0137] In an exemplary embodiment, the plurality of vias in the second insulating layer may further include a fifth via V5. The orthogonal projection of the base of the fifth via V5 is within the range of the orthogonal projection of the base of the power electrode 11. The second insulating layer and the first insulating layer within the fifth via V5 are etched to expose the surface of the power electrode 11. The fifth via V5 is configured to connect a subsequently formed seventh connection electrode to the power electrode 11 through the via.

[0138] In an exemplary embodiment, in order to increase connection reliability, there may be a plurality of first vias V1 to fifth vias V5.

[0139] (14) Forming a second conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 10A and 10B, forming the second conductive layer pattern may include depositing a second conductive thin film on the base on which the above-mentioned pattern is formed, and patterning the second conductive thin film by a patterning process to form a second conductive layer pattern disposed on the second insulating layer. FIG. 10B is a schematic plan view of the second conductive layer in FIG. 10A. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0140] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least a fourth electrode plate CF4, a fifth electrode plate CF5, a sixth electrode plate CF6, a first scanning signal line S1, a second scanning signal line S2, a light emitting signal line EM, an initial signal line Vint, a high-frequency signal line Hf, a high-voltage connecting line VDD-C, a low-voltage connecting line VSS-C, a plurality of gate electrodes and a plurality of connecting electrodes.

[0141] In an exemplary embodiment, the shape of the fourth plate CF4 may be an L-shape with a notch at one corner, the orthogonal projection of the fourth plate CF4 at the base at least partially overlaps with the orthogonal projection of the first plate CF1 at the base, and the fourth plate CF4 may be the other plate of a first capacitor, and the first plate CF1 and the fourth plate CF4 constitute one first capacitor of the pixel driving circuit.

[0142] In an exemplary embodiment, the position, shape and size of the fourth plate CF4 in the first circuit unit Q1, the second circuit unit Q2 and the third circuit unit Q3 may be substantially the same.

[0143] In an exemplary embodiment, the shape of the fifth plate CF5 may be a rectangle with a notch at one corner, the orthogonal projection at the base of the fifth plate CF5 at least partially overlaps with the orthogonal projection at the base of the second plate CF2, and the fifth plate CF5 may be the other plate of a second capacitor, and the second plate CF2 and the fifth plate CF5 constitute one second capacitor of the pixel driving circuit.

[0144] In an exemplary embodiment, the position, shape and size of the fifth plate CF5 in the first circuit unit Q1, the second circuit unit Q2 and the third circuit unit Q3 may be substantially the same.

[0145] In an exemplary embodiment, the shape of the sixth plate CF6 may be a rectangle with a notch at one corner, the orthogonal projection at the base of the sixth plate CF6 at least partially overlaps with the orthogonal projection at the base of the third plate CF3, and the sixth plate CF6 may be the other plate of a storage capacitor, and the third plate CF3 and the sixth plate CF6 constitute one storage capacitor of the pixel driving circuit.

[0146] In an exemplary embodiment, the position, shape and size of the sixth plate CF6 in the second circuit unit Q2 and the third circuit unit Q3 may be substantially the same, but different from the shape and size of the sixth plate CF6 in the first circuit unit Q1.

[0147] In an exemplary embodiment, the area of ​​the sixth plate CF6 in the first circuit unit Q1 may be larger than the area of ​​the sixth plate CF6 in the second circuit unit Q2, and the area of ​​the sixth plate CF6 in the first circuit unit Q1 may be larger than the area of ​​the sixth plate CF6 in the third circuit unit Q3, so that the capacitance value of the storage capacitor in the first circuit unit Q1 is larger than the capacitance values ​​of the storage capacitors in the second circuit unit Q2 and the third circuit unit Q3.

[0148] In an exemplary embodiment, the first lengths M1 of the sixth plate CF6 in the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be approximately the same, and the second length M2 of the sixth plate CF6 in the first circuit unit Q1 may be greater than the second length M2 of the sixth plate CF6 in the second circuit unit Q2 and the third circuit unit Q3, so that the area of ​​the sixth plate CF6 in the first circuit unit Q1 is greater than the area of ​​the sixth plate CF6 in the second circuit unit Q2 and the third circuit unit Q3.

[0149] In an exemplary embodiment, the ratio between the second length M2 of the sixth electrode plate CF6 in the first circuit unit Q1 and the second length M2 of the sixth electrode plate CF6 in the second circuit unit Q2 and the third circuit unit Q3 may be about 1 to 2. For example, the ratio may be about 1.3.

[0150] In an exemplary embodiment, the first scanning signal line S1, the second scanning signal line S2, the light-emitting signal line EM, the initial signal line Vint, the high-frequency signal line Hf, the high-voltage connecting line VDD-C, and the low-voltage connecting line VSS-C may have a linear or polygonal shape with their main bodies extending along the first direction X. The first scanning signal line S1, the light-emitting signal line EM, and the high-frequency signal line Hf may be located between the fourth electrode plate CF4 and the fifth electrode plate CF5, the high-frequency signal line Hf may be located on the second direction Y side of the fourth electrode plate CF4, the light-emitting signal line EM may be located on the second direction Y side of the high-frequency signal line Hf, and the first scanning signal line S1 may be located on the second direction Y side of the light-emitting signal line EM. The second scanning signal line S2 and the initial signal line Vint may be located between the fifth electrode plate CF5 and the sixth electrode plate CF6, the initial signal line Vint may be located on the side of the sixth electrode plate CF6 in the second direction Y, and the second scanning signal line S2 may be located on the side of the initial signal line Vint in the second direction Y. The high-voltage connecting line VDD-C may be located on the side of the third electrode plate CF3 away from the fourth electrode plate CF4, and the low-voltage connecting line VSS-C may be located on the side of the sixth electrode plate CF6 away from the fifth electrode plate CF5.

[0151] In the exemplary embodiment, a high-frequency connection block is provided on the side of the high-frequency signal line Hf away from the light-emitting signal line EM, and the high-frequency connection block is configured to be connected to the 26th connection electrode formed subsequently.

[0152] In an exemplary embodiment, a high-voltage connection block is installed on the side of the high-voltage connection line VDD-C close to the fourth electrode plate CF4, and the high-voltage connection block is configured to be connected to the subsequently formed 16th connection electrode.

[0153] In an exemplary embodiment, a low-voltage connection block is provided on the side of the low-voltage connection line VSS-C that is close to the sixth electrode plate CF6, and the low-voltage connection block is configured to be connected to the subsequently formed 32nd connection electrode. In an exemplary embodiment, the low-voltage connection block may be provided on the first circuit unit Q1 and the second circuit unit Q2, and no low-voltage connection block is provided on the third circuit unit Q3.

[0154] In an exemplary embodiment, the first scanning signal line S1 may also be used as a first control line to control the turning on and off of the eighth transistor T8, and the second scanning signal line S2 may also be used as a second control line to control the turning on and off of the tenth transistor T10.

[0155] In an exemplary embodiment, the multiple gate electrodes of each circuit unit may include at least a first gate electrode Gate1, a second gate electrode Gate2, a third top gate electrode Gate3-T, a fourth gate electrode Gate4, a fifth gate electrode Gate5, a sixth gate electrode Gate6, a seventh gate electrode Gate7, an eighth gate electrode Gate8, a ninth gate electrode Gate9, a tenth gate electrode Gate10, an eleventh gate electrode Gate11, and a twelfth gate electrode Gate12.

[0156] In an exemplary embodiment, the second gate electrode Gate2, the fourth gate electrode Gate4, and the eighth gate electrode Gate8 may be disposed on a side of the first scan signal line S1 away from the emission signal line EM. The second gate electrode Gate2 is the gate electrode of the second transistor T2, and the orthogonal projection of the second gate electrode Gate2 at the base at least partially overlaps with the orthogonal projection of the base of the second active layer, the fourth gate electrode Gate4 is the gate electrode of the fourth transistor T4, and the orthogonal projection of the fourth gate electrode Gate4 at the base at least partially overlaps with the orthogonal projection of the base of the fourth active layer, and the eighth gate electrode Gate8 is the gate electrode of the eighth transistor T8, and the orthogonal projection of the eighth gate electrode Gate8 at the base at least partially overlaps with the orthogonal projection of the base of the eighth active layer.

[0157] In an exemplary embodiment, the first scanning signal line S1, the second gate electrode Gate2, the fourth gate electrode Gate4 and the eighth gate electrode Gate8 may be an integrated structure in which they are connected to each other.

[0158] In an exemplary embodiment, the first gate electrode Gate1 and the seventh gate electrode Gate7 may be disposed on a side of the second scanning signal line S2 closer to the initial signal line Vint, and the tenth gate electrode Gate10 may be disposed on a side of the second scanning signal line S2 farther from the initial signal line Vint. The first gate electrode Gate1 is the gate electrode of the first transistor T1, and an orthogonal projection of the first gate electrode Gate1 at a base at least partially overlaps with an orthogonal projection of the base of the first active layer. The seventh gate electrode Gate7 is the gate electrode of the seventh transistor T7, and an orthogonal projection of the seventh gate electrode Gate7 at a base at least partially overlaps with an orthogonal projection of the base of the seventh active layer. The tenth gate electrode Gate10 is the gate electrode of the tenth transistor T10, and an orthogonal projection of the tenth gate electrode Gate10 at a base at least partially overlaps with an orthogonal projection of the base of the tenth active layer.

[0159] In an exemplary embodiment, the second scanning signal line S2, the first gate electrode Gate1, the seventh gate electrode Gate7, and the tenth gate electrode Gate10 may be an integrated structure in which they are connected to each other.

[0160] In an exemplary embodiment, the first gate electrode Gate1, the second gate electrode Gate2, the seventh gate electrode Gate7, the eighth gate electrode Gate8, and the tenth gate electrode Gate10 may be two in number, forming the first transistor T1, the second transistor T2, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 with a double-gate structure, which can improve the driving capability, improve the current saturation of the light emitting diode, and prevent or reduce the occurrence of leakage current.

[0161] In an exemplary embodiment, the third top gate electrode Gate3-T may be a top gate electrode of the third transistor T3, and the orthogonal projection of the third top gate electrode Gate3-T at the base at least partially overlaps with the orthogonal projection of the third top gate electrode Gate3-T at the base of the third active layer. The shape of the third top gate electrode Gate3-T may be substantially the same as the shape of the third bottom gate electrode Gate3-B, and the orthogonal projection of the third top gate electrode Gate3-T at the base at least partially overlaps with the orthogonal projection of the third bottom gate electrode Gate3-B at the base, and the third top gate electrode Gate3-T is connected to the third bottom gate electrode Gate3-B through the fourth via V4.

[0162] In an exemplary embodiment, a third gate electrode block 103 is installed on the side of the third top gate electrode Gate3-T closer to the fourth electrode plate CF4, and the shape of the third gate electrode block 103 may be a polygonal line extending along the first direction X, and the third gate electrode block 103 is configured to be connected to a twelfth connection electrode to be formed subsequently.

[0163] In an exemplary embodiment, the fifth gate electrode Gate5 may be the gate electrode of the fifth transistor T5, and the orthogonal projection of the fifth gate electrode Gate5 at a base thereof at least partially overlaps with the orthogonal projection of the base of the fifth active layer. The fifth gate electrode Gate5 may be located between the first scanning signal line S1 and the third top gate electrode Gate3-T, and the fifth gate electrode Gate5 may have a comb-like shape.

[0164] In an exemplary embodiment, a fifth gate electrode block 105 is provided on the side of the fifth gate electrode Gate5 closer to the first scanning signal line S1, and the fifth gate electrode block 105 may have an elongated shape extending along the second direction Y, and the fifth gate electrode block 105 is configured to be connected to a 27th connection electrode to be formed subsequently.

[0165] In an exemplary embodiment, the sixth gate electrode Gate6 may be the gate electrode of the sixth transistor T6, and the orthogonal projection of the sixth gate electrode Gate6 at the base at least partially overlaps with the orthogonal projection of the base of the sixth active layer. The sixth gate electrode Gate6 may be located between the fourth electrode plate CF4 and the third top gate electrode Gate3-T, and the sixth gate electrode Gate6 may have a comb-like shape.

[0166] In an exemplary embodiment, a sixth gate electrode block 106 is provided on the side of the sixth gate electrode Gate6 closer to the first scanning signal line S1, and the shape of the sixth gate electrode block 106 may be a zigzag line extending along the second direction Y, and the sixth gate electrode block 106 is configured to be connected to the 22nd connection electrode formed subsequently.

[0167] In an exemplary embodiment, the ninth gate electrode Gate9 may be the gate electrode of the ninth transistor T9, and the orthogonal projection of the base of the ninth gate electrode Gate9 at least partially overlaps with the orthogonal projection of the base of the ninth active layer. The ninth gate electrode Gate9 may be located on a side of the fourth plate CF4 closer to the first scanning signal line S1 and connected to the fourth plate CF4.

[0168] In an exemplary embodiment, the fourth electrode plate CF4 and the ninth gate electrode Gate9 may be an integrated structure connected to each other.

[0169] In an exemplary embodiment, the eleventh gate electrode Gate11 may be the gate electrode of the eleventh transistor T11, and the orthogonal projection of the eleventh gate electrode Gate11 at the base at least partially overlaps with the orthogonal projection of the base of the eleventh active layer. The eleventh gate electrode Gate11 may be located on the first direction X side of the fifth electrode plate CF5, and the shape of the eleventh gate electrode Gate11 may be a polygonal line extending along the first direction X.

[0170] In an exemplary embodiment, the twelfth gate electrode Gate12 may be the gate electrode of the twelfth transistor T12, and the orthogonal projection of the base of the twelfth gate electrode Gate12 at least partially overlaps with the orthogonal projection of the base of the twelfth active layer. The twelfth gate electrode Gate12 may be located between the first scanning signal line S1 and the third top gate electrode Gate3-T, and the shape of the twelfth gate electrode Gate12 may be comb-like.

[0171] In an exemplary embodiment, a 12th gate electrode block 112 is provided on the side of the 12th gate electrode Gate12 away from the fifth gate electrode Gate5, and the 12th gate electrode block 112 may have an elongated shape extending along the first direction X, and the 12th gate electrode block 112 is configured to be connected to a 23rd connection electrode to be formed subsequently.

[0172] In an exemplary embodiment, the plurality of connection electrodes of each circuit unit includes at least a first connection electrode CO1, a second connection electrode CO2, a third connection electrode CO3, a fourth connection electrode CO4, a fifth connection electrode CO5, and a sixth connection electrode CO6.

[0173] In an exemplary embodiment, the first connection electrode CO1 may be rectangular in shape and may be located in a notch in the fourth plate CF4, and the first connection electrode CO1 is connected to the first plate CF1 through a first via V1.

[0174] In an exemplary embodiment, the second connection electrode CO2 may be rectangular in shape and may be located in a notch in the fifth electrode plate CF5, the second connection electrode CO2 may be connected to the second electrode plate CF2 through a second via V2, and the second connection electrode CO2 may be connected to the eleventh gate electrode Gate11.

[0175] In an exemplary embodiment, the second connection electrode CO2 and the eleventh gate electrode Gate11 may be an integrated structure connected to each other.

[0176] In an exemplary embodiment, the third connection electrode CO3 may be rectangular in shape and may be located in a notch in the sixth plate CF6, and the third connection electrode CO3 is connected to the third plate CF3 through a third via V3.

[0177] In an exemplary embodiment, the shape of the fourth connection electrode CO4 may be a broken line extending along the second direction Y, and in the first direction X, the fourth connection electrode CO4 may be located between the fifth gate electrode Gate5 and the twelfth gate electrode Gate12, and in the second direction Y, the fourth connection electrode CO4 may be located on the second direction Y side of the first scanning signal line S1, and the fourth connection electrode CO4 is configured to be connected to the thirteenth and fifteenth connection electrodes to be formed subsequently.

[0178] In an exemplary embodiment, the fifth connection electrode CO5 may have a polygonal line shape extending along the first direction X, and may be disposed between the first scanning signal line S1 and the twelfth gate electrode Gate12, and the fifth connection electrode CO5 is configured to be connected to the 19th and 20th connection electrodes to be formed subsequently.

[0179] In an exemplary embodiment, the sixth connecting electrode CO6 may have an elongated shape extending along the first direction X, and may be disposed between the second scanning signal line S2 and the high-frequency signal line Hf, and the sixth connecting electrode CO6 is configured to be connected to the subsequently formed 25th connecting electrode and 26th connecting electrode.

[0180] In an exemplary embodiment, the second conductive layer pattern may further include a seventh connection electrode CO7 installed in the third circuit unit Q3, the seventh connection electrode CO7 may have a rectangular shape, and the seventh connection electrode CO7 is connected to the power electrode 11 through the fifth via V5, and the seventh connection electrode CO7 is configured to be connected to the subsequently formed 33rd connection electrode.

[0181] In an exemplary embodiment, after forming the second conductive layer pattern, the semiconductor layer can be made conductive by using the second conductive layer as a shield. The semiconductor layer in the region blocked by the second conductive layer forms the channel regions of the first transistor T1 to the twelfth transistor T12. The semiconductor layer in the region not blocked by the first conductive layer is made conductive, i.e., both the first region and the second region of the first transistor T1 to the twelfth transistor T12 are made conductive.

[0182] (15) Forming a third insulating layer pattern. In an exemplary embodiment, as shown in Figure 11, forming the third insulating layer pattern may include depositing a third insulating thin film on the base on which the pattern is formed, and patterning the third insulating thin film through a patterning process to form a third insulating layer covering the second conductive layer, and a plurality of vias are provided in the third insulating layer.

[0183] In the exemplary embodiment, the plurality of vias in the third insulating layer in each circuit unit includes at least an eleventh via V11 to a fifty-eighth via V58.

[0184] In an exemplary embodiment, the orthogonal projection of the base of the eleventh via V11 is within the range of the orthogonal projection of the base of the first region of the first active layer. The third insulating layer and the second insulating layer within the eleventh via V11 are etched to expose the surface of the first region of the first active layer. The eleventh via V11 is configured to connect a subsequently formed eleventh connecting electrode to the first region of the first active layer through the via.

[0185] In an exemplary embodiment, the orthogonal projection of the base of the twelfth via V12 is within the range of the orthogonal projection of the base of the second region of the first active layer. The third insulating layer and the second insulating layer within the twelfth via V12 are etched to expose the surface of the second region of the first active layer. The twelfth via V12 is configured to connect a subsequently formed twelfth connecting electrode to the second region of the first active layer through the via.

[0186] In an exemplary embodiment, the orthogonal projection of the base of the via V13 is within the range of the orthogonal projection of the base of the first region of the second active layer. The third insulating layer and the second insulating layer within the via V13 are etched to expose the surface of the first region of the second active layer. The via V13 is configured to connect a subsequently formed twelfth connecting electrode to the first region of the second active layer through the via.

[0187] In an exemplary embodiment, the orthogonal projection of the base of the via V14 is within the range of the orthogonal projection of the base of the second region of the second active layer. The third insulating layer and the second insulating layer within the via V14 are etched to expose the surface of the second region of the second active layer. The via V14 is configured to connect a subsequently formed thirteenth connecting electrode to the second region of the second active layer through the via.

[0188] In an exemplary embodiment, the orthogonal projection of the base of the fifteenth via V15 is within the range of the orthogonal projection of the base of the first region of the third active layer. The third insulating layer and the second insulating layer within the fifteenth via V15 are etched to expose the surface of the first region of the third active layer. The fifteenth via V15 is configured to connect a subsequently formed fourteenth connecting electrode to the first region of the third active layer through the via.

[0189] In an exemplary embodiment, the orthogonal projection of the base of the sixteenth via V16 is within the range of the orthogonal projection of the base of the second region of the third active layer. The third insulating layer and the second insulating layer within the sixteenth via V16 are etched to expose the surface of the second region of the third active layer. The sixteenth via V16 is configured to connect a subsequently formed fifteenth connecting electrode to the second region of the third active layer through the via.

[0190] In an exemplary embodiment, the orthogonal projection of the base of the 17th via V17 is within the range of the orthogonal projection of the base of the first region of the fourth active layer. The third insulating layer and the second insulating layer within the 17th via V17 are etched to expose the surface of the first region of the fourth active layer. The 17th via V17 is configured to connect a subsequently formed data signal line through the via to the first region of the fourth active layer.

[0191] In the exemplary embodiment, the orthogonal projection of the base of the via V18 is within the range of the orthogonal projection of the base of the second region of the fourth active layer. The third insulating layer and the second insulating layer within the via V18 are etched to expose the surface of the second region of the fourth active layer. The via V18 is configured to connect a subsequently formed fourteenth connecting electrode to the second region of the fourth active layer through the via.

[0192] In an exemplary embodiment, the orthogonal projection of the base of the 19th via V19 is within the range of the orthogonal projection of the base of the first region of the fifth active layer. The third insulating layer and the second insulating layer within the 19th via V19 are etched to expose the surface of the first region of the fifth active layer. The 19th via V19 is configured to connect a subsequently formed 16th connecting electrode to the first region of the fifth active layer through the via.

[0193] In an exemplary embodiment, the orthogonal projection of the base of the 20th via V20 is within the range of the orthogonal projection of the base of the second region of the fifth active layer. The third insulating layer and the second insulating layer within the 20th via V20 are etched to expose the surface of the second region of the fifth active layer. The 20th via V20 is configured to connect a subsequently formed 14th connecting electrode to the second region of the fifth active layer through the via.

[0194] In the exemplary embodiment, the nineteenth vias V19 and the twentieth vias V20 are both plural, and the plural nineteenth vias V19 and the plural twentieth vias V20 are alternately arranged in the second direction Y.

[0195] In an exemplary embodiment, the orthogonal projection of the base of the via V21 is within the range of the orthogonal projection of the base of the first region of the sixth active layer. The third insulating layer and the second insulating layer within the via V21 are etched to expose the surface of the first region of the sixth active layer. The via V21 is configured to connect a subsequently formed connecting electrode to the first region of the sixth active layer through the via.

[0196] In an exemplary embodiment, the orthogonal projection of the base of the 22nd via V22 is within the range of the orthogonal projection of the base of the second region of the sixth active layer. The third insulating layer and the second insulating layer within the 22nd via V22 are etched to expose the surface of the second region of the sixth active layer. The 22nd via V22 is configured to connect a subsequently formed 17th connecting electrode to the second region of the sixth active layer through the via.

[0197] In the exemplary embodiment, there are a plurality of the 21st vias V21 and a plurality of the 22nd vias V22, and the plurality of the 21st vias V21 and the plurality of the 22nd vias V22 are arranged alternately in the second direction Y.

[0198] In an exemplary embodiment, the orthogonal projection of the base of the via V23 is within the range of the orthogonal projection of the base of the first region of the seventh active layer. The third insulating layer and the second insulating layer within the via V23 are etched to expose the surface of the seventh region of the seventh active layer. The via V23 is configured to connect a subsequently formed connecting electrode to the first region of the seventh active layer through the via.

[0199] In an exemplary embodiment, the orthogonal projection of the base of the 24th via V24 is within the range of the orthogonal projection of the base of the second region of the seventh active layer. The third insulating layer and the second insulating layer within the 24th via V24 are etched to expose the surface of the second region of the seventh active layer. The 24th via V24 is configured to connect a subsequently formed 19th connecting electrode to the second region of the seventh active layer through the via.

[0200] In an exemplary embodiment, the orthogonal projection of the base of the 25th via V25 is within the range of the orthogonal projection of the base of the first region of the 12th active layer. The third insulating layer and the second insulating layer within the 25th via V25 are etched to expose the surface of the first region of the 12th active layer. The 25th via V25 is configured to connect a subsequently formed 17th connecting electrode to the first region of the 12th active layer through the via.

[0201] In the exemplary embodiment, the orthogonal projection of the base of the 26th via V26 is within the range of the orthogonal projection of the base of the second region of the 12th active layer. The third insulating layer and the second insulating layer within the 26th via V26 are etched to expose the surface of the second region of the 12th active layer. The 26th via V26 is configured to connect a subsequently formed 20th connecting electrode to the second region of the 12th active layer through the via.

[0202] In the exemplary embodiment, the number of the 25th vias V25 and the number of the 26th vias V26 are both plural, and the plural 25th vias V25 and the plural 26th vias V26 are alternately arranged in the second direction Y.

[0203] In an exemplary embodiment, the orthogonal projection of the base of the 27th via V27 is within the range of the orthogonal projection of the base of the first region of the eighth active layer. The third insulating layer and the second insulating layer within the 27th via V27 are etched to expose the surface of the 9th region of the eighth active layer. The 27th via V27 is configured to connect a subsequently formed time-length signal line through the via to the first region of the eighth active layer.

[0204] In the exemplary embodiment, the orthogonal projection of the base of the via V28 is within the range of the orthogonal projection of the base of the second region of the eighth active layer. The third insulating layer and the second insulating layer within the via V28 are etched to expose the surface of the second region of the eighth active layer. The via V28 is configured to connect a subsequently formed connecting electrode to the second region of the eighth active layer through the via.

[0205] In an exemplary embodiment, the orthogonal projection of the base of the 29th via V29 is within the range of the orthogonal projection of the base of the first region of the 9th active layer. The third insulating layer and the second insulating layer within the 29th via V29 are etched to expose the surface of the first region of the 9th active layer. The 29th via V29 is configured to connect a subsequently formed 22nd connecting electrode to the first region of the 9th active layer through the via.

[0206] In an exemplary embodiment, the orthogonal projection of the base of the 30th via V30 is within the range of the orthogonal projection of the base of the second region of the ninth active layer. The third insulating layer and the second insulating layer within the 30th via V30 are etched to expose the surface of the second region of the ninth active layer. The 30th via V30 is configured to connect a subsequently formed 23rd connecting electrode through the via to the second region of the ninth active layer.

[0207] In an exemplary embodiment, the orthogonal projection of the base of the via V31 is within the range of the orthogonal projection of the base of the first region of the tenth active layer. The third insulating layer and the second insulating layer within the via V31 are etched to expose the surface of the first region of the tenth active layer. The via V31 is configured to connect a subsequently formed time-length signal line through the via to the first region of the tenth active layer.

[0208] In the exemplary embodiment, the orthogonal projection of the base of the 32nd via V32 is within the range of the orthogonal projection of the base of the second region of the tenth active layer. The third insulating layer and the second insulating layer within the 32nd via V32 are etched to expose the surface of the second region of the tenth active layer. The 32nd via V32 is configured to connect a subsequently formed 24th connecting electrode to the second region of the tenth active layer through the via.

[0209] In an exemplary embodiment, the orthogonal projection of the base of the via V33 is within the range of the orthogonal projection of the base of the first region of the eleventh active layer. The third insulating layer and the second insulating layer within the via V33 are etched to expose the surface of the first region of the eleventh active layer. The via V33 is configured to connect a subsequently formed 25th connecting electrode to the first region of the eleventh active layer through the via.

[0210] In the exemplary embodiment, the orthogonal projection of the base of the via V34 is within the range of the orthogonal projection of the base of the second region of the eleventh active layer. The third insulating layer and the second insulating layer within the via V34 are etched to expose the surface of the second region of the eleventh active layer. The via V34 is configured to connect a subsequently formed 23rd connecting electrode to the second region of the eleventh active layer through the via.

[0211] In the exemplary embodiment, the orthogonal projections of the bases of the 35th vias V35 and 36th vias V36 are within the range of the orthogonal projections of the bases of the light emission signal line EM. The third insulating layer in the 35th vias V35 and 36th vias V36 is etched to expose the surfaces of the light emission signal line EM, respectively. The 35th vias V35 and 36th vias V36 are configured to connect the 22nd and 27th connecting electrodes, which will be subsequently formed, to the light emission signal line EM, respectively.

[0212] In an exemplary embodiment, the orthogonal projections of the bases of the 37th via V37, the 38th via V38, and the 39th via V39 are each within the range of the orthogonal projection of the base of the initial signal line Vint. The third insulating layer in the 37th via V37, the 38th via V38, and the 39th via V39 is etched to expose the surface of the initial signal line Vint. The 37th via V37, the 38th via V38, and the 39th via V39 are configured to connect the 11th, 18th, and 28th connection electrodes, which will be formed subsequently, to the initial signal line Vint, respectively.

[0213] In the exemplary embodiment, the orthogonal projection of the base of the 40th via V40 is within the range of the orthogonal projection of the high-frequency signal line Hf on the base of the high-frequency connection block. The third insulating layer in the 40th via V40 is etched to expose the surface of the high-frequency connection block. The 40th via V40 is configured to connect a subsequently formed 26th connection electrode to the high-frequency signal line Hf through the via.

[0214] In an exemplary embodiment, the orthogonal projection of the base of the 41st via V41 is within the range of the orthogonal projection of the high-voltage connection line VDD-C on the base of the high-voltage connection block. The third insulating layer in the 41st via V41 is etched to expose the surface of the high-voltage connection block. The 41st via V41 is configured to connect a subsequently formed 16th connection electrode to the high-voltage connection line VDD-C through the via.

[0215] In the exemplary embodiment, the orthogonal projection of the base of the via V42 is within the range of the orthogonal projection of the base of the fifth electrode plate CF5. The third insulating layer in the via V42 is etched to expose the surface of the fifth electrode plate CF5. The via V42 is configured to connect a subsequently formed 28th connection electrode to the fifth electrode plate CF5 through the via.

[0216] In the exemplary embodiment, the orthogonal projection of the base of the via V43 is within the range of the orthogonal projection of the base of the sixth electrode plate CF6. The third insulating layer in the via V43 is etched to expose the surface of the sixth electrode plate CF6. The via V43 is configured to connect a subsequently formed twelfth connection electrode to the sixth electrode plate CF6 through the via.

[0217] In the exemplary embodiment, the orthogonal projection of the base of the via V44 is within the range of the orthogonal projection of the base of the first connection electrode CO1. The third insulating layer within the via V44 is etched to expose the surface of the first connection electrode CO1. The via V44 is configured to connect a subsequently formed seventh electrode plate to the first connection electrode CO1 through the via.

[0218] In the exemplary embodiment, the orthogonal projection of the base of the via V45 is within the range of the orthogonal projection of the base of the second connection electrode CO2. The third insulating layer within the via V45 is etched to expose the surface of the second connection electrode CO2. The via V45 is configured to connect a subsequently formed eighth electrode plate to the second connection electrode CO2 through the via.

[0219] In the exemplary embodiment, the orthogonal projection of the base of the 46th via V46 is within the range of the orthogonal projection of the base of the third connection electrode CO3. The third insulating layer within the 46th via V46 is etched to expose the surface of the third connection electrode CO3. The 46th via V46 is configured to connect a subsequently formed ninth electrode plate to the third connection electrode CO3 through the via.

[0220] In the exemplary embodiment, the orthogonal projection of the base of the 47th via V47 is within the range of the orthogonal projection of the base of the first end of the fourth connection electrode CO4. The third insulating layer in the 47th via V47 is etched to expose the surface of the first end of the fourth connection electrode CO4. The 47th via V47 is configured to connect a subsequently formed 13th connection electrode through the via to the first end of the fourth connection electrode CO4.

[0221] In the exemplary embodiment, the orthogonal projection of the base of the via V48 is within the range of the orthogonal projection of the base of the second end of the fourth connection electrode CO4. The third insulating layer in the via V48 is etched to expose the surface of the second end of the fourth connection electrode CO4. The via V48 is configured to connect a subsequently formed fifteenth connection electrode through the via to the second end of the fourth connection electrode CO4.

[0222] In the exemplary embodiment, the orthogonal projection of the base of the 49th via V49 is within the range of the orthogonal projection of the base of the first end of the fifth connecting electrode CO5. The third insulating layer in the 49th via V49 is etched to expose the surface of the first end of the fifth connecting electrode CO5. The 49th via V49 is configured to connect a subsequently formed 20th connecting electrode through the via to the first end of the fifth connecting electrode CO5.

[0223] In the exemplary embodiment, the orthogonal projection of the base of the 50th via V50 is within the range of the orthogonal projection of the base of the second end of the fifth connecting electrode CO5. The third insulating layer in the 50th via V50 is etched to expose the surface of the second end of the fifth connecting electrode CO5. The 50th via V50 is configured to connect a subsequently formed 19th connecting electrode through the via to the second end of the fifth connecting electrode CO5.

[0224] In the exemplary embodiment, the orthogonal projection of the base of the via V51 is within the range of the orthogonal projection of the base of the first end of the sixth connecting electrode CO6. The third insulating layer in the via V51 is etched to expose the surface of the first end of the sixth connecting electrode CO6. The via V51 is configured to connect a subsequently formed 25th connecting electrode through the via to the first end of the sixth connecting electrode CO6.

[0225] In the exemplary embodiment, the orthogonal projection of the base of the 52nd via V52 is within the range of the orthogonal projection of the base of the second end of the sixth connecting electrode CO6. The third insulating layer in the 52nd via V52 is etched to expose the surface of the second end of the sixth connecting electrode CO6. The 52nd via V52 is configured to connect a subsequently formed 26th connecting electrode to the second end of the sixth connecting electrode CO6 through the via.

[0226] In the exemplary embodiment, the orthogonal projection of the base of the 53rd via V53 is within the range of the orthogonal projection of the base of the third gate electrode block 103 of the third top gate electrode Gate3-T. The third insulating layer in the 53rd via V53 is etched to expose the surface of the third gate electrode block 103. The 53rd via V53 is configured to connect a subsequently formed twelfth connection electrode to the third top gate electrode Gate3-T through the via.

[0227] In the exemplary embodiment, the orthogonal projection of the base of the 54th via V54 is within the range of the orthogonal projection of the base of the fifth gate electrode block 105 of the fifth gate electrode Gate5. The third insulating layer in the 54th via V54 is etched to expose the surface of the fifth gate electrode block 105. The 54th via V54 is configured to connect a subsequently formed 27th connection electrode to the fifth gate electrode Gate5 through the via.

[0228] In the exemplary embodiment, the orthogonal projection of the base of the 55th via V55 is within the range of the orthogonal projection of the base of the sixth gate electrode block 106 of the sixth gate electrode Gate6. The third insulating layer in the 55th via V55 is etched to expose the surface of the sixth gate electrode block 106. The 55th via V55 is configured to connect a subsequently formed 22nd connection electrode to the sixth gate electrode Gate6 through the via.

[0229] In the exemplary embodiment, the orthogonal projection of the base of the 56th via V56 is within the range of the orthogonal projection of the base of the twelfth gate electrode block 112 of the twelfth gate electrode Gate12. The third insulating layer in the 56th via V56 is etched to expose the surface of the twelfth gate electrode block 112. The 56th via V56 is configured to connect a subsequently formed 23rd connection electrode to the twelfth gate electrode Gate12 through the via.

[0230] In the exemplary embodiment, the orthogonal projection of the base of the 57th via V57 is within the range of the orthogonal projection of the base of the ninth gate electrode Gate 9. The third insulating layer in the 57th via V57 is etched to expose the surface of the ninth gate electrode Gate 9. The 57th via V57 is configured to connect a subsequently formed 21st connecting electrode to the ninth gate electrode Gate 9 through the via.

[0231] In the exemplary embodiment, the orthogonal projection of the base of the 58th via V58 is within the range of the orthogonal projection of the base of the 11th gate electrode Gate11. The third insulating layer in the 58th via V58 is etched to expose the surface of the 11th gate electrode Gate11. The 58th via V58 is configured to connect a subsequently formed 24th connection electrode to the 11th gate electrode Gate11 through the via.

[0232] In an exemplary embodiment, the plurality of vias in the third insulating layer may further include a 59th via V59 to a 62nd via V62.

[0233] In the exemplary embodiment, the orthogonal projection of the base of the 59th via V59 is within the range of the orthogonal projection of the base of the high-voltage connecting line VDD-C in the third circuit unit Q3. The third insulating layer in the 59th via V59 is etched to expose the surface of the high-voltage connecting line VDD-C. The 59th via V59 is configured to connect a subsequently formed 31st connecting electrode to the high-voltage connecting line VDD-C through the via.

[0234] In the exemplary embodiment, the orthogonal projection of the base of the 60th via V60 is within the range of the orthogonal projection of the base of the low-voltage connection block of the low-voltage connection line VSS-C in the first circuit unit Q1 and the second circuit unit Q2. The third insulating layer in the 60th via V60 is etched to expose the surface of the low-voltage connection block. The 60th via V60 is configured to connect a subsequently formed 32nd connection electrode to the low-voltage connection line VSS-C through the via.

[0235] In the exemplary embodiment, the orthogonal projection of the base of the 61st via V61 is within the range of the orthogonal projection of the base of the seventh connecting electrode CO7 in the third circuit unit Q3. The third insulating layer in the 61st via V61 is etched to expose the surface of the seventh connecting electrode CO7. The 61st via V61 is configured to connect the subsequently formed 33rd connecting electrode to the seventh connecting electrode CO7 through the via.

[0236] In the exemplary embodiment, the orthogonal projection of the base of the 62nd via V62 is within the range of the orthogonal projection of the base of the power electrode 11 in the third circuit unit Q3. The third insulating layer, the second insulating layer, and the first insulating layer in the 62nd via V62 are etched to expose the surface of the power electrode 11. The 62nd via V62 is configured to connect a subsequently formed 33rd connection electrode to the power electrode 11 through the via.

[0237] (16) Forming a third conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 12A and 12B, forming the third conductive layer pattern may include depositing a third conductive thin film on the base on which the above-mentioned pattern is formed, and patterning the third conductive thin film by a patterning process to form a third conductive layer pattern disposed on the third insulating layer. FIG. 12B is a schematic plan view of the third conductive layer in FIG. 12A. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0238] In an exemplary embodiment, the third conductive layer pattern of each circuit unit includes at least a data signal line DataI, a time-length signal line DataT, a seventh electrode plate CF7, an eighth electrode plate CF8, a ninth electrode plate CF9, an anode connection block 12, and an eleventh connection electrode CO11 to a twenty-eighth connection electrode CO28.

[0239] In an exemplary embodiment, the data signal line DataI may have a linear shape with its main body extending along the second direction Y, and may be located on the opposite side of the circuit unit in the first direction X. The data signal line DataI is connected to the first region of the fourth active layer through the seventeenth via V17, thereby realizing the data signal line DataI to write a data signal to the first pole of the fourth transistor T4.

[0240] In an exemplary embodiment, the time-long signal line DataT may have a linear shape with its main body extending along the second direction Y and may be located on the first direction X side of the circuit unit. On the one hand, the time-long signal line DataT is connected to the first region of the eighth active layer through the 27th via V27, and on the other hand, the time-long signal line DataT is connected to the first region of the tenth active layer through the 31st via V31. Thus, the time-long signal line DataT writes time-long signals to the first pole of the eighth transistor T8 and the first pole of the tenth transistor T10, respectively.

[0241] In an exemplary embodiment, the seventh plate CF7 may have an L-shape, the orthogonal projection at the base of the seventh plate CF7 at least partially overlaps with the orthogonal projection at the base of the fourth plate CF4, and the seventh plate CF7 is connected to the first connection electrode CO1 through the via V44. The seventh plate CF7 may be another plate of a first capacitor, and the fourth plate CF4 and the seventh plate CF7 constitute another first capacitor of the pixel driving circuit.

[0242] In the exemplary embodiment, the seventh plate CF7 is connected to the first connecting electrode CO1 through the 44th via V44, and the first connecting electrode CO1 is connected to the first plate CF1 through the via, so that the first plate CF1 and the seventh plate CF7 have the same potential, whereby the first plate CF1, the fourth plate CF4 and the third plate 97 form a first capacitor of a parallel connection structure, the first plate CF1 and the fourth plate CF4 form one first capacitor of the pixel driving circuit, and the fourth plate CF4 and the seventh plate CF7 form another first capacitor of the pixel driving circuit, and the two first capacitors are connected in parallel.

[0243] In an exemplary embodiment, the eighth plate CF8 may have a rectangular shape, the orthogonal projection at the base of the eighth plate CF8 at least partially overlaps with the orthogonal projection at the base of the fifth plate CF5, and the eighth plate CF8 is connected to the second connection electrode CO2 through the 45th via V45. The eighth plate CF8 may be another plate of a second capacitor, and the fifth plate CF5 and the eighth plate CF8 constitute another second capacitor of the pixel driving circuit.

[0244] In the exemplary embodiment, the eighth plate CF8 is connected to the second connection electrode CO2 through the 45th via V45, and the second connection electrode CO2 is connected to the second plate CF2 through the via, so that the second plate CF2 and the eighth plate CF8 have the same potential, whereby the second plate CF2, the fifth plate CF5 and the eighth plate CF8 form a second capacitor in a parallel connection structure, the second plate CF2 and the fifth plate CF5 form one second capacitor of the pixel driving circuit, and the fifth plate CF5 and the eighth plate CF8 form another second capacitor of the pixel driving circuit, and the two second capacitors are connected in parallel.

[0245] In an exemplary embodiment, the ninth plate CF9 may have a rectangular shape, the orthogonal projection at the base of the ninth plate CF9 at least partially overlaps with the orthogonal projection at the base of the sixth plate CF6, and the ninth plate CF9 is connected to the third connection electrode CO3 through the 46th via V46. The ninth plate CF9 may be another plate of a storage capacitor, and the sixth plate CF6 and the ninth plate CF9 constitute another storage capacitor of the pixel driving circuit.

[0246] In the exemplary embodiment, the ninth plate CF9 is connected to the third connecting electrode CO3 through the forty-sixth via V46, and the third connecting electrode CO3 is connected to the third plate CF3 through the via, so that the third plate CF3 and the ninth plate CF9 have the same potential, whereby the third plate CF3, the sixth plate CF6, and the ninth plate CF9 form a storage capacitor in a parallel connection structure, the third plate CF3 and the sixth plate CF6 form one storage capacitor of the pixel driving circuit, and the sixth plate CF6 and the ninth plate CF9 form the other storage capacitor of the pixel driving circuit, and the two storage capacitors are connected in parallel.

[0247] In an exemplary embodiment, the position, shape and size of the ninth electrode plate CF9 in the second circuit unit Q2 and the third circuit unit Q3 may be substantially the same, but different from the shape and size of the ninth electrode plate CF9 in the first circuit unit Q1.

[0248] In an exemplary embodiment, the area of ​​the ninth plate CF9 in the first circuit unit Q1 may be larger than the area of ​​the ninth plate CF9 in the second circuit unit Q2, and the area of ​​the ninth plate CF9 in the first circuit unit Q1 may be larger than the area of ​​the ninth plate CF9 in the third circuit unit Q3, so that the capacitance value of the storage capacitor in the first circuit unit Q1 is larger than the capacitance values ​​of the storage capacitors in the second circuit unit Q2 and the third circuit unit Q3.

[0249] In an exemplary embodiment, the first lengths M1 of the ninth plate CF9 in the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be approximately the same, and the second length M2 of the ninth plate CF9 in the first circuit unit Q1 may be greater than the second length M2 of the ninth plate CF9 in the second circuit unit Q2 and the third circuit unit Q3, so that the area of ​​the ninth plate CF9 in the first circuit unit Q1 is greater than the area of ​​the ninth plate CF9 in the second circuit unit Q2 and the third circuit unit Q3.

[0250] In an exemplary embodiment, the ratio between the second length M2 of the ninth electrode plate CF9 in the first circuit unit Q1 and the second length M2 of the ninth electrode plate CF9 in the second circuit unit Q2 and the third circuit unit Q3 may be about 1 to 2. For example, the ratio may be about 1.3.

[0251] In an exemplary embodiment, the shape of the 11th connecting electrode CO11 may be elongated extending along the second direction Y, and the first end of the 11th connecting electrode CO11 is connected to the first region of the first active layer through the 11th via V11, and the second end of the 11th connecting electrode CO11 is connected to the initial signal line Vint through the 37th via V37, so that the initial signal line Vint writes an initial signal to the first pole of the first transistor T1.

[0252] In an exemplary embodiment, the 12th connecting electrode CO12 may have an elongated shape extending along the second direction Y, and a first end of the 12th connecting electrode CO12 close to the 9th electrode plate CF9 is connected to the 6th electrode plate CF6 via the 43rd via V43, a second end of the 12th connecting electrode CO12 close to the 7th electrode plate CF7 is connected to the 3rd gate electrode block 103 via the 53rd via V53, and a portion of the 12th connecting electrode CO12 between the first and second ends is connected to the second region of the first active layer via the 12th via V12 and to the first region of the second active layer via the 13th via V13. In the exemplary embodiment, the third gate electrode block 103 is connected to the third top gate electrode Gate3-T, and the third top gate electrode Gate3-T is connected to the third bottom gate electrode Gate3-B, so that the second pole of the first transistor T1, the first pole of the second transistor T2, the gate electrode of the third transistor T3, and the sixth plate CF6 have the same potential (i.e., the third node N3 of the pixel driving circuit) through the twelfth connecting electrode CO12, and the twelfth connecting electrode CO12 may also be referred to as the third node electrode.

[0253] In an exemplary embodiment, the 13th connecting electrode CO13 may have an elongated shape extending along the first direction X, and a first end of the 13th connecting electrode CO13 is connected to the second region of the second active layer via the 14th via V14, and a second end of the 13th connecting electrode CO13 is connected to the first end of the fourth connecting electrode CO4 via the 47th via V47.

[0254] In an exemplary embodiment, the shape of the fourteenth connecting electrode CO14 may be a polygonal line extending along the second direction Y, with a first end of the fourteenth connecting electrode CO14 connected to a first region of the third active layer via a fifteenth via V15, a second end of the fourteenth connecting electrode CO14 connected to a second region of the fourth active layer via a eighteenth via V18, and a portion of the fourteenth connecting electrode CO14 between the first and second ends connected to a second region of the fifth active layer via a tenth via V20. In an exemplary embodiment, the fourteenth connecting electrode CO14 causes the first pole of the third transistor T3, the second pole of the fourth transistor T4, and the second pole of the fifth transistor T5 to have the same potential (i.e., a fifth node N5 of the pixel driving circuit), and the fourteenth connecting electrode CO14 may be referred to as a fifth node electrode.

[0255] In an exemplary embodiment, the shape of the fifteenth-connecting electrode CO15 may be a polygonal line extending along the first direction X, with a first end of the fifteenth-connecting electrode CO15 connected to the second region of the third active layer via the sixteenth via V16, a second end of the fifteenth-connecting electrode CO15 connected to the first region of the sixth active layer via the twenty-first via V21, and a portion of the fifteenth-connecting electrode CO15 between the first and second ends connected to the second end of the fourth-connecting electrode CO4 via the twenty-eighth via V48. In an exemplary embodiment, the fourth-connecting electrode CO4 is connected to the thirteenth-connecting electrode CO13 via a via, and the thirteenth-connecting electrode CO13 is connected to the second region of the second active layer. Therefore, the fifteenth-connecting electrode CO15 causes the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole of the sixth transistor T6 to have the same potential (i.e., the fourth node N4 of the pixel driving circuit), and the fifteenth-connecting electrode CO15 may be referred to as a fourth-node electrode.

[0256] In an exemplary embodiment, the shape of the 16th connecting electrode CO16 may be a broken line extending along the second direction Y, and a first end of the 16th connecting electrode CO16 is connected to the first region of the fifth active layer via the 19th via V19, and a second end of the 16th connecting electrode CO16 is connected to the high-voltage connecting line VDD-C via the 41st via V41.

[0257] In an exemplary embodiment, the shape of the 17th connecting electrode CO17 may be a broken line extending along the second direction Y, and the first end of the 17th connecting electrode CO17 is connected to the second region of the sixth active layer through the 22nd via V22, and the second end of the 17th connecting electrode CO17 is connected to the first region of the 12th active layer through the 25th via V25, thereby realizing a connection between the second pole of the sixth transistor T6 and the first pole of the 12th transistor T12.

[0258] In an exemplary embodiment, the shape of the 18th connecting electrode CO18 may be a broken line extending along the second direction Y, a first end of the 18th connecting electrode CO18 is connected to the initial signal line Vint through the 38th via V38, a second end of the 18th connecting electrode CO18 is connected to the seventh electrode plate CF7, and a portion between the first and second ends of the 18th connecting electrode CO18 is connected to the first region of the seventh active layer through the 23rd via V23, so that the initial signal line Vint writes an initial signal to the first electrode of the seventh transistor T7 and one electrode plate of the first capacitor.

[0259] In an exemplary embodiment, the shape of the 19th connecting electrode CO19 may be a broken line extending along the second direction Y, and a first end of the 19th connecting electrode CO19 is connected to the second region of the seventh active layer via the 24th via V24, and a second end of the 19th connecting electrode CO19 is connected to the second end of the 5th connecting electrode CO5 via the 50th via V50.

[0260] In an exemplary embodiment, the shape of the 20th connection electrode CO20 may be a broken line extending along the second direction Y, and the first end of the 20th connection electrode CO20 is connected to the second region of the 12th active layer via the 26th via V26, and the second end of the 20th connection electrode CO20 is connected to the first end of the 5th connection electrode CO5 via the 49th via V49.

[0261] In the exemplary embodiment, the 20th connecting electrode CO20 is connected to the first end of the fifth connecting electrode CO5, and the 19th connecting electrode CO19 is connected to the second end of the fifth connecting electrode CO5, so that with the 19th connecting electrode CO19, the fifth connecting electrode CO5, and the 20th connecting electrode CO20 connected to each other, the second pole of the seventh transistor T7 and the second pole of the twelfth transistor T12 have the same potential (i.e., the second node N2 of the pixel driving circuit).

[0262] In an exemplary embodiment, the anode connection block 12 may be installed on the side of the 19th connection electrode CO19 away from the seventh electrode plate CF7 and connected to the 19th connection electrode CO19 via a connection wire, and the anode connection block 12 is configured to be connected to a subsequently formed anode connection electrode.

[0263] In an exemplary embodiment, the anode connection block 12 of the first circuit unit Q1 may be located on the first direction X side of the ninth electrode plate CF9, and the anode connection blocks 12 of the second circuit unit Q2 and the third circuit unit Q3 may be located on the opposite side of the ninth electrode plate CF9 in the second direction Y.

[0264] In an exemplary embodiment, the shape of the twenty-first connecting electrode CO21 may be elongated extending along the second direction Y, with a first end of the twenty-first connecting electrode CO21 connected to the second region of the eighth active layer through the twenty-eighth via V28 and a second end of the twenty-first connecting electrode CO21 connected to the ninth gate electrode Gate9 through the fifty-seventh via V57. Because the ninth gate electrode Gate9 is connected to the fourth electrode plate CF4, the twenty-first connecting electrode CO21 causes the second electrode of the eighth transistor T8, the gate electrode of the ninth transistor T9, and the fourth electrode plate CF4 to have the same potential (i.e., the sixth node N6 of the pixel driving circuit).

[0265] In an exemplary embodiment, the shape of the 22nd connecting electrode CO22 may be elongated extending along the second direction Y, and the first end of the 22nd connecting electrode CO22 is connected to the first region of the 9th active layer through the 29th via V29, the second end of the 22nd connecting electrode CO22 is connected to the light-emitting signal line EM through the 35th via V35, and the portion between the first and second ends of the 22nd connecting electrode CO22 is connected to the 6th gate electrode block 106 of the 6th gate electrode Gate6 through the 55th via V55, so that the light-emitting signal line EM controls the turning on or off of the 6th transistor T6 to write the light-emitting signal to the first pole of the 9th transistor T9.

[0266] In an exemplary embodiment, the shape of the 23rd connecting electrode CO23 may be elongated extending along the second direction Y, and a first end of the 23rd connecting electrode CO23 is connected to the second region of the 9th active layer via the 30th via V30, a second end of the 23rd connecting electrode CO23 is connected to the second region of the 11th active layer via the 34th via V34, and a portion between the first and second ends of the 23rd connecting electrode CO23 is connected to the 12th gate electrode block 112 of the 12th gate electrode Gate12 via the 56th via V56, so that the second pole of the 9th transistor T9, the second pole of the 11th transistor T11 and the gate electrode of the 12th transistor T12 have the same potential (i.e., the first node N1 of the pixel driving circuit).

[0267] In an exemplary embodiment, the shape of the 24th connecting electrode CO24 may be elongated extending along the second direction Y, with a first end of the 24th connecting electrode CO24 connected to the second region of the tenth active layer through the 32nd via V32 and a second end of the 24th connecting electrode CO24 connected to the 11th gate electrode Gate11 through the 58th via V58. The 11th gate electrode Gate11 is connected to the second connecting electrode CO2, and the second connecting electrode CO2 is connected to the second electrode plate CF2 through a via, so that the 24th connecting electrode CO24 causes the second electrode of the tenth transistor T10, the gate electrode of the 11th transistor T11, and the second electrode plate CF2 to have the same potential (i.e., the seventh node N7 of the pixel driving circuit).

[0268] In an exemplary embodiment, the shape of the 25th connecting electrode CO25 may be L-shaped, and a first end of the 25th connecting electrode CO25 is connected to the first region of the 11th active layer through the 33rd via V33, and a second end of the 25th connecting electrode CO25 is connected to the first end of the 6th connecting electrode CO6 through the 51st via V51.

[0269] In an exemplary embodiment, the connecting electrode CO26 may have an elongated shape extending along the second direction Y, with a first end of the connecting electrode CO26 connected to the high-frequency signal line Hf through the via V40 and a second end of the connecting electrode CO26 connected to the second end of the sixth connecting electrode CO6 through the via V52. The high-frequency signal line Hf is connected to the first region of the eleventh active layer through the connecting electrode CO26, the sixth connecting electrode CO6, and the connecting electrode CO25, thereby enabling the high-frequency signal line Hf to write a high-frequency signal to the first pole of the eleventh transistor T11.

[0270] In an exemplary embodiment, the shape of the 27th connecting electrode CO27 may be elongated extending along the second direction Y, and a first end of the 27th connecting electrode CO27 is connected to the light-emitting signal line EM through the 36th via V36, and a second end of the 27th connecting electrode CO27 is connected to the fifth gate electrode block 105 of the fifth gate electrode Gate5 through the 54th via V54, thereby realizing that the light-emitting signal line EM controls the turning on or off of the fifth transistor T5.

[0271] In an exemplary embodiment, the shape of the 28th connecting electrode CO28 may be elongated extending along the second direction Y, and a first end of the 28th connecting electrode CO28 is connected to the initial signal line Vint through the 39th via V39, and a second end of the 28th connecting electrode CO28 is connected to the fifth electrode plate CF5 through the 42nd via V42, so that the initial signal line Vint writes an initial signal to one electrode plate of the second capacitor.

[0272] In an exemplary embodiment, the third conductive layer may further include a thirty-first connection electrode CO31, a thirty-second connection electrode CO32, and a thirty-third connection electrode CO33.

[0273] In an exemplary embodiment, the connecting electrode CO31 may have a rectangular shape and may be disposed in the third circuit unit Q3, and the connecting electrode CO31 is connected to the high-voltage connecting line VDD-C of the third circuit unit Q3 through the via hole V59. In an exemplary embodiment, the connecting electrode CO31 is configured to be connected to a high-voltage power supply line to be formed later.

[0274] In an exemplary embodiment, the 32nd connecting electrode CO32 may have a rectangular shape and may be disposed in the first circuit unit Q1 and the second circuit unit Q2. The 32nd connecting electrode CO32 is connected to the low-voltage connecting block of the low-voltage connecting line VSS-C in the first circuit unit Q1 and the second circuit unit Q2 through the 60th via V60. In an exemplary embodiment, the 32nd connecting electrode CO32 is configured to be connected to a low-voltage power supply line to be formed subsequently.

[0275] In an exemplary embodiment, the thirty-third connecting electrode CO33 may have a rectangular shape and may be disposed in the third circuit unit Q3, where on the one hand, the thirty-third connecting electrode CO33 is connected to the seventh connecting electrode CO7 through the sixty-first via V61, and on the other hand, the thirty-third connecting electrode CO33 is connected to the power supply electrode 11 through the sixty-second via V62. In an exemplary embodiment, the thirty-third connecting electrode CO33 is configured to be connected to a subsequently formed high-voltage power supply line.

[0276] (17) Forming a fourth insulating layer and a first flat layer pattern. In an exemplary embodiment, as shown in Figure 13, forming the fourth insulating layer and the first flat layer pattern may include first applying a first flat thin film on the base on which the above-mentioned pattern is formed, patterning the first flat thin film by a patterning process, depositing a fourth insulating thin film, and patterning the first flat thin film by a patterning process to form a first flat layer covering the third conductive layer pattern and a fourth insulating layer disposed on a side of the first flat layer away from the base, and a plurality of vias are disposed in the fourth insulating layer and the first flat layer.

[0277] In the exemplary embodiment, the plurality of vias in the fourth insulating layer and the first planar layer in each circuit unit includes at least a 65th via V65.

[0278] In the exemplary embodiment, the orthogonal projection of the base of the 65th via V65 is within the range of the orthogonal projection of the base of the anode connection block 12. The fourth insulating thin film and the first planar thin film in the 65th via V65 are removed to expose the surface of the anode connection block 12. The 65th via V65 is configured to connect a subsequently formed anode connection electrode to the anode connection block 12 through the via.

[0279] In an exemplary embodiment, the plurality of vias in the fourth insulating layer and the first planar layer may further include a 66th via V66, a 67th via V67, and a 68th via V68.

[0280] In an exemplary embodiment, the orthogonal projection of the base of the 66th via V66 is within the range of the orthogonal projection of the base of the 31st connecting electrode CO31 and may be located in the third circuit unit Q3. The fourth insulating thin film and the first planar thin film in the 66th via V66 are removed to expose the surface of the 31st connecting electrode CO31. The 66th via V66 is configured to connect a subsequently formed high-voltage power line to the 31st connecting electrode CO31 through the via.

[0281] In an exemplary embodiment, the orthogonal projection of the base of the 67th via V67 is within the range of the orthogonal projection of the base of the 32nd connecting electrode CO32 and may be disposed in the first circuit unit Q1 and the second circuit unit Q2, respectively. The fourth insulating thin film and the first planar thin film in the 67th via V67 are removed to expose the surface of the 32nd connecting electrode CO32. The 67th via V67 is configured to connect a subsequently formed low-voltage power line to the 32nd connecting electrode CO32 through the via.

[0282] In an exemplary embodiment, the orthogonal projection of the base of the via V68 is within the range of the orthogonal projection of the base of the connecting electrode CO33 and may be located in the third circuit unit Q3. The fourth insulating thin film and the first planar thin film in the via V68 are removed to expose the surface of the connecting electrode CO33. The via V68 is configured to connect a subsequently formed high-voltage power line to the connecting electrode CO33.

[0283] (18) Forming a fourth conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 14A and 14B, forming the fourth conductive layer pattern may include depositing a fourth conductive thin film on the base on which the above-mentioned pattern is formed, and patterning the fourth conductive thin film by a patterning process to form a fourth conductive layer pattern disposed on the fourth insulating layer. FIG. 14B is a schematic plan view of the fourth conductive layer in FIG. 14A. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0284] In the exemplary embodiment, the fourth conductive layer pattern of each circuit unit includes at least an anode connecting electrode 13 .

[0285] In an exemplary embodiment, the anode connecting electrode 13 may have a rectangular shape and is connected to the anode connecting block 12 through the 65th via V65. The anode connecting electrode 13 is configured to be bound-connected to the first electrode of the light-emitting diode. The anode connecting block 12 is connected to the 19th connecting electrode CO19, which is connected to the 20th connecting electrode CO20 through the 5th connecting electrode CO5, and the 20th connecting electrode CO20 is connected to the second region of the 12th active layer through a via. This establishes a connection between the anode connecting electrode 13 and the second electrode of the seventh transistor T7 and the second electrode of the 12th transistor T12, allowing the pixel driving circuit to drive the light-emitting diode to emit light.

[0286] In an exemplary embodiment, the fourth conductive layer pattern may further include at least a high voltage power line VDD and a low voltage power line VSS, where the high voltage power line may be referred to as a first power line and the low voltage power line may be referred to as a second power line.

[0287] In an exemplary embodiment, the high-voltage power supply line VDD may have a linear shape extending along the second direction Y and may be installed in the third circuit unit Q3, where on the one hand, the high-voltage power supply line VDD is connected to the 31st connecting electrode CO31 through the 66th via V66, and on the other hand, the high-voltage power supply line VDD is connected to the 33rd connecting electrode CO33 through the 68th via V68.

[0288] In the exemplary embodiment, the 31st connecting electrode CO31 is connected to the high-voltage connecting line VDD-C through a via. Therefore, the high-voltage connecting line VDD-C extending along the first direction X and the high-voltage power supply line VDD extending along the second direction Y form a net-like interconnection structure, which not only minimizes the resistance of the power supply transmission line but also reduces the drop in power supply voltage, effectively improving the uniformity of the power supply voltage on the display substrate, effectively improving the uniformity in the signal plane, effectively improving display uniformity, and improving display attributes and display quality.

[0289] In the exemplary embodiment, the high-voltage connecting line VDD-C is respectively connected to the 16th connecting electrode CO16 of each circuit unit through a via, and the 16th connecting electrode CO16 is connected to the first region of the fifth active layer through a via, so that the high-voltage power supply line VDD realizes writing the first power supply signal to the first pole of the fifth transistor T5 of each circuit unit.

[0290] In the exemplary embodiment, the thirty-third connecting electrode CO33 is connected to the power supply electrode 11 via the seventh connecting electrode CO7, which is connected to the integrated third plate CF3, which is connected to the ninth plate CF9 via the third connecting electrode CO3. Therefore, the third plate CF3 and the ninth plate CF9 of the storage capacitor have the potential of the high-voltage power supply line VDD. The sixth plate CF6 is connected to the twelfth connecting electrode CO12 via a via, which is connected to the third top gate electrode Gate3-T via a via. Therefore, the sixth plate CF6 has the potential of the gate electrode of the third transistor T3. In this manner, the third plate CF3 having the potential of the high-voltage power supply line VDD and the sixth plate CF6 having the potential of the gate electrode of the third transistor T3 constitute one storage capacitor of the pixel driving circuit, and the sixth plate CF6 having the potential of the gate electrode of the third transistor T3 and the ninth plate CF9 having the potential of the high-voltage power supply line VDD constitute another storage capacitor of the pixel driving circuit.

[0291] In the exemplary embodiment, in the third circuit unit Q3, the orthogonal projection of the base of the high-voltage power supply line VDD at least partially overlaps with the orthogonal projection of the base of the twelfth connecting electrode CO12. Because the high-voltage power supply line VDD has a constant potential, the high-voltage power supply line VDD not only effectively shields the influence of data voltage jumps and other signals on the key nodes of the pixel driving circuit, but also prevents data voltage jumps and other signals from affecting the potential of the key nodes, effectively avoiding crosstalk degradation and improving the display effect.

[0292] In an exemplary embodiment, the low-voltage power line VSS may have a linear shape extending along the second direction Y and may be installed in the first circuit unit Q1 and the second circuit unit Q2, respectively, and the low-voltage power line VSS is connected to the 32nd connection electrode CO32 through the 67th via V67.

[0293] In the exemplary embodiment, the 32nd connecting electrode CO32 is connected to the low-voltage connecting line VSS-C through a via. Therefore, the low-voltage connecting line VSS-C extending along the first direction X and the low-voltage power supply line VSS extending along the second direction Y form a net-like interconnection structure, which not only minimizes the resistance of the power transmission line but also reduces the drop in power supply voltage, effectively improving the uniformity of the power supply voltage on the display substrate, effectively improving the uniformity in the signal plane, effectively improving display uniformity, and improving display attributes and display quality.

[0294] In the exemplary embodiment, in the second circuit unit Q2, the orthogonal projection of the low-voltage power line VSS at the base at least partially overlaps with the orthogonal projection of the base of the twelfth connecting electrode CO12. Because the low-voltage power line VSS is at a constant potential, the low-voltage power line VSS not only effectively shields the influence of data voltage jumps and other signals on the key nodes of the pixel driving circuit, but also prevents data voltage jumps and other signals from affecting the potential of the key nodes, effectively avoiding crosstalk degradation and improving the display effect.

[0295] (19) Forming a fifth insulating layer and a second planar layer pattern. In an exemplary embodiment, as shown in FIG. 15 , forming the fifth insulating layer and the second planar layer pattern may include first depositing a fifth insulating thin film on the base on which the above-mentioned pattern is formed, patterning the fifth insulating thin film by a patterning process, then applying a second planar thin film, then depositing a sixth insulating thin film, and patterning the fifth insulating thin film, the second planar thin film, and the sixth insulating thin film by a patterning process to form a fifth insulating layer covering the fourth conductive layer pattern, a second planar layer disposed on a side of the fifth insulating layer away from the base, and a sixth insulating layer disposed on a side of the second planar layer away from the base, and forming a plurality of binding vias in the fifth insulating layer, the second planar layer, and the sixth insulating layer.

[0296] In the exemplary embodiment, the plurality of binding vias in each circuit unit includes a first binding via K1 and a second binding via K2.

[0297] In an exemplary embodiment, the first binding via K1 may have a rectangular shape, and the orthogonal projection of the base of the first binding via K1 is within the range of the orthogonal projection of the base of the anode connecting electrode 13. The sixth insulating thin film, the second planar thin film, and the fifth insulating thin film in the first binding via K1 are removed to expose the surface of the anode connecting electrode 13. The area of ​​the anode connecting electrode 13 exposed by the first binding via K1 may be an anode pad. The first binding via K1 is configured to bind-connect a first electrode of the light-emitting diode to the anode connecting electrode 13 through the binding via.

[0298] In an exemplary embodiment, the second binding via K2 may have a rectangular shape, and the orthogonal projection of the base of the second binding via K2 is within the range of the orthogonal projection of the base of the low-voltage power line VSS. The sixth insulating thin film, the second planar thin film, and the fifth insulating thin film in the second binding via K2 are removed to expose the surface of the low-voltage power line VSS. The area of ​​the low-voltage power line VSS exposed by the second binding via K2 may be a cathode pad. The second binding via K2 is configured to connect the second electrode of the light-emitting diode to the low-voltage power line VSS through the binding via.

[0299] Thus, the driving circuit layer of this exemplary embodiment is fabricated and completed. In a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units, each of which may include a pixel driving circuit, a first scanning signal line, a second scanning signal line, a light-emitting signal line, a data signal line, a duration signal line, an initial signal line, a high-frequency signal line, and a high-voltage power line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include at least a first conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a first planar layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, and a second planar layer, which are sequentially disposed on a base.

[0300] In exemplary embodiments, the base may be a flexible base or a rigid base. The rigid base may include, but is not limited to, one or more of glass and quartz. The flexible base may include, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyaryl ester, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0301] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer may be made of a metal material, such as one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may have a single layer, multi-layer, or composite structure. The first planar layer and the second planar layer may be made of an organic material, such as a resin. The semiconductor layer may be made of one or more materials, such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, polythiophene, etc. That is, the present disclosure is applicable to transistors fabricated based on oxide technology, silicon technology, and organic technology. For example, the material of the semiconductor layer may be polycrystalline silicon (p-Si).

[0302] In an exemplary embodiment, the subsequent manufacturing flow may include first using a dispenser to add a binding material (e.g., solder paste) to the plurality of first binding vias and the plurality of second binding vias, and then using a transfer die bonding process to bind-connect first electrodes of the plurality of light-emitting diodes to anode connecting electrodes through the first binding vias and bind-connect second electrodes of the plurality of light-emitting diodes to low-voltage power supply lines through the second binding vias, thereby completing the connection between the light-emitting diodes and corresponding pixel driving circuits. Then, a cover thin film is applied to the base on which the above structure is formed to form a cover layer, and the cover layer covers the plurality of light-emitting diodes. In an exemplary embodiment, the plurality of light-emitting diodes and the cover layer may constitute a light-emitting structure layer.

[0303] As can be seen from the structure and manufacturing process of the display substrate described above, the display substrate according to the exemplary embodiment of the present disclosure can better accommodate the differences in light emission efficiency and yield rate of red, blue, and green LEDs by making the width-to-length ratio of the third transistor in the first circuit unit greater than the width-to-length ratios of the third transistors in the second and third circuit units, and can not only meet the current value required for the red LED, but also achieve more gray scales, thereby avoiding defects such as insufficient brightness or inability to achieve more gray scales in conventional structures.

[0304] In the present disclosure, increasing the capacitance value of the storage capacitor in the first circuit unit can effectively reduce the jump in the gate voltage of the third transistor and ensure accurate gate voltage writing. Research has shown that when the width-to-length ratios of the third transistors in different circuit units are different, the parasitic capacitance of the third transistor (e.g., the gate-source capacitor Cgs and the gate-drain capacitor Cgd) also increases with the increase in the width-to-length ratio. This causes the gate voltage of the third transistor to jump when the capacitor couples with the gate electrode to turn off and when the light-emitting signal line turns on, affecting the accuracy of gate voltage writing. Because the jump in the gate voltage is inversely proportional to the capacitance value of the storage capacitor, increasing the capacitance value of the storage capacitor can effectively reduce the jump in the gate voltage of the third transistor.

[0305] In the present disclosure, the first capacitor, the second capacitor, and the storage capacitor are connected in parallel, thereby ensuring capacitance while minimizing the space occupied by the first capacitor, the second capacitor, and the storage capacitor, which is advantageous for achieving high-resolution displays. In the present disclosure, the high-voltage power line and the low-voltage power line are formed in a network-connected structure, which minimizes the resistance of the power transmission line and reduces power supply voltage drops, effectively improving power supply voltage uniformity on the display substrate, effectively improving uniformity within the signal plane, effectively improving display uniformity, and improving display attributes and display quality. The manufacturing process of the present disclosure is highly compatible with conventional manufacturing processes, is simple to implement, easy to implement, has high production efficiency, low production costs, and a high yield rate.

[0306] FIG. 16 is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure, showing an 11T3C pixel driving circuit structure. In an exemplary embodiment, the pixel driving circuit according to this exemplary embodiment may include at least a current control sub-circuit DK and a time length control sub-circuit SK. The current control sub-circuit DK may include at least a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cs, and the time length control sub-circuit SK may include at least an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a first capacitor C1, and a second capacitor C2. Unlike the pixel driving circuit shown in FIG. 3, in this embodiment, the twelfth transistor T12 is not grounded, and the time length control sub-circuit SK is connected to the gate electrode of the sixth transistor T6.

[0307] In the exemplary embodiment, the first node N1 in this embodiment is respectively connected to the gate electrode of the sixth transistor T6, the second electrode of the ninth transistor T9, and the second electrode of the eleventh transistor T11, the second node N2 is respectively connected to the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7, and the anode of the light-emitting diode EL, and the other nodes are substantially the same as the structure shown in FIG. 3.

[0308] In the exemplary embodiment, the gate electrode of the sixth transistor T6 is connected to the first node N1, the first electrode of the sixth transistor T6 is connected to the fourth node N4, and the second electrode of the sixth transistor T6 is connected to the second node N2. The connections of the first to fifth transistors T1 to T5, the seventh transistor T7, the eleventh transistor T11, the first capacitor C1, the second capacitor C2, and the storage capacitor Cs are substantially the same as those in the structure shown in FIG. 3, and will not be described again here.

[0309] 17 is a structural schematic diagram of another display substrate according to an exemplary embodiment of the present disclosure, showing the structure of three circuit units, each including the pixel driving circuit shown in FIG. 16. As shown in FIG. 17, the plurality of circuit units may include at least a first circuit unit Q1, a blank unit KB, a second circuit unit Q2, and a third circuit unit Q3 arranged in sequence along a first direction X. The blank unit KB has light-emitting diodes (LEDs) installed therein and is configured to transmit light, and no pixel driving circuit is installed within the blank unit KB. The first pixel driving circuit in the first circuit unit Q1 is configured to be connected to the first LED, the second pixel driving circuit in the second circuit unit Q2 is configured to be connected to the second LED, and the third pixel driving circuit in the third circuit unit Q3 is configured to be connected to the third LED. The first LED may be a red LED, the second LED may be a green LED, and the third LED may be a blue LED.

[0310] In an exemplary embodiment, the first pixel driving circuit in the first circuit unit Q1 may include at least a first driving transistor DTFT1 and a first storage capacitor Cs1, the second pixel driving circuit in the second circuit unit Q2 may include at least a second driving transistor DTFT2 and a second storage capacitor Cs2, and the third pixel driving circuit in the third circuit unit Q3 may include at least a third driving transistor DTFT3 and a third storage capacitor Cs3. The width-to-length ratio (W / L) of the first driving transistor DTFT1 may be greater than the width-to-length ratios of the second driving transistor DTFT2 and the third driving transistor DTFT3, and the capacitance value of the first storage capacitor Cs1 may be greater than the capacitance values ​​of the second storage capacitor Cs2 and the third storage capacitor Cs3.

[0311] In an exemplary embodiment, at least one circuit unit may include a high-frequency connecting line Hf-C extending along a first direction X and a high-frequency signal line Hf extending along a second direction Y, and the high-frequency signal line Hf may be connected to the high-frequency connecting line Hf-C through a via to form a net-like communication structure for transmitting high-frequency signals.

[0312] In an exemplary embodiment, at least one circuit unit may include a high-voltage connecting line VDD-C extending along a first direction X and a high-voltage power supply line VDD extending along a second direction Y, where the high-voltage connecting line VDD is connected to a corresponding pixel driving circuit, and the high-voltage power supply line VDD is connected to the high-voltage connecting line VDD-C through a via, forming a net-like communication structure for transmitting a high-voltage power supply signal.

[0313] In an exemplary embodiment, the low-voltage connection lines may include at least a first low-voltage connection line VSS-C1 and a second low-voltage connection line VSS-C2, and the low-voltage power supply lines may include at least a first low-voltage power supply line VSS1 and a second low-voltage power supply line VSS2.

[0314] In an exemplary embodiment, at least one circuit unit may include a first low-voltage connecting line VSS-C1 extending along a first direction X and a first low-voltage power supply line VSS1 extending along a second direction Y, where the first low-voltage power supply line VSS1 is connected to the first light-emitting diode, and the first low-voltage power supply line VSS1 is connected to the first low-voltage connecting line VSS-C1 through a via, forming a net-like communication structure for transmitting a first low-voltage power supply signal.

[0315] In an exemplary embodiment, at least one circuit unit may include a second low-voltage connecting line VSS-C2 extending along the first direction X and a second low-voltage power supply line VSS2 extending along the second direction Y, where the second low-voltage power supply line VSS2 is connected to the second light-emitting diode and the third light-emitting diode, and the second low-voltage power supply line VSS2 is connected to the second low-voltage connecting line VSS-C2 through a via, forming a net-like communication structure for transmitting a second low-voltage power supply signal.

[0316] 18A is a structural schematic diagram of another first drive transistor of the present disclosure, and FIG. 18B is a structural schematic diagram of another second drive transistor of the present disclosure. As shown in FIG. 18A and FIG. 18B, the first drive transistor DTFT1 and the second drive transistor DTFT2 may each include an active layer Active, a gate electrode Gate, a first electrode Source, and a second electrode Drain, where the first drive transistor DTFT1 has a first width-to-length ratio, and the second drive transistor DTFT2 has a second width-to-length ratio, and the first width-to-length ratio may be greater than the second width-to-length ratio.

[0317] In an exemplary embodiment, the gate electrode Gate, the first electrode Source, and the second electrode Drain are all elongated and extend along a first direction X, the active layers Active are all elongated and extend along a second direction Y, the first drive transistor DTFT1 has a first channel length L1 and a first channel width W1, and the second drive transistor DTFT2 has a second channel length L2 and a second channel width W2, and the first channel length L1 and the second channel length L2 may be approximately the same, and the first channel width W1 may be larger than the second channel width W2.

[0318] In an exemplary embodiment, the ratio value between the first channel width W1 and the second channel width W2 may be approximately three.

[0319] In an exemplary embodiment, the shapes and sizes of the gate electrode Gate, the first electrode Source, and the second electrode Drain of the first drive transistor DTFT1 and the second drive transistor DTFT2 may be approximately the same, and the width of the active layer Active of the first drive transistor DTFT1 may be larger than the width of the active layer Active of the second drive transistor DTFT2, and the width may be the size of the active layer Active in the first direction X.

[0320] In an exemplary embodiment, the second channel width of the second drive transistor DTFT2 and the third channel width of the third drive transistor DTFT3 may be approximately the same, and the second channel length of the second drive transistor DTFT2 and the third channel length of the third drive transistor DTFT3 may be approximately the same.

[0321] 19A is a structural schematic diagram of another first storage capacitor of the present disclosure, and FIG. 19B is a structural schematic diagram of another second storage capacitor of the present disclosure. As shown in FIG. 19A and FIG. 19B, the first storage capacitor Cs1 has a first area, and the second storage capacitor Cs2 has a second area, and the first area may be larger than the second area.

[0322] In an exemplary embodiment, the first length M1 of the first storage capacitor Cs1 and the first length M1 of the second storage capacitor Cs2 may be approximately the same, and the second length M2 of the first storage capacitor Cs1 may be greater than the second length M2 of the second storage capacitor Cs2. In an exemplary embodiment, the ratio value of the second length M2 of the first storage capacitor Cs1 to the second length M2 of the second storage capacitor Cs2 may be approximately 1.8. In an exemplary embodiment, the first length M1 of the second storage capacitor Cs2 and the first length M1 of the third storage capacitor Cs3 may be approximately the same, and the second length M2 of the second storage capacitor Cs2 and the second length M2 of the third storage capacitor Cs3 may be approximately the same.

[0323] In an exemplary embodiment, the manufacturing process of the driving circuit layer of this example may include the following operations.

[0324] (21) Forming a first conductive layer pattern. In an exemplary embodiment, as shown in Figure 20, forming the first conductive layer pattern may include depositing a first conductive thin film on the base on which the above-mentioned pattern has been formed, and patterning the first conductive thin film by a patterning process to form a first conductive layer pattern disposed on the base.

[0325] In an exemplary embodiment, the first conductive layer pattern of each circuit unit may include at least a first electrode plate CF1, a second electrode plate CF2, a third electrode plate CF3, and a third bottom gate electrode Gate3-B.

[0326] In an exemplary embodiment, the first plate CF1, the second plate CF2, and the third plate CF3 may have a rectangular shape, and the corners of the rectangle may be chamfered, the first plate CF1 and the second plate CF2 may be disposed on opposite sides of the circuit unit in the second direction Y, the third bottom gate electrode Gate3-B may be disposed on the second direction Y side of the circuit unit, and the third plate CF3 may be located between the first plate CF1 and the third bottom gate electrode Gate3-B.

[0327] In an exemplary embodiment, the area of ​​the third plate CF3 in the first circuit unit Q1 may be larger than the area of ​​the third plate CF3 in the second circuit unit Q2, the area of ​​the third plate CF3 in the first circuit unit Q1 may be larger than the area of ​​the third plate CF3 in the third circuit unit Q3, and the position, shape and size of the third plate CF3 in the second circuit unit Q2 and the third circuit unit Q3 may be approximately the same.

[0328] In an exemplary embodiment, the first lengths M1 of the third plate CF3 in the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be approximately the same, and the second length M2 of the third plate CF3 in the first circuit unit Q1 may be greater than the second length M2 of the third plate CF3 in the second circuit unit Q2 and the third circuit unit Q3, so that the area of ​​the third plate CF3 in the first circuit unit Q1 is greater than the area of ​​the third plate CF3 in the second circuit unit Q2 and the third circuit unit Q3.

[0329] In an exemplary embodiment, the ratio between the second length M2 of the third electrode plate CF3 in the first circuit unit Q1 and the second length M2 of the third electrode plate CF3 in the second circuit unit Q2 and the third circuit unit Q3 may be about 1 to 2. For example, the ratio may be about 1.8.

[0330] In an exemplary embodiment, the shape of the third bottom gate electrode Gate3-B may be L-shaped, and the shapes of the third bottom gate electrodes Gate3-B in the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be approximately the same.

[0331] In an exemplary embodiment, the third plates CF3 in one unit row may be connected to each other by plate electrode connecting lines, and multiple third plates CF3 and multiple plate electrode connecting lines in one unit row may be an integrated structure connected to each other.

[0332] (22) Forming a semiconductor layer pattern. In an exemplary embodiment, as shown in Figures 21A and 21B, forming the semiconductor layer pattern may include sequentially depositing a first insulating thin film and a first semiconductor thin film on a base, and patterning the first semiconductor thin film by a patterning process to form a first insulating layer covering the first conductive layer and a semiconductor layer pattern disposed on the first insulating layer. Figure 21B is a schematic plan view of the semiconductor layer of Figure 21A.

[0333] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit may include at least the first active layer AT1 of the first transistor T1 to the eleventh active layer AT11 of the eleventh transistor T11.

[0334] In an exemplary embodiment, the first active layer AT1, the second active layer AT2, the fourth active layer AT4, the seventh active layer AT7, the eighth active layer AT8, the ninth active layer AT9, and the tenth active layer AT10 may have an elongated shape extending along the first direction X, the third active layer AT3 and the eleventh active layer AT11 may have a rectangular shape, and the fifth active layer AT5 and the sixth active layer AT6 may have an elongated shape extending along the second direction Y.

[0335] In an exemplary embodiment, the first active layer AT1 and the seventh to eleventh active layers AT7 to AT118 may be located between the first electrode plate CF1 and the third electrode plate CF3. The eighth active layer AT8 may be located on the second direction Y side of the first electrode plate CF1, the tenth active layer AT10 may be located on the second direction Y side of the eighth active layer AT8, the eleventh active layer AT11 may be located on the second direction Y side of the tenth active layer AT10, the first active layer AT1 and the seventh active layer AT7 may be located on the first direction X side of the tenth active layer AT10, the first active layer AT1 and the seventh active layer AT7 may be an integrated structure connected to each other, and the ninth active layer AT9 may be located on the first direction X side of the eleventh active layer AT11.

[0336] In an exemplary embodiment, the second active layer AT2 to the sixth active layer AT6 may be located on the second direction Y side of the third electrode plate CF3, the orthogonal projection of the third active layer AT3 at the base at least partially overlaps with the orthogonal projection of the third bottom gate electrode Gate3-B at the base, the second active layer AT2 may be located on the first direction X side of the third active layer AT3, the fourth active layer AT4 may be located on the opposite side of the third active layer AT3 in the first direction X, the fifth active layer AT5 and the sixth active layer AT6 may be located between the third electrode plate CF3 and the third active layer AT3, and the sixth active layer AT6 may be located on the first direction X side of the fifth active layer AT5.

[0337] In an exemplary embodiment, the width of the third active layer AT3 in the first circuit unit Q1 may be larger than the width of the third active layer AT3 in the second circuit unit Q2 and the third circuit unit Q3, and the width may be the size of the third active layer AT3 in the first direction X, so that the width-to-length ratio of the driving transistor in the first circuit unit Q1 is larger than the width-to-length ratio of the driving transistor in the second circuit unit Q2 and the third circuit unit Q3.

[0338] (23) Forming a second conductive layer pattern. In an exemplary embodiment, as shown in Figures 22A and 22B, forming the second conductive layer pattern may include sequentially depositing a second insulating thin film and a second conductive thin film on the base on which the above-mentioned pattern is formed, and patterning the second conductive thin film by a patterning process to form a second insulating layer covering the semiconductor layer and a second conductive layer pattern disposed on the second insulating layer. Figure 22B is a schematic plan view of the second conductive layer in Figure 22A.

[0339] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least a fourth electrode plate CF4, a fifth electrode plate CF5, a sixth electrode plate CF6, a first scanning signal line S1, a second scanning signal line S2, a light emitting signal line EM, a first control line CT1, an initial signal line Vint, a high frequency connecting line Hf-C, a high voltage connecting line VDD-C, a first low voltage connecting line VSS-C1, a second low voltage connecting line VSS-C2, a plurality of gate electrodes and a plurality of connecting electrodes.

[0340] In an exemplary embodiment, the fourth plate CF4, the fifth plate CF5, and the sixth plate CF6 may have a rectangular shape with a notch at one corner. The orthogonal projection of the fourth plate CF4 at the base at least partially overlaps with the orthogonal projection of the first plate CF1 at the base, and the fourth plate CF4 may be the other plate of a first capacitor, and the first plate CF1 and the fourth plate CF4 form one first capacitor of the pixel driving circuit. The orthogonal projection of the fifth plate CF5 at the base at least partially overlaps with the orthogonal projection of the second plate CF2 at the base, and the fifth plate CF5 may be the other plate of a second capacitor, and the second plate CF2 and the fifth plate CF5 form one second capacitor of the pixel driving circuit. The orthogonal projection at the base of the sixth plate CF6 at least partially overlaps with the orthogonal projection at the base of the third plate CF3, and the sixth plate CF6 may be the other plate of a storage capacitor, and the third plate CF3 and the sixth plate CF6 constitute one storage capacitor of the pixel driving circuit.

[0341] In an exemplary embodiment, the position, shape and size of the sixth plate CF6 in the second circuit unit Q2 and the third circuit unit Q3 may be approximately the same, the area of ​​the sixth plate CF6 in the first circuit unit Q1 may be larger than the area of ​​the sixth plate CF6 in the second circuit unit Q2, and the area of ​​the sixth plate CF6 in the first circuit unit Q1 may be larger than the area of ​​the sixth plate CF6 in the third circuit unit Q3, so that the capacitance value of the storage capacitor in the first circuit unit Q1 is larger than the capacitance values ​​of the storage capacitors in the second circuit unit Q2 and the third circuit unit Q3.

[0342] In an exemplary embodiment, the first lengths M1 of the sixth plate CF6 in the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be approximately the same, and the second length M2 of the sixth plate CF6 in the first circuit unit Q1 may be greater than the second length M2 of the sixth plate CF6 in the second circuit unit Q2 and the third circuit unit Q3, so that the area of ​​the sixth plate CF6 in the first circuit unit Q1 is greater than the area of ​​the sixth plate CF6 in the second circuit unit Q2 and the third circuit unit Q3.

[0343] In an exemplary embodiment, the ratio between the second length M2 of the sixth electrode plate CF6 in the first circuit unit Q1 and the second length M2 of the sixth electrode plate CF6 in the second circuit unit Q2 and the third circuit unit Q3 may be about 1 to 2. For example, the ratio may be about 1.8.

[0344] In an exemplary embodiment, the first scanning signal line S1, the second scanning signal line S2, the emission signal line EM, the first control line CT1, the initial signal line Vint, the high-frequency connecting line Hf-C, the high-voltage connecting line VDD-C, the first low-voltage connecting line VSS-C1, and the second low-voltage connecting line VSS-C may have a linear or polygonal shape with main bodies extending along the first direction X. The first scanning signal line S1 may be located on the side of the sixth plate CF6 in the second direction Y, the high-frequency connecting line Hf-C, the first low-voltage connecting line VSS-C1, and the second low-voltage connecting line VSS-C may be located on the opposite side of the fourth plate CF4 and the fifth plate CF5 in the second direction Y, and the second scanning signal line S2, the emission signal line EM, the first control line CT1, the initial signal line Vint, and the high-voltage connecting line VDD-C may be located between the fourth plate CF4 and the sixth plate CF6.

[0345] In an exemplary embodiment, the first low-voltage connecting wire VSS-C1 may be located on the opposite side of the fourth plate CF4 and the fifth plate CF5 in the second direction Y, the second low-voltage connecting wire VSS-C may be located on the side of the first low-voltage connecting wire VSS-C1 away from the fourth plate CF4 and the fifth plate CF5, and the high-frequency connecting wire Hf-C may be located on the side of the second low-voltage connecting wire VSS-C away from the fourth plate CF4 and the fifth plate CF5.

[0346] In an exemplary embodiment, the high-voltage connecting line VDD-C is configured to be connected to a subsequently formed high-voltage power supply line to form a net-like interconnection structure, the first low-voltage connecting line VSS-C1 is configured to be connected to a subsequently formed first low-voltage power supply line to form a net-like interconnection structure, the second low-voltage connecting line VSS-C2 is configured to be connected to a subsequently formed second low-voltage power supply line to form a net-like interconnection structure, and the high-frequency connecting line Hf-C is configured to be connected to a subsequently formed high-frequency signal line to form a net-like interconnection structure.

[0347] In an exemplary embodiment, the initial signal line Vint may be located on the second direction Y side of the fourth electrode plate CF4 and the fifth electrode plate CF5, the first control line CT1 may be located on the second direction Y side of the initial signal line Vint, the second scanning signal line S2 may be located on the second direction Y side of the first control line CT1, the high voltage connecting line VDD-C may be located on the second direction Y side of the second scanning signal line S2, and the light emitting signal line EM may be located on the second direction Y side of the high voltage connecting line VDD-C.

[0348] In an exemplary embodiment, the second scan signal line S2 may also be used as a second control line to control the turning on and off of the tenth transistor T10.

[0349] In an exemplary embodiment, the multiple gate electrodes of each circuit unit may include at least a first gate electrode Gate1, a second gate electrode Gate2, a third top gate electrode Gate3-T, a fourth gate electrode Gate4, a fifth gate electrode Gate5, a sixth gate electrode Gate6, a seventh gate electrode Gate7, an eighth gate electrode Gate8, a ninth gate electrode Gate9, a tenth gate electrode Gate10, and an eleventh gate electrode Gate11.

[0350] In an exemplary embodiment, the second gate electrode Gate2 and the fourth gate electrode Gate4 may be disposed on a side of the first scanning signal line S1 closer to the sixth electrode plate CF6. The second gate electrode Gate2 is the gate electrode of the second transistor T2, and the orthogonal projection of the second gate electrode Gate2 at the base at least partially overlaps with the orthogonal projection of the base of the second active layer. The fourth gate electrode Gate4 is the gate electrode of the fourth transistor T4, and the orthogonal projection of the fourth gate electrode Gate4 at the base at least partially overlaps with the orthogonal projection of the base of the fourth active layer. In an exemplary embodiment, the first scanning signal line S1, the second gate electrode Gate2, and the fourth gate electrode Gate4 may be an integrated structure connected to each other.

[0351] In an exemplary embodiment, the first gate electrode Gate1, the seventh gate electrode Gate7, and the tenth gate electrode Gate10 may be disposed on a side of the second scanning signal line S2 away from the initial signal line Vint. The first gate electrode Gate1 is the gate electrode of the first transistor T1, and an orthogonal projection of the first gate electrode Gate1 at a base at least partially overlaps with an orthogonal projection of the base of the first active layer. The seventh gate electrode Gate7 is the gate electrode of the seventh transistor T7, and an orthogonal projection of the seventh gate electrode Gate7 at a base at least partially overlaps with an orthogonal projection of the base of the seventh active layer. The tenth gate electrode Gate10 is the gate electrode of the tenth transistor T10, and an orthogonal projection of the tenth gate electrode Gate10 at a base at least partially overlaps with an orthogonal projection of the base of the tenth active layer. In an exemplary embodiment, the second scanning signal line S2, the first gate electrode Gate1, the seventh gate electrode Gate7, and the tenth gate electrode Gate10 may be an integrated structure connected to each other.

[0352] In an exemplary embodiment, the eighth gate electrode Gate8 may be disposed on a side of the first control line CT1 closer to the initial signal line Vint. The eighth gate electrode Gate8 is the gate electrode of the eighth transistor T8, and the orthogonal projection of the base of the eighth gate electrode Gate8 at least partially overlaps with the orthogonal projection of the base of the eighth active layer. In an exemplary embodiment, the first control line CT1 and the eighth gate electrode Gate8 may be an integrated structure connected to each other.

[0353] In an exemplary embodiment, the third top gate electrode Gate3-T may be the top gate electrode of the third transistor T3, wherein the orthogonal projection of the third top gate electrode Gate3-T at the base at least partially overlaps with the orthogonal projection of the third top gate electrode Gate3-T at the base of the third active layer, and the orthogonal projection of the third top gate electrode Gate3-T at the base at least partially overlaps with the orthogonal projection of the third bottom gate electrode Gate3-B at the base.

[0354] In an exemplary embodiment, a third gate electrode block 103 is provided on a side of the third top gate electrode Gate3-T closer to the sixth plate CF6, and the third gate electrode block 103 may have a polygonal line shape extending along the second direction Y, with a first end of the third gate electrode block 103 connected to the third top gate electrode Gate3-T and a second end of the third gate electrode block 103 connected to the sixth plate CF6. In an exemplary embodiment, the third top gate electrode Gate3-T, the sixth plate CF6, and the third gate electrode block 103 may have an integrated structure in which they are connected to each other.

[0355] In an exemplary embodiment, the fifth gate electrode Gate5 may be the gate electrode of the fifth transistor T5, and the orthogonal projection of the fifth gate electrode Gate5 at the base at least partially overlaps with the orthogonal projection of the base of the fifth active layer. The fifth gate electrode Gate5 may be located between the emission signal line EM and the third top gate electrode Gate3-T, and may be located on the opposite side of the third gate electrode block 103 in the first direction X, and may have a comb-like shape.

[0356] In an exemplary embodiment, a fifth gate electrode block 105 is provided on a side of the fifth gate electrode Gate5 that is closer to the light-emitting signal line EM, and the fifth gate electrode block 105 may have an elongated shape extending along the second direction Y. A first end of the fifth gate electrode block 105 is connected to the fifth gate electrode Gate5, and a second end of the fifth gate electrode block 105 is connected to the light-emitting signal line EM, so that the light-emitting signal line EM can control the turning on or off of the fifth transistor T5. In an exemplary embodiment, the light-emitting signal line EM, the fifth gate electrode Gate5, and the fifth gate electrode block 105 may be an integrated structure that is connected to each other.

[0357] In an exemplary embodiment, the sixth gate electrode Gate6 may be the gate electrode of the sixth transistor T6, and the orthogonal projection of the sixth gate electrode Gate6 at the base at least partially overlaps with the orthogonal projection of the base of the sixth active layer. The sixth gate electrode Gate6 may be located between the emission signal line EM and the third top gate electrode Gate3-T, and may be located on the first direction X side of the third gate electrode block 103, and may have a comb shape.

[0358] In an exemplary embodiment, a sixth gate electrode block 106 is provided on the side of the sixth gate electrode Gate6 that is closer to the light-emitting signal line EM, and the sixth gate electrode block 106 may have an elongated shape extending along the second direction Y, with a first end of the sixth gate electrode block 106 connected to the sixth gate electrode Gate6 and a second end of the sixth gate electrode block 106 that is closer to the light-emitting signal line EM, and the sixth gate electrode block 106 configured to be connected to a subsequently formed 62nd connecting electrode.

[0359] In an exemplary embodiment, the ninth gate electrode Gate9 may be the gate electrode of the ninth transistor T9, and the orthogonal projection of the ninth gate electrode Gate9 at the base at least partially overlaps with the orthogonal projection of the base of the ninth active layer. The ninth gate electrode Gate9 may be located between the second scanning signal line S2 and the high-voltage connecting line VDD-C, and the shape of the ninth gate electrode Gate9 may be elongated and extend along the second direction Y.

[0360] In an exemplary embodiment, the eleventh gate electrode Gate11 may be the gate electrode of the eleventh transistor T11, and the orthogonal projection of the base of the eleventh gate electrode Gate11 at least partially overlaps with the orthogonal projection of the base of the eleventh active layer. The eleventh gate electrode Gate11 may be located between the second scanning signal line S2 and the high-voltage connecting line VDD-C, and may have a polygonal line shape extending along the second direction Y.

[0361] In the exemplary embodiment, the plurality of connection electrodes of each circuit unit includes at least a 41st connection electrode CO41, a 42nd connection electrode CO42, a 43rd connection electrode CO43, a 44th connection electrode CO44, and a 45th connection electrode CO45.

[0362] In an exemplary embodiment, the 41st connecting electrode CO41 may have an elongated shape extending along the first direction X, and may be disposed between the second scanning signal line S2 and the high-voltage connecting line VDD-C, and is configured to be connected to a subsequently formed high-frequency signal line and the 63rd connecting electrode.

[0363] In an exemplary embodiment, the 42nd connecting electrode CO42 may have a linear shape extending along the first direction X, and may be disposed between the second scanning signal line S2 and the high-voltage connecting line VDD-C, and is configured to be connected to the 61st connecting electrode and the 62nd connecting electrode that will be subsequently formed.

[0364] In an exemplary embodiment, the 43rd connecting electrode CO43 may have a linear shape extending along the first direction X, and may be located on the side away from the fourth electrode plate CF4 and the fifth electrode plate CF5 of the high-frequency connecting line Hf-C, and the 43rd connecting electrode CO43 is configured to be connected to the anode connecting block 12 of the subsequently formed second circuit unit Q2 and the 52nd connecting electrode of the second circuit unit Q2.

[0365] In an exemplary embodiment, the shape of the 44th connecting electrode CO44 may be a line extending along the first direction X, and the 44th connecting electrode CO44 may be located on the side of the 43rd connecting electrode CO43 away from the high-frequency connecting line Hf-C, and the 44th connecting electrode CO44 is configured to be connected to the anode connecting block 12 of the third circuit unit Q3 to be formed subsequently and the 52nd connecting electrode of the third circuit unit Q3.

[0366] In an exemplary embodiment, the 45th connecting electrode CO45 may have a rectangular shape, may be located on the opposite side of the 42nd connecting electrode CO42 in the second direction Y, and is configured to be connected to the 64th connecting electrode formed subsequently.

[0367] In an exemplary embodiment, after forming the second conductive layer pattern, the semiconductor layer can be made conductive by using the second conductive layer as a shield. The semiconductor layer in the region blocked by the second conductive layer forms the channel regions of the first transistor T1 through the twelfth transistor T12. The semiconductor layer in the region not blocked by the first conductive layer is made conductive, i.e., both the first region and the second region of the first transistor T1 through the eleventh transistor T11 are made conductive.

[0368] (24) Forming a third insulating layer pattern. In an exemplary embodiment, as shown in FIG. 23 , forming the third insulating layer pattern may include depositing a third insulating thin film on the base on which the above-mentioned pattern is formed, and patterning the third insulating thin film through a patterning process to form a third insulating layer covering the second conductive layer, and a plurality of vias are provided in the third insulating layer.

[0369] In the exemplary embodiment, the plurality of vias in the third insulating layer in each circuit unit includes at least the 11th via V11 to the 24th via V24, the 27th via V27 to the 34th via V34, and the 77th via V77 to the 99th via V99.

[0370] In the exemplary embodiment, the structures of the eleventh via V11 to the twenty-fourth via V24 and the twenty-seventh via V27 to the thirty-fourth via V34 are substantially the same as those in the above-described embodiment, and the eleventh via V11 and the twenty-third via V23 are common vias.

[0371] In the exemplary embodiment, the orthogonal projections of the bases of the 77th via V77 and the 78th via V78 are within the range of the orthogonal projections of the base of the 11th gate electrode Gate11. The third insulating layer in the 77th via V77 and the 78th via V78 is etched to expose the surface of the 11th gate electrode Gate11. The 77th via V77 and the 78th via V78 are configured to connect the 59th and 60th connection electrodes, which will be subsequently formed, to the 11th gate electrode Gate11, respectively, through the vias.

[0372] In the exemplary embodiment, the orthogonal projections of the 79th via V79 and the 80th via V80 at their bases are within the range of the orthogonal projections of the 42nd connection electrode CO42 at their bases. The third insulating layer in the 79th via V79 and the 80th via V80 is etched to expose the surfaces of the first and second ends of the 42nd connection electrode CO42, respectively. The 79th via V79 and the 80th via V80 are configured to connect the subsequently formed 61st and 62nd connection electrodes to the 42nd connection electrode CO42, respectively, through the vias.

[0373] In the exemplary embodiment, the orthogonal projection of the base of the via V81 is within the range of the orthogonal projection of the base of the light emission signal line EM. The third insulating layer in the via V81 is etched to expose the surface of the light emission signal line EM. The via V81 is configured to connect the subsequently formed 64th connection electrode to the light emission signal line EM through the via.

[0374] In an exemplary embodiment, the orthogonal projections of the bases of the 82nd via V82, the 83rd via V83, and the 84th via V84 are each within the range of the orthogonal projection of the base of the initial signal line Vint. The third insulating layer in the 82nd via V82, the 83rd via V83, and the 84th via V84 is etched to expose the surface of the initial signal line Vint. The 82nd via V82, the 83rd via V83, and the 84th via V84 are configured to connect the seventh electrode plate, the eighth electrode plate, and the 51st connection electrode, which will be subsequently formed, to the initial signal line Vint, respectively, through the vias.

[0375] In an exemplary embodiment, the orthogonal projection of the base of the 85th via V85 is within the range of the orthogonal projection of the base of the high-frequency connecting line Hf-C. The third insulating layer in the 85th via V85 is etched to expose the surface of the high-frequency connecting line Hf-C. The 85th via V85 is configured to connect a subsequently formed high-frequency signal line to the high-frequency connecting line Hf-C through the via.

[0376] In an exemplary embodiment, the orthogonal projection of the base of the 86th via V86 is within the range of the orthogonal projection of the base of the high-voltage connection line VDD-C. The third insulating layer in the 86th via V86 is etched to expose the surface of the high-voltage connection line VDD-C. The 86th via V86 is configured to connect a subsequently formed ninth plate to the high-voltage connection line VDD-C through the via.

[0377] In the exemplary embodiment, the orthogonal projection of the base of the 87th via V87 is within the range of the orthogonal projection of the base of the first electrode plate CF1. The third insulating layer, the second insulating layer, and the first insulating layer within the 87th via V87 are etched to expose the surface of the first electrode plate CF1. The 87th via V87 is configured to connect a subsequently formed seventh electrode plate to the first electrode plate CF1 through the via.

[0378] In the exemplary embodiment, the orthogonal projection of the base of the via V88 is within the range of the orthogonal projection of the base of the second electrode plate CF2. The third insulating layer, the second insulating layer, and the first insulating layer within the via V88 are etched to expose the surface of the second electrode plate CF2. The via V88 is configured to connect a subsequently formed eighth electrode plate to the second electrode plate CF2 through the via.

[0379] In the exemplary embodiment, the orthogonal projection of the base of the 89th via V89 is within the range of the orthogonal projection of the base of the third plate CF3. The third insulating layer, the second insulating layer, and the first insulating layer within the 89th via V89 are etched to expose the surface of the third plate CF3. The 89th via V89 is configured to connect a subsequently formed ninth plate to the third plate CF3 through the via.

[0380] In the exemplary embodiment, the orthogonal projection of the base of the 90th via V90 is within the range of the orthogonal projection of the base of the fourth electrode plate CF4. The third insulating layer in the 90th via V90 is etched to expose the surface of the fourth electrode plate CF4. The 90th via V90 is configured to connect a subsequently formed 58th connection electrode to the fourth electrode plate CF4 through the via.

[0381] In the exemplary embodiment, the orthogonal projection of the base of the 91st via V91 is within the range of the orthogonal projection of the base of the fifth electrode plate CF5. The third insulating layer in the 91st via V91 is etched to expose the surface of the fifth electrode plate CF5. The 91st via V91 is configured to connect a subsequently formed 59th connection electrode to the fifth electrode plate CF5 through the via.

[0382] In the exemplary embodiment, the orthogonal projection of the base of the 92nd via V92 is within the range of the orthogonal projection of the base of the sixth electrode plate CF6. The third insulating layer in the 92nd via V92 is etched to expose the surface of the sixth electrode plate CF6. The 92nd via V92 is configured to connect a subsequently formed 57th connection electrode to the sixth electrode plate CF6 through the via.

[0383] In the exemplary embodiment, the orthogonal projection of the base of the via V93 is within the range of the orthogonal projection of the base of the first end of the connecting electrode CO41. The third insulating layer in the via V93 is etched to expose the surface of the first end of the connecting electrode CO41. The via V93 is configured to connect a subsequently formed high-frequency connecting line to the connecting electrode CO41 through the via.

[0384] In the exemplary embodiment, the orthogonal projection of the base of the 94th via V94 is within the range of the orthogonal projection of the base of the second end of the 41st connecting electrode CO41. The third insulating layer in the 94th via V94 is etched to expose the surface of the second end of the 41st connecting electrode CO41. The 94th via V94 is configured to connect a subsequently formed 63rd connecting electrode to the second end of the 41st connecting electrode CO41 through the via.

[0385] In the exemplary embodiment, the orthogonal projection of the base of the 95th via V95 is within the range of the orthogonal projection of the base of the third top gate electrode Gate3-T. The third insulating layer in the 95th via V95 is etched to expose the surface of the third top gate electrode Gate3-T. The 95th via V95 is configured to connect a subsequently formed 55th connection electrode to the third top gate electrode Gate3-T through the via.

[0386] In the exemplary embodiment, the orthogonal projection of the base of the 96th via V96 is within the range of the orthogonal projection of the base of the third bottom gate electrode Gate3-B. The third insulating layer, the second insulating layer, and the first insulating layer in the 96th via V96 are etched to expose the surface of the third bottom gate electrode Gate3-B. The 96th via V96 is configured to connect a subsequently formed 55th connecting electrode to the third bottom gate electrode Gate3-B through the via.

[0387] In the exemplary embodiment, the orthogonal projection of the 97th via V97 at the base is within the range of the orthogonal projection of the sixth gate electrode block 106 of the sixth gate electrode Gate6 at the base. The third insulating layer in the 97th via V97 is etched to expose the surface of the sixth gate electrode block 106. The 97th via V97 is configured to connect a subsequently formed 62nd connecting electrode to the sixth gate electrode Gate6 through the via.

[0388] In the exemplary embodiment, the orthogonal projection of the base of the 98th via V98 is within the range of the orthogonal projection of the base of the 9th gate electrode Gate 9. The third insulating layer in the 98th via V98 is etched to expose the surface of the 9th gate electrode Gate 9. The 98th via V98 is configured to connect a subsequently formed 58th connecting electrode to the 9th gate electrode Gate 9 through the via.

[0389] In the exemplary embodiment, the orthogonal projection of the base of the 99th via V99 is within the range of the orthogonal projection of the base of the 45th connection electrode CO45. The third insulating layer in the 99th via V99 is etched to expose the surface of the 45th connection electrode CO45. The 99th via V99 is configured to connect the subsequently formed 64th connection electrode to the 45th connection electrode CO45 through the via.

[0390] In an exemplary embodiment, the plurality of vias in the third insulating layer may further include a 101st via V101 to a 106th via V106.

[0391] In an exemplary embodiment, the via 101 V101 may be located in the second circuit unit Q2. The orthogonal projection of the base of the via 101 V101 is within the range of the orthogonal projection of the base of the first low-voltage connecting line VSS-C1. The third insulating layer in the via 101 V101 is etched to expose the surface of the first low-voltage connecting line VSS-C1. The via 101 V101 is configured to connect the subsequently formed connecting electrode 71 to the first low-voltage connecting line VSS-C1 through the via.

[0392] In an exemplary embodiment, the 102 via V102 may be disposed in the first circuit unit Q1. The orthogonal projection of the base of the 102 via V102 is within the range of the orthogonal projection of the base of the second low-voltage connecting line VSS-C2. The third insulating layer in the 102 via V102 is etched to expose the surface of the second low-voltage connecting line VSS-C2. The 102 via V102 is configured to connect a subsequently formed 72nd connecting electrode to the second low-voltage connecting line VSS-C2 through the via.

[0393] In the exemplary embodiment, the orthogonal projection of the base of the via V103 is within the range of the orthogonal projection of the base of the first end of the connecting electrode CO43. The third insulating layer in the via V103 is etched to expose the surface of the first end of the connecting electrode CO43. The via V103 is configured to connect the anode connecting block of the second circuit unit Q2, which will be subsequently formed, to the first end of the connecting electrode CO43.

[0394] In the exemplary embodiment, the orthogonal projection of the base of the via V104 is within the range of the orthogonal projection of the base of the second end of the connecting electrode CO43. The third insulating layer in the via V104 is etched to expose the surface of the second end of the connecting electrode CO43. The via V104 is configured to connect the connecting electrode 52 of the second circuit unit Q2 (to be subsequently formed) to the second end of the connecting electrode CO43 through the via.

[0395] In the exemplary embodiment, the orthogonal projection of the base of the 105 via V105 is within the range of the orthogonal projection of the base of the first end of the 44th connection electrode CO44. The third insulating layer in the 105 via V105 is etched to expose the surface of the first end of the 44th connection electrode CO44. The 105 via V105 is configured to connect the anode connection block of a subsequently formed third circuit unit Q3 to the first end of the 44th connection electrode CO44 through the via.

[0396] In the exemplary embodiment, the orthogonal projection of the base of the via V106 is within the range of the orthogonal projection of the base of the second end of the connecting electrode CO44. The third insulating layer in the via V106 is etched to expose the surface of the second end of the connecting electrode CO44. The via V106 is configured to connect the connecting electrode 52 of the third circuit unit Q3 (to be subsequently formed) to the second end of the connecting electrode CO44.

[0397] (25) Forming a third conductive layer pattern. In an exemplary embodiment, as shown in Figures 24A and 24B, forming the third conductive layer pattern may include depositing a third conductive thin film on the base on which the above-mentioned pattern is formed, and patterning the third conductive thin film by a patterning process to form a third conductive layer pattern disposed on the third insulating layer. Figure 24B is a schematic plan view of the third conductive layer in Figure 24A.

[0398] In an exemplary embodiment, the third conductive layer pattern of each circuit unit includes at least a data signal line DataI, a high-frequency signal line Hf, a seventh electrode plate CF7, an eighth electrode plate CF8, a ninth electrode plate CF9, an anode connection block 12, and a 51st connection electrode CO51 to a 64th connection electrode CO64.

[0399] In an exemplary embodiment, the data signal line DataI may have a linear shape with its main body extending along the second direction Y, and may be located on the opposite side of the circuit unit in the first direction X. The data signal line DataI is connected to the first region of the fourth active layer through the 17th via V17 on the one hand, the first region of the eighth active layer through the 27th via V27 on the other hand, and the first region of the tenth active layer through the 31st via V31 on the other hand, so that the data signal line DataI writes data signals to the first pole of the fourth transistor T4, the first pole of the eighth transistor T8, and the first pole of the tenth transistor T10, respectively.

[0400] In an exemplary embodiment, the data signal line DataI may also be used as a time-length signal line DataT. The data signal line DataI is used to provide a time-length signal to the first pole of the eighth transistor T8 and the first pole of the tenth transistor T10, respectively.

[0401] In an exemplary embodiment, the high-frequency signal line Hf may have a linear shape with its main body extending along the second direction Y, and may be located on the opposite side of the data signal line DataI in the first direction X. On the one hand, the high-frequency signal line Hf is connected to a first end of the connecting electrode CO41 through the via V93, and on the other hand, the high-frequency signal line Hf is connected to the high-frequency connecting line Hf-C through the via V85. This realizes connection between the high-frequency connecting line Hf-C extending along the first direction X and the high-frequency signal line Hf extending along the second direction Y, forming a net-like communication structure for transmitting high-frequency signals.

[0402] In an exemplary embodiment, the seventh plate CF7 may have a rectangular shape, and the orthogonal projection of the seventh plate CF7 at the base at least partially overlaps with the orthogonal projection of the fourth plate CF4 at the base. On the one hand, the seventh plate CF7 is connected to the first plate CF1 through the via V87, and on the other hand, the seventh plate CF7 is connected to the initial signal line Vint through the via V82. The seventh plate CF7 may be a further plate of a first capacitor, and the fourth plate CF4 and the seventh plate CF7 constitute another first capacitor of the pixel driving circuit. Because the seventh plate CF7 is connected to the first plate CF1 through a via, the first plate CF1 and the seventh plate CF7 have the same initial signal potential, so that the first plate CF1, the fourth plate CF4 and the third plate 97 form a first capacitor in a parallel connection structure, the first plate CF1 and the fourth plate CF4 form one first capacitor of the pixel driving circuit, and the fourth plate CF4 and the seventh plate CF7 form the other first capacitor of the pixel driving circuit, and the two first capacitors are connected in parallel.

[0403] In an exemplary embodiment, the eighth plate CF8 may have a rectangular shape, and the orthogonal projection of the eighth plate CF8 at the base at least partially overlaps with the orthogonal projection of the fifth plate CF5 at the base. On the one hand, the eighth plate CF8 is connected to the second plate CF2 through the via V88, and on the other hand, the eighth plate CF8 is connected to the initial signal line Vint through the via V83. The eighth plate CF8 may be a further plate of a second capacitor, and the fifth plate CF5 and the eighth plate CF8 constitute another second capacitor of the pixel driving circuit. Because the eighth plate CF8 is connected to the second plate CF2 through a via, the second plate CF2 and the eighth plate CF8 have the same initial signal potential, so that the second plate CF2, the fifth plate CF5 and the eighth plate CF8 form a second capacitor in a parallel connection structure, the second plate CF2 and the fifth plate CF5 form one second capacitor of the pixel driving circuit, and the fifth plate CF5 and the eighth plate CF8 form another second capacitor of the pixel driving circuit, and the two second capacitors are connected in parallel.

[0404] In an exemplary embodiment, the ninth plate CF9 may have a rectangular shape, and the orthogonal projection of the ninth plate CF9 at the base at least partially overlaps with the orthogonal projection of the sixth plate CF6 at the base. On the one hand, the ninth plate CF9 is connected to the third plate CF3 through the 89th via V89, and on the other hand, the ninth plate CF9 is connected to the high-voltage connection line VDD-C through the 86th via V86. The ninth plate CF9 may be a further plate of a storage capacitor, and the sixth plate CF6 and the ninth plate CF9 constitute another storage capacitor of the pixel driving circuit. Because the ninth plate CF9 is connected to the third plate CF3 through a via, the third plate CF3 and the ninth plate CF9 have the same first power supply potential, so that the third plate CF3, the sixth plate CF6 and the ninth plate CF9 form a storage capacitor in a parallel connection structure, in which the third plate CF3 and the sixth plate CF6 form one storage capacitor of the pixel driving circuit, and the sixth plate CF6 and the ninth plate CF9 form the other storage capacitor of the pixel driving circuit, and the two storage capacitors are connected in parallel.

[0405] In an exemplary embodiment, the position, shape and size of the ninth electrode plate CF9 in the second circuit unit Q2 and the third circuit unit Q3 may be substantially the same, but different from the shape and size of the ninth electrode plate CF9 in the first circuit unit Q1.

[0406] In an exemplary embodiment, the area of ​​the ninth plate CF9 in the first circuit unit Q1 may be larger than the area of ​​the ninth plate CF9 in the second circuit unit Q2 and the third circuit unit Q3, so that the capacitance value of the storage capacitor in the first circuit unit Q1 is larger than the capacitance value of the storage capacitor in the second circuit unit Q2 and the third circuit unit Q3.

[0407] In an exemplary embodiment, the first lengths M1 of the ninth plate CF9 in the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be approximately the same, and the second length M2 of the ninth plate CF9 in the first circuit unit Q1 may be greater than the second length M2 of the ninth plate CF9 in the second circuit unit Q2 and the third circuit unit Q3, so that the area of ​​the ninth plate CF9 in the first circuit unit Q1 is greater than the area of ​​the ninth plate CF9 in the second circuit unit Q2 and the third circuit unit Q3.

[0408] In an exemplary embodiment, the ratio between the second length M2 of the ninth electrode plate CF9 in the first circuit unit Q1 and the second length M2 of the ninth electrode plate CF9 in the second circuit unit Q2 and the third circuit unit Q3 may be about 1 to 2. For example, the ratio may be about 1.8.

[0409] In an exemplary embodiment, the shape of the 51st connecting electrode CO51 may be elongated extending along the second direction Y, and the first end of the 51st connecting electrode CO51 is connected to the first region of the first active layer (which is also the first region of the seventh active layer) through the 11th via V11, and the second end of the 51st connecting electrode CO51 is connected to the initial signal line Vint through the 84th via V84, thereby realizing the initial signal line Vint to write an initial signal to the first pole of the first transistor T1 and the first pole of the seventh transistor T7.

[0410] In an exemplary embodiment, the shape of the 52nd connecting electrode CO52 may be elongated extending along the second direction Y, and a first end of the 52nd connecting electrode CO52 is connected to the second region of the sixth active layer via the 22nd via V22, and a second end of the 52nd connecting electrode CO52 is connected to the second region of the seventh active layer via the 24th via V24, so that the 52nd connecting electrode CO52 causes the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7 to have the same potential (i.e., the second node N2 of the pixel driving circuit).

[0411] In an exemplary embodiment, the anode connection block 12 of the first circuit unit Q1 may be installed on the side of the 52nd connection electrode CO52 of the first circuit unit Q1 away from the 9th electrode CF9, and may be connected to the 52nd connection electrode CO52 of the first circuit unit Q1 via a connecting wire, thereby realizing the connection between the anode connection block 12 and the 52nd connection electrode CO52 in the first circuit unit Q1.

[0412] In an exemplary embodiment, the anode connection block 12 of the second circuit unit Q2 may be installed on the opposite side of the connecting electrode CO43 in the first direction X, and the anode connection block 12 is connected to the first end of the connecting electrode CO43 through the via V103, and the connecting electrode CO52 of the second circuit unit Q2 is connected to the second end of the connecting electrode CO43 through the via V104, thereby realizing the connection between the anode connection block 12 and the connecting electrode CO52 in the second circuit unit Q2.

[0413] In an exemplary embodiment, the anode connection block 12 of the third circuit unit Q3 may be installed on the opposite side of the 44th connection electrode CO44 in the first direction X, and the anode connection block 12 is connected to the first end of the 44th connection electrode CO44 through the 105th via V105, and the 52nd connection electrode CO52 of the third circuit unit Q3 is connected to the second end of the 44th connection electrode CO44 through the 106th via V106, thereby realizing the connection between the anode connection block 12 and the 52nd connection electrode CO52 in the third circuit unit Q3.

[0414] In the exemplary embodiment, the shape of the 53-connecting electrode CO53 is a polygonal line, a first end of the 53-connecting electrode CO53 is connected to the second region of the second active layer through the 14th via V14, a second end of the 53-connecting electrode CO53 is connected to the second region of the third active layer through the 16th via V16, and a portion between the first and second ends of the 53-connecting electrode CO53 is connected to the first region of the sixth active layer through the 21st via V21, and the 53-connecting electrode CO53 causes the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole of the sixth transistor T6 to have the same potential (i.e., the fourth node N4 of the pixel driving circuit).

[0415] In an exemplary embodiment, the shape of the 54th connecting electrode CO54 may be a polygonal line, with a first end of the 54th connecting electrode CO54 connected to the first region of the third active layer via the 15th via V15, a second end of the 54th connecting electrode CO54 connected to the second region of the fifth active layer via the 20th via V20, and a portion between the first and second ends of the 54th connecting electrode CO54 connected to the second region of the fourth active layer via the 18th via V18, so that the 54th connecting electrode CO54 causes the first pole of the third transistor T3, the second pole of the fourth transistor T4, and the second pole of the fifth transistor T5 to have the same potential (i.e., the fifth node N5 of the pixel driving circuit).

[0416] In an exemplary embodiment, the shape of the 55-connection electrode CO55 may be a polygonal line, with a first end of the 55-connection electrode CO55 connected to the first region of the second active layer via the 13th via V13, a second end of the 55-connection electrode CO55 connected to the third top gate electrode Gate3-T via the 95th via V95, and a portion of the 55-connection electrode CO55 between the first and second ends connected to the third bottom gate electrode Gate3-B via the 96th via V96. In an exemplary embodiment, the 55th-connection electrode CO55 connects the third top gate electrode Gate3-T and the third bottom gate electrode Gate3-B to each other, thereby connecting the first electrode of the second transistor T2 and the gate electrode of the third transistor T3 to each other.

[0417] In an exemplary embodiment, the shape of the 56th connecting electrode CO56 may be a polygonal line, a first end of the 56th connecting electrode CO56 is connected to the first region of the fifth active layer through the 19th via V19, and a second end of the 56th connecting electrode CO56 is connected to the 9th electrode plate CF9, and the 56th connecting electrode CO56 causes the first electrode of the fifth transistor T5 and the 9th electrode plate CF9 to have the same potential.

[0418] In an exemplary embodiment, the fifty-sixth connecting electrode CO56 and the ninth electrode plate CF9 may be an integrated structure connected to each other.

[0419] In an exemplary embodiment, the shape of the 57th connecting electrode CO57 may be a broken line extending along the second direction Y, a first end of the 57th connecting electrode CO57 is connected to the second region of the first active layer through the 12th via V12, and a second end of the 57th connecting electrode CO57 is connected to the sixth electrode plate CF6 through the 92nd via V92, and the 57th connecting electrode CO57 causes the second electrode of the first transistor T1 and the sixth electrode plate CF6 to have the same potential. The third top gate electrode Gate3-T, the sixth plate CF6 and the third gate electrode block 103 may be an integrated structure, in which the second pole of the first transistor T1 is connected to the sixth plate CF6, and the first pole of the second transistor T2 is connected to the gate electrode of the third transistor T3. Therefore, through the 55th connecting electrode CO55 and the 57th connecting electrode CO57, the second pole of the first transistor T1, the first pole of the second transistor T2, the gate electrode of the third transistor T3 and the sixth plate CF6 have the same potential (i.e., the third node N3 of the pixel driving circuit).

[0420] In an exemplary embodiment, the shape of the 58th connecting electrode CO58 may be a polygonal line extending along the second direction Y, a first end of the 58th connecting electrode CO58 is connected to the ninth gate electrode Gate9 through the 98th via V98, a second end of the 58th connecting electrode CO58 is connected to the fourth electrode plate CF4 through the 90th via V90, and a portion between the first and second ends of the 58th connecting electrode CO58 is connected to the second region of the eighth active layer through the 28th via V28, and the 58th connecting electrode CO58 causes the second electrode of the eighth transistor T8, the gate electrode of the 9th transistor T9, and the fourth electrode plate CF4 to have the same potential (i.e., the sixth node N6 of the pixel driving circuit).

[0421] In an exemplary embodiment, the 59th connecting electrode CO59 may have an elongated shape extending along the second direction Y, a first end of the 59th connecting electrode CO59 is connected to the 11th gate electrode Gate11 through the 77th via V77, and a second end of the 59th connecting electrode CO59 is connected to the 5th electrode CF5 through the 91st via V91, and the 59th connecting electrode CO59 causes the gate electrode of the 11th transistor T11 and the 5th electrode CF5 to have the same potential.

[0422] In an exemplary embodiment, the shape of the 60th connecting electrode CO60 may be elongated extending along the first direction X, a first end of the 60th connecting electrode CO60 is connected to the second region of the tenth active layer through the 32nd via V32, a second end of the 60th connecting electrode CO60 is connected to the 11th gate electrode Gate11 through the 78th via V78, and the gate electrode of the 11th transistor T11 and the second electrode of the tenth transistor T10 have the same potential through the 60th connecting electrode CO60. Since the gate electrode of the 11th transistor T11 is connected to the fifth plate CF5 and the second electrode of the tenth transistor T10, respectively, the 59th connecting electrode CO59 and the 60th connecting electrode CO60 cause the second electrode of the tenth transistor T10, the gate electrode of the 11th transistor T11, and the fifth plate CF5 to have the same potential (i.e., the seventh node N7 of the pixel driving circuit).

[0423] In an exemplary embodiment, the 61st connecting electrode CO61 may have an elongated shape extending along the first direction X, a first end of the 61st connecting electrode CO61 connected to the second region of the 11th active layer via the 34th via V34, a second end of the 61st connecting electrode CO61 connected to the first end of the 42nd connecting electrode CO42 via the 79th via V79, a portion of the 61st connecting electrode CO61 between the first and second ends connected to the second region of the 9th active layer via the 30th via V30, and the 61st connecting electrode CO61 connecting the second pole of the 9th transistor T9 and the second pole of the 11th transistor T11 to each other.

[0424] In an exemplary embodiment, the 62-connecting electrode CO62 may have an elongated shape extending along the second direction Y, with a first end of the 62-connecting electrode CO62 connected to a second end of the 42-connecting electrode CO42 via the 80th via V80 and a second end of the 62-connecting electrode CO62 connected to the 6th gate electrode block 106 via the 97th via V97. The 6th gate electrode block 106 is connected to the 6th gate electrode Gate6, and the 61st connecting electrode CO61 and the 62nd connecting electrode CO62 are connected to each other via the 42-connecting electrode CO42. Therefore, the 61st connecting electrode CO61 and the 62nd connecting electrode CO62 cause the 6th gate electrode Gate6, the second pole of the 9th transistor T9, and the second pole of the 11th transistor T11 to have the same potential (i.e., the first node N1 of the pixel driving circuit).

[0425] In an exemplary embodiment, the connecting electrode CO63 may have an L-shape, with a first end connected to the first region of the active layer through the via V33 and a second end connected to the second end of the connecting electrode CO41 through the via V94. The first end of the connecting electrode CO41 is connected to the high-frequency signal line Hf through a via, thereby enabling a high-frequency signal to be written to the first electrode of the transistor T11.

[0426] In an exemplary embodiment, the shape of the 64th connecting electrode CO64 may be L-shaped, a first end of the 64th connecting electrode CO64 is connected to the first region of the 9th active layer through the 29th via V29, a second end of the 64th connecting electrode CO64 is connected to the light-emitting signal line EM through the 81st via V81, and the region between the first and second ends of the 64th connecting electrode CO64 is connected to the 45th connecting electrode CO45 through the 99th via V99, thereby realizing the light-emitting signal being written to the first pole of the 9th transistor T9.

[0427] In an exemplary embodiment, the third conductive layer may further include a seventy-first connection electrode CO71 and a seventy-second connection electrode CO72.

[0428] In an exemplary embodiment, the shape of the 71st connection electrode CO71 may be elongated extending along the second direction Y, the 71st connection electrode CO71 may be installed in the second circuit unit Q2, one end of the 71st connection electrode CO71 is connected to the first low-voltage connection line VSS-C1 through the 101st via V101, and the 71st connection electrode CO71 is configured to be connected to the first power supply low-voltage line formed subsequently.

[0429] In an exemplary embodiment, the shape of the 72nd connection electrode CO72 may be elongated extending along the second direction Y, the 72nd connection electrode CO72 may be installed in the first circuit unit Q1, one end of the 72nd connection electrode CO72 is connected to the second low-voltage connection line VSS-C2 through the 102nd via V102, and the 72nd connection electrode CO72 is configured to be connected to a second low-voltage power supply line to be formed subsequently.

[0430] (26) Forming a fourth insulating layer and a first flat layer pattern. In an exemplary embodiment, as shown in Fig. 25, forming the fourth insulating layer and the first flat layer pattern may include first applying a first flat thin film on the base on which the above-mentioned pattern is formed, patterning the first flat thin film by a patterning process, depositing a fourth insulating thin film, and patterning the fourth insulating thin film by a patterning process to form a first flat layer covering the third conductive layer pattern and a fourth insulating layer disposed on a side of the first flat layer away from the base, and a plurality of vias may be disposed in the fourth insulating layer and the first flat layer.

[0431] In an exemplary embodiment, the plurality of vias may include at least a 65th via V65, a 70th via V70, a 71st via V71, and a 72nd via V72.

[0432] In an exemplary embodiment, a 65th via V65 may be installed in each circuit unit, and the orthogonal projection of the base of the 65th via V65 is within the range of the orthogonal projection of the base of the anode connection block 12. The fourth insulating thin film and the first flat thin film in the 65th via V65 are removed to expose the surface of the anode connection block 12. The 65th via V65 is configured to connect a subsequently formed anode connection electrode to the anode connection block 12 through the via.

[0433] In the exemplary embodiment, the orthogonal projection of the base of the 70th via V70 is within the range of the orthogonal projection of the base of the 71st connecting electrode CO71. The fourth insulating thin film and the first planar thin film in the 70th via V70 are removed to expose the surface of the 71st connecting electrode CO71. The 70th via V70 is configured to connect a subsequently formed first low-voltage power line to the 71st connecting electrode CO71 through the via.

[0434] In the exemplary embodiment, the orthogonal projection of the base of the 71st via V71 is within the range of the orthogonal projection of the base of the 72nd connecting electrode CO72. The fourth insulating thin film and the first planar thin film in the 71st via V71 are removed to expose the surface of the 72nd connecting electrode CO72. The 71st via V71 is configured to connect a subsequently formed second low-voltage power line to the 72nd connecting electrode CO72 through the via.

[0435] In an exemplary embodiment, the orthogonal projection of the base of the 72nd via V72 is within the range of the orthogonal projection of the base of the high-voltage connecting line VDD-C. The fourth insulating thin film, the first planar thin film, and the third insulating layer in the 72nd via V72 are removed to expose the surface of the high-voltage connecting line VDD-C. The 72nd via V72 is configured to connect a subsequently formed high-voltage power supply line to the high-voltage connecting line VDD-C through the via.

[0436] (27) Forming a fourth conductive layer pattern. In an exemplary embodiment, as shown in Figures 26A and 26B, forming the fourth conductive layer pattern may include depositing a fourth conductive thin film on the base on which the above-mentioned pattern is formed, and patterning the fourth conductive thin film by a patterning process to form a fourth conductive layer pattern disposed on the fourth insulating layer. Figure 26B is a schematic plan view of the fourth conductive layer in Figure 26A.

[0437] In an exemplary embodiment, the fourth conductive layer pattern may include at least an anode connecting electrode 13, a high-voltage power supply line VDD, a first low-voltage power supply line VSS1, and a second low-voltage power supply line VSS2.

[0438] In an exemplary embodiment, the anode connection electrode 13 may be rectangular in shape, and the anode connection electrode 13 is connected to the anode connection block 12 through the 65th via V65, and the anode connection electrode 13 is configured to be binding-connected to the first pole of the light-emitting diode.

[0439] In an exemplary embodiment, the high-voltage power line VDD may have a linear shape extending along the second direction Y, and the high-voltage power line VDD is connected to the high-voltage connecting line VDD-C through the 72nd via V72, thereby realizing a connection between the high-voltage connecting line VDD-C extending along the first direction X and the high-voltage power line VDD extending along the second direction Y, and forming a net-like communication structure for transmitting high-voltage power signals.

[0440] In an exemplary embodiment, the first low-voltage power supply line VSS1 may have a linear shape extending along the second direction Y, and the first low-voltage power supply line VSS1 is connected to the 71st connecting electrode CO71 through the 70th via V70. The 71st connecting electrode CO71 is connected to the first low-voltage connecting line VSS-C1 through the via, thereby realizing a connection between the first low-voltage connecting line VSS-C1 extending along the first direction X and the first low-voltage power supply line VSS1 extending along the second direction Y, and forming a net-like communication structure for transmitting a first low-voltage power supply signal.

[0441] In an exemplary embodiment, the second low-voltage power supply line VSS2 may have a linear shape extending along the second direction Y, and the second low-voltage power supply line VSS2 is connected to the 72nd connection electrode CO72 through the 71st via V71. The 72nd connection electrode CO72 is connected to the second low-voltage connecting line VSS-C2 through the via, thereby realizing a connection between the second low-voltage connecting line VSS-C2 extending along the first direction X and the second low-voltage power supply line VSS2 extending along the second direction Y, and forming a net-like communication structure for transmitting a second low-voltage power supply signal.

[0442] 26C is a schematic diagram of power supply wiring according to an exemplary embodiment of the present disclosure, illustrating the structure of high-voltage power lines and low-voltage power lines in multiple circuit units. As shown in FIG. 26C, the high-voltage power line VDD, the first low-voltage power line VSS1, and the second low-voltage power line VSS2 may have linear shapes extending along the second direction Y, and the first low-voltage power line VSS1 and the second low-voltage power line VSS2 may be disposed between adjacent high-voltage power lines VDD, and multiple anode connecting electrodes 13 may be disposed between the first low-voltage power line VSS1 and the second low-voltage power line VSS2.

[0443] In an exemplary embodiment, a first pad block is provided on a side of the first low-voltage power line VSS1 closer to the second low-voltage power line VSS2, and the first pad block is configured to connect the second pole of the first light-emitting diode. A second pad block is provided on a side of the second low-voltage power line VSS2 closer to the first low-voltage power line VSS1, and the second pad block is configured to connect the second poles of the second light-emitting diode and the third light-emitting diode.

[0444] In an exemplary embodiment, the low-voltage power supply lines may include a first low-voltage power supply line, a second low-voltage power supply line, and a third low-voltage power supply line, and the three low-voltage power supply lines respectively supply low-voltage power supply signals to the first light-emitting diode, the second light-emitting diode, and the third light-emitting diode, thereby maximally reducing power consumption.

[0445] (28) Forming a fifth insulating layer and a second planar layer pattern. In an exemplary embodiment, as shown in FIG. 27 , forming the fifth insulating layer and the second planar layer pattern may include first depositing a fifth insulating thin film on the base on which the above-mentioned pattern is formed, then applying a second planar thin film, and then depositing a sixth insulating thin film, and patterning the fifth insulating thin film, the second planar thin film, and the sixth insulating thin film through a patterning process to form a fifth insulating layer covering the fourth conductive layer pattern, a second planar layer disposed on a side of the fifth insulating layer away from the base, and a sixth insulating layer disposed on a side of the second planar layer away from the base, and forming a plurality of binding vias in the fifth insulating layer, the second planar layer, and the sixth insulating layer.

[0446] In an exemplary embodiment, the plurality of binding vias includes at least a plurality of first binding vias K1 and a plurality of second binding vias K2, and the plurality of first binding vias K1 and the plurality of second binding vias K2 are both located in the area where the blank unit KB is located.

[0447] In an exemplary embodiment, the first binding via K1 may have a rectangular shape, and the orthogonal projection of the base of the first binding via K1 is within the range of the orthogonal projection of the base of the anode connecting electrode 13. The sixth insulating thin film, the second planar thin film, and the fifth insulating thin film in the first binding via K1 are removed to expose the surface of the anode connecting electrode 13. The area of ​​the anode connecting electrode 13 exposed by the first binding via K1 may be an anode pad. The first binding via K1 is configured to bind-connect a first electrode of the light-emitting diode to the anode connecting electrode 13 through the binding via.

[0448] In an exemplary embodiment, the second binding via K2 may have a rectangular shape. The orthogonal projection of the base of the second binding via K2 of the first circuit unit Q1 is within the range of the orthogonal projection of the base of the first low-voltage power line VSS1. The sixth insulating thin film, the second flattening thin film, and the fifth insulating thin film in the second binding via K2 are removed to expose the surface of the first low-voltage power line VSS1. The area of ​​the first low-voltage power line VSS1 exposed by the second binding via K2 may be used as a cathode pad for connecting a first light-emitting diode. The second binding via K2 is configured to connect a second electrode of the first light-emitting diode to the first low-voltage power line VSS1 through the binding via. The orthogonal projection of the base of the second binding via K2 of the second circuit unit Q2 and the second circuit unit Q3 is within the range of the orthogonal projection of the base of the second low-voltage power line VSS2. The sixth insulating thin film, the second flattening thin film, and the fifth insulating thin film in the second binding via K2 are removed to expose the surface of the second low-voltage power line VSS2. The area of ​​the second low-voltage power line VSS2 exposed by the second binding via K2 may be used as a cathode pad connecting the second light-emitting diode and the third light-emitting diode, and the second binding via K2 is configured to connect the second electrodes of the second light-emitting diode and the third light-emitting diode to the second low-voltage power line VSS2, respectively, through the binding via.

[0449] Up to this point, the drive circuit layer of this exemplary embodiment is fabricated and completed.

[0450] In the display substrate according to the exemplary embodiment of the present disclosure, the width-to-length ratio of the third transistor in the first circuit unit is set to be greater than the width-to-length ratio of the third transistor in the second circuit unit and the third circuit unit, and the capacitance value of the storage capacitor in the first circuit unit is set to be greater than the capacitance values ​​of the storage capacitors in the second circuit unit and the third circuit unit, thereby satisfying the current value required by the red LED and realizing more gray scales, and not only can avoid defects such as the brightness not meeting the requirements or the inability to realize more gray scales in the conventional structure, but also effectively reducing the jump amount of the gate voltage of the third transistor and ensuring accurate writing of the gate voltage.

[0451] In the present disclosure, the first capacitor, the second capacitor, and the storage capacitor are connected in parallel, thereby ensuring capacitance while minimizing the space occupied by the first capacitor, the second capacitor, and the storage capacitor, which is advantageous for achieving high-resolution displays. In the present disclosure, the high-frequency signal lines are formed with a network-connected structure, thereby minimizing the resistance of the high-frequency signal lines, reducing the voltage drop of the high-frequency signals, and effectively improving the power supply voltage uniformity on the display substrate and the uniformity within the signal plane. In the present disclosure, the high-voltage power supply lines and the low-voltage power supply lines are formed with a network-connected structure, thereby minimizing the resistance of the power supply transmission lines, reducing the power supply voltage drop, effectively improving the power supply voltage uniformity on the display substrate, effectively improving the uniformity within the signal plane, effectively improving display uniformity, and improving display attributes and display quality.

[0452] In the present disclosure, the addition of a first low-voltage power supply line and a second low-voltage power supply line can effectively reduce and minimize power consumption. Research has shown that when driving light-emitting diodes, there is a certain difference in the voltages across the R, G, and B chips. For example, for the same emission brightness, the voltage required across the R chip is approximately 2V lower than the voltage required across the B chip. If the low-voltage power supply voltage is designed to meet the crossover voltage demand of the B chip, the crossover voltage of the R chip will exceed the crossover voltage demand, resulting in increased power consumption. In the present disclosure, the low-voltage power supplies of the R chip and the G / B chips are designed independently. The first low-voltage power supply line is used to supply the first low-voltage power signal to the R chip, and the second low-voltage power supply line is used to supply the second low-voltage power signal to the G / B chip. This separately controls the low-voltage power supplies of the different chips, effectively reducing and minimizing power consumption while ensuring the normal operation of the pixel driving circuit. Experimental verification has shown that compared to a display substrate structure that uses one low-voltage power line, the present disclosure uses two low-voltage power lines, with the low-voltage power supply voltage of the first low-voltage power line set to 6.6V and the low-voltage power supply voltage of the second low-voltage power line set to 4.6V, thereby reducing overall power consumption by more than 12%.

[0453] 28 is a structural schematic diagram of a further display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of three circuit units, each including the pixel driving circuit shown in FIG. 16. As shown in FIG. 28, the plurality of circuit units may include at least a first circuit unit Q1, a second circuit unit Q2, and a third circuit unit Q3 arranged in sequence along a first direction X. The first pixel driving circuit in the first circuit unit Q1 is configured to be connected to a first light-emitting diode, the second pixel driving circuit in the second circuit unit Q2 is configured to be connected to a second light-emitting diode, and the third pixel driving circuit in the third circuit unit Q3 is configured to be connected to a third light-emitting diode. The first light-emitting diode may be a red light-emitting diode, the second light-emitting diode may be a green light-emitting diode, and the third light-emitting diode may be a blue light-emitting diode.

[0454] In an exemplary embodiment, the width-to-length ratio of the first drive transistor DTFT1 may be greater than the width-to-length ratios of the second drive transistor DTFT2 and the third drive transistor DTFT3, and the capacitance value of the first storage capacitor Cs1 may be approximately the same as the capacitance values ​​of the second storage capacitor Cs2 and the third storage capacitor Cs3.

[0455] In an exemplary embodiment, at least one circuit unit may include a high-frequency connecting line Hf-C extending along a first direction X and a high-frequency signal line Hf extending along a second direction Y, and the high-frequency signal line Hf may be connected to the high-frequency connecting line Hf-C through a via to form a net-like communication structure for transmitting high-frequency signals.

[0456] In an exemplary embodiment, at least one circuit unit may include a high-voltage connecting line VDD-C extending along a first direction X and a high-voltage power supply line VDD extending along a second direction Y, where the high-voltage connecting line VDD is connected to a corresponding pixel driving circuit, and the high-voltage power supply line VDD is connected to the high-voltage connecting line VDD-C through a via, forming a net-like communication structure for transmitting a high-voltage power supply signal.

[0457] In an exemplary embodiment, at least one circuit unit may include a low-voltage connecting line VSS-C extending along a first direction X and a low-voltage power supply line VSS extending along a second direction Y, and the low-voltage power supply line VSS may be connected to the low-voltage connecting line VSS-C through a via to form a net-like communication structure for transmitting a low-voltage power supply signal.

[0458] In an exemplary embodiment, the structure of the driving transistor in this embodiment may be substantially the same as the structure of the driving transistor shown in FIG. 17, and the structure of the storage capacitor in this embodiment may be substantially the same as the structure of the storage capacitor shown in FIG. 17, with the difference being that the areas of the first storage capacitor Cs1, the second storage capacitor Cs2 and the third storage capacitor Cs3 may be substantially the same.

[0459] In an exemplary embodiment, the manufacturing process of the driving circuit layer of this example may include the following operations.

[0460] (31) Form a first conductive layer pattern. As shown in Figure 29, the first conductive layer pattern of each circuit unit may include at least a first electrode plate CF1, a second electrode plate CF2, a third electrode plate CF3, and a third bottom gate electrode Gate3-B.

[0461] In an exemplary embodiment, the first plate CF1, the second plate CF2, and the third plate CF3 may have a rectangular shape, the corners of the rectangle may be chamfered, the first plate CF1 and the second plate CF2 may be disposed on opposite sides of the circuit unit in the second direction Y, the third bottom gate electrode Gate3-B may be disposed on the second direction Y side of the circuit unit, and the third plate CF3 may be located between the first plate CF1 and the third bottom gate electrode Gate3-B. The difference from the structure shown in FIG. 20 is that the first plate CF1 is disposed on the first direction X side of the second plate CF2.

[0462] In an exemplary embodiment, the position and shape of the third plate CF3 in the three circuit units may be approximately the same, the first length M1 and the second length M2 of the third plate CF3 in the three circuit units may be approximately the same, and the area of ​​the third plate CF3 in the three circuit units may be approximately the same.

[0463] In an exemplary embodiment, the position, shape and size of the third bottom gate electrode Gate3-B may be substantially the same as the structure shown in FIG.

[0464] (32) Forming a Semiconductor Layer Pattern As shown in Fig. 30, the semiconductor layer pattern of each circuit unit may include at least the first active layer AT1 of the first transistor T1 to the eleventh active layer AT11 of the eleventh transistor T11.

[0465] In an exemplary embodiment, the positions and shapes of the first active layer AT1 to the eleventh active layer AT11 may be substantially the same as the structure shown in Figures 21A and 21B, with the difference being that the tenth active layer AT10 may be located on the second direction Y side of the second electrode plate CF2, and the eighth active layer AT8 may be located on the second direction Y side of the tenth active layer AT10.

[0466] (33) Forming a second conductive layer pattern. As shown in Figure 31, the second conductive layer pattern of each circuit unit includes at least a fourth electrode plate CF4, a fifth electrode plate CF5, a sixth electrode plate CF6, a first scanning signal line S1, a second scanning signal line S2, a light emitting signal line EM, a second control line CT2, an initial signal line Vint, a high frequency connecting line Hf-C, a high voltage connecting line VDD-C, a low voltage connecting line VSS-C, a plurality of gate electrodes, and a plurality of connecting electrodes.

[0467] In an exemplary embodiment, the positions of the fourth electrode plate CF4, the fifth electrode plate CF5, and the sixth electrode plate CF6 may be substantially the same as the structure shown in FIGS. 22A and 22B, with the difference being that the fourth electrode plate CF4 is disposed on the first direction X side of the fifth electrode plate CF5, and the position, shape, and size of the sixth electrode plate CF6 in the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be substantially the same.

[0468] In an exemplary embodiment, the positions and shapes of the first scanning signal line S1, the second scanning signal line S2, the light-emitting signal line EM, the second control line CT2, the initial signal line Vint, the high-frequency connecting line Hf-C, the high-voltage connecting line VDD-C, and the low-voltage connecting line VSS-C may be substantially the same as those shown in FIGS. 22A and 22B, with the difference being that in this embodiment, only one low-voltage connecting line VSS-C is provided, and the second scanning signal line S2 is also used as the first control line to control the turning on and off of the eighth transistor T8.

[0469] In an exemplary embodiment, the multiple gate electrodes of each circuit unit may include at least a first gate electrode Gate1, a second gate electrode Gate2, a third top gate electrode Gate3-T, a fourth gate electrode Gate4, a fifth gate electrode Gate5, a sixth gate electrode Gate6, a seventh gate electrode Gate7, an eighth gate electrode Gate8, a ninth gate electrode Gate9, a tenth gate electrode Gate10, and an eleventh gate electrode Gate11.

[0470] In an exemplary embodiment, the multiple connection electrodes of each circuit unit include at least the 41st connection electrode CO41, the 42nd connection electrode CO42, and the 45th connection electrode CO45, and the positions and shapes of the 41st connection electrode CO41, the 42nd connection electrode CO42, and the 41st connection electrode CO41 may be approximately the same as the structure shown in Figures 22A and 22B.

[0471] (34) Forming a third insulating layer pattern As shown in Fig. 32, a plurality of vias are provided in the third insulating layer in each circuit unit.

[0472] In an exemplary embodiment, the positions and functions of the multiple vias may be approximately the same as the structure shown in Figure 23, with the difference being that the 43rd and 44th connection electrodes are not installed, and the shapes of the 9th gate electrode Gate9 and the 11th gate electrode Gate11 are different, so the positions of the corresponding vias are different, which will not be described again here.

[0473] (35) Form a third conductive layer pattern. As shown in Figure 33, the third conductive layer pattern includes at least a data signal line DataI, a high-frequency signal line Hf, a seventh electrode plate CF7, an eighth electrode plate CF8, a ninth electrode plate CF9, an anode connection block 12, and a plurality of connection electrodes.

[0474] In an exemplary embodiment, the positions, shapes, and connection structures of the data signal line DataI, the high-frequency signal line Hf, the seventh plate CF7, the eighth plate CF8, and the ninth plate CF9 may be substantially the same as those shown in FIGS. 24A and 24B , except that the seventh plate CF7 is disposed on the first direction X side of the eighth plate CF8, and the sizes and areas of the ninth plate CF9 in the first circuit unit Q1, the second circuit unit Q2, and the third circuit unit Q3 may be substantially the same.

[0475] In an exemplary embodiment, the plurality of connection electrodes may include at least a 51st connection electrode CO51, a 52nd connection electrode CO52, a 53rd connection electrode CO53, a 54th connection electrode CO54, a 55th connection electrode CO55, a 56th connection electrode CO56, a 57th connection electrode CO57, a 58th connection electrode CO58, a 59th connection electrode CO59, a 60th connection electrode CO60, a 61st connection electrode CO61, a 62nd connection electrode CO62, a 63rd connection electrode CO63, and a 64th connection electrode CO64. The positions, shapes, and connection structures of the above connection electrodes may be substantially the same as those shown in Figures 24A and 24B, with the only differences being that the 51st connection electrode CO51 is further connected to the seventh electrode plate CF7 through a via, the 58th connection electrode CO58 is connected to the 11th gate electrode Gate11, and the 59th connection electrode CO59 is connected to the 9th gate electrode Gate9, and these will not be described again here.

[0476] In the exemplary embodiment, the anode connection block 12 and the 52nd connection electrode CO52 of each circuit unit are an integrated structure connected to each other.

[0477] In an exemplary embodiment, the third conductive layer may further include a 71st connecting electrode CO71. The 71st connecting electrode CO71 may have an elongated shape extending along the second direction Y, and may be disposed on the second circuit unit Q2. One end of the 71st connecting electrode CO71 is connected to the low-voltage connecting line VSS-C through a via, and the 71st connecting electrode CO71 is configured to be connected to a power supply low-voltage line to be formed subsequently.

[0478] (36) Forming a fourth insulating layer and a first flat layer pattern As shown in Fig. 34, in each circuit unit, a plurality of vias are provided in the fourth insulating layer and the first flat layer.

[0479] In an exemplary embodiment, the vias may include at least the 65th via V65, the 70th via V70, and the 72nd via V72, and the positions and functions of the vias may be substantially the same as the structure shown in FIG.

[0480] (37) Form a fourth conductive layer pattern. The fourth conductive layer pattern may include at least an anode connecting electrode 13, a high-voltage power supply line VDD, and a low-voltage power supply line VSS. As shown in FIGS. 35A and 35B, FIG. 35B is a schematic diagram of another power supply wiring according to an exemplary embodiment of the present disclosure, illustrating the structure of the high-voltage power supply line and the low-voltage power supply line in multiple circuit units.

[0481] In an exemplary embodiment, the high-voltage power supply line VDD and the low-voltage power supply line VSS may have a linear shape extending along the second direction Y. The high-voltage connection line VDD-C extending along the first direction X is connected to the high-voltage power supply line VDD extending along the second direction Y through a via, forming a net-like communication structure for transmitting a high-voltage power supply signal. The low-voltage connection line VSS-C extending along the first direction X is connected to the low-voltage power supply line VSS extending along the second direction Y through a via, forming a net-like communication structure for transmitting a low-voltage power supply signal.

[0482] The high-voltage power line VDD and the low-voltage power line VSS are respectively provided with a high-voltage opening and a low-voltage opening, the high-voltage opening may be provided with one T-shaped low-voltage power line and three anode connecting electrodes 13, and the low-voltage opening may be provided with two anode connecting electrodes 13, the low-voltage power line being configured to connect the second pole of the light-emitting diode. A pad block is provided on the side of the low-voltage power line VSS closer to the high-voltage power line VDD, and the pad block is configured to connect the second pole of the light-emitting diode.

[0483] In an exemplary embodiment, the position, shape and connection structure of the anode connection electrode 13 may be substantially the same as the structure shown in FIGS. 26A and 26B, and will not be described again here.

[0484] (38) Forming a fifth insulating layer and a second flat layer pattern. As shown in Figure 36, a first binding via K1 and a second binding via K2 are provided in the fifth insulating layer, the second flat layer, and the sixth insulating layer of each circuit unit.

[0485] In an exemplary embodiment, the location and function of the binding vias may be substantially the same as the structure shown in FIG.

[0486] Up to this point, the drive circuit layer of this exemplary embodiment is fabricated and completed.

[0487] In the display substrate according to the exemplary embodiment of the present disclosure, the width-to-length ratio of the third transistor in the first circuit unit is made larger than the width-to-length ratios of the third transistors in the second circuit unit and the third circuit unit, thereby meeting the current value required by the red light-emitting diode and realizing more gray scales, and avoiding defects such as insufficient brightness or inability to realize more gray scales in the conventional structure.

[0488] In the present disclosure, the first capacitor, the second capacitor, and the storage capacitor are connected in parallel, thereby ensuring capacitance while minimizing the space occupied by the first capacitor, the second capacitor, and the storage capacitor, which is advantageous for achieving high-resolution displays. In the present disclosure, the high-frequency signal lines are formed with a network-connected structure, thereby minimizing the resistance of the high-frequency signal lines, reducing the voltage drop of the high-frequency signals, and effectively improving the power supply voltage uniformity on the display substrate and the uniformity within the signal plane. In the present disclosure, the high-voltage power supply lines and the low-voltage power supply lines are formed with a network-connected structure, thereby minimizing the resistance of the power supply transmission lines, reducing the power supply voltage drop, effectively improving the power supply voltage uniformity on the display substrate, effectively improving the uniformity within the signal plane, effectively improving display uniformity, and improving display attributes and display quality.

[0489] In an exemplary embodiment, a number of inspections are required during the manufacturing process of a display substrate, and one of the most important inspections is screen inspection using a detection circuit CT, also known as CT inspection. CT inspection involves inputting a detection signal to the display substrate to cause the light-emitting diodes to emit light, and then using a defect detection device to inspect whether each light-emitting diode is normal, thereby determining whether the display substrate has any defects.

[0490] FIG. 37 is a schematic diagram illustrating a display substrate performing CT detection. As shown in FIG. 37, the display substrate may include a display area AA and a binding area FA located on the display area AA side. The display area AA may include a plurality of circuit units and a plurality of light-emitting units. The circuit units may include at least a pixel driving circuit. The light-emitting units may include at least a light-emitting diode. The light-emitting diodes may be connected to the pixel driving circuit of the corresponding circuit unit. The display area AA may include a plurality of data signal lines DataI, and each data signal line DataI is connected to a plurality of pixel driving circuits in one unit column.

[0491] In an exemplary embodiment, the binding area FA may include a detection circuit, which may include at least a plurality of detection units 210, at least one control line 220, and at least one detection line 230. The detection units 210 may be sequentially arranged at set intervals along the first direction X, and the positions of the detection units 210 may correspond one-to-one to the positions of the plurality of data signal lines DataI in the display area AA. Each detection unit 210 may include a control end, an input end, and an output end. One end of the control line 220 may be connected to a pin in the binding pin area, and the other end of the control line 220 may be connected to the control ends of the plurality of detection units 210. The control line 220 is configured to control the turn-on or turn-off of the plurality of detection units 210. One end of the detection line 230 may be connected to a pin in the binding pin area, and the other end of the detection line 230 may be connected to the input ends of the plurality of detection units 210. The output ends of the plurality of detection units 210 may be connected to the plurality of data signal lines DataI in the display area AA. The detection unit 210 is configured to output a signal from the detection line 230 to the data signal line DataI of the display area AA under the control of the control line 220, thereby realizing CT detection of the display substrate.

[0492] 38 is a structural schematic diagram of a detection circuit according to an exemplary embodiment of the present disclosure. As shown in FIG. 38, the detection circuit may include at least a plurality of detection units 210, a control line 220, and a detection line 230. Output ends of the plurality of detection units 210 may be connected to a plurality of data signal lines DataI in the display area via a plurality of transmission lines 240. The shape of the plurality of transmission lines 240 may be a polygonal line extending toward the display area. The intervals between adjacent transmission lines 240 may be approximately the same.

[0493] In an exemplary embodiment, a shield line 250 may be installed between at least one transmission line 240 and an adjacent transmission line 240, and the shape of the shield line 250 may be substantially the same as the shape of the transmission line 240.

[0494] In an exemplary embodiment, the transmission line 240 and the shield line 250 may be disposed on the same layer and formed synchronously by the same patterning process.

[0495] In an exemplary embodiment, the distance between the edge of shield wire 250 closer to transmission line 240 and the edge of transmission line 240 closer to shield wire 250 may be approximately 10 μm to 20 μm. For example, the distance between the edge of shield wire 250 closer to transmission line 240 and the edge of transmission line 240 closer to shield wire 250 may be approximately 15 μm.

[0496] In an exemplary embodiment, the shield line 250 may be connected to a constant voltage signal line or a ground signal line, and the shield line 250 is configured to reduce data voltage jumps on the transmission line 240 due to coupling capacitance.

[0497] In an exemplary embodiment, the constant voltage signal line may be a high voltage power supply line, a low voltage power supply line, or an initial signal line.

[0498] 39 is a schematic diagram of a connection between a shield line and a constant-voltage signal line according to an exemplary embodiment of the present disclosure. As shown in FIG. 39, the constant-voltage signal line may be the initial signal line Vint, the shield line 250 and the initial signal line Vint may be installed on different conductive layers, and the shield line 250 may be connected to the initial signal line Vint through a via K0.

[0499] In an exemplary embodiment, the initial signal line Vint may be connected to the plurality of shield lines 250 through the plurality of vias K0, respectively, to supply a constant voltage signal to the plurality of shield lines 250.

[0500] In an exemplary embodiment, there may be a plurality of initial signal lines Vint in order to improve connection reliability.

[0501] In this disclosure, by providing a shielding line between the transmission lines of the detection circuit, it is possible to effectively shield the coupling capacitance between adjacent transmission lines and reduce data voltage jumps. Research has shown that when a detection circuit performs CT detection, coupling capacitance exists between adjacent transmission lines, which causes data voltage jumps and leads to test errors. In this disclosure, by providing a shielding line between the transmission lines of the detection circuit and connecting the shielding line to a constant voltage signal line, the constant voltage shielding line can effectively shield the coupling capacitance between adjacent transmission lines, effectively reducing data voltage jumps and improving test data accuracy, without the need for additional signals and without affecting the data voltage.

[0502] It should be noted that the structures and manufacturing processes shown in the exemplary embodiments of the present disclosure are merely examples, and the corresponding structures can be modified or patterning processes can be added or removed according to actual needs, and the embodiments of the present disclosure are not specifically limited here.

[0503] The display substrate according to the exemplary embodiments of the present disclosure can be applied to any LED driving pixel circuit, including P-type PAM, P-type PAM+PWM, N-type PAM, N-type PAM+PWM, LTPO-type PAM and PAM+PWM circuits, etc.

[0504] An exemplary embodiment of the present disclosure further provides a method for manufacturing the display substrate, in an exemplary embodiment, the method includes: The method may include forming a drive circuit layer on a base, the drive circuit layer including a plurality of circuit units, the plurality of circuit units including at least a first circuit unit, a second circuit unit, and a third circuit unit, the first circuit unit including a first pixel drive circuit, the first pixel drive circuit including at least a first drive transistor, the second circuit unit including a second pixel drive circuit, the second pixel drive circuit including at least a second drive transistor, the third circuit unit including a third pixel drive circuit, the third pixel drive circuit including at least a third drive transistor, a channel width of the first drive transistor being larger than a channel width of the second drive transistor or the third drive transistor, and a channel length of the first drive transistor being the same as a channel length of the second drive transistor or the third drive transistor.

[0505] An exemplary embodiment of the present disclosure further provides a display device, comprising the display substrate of the above embodiment. The display device may be a product or component with a display function, such as a mobile phone, a tablet, a television, a monitor, a laptop, a digital frame, or a navigation device.

[0506] The drawings in this disclosure only relate to the structures disclosed herein, and other structures may refer to conventional designs. Where there is no conflict, the embodiments and features of the embodiments in this disclosure may be combined with each other to obtain new embodiments. As will be understood by those skilled in the art, modifications or equivalent substitutions may be made to the technical solutions of this disclosure without departing from the spirit and scope of the technical solutions of this disclosure. Any such modifications or equivalent substitutions should be included within the scope of the claims of this disclosure. [Explanation of symbols]

[0507] AA display area, AT1 first active layer, AT2 second active layer, AT3 3rd active layer, AT4 4th active layer, AT5 5th active layer, AT6 6th active layer, AT7 7th active layer, AT8 8th active layer, AT9 9th active layer, AT10 10th active layer, AT11 11th active layer, AT12 12th active layer, CF1 1st electrode plate, CF2 2nd electrode plate, CF3 3rd plate, CF4 4th plate, CF5 5th plate, CF6 6th plate, CF7 7th plate, CF8 8th plate, CF9 9th plate, Cs1 1st storage capacitor, Cs2 2nd storage capacitor, Cs3 third storage capacitor, CT1 first control line, CT2 second control line, C1: First capacitor; C2: Second capacitor; DTFT1: First driving transistor; DTFT2: Second driving transistor, DTFT3: Third driving transistor, DataI: Data signal line, DataT time length signal line, EM emission signal line, FA binding region, Gate1: first gate electrode; Gate2: second gate electrode; Gate3-B: third bottom gate electrode; Gate3-T: third top gate electrode, Gate4: fourth gate electrode, Gate5: fifth gate electrode, Gate 6: sixth gate electrode, Gate 7: seventh gate electrode, Gate 8: eighth gate electrode, Gate 9: 9th gate electrode, Gate 10: 10th gate electrode, Gate 11: 11th gate electrode, Gate12 12th gate electrode, Hf high frequency signal line, Hf-C high frequency connection line, S1 First scan signal line, S2 Second scan signal line, VDD High voltage power supply line, VDD-C high voltage connection line, VSS low voltage power supply line, VSS-C low voltage connection line, Vint initial signal line, 10 base, 11 power electrode, 12 anode connection block; 13 anode connection electrode; 20 drive circuit layer; 30 light-emitting structure layers, 40 light-emitting diodes, 100 motherboards, 200 display board, 210 detection unit, 220 control line, 230 detection wire, 240 transmission wire, 250 shielded wire

Claims

1. 1. A display substrate comprising: a driving circuit layer disposed on a base; the driving circuit layer comprising a plurality of circuit units, the plurality of circuit units including at least a first circuit unit, a second circuit unit, and a third circuit unit; the first circuit unit comprising a first pixel driving circuit, the first pixel driving circuit comprising at least a first driving transistor, the second circuit unit comprising a second pixel driving circuit, the second pixel driving circuit comprising at least a second driving transistor, the third circuit unit comprising a third pixel driving circuit, the third pixel driving circuit comprising at least a third driving transistor, a channel width of the first driving transistor being larger than a channel width of the second driving transistor or the third driving transistor, and a channel length of the first driving transistor being the same as a channel length of the second driving transistor or the third driving transistor.

2. 2. The display substrate of claim 1, wherein a ratio of the channel width of the first driving transistor to the channel width of the second driving transistor or the third driving transistor is 2-6.

3. 2. The display substrate of claim 1, wherein a channel width of the second driving transistor is the same as a channel width of the third driving transistor, and a channel length of the second driving transistor is the same as a channel length of the third driving transistor.

4. the first pixel driving circuit further includes a first storage capacitor, the second pixel driving circuit further includes a second storage capacitor, and the third pixel driving circuit further includes a third storage capacitor, and a capacitance value of the first storage capacitor is equal to or greater than a capacitance value of the second storage capacitor or the third storage capacitor; 2. The display substrate according to claim 1, wherein the area of ​​the orthogonal projection of the first storage capacitor on the base is preferably larger than the area of ​​the orthogonal projection of the second storage capacitor or the third storage capacitor on the base.

5. 5. The display substrate of claim 4, wherein a first length of the orthogonal projection of the first storage capacitor at the base is the same as a first length of the orthogonal projection of the second storage capacitor or the third storage capacitor at the base, a second length of the orthogonal projection of the first storage capacitor at the base is equal to or greater than a second length of the orthogonal projection of the second storage capacitor or the third storage capacitor at the base, the first length being a size in a first direction, the second length being a size in a second direction, and the first direction intersecting the second direction.

6. 6. The display substrate of claim 5, wherein a ratio between the second length of the orthogonal projection of the first storage capacitor at the base and the second length of the orthogonal projection of the second storage capacitor or the third storage capacitor at the base is 1 to 2.

7. 6. The display substrate of claim 5, wherein a first length of the orthogonal projection of the second storage capacitor at the base is the same as a first length of the orthogonal projection of the third storage capacitor at the base, and a second length of the orthogonal projection of the second storage capacitor at the base is the same as a second length of the orthogonal projection of the third storage capacitor at the base.

8. 2. The display substrate of claim 1, further comprising: a light-emitting structure layer disposed on a side of the driving circuit layer away from the base, the light-emitting structure layer comprising a plurality of light-emitting units, the plurality of light-emitting units including at least a red light-emitting diode emitting red light, a green light-emitting diode emitting green light, and a blue light-emitting diode emitting blue light, the red light-emitting diode being connected to the first pixel driving circuit, the green light-emitting diode being connected to the second pixel driving circuit, and the blue light-emitting diode being connected to the third pixel driving circuit.

9. At least one circuit unit among the plurality of circuit units comprises a high-voltage connection line extending along a first direction and a high-voltage power supply line extending along a second direction, the high-voltage power supply line being connected to the high-voltage connection line through a via, forming a net-like communication structure for transmitting a high-voltage power supply signal, the first direction intersecting with the second direction, or 9. A display substrate according to claim 1, wherein at least one circuit unit among the plurality of circuit units comprises a low-voltage connecting line extending along a first direction and a low-voltage power supply line extending along a second direction, the low-voltage power supply line being connected to the low-voltage connecting line through a via, forming a net-like communication structure for transmitting a low-voltage power supply signal, and the first direction intersects with the second direction.

10. 10. The display substrate of claim 9, wherein the low-voltage power line includes a first low-voltage power line and a second low-voltage power line, the first low-voltage power line is connected to a red light emitting diode, and the second low-voltage power line is connected to a green light emitting diode and a blue light emitting diode.

11. At least one circuit unit includes a first low-voltage connecting line extending along the first direction, and the first low-voltage power supply line is connected to the first low-voltage connecting line through a via, forming a net-like communication structure for transmitting a first low-voltage power supply signal; or 11. The display substrate of claim 10, wherein at least one circuit unit includes a second low-voltage connecting line extending along the first direction, and the second low-voltage power supply line is connected to the second low-voltage connecting line through a via, forming a net-like communication structure for transmitting a second low-voltage power supply signal.

12. 9. The display substrate of claim 1, wherein at least one circuit unit comprises a high-frequency connecting line extending along a first direction and a high-frequency signal line extending along a second direction, the high-frequency signal line being connected to the high-frequency connecting line through a via, forming a net-like communication structure for transmitting high-frequency signals, and the first direction intersects with the second direction.

13. A display substrate as described in any one of claims 1 to 8, further comprising a detection circuit and a plurality of data signal lines, the data signal lines being connected to a pixel driving circuit, the detection circuit comprising at least a plurality of detection units and a plurality of transmission lines, the plurality of detection units being connected to corresponding ones of the plurality of data signal lines via the plurality of transmission lines, a shielding line being installed between at least one transmission line and an adjacent transmission line, and the shielding line being connected to a constant voltage signal line or a ground signal line.

14. the distance between at least one transmission line and an adjacent shield line is between 10 μm and 20 μm; or The display substrate according to claim 13 , wherein the transmission line and the shield line are disposed on the same layer.

15. A display device comprising the display substrate according to any one of claims 1 to 8.

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