LED constant-current driving chip and display system

Abstract

The invention provides an LED constant-current driving chip and a display system, and relates to the field of display. The LED constant current driving chip comprises a line feed signal generation module, a display data cache module, a display control module and a constant current driving module. The line feed signal generation module is used for resetting in response to the received frame synchronization signal, and counting or timing based on the frame synchronization signal and a line feed period so as to periodically output a line feed signal; the display data caching module is used for caching the input display data; the display control module is used for generating a PWM (Pulse Width Modulation) signal according to the line feed signal and the display data read from the display data cache module; and the constant current driving module outputs a constant current driving signal based on the PWM signal so as to drive a corresponding LED lamp bead to emit light. The LED constant-current driving chip provided by the invention can output the line feed signal under the condition of no ROW line, so that the wiring is simplified, and the port utilization rate is improved.

Description

Technical Field

[0001] This application relates to the display field, and more particularly to an LED constant current driving chip and display system. Background Technology

[0002] A typical LED display system generally includes a controller and multiple LED modules. The LED display refreshes line by line, and all LED constant current driver chips within the LED module require a unified line feed signal. The line feed signal is used to indicate when a line feed occurs; for example, whenever a line feed signal is detected (e.g., a rising edge), a new line is displayed.

[0003] In current display control systems, the controller and the LED constant current driver chip typically communicate via ROW lines to transmit line feed signals. Therefore, ROW lines are indispensable in related technologies. This makes the wiring scheme between the controller and the LED constant current driver chip relatively complex, and the LED constant current driver chip must be designed with corresponding ROW line communication ports to achieve this, which increases the chip cost. Summary of the Invention

[0004] The main purpose of this application is to provide an LED constant current driver chip and display system that can output line feed signals even without a ROW line, thereby simplifying wiring and improving port utilization.

[0005] In a first aspect, this application provides an LED constant current driving chip, which includes a line feed signal generation module, a display data buffer module, a display control module, and a constant current driving module;

[0006] The line feed signal generation module is reset in response to the received frame synchronization signal, and counts or times based on the frame synchronization signal and the line feed cycle to periodically output the line feed signal.

[0007] The display data caching module is used to cache the input display data;

[0008] The display control module is used to generate a PWM signal based on the line feed signal and the display data read from the display data cache module;

[0009] The constant current drive module outputs a constant current drive signal based on the PWM signal to drive the corresponding LED beads to emit light.

[0010] Secondly, this application provides a display device, which includes a controller and an LED constant current driving chip as described above.

[0011] This application provides an LED constant current driver chip and a display system. The LED constant current driver chip includes a line feed signal generation module, a display data buffer module, a display control module, and a constant current drive module. The line feed signal generation module is reset in response to a received frame synchronization signal and counts or times based on the frame synchronization signal and the line feed cycle to periodically output a line feed signal. The display data buffer module is used to buffer the input display data. The display control module is used to generate a PWM signal based on the line feed signal and the display data read from the display data buffer module. The constant current drive module outputs a constant current drive signal based on the PWM signal to drive the corresponding LED beads to emit light. Therefore, the LED constant current driver chip provided in this application can count or time based on the received frame synchronization signal and the preset line feed cycle through the line feed signal generation module, thereby periodically outputting line feed signals without the need to use ROW lines to transmit line feed signals. This enables the output of line feed signals even without ROW lines, effectively reducing the number of signal lines such as ROW lines, simplifying wiring and routing, and reducing the number of ports occupied by the LED constant current driver chip, thereby improving port utilization and saving chip costs. Attached Figure Description

[0012] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of the structure of a display system provided by related technologies;

[0014] Figure 2 This is a schematic diagram of the signal waveform of an LED constant current driver chip provided by related technologies;

[0015] Figure 3 This is a schematic block diagram of the structure of an LED constant current driver chip provided in an embodiment of this application;

[0016] Figure 4 This is a schematic diagram of the structure of an LED constant current driving chip provided in an embodiment of this application;

[0017] Figure 5 This is a schematic diagram of another LED constant current driver chip provided in the embodiments of this application;

[0018] Figure 6 This is a schematic diagram of the structure of a display system provided in an embodiment of this application;

[0019] Figure 7This is a schematic diagram of another LED constant current driver chip provided in the embodiments of this application;

[0020] Figure 8 This is a schematic diagram of the signal waveform of an LED constant current driver chip provided in an embodiment of this application;

[0021] Figure 9 This is a schematic diagram of another LED constant current driver chip provided in the embodiments of this application;

[0022] Figure 10(a) is a schematic diagram of the signal waveform of another LED constant current driving chip provided in the embodiment of this application;

[0023] Figure 10(b) is a schematic diagram of the data transmission format of an LED constant current driver chip provided in an embodiment of this application;

[0024] Figure 11 This is a schematic diagram of another LED constant current driver chip provided in the embodiments of this application;

[0025] Figure 12 This is a schematic diagram of another LED constant current driver chip provided in the embodiments of this application;

[0026] Figure 13 This is a schematic diagram of another LED constant current driver chip provided in the embodiments of this application;

[0027] Figure 14 This is a schematic diagram of another LED constant current driver chip provided in the embodiments of this application;

[0028] Figure 15 This is a schematic diagram of another LED constant current driver chip provided in the embodiments of this application;

[0029] Figure 16 This is a schematic diagram of another LED constant current driver chip provided in the embodiments of this application;

[0030] Figure 17 This is a schematic block diagram of a display system provided in an embodiment of this application. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0033] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0034] It should be understood that, in order to clearly describe the technical solutions of the embodiments of this application, the terms "first" and "second" are used in the embodiments of this application to distinguish identical or similar items with essentially the same function and effect. For example, the first callback function and the second callback function are only used to distinguish different callback functions and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" do not necessarily mean they must be different.

[0035] It should also be understood that the term "and / or" as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0036] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0037] Before introducing the LED constant current driving chip and display system provided in this application, let's first introduce the LED constant current driving chip in related technologies.

[0038] A typical LED display system generally includes a controller and multiple LED modules, with each LED module containing one or more LED constant current driver chips.

[0039] Currently, controllers and LED constant current driver chips typically use a four-wire connection: SDI line, CLK line, LE line, and ROW line. The connection method is as follows: Figure 1 As shown, the controller sends display data and control information signals to the LED constant current driver chip via the above four signal lines.

[0040] Since LED displays refresh line by line, all LED constant current driver chips within the LED module require a unified line feed signal. The ROW line is used to transmit the line feed signal to indicate when a line feed occurs; whenever a line feed signal is detected (e.g., a rising edge), a new line begins to be displayed.

[0041] Because LED constant current driver chips need to transmit some control commands, such as when to latch data and when to switch a frame of the display, an LE line is needed to transmit the command information.

[0042] The LED constant current driver chip transmits the data input from the SDI line to the next LED constant current driver chip through the SDO port. Multiple LED constant current driver chips are connected in series. Under the action of the command signal transmitted through the LE line, each LED constant current driver chip obtains its own display data and configuration information.

[0043] Therefore, in related technologies, the SDI line is used to transmit display data, the CLK line is used to transmit clock signals, the LE line is used to transmit command signals, and the ROW line is used to transmit line feed signals. For LED constant current driver chips, each signal is essential.

[0044] However, the four-wire method is more complex, and more and more customers are requesting simplified wiring as much as possible. Furthermore, the LE and ROW lines operate independently, both frequently sending signals, which can overlap in timing, such as... Figure 2 As shown in the red box, these two signal lines cannot be simply merged.

[0045] To address the aforementioned issues, this application provides an LED constant current driver chip and display system. The chip uses a line feed signal generation module to count or time based on the received frame synchronization signal and a preset line feed cycle, thereby periodically outputting line feed signals. This eliminates the need for ROW lines to transmit line feed signals, enabling line feed signal output even without ROW lines. This effectively reduces the number of signal lines such as ROW lines, simplifies wiring and cabling, reduces the number of ports occupied by the LED constant current driver chip, improves port utilization, and saves chip costs.

[0046] like Figure 3 As shown, the LED constant current driver chip 100 includes a line feed signal generation module 10, a display data buffer module 20, a display control module 30, and a constant current driver module 40.

[0047] The line feed signal generation module 10 is reset in response to the received frame synchronization signal, and counts or times based on the frame synchronization signal and the line feed cycle to periodically output the line feed signal.

[0048] For example, the controller can send a signal to the LED constant current driver chip 100, which parses the received signal to obtain a frame synchronization signal, so that the line feed signal generation module 10 can receive the frame synchronization signal. The line feed signal generation module 10 in this embodiment can receive the frame synchronization signal in any manner, and no specific limitation is made here.

[0049] For example, after receiving the frame synchronization signal, the line feed signal generation module 10 is reset and starts counting or timing. When the count value or timing value meets the corresponding conditions, it outputs a line feed signal. After receiving the frame synchronization signal again, it is reset again and the above process is repeated to achieve the effect of periodically outputting line feed signals.

[0050] It should be noted that the line break cycle can be preset or adjusted according to actual display requirements; no specific limitation is made here.

[0051] The display data cache module 20 caches the input display data, allowing the display control module 30 to quickly read the corresponding display data. The display control module 30 generates a PWM signal based on the line feed signal and the display data read from the display data cache module 20. Specifically, the display control module 30 determines when to perform a line feed based on the line feed signal, reads the corresponding display data from the data cache module 20, and outputs the PWM signal according to a specific display algorithm. The constant current drive module 40 outputs a constant current drive signal based on the PWM signal to drive the corresponding LED beads to emit light.

[0052] Therefore, the LED constant current driver chip 100 provided in this application can periodically generate and output a line feed signal without using a ROW line to transmit the line feed signal. This enables the output of a line feed signal even without a ROW line, thereby effectively reducing the number of signal lines such as ROW lines, simplifying wiring and routing, and reducing the number of ports occupied by the LED constant current driver chip 100, thereby improving port utilization and saving chip costs.

[0053] like Figure 4 As shown, in some embodiments, the line feed cycle is the line counting cycle; the line feed signal generation module 10 includes a counter 11 and a line counting cycle module 12. The counter 11 is reset in response to the received frame synchronization signal and counts cyclically according to the line counting cycle. When the count value reaches the line counting cycle, a line feed signal is output; the line counting cycle module 12 is used to provide the line counting cycle to the counter 11.

[0054] Specifically, the line counting cycle module 12 can obtain the line counting cycle corresponding to the LED constant current driver chip 100. This line counting cycle can be preset or obtained through calculation, and no specific limitation is made here. When the line feed signal generation module 10 is working, the line counting cycle module 12 provides the line counting cycle to the counter 11. The counter 11 is reset in response to the received frame synchronization signal and counts cyclically according to the line counting cycle. Whenever the count value reaches the line counting cycle, a line feed signal is output. That is, whenever the count value is full for one line counting cycle, a line feed signal is output.

[0055] For example, taking a line counting period of 10 as an example, after receiving the frame synchronization signal, the counter 11 will reset its count value to 0 and start counting. When the count value reaches 10, it will output a line feed signal and continue counting. When the count value reaches 20, it will output a line feed signal again and continue counting. When the count value reaches 30, it will output a line feed signal again. That is, a line feed signal will be output whenever the count value reaches an integer multiple of 10, until the counter 11 receives the frame synchronization signal again, resets the count value, and repeats the above counting process to achieve the effect of periodically outputting a line feed signal.

[0056] like Figure 5 As shown, in some embodiments, the line feed cycle is a line timing cycle; the line feed signal generation module 10 includes a timer 13 and a line timing cycle module 14. The timer 13 is reset in response to the received frame synchronization signal and cycles according to the line timing cycle. When the timing value reaches the line timing cycle, it outputs a line feed signal; the line timing cycle module 14 is used to provide the timer 13 with the line timing cycle.

[0057] Specifically, the line timing cycle module 14 can obtain the line timing cycle corresponding to the LED constant current driver chip 100. This line timing cycle can be preset or obtained through calculation, and no specific limitation is made here. When the line feed signal generation module 10 is working, the line timing cycle module 14 provides the line timing cycle to the timer 13. The timer 13 is reset in response to the received frame synchronization signal and cycles according to the line timing cycle. Whenever the timing value reaches the line timing cycle, a line feed signal is output.

[0058] For example, taking a timing value of 8 seconds corresponding to the line timing cycle as an example, after receiving the frame synchronization signal, the timer 13 will reset its timing value to 0. When the timing value reaches 8 seconds, it will output a line feed signal and continue timing. When the timing value reaches 16 seconds, it will output a line feed signal again and continue timing. When the timing value reaches 24 seconds, it will output a line feed signal again. That is, a line feed signal will be output whenever the timing value reaches an integer multiple of 8 seconds, until the timer 13 receives the frame synchronization signal again, resets the timing value, and repeats the above timing process to achieve the effect of periodically outputting a line feed signal.

[0059] In some embodiments, the line feed cycle is obtained based on the display refresh rate configuration of the LED constant current driver chip.

[0060] Specifically, the line feed cycle is determined by the line scan frequency, and the display refresh rate determines the line scan frequency. That is, the line scan frequency is determined according to the specific application scenario of the LED constant current driver chip 100. For example, in high refresh rate application scenarios, the line scan frequency is generally higher. Since the line feed cycle and the line scan frequency are negatively correlated, the line feed cycle will be smaller. Therefore, the count value or timing value corresponding to the line feed cycle will generally also be smaller.

[0061] It should be noted that the line break cycle is generally obtained based on the display refresh rate configuration of the LED constant current driver chip 100. Of course, it can also be obtained through any parameter configuration associated with the LED constant current driver chip 100, and no specific limitation is made here.

[0062] The following provides an example of the source of the frame synchronization signal, which can be implemented through different communication framework structures to simplify the aforementioned scheme of communication between the controller and the LED constant current driver chip, which relies on the SDI line, CLK line, LE line and ROW line, to 3 lines, 2 lines or even 1 line.

[0063] In one embodiment of the present invention, the frame synchronization signal is obtained by parsing the command signal. For example... Figure 4 As shown, the LED constant current driver chip 100 also includes an instruction parsing module 50. The instruction parsing module 50 is used to parse the received instruction signal according to the different durations of the effective level to obtain the frame synchronization signal. The effective level durations of different instruction signals are different.

[0064] The effective level can be either high or low; no specific limitation is made here.

[0065] Specifically, the instruction parsing module 50 can receive instruction signals and parse the received instruction signals according to the different durations of the effective level to obtain different control signals.

[0066] The following is an example of an effective high level.

[0067] For example, the instruction parsing module 50 is used to parse the received instruction signal and can distinguish different instructions based on the duration of the high level, as shown in Table 1.

[0068] Table 1

[0069]

[0070]

[0071] In this embodiment, the VSYNC signal is a frame synchronization signal used to indicate frame changes and also enables the display control module to read the display data of the next frame from the display data cache module. The line feed signal generation module 10 is reset according to the VSYNC signal and counts or times based on the frame synchronization signal and the line feed cycle to periodically output the line feed signal.

[0072] Different command signals have different effective level durations. For example, taking Table 1 as an example, the command parsing module 50 parses the received command signal and finds that the effective level duration of the command signal is 3 clock cycles. Therefore, it can be determined that the received command signal is a VSYNC signal, i.e., a frame synchronization signal.

[0073] The following describes various embodiments of the LED constant current driver chip 100, which includes an instruction parsing module 50 and is used to parse and obtain a frame synchronization signal.

[0074] like Figures 4-6 As shown, in some embodiments, the LED constant current driver chip 100 further includes an instruction communication terminal, a clock communication terminal, and a data communication terminal; the instruction communication terminal is used to receive instruction signals; the clock communication terminal is used to receive clock signals; and the data communication terminal is used to receive display data.

[0075] For example, after receiving the command signal sent by the controller 200, the command communication terminal transmits the command signal to the command parsing module 50. Specifically, the command parsing module 50 can parse the high and low levels of the received command signal using a clock signal to determine the frame synchronization signal based on the different durations of the effective level of different command signals. The frame synchronization signal is then transmitted to the line feed signal generation module 10. The line feed signal generation module 10 is reset in response to the received frame synchronization signal and counts or times based on the frame synchronization signal and the line feed cycle to periodically output the line feed signal. At the same time, the display data buffer module 20 buffers the display data received by the data communication terminal. The line feed signal generation module 10 and the display data buffer module 20 transmit the line feed signal and display data to the display control module 30 so that the display control module 30 generates a PWM signal.

[0076] It should be noted that the command signal in this embodiment is received from the command communication terminal, and the frame synchronization signal is obtained by parsing the received command signal; that is, the frame synchronization signal is essentially a command signal. Therefore, the LED constant current driver chip 100 provided in this embodiment includes a command communication terminal, a data communication terminal, and a clock communication terminal. The output line feed signal is achieved through the CLK line, SDI line, and LE line, thereby effectively reducing the number of signal lines such as ROW lines, simplifying wiring and routing, and reducing the number of ports occupied by the LED constant current driver chip 100, thus improving port utilization.

[0077] like Figure 7 As shown, in some embodiments, the LED constant current driver chip 100 further includes a data communication terminal, a clock communication terminal, and a clock parsing module 60; the data communication terminal is used to receive display data; the clock communication terminal is used to receive clock signals and command signals, wherein the clock signals and command signals have different duty cycles; the clock parsing module 60 is used to parse the signals received by the clock communication terminal according to the different duty cycles to obtain clock signals and command signals.

[0078] In the embodiments of this application, both the clock signal and the command signal are received through the clock communication terminal. That is, the signal received by the clock communication terminal may be a clock signal or a command signal.

[0079] For example, the clock communication terminal receives a signal sent by the controller 200 and transmits the signal to the clock analysis module 60. Specifically, the clock analysis module 60 can analyze the duty cycle of the received signal to determine whether it is a clock signal or a command signal based on the different duty cycles of the clock signal and the command signal. The corresponding signal waveform is shown in the figure below. Figure 8 As shown, in Figure 8 In the diagram, the signals received by the clock communication terminal include clock signals and command signals. The black signals in the diagram are clock signals, and the red signals are command signals. The duty cycles of the two signals are different.

[0080] For example, assuming the high-level duty cycle of the clock signal is 1 / 3 and the high-level duty cycle of the instruction signal is 2 / 3, if the clock parsing module 60 parses the high-level duty cycle of the signal received by the clock communication terminal as 1 / 3, then the signal is determined to be a clock signal; if the clock parsing module 60 parses the high-level duty cycle of the signal received by the clock communication terminal as 2 / 3, then the signal is determined to be an instruction signal. Different instruction signals have different high-level durations. For example, if three consecutive high-level duty cycles of 2 / 3 appear, the signal can be determined to be a frame synchronization signal; if five consecutive high-level duty cycles of 2 / 3 appear, the signal can be determined to be the instruction signal WR CFG indicating a write register.

[0081] It should be noted that the duty cycle of the clock signal and the command signal can be a specific value or a specific range of values, as long as the duty cycles of the two are different. It can be set according to the actual situation, and no specific limitation is made here.

[0082] For example, the clock parsing module 60 parses the signal received from the clock communication terminal to obtain the clock signal and the command signal, and then transmits the command signal to the command parsing module 50. The command parsing module 50 parses the command signal according to the different durations of the effective level to obtain the frame synchronization signal, and transmits the frame synchronization signal to the line feed signal generation module 10. The line feed signal generation module 10 is reset in response to the received frame synchronization signal, and counts or times based on the frame synchronization signal and the line feed cycle to periodically output the line feed signal. At the same time, the display data buffer module 20 buffers the display data received from the data communication terminal. The line feed signal generation module 10 and the display data buffer module 20 transmit the line feed signal and the display data to the display control module 30 so that the display control module 30 generates a PWM signal.

[0083] It should be noted that the command signal in this embodiment is received from the clock communication terminal, and the frame synchronization signal is obtained by parsing the received command signal. Therefore, the LED constant current driver chip 100 provided in this embodiment includes a data communication terminal and a clock communication terminal, that is, the output line feed signal is realized through the CLK line and SDI line, thereby effectively reducing the number of signal lines such as ROW lines, simplifying the wiring and routing, and reducing the number of ports occupied by the LED constant current driver chip 100, thereby improving the port utilization rate.

[0084] like Figure 9 As shown, in some embodiments, the LED constant current driver chip 100 further includes a clock communication terminal, a data communication terminal, and a data parsing module 70; the clock communication terminal is used to receive clock signals; the data communication terminal is used to receive display data and instruction signals, wherein the display data and instruction signals have different data formats; the data parsing module 70 is used to parse the signals received by the data communication terminal according to the different data formats or different data packet formats to obtain display data and instruction signals.

[0085] In the embodiments of this application, both display data and command signals are received through a data communication terminal. That is, the data communication terminal may receive either display data or command signals.

[0086] For example, the data communication terminal receives a signal sent by the controller 200 and transmits the signal to the data parsing module 70. Specifically, the data parsing module 70 can parse the data format or data packet format of the received signal to determine whether the signal is display data or instruction signal based on the different data formats or data packet formats of display data and instruction signals.

[0087] The following explanation uses the data parsing module 70 as an example to illustrate how it determines the display data or instruction signal by parsing the data format of the received signal.

[0088] The data format corresponding to the displayed data and command signals can be set according to the duty cycle of the signal. The following is an explanation using a specific embodiment.

[0089] For example, analyzing the signals received by the data communication terminal, if the signal's data format consists of 30% high level and 70% low level, it indicates low-level display data; if it consists of 70% high level and 30% low level, it indicates high-level display data; if it consists of 10% high level and 90% low level, it indicates low-level command signal; and if it consists of 90% high level and 10% low level, it indicates high-level command signal. Therefore, the duty cycles of display data and command signals are different, meaning their data formats are different. The corresponding signal waveforms are shown in Figure 10(a). In Figure 10(a), the signals received by the data communication terminal include display data and command signals. The black signal represents display data, and the red signal represents command signals. Their duty cycles are different, indicating different data formats.

[0090] It should be noted that the duty cycle of the displayed data and the command signal can be a specific value or a specific range of values, as long as the duty cycles of the two are different. It can be set according to the actual situation, and no specific limitation is made here.

[0091] The following explanation uses the example of the data parsing module 70 determining the display data or instruction signal by parsing the data format packet of the received signal.

[0092] For example, when parsing the signal received by the data communication terminal, if the data packet format corresponding to the signal is: packet header + DATA data + packet tail, then the signal can be considered as display data; if the data packet format corresponding to the signal is: packet header + identifier + CMD data + packet tail, then the signal can be considered as an instruction signal.

[0093] In Figure 10(b), since the display data and command signals are set to different data packet formats, this feature can be used to integrate the command signals originally transmitted by the LE line with the display data originally transmitted by the SDI line, so that the new SDI line can transmit command signals and display data at the same time, and the subsequent data parsing module 70 can also easily distinguish between command signals and display data.

[0094] It should be noted that the data format corresponding to the display data and command signals can be any format, and the data packet format corresponding to the display data and command signals can also be any packet format, as long as the data format or arbitrary packet format of the two are different. It can be set according to the actual situation, and no specific limitation is made here.

[0095] For example, after the data parsing module 70 parses the signal received from the data communication terminal to obtain display data and instruction signals, it transmits the instruction signals to the instruction parsing module 50. The instruction parsing module 50 parses the instruction signals according to the different durations of the effective level to obtain frame synchronization signals, and transmits the frame synchronization signals to the line feed signal generation module 10. The line feed signal generation module 10 is reset in response to the received frame synchronization signals, and counts or times based on the frame synchronization signals and the line feed cycle to periodically output line feed signals. At the same time, the display data buffer module 20 buffers the display data received from the data communication terminal. The line feed signal generation module 10 and the display data buffer module 20 transmit line feed signals and display data to the display control module 30 so that the display control module 30 generates PWM signals.

[0096] It should be noted that the command signal in this embodiment is received from the data communication terminal, and the frame synchronization signal is obtained by parsing the received command signal. Therefore, the LED constant current driver chip 100 provided in this embodiment includes a data communication terminal and a clock communication terminal, that is, the output line feed signal is realized through the CLK line and SDI line, thereby effectively reducing the number of signal lines such as ROW lines, simplifying the wiring and routing, reducing the number of ports occupied by the LED constant current driver chip 100, and thus improving the port utilization rate.

[0097] like Figure 11 As shown, in some embodiments, the LED constant current driver chip 100 further includes a data communication terminal, a data parsing module 70, and a clock recovery module 80. The data communication terminal is used to receive display data and command signals, wherein the data format or data packet format of the display data and command signals is different; the data parsing module 70 is used to parse the signals received by the data communication terminal according to the different data format or data packet format to obtain the display data and command signals; the clock recovery module 80 is used to process the display data to obtain a clock signal.

[0098] In this embodiment of the application, both display data and command signals are received through a data communication terminal. That is, the data communication terminal may receive display data or command signals, while the clock signal is obtained by processing the display data.

[0099] The embodiments of the data communication terminal and the data parsing module 70 have been described above and can be referred to the corresponding embodiments therein, and will not be repeated here. Specific embodiments of the clock recovery module 80 can be found in the prior art and will not be described in detail here.

[0100] In this embodiment, the command signal is received from the data communication terminal, the frame synchronization signal is obtained by parsing the received command signal, and the clock signal is obtained by processing the display data. Therefore, the LED constant current driver chip 100 provided in this embodiment includes a data communication terminal, that is, the output line feed signal is realized through the SDI line, thereby effectively reducing the number of signal lines such as ROW lines, simplifying the wiring and routing, and reducing the number of ports occupied by the LED constant current driver chip 100, thereby improving the port utilization rate.

[0101] The following describes various embodiments of the LED constant current driver chip 100 that do not include the instruction parsing module 50 or where the instruction parsing module 50 is not used to parse and obtain the frame synchronization signal.

[0102] like Figure 12 and Figure 13 As shown, in some embodiments, the LED constant current driver chip 100 further includes a clock communication terminal and a clock parsing module 60. The clock communication terminal is used to receive clock signals and frame synchronization signals, wherein the clock signals and frame synchronization signals have different duty cycles. The clock parsing module 60 is used to parse the signals received by the clock communication terminal according to the different duty cycles to obtain clock signals and frame synchronization signals.

[0103] In the embodiments of this application, both the clock signal and the frame synchronization signal are received through the clock communication terminal. That is, the signal received by the clock communication terminal may be a clock signal or a frame synchronization signal.

[0104] For example, the clock communication terminal receives a signal sent by the controller 200 and transmits the signal to the clock parsing module 60. Specifically, the clock parsing module 60 can parse the duty cycle of the received signal to determine whether the signal is a clock signal or a frame synchronization signal based on the different duty cycles of the clock signal and the instruction signal.

[0105] For example, assuming the high-level duty cycle of the clock signal is 1 / 4 and the high-level duty cycle of the frame synchronization signal is 3 / 4, if the clock parsing module 60 parses the high-level duty cycle of the signal received by the clock communication terminal as 1 / 4, then the signal is determined to be a clock signal; if the clock parsing module 60 parses the high-level duty cycle of the signal received by the clock communication terminal as 3 / 4, then the signal is determined to be a frame synchronization signal.

[0106] It should be noted that the duty cycle of the clock signal and the frame synchronization signal can be a specific value or a specific range of values, as long as the duty cycles of the two are different. It can be set according to the actual situation, and no specific limitation is made here.

[0107] For example, the clock parsing module 60 parses the signal received by the clock communication terminal to obtain the clock signal and the frame synchronization signal, and then transmits the frame synchronization signal to the line feed signal generation module 10. The line feed signal generation module 10 is reset in response to the received frame synchronization signal, and counts or times based on the frame synchronization signal and the line feed cycle to periodically output the line feed signal.

[0108] like Figure 12 As shown, in some embodiments, the LED constant current driver chip 100 further includes an instruction communication terminal and a data communication terminal; the instruction communication terminal is used to receive instruction signals; and the data communication terminal is used to receive display data.

[0109] In this embodiment, the command signal is received from the command communication terminal, and the frame synchronization signal is received from the clock communication terminal. Therefore, the LED constant current driver chip 100 provided in this embodiment includes a command communication terminal, a data communication terminal, and a clock communication terminal. That is, the output line feed signal is realized through the CLK line, SDI line, and LE line, thereby effectively reducing the number of signal lines such as ROW lines, simplifying the wiring and routing, and reducing the number of ports occupied by the LED constant current driver chip 100, thereby improving the port utilization rate.

[0110] like Figure 13 As shown, in some embodiments, the LED constant current driver chip 100 further includes a data communication terminal and a data parsing module 70; the data communication terminal is used to receive display data and instruction signals, wherein the data formats of the display data and instruction signals are different or the data packet formats are different; the data parsing module 70 is used to parse the signals received by the data communication terminal according to the different data formats or data packet formats to obtain the display data and instruction signals.

[0111] The relevant embodiments of the data communication terminal and the data parsing module 70 have been described above, and can be referred to the corresponding embodiments above, and will not be repeated here.

[0112] In this embodiment, the command signal is received from the data communication terminal, and the frame synchronization signal is received from the clock communication terminal. Therefore, the LED constant current driver chip 100 provided in this embodiment includes a data communication terminal and a clock communication terminal, that is, the output line feed signal is realized through the CLK line and SDI line, thereby effectively reducing the number of signal lines such as ROW lines, simplifying the wiring and routing, and reducing the number of ports occupied by the LED constant current driver chip 100, thereby improving the port utilization rate.

[0113] like Figures 14-16 As shown, in some embodiments, the LED constant current driver chip 100 further includes a data communication terminal and a data parsing module 70. The data communication terminal is used to receive display data and frame synchronization signals, wherein the data formats of the display data and frame synchronization signals are different or the data packet formats are different; the data parsing module 70 is used to parse the signals received by the data communication terminal according to the different data formats or data packet formats to obtain the display data and frame synchronization signals.

[0114] In the embodiments of this application, both the display data and the frame synchronization signal are received through the data communication terminal. That is, the data communication terminal may receive either the display data or the frame synchronization signal.

[0115] For example, the data communication terminal receives a signal sent by the controller 200 and transmits the signal to the data parsing module 70. Specifically, the data parsing module 70 can parse the data format or data packet format of the received signal to determine whether the signal is display data or frame synchronization signal based on the different data formats or data packet formats of display data and frame synchronization signal.

[0116] For example, when analyzing the signal received by the data communication terminal, if the data format of the signal is composed of 40% high level and 60% low level, it can be indicated that the signal is low-level display data; if the data format of the signal is composed of 60% high level and 40% low level, it can be indicated that the signal is high-level display data; if the data format of the signal is composed of 15% high level and 85% low level, it can be indicated that the signal is low-level frame synchronization signal; if the data format of the signal is composed of 85% high level and 15% low level, it can be indicated that the signal is high-level frame synchronization signal. Therefore, the duty cycle of the display data and the frame synchronization signal are different, that is, the data formats are different.

[0117] For example, when parsing the signal received by the data communication terminal, if the data packet format corresponding to the signal is: packet header + DATA data + packet trailer, then the signal can be considered as display data; if the data packet format corresponding to the signal is: packet header + identifier + CMD data + packet trailer, then the signal can be considered as a frame synchronization signal.

[0118] For example, after the data parsing module 70 parses the signal received by the data communication terminal to obtain the display data and the frame synchronization signal, it transmits the frame synchronization signal to the line feed signal generation module 10. The line feed signal generation module 10 is reset in response to the received frame synchronization signal and counts or times based on the frame synchronization signal and the line feed cycle to periodically output the line feed signal.

[0119] like Figure 14 As shown, in some embodiments, the LED constant current driver chip 100 further includes an instruction communication terminal and a clock communication terminal; the instruction communication terminal is used to receive instruction signals; and the clock communication terminal is used to receive clock signals.

[0120] In this embodiment, the command signal is received from the command communication terminal, and the frame synchronization signal is received from the data communication terminal. Therefore, the LED constant current driver chip 100 provided in this embodiment includes a command communication terminal, a data communication terminal, and a clock communication terminal. That is, the output line feed signal is realized through the CLK line, SDI line, and LE line, thereby effectively reducing the number of signal lines such as ROW lines, simplifying wiring and routing, and reducing the number of ports occupied by the LED constant current driver chip 100, thereby improving port utilization.

[0121] like Figure 15 As shown, in some embodiments, the LED constant current driver chip 100 further includes a clock communication terminal and a clock parsing module 60; the clock communication terminal is used to receive clock signals and command signals, wherein the clock signals and command signals have different duty cycles; the clock parsing module 60 is used to parse the signals received by the clock communication terminal according to the different duty cycles to obtain clock signals and command signals.

[0122] The relevant embodiments of the clock communication terminal and the clock parsing module 60 have been described above, and can be referred to the corresponding embodiments above. They will not be repeated here.

[0123] In this embodiment, the command signal is received from the clock communication terminal, and the frame synchronization signal is received from the data communication terminal. Therefore, the LED constant current driver chip 100 provided in this embodiment includes a data communication terminal and a clock communication terminal, that is, the output line feed signal is realized through the CLK line and SDI line, thereby effectively reducing the number of signal lines such as ROW lines, simplifying the wiring and routing, and reducing the number of ports occupied by the LED constant current driver chip 100, thereby improving port utilization and saving chip costs.

[0124] like Figure 16 As shown, in some embodiments, the LED constant current driver chip 100 further includes an instruction communication terminal and a clock recovery module 80; the instruction communication terminal is used to receive instruction signals; the clock recovery module 80 is used to process the display data to obtain a clock signal.

[0125] The specific embodiments of the clock recovery module 80 can be found in the prior art and will not be described in detail in this article.

[0126] In this embodiment, the command signal is received from the command communication terminal, the frame synchronization signal is received from the data communication terminal, and the clock signal is obtained by processing the display data. Therefore, the LED constant current driver chip 100 provided in this embodiment includes a data communication terminal and a command communication terminal, that is, the output line feed signal is realized through the LE line and SDI line, thereby effectively reducing the number of signal lines such as ROW lines, simplifying the wiring and routing, and reducing the number of ports occupied by the LED constant current driver chip 100, thereby improving the port utilization rate.

[0127] like Figure 17 As shown, this application also provides a display system 1000, which includes a controller 200 and an LED constant current drive chip 100 as described above.

[0128] The controller 200 can send one or more of the following to the LED constant current driver chip 100: instruction signal, clock signal, display data, and frame synchronization signal. Relevant embodiments of the LED constant current driver chip 100 have been described above and will not be repeated here. The display system 1000 provided in this application eliminates the need for ROW lines to transmit line feed signals, enabling line feed signal output even without ROW lines. This effectively reduces the number of signal lines such as ROW lines, simplifies wiring and cabling, and reduces the number of ports occupied by the LED constant current driver chip 100, thereby improving port utilization and saving chip costs.

[0129] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection. They can refer to a mechanical connection or an electrical connection. They can refer to a direct connection or an indirect connection through an intermediate medium, and they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in this application can be understood according to the specific circumstances.

[0130] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0131] The foregoing disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described above. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0132] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0133] The above embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of protection of this application. Any non-substantial changes and substitutions made by those skilled in the art based on this application shall fall within the scope of protection claimed by this application.

Claims

1. An LED constant current driver chip, characterized in that, include: The line feed signal generation module is reset in response to the received frame synchronization signal, and counts or times based on the frame synchronization signal and the line feed cycle to periodically output the line feed signal. The display data caching module is used to cache the input display data; The display control module is used to generate a PWM signal based on the line feed signal and the display data read from the display data cache module; The constant current drive module outputs a constant current drive signal based on the PWM signal to drive the corresponding LED beads to emit light.

2. The LED constant current driver chip according to claim 1, characterized in that, The line feed cycle is a line counting cycle; the line feed signal generation module includes: The counter is reset in response to the received frame synchronization signal and counts cyclically according to the line counting cycle. Whenever the count value reaches the line counting cycle, the newline signal is output. A row counting cycle module is used to provide the row counting cycle to the counter; or, The line feed cycle is a line timing cycle; the line feed signal generation module includes: The timer is reset in response to the received frame synchronization signal and cycles according to the line timing period. Whenever the timing value reaches the line timing period, the line feed signal is output. The row timing cycle module is used to provide the row timing cycle to the timer.

3. The LED constant current driver chip according to claim 1 or 2, characterized in that, The line feed cycle is obtained based on the display refresh rate configuration of the LED constant current driver chip.

4. The LED constant current driver chip according to claim 1, characterized in that, The LED constant current driver chip also includes: The instruction parsing module is used to parse the received instruction signals according to the different durations of the effective level to obtain the frame synchronization signal, wherein the effective level durations of different instruction signals are different.

5. The LED constant current driver chip according to claim 4, characterized in that, The LED constant current driver chip also includes: an instruction communication terminal, a clock communication terminal, and a data communication terminal; The instruction communication terminal is used to receive the instruction signal; The clock communication terminal is used to receive clock signals; The data communication terminal is used to receive the display data; or, The LED constant current driver chip also includes: a data communication terminal, a clock communication terminal, and a clock parsing module; The data communication terminal is used to receive the display data; The clock communication terminal is used to receive clock signals and command signals, wherein the clock signals and command signals have different duty cycles. The clock parsing module is used to parse the signals received by the clock communication terminal according to different duty cycles to obtain the clock signal and the command signal; or, The LED constant current driver chip also includes: a clock communication terminal, a data communication terminal, and a data parsing module; The clock communication terminal is used to receive the clock signal; The data communication terminal is used to receive the display data and the instruction signal, wherein the display data and the instruction signal have different data formats or different data packet formats; The data parsing module is used to parse the signals received by the data communication terminal according to different data formats or different data packet formats to obtain the display data and the instruction signal; or, The LED constant current driver chip also includes: a data communication terminal, a data parsing module, and a clock recovery module; The data communication terminal is used to receive the display data and the instruction signal, wherein the display data and the instruction signal have different data formats or different data packet formats; The data parsing module is used to parse the signals received by the data communication terminal according to different data formats or different data packet formats to obtain the display data and the instruction signal; The clock recovery module is used to process the display data to obtain a clock signal.

6. The LED constant current driver chip according to claim 1, characterized in that, The LED constant current driver chip also includes: A clock communication terminal is used to receive a clock signal and the frame synchronization signal, wherein the clock signal and the frame synchronization signal have different duty cycles. The clock parsing module is used to parse the signals received by the clock communication terminal according to different duty cycles to obtain the clock signal and the frame synchronization signal.

7. The LED constant current driver chip according to claim 6, characterized in that, The LED constant current driver chip also includes: an instruction communication terminal and a data communication terminal; The command communication terminal is used to receive command signals; The data communication terminal is used to receive the display data; or, The LED constant current driver chip also includes: a data communication terminal and a data parsing module; The data communication terminal is used to receive the display data and the instruction signal, wherein the display data and the instruction signal have different data formats or different data packet formats; The data parsing module is used to parse the signals received by the data communication terminal according to different data formats or different data packet formats, so as to obtain the display data and the instruction signal.

8. The LED constant current driver chip according to claim 1, characterized in that, The LED constant current driver chip also includes: A data communication terminal is used to receive display data and the frame synchronization signal, wherein the display data and the frame synchronization signal have different data formats or different data packet formats; The data parsing module is used to parse the signals received by the data communication terminal according to different data formats or data packet formats, so as to obtain the display data and the frame synchronization signal.

9. The LED constant current driver chip according to claim 8, characterized in that, The LED constant current driver chip also includes: an instruction communication terminal and a clock communication terminal; The command communication terminal is used to receive command signals; The clock communication terminal is used to receive clock signals; or, The LED constant current driver chip also includes: a clock communication terminal and a clock parsing module; The clock communication terminal is used to receive clock signals and command signals, wherein the clock signals and command signals have different duty cycles. The clock parsing module is used to parse the signals received by the clock communication terminal according to different duty cycles to obtain the clock signal and the command signal; or, The LED constant current driver chip also includes: an instruction communication terminal and a clock recovery module; The command communication terminal is used to receive command signals; The clock recovery module is used to process the display data to obtain a clock signal.

10. A display system, characterized in that, include: The controller and the LED constant current drive chip as described in any one of claims 1-9.

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