Video data processing method and device, display device and storage medium

Abstract

A video data processing method, a video data processing device, a display device, and a storage medium. The method includes a step (S101) of determining that a current video block of a video is to be encoded and decoded using a first intra-prediction mode, and a step (S102) of performing conversion between the current video block and a video bitstream based on the determination. In the first intra-prediction mode, the reference pixels used by the current video block exclude pixels of the neighboring block to the upper right of the current video block. This method allows the bitstream to be partially decoded based on the area that actually needs to be displayed, thereby reducing the consumption of decoding resources for the portion not being displayed and improving encoding and decoding efficiency.

Description

[Technical Field]

[0001] SUMMARY OF THE INVENTION The embodiments of the present disclosure relate to a video data processing method and apparatus, a display device, and a computer-readable storage medium. [Background technology]

[0002] Digital video capabilities can be incorporated into a variety of devices, including digital televisions, digital live streaming systems, wireless broadcasting systems, portable or desktop personal computers, tablet computers, e-readers, digital cameras, digital recording devices, digital media players, video game devices, video game consoles, smartphones, video teleconferencing equipment, and video streaming devices. Digital video devices can implement video encoding and decoding technologies, such as those described in standards defined by MPEG-2, MPEG-4, ITU-T H.263, ITU-T H.264 / MPEG-4, Part 10, Advanced Video Coding and Decoding (AVC), High Efficiency Video Coding and Decoding (HEVC), ITU-T H.265 / High Efficiency Video Coding and Decoding, and extensions to such standards. By implementing these video encoding and decoding technologies, video devices can more efficiently transmit, receive, encode, decode, and / or store digital video information. Summary of the Invention [Means for solving the problem]

[0003] At least one embodiment of the present disclosure provides a video data processing method, including: determining to encode and decode a current video block of a video using a first intra-prediction mode; and performing conversion between the current video block and a bitstream of the video based on the determination, wherein in the first intra-prediction mode, reference pixels used by the current video block exclude pixels of a neighboring block to the upper right of the current video block.

[0004] For example, in at least one embodiment of the present disclosure, in the first intra-prediction mode, reference pixels for the current video block are determined based on the availability of a first neighboring block of the current video block.

[0005] For example, in at least one embodiment of the present disclosure, determining reference pixels for the current video block based on the availability of a first neighboring block of the current video block includes determining the availability of the first neighboring block based on a position of the first neighboring block and a position of the current video block.

[0006] For example, in at least one embodiment of the present disclosure, determining the availability of the first neighboring block based on the position of the first neighboring block and the position of the current video block includes determining that the first neighboring block is unavailable in response to the first neighboring block being located to the upper right side of the current video block.

[0007] For example, in at least one embodiment of the present disclosure, determining reference pixels of the current video block based on the availability of the first neighboring block includes, in response to the first neighboring block being unavailable, determining pixel values ​​of the first neighboring block based on other neighboring blocks other than the first neighboring block of the current video block.

[0008] For example, in at least one embodiment of the present disclosure, determining pixel values ​​of the first neighboring block based on neighboring blocks other than the first neighboring block of the current video block includes determining pixel values ​​of the first neighboring block based on an upper left neighboring block and at least one upper neighboring block of the current video block.

[0009] For example, in at least one embodiment of the present disclosure, determining a pixel value of the first neighboring block based on an upper-left neighboring block and at least one upper neighboring block of the current video block includes, in response to satisfying a first condition, determining a pixel value of the first neighboring block based on a pixel value of a rightmost block of the at least one upper neighboring block and a pixel value of the upper-left neighboring block.

[0010] For example, in at least one embodiment of the present disclosure, the step of determining a pixel value of the first adjacent block based on a pixel value of the rightmost block of the at least one upper adjacent block and a pixel value of the upper-left adjacent block includes a step of performing linear interpolation using the pixel value of the rightmost block of the at least one upper adjacent block and the pixel value of the upper-left adjacent block to determine the pixel value of the first adjacent block.

[0011] For example, in at least one embodiment of the present disclosure, the first condition includes that the difference between the average value of the pixel values ​​of the upper left neighboring block and the rightmost block of the at least one upper neighboring block and the average value of the pixel values ​​of all blocks of the at least one upper neighboring block is less than a threshold.

[0012] For example, in at least one embodiment of the present disclosure, the threshold is equal to bitdepth / 2, where bitdepth represents the bit depth of the video.

[0013] For example, in at least one embodiment of the present disclosure, determining pixel values ​​of the first neighboring block based on an upper-left neighboring block of the current video block and the at least one upper neighboring block includes determining pixel values ​​of the first neighboring block based on pixel values ​​of the upper-left neighboring block in response to a first condition not being satisfied.

[0014] For example, in at least one embodiment of the present disclosure, the step of determining pixel values ​​of the first neighboring block based on pixel values ​​of the upper-left neighboring block includes the step of setting pixel values ​​of the first neighboring block equal to pixel values ​​of the upper-left neighboring block.

[0015] For example, in at least one embodiment of the present disclosure, the first intra prediction mode includes a planar intra prediction mode, a DC intra prediction mode, an angular intra prediction mode, or a multi-reference line intra prediction mode.

[0016] At least one embodiment of the present disclosure provides a video data processing method, including receiving a bitstream of video, determining that a current video block of the video is to be encoded and decoded using a first intra-prediction mode, and decoding the bitstream based on the determination, wherein in the first intra-prediction mode, reference pixels used by the current video block exclude pixels of a neighboring block to the upper right of the current video block.

[0017] For example, in at least one embodiment of the present disclosure, the step of decoding the bitstream includes, in response to a current video frame of the video including a first display partition to be displayed and a second display partition that does not need to be displayed, determining an area to be decoded that corresponds to the first display partition, and decoding the bitstream based on the area to be decoded.

[0018] For example, in at least one embodiment of the present disclosure, the step of determining the area to be decoded corresponding to the first display partition includes a step of determining the area to be decoded based on the encoding direction of the video, the partition direction between the first display partition and the second display partition, the number of pixels in the first display partition, and the size of the encoding unit of the video.

[0019] For example, in at least one embodiment of the present disclosure, the step of determining the area to be decoded based on the encoding direction, the partitioning direction, the number of pixels in the first display partition, and the size of the encoding unit includes a step of determining the number of encoding units for each line of the area to be decoded by applying a function to the ratio between the number of pixels in the first display partition and the size of the encoding unit in response to the video encoding direction being perpendicular to the partitioning direction.

[0020] For example, in at least one embodiment of the present disclosure, the step of determining the area to be decoded based on the encoding direction, the partitioning direction, the number of pixels in the first display partition, and the size of the encoding unit includes a step of determining the number of lines of the encoding-decoding unit of the area to be decoded by applying a function to the ratio between the number of pixels in the first display partition and the size of the encoding unit, in response to the encoding direction being parallel to the partitioning direction.

[0021] For example, in at least one embodiment of the present disclosure, the function is a round-up function.

[0022] For example, at least one embodiment of the present disclosure further provides a video data processing device, including: a determining module; and an executing module. The determining module is configured to determine to encode / decode a current video block of a video using a first intra-prediction mode. The executing module is configured to perform conversion between the current video block and a bitstream of the video based on the determination, wherein in the first intra-prediction mode, reference pixels used by the current video block exclude pixels of a neighboring block to the upper right of the current video block.

[0023] For example, at least one embodiment of the present disclosure further provides a display device, including a video data processing device and a roll-up display, wherein the video data processing device is configured to decode a received bitstream according to the method of the at least one embodiment, and transmit decoded pixel values ​​to the roll-up display for display.

[0024] For example, in at least one embodiment of the present disclosure, in response to the wrap-around display including a display area and a non-display area during operation, the video data processing device decodes the bitstream based on the size of the display area.

[0025] For example, in at least one embodiment of the present disclosure, the display device further includes a winding state determination device configured to detect a size of a display area of ​​the winding display and transmit the size of the display area to the video data processing device, so that the video data processing device decodes the bitstream based on the size of the display area.

[0026] For example, at least one embodiment of the present disclosure further provides a video data processing apparatus, including a processor and a memory including one or more computer program modules stored in the memory and configured to be executed by the processor, the one or more computer program modules including instructions for performing a video data processing method according to any of the previous embodiments.

[0027] For example, at least one embodiment of the present disclosure further provides a computer-readable storage medium having stored thereon computer instructions that, when executed by a processor, implement the steps of the video data processing method according to any of the above embodiments.

[0028] In order to more clearly describe the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be apparent that the drawings described below are only related to some embodiments of the present disclosure and are not intended to limit the present disclosure. [1] A video data processing method, comprising: determining, for a current video block of a video, to encode and decode using a first intra-prediction mode; performing a conversion between the current video block and the video bitstream based on the determination; In the first intra prediction mode, the reference pixels used by the current video block exclude pixels of a neighboring block to the upper right of the current video block. [2] The method of [1], in which in the first intra prediction mode, reference pixels for the current video block are determined based on the availability of a first neighboring block of the current video block. [3] determining reference pixels for the current video block based on availability of first neighboring blocks of the current video block, The method of [2], comprising determining the availability of the first neighboring block based on the position of the first neighboring block and the position of the current video block. [4] determining the availability of the first neighboring block based on the position of the first neighboring block and the position of the current video block, The method of [3], comprising the step of determining that the first neighboring block is unavailable in response to the first neighboring block being located to the upper right side of the current video block. [5] determining reference pixels for the current video block based on availability of the first neighboring block, The method according to any one of [2] to [4], comprising a step of determining pixel values ​​of the first neighboring block based on other neighboring blocks other than the first neighboring block of the current video block in response to the first neighboring block being unavailable. [6] determining pixel values ​​of the first neighboring block based on neighboring blocks other than the first neighboring block of the current video block, [5] The method of [5], comprising determining pixel values ​​of the first neighboring block based on an upper left neighboring block and at least one upper neighboring block of the current video block. [7] determining pixel values ​​of the first neighboring block based on an upper-left neighboring block and at least one upper neighboring block of the current video block, [6] The method according to [6], comprising a step of determining a pixel value of the first neighboring block based on a pixel value of a rightmost block of the at least one upper neighboring block and a pixel value of the upper-left neighboring block in response to satisfying a first condition. [8] The step of determining pixel values ​​of the first neighboring block based on pixel values ​​of a rightmost block of the at least one upper neighboring block and pixel values ​​of the upper left neighboring block includes: The method described in [7], further comprising a step of determining pixel values ​​of the first neighboring block by performing linear interpolation using pixel values ​​of the rightmost block of the at least one upper neighboring block and pixel values ​​of the upper left neighboring block. [9] The method described in [7] or [8], wherein the first condition includes that the difference between the average value of the pixel values ​​of the upper left neighboring block and the rightmost block of the at least one upper neighboring block and the average value of the pixel values ​​of all blocks of the at least one upper neighboring block is less than a threshold.

[10] The method according to [9], wherein the threshold is equal to bitdepth / 2, where bitdepth represents the bit depth of the video.

[11] The step of determining pixel values ​​of the first neighboring block based on an upper-left neighboring block of the current video block and the at least one upper neighboring block includes: The method according to any one of [6] to

[10] , comprising a step of determining pixel values ​​of the first adjacent block based on pixel values ​​of the upper left adjacent block in response to a first condition not being satisfied.

[12] The step of determining pixel values ​​of the first neighboring block based on pixel values ​​of the upper left neighboring block includes:

[11] The method of

[11] , comprising the step of setting pixel values ​​of the first neighboring block equal to pixel values ​​of the upper left neighboring block.

[13] The method according to any one of [1] to

[12] , wherein the first intra prediction mode includes a planar intra prediction mode, a DC intra prediction mode, an angular intra prediction mode, or a multi-reference line intra prediction mode.

[14] A video data processing method, comprising: receiving a video bitstream; determining that a current video block of the video is to be encoded and decoded using a first intra-prediction mode; and decoding the bitstream based on the determination; In the first intra prediction mode, the reference pixels used by the current video block exclude pixels of a neighboring block to the upper right of the current video block.

[15] The step of decoding the bitstream comprises: determining a region to be decoded corresponding to a first display partition in response to a current video frame of the video including a first display partition to be displayed and a second display partition that does not need to be displayed;

[14] The method according to

[14] , further comprising the step of decoding the bitstream based on the region to be decoded.

[16] The step of determining an area to be decoded corresponding to the first display partition includes: The method described in

[15] includes a step of determining the area to be decoded based on the encoding direction of the video, the partition direction between the first display partition and the second display partition, the number of pixels in the first display partition, and the size of the encoding unit of the video.

[17] The step of determining the area to be decoded based on the encoding direction, the partition direction, the number of pixels of the first display partition, and the size of the encoding unit includes: The method of

[16] , comprising a step of determining the number of coding-decoding units for each line of the area to be decoded by applying a function to the ratio between the number of pixels of the first display partition and the size of the coding unit in response to the coding direction of the video being perpendicular to the partition direction.

[18] The step of determining the area to be decoded based on the encoding direction, the partition direction, the number of pixels of the first display partition, and the size of the encoding unit includes: The method of

[16] , comprising a step of determining the number of lines of the encoding-decoding unit of the area to be decoded by applying a function to the ratio between the number of pixels of the first display partition and the size of the encoding unit in response to the encoding direction being parallel to the partition direction.

[19] The method according to

[17] or

[18] , wherein the function is a round-up function.

[20] A video data processing device, comprising: a decision module configured to determine to encode and decode a current video block of a video using a first intra-prediction mode; an execution module configured to perform a conversion between the current video block and the video bitstream based on the determination; In the first intra prediction mode, the reference pixels used by the current video block exclude pixels of a neighboring block to the upper right of the current video block.

[21] A display device, comprising: a video data processing device; and a roll-up display; A display device, wherein the video data processing device is configured to decode a received bitstream based on the video data processing method described in any one of [1] to

[19] , and transmit the decoded pixel values ​​to the roll-up display for display.

[22] The display device described in

[21] , wherein in response to the wrap-around display including a display area and a non-display area during operation, the video data processing device decodes the bitstream based on the size of the display area.

[23] The display device described in

[21] further includes a winding status determination device, wherein the winding status determination device detects the size of the display area of ​​the winding display and transmits the size of the display area to the video data processing device, so that the video data processing device is configured to decode the bitstream based on the size of the display area.

[24] A video data processing device, comprising: a processor; a memory containing one or more computer program modules; A video data processing device, wherein the one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include instructions for executing the video data processing method described in any of [1] to

[19] .

[25] A computer-readable storage medium having stored thereon computer instructions that, when executed by a processor, implement the steps of the video data processing method described in any one of [1] to

[19] . [Brief explanation of the drawings]

[0029] [Figure 1] FIG. 1 is a structural schematic diagram of a wrap-around display in accordance with at least one embodiment of the present disclosure. [Figure 2] FIG. 2 is a block diagram of an example video encoding and decoding system in accordance with at least one embodiment of the present disclosure. [Figure 3] FIG. 3 is a block diagram of an example video encoder in accordance with at least one embodiment of the present disclosure. [Figure 4] FIG. 4 is a block diagram of an example video decoder in accordance with at least one embodiment of the present disclosure. [Figure 5] FIG. 5 is a schematic diagram of an all-intra coding structure in accordance with at least one embodiment of the present disclosure. [Figure 6] FIG. 6 is a schematic diagram of a low-delay encoding structure in accordance with at least one embodiment of the present disclosure. [Figure 7A] FIG. 7A is a schematic diagram of intra-prediction coding in accordance with at least one embodiment of the present disclosure. [Figure 7B] FIG. 7B is a schematic diagram of another intra-prediction coding scheme in accordance with at least one embodiment of the present disclosure. [Figure 7C] FIG. 7C is a schematic diagram of multiple reference line intra prediction in accordance with at least one embodiment of the present disclosure. [Figure 8] FIG. 8 is a schematic diagram of a video data processing method in accordance with at least one embodiment of the present disclosure. [Figure 9] FIG. 9 is a schematic diagram of video encoding and decoding for a wrap-around display in accordance with at least one embodiment of the present disclosure. [Figure 10A] FIG. 10A is a schematic diagram of a rollable display in accordance with at least one embodiment of the present disclosure, showing the direction of the rotation axis. [Figure 10B] FIG. 10B is a schematic diagram of an axis of rotation of another wraparound display in accordance with at least one embodiment of the present disclosure. [Figure 11] FIG. 11 is a schematic diagram of a method for processing video data in accordance with at least one embodiment of the present disclosure. [Figure 12] FIG. 12 is a schematic block diagram of a video encoding and decoding system in an all-intra configuration in accordance with at least one embodiment of the present disclosure. [Figure 13] FIG. 13 is a schematic flow chart of a method for processing video data in an all-intra configuration in accordance with at least one embodiment of the present disclosure. [Figure 14] FIG. 14 is a schematic flow chart of a video data processing apparatus in accordance with at least one embodiment of the present disclosure. [Figure 15] FIG. 15 is a schematic block diagram of another video data processing apparatus in accordance with at least one embodiment of the present disclosure. [Figure 16] FIG. 16 is a schematic block diagram of a further video data processing apparatus in accordance with at least one embodiment of the present disclosure. [Figure 17] FIG. 17 is a schematic block diagram of a non-transitory readable storage medium in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0030] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. It is obvious that the described embodiments are only a part of the embodiments of the present disclosure, but not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without requiring creative work fall within the scope of protection of the present application.

[0031] Flowcharts are used in this disclosure to describe operations performed by systems according to embodiments of the present application. It should be understood that the operations described above or below are not necessarily performed in precise order. Rather, various steps may be processed in reverse order or simultaneously, as desired. At the same time, other operations may be added to these processes, or one or more operations may be removed from these processes.

[0032] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning understood by those skilled in the art. The terms "first," "second," and similar terms used in this disclosure do not denote any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, similar terms such as "one," "an," or "the" do not denote a limitation of quantity, but rather indicate the presence of at least one. Similar terms such as "comprise" or "comprises" mean that the elements or components listed before the term cover the elements or components listed after the term and their equivalents, and do not exclude other elements or components. Similar terms such as "connect" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" only denote relative positions, and if the absolute positions of the objects being described change, the relative positions may change accordingly.

[0033] Due to the increasing demand for high-definition video, video encoding and decoding methods and techniques are commonplace in modern technology. Video codecs typically include electronic circuits or software that compress or decompress digital video and are continually being improved to provide higher coding efficiency. Video codecs convert uncompressed video into compressed formats, and vice versa. There is a complex relationship between video quality, the amount of data required to represent the video (determined by the bit rate), the complexity of the encoding and decoding algorithms, sensitivity to data loss and errors, ease of editing, random access, and end-to-end latency. Compression formats typically conform to standard video compression specifications, such as the High Efficiency Video Coding and Decoding (HEVC) standard (also known as H.265), the finalized Universal Video Coding and Decoding (VVC) standard (also known as H.266), or other current and / or future video encoding and decoding standards.

[0034] As will be appreciated, embodiments of the techniques disclosed herein can be applied to conventional video encoding / decoding standards (e.g., AVC, HEVC, and VVC) and future standards to improve compression performance. References to encoding / decoding operations herein may refer to conventional video encoding / decoding standards, and it will be appreciated that the methods disclosed herein are not limited to the described video encoding / decoding standards.

[0035] With the emergence of terminal products such as foldable smartphones and foldable tablets, research into flexible display screens, such as flexible rollable displays, is currently receiving increasing attention. FIG. 1 is a structural schematic diagram of a rollable display according to at least one embodiment of the present disclosure. As shown in FIG. 1, a rollable display typically includes a fully unfolded state and a partially unfolded state. The unwound portion of the rollable display is considered the display area, and the rolled portion is considered the non-display area. Note that in the embodiments of the present disclosure, the rollable display may be any type of display screen with a variable display area, including but not limited to the rollable display structure shown in FIG. 1. Typically, during the actual use of a rollable display, for example, during the winding process, the video screen of the rolled portion of the rollable display does not need to be displayed, but the screen of that portion still needs to be decoded, resulting in a waste of decoding resources.

[0036] In order to solve at least the above technical problem, at least one embodiment of the present disclosure provides a video data processing method, the method including: determining to encode and decode a current video block of a video using a first intra-prediction mode; and performing conversion between the current video block and a video bitstream based on the determination. In the first intra-prediction mode, reference pixels used by the current video block exclude pixels of a neighboring block to the upper right of the current video block.

[0037] Correspondingly, at least one embodiment of the present disclosure further provides a video data processing device, a display device, and a computer-readable storage medium corresponding to the above video data processing method.

[0038] According to at least one embodiment of the video data processing method of the present disclosure, by removing the information dependency of a current video block on the neighboring block to the upper right and restricting the intra prediction mode of the current video block to only use the coded information of the neighboring blocks above, to the upper left, and to the left of the current video block, the video bitstream can be partially decoded based on the display area actually displayed, thereby reducing the consumption of decoding resources for the non-displayed part, effectively improving the efficiency of video encoding and decoding, and further improving the user's product usage experience.

[0039] Note that in embodiments of the present disclosure, terms used to describe the positions of neighboring blocks or reference pixels relative to a current video block, such as "upper left," "upper right," "upper," "lower left," "left side," and "right side," have meanings consistent with those defined in video encoding and decoding standards (e.g., AVC, HEVC, and VVC). For example, in some examples, "left" and "right" refer to opposite sides in the horizontal direction, respectively, "upper" and "lower" refer to opposite sides in the vertical direction, respectively, "upper left" refers to a range of positions from directly above the current position, rotated counterclockwise by 0 to 90 degrees, and "upper right" refers to a range of positions from directly above the current position, rotated clockwise by 0 to 90 degrees.

[0040] Below, a number of examples or embodiments and the layout design method according to the present disclosure are described in a non-limiting manner, and as described below, different features in these specific examples or embodiments can be combined with each other when not mutually contradictory, to obtain new examples or embodiments, and all of these new examples or embodiments also fall within the scope of protection of the present disclosure.

[0041] At least one embodiment of the present disclosure provides an encoding / decoding system. As can be understood, the present disclosure can be implemented using a codec with the same structure for both the encoding side and the decoding side.

[0042] 2 is a block diagram illustrating an example video encoding and decoding system 1000 according to some embodiments of the present disclosure. The techniques of this disclosure generally relate to encoding and decoding (encoding and / or decoding) video data. Generally, video data includes any data for processing video, and thus may include unencoded original video, encoded video, decoded (e.g., reconstructed) video, and video metadata such as syntax data. Video may include one or more pictures, also referred to as a picture sequence.

[0043] 2 , in this example, system 1000 includes a source device 102 for providing encoded video data to be decoded by a destination device 116 for display. The encoded video data is used to transmit to the decoding side by forming a bitstream, which may also be referred to as a bitstream. Specifically, source device 102 provides the encoded video data to destination device 116 via computer-readable medium 110. Source device 102 and destination device 116 may be embodied as various devices, such as a desktop computer, a laptop (i.e., portable) computer, a tablet computer, a mobile device, a set-top box, a smartphone, a handheld phone, a television, a camera, a display device, a digital media player, a video game console, a video streaming device, etc. In some cases, source device 102 and destination device 116 may be configured for wireless communication and therefore may be referred to as wireless communication devices.

[0044] In the example of FIG. 2 , source device 102 includes video source 104, memory 106, video encoder 200, and output interface 108. Destination device 116 includes input interface 122, video decoder 300, memory 120, and display device 118. According to some embodiments of the present disclosure, video encoder 200 of source device 102 and video decoder 300 of destination device 116 may be configured to implement encoding and decoding methods according to some embodiments of the present disclosure. Thus, source device 102 represents an example of a video encoding device, while destination device 116 represents an example of a video decoding device. In other examples, source device 102 and destination device 116 may include other components or configurations. For example, source device 102 can receive video data from an external video source, such as an external camera. Similarly, destination device 116 can be connected to an external display device and need not incorporate integrated display device 118.

[0045] The system 1000 shown in FIG. 2 is merely an example. In general, any digital video encoding and / or decoding device can perform the encoding and decoding methods according to some embodiments of the present disclosure. The source device 102 and the destination device 116 are merely examples of such encoding-decoding devices, with the source device 102 generating and transmitting a bitstream to the destination device 116. This disclosure refers to an "encoding-decoding" device as a device that performs data encoding and decoding (encoding and / or decoding). Accordingly, the video encoder 200 and the video decoder 300 each represent an example of an encoding-decoding device.

[0046] In some examples, devices 102, 116 operate in a substantially symmetrical manner, such that both devices 102, 116 include video encoding and decoding components, i.e., both devices 102, 116 are capable of implementing video encoding and decoding processes. Accordingly, system 1000 can support one-way or two-way video transmission between video devices 102, 116 and can be used, for example, for video streaming, video playback, video broadcasting, or video telephony.

[0047] Generally, the video source 104 represents a video data source (i.e., unencoded original video data) and provides a continuous series of pictures (also called "frames") of video data to the video encoder 200, which encodes the picture data. The video source 104 of the source device 102 may include a video capture device, such as a video camera, a video archive containing previously captured original video, and / or a video feed interface for receiving video from a video content provider. As another alternative, the video source 104 may generate computer graphics-based data as source video or a combination of live video, archived video, and computer-generated video. In various cases, the video encoder 200 encodes captured, pre-captured, or computer-generated video data. The video encoder 200 may rearrange the pictures from the order in which they are received (sometimes called "display order") to a coding order for encoding. The video encoder 200 may generate a bitstream containing the encoded video data. Source device 102 then outputs the generated bitstream via output interface 108 to computer-readable medium 110, where it is available for receipt and / or retrieval, such as by input interface 122 of destination device 116, for example.

[0048] Memory 106 of source device 102 and memory 120 of destination device 116 represent general-purpose memory. In some examples, memory 106 and memory 120 can store original video data, such as original video data from video source 104 and decoded video data from video decoder 300. Alternatively, memory 106 and memory 120 can store software instructions executable by video encoder 200, video decoder 300, etc., respectively. While shown separately from video encoder 200 and video decoder 300 in this example, it should be understood that video encoder 200 and video decoder 300 may include internal memory to achieve functionally similar or equivalent purposes. Memory 106 and memory 120 can also store encoded video data output from video encoder 200 and input to video decoder 300, etc. In some examples, portions of memory 106 and memory 120 may be allocated as one or more video buffers, for example, to store decoded original video data and / or encoded original video data.

[0049] The computer-readable medium 110 may represent any type of medium or device capable of transmitting encoded video data from the source device 102 to the destination device 116. In some examples, the computer-readable medium 110 represents a communications medium, by which the source device 102 can transmit a bitstream directly and in real time to the destination device 116, such as via a radio frequency network or a computer network. Based on a communications standard, such as a wireless communications protocol, the output interface 108 can modulate a transmission signal containing the encoded video data, and the input interface 122 can modulate a received transmission signal. The communications medium may include a wireless or wired communications medium, or may include both, such as a radio frequency (RF) spectrum or one or more physical transmission lines. The communications medium may form part of a packet-based network, such as a local area network, a wide area network, or a global network such as the Internet. The communications medium may include a router, a switch, a base station, or any other device that can be used to facilitate communications from the source device 102 to the destination device 116.

[0050] In some examples, source device 102 may output the encoded data from output interface 108 to storage device 112. Similarly, destination device 116 may access the encoded data from storage device 112 via input interface 122. Storage device 112 may include a variety of distributed or locally accessed data storage media, such as a hard disk drive, a Blu-ray disc, a digital video disc (DVD), a read-only optical disc drive (CD-ROM), flash memory, volatile or non-volatile memory, or any other suitable digital storage medium for storing encoded video data.

[0051] In some examples, source device 102 may output the encoded data to file server 114 or another intermediate storage device capable of storing the encoded video generated by source device 102. Destination device 116 may access the stored video data from file server 114 online or via download. File server 114 may be any type of server device capable of storing encoded data and transmitting the encoded data to destination device 116. File server 114 may represent a network server (e.g., for a website), a file transfer protocol (FTP) server, a content delivery network device, or a network-attached storage (NAS) device. Destination device 116 may access the encoded data from file server 114 via any standard data connection, including an Internet connection. This may include a wireless channel, such as a Wi-Fi connection, a wired connection, such as a digital subscriber line (DSL) or cable modem, or a combination of a wireless channel and a wired connection, adapted to access the encoded video data stored on file server 114. File server 114 and input interface 122 may be configured to operate based on a streaming transmission protocol, a download transmission protocol, or a combination thereof.

[0052] Output interface 108 and input interface 122 may represent wired networking components such as a wireless transmitter / receiver, a modem, an Ethernet card, or other physical components, wireless communication components operating in accordance with any of the various IEEE 802.11 standards. In examples where output interface 108 and input interface 122 include wireless components, output interface 108 and input interface 122 may be configured to transfer data, such as data encoded in accordance with a fourth generation mobile communication technology (4G), 4G Long Term Evolution (4G-LTE), LTE Advanced, fifth generation mobile communication technology (5G), or other cellular communication standards. In some examples where output interface 108 includes a wireless transmitter, output interface 108 and input interface 122 may represent data encoded in accordance with, for example, the IEEE 802.11 standard, the IEEE 802.15 standard (e.g., ZigBee), or other standards. TM ), or data encoded according to other wireless standards, such as the Bluetooth standard. In some examples, source device 102 and / or destination device 116 may include corresponding system-on-chip (SoC) devices. For example, source device 102 may include SoC devices to perform the functions of video encoder 200 and / or output interface 108, and destination device 116 may include SoC devices to perform the functions of video decoder 300 and / or input interface 122, for example.

[0053] The techniques of this disclosure may be applied to various multimedia applications, such as over-the-air television broadcasting, cable television transmission, satellite television transmission, Internet streaming video transmission such as HTTP-based dynamically adaptive streams, digital video encoded on a data storage medium, decoding of digital video stored on a data storage medium, or video encoding to support other applications.

[0054] Input interface 122 of destination device 116 receives a bitstream from computer-readable medium 110 (e.g., storage device 112, file server 114, etc.). The bitstream may include signaling information defined by video encoder 200 that is also used by video decoder 300, such as syntax elements with values ​​that describe the nature and / or processing of video blocks or other coding units (e.g., slices, pictures, groups of pictures, sequences, etc.).

[0055] Display device 118 displays decoded pictures of the decoded video data to a user and may be any of a variety of types of display devices, such as a cathode ray tube (CRT)-based device, a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, or other types of display devices.

[0056] 2, in some examples, video encoder 200 and video decoder 300 may be integrated with an audio encoder and / or audio decoder, respectively, and may include a suitable multiplexing-demultiplexing (MUX-DEMUX) unit or other hardware and / or software to process multiplexed streams containing both audio and video in a common data stream. If applicable, the MUX-DEMUX unit may conform to the ITU H.223 multiplexer protocol or other protocols, such as the User Datagram Protocol (UDP).

[0057] Both the video encoder 200 and the video decoder 300 may be implemented as any suitable codec circuit, such as a microprocessor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), discrete logic elements, software, hardware, firmware, or any combination thereof. When the techniques are partially implemented in software, a device can store instructions for the software on a suitable non-transitory computer-readable medium and use one or more such processors to execute the instructions in hardware to perform the techniques of this disclosure. Both the video encoder 200 and the video decoder 300 may be included in one or more encoders or decoders, or either of the encoders or decoders may be integrated as part of a combined encoder / decoder (CODEC) in a corresponding device. Devices including the video encoder 200 and / or the video decoder 300 may be integrated circuits, microprocessors, and / or wireless communication devices such as cellular phones.

[0058] Video encoder 200 and video decoder 300 may operate based on a video encoding / decoding standard, such as ITU-T H.265 (also known as High Efficiency Video Coding / Decoding (HEVC)), or an extension of HEVC, such as multiview and / or scalable video encoding / decoding extensions. Alternatively, video encoder 200 and video decoder 300 may operate based on other proprietary or industry standards (e.g., the Joint Search and Test Model (JEM) or Universal Video Coding / Decoding (VVC) standards currently under development). The technology involved in this disclosure is not limited to any particular encoding / decoding standard.

[0059] Generally, the video encoder 200 and the video decoder 300 can encode and decode video data represented in YUV (e.g., Y, Cb, Cr) format. That is, the video encoder 200 and the video decoder 300 can encode and decode luma and chroma components, which may include red and blue hues, rather than encoding and decoding red, green, and blue (RGB) data of a picture's sampling points. In some examples, the video encoder 200 converts received RGB format data to YUV format before encoding, and the video decoder 300 converts the YUV format to RGB format. Optionally, a pre-processing unit and a post-processing unit (not shown) can perform these conversions.

[0060] Generally, the video encoder 200 and the video decoder 300 may perform block-based encoding and decoding processes of a picture. The term "block" generally refers to a structure containing data to be processed (to be encoded, to be decoded, or to be used in other encoding and / or decoding processes). For example, a block may contain a two-dimensional matrix of luma and / or chroma data samples. Generally, encoding and decoding processes may be performed by first partitioning a picture into multiple blocks, and the block in a picture currently being encoded or decoded may be referred to as the "current block" or "current video block."

[0061] Additionally, embodiments of the present disclosure may further relate to encoding and decoding a picture, such as encoding or decoding picture data. Similarly, the present disclosure may relate to encoding a block of a picture, e.g., predictive and / or residual coding, such as encoding or decoding data of the block. The bitstream resulting from the encoding process typically includes a series of values ​​for syntax elements, which represent coding decisions (e.g., coding modes) and information about dividing the picture into blocks. Thus, encoding a picture or block may generally be understood as encoding the values ​​of the syntax elements that form the picture or block.

[0062] HEVC defines various blocks including coding units (CUs), prediction units (PUs), and transform units (TUs). According to HEVC, a video encoder (e.g., video encoder 200) divides coding tree units (CTUs) into CUs based on a quadtree structure. That is, the video encoder divides CTUs and CUs into four equal, non-overlapping blocks, and each node of the quadtree has zero or four subnodes. A node without subnodes may be called a "leaf node," and a CU of such a leaf node may include one or more PUs and / or one or more TUs. The video encoder can further divide PUs and TUs. For example, in HEVC, a residual quadtree (RQT) represents the division into TUs. In HEVC, a PU represents inter-predicted data, and a TU represents residual data. An intra-predicted CU includes intra-prediction information such as an intra-mode indication.

[0063] In VVC, a quadtree with nested multi-type trees (partitioned using binary and ternary trees) replaces the concept of multiple partition unit types, i.e., it eliminates the separation of CU, PU, ​​and TU concepts unless a CU whose size is too large for the maximum transform length is required and supports greater flexibility in CU partition shape. In the coding tree structure, a CU may have a square or rectangular shape. First, a CTU is partitioned using a quadtree structure. Then, the quadtree leaf nodes can be further partitioned using a multi-type tree structure. The multi-type tree leaf nodes are called coding units (CUs), and as long as the CU is not too large for the maximum transform length, this partition is used in the prediction and transform processes and does not require any further partitioning. This means that in many cases, CUs, PUs, and TUs have the same block size in a quadtree with a nested multi-type tree coding block structure.

[0064] Video encoder 200 and video decoder 300 may be configured to use quadtree partitioning according to HEVC, quadtree binary tree (QTBT) partitioning based on JEM, or other partitioning structures. As should be understood, the techniques of this disclosure may also be applied to video encoders configured to use quadtree partitioning or other partitioning types. Video encoder 200 encodes video data of a CU to represent prediction information and / or residual information and other information. The prediction information indicates how to predict the CU to form a prediction block for the CU. The residual information typically represents a sampling-point-by-sampling point difference between the sampling points of the CU before encoding and the prediction block sampling points.

[0065] The video encoder 200 may further generate syntax data for the video decoder 300, such as block-based syntax data, picture-based syntax data, and sequence-based syntax data, for example, in a picture header, a block header, a slice header, etc., or other syntax data, for example, a sequence parameter set (SPS), a picture parameter set (PPS), or a video parameter set (VPS). The video decoder 300 may similarly decode such syntax data to determine how to decode the corresponding video data. For example, the syntax data may include various syntax elements, flags, parameters, etc., for representing video encoding and decoding information.

[0066] In this manner, video encoder 200 can generate a bitstream that includes coded video data, e.g., syntax elements that describe the division of a picture into blocks (e.g., CUs), and prediction and / or residual information for the blocks. Finally, video decoder 300 can receive the bitstream and decode the coded video data.

[0067] Generally, the video decoder 300 decodes the encoded video data in the bitstream by performing the reverse process of that performed by the video encoder 200. For example, the video decoder 300 may decode values ​​of syntax elements in the bitstream in a manner substantially similar to that of the video encoder 200. The syntax elements may define CTUs of a picture based on partition information and define CUs of the CTUs by partitioning each CTU based on a corresponding partition structure, such as a QTBT structure. The syntax elements may further define prediction information and residual information of a block (e.g., a CU) of video data. The residual information may be represented, for example, by quantized transform coefficients. The video decoder 300 may reconstruct a residual block of the block by performing inverse quantization and inverse transform on the quantized transform coefficients of the block. The video decoder 300 forms a prediction block of the block using a prediction mode (intra- or inter-prediction) and related prediction information (e.g., motion information for inter-prediction) signaled in the bitstream. The video decoder 300 can then reconstruct the original block by combining the prediction block and the residual block (sampling point by sampling point). The video decoder 300 can also perform additional processing, such as performing a deblocking process to reduce visual artifacts along block boundaries.

[0068] Figure 3 is a block diagram illustrating an exemplary video encoder according to some embodiments of the present disclosure, and correspondingly, Figure 4 is a block diagram illustrating an exemplary video decoder according to some embodiments of the present disclosure, for example, the encoder shown in Figure 3 may be implemented as video encoder 200 in Figure 2, and the decoder shown in Figure 4 may be implemented as video decoder 300 in Figure 2. Below, a codec according to some embodiments of the present disclosure will be described in detail with reference to Figures 3 and 4.

[0069] 3 and 4 are provided for purposes of interpretation and should not be construed as limiting the techniques broadly illustrated and described in this disclosure. For purposes of interpretation, this disclosure describes video encoder 200 and video decoder 300 in the context of developing video encoding and decoding standards (e.g., the HEVC video encoding and decoding standard or the H.266 video encoding and decoding standard), but the techniques of this disclosure are not limited to these video encoding and decoding standards.

[0070] Each unit (also called a module) in FIG. 3 is shown to aid in understanding the operations performed by video encoder 200. These units may be implemented as fixed-function circuits, programmable circuits, or a combination of both. A fixed-function circuit refers to a circuit that provides a specific function and is preconfigured for the operations it can perform. A programmable circuit refers to a circuit that can be programmed to perform various tasks and provides flexibility in the operations it can perform. For example, a programmable circuit can execute software or firmware that causes the programmable circuit to operate in a manner defined by the software or firmware instructions. Although a fixed-function circuit can execute software instructions (such as receiving or outputting parameters), the type of operation performed by the fixed-function circuit is typically constant. In some examples, one or more units may be different circuit blocks (fixed-function circuit blocks or programmable circuit blocks), and in some examples, one or more units may be integrated circuits.

[0071] The video encoder 200 shown in Figure 3 may include an arithmetic logic unit (ALU), a basic functional unit (EFU), digital circuitry, analog circuitry, and / or a programmable core formed by programmable circuitry. In examples where the video encoder 200 uses software executed by programmable circuitry to perform its operations, the memory 106 (Figure 2) may store software target code that the video encoder 200 receives and executes, or other memory (not shown) within the video encoder 200 may be used to store such instructions.

[0072] In the example of FIG. 3, video encoder 200 can receive input video, such as from a video data memory, or can receive input video directly from a video acquisition device. The video data memory can store video data to be encoded by the video encoder 200 components. Video encoder 200 can receive video data stored in the video data memory from, for example, video source 104 (shown in FIG. 2). The decoding cache memory can be used as a reference picture memory for storing reference video data for use when video encoder 200 predicts subsequent video data. The video data memory and the decoding cache memory can be formed by various memory devices, such as dynamic random access memory (DRAM), including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), and resistive RAM (RRAM), or other types of memory devices. The video data memory and the decoding cache memory can be provided by the same storage device or different storage devices. In various examples, the video data memory may or may not be located on the same chip as other components of video encoder 200, as shown in FIG. 3.

[0073] In this disclosure, references to video data memory should not be construed as being limited to memory internal to video encoder 200 (unless specifically described as such) or limited to memory external to video encoder 200 (unless specifically described as such). More specifically, references to video data memory should be understood to be reference memory that stores video data for encoding received by video encoder 200 (e.g., video data of a current block to be encoded). Additionally, memory 106 in FIG. 2 may also provide temporary storage for the output of each unit in video encoder 200.

[0074] The mode selection unit typically tests combinations of coding parameters and rate-distortion values ​​obtained by these combinations in cooperation with multiple coding channels. The coding parameters may include the division of CTUs into CUs, prediction modes of CUs, transform types of CU residual data, quantization parameters of CU residual data, etc. The mode selection unit can ultimately select a coding parameter combination that has a better rate-distortion value than the other tested combinations.

[0075] Video encoder 200 may divide a picture retrieved from video memory into a series of CTUs and encapsulate one or more CTUs in a slice. The mode selection unit may divide the CTUs of a picture based on a tree structure (e.g., the above-mentioned QTBT structure or the quadtree structure of HEVC). As described above, video encoder 200 may form one or more CUs by dividing the CTUs based on the tree structure. Such a CU may generally be referred to as a "block" or a "video block."

[0076] In general, the mode selection unit further controls its components (e.g., a motion estimation unit, a motion compensation unit, and an intra prediction unit) to generate a prediction block for a current block (e.g., a current CU or an overlapping portion of a PU and a TU in HEVC). For inter prediction of the current block, the motion estimation unit can perform motion search to identify one or more closely matching reference blocks in one or more reference pictures (e.g., one or more decoded pictures stored in a decoding cache memory). Specifically, the motion estimation unit can calculate a value representing the similarity between a potential reference block and the current block based on, for example, a sum of absolute differences (SAD), a sum of squared differences (SSD), a mean absolute deviation (MAD), a mean squared deviation (MSD), etc., and the motion estimation unit can typically perform these calculations using the sampling point-by-sampling difference between the current block and the reference block under consideration. The motion estimation unit can indicate the reference block that most closely matches the current block by identifying the reference block with the lowest value generated from these calculations.

[0077] The motion estimation unit may generate one or more motion vectors (MVs), which define the location of a reference block in a reference picture relative to the location of a current block in the current picture. The motion estimation unit may then provide the motion vectors to a motion compensation unit. For example, for unidirectional inter prediction, the motion estimation unit may provide a single motion vector, and for bidirectional inter prediction, the motion estimation unit may provide two motion vectors. The motion compensation unit may then use the motion vectors to generate a predictive block. For example, the motion compensation unit may use the motion vectors to retrieve data for a reference block. As another example, if the motion vectors have fractional sampling point accuracy, the motion compensation unit may interpolate the predictive block based on one or more interpolation filters. Also, for bidirectional inter prediction, the motion compensation unit may retrieve data for two reference blocks identified by corresponding motion vectors and combine the retrieved data by averaging or weighted averaging per sampling point, etc.

[0078] As another example, for intra prediction, the intra prediction unit may generate a prediction block from sampling points neighboring the current block. For example, for a directional mode, the intra prediction unit may generate a prediction block by mathematically combining values ​​of neighboring sampling points and filling these calculations along a direction defined in the current block. As another example, for a DC mode, the intra prediction unit may calculate average values ​​of sampling points neighboring the current block, including the average value obtained at each sampling point of the prediction block, and generate a prediction block.

[0079] For other video encoding / decoding techniques, such as intra block copy mode encoding, affine mode encoding, and linear model (LM) mode encoding, the mode selection unit may generate a prediction block for the current block being encoded via a corresponding unit associated with the encoding / decoding technique. In some examples, for example, in the case of palette mode encoding, the mode selection unit may generate syntax elements that indicate how to reconstruct the block based on a selected palette without generating a prediction block. In such modes, the mode selection unit may provide these syntax elements to the entropy coding unit for encoding.

[0080] As described above, the residual unit receives the current block and the corresponding predicted block. The residual unit then generates a residual block for the current block. To generate the residual block, the residual unit calculates the sample-by-sample difference between the predicted block and the current block.

[0081] A transform unit (shown as "Transform & Sample & Quantize" in FIG. 3) applies one or more transforms to a residual block, generating blocks of transform coefficients (e.g., referred to as "transform coefficient blocks"). A transform unit may apply various transforms to a residual block to form transform coefficient blocks. For example, a transform unit may apply a Discrete Cosine Transform (DCT), a Directional Transform, a Karhunen-Loeve Transform (KLT), or a conceptually similar transform to a residual block. In some examples, a transform unit may perform multiple transforms on a residual block, such as a linear and a quadratic transform, a rotational transform, etc. In some examples, a transform unit may not apply a transform to a residual block.

[0082] The transform unit may then quantize the transform coefficients in the transform coefficient block to generate a quantized transform coefficient block. The transform unit may quantize the transform coefficients of the transform coefficient block based on a quantization parameter (QP) value associated with the current block. The video encoder 200 may adjust the degree of quantization applied to the coefficient block associated with the current block by adjusting the QP value associated with the CU (e.g., via a mode selection unit). Quantization may cause information loss, and therefore, the precision of the quantized transform coefficients may be lower than the precision of the original transform coefficients.

[0083] The encoder 200 may further include a coding control unit for generating control information for operations in the encoding process. Subsequently, the inverse quantization and inverse transform unit ("Inverse Quantization & Inverse Transform" shown in FIG. 3) may apply inverse quantization and inverse transform, respectively, to the quantized transform coefficient block to obtain a reconstructed residual block from the transform coefficient block. The reconstruction unit may generate a reconstructed block (which may have some distortion) corresponding to the current block based on the reconstructed residual block and the prediction block generated by the mode selection unit. For example, the reconstruction unit may generate the reconstructed block by adding sampling points of the reconstructed residual block to corresponding sampling points of the prediction block generated by the mode selection unit.

[0084] The reconstruction block may perform one or more filtering operations by a filtering process, such as the loop filtering unit shown in Figure 3. For example, the filtering process may include a deblocking operation to reduce blocking artifacts along CU edges. In some examples, operations in the filtering process may be skipped.

[0085] Subsequently, after, for example, loop filtering, the video encoder 200 can store the reconstructed blocks in a decoding cache memory. In an example that skips the filtering process, the reconstruction unit can store the reconstructed blocks in the decoding cache memory. In an example that requires the filtering process, the filtered reconstructed blocks can be stored in the decoding cache memory. The motion estimation unit and the motion compensation unit can retrieve the reference picture formed by the reconstructed (and possibly filtered) blocks from the decoding cache memory, thereby performing inter prediction on blocks of a subsequently coded picture. Also, the intra prediction unit can perform intra prediction on other blocks in the current picture using the reconstructed blocks in the decoding cache memory of the current picture.

[0086] The operations described above are block-wise. This description should be understood to be for luma-coding blocks and / or chroma-coding blocks. As noted above, in some examples, the luma-coding blocks and chroma-coding blocks are the luma and chroma components of a CU. In some examples, the luma-coding blocks and chroma-coding blocks are the luma and chroma components of a PU.

[0087] In general, the entropy coding unit may entropy code syntax elements received from other functional components of the video encoder 200. For example, the entropy coding unit may entropy code quantized transform coefficient blocks from a transform unit. For example, the entropy coding unit may entropy code prediction syntax elements (e.g., motion information for inter prediction or intra-mode information for intra prediction) from a mode selection unit to generate entropy-coded data. For example, the entropy coding unit may perform a context-adaptive variable-length coding (CAVLC) operation, a context-adaptive binary arithmetic coding (CABAC) operation, a variable-length coding operation, a syntax-based context-adaptive binary arithmetic coding (SBAC) operation, a probability interval partitioning entropy (PIPE) coding operation, an exponential-Golomb coding operation, or other types of entropy coding operations on the data. In some examples, the entropy coding unit may operate in a bypass mode in which syntax elements are not entropy coded. Video encoder 200 can output a bitstream that includes the entropy coding syntax elements necessary to reconstruct the blocks of a slice or picture.

[0088] 4 is a block diagram illustrating an exemplary video decoder according to some embodiments of the present disclosure. For example, the decoder illustrated in FIG. 4 may be the video decoder 300 in FIG. 2. As can be appreciated, the provision of FIG. 4 is for purposes of interpretation and is not intended to limit the techniques broadly illustrated and described in this disclosure. For purposes of interpretation, the video decoder 300 is described based on HEVC technology. However, the techniques of the present disclosure may be performed by video decoding devices configured for other video encoding and decoding standards.

[0089] As can be understood, in practical applications, the basic structure of the video decoder 300 may be similar to the video encoder shown in FIG. 3, whereby both the encoder 200 and the decoder 300 include video encoding and decoding components, i.e., both the encoder 200 and the decoder 300 can implement video encoding and decoding processes. In such a case, the encoder 200 and the decoder 300 may be collectively referred to as a codec. Therefore, a system consisting of the encoder 200 and the decoder 300 can support one-way or two-way video transmission between devices, and can be used, for example, for video streaming, video playback, video broadcasting, or video telephony. As can be understood, the video decoder 300 may include more, fewer, or different functional components than those shown in FIG. 4. For ease of understanding, FIG. 4 illustrates components related to a decoding conversion process according to some embodiments of the present disclosure.

[0090] In the example of FIG. 4, the video decoder 300 includes a memory, an entropy decoding unit, a prediction processing unit, an inverse quantization and inverse transform unit (shown as the "inverse quantization & inverse transform unit" in FIG. 4), a reconstruction unit, a filter unit, a decoding cache memory, and a bit-depth inverse transform unit. The prediction processing unit may include a motion compensation unit and an intra-prediction unit. The prediction processing unit may further include an addition unit, for example, to perform prediction based on other prediction modes. By way of example, the prediction processing unit may include a palette unit, an intra-block copy unit (which may form part of the motion compensation unit), an affine unit, a linear model (LM) unit, etc. In other examples, the video decoder 300 may include more, fewer, or different functional components.

[0091] As shown in FIG. 4, decoder 300 may first receive a bitstream containing encoded video data. For example, the memory in FIG. 4 may be referred to as a coding-decoding picture buffer (CPB), which stores the bitstream containing the encoded video data and awaits decoding by components of video decoder 300. The video data stored in the CPB may be obtained, for example, from computer-readable medium 110 (FIG. 1). The CPB may also store temporary data output from each unit of video decoder 300. A decoding cache memory typically stores decoded pictures, which video decoder 300 can output and / or use as reference video data when decoding subsequent data or pictures in the bitstream. The CPB memory and the decoding cache memory may be formed by various memory devices, for example, dynamic random access memory (DRAM), including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), and resistive RAM (RRAM), or other types of memory devices. The CPB memory and the decoding cache memory may be provided by the same storage device or different storage devices. In various examples, the CPB memory may be located on the same chip as other components of video decoder 300, or may not be located on the same chip as other components, as shown in the figures.

[0092] The various units shown in FIG. 4 are presented to aid in understanding the operations performed by video decoder 300. These units may be implemented as fixed-function circuits, programmable circuits, or a combination of both. As with FIG. 3, fixed-function circuits refer to circuits that provide specific functionality and are preconfigured for possible operations. Programmable circuits refer to circuits that can be programmed to perform various tasks and provide flexibility in the operations they can perform. For example, a programmable circuit may execute software or firmware that causes the programmable circuit to operate in a manner defined by the software or firmware instructions. While a fixed-function circuit may execute software instructions (such as receiving or outputting parameters), the type of operation performed by the fixed-function circuit is typically constant. In some examples, one or more units may be different circuit blocks (fixed-function circuit blocks or programmable circuit blocks), and in some examples, one or more units may be integrated circuits.

[0093] Video decoder 300 may include a programmable core formed by ALUs, EFUs, digital circuits, analog circuits, and / or programmable circuits. In examples where the operation of video decoder 300 is performed by software executed in programmable circuits, on-chip or off-chip memory may store software instructions (e.g., target code) received and executed by video decoder 300.

[0094] Subsequently, the entropy decoding unit can entropy decode the received bitstream to parse out the coding information corresponding to the picture therefrom.

[0095] Subsequently, the decoder 300 can be used to perform a decoding conversion process based on the analyzed encoding information to generate display video data. According to some embodiments of the present disclosure, the operations that can be performed by the decoder 300 located on the decoding side can refer to the decoding conversion process shown in Figure 4, which may be understood to include a general decoding process, thereby generating a display picture for display by a display device.

[0096] In the decoder 300 shown in Figure 4, the entropy decoding unit can receive a bitstream containing encoded video, for example from memory 120, and entropy decode it to recover syntax elements. The inverse quantization and inverse transform unit ("Inverse Quantization & Inverse Transform" shown in Figure 4), the reconstruction unit, and the filter unit can generate decoded video, for example, generate decoded pictures, based on the syntax elements extracted from the bitstream.

[0097] Generally, video decoder 300 reconstructs a picture on a block-by-block basis. Video decoder 400 may perform a reconstruction operation on each block independently, and the block currently being reconstructed (i.e., decoded) may be referred to as the "current block."

[0098] Specifically, the entropy decoding unit can entropy decode syntax elements that define the quantized transform coefficients of a quantized transform coefficient block, as well as transform information such as a quantization parameter (QP) and / or a transform mode indication. The inverse quantization and inverse transform unit can determine the degree of quantization using the QP associated with the quantized transform coefficient block, and can similarly determine the degree of inverse quantization to be applied. For example, the inverse quantization and inverse transform unit can inverse quantize the quantized transform coefficients by performing a bitwise left-shift operation. The inverse quantization and inverse transform unit can then form a transform coefficient block containing the transform coefficients. After forming the transform coefficient block, the inverse quantization and inverse transform unit can apply one or more inverse transforms to the transform coefficient block to generate a residual block associated with the current block. For example, the inverse quantization and inverse transform unit can apply an inverse DCT, an inverse integer transform, an inverse Karhunen-Loeve transform (KLT), an inverse rotational transform, an inverse transform, or other inverse transform to the coefficient block.

[0099] The prediction processing unit also generates a prediction block based on the prediction information syntax element entropy decoded by the entropy decoding unit. For example, if the prediction information syntax element indicates that the current block is inter-predicted, the motion compensation unit can generate a prediction block. In this case, the prediction information syntax element can indicate a reference picture in the decoding cache memory (from which the reference block is retrieved) and a motion vector that identifies the location of the reference block in the reference picture relative to the current block in the current picture. The motion compensation unit can generally perform an inter-prediction process in a manner essentially similar to that described for the motion compensation unit in FIG. 3.

[0100] As another example, if the prediction information syntax element indicates that intra prediction is to be performed on the current block, the intra prediction unit may generate a predicted block based on the intra prediction mode indicated by the prediction information syntax element. Similarly, the intra prediction unit may generally perform an intra prediction process in a manner essentially similar to that described for the intra prediction unit in Figure 3. The intra prediction unit may retrieve data of sampling points adjacent to the current block from a decoding cache memory.

[0101] The reconstruction unit may use the prediction block and the residual block to reconstruct the current block, for example, by adding sampling points of the residual block to corresponding sampling points of the prediction block.

[0102] Subsequently, the filter unit may perform one or more filter operations on the reconstructed block. For example, the filter unit may perform a deblocking operation to reduce blocking effect artifacts along the edges of the reconstructed block. As can be appreciated, the filtering operation does not need to be performed in all instances, i.e., the filtering operation may be skipped in some cases.

[0103] The video decoder 300 may store the reconstructed blocks in a decoding cache memory. As such, the decoding cache memory may provide reference information to, for example, a motion compensation unit or a motion estimation unit, such as sampling points of the current picture for intra-prediction and sampling points of a previously decoded picture for subsequent motion compensation. The video decoder 300 may also output the decoded pictures from the decoding cache memory for subsequent presentation to a display device (e.g., display device 118 of FIG. 2).

[0104] FIG. 5 is a schematic diagram of an All Intra (AI) coding structure in accordance with at least one embodiment of the present disclosure.

[0105] For example, as shown in Figure 5, in an all-intra (AI) configuration, all frames in a video are coded according to the I-frame during the coding process, meaning that the coding and decoding processes are completely independent and have no dependency on other frames. At the same time, the quantization parameter (QP) during the coding process does not change according to the coding position, and is always equal to the QP value (QPI) of the first frame. As shown in Figure 5, in an all-intra (AI) configuration, the playback order and coding order of all frames in a video are the same, meaning that the playback order count (POC) and coding order count (EOC) of each video frame are the same.

[0106] FIG. 6 is a schematic diagram of an encoding structure for a low-delay (LD) configuration in accordance with at least one embodiment of the present disclosure.

[0107] In practical applications, low-delay (LD) configurations are typically used in real-time communication environments with low-delay needs. As shown in Figure 6, in LD configurations, all P or B frames use broad-sense P / B frame prediction, and the EOC of all frames still matches the POC. A "1+x" solution is proposed for low-delay configurations, where "1" is one nearest reference frame and "x" is x high-quality reference frames.

[0108] FIG. 7A is a schematic diagram of intra-prediction coding in accordance with at least one embodiment of the present disclosure.

[0109] The main idea of ​​video predictive coding is to eliminate correlation between pixels through prediction. According to different reference pixel locations, video predictive coding techniques are mainly divided into two types: (1) intra prediction, which generates a predicted value using pixels coded in the current image (current video frame), and (2) inter prediction, which generates a predicted value using reconstructed pixels of an image coded before the current image (current video frame). Intra predictive coding refers to utilizing correlation in the video spatial domain and predicting the current pixel using coded pixels in the current image, thereby achieving the goal of eliminating redundancy in the video spatial domain. As shown in Figure 7A, a current coding block can perform intra prediction using coded information of neighboring reference blocks in the current video frame (e.g., an I-frame) to generate prediction information (or predicted block) for the current coding block.

[0110] FIG. 7B is a schematic diagram of another intra-prediction coding scheme in accordance with at least one embodiment of the present disclosure.

[0111] For example, in the HEVC video coding and decoding standard, I-frame images can be compressed and coded using only intra-coding techniques. For example, the intra-prediction process can be divided into the following three steps:

[0112] Step 1: Determine whether the neighboring reference pixels of the current video block (e.g., CU / PU / TU) are available (if they exist, and if they do not, fill them in), and obtain the neighboring reference pixels.

[0113] Step 2: Filter the reference pixels.

[0114] Step 3: Calculate predicted pixel values ​​for the current video block based on the filtered reference pixels and the prediction mode.

[0115] The current video block generally supports 35 prediction modes, including a planar mode, a DC mode, and 33 angular prediction modes.x,y represents the pixel reconstruction value (decoded pixel value) of the neighboring block, which is used as the reference pixel, and P x,y represents a predicted value of a pixel of the current video block. In the intra prediction process, the selection of neighboring reference pixels is an important step. For example, as shown in FIG. 7B, the size of the current TU is N×N, and the reference blocks or reference pixels of the current video block can be divided into five parts according to the region: lower left (region A), left side (region B), upper right (region C), upper side (region D), and upper right (region E). A total of 4N+1 sampling points are included, and region C has only one reference sampling point. If the current TU is located on an image boundary, a slice boundary, or a tile boundary, neighboring reference pixels may not exist or may be unavailable. In addition, in some cases, a block in region A or region E may not be coded, and reference pixels may also be unavailable. When reference pixels do not exist or are unavailable, the HEVC standard uses the nearest neighboring pixel to fill in the gap. For example, if reference pixels in region A do not exist or are unavailable, all reference pixels in region A are filled in with the bottommost pixel in region B. Furthermore, for example, if a reference pixel in region E does not exist or is unavailable, all reference pixels in region E are filled with the rightmost pixel in region D. Note that if all reference pixels in all regions are unavailable, all reference pixels are filled with a fixed value.

[0116] FIG. 7C is a schematic diagram of multiple reference line intra prediction in accordance with at least one embodiment of the present disclosure.

[0117] For example, the video coding and decoding standard VVC improves HEVC's intra prediction method by expanding the number of prediction angles from 33 to 65 and switching the angular prediction interpolation filter to a 4-tap Gaussian interpolation filter. At the same time, the multi-type tree (MTT) partitioning structure eliminates the need for square coding units (CUs) and allows for the widespread use of CUs of various rectangular sizes. VVC also expands the prediction range of HEVC's angular prediction and introduces the Wide Angular Intra Prediction Mode (WAIP). In addition to HEVC's improved intra coding technology, VVC also incorporates new high-efficiency prediction techniques, such as Cross-Component Linear Model (CCLM), Position Dependent Intra Prediction Combination (PDPC), Multiple Reference Line Intra Prediction (MRL), and Intra Sub-Partition Prediction (ISP).

[0118] As shown in FIG. 7C, multiple reference line intra prediction uses multiple reference lines for intra prediction. HEVC uses only reference line 0, i.e., one line of coded information, while VVC can use reference lines 0, 1, and 3. Among the reference lines with indexes 0 to 3, the reference lines with indexes 0 and 1 are relatively close to the pixels in the current video block and have a relatively high correlation, and therefore need to be reserved. The reference pixel line with index 3 is relatively far from the current prediction unit and can provide relatively different reference pixels. The reference pixel line with index 2 is difficult to provide additional reference pixel information and introduces more complexity, so it is discarded.

[0119] 8 is a schematic diagram of a method for processing video data in accordance with at least one embodiment of the present disclosure. FIG. 9 is a schematic diagram of video encoding and decoding for a rollable display in accordance with at least one embodiment of the present disclosure.

[0120] For example, at least one embodiment of the present disclosure provides a video data processing method 10. The video data processing method 10 can be applied to various application scenarios related to video encoding and decoding, such as terminals such as mobile phones and computers, and can also be applied to, for example, video websites / video platforms, etc., although the embodiments of the present disclosure are not specifically limited thereto. For example, as shown in FIG. 8, the video data processing method 10 includes the following operations S101 and S102.

[0121] Step S101: Determine that a current video block of a video is to be encoded or decoded using a first intra prediction mode.

[0122] Step S102: Based on the determination, perform conversion between the current video block and the video bitstream. In the first intra prediction mode, the reference pixels used by the current video block exclude pixels of the neighboring block to the upper right of the current video block.

[0123] For example, in at least one embodiment of the present disclosure, the video may be a filmed production, a video downloaded from a network, or a locally stored video, and may be an LDR video, an SDR video, etc., and the embodiments of the present disclosure are not limited thereto.

[0124] For example, in at least one embodiment of the present disclosure, in the HEVC standard, a current video block has 35 intra prediction modes to choose from, such as planar mode, DC mode, and 33 angular modes. For example, in the VVC standard, the number of intra angular prediction modes increases from 33 to 65. The VVC standard also introduces new intra prediction modes, such as matrix weighted intra prediction (MIP), intra subpartition (ISP), multiple reference line (MRL) intra prediction, position-dependent intra prediction, cross-component linear model prediction, wide-angle intra prediction mode, etc. For example, in an embodiment of the present disclosure, for a current video block, the available intra prediction modes include at least one of the above intra prediction modes, although the embodiments of the present disclosure are not limited thereto.

[0125] For example, in at least one embodiment of the present disclosure, a Most Probable Mode (MPM) list, also referred to as an intra-prediction mode candidate list, may be constructed for a current video block. Note that the embodiments of the present disclosure do not limit the construction process of the MPM list, and the MPM list may be configured according to actual circumstances. For example, in at least one embodiment of the present disclosure, the MPM list may include three MPM candidates, five MPM candidates, or six MPM candidates. For example, in the HEVC standard, an MPM list including three MPM candidates may be constructed.

[0126] For example, in at least one embodiment of the present disclosure, to obtain the optimal coding effect in terms of rate-distortion, the rate-distortion overhead of each possible prediction mode for the current video block is compared, and the mode with the smallest rate-distortion overhead is selected as the optimal intra prediction mode. For example, in some examples, after constructing an MPM sequence for the current video block, the intra prediction mode with the smallest rate-distortion overhead in the MPM list is selected as the "first intra prediction mode." Note that the "first intra prediction mode" is used to indicate the ultimately selected intra prediction mode for the current video block, e.g., the intra prediction mode with the smallest rate-distortion overhead. The "first intra prediction mode" is not limited to any particular intra prediction mode or any particular order.

[0127] For example, in at least one embodiment of the present disclosure, the first intra prediction mode may be any of the above available intra prediction modes, such as a planar intra prediction mode, a DC intra prediction mode, an angular intra prediction mode, a multi-reference line intra prediction mode, a cross-component linear prediction mode, an intra sub-partition prediction mode, etc., and the embodiments of the present disclosure are not limited thereto.

[0128] For example, in at least one embodiment of the present disclosure, in a first intra-prediction mode, the reference pixels used by the current video block exclude pixels of the neighboring block to the upper right of the current video block, i.e., in the first intra-prediction mode, the reference pixels used by the current video block do not include pixels of the neighboring block to the upper right of the current video block. For example, in some examples, when selecting reference pixels for an intra-prediction mode in the MPM list of the current video block, pixels of the neighboring block to the upper right of the current video block are excluded. This removes information dependency on the neighboring block to the upper right of the current video block (reference pixels) and restricts the intra-prediction mode of the current video block to only use coded information of the neighboring blocks to the upper left, upper left, and left of the current video block, thereby allowing the video bitstream to be partially decoded based on the display area that is actually displayed, thereby reducing the consumption of decoding resources for the non-displayed portion, effectively improving the efficiency of video encoding and decoding, and further improving the user's product usage experience.

[0129] For example, in at least one embodiment of the present disclosure, converting between the current video block and the bitstream may include encoding the current video block into the bitstream or may include decoding the current video block from the bitstream, i.e., the conversion process may include an encoding process or a decoding process, and embodiments of the present disclosure are not limited thereto.

[0130] For example, as shown in FIG. 9, in at least one embodiment of the present disclosure, when the video data processing method 10 is applied to a display device with a rollable display, the video content corresponding to the rolled-up area may not be displayed during the roll-up process of the rollable display, and therefore the bitstream corresponding to the rolled-up area may not be decoded. In FIG. 9, the shaded area represents the area not participating in decoding. As the roll-up display is gradually rolled up from its fully unfolded state, the size of the area not participating in decoding also gradually increases. Therefore, the received bitstream is partially decoded based on the actual display area of ​​the roll-up display, thereby achieving the technical effect of saving resources in the decoding process, thereby improving the service life of products with roll-up displays and enhancing the user's product experience.

[0131] For example, in at least one embodiment of this disclosure, in a first intra-prediction mode, reference pixels for a current video block are determined based on the availability of a first neighboring block of the current video block.

[0132] For example, in some cases, since only a portion of the content in the video bitstream (i.e., the content that needs to be displayed) is decoded, not all of the neighboring blocks of the current video may be decoded, that is, not all of the neighboring blocks may have reconstructed values. In consideration of the above technical issues, it is necessary to determine whether the neighboring blocks are available by checking the availability of the neighboring blocks of the current video block.

[0133] For example, in at least one embodiment of the present disclosure, determining reference pixels for the current video block based on the availability of the first neighboring block includes determining the availability of the first neighboring block based on the position of the first neighboring block and the position of the current video. Note that in the embodiments of the present disclosure, the term "first neighboring block" is used to refer to any neighboring block of the current video block. The term "first neighboring block" is not limited to any particular neighboring block or any particular order.

[0134] FIG. 10A is a schematic view of a rotation axis direction of a rollable display according to at least one embodiment of the present disclosure, and FIG. 10B is a schematic view of a rotation axis direction of another rollable display according to at least one embodiment of the present disclosure.

[0135] For example, in at least one embodiment of the present disclosure, the video encoding direction is typically horizontally from left to right and then vertically from top to bottom. In the example shown in Figure 10A, the rotation axis direction of the rollable display (also referred to herein as the division direction between the first and second display partitions) is considered to be perpendicular to the video encoding direction. In the example shown in Figure 10B, the rotation axis direction of the rollable display (also referred to herein as the division direction between the first and second display partitions) is considered to be parallel to the video encoding direction.

[0136] In the embodiments of the present disclosure, the "first display partition" is used to indicate a part of video content or a video area to be displayed in the current video frame, and the "second display partition" is used to indicate a part of video content or a video area that does not need to be displayed in the current video frame. The "first display partition" and the "second display partition" are not limited to any particular one or some video areas or video contents, and are not limited to a particular order.

[0137] For example, in the example shown in FIG. 10A, as the rotation axis of the roll-up display moves from left to right, the area that needs to be displayed also expands to the right, i.e., the area that needs to be decoded expands to the right. In intra-prediction mode, the current video block needs to be predicted using decoded information of neighboring blocks of the current video block in the same image. Therefore, a situation may occur in which the neighboring block to the upper right of the current video block has not been decoded. To avoid this situation, the range of the reference block / reference pixel of the current video block can be limited during the encoding process to eliminate information dependency on the neighboring block to the upper right of the current video block.

[0138] For example, in at least one embodiment of the present disclosure, when the video coding direction is perpendicular to the partitioning direction (the example shown in FIG. 10A), the first neighboring block is determined to be unavailable in response to the first neighboring block being located to the upper right of the current video block.

[0139] For example, in some instances, when the rotation axis direction of the roll-up display (i.e., the division direction of the current video frame) is perpendicular to the video encoding direction, the neighboring block of the current video block is considered unavailable if it is located to the upper right of the current video block, for example, as shown in FIG. 10A.

[0140] For example, in some cases, as shown in Figure 7B, when a neighboring block is located in region E, the neighboring block is deemed unavailable because there may be no reconstructed pixel values ​​in the neighboring block located in region E. Furthermore, in some cases, as shown in Figure 7C, when a neighboring block is located in the right part of Segment E indicated by the dashed line or in Segment F, the neighboring block is deemed unavailable because there may be no reconstructed pixel values ​​in the neighboring block located in the right part of Segment E indicated by the dashed line or in Segment F.

[0141] For example, in some instances, when the direction of the rotation axis of the roll-up display (i.e., the segmentation direction of the current video frame) is parallel to the encoding direction of the video, for example, in the example shown in Figure 10B, there is no need to remove information dependency on the upper right neighboring block. Therefore, the encoding process does not need to be modified for situations where the direction of the rotation axis of the roll-up display (i.e., the segmentation direction of the current video frame) is parallel to the encoding direction of the video.

[0142] For example, in at least one embodiment of the present disclosure, determining reference pixels of the current video block based on the availability of the first neighboring block includes, in response to the first neighboring block being unavailable, determining pixel values ​​of the first neighboring block based on other neighboring blocks other than the first neighboring block of the current video block.

[0143] For example, in some instances, since neighboring blocks in the upper right region are unavailable (because they may not have pixel reconstruction values), information dependency on neighboring blocks in the upper right region can be eliminated by supplementing with information from neighboring blocks located in the left, upper and / or upper left regions of the current video block.

[0144] For example, in at least one embodiment of the present disclosure, determining pixel values ​​of the first neighboring block based on neighboring blocks other than the first neighboring block of the current video block includes determining pixel values ​​of the first neighboring block based on an upper left neighboring block and at least one upper neighboring block of the current video block.

[0145] For example, in some cases, as shown in FIG. 7B, when the current video block is located at the right boundary of a CU, region E is generated by supplementing the information of region E using information from regions C and D without using previously coded information. For example, in the example shown in FIG. 7B, the pixel value of the neighboring block located at region C is R 0,0 and the pixel values ​​of the neighboring blocks located in region D are expressed as R 1,0 , R2,0 …R N,0 The pixel values ​​of the neighboring blocks located in the region E are expressed as R N+1,0 , R N+2,0 …R 2N,0 It is expressed as:

[0146] For example, in at least one embodiment of the present disclosure, the step of determining a pixel value of the first neighboring block based on an upper left neighboring block and at least one upper neighboring block of the current video block includes, in response to satisfying a first condition, obtaining a pixel value of the first neighboring block based on a pixel value of a rightmost block of the at least one upper neighboring block and a pixel value of the upper left neighboring block.

[0147] In the embodiments of the present disclosure, the "first condition" is not limited to any one or several specific conditions, and is not limited to a specific order. For example, in some examples, the first condition includes that a difference between an average value of pixel values ​​of the upper left neighboring block (located in region C) and the rightmost block among at least one upper neighboring block (located in region D) and an average value of pixel values ​​of all blocks among the at least one upper neighboring block is less than a certain threshold.

[0148] For example, in some examples, the threshold is equal to bitdepth / 2, where bitdepth represents the bit depth of the video. Note that the embodiments of the present disclosure do not specifically limit the value of the threshold, and it can be set according to actual needs.

[0149] For example, in some cases, as shown in FIG. 7B, the pixel values ​​(R 0,0 ) and the pixel value (R N,0 ) and the pixel values ​​(R 1,0 , R 2,0 …R N,0) is less than a certain threshold, the pixel value of the upper left neighboring block (R 0,0 ) and the pixel value (R N,0 ) to calculate the pixel value (R N+1,0 , R N+2,0 …R 2N,0 ) can be replenished and generated.

[0150] For example, in at least one embodiment of the present disclosure, the pixel value (R N,0 ) and the pixel value of the upper left adjacent block (R 0,0 ) to perform linear interpolation to obtain the pixel value of the first adjacent block. The calculation method of linear interpolation may be as shown in Equation 1 below, or may be set according to actual needs, and the embodiments of the present disclosure do not specifically limit it.

[0151] For example, in at least one embodiment of the present disclosure, in response to not satisfying the first condition, pixel values ​​of the first neighboring block are determined based on pixel values ​​of the upper-left neighboring block, e.g., in some examples, pixel values ​​of the first neighboring block are obtained by copying pixel values ​​of the upper-left neighboring block, i.e., pixel values ​​of the first neighboring block are set equal to pixel values ​​of the upper-left neighboring block.

[0152] For example, in the example shown in FIG. 7B, the pixel value (R 0,0 ) and the pixel value (R N,0 ) and the pixel values ​​(R 1,0 , R 2,0 …R N,0 ) is greater than or equal to a threshold, the pixel value of the upper left adjacent block (R 0,0 ) is directly copied to the pixel value (R N+1,0, R N+2,0 …R 2N,0 ) can be replenished and generated.

[0153] For example, in at least one embodiment of the present disclosure, with reference to FIG. 7B, Equation 1 is provided to calculate the pixel value of the upper right neighboring block (e.g., R N+1,0 , R N+2,0 …R 2N,0 ) is calculated as follows:

[0154]

number

[0155] In Equation 1, R m,0 represents the pixel located at coordinate (m, 0), bitdepth represents the bit depth of the video, the size of the current video block is NxN, i is an integer and is 0 <i≦Nである。

[0156] For example, in at least one embodiment of the present disclosure, for the multiple reference line intra prediction method shown in FIG. 7C , pixel information of an unavailable neighboring block (e.g., a neighboring block located to the right of the dashed line of Segment E in FIG. 7C ) can be generated based on pixel information of each reference line. Because Segment F itself is generated based on Segment E, there is no need to process Segment F. For example, in some examples, pixel information of a neighboring block located to the right of the dashed line of Segment E can be calculated and generated based on Equation 1 above. A detailed description of the specific calculation method will be omitted here, and reference may be made to the related description of Equation 1.

[0157] For example, a video data processing method according to at least one embodiment of the present disclosure may remove information dependency of a current video block on unavailable neighboring blocks during video encoding and decoding.

[0158] For example, in at least one embodiment of the present disclosure, for step S102, performing a conversion between the current video block of the current video frame and the video bitstream may include an encoding process and a decoding process. For example, in some examples, the received bitstream is entirely decoded for display. Further, for example, in some examples, when only a portion is to be displayed on a display terminal, e.g., the display terminal has a roll-up display as shown in FIG. 1, only a portion of the received bitstream needs to be decoded, thereby reducing the use of decoding resources and improving video encoding and decoding efficiency.

[0159] FIG. 11 is a schematic diagram of another method for processing video data in accordance with at least one embodiment of the present disclosure.

[0160] For example, at least one embodiment of the present disclosure provides another video data processing method 30. The video data processing method 30 can be applied to various application scenarios related to video decoding (i.e., applied to the decoding side). For example, as shown in FIG. 11, the video data processing method 30 includes the following operations S301 to S303.

[0161] Step S301: Receive a video bitstream.

[0162] Step S302: Determine that a current video block of a video is to be encoded or decoded using a first intra-prediction mode.

[0163] Step S303: Based on the determination, decode the bitstream, and in the first intra prediction mode, the reference pixels used by the current video block exclude the pixels of the neighboring block to the upper right of the current video block.

[0164] For example, in at least one embodiment of the present disclosure, in response to a current video frame including a first display partition to be displayed and a second display partition that does not need to be displayed, an area to be decoded corresponding to the first display partition is obtained, and the bitstream is partially decoded.

[0165] Since only the first display partition to be displayed needs to be decoded, it is necessary to limit the decoding area in the decoding process. For example, in the embodiment of the present disclosure, the decoding area is limited by the boundary of the coding unit, or the coding unit is used as the unit of the decoding area. Note that in the embodiment of the present disclosure, the coding unit is used as an example of a coding tree unit (CTU).

[0166] For example, in some instances, the decoding area is limited to the boundary of the coding tree unit (CTU) of the first display partition, and there is no need to decode to the right or below the boundary, thereby saving decoding resources and improving encoding and decoding efficiency.

[0167] For example, in at least one embodiment of the present disclosure, the area to be decoded corresponding to the first display partition can be determined based on the video encoding direction, the partition direction between the first display partition and the second display partition, the number of pixels in the first display partition, and the size of the CTU.

[0168] For example, in at least one embodiment of the present disclosure, in response to the video coding direction being perpendicular to the partition direction, the number of CTUs for each line of the area to be decoded is determined by applying a function to the ratio between the number of pixels in the first display partition and the size of the CTU.

[0169] For example, in the example shown in Figure 10A, when the rotation axis direction of the winding display (i.e., the division direction of the current video frame) is perpendicular to the encoding direction of the video, the right screen of the current video frame of the video is wound, and the area to the left of the rotation axis is the area to be decoded. Therefore, it is necessary to calculate the number n of CTUs required for each line of the area to be decoded.

[0170] For example, in some examples, the number of CTUs, n, is calculated according to Equation 2, as follows:

[0171]

number

[0172] In Equation 2, ceil() represents a round-up function, l represents the number of pixels in the partition to be displayed (first display partition), and CTU_size represents the size of the CTU. For example, the size of the CTU may be 32x32, 64x64, 128x128, etc. The embodiments of the present disclosure are not limited thereto and can be set according to actual needs.

[0173] For example, in at least one embodiment of the present disclosure, in response to the video coding direction being parallel to the partition direction, the number of CTU lines in the area to be decoded is determined by applying a function to the ratio between the number of pixels in the first display partition and the size of the coding tree unit (CTU).

[0174] For example, in the example shown in Figure 10B, when the rotation axis direction of the winding display (i.e., the division direction of the current video frame) is parallel to the encoding direction of the video, the lower screen of the current video frame of the video is wound, and the area above the rotation axis is the area to be decoded. Therefore, it is necessary to calculate the number T of CTU lines in the area to be decoded.

[0175] For example, in some instances, the quantity T of the CTU line is calculated according to Equation 3, as follows:

[0176]

number

[0177] In Equation 3, ceil() represents a round-up function, l represents the number of pixels in the partition to be displayed (first display partition), and CTU_size represents the size of the CTU. For example, the size of the CTU may be 32x32, 64x64, 128x128, etc. The embodiments of the present disclosure are not limited thereto and can be set according to actual needs.

[0178] For example, in at least one embodiment of the present disclosure, a non-decoded area (corresponding to the second display partition) other than the area to be decoded may be filled with a default pixel value, such as 0 pixels. Of course, other pixel values ​​may be used for filling, and the embodiments of the present disclosure are not limited to this and may be set according to actual needs. In this way, the efficiency of video encoding and decoding can be improved, the encoding and decoding process can be simplified, and product energy can be saved.

[0179] For example, in at least one embodiment of the present disclosure, the decoding side can determine whether the video data processing method 10 / 30 is applied to the current video and the corresponding video expansion direction based on the received video bitstream. For example, in some examples, when the received bitstream includes the syntax element "enhanced_tile_enabled_hor" (or the value of the syntax element is 1), the current video applies the video data processing method 10 / 30, and the video expansion direction is horizontal (e.g., from left to right). Note that in the embodiment of the present disclosure, the application of the video data processing method 10 / 30 during the decoding process is not only determined based on the relevant syntax element in the received bitstream, but also takes into account the actual situation of the display terminal. For example, in some examples, when the video display format of the display terminal does not match the video expansion format identified in the bitstream, the video data processing method 10 / 30 is not applied. For example, when a relevant syntax element in the bitstream indicates that the current video applies the above video data processing method 10 / 30 and the video expansion direction is horizontal, and at the same time, when the video display mode of the display terminal is vertically rewinding or unwinding, it is determined that the enhanced tile display mode is not applied to the current video.Furthermore, when a relevant syntax element in the bitstream indicates that the above video data processing method 10 / 30 is applied to the current video and the video expansion direction is horizontal, and at the same time, when the video display mode of the display terminal is normal display (e.g., full-screen display) and no rewinding or unwinding is required, it is determined that the above video data processing method 10 / 30 is not applied to the current video.The embodiments of the present disclosure are not specifically limited thereto and can be configured according to actual situations.

[0180] For example, in at least one embodiment of the present disclosure, when the display terminal is fully wound up, i.e., when there is no area that needs to be displayed, the decoding area can still be determined based on the above Equations 2 and 3 (e.g., based on the number of pixels in the partition to be displayed and the CTU size indicated by the syntax element). Figure 12 is a schematic block diagram of a video encoding and decoding system in an all-intra configuration according to at least one embodiment of the present disclosure.

[0181] For example, in at least one embodiment of the present disclosure, a general description of the video encoding / decoding system in FIG. 12 may refer to the related descriptions of FIGS. 2 to 4, and a detailed description thereof will be omitted here. In an embodiment of the present disclosure, the encoding process is adjusted in the intra prediction unit. For example, the range from which a current video block selects reference pixels is restricted, eliminating dependency on the encoding information of the neighboring block to the upper right of the current video block. The encoding process is adjusted in the video data decoding unit. For example, a region to be decoded is set, and only the region to be decoded is decoded, thereby reducing consumption of decoding resources for portions not displayed and improving encoding / decoding efficiency.

[0182] FIG. 13 is a schematic flow chart of a method for processing video data in an all-intra configuration in accordance with at least one embodiment of the present disclosure.

[0183] For example, at least one embodiment of the present disclosure provides a video data processing method, as shown in Figure 13. The video data processing method includes steps S201 to S206.

[0184] Step S201: Use an encoding process that limits the reference pixel range of the current video block.

[0185] Step S202: Obtain the number of unwound pixels of the roll-up display.

[0186] Step S203: The decoding side receives a video bitstream.

[0187] Step S204: Set a decoding target area based on the rotation axis direction of the roll-up display and the video encoding direction.

[0188] Step S205: Decode the set area, and fill in the undecoded area.

[0189] Step S206: The data is transmitted to the display terminal and displayed.

[0190] Note that the specific operations of steps S201 to S206 shown in FIG. 13 have all been described in detail above, and so detailed description thereof will be omitted here.

[0191] Therefore, a video data processing method according to at least one embodiment of the present disclosure can partially decode a video bitstream based on the area to be displayed, thereby reducing the consumption of decoding resources for the non-displayed portion and improving the encoding and decoding efficiency.

[0192] It should be noted that in the embodiments of the present disclosure, the order in which the steps of the video data processing method 10 are performed is not limited, and although the steps are described above in a specific order, this does not limit the embodiments of the present disclosure. The steps of the video data processing method 10 may be performed serially or in parallel, which can be determined according to actual needs. For example, the video data processing method 10 may include more or fewer steps, and the embodiments of the present disclosure are not limited thereto.

[0193] FIG. 14 is a schematic block diagram of a video data processing apparatus in accordance with at least one embodiment of the present disclosure.

[0194] For example, at least one embodiment of the present disclosure provides a video data processing device 40, as shown in FIG. 14 . The video data processing device 40 includes a determination module 401 and an execution module 402. For example, the determination module 401 is configured to determine that a current video block of a video is encoded or decoded using a first intra-prediction mode. For example, the determination module 401 may implement step S101, and specific implementation methods thereof may refer to the related description of step S101, and detailed descriptions thereof will be omitted here. The execution module 402 is configured to perform conversion between the current video block and the video bitstream based on the determination. In the first intra-prediction mode, reference pixels used by the current video block exclude pixels of a neighboring block to the upper right of the current video block. For example, the execution module 402 may implement step S102, and specific implementation methods thereof may refer to the related description of step S102, and detailed descriptions thereof will be omitted here.

[0195] It should be noted that the determination module 401 and the execution module 402 can be realized by software, hardware, firmware, or any combination thereof, for example, as a determination circuit 401 and an execution circuit 402, respectively, and the embodiments of the present disclosure do not limit these specific embodiments.

[0196] It should be understood that the video data processing device 40 according to at least one embodiment of the present disclosure can achieve technical effects similar to those of the above-described video data processing method 10. For example, in the video data processing device 40 according to at least one embodiment of the present disclosure, the above-described method can partially decode a bitstream based on the area that actually needs to be displayed, thereby reducing the consumption of decoding resources for the non-displayed portion and improving the encoding and decoding efficiency.

[0197] In the embodiments of the present disclosure, the video data processing device 40 may include more or fewer circuits or units, and the connection relationships between the circuits or units are not limited and can be determined according to actual needs. The specific configuration of each circuit is not limited and may be configured by analog devices, digital chips, or other applicable methods based on circuit principles.

[0198] For example, at least one embodiment of the present disclosure further provides a display device, including a video data processing device and a roll-up display. The video data processing device is configured to decode a received bitstream based on the method according to the at least one embodiment and transmit the decoded pixel values ​​to the roll-up display for display. For example, in some examples, when the roll-up display is fully unfolded and there is no non-display area, the video data processing device fully decodes the received bitstream. Furthermore, in some other examples, when the roll-up display includes a rolled-up portion and an unfolded portion, i.e., there is a display area and a non-display area, as shown in FIG. 1, the video data processing device partially decodes the received bitstream.

[0199] For example, in at least one embodiment of the present disclosure, in response to the rollable display including a display area and a non-display area during operation, the video data processing device decodes the bitstream based on the size of the display area. For example, as shown in FIG. 1, when the rollable display is in a partially unfolded state, the video data processing device only needs to decode content corresponding to the display area. For example, the video data processing device can determine the number of pixels corresponding to the display area based on the size of the display area, thereby determining the area to be decoded. The operation of determining the area to be decoded has already been described in detail above, and will not be described in detail here.

[0200] For example, in at least one embodiment of the present disclosure, the display device further includes a winding status determination device in addition to the video data processing device and the winding display. For example, the winding status determination device is configured to detect the size of a display area of ​​the winding display and transmit the size of the display area to the video data processing device, so that the video data processing device decodes the bitstream based on the size of the display area. Note that the winding status determination device can be realized by software, hardware, firmware, or any combination thereof, and may be realized, for example, as a winding status determination circuit. The embodiments of the present disclosure do not limit the specific embodiment of the winding status determination device.

[0201] It should be noted that the embodiments of the present disclosure do not limit the type of display device. For example, the display device may be a mobile terminal, a computer, a tablet PC, a smart watch, a television, etc., and the embodiments of the present disclosure are not limited thereto. Similarly, the embodiments of the present disclosure do not limit the type of rollable display. For example, in the embodiments of the present disclosure, the rollable display may be any type of display screen with a variable display area, including, but not limited to, the rollable display type shown in FIG. 1. For example, in the embodiments of the present disclosure, the video data processing device included in the display device may be implemented as the video data processing device 40 / 90 / 600, etc., referred to in the present disclosure, and the embodiments of the present disclosure are not limited to the specific embodiment of the video data processing device.

[0202] It should be noted that in the embodiments of the present disclosure, the display device may include more or fewer circuits or units, and the connection relationships between each circuit or unit are not limited and can be determined according to actual needs. The specific configuration manner of each circuit is not limited and may be configured by analog devices, digital chips, or other applicable methods based on circuit principles.

[0203] FIG. 15 is a schematic block diagram of another video data processing apparatus in accordance with at least one embodiment of the present disclosure.

[0204] At least one embodiment of the present disclosure further provides a video data processing device 90. As shown in FIG. 15 , the video data processing device 90 includes a processor 910 and a memory 920. The memory 920 includes one or more computer program modules 921. The one or more computer program modules 921 are stored in the memory 920 and configured to be executed by the processor 910, the one or more computer program modules 921 including instructions for performing a video data processing method 10 according to at least one embodiment of the present disclosure, which, when executed by the processor 910, can perform one or more steps of the video data processing method 10 according to at least one embodiment of the present disclosure. The memory 920 and the processor 910 can be connected to each other via a bus system and / or other type of connection mechanism (not shown).

[0205] For example, the processor 910 may be a central processing unit (CPU), a digital signal processor (DSP), or other type of processing unit having data processing capabilities and / or program execution capabilities, such as a field programmable gate array (FPGA), etc. For example, the central processing unit (CPU) may have an X86 or ARM architecture, etc. The processor 910 may be a general-purpose processor or a special-purpose processor, and may control other components in the video data processing device 90 to perform desired functions.

[0206] For example, the memory 920 may include any combination of one or more computer program products, which may include various types of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules 921 may be stored in the computer-readable storage medium, and the processor 910 may operate the one or more computer program modules 921 to realize various functions of the video data processing device 90. The computer-readable storage medium may also store various application programs, various data, and various data used and / or generated by the application programs. For specific functions and technical effects of the video data processing device 90, please refer to the above description of the video data processing method 10, and detailed description thereof will be omitted here.

[0207] FIG. 16 is a schematic block diagram of a further video data processing apparatus in accordance with at least one embodiment of the present disclosure.

[0208] The terminal devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet personal computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. The video data processing device 600 shown in Fig. 16 is merely an example and should not limit the functionality and scope of use of the embodiments of the present disclosure.

[0209] 16, in some examples, a video data processing device 600 includes a processing device (e.g., a central processor, a graphics processor, etc.) 601, which can perform various appropriate operations and processes based on programs stored in a read-only memory (ROM) 602 or loaded from a storage device 608 into a random access memory (RAM) 603. The RAM 603 further stores various programs and data necessary for the operation of the computer system. The processing device 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0210] Input devices 606, including, for example, a touch panel, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 607, including, for example, a liquid crystal display (LCD), speaker, oscillator, etc.; storage devices 608, including, for example, a magnetic tape, hard disk, etc.; and communication devices 609, including, for example, a network interface card such as a LAN card or modem, can be connected to the I / O interface 605. The communication devices 609 can enable the video data processing device 600 to communicate with other devices wirelessly or via wires to exchange data, and perform communication processing via a network such as the Internet. A driver 610 is also connected to the I / O interface 605 as needed. Removable media 611, such as a magnetic disk, optical disk, magneto-optical disk, semiconductor memory, etc., can be attached to the driver 610 as needed, so that a computer program read from the removable media 611 can be installed in the storage device 608 as needed. While FIG. 16 shows the video data processing device 600 including various devices, it should be understood that it is not required to implement or include all of the devices shown. Instead, more or fewer devices can be implemented or included.

[0211] For example, the video data processing device 600 may further include a peripheral interface (not shown), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a Lightning interface, etc. The communication device 609 can communicate with a network and other devices by wireless communication, and the network may be, for example, a wireless network such as the Internet, an intranet, and / or a cellular phone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and technologies, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on the IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, email, protocols for instant messaging and / or short message service (SMS), or any other suitable communication protocol.

[0212] For example, the video data processing device 600 may be any device such as a mobile phone, a tablet computer, a laptop, an e-book reader, a television, etc., or may be any combination of data processing devices and hardware, and the embodiments of the present disclosure are not limited thereto.

[0213] For example, according to an embodiment of the present disclosure, the processes described above with reference to the flowcharts may be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product including a computer program stored on a non-transitory computer-readable medium, the computer program including program code for performing the methods shown in the flowcharts. In such an embodiment, the computer program may be downloaded and installed from a network via the communication device 609, or may be installed from the storage device 608, or may be installed from the ROM 602. When executed by the processing device 601, the computer program performs the video data processing method 10 disclosed in the embodiment of the present disclosure.

[0214] It should be noted that the computer-readable medium of the present disclosure may be a computer-readable signal medium, a computer-readable storage medium, or any combination thereof. The computer-readable storage medium may be, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of the computer-readable storage medium may include, but are not limited to, an electrical connection having one or more conductors, a portable computer magnetic disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In embodiments of the present disclosure, the computer-readable storage medium may be any tangible medium that contains or stores a program, and the program may be used by or in combination with an instruction execution system, apparatus, or device. In embodiments of the present disclosure, the computer-readable signal medium may be a data signal, either in baseband or propagated as part of a carrier wave, having computer-readable program code embodied therein. Such propagated data signals may take various forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may transmit, propagate, or carry a program for use by or in connection with an instruction execution system, apparatus, or device. The program code embodied in the computer-readable medium may be transmitted over any suitable medium, including, but not limited to, wire, optical cable, RF (radio frequency), etc., or any suitable combination of the above.

[0215] The computer-readable medium may be included in the video data processing apparatus 600 or may exist independently of the video data processing apparatus 600 .

[0216] FIG. 17 is a schematic block diagram of a non-transitory readable storage medium in accordance with at least one embodiment of the present disclosure.

[0217]

[0013] Embodiments of the present disclosure further provide a non-transitory readable storage medium. Figure 17 is a schematic block diagram of a non-transitory readable storage medium according to at least one embodiment of the present disclosure. As shown in Figure 17, the non-transitory readable storage medium 70 has stored thereon computer instructions 111 that, when executed by a processor, perform one or more steps of the video data processing method 10 described above.

[0218] For example, non-transitory readable storage medium 70 may be any combination of one or more computer-readable storage media, such as one computer-readable storage medium including computer-readable program code for determining to encode and decode a current video block of a video using a first intra-prediction mode, and another computer-readable storage medium including computer-readable program code for performing conversion between the current video block and a video bitstream based on the determination, where in the first intra-prediction mode, reference pixels used by the current video block exclude pixels of a neighboring block to the upper right of the current video block. Of course, the above program codes may be stored on the same computer-readable medium, and embodiments of the present disclosure are not limited thereto.

[0219] For example, when the program code is read by a computer, the computer can execute the program code stored in the computer storage medium, for example, to perform the video data processing method 10 according to any embodiment of the present disclosure.

[0220] For example, the storage medium may include a memory card of a smartphone, a storage member of a tablet PC, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a flash memory, or any combination of the above storage media, or other applicable storage media. For example, the readable storage medium may be the memory 920 in FIG. 15, the relevant description of which can be referred to above, and a detailed description thereof will be omitted here.

[0221] In this disclosure, unless expressly limited otherwise, the term "plurality" refers to two or more than two.

[0222] Those skilled in the art will readily appreciate other implementations of the present disclosure after considering the specification and practicing the present disclosure. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that comply with the general principles of the present disclosure and include common knowledge or customary techniques well known in the art that are not disclosed in the present disclosure. The specification and examples are exemplary only, with the true scope and spirit of the present disclosure being indicated by the following claims.

[0223] It should be understood that the present disclosure is not limited to the exact construction described above and illustrated in the drawings, and that various modifications and changes can be made without departing from the scope thereof, which is limited only by the appended claims. [Explanation of symbols]

[0224] 10 Video Data Processing Methods 30 Video data processing method 40 Video data processing device 70 Readable storage medium 90 Video data processing device 102 Equipment 104 Video Sources 106 memory 108 Output Interface 110 Computer-Readable Medium 111 Computer Instructions 112 Storage devices 114 File Server 116 Destination Device 118 Integrated display equipment 120 memory 122 Input Interface 200 Video Encoder 200 Encoder 400 Video Decoder 401 Decision Module 402 Execution Module 600 Video data processing device 601 Processing equipment 602 Dedicated memory (ROM) 603 Random Access Memory (RAM) 604 Bus 605 Output (I / O) Interface 606 Input Device 607 Output Device 608 Storage device 609 Communication Equipment 610 Driver 611 Removable Media 910 processor 920 memory 921 Computer Program Modules 1000 Video Encoding and Decoding System

Claims

1. 1. A method for processing video data, comprising: determining, for a current video block of a video, to encode and decode using a first intra-prediction mode; performing a conversion between the current video block and the video bitstream based on the determination; In the first intra prediction mode, the reference pixels used by the current video block exclude pixels of a neighboring block to the upper right of the current video block.

2. 10. The method of claim 1, wherein in the first intra-prediction mode, reference pixels for the current video block are determined based on availability of a first neighboring block of the current video block.

3. determining reference pixels for the current video block based on availability of first neighboring blocks of the current video block; The method of claim 2 , comprising determining availability of the first neighboring block based on a position of the first neighboring block and a position of the current video block.

4. determining availability of the first neighboring block based on the position of the first neighboring block and the position of the current video block; 4. The method of claim 3, comprising determining that the first neighboring block is unavailable in response to the first neighboring block being located to a top right side of the current video block.

5. determining reference pixels for the current video block based on availability of the first neighboring block; 5. The method of claim 2, further comprising: in response to the first neighboring block being unavailable, determining pixel values ​​of the first neighboring block based on other neighboring blocks of the current video block other than the first neighboring block.

6. determining pixel values ​​of the first neighboring block based on neighboring blocks other than the first neighboring block of the current video block, 6. The method of claim 5, comprising determining pixel values ​​of the first neighboring block based on an upper left neighboring block and at least one upper neighboring block of the current video block.

7. determining pixel values ​​of the first neighboring block based on an upper left neighboring block and at least one upper neighboring block of the current video block; 7. The method of claim 6, further comprising: in response to satisfying a first condition, determining pixel values ​​of the first neighboring block based on pixel values ​​of a rightmost block of the at least one upper neighboring block and pixel values ​​of the upper-left neighboring block.

8. determining pixel values ​​of the first neighboring block based on pixel values ​​of a rightmost block of the at least one upper neighboring block and pixel values ​​of the upper left neighboring block, 8. The method of claim 7, further comprising: determining pixel values ​​of the first neighboring block by linear interpolation using pixel values ​​of a rightmost block of the at least one upper neighboring block and pixel values ​​of the upper left neighboring block.

9. 9. The method according to claim 7 or 8, wherein the first condition includes that a difference between an average value of pixel values ​​of the upper left neighboring block and the rightmost block of the at least one upper neighboring block and an average value of pixel values ​​of all blocks of the at least one upper neighboring block is less than a threshold value.

10. The method of claim 9 , wherein the threshold is equal to bitdepth / 2, where bitdepth represents the bit depth of the video.

11. determining pixel values ​​of the first neighboring block based on an upper left neighboring block of the current video block and the at least one upper neighboring block; 11. The method of claim 6, further comprising: in response to a first condition not being satisfied, determining pixel values ​​of the first neighboring block based on pixel values ​​of the upper left neighboring block.

12. The step of determining pixel values ​​of the first neighboring block based on pixel values ​​of the upper left neighboring block includes:

12. The method of claim 11, comprising setting pixel values ​​of the first neighboring block equal to pixel values ​​of the upper left neighboring block.

13. The method of any one of claims 1 to 12, wherein the first intra prediction mode comprises a planar intra prediction mode, a DC intra prediction mode, an angular intra prediction mode or a multi-reference line intra prediction mode.

14. 1. A method for processing video data, comprising: receiving a video bitstream; determining that a current video block of the video is to be encoded and decoded using a first intra-prediction mode; and decoding the bitstream based on the determination; In the first intra prediction mode, the reference pixels used by the current video block exclude pixels of a neighboring block to the upper right of the current video block.

15. The step of decoding the bitstream comprises: determining a region to be decoded corresponding to a first display partition in response to a current video frame of the video including a first display partition to be displayed and a second display partition that does not need to be displayed; and decoding the bitstream based on the region to be decoded.

16. The step of determining an area to be decoded corresponding to the first display partition includes:

16. The method of claim 15, comprising determining the region to be decoded based on the coding direction of the video, the partition direction between the first display partition and the second display partition, the number of pixels in the first display partition, and the size of a coding unit of the video.

17. The step of determining the area to be decoded based on the coding direction, the partition direction, the number of pixels of the first display partition, and the size of the coding unit includes:

17. The method of claim 16, comprising, in response to the video encoding direction being perpendicular to the partition direction, determining the number of encoding / decoding units for each line of the area to be decoded by applying a function to the ratio between the number of pixels of the first display partition and the size of the encoding unit.

18. The step of determining the area to be decoded based on the coding direction, the partition direction, the number of pixels of the first display partition, and the size of the coding unit includes:

17. The method of claim 16, comprising a step of determining the number of lines of the encoding / decoding unit of the area to be decoded by applying a function to the ratio between the number of pixels of the first display partition and the size of the encoding unit in response to the encoding direction being parallel to the partition direction.

19. 19. The method of claim 17 or 18, wherein the function is a round-up function.

20. 1. A video data processing device, comprising: a decision module configured to decide to encode and decode a current video block of a video using a first intra-prediction mode; an execution module configured to perform a conversion between the current video block and the video bitstream based on the determination; In the first intra prediction mode, the reference pixels used by the current video block exclude pixels of a neighboring block to the upper right of the current video block.

21. a display device, the display device including a video data processing device and a roll-up display; A display device, wherein the video data processing device is configured to decode a received bitstream according to the video data processing method of any one of claims 1 to 19, and transmit the decoded pixel values ​​to the roll-up display for display.

22. 22. The display device of claim 21, responsive to the wrap display including a display area and a non-display area during operation, the video data processor decoding the bitstream based on the size of the display area.

23. 22. The display device of claim 21, further comprising a winding state determination device configured to detect a size of a display area of ​​the winding display and transmit the size of the display area to the video data processing device, so that the video data processing device decodes the bitstream based on the size of the display area.

24. 1. A video data processing device, comprising: a processor; a memory containing one or more computer program modules; A video data processing device, wherein the one or more computer program modules are stored in the memory and configured to be executed by the processor, the one or more computer program modules including instructions for performing the video data processing method of any one of claims 1 to 19.

25. A computer readable storage medium having stored thereon computer instructions which, when executed by a processor, implement the steps of the video data processing method of any one of claims 1 to 19.

Images