MINIMUM PROCESS GRID FOR INTER PREDICTION-RELATED VIDEO CODING PROCESSES - Patent application

Abstract

The video decoder may be configured to perform motion compensation for the block of video data using a first process grid size; determine a second process grid size for a subsequent inter-prediction-related video coding process, the second process grid size being larger than the first process grid size; determine whether the block of video data has at least one sample with a motion vector that differs from at least one other sample in the block of the second process grid size; and, in response to determining that the block of video data has at least one sample with a motion vector that differs from at least one other sample in the block of the second process grid size, perform the subsequent inter-prediction-related video coding process for the block of video data using the second process grid size; and output a decoded version of the block of video data.

Description

[Technical Field]

[0001]

[0001] This application claims priority to U.S. Patent Application No. 18 / 532,889, filed December 7, 2023, and U.S. Provisional Patent Application No. 63 / 386,609, filed December 8, 2022, the entire contents of each of which are incorporated herein by reference. U.S. Patent Application No. 18 / 532,889, filed December 7, 2023, claims the benefit of U.S. Provisional Patent Application No. 63 / 386,609, filed December 8, 2022.

[0002]

[0002] This disclosure relates to video encoding and decoding. [Background technology]

[0003]

[0003] Digital video capabilities can be incorporated into a wide range of devices, including digital televisions, digital direct broadcast systems, wireless broadcast systems, personal digital assistants (PDAs), laptop or desktop computers, tablet computers, e-book readers, digital cameras, digital recording devices, digital media players, video gaming devices, video game consoles, cellular or satellite wireless telephones, so-called "smartphones," video teleconferencing devices, video streaming devices, and the like. Digital video devices implement video coding techniques such as those described in standards defined by MPEG-2, MPEG-4, ITU-T H.263, ITU-T H.264 / MPEG-4, Part 10, Advanced Video Coding (AVC), ITU-T H.265 / High Efficiency Video Coding (HEVC), ITU-T H.266 / Versatile Video Coding (VVC), and extensions to such standards, as well as proprietary video codecs / formats such as AOMedia Video 1 (AV1) developed by the Alliance for Open Media. By implementing such video coding techniques, video devices may transmit, receive, encode, decode, and / or store digital video information more efficiently.

[0004]

[0004] Video coding techniques include spatial (intra-picture) prediction and / or temporal (inter-picture) prediction to reduce or remove redundancy inherent in video sequences. In block-based video coding, a video slice (e.g., a video picture or a portion of a video picture) may be partitioned into video blocks, which are also sometimes referred to as coding tree units (CTUs), coding units (CUs), and / or coding nodes. Video blocks in an intra-coded (I) slice of a picture are encoded using spatial prediction with respect to reference samples in neighboring blocks in the same picture. Video blocks in an inter-coded (P or B) slice of a picture may use spatial prediction with respect to reference samples in neighboring blocks in the same picture or temporal prediction with respect to reference samples in other reference pictures. A picture may be referred to as a frame, and a reference picture may be referred to as a reference frame. Summary of the Invention

[0005] This disclosure describes techniques related to inter-prediction in video codecs. More specifically, this disclosure describes techniques related to determining process grid sizes for certain inter-prediction-related video coding processes, such as local illumination compensation (LIC) and out-of-picture boundary (OOB) checking.

[0006]

[0006] The process grid or process grid size generally refers to the shape and number of samples that are processed together. In certain inter-prediction processes, such as regular motion compensation or affine motion compensation, it may be desirable to utilize a relatively small process grid, such as 1x1 or 2x2. However, for subsequent inter-prediction-related video coding processes, the small process grid may be unnecessarily computationally complex or otherwise too small to produce the desired results.

[0007]

[0007] Accordingly, this disclosure describes techniques for configuring a video coder to perform motion compensation for a block of video data using a first process grid size, and, in response to determining that the block of video data has at least one sample having a motion vector that differs from at least one other sample in the block of a second process grid size, for a subsequent inter-prediction process, perform a subsequent inter-prediction-related video coding process for the block of video data using a second process grid size. By using two different process grid sizes for the motion compensation and the subsequent inter-prediction-related video coding process, the techniques of this disclosure can prevent motion vector mismatch and reduce complexity when performing the motion compensation and the subsequent inter-prediction-related video coding process.

[0008]

[0008] According to one embodiment of the present disclosure, a method for decoding video data includes performing motion compensation for a block of video data using a first process grid size; determining a second process grid size for a subsequent inter-prediction-related video coding process, the second process grid size being larger than the first process grid size; determining whether the block of video data has at least one sample having a motion vector that is different from at least one other sample in the block of the second process grid size; performing the subsequent inter-prediction-related video coding process for the block of video data using the second process grid size in response to determining that the block of video data has at least one sample having a motion vector that is different from at least one other sample in the block of the second process grid size; and outputting a decoded version of the block of video data.

[0009]

[0009] According to one embodiment of the present disclosure, a device for decoding video data includes one or more memory units configured to store the video data; and one or more processors implemented in circuitry coupled to the one or more memory units, the one or more processors configured to: perform motion compensation for a block of video data using a first process grid size; determine a second process grid size for a subsequent inter-prediction related video coding process, the second process grid size being larger than the first process grid size; determine whether the block of video data has at least one sample having a motion vector that differs from at least one other sample in the block of the second process grid size; and, in response to determining that the block of video data has at least one sample having a motion vector that differs from at least one other sample in the block of the second process grid size, perform the subsequent inter-prediction related video coding process for the block of video data using the second process grid size and output a decoded version of the block of video data.

[0010]

[0010] A computer-readable storage medium stores instructions that, when executed by one or more processors, cause the one or more processors to perform motion compensation for a block of video data using a first process grid size, determine a second process grid size for a subsequent inter-prediction associated video coding process, the second process grid size being larger than the first process grid size, determine whether the block of video data has at least one sample having a motion vector that is different from at least one other sample in the block of the second process grid size, and, in response to determining that the block of video data has at least one sample having a motion vector that is different from at least one other sample in the block of the second process grid size, perform a subsequent inter-prediction associated video coding process for the block of video data using the second process grid size, and output a decoded version of the block of video data.

[0011]

[0011] According to one embodiment of the present disclosure, a device for decoding video data includes means for performing motion compensation for a block of video data using a first process grid size; means for determining a second process grid size for a subsequent inter-prediction-related video coding process, the second process grid size being larger than the first process grid size; means for determining whether the block of video data has at least one sample having a motion vector that is different from at least one other sample in the block of the second process grid size; means for performing the subsequent inter-prediction-related video coding process for the block of video data using the second process grid size in response to determining that the block of video data has at least one sample having a motion vector that is different from at least one other sample in the block of the second process grid size; and means for outputting a decoded version of the block of video data.

[0012] The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will become apparent from the description, drawings, and claims. [Brief explanation of the drawings]

[0013] [Figure 1]

[0013] FIG. 1 is a block diagram illustrating an example video encoding and decoding system that may implement the techniques of this disclosure. [Figure 2]

[0014] 10 illustrates an example of affine motion for a block using a six-parameter affine motion model. [Figure 3]

[0015] 10 illustrates an example of affine motion for a block using a four-parameter affine motion model. [Figure 4]

[0016] 1 illustrates one embodiment of motion vectors for luma and chroma blocks for motion compensation. [Figure 5]

[0017] 1 illustrates an example of motion vectors for luma and chroma out-of-block-boundary (OOB) testing. [Figure 6]

[0018] 1 illustrates an example of pixel-based OOB inspection. [Figure 7]

[0019] 1 illustrates an example of pixel-based local illumination compensation (LIC) reference template sample derivation. [Figure 8]

[0020] 1 illustrates an example of sub-block based OOB inspection. [Figure 9]

[0021] 10 illustrates an example of sub-block-based LIC reference template sample derivation. [Figure 10]

[0022] 1 is a block diagram illustrating an example video encoder capable of implementing the techniques of this disclosure. [Figure 11]

[0023] FIG. 2 is a block diagram illustrating an example video decoder capable of performing the techniques of this disclosure. [Figure 12]

[0024] 10 is a flowchart illustrating an example process for encoding a current block, in accordance with techniques of this disclosure. [Figure 13]

[0025] 10 is a flowchart illustrating an example process for decoding a current block in accordance with techniques of this disclosure. [Figure 14]

[0026] 10 is a flowchart illustrating an example process for decoding a current block in accordance with techniques of this disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0014]

[0027] Video coding (e.g., video encoding and / or video decoding) typically involves predicting blocks of video data from either already coded blocks of video data in the same picture (e.g., intra prediction) or already coded blocks of video data in a different picture (e.g., inter prediction). In some instances, a video encoder also calculates residual data by comparing the predicted block with the original block. The residual data thus represents the difference between the predicted block and the original block. To reduce the number of bits required to signal the residual data, the video encoder transforms and quantizes the residual data and signals the transformed and quantized residual data in an encoded bitstream. The compression achieved by the transform and quantization process may be lossy, meaning that the transform and quantization process may introduce distortion into the decoded video data.

[0015]

[0028] A video decoder decodes and adds the residual data to the predictive block to generate a reconstructed video block that more closely matches the original video block than the predictive block alone. Due to losses introduced by transforming and quantizing the residual data, the initial reconstructed block may have distortions or artifacts. One common type of artifact or distortion is called blockiness, where boundaries of blocks used to code the video data are visible. To further improve the quality of the decoded video, the video decoder may perform one or more filtering operations on the reconstructed video block, such as deblocking filtering, sample adaptive offset (SAO) filtering, and adaptive loop filtering (ALF).

[0016]

[0029] This disclosure describes techniques related to inter-prediction in video codecs. More specifically, this disclosure describes techniques related to determining process grid sizes for certain inter-prediction-related video coding processes, such as local lighting compensation (LIC) and out-of-picture-boundary (OOB) checks.

[0017]

[0030] The process grid or process grid size generally refers to the shape and number of samples that are processed together. In certain inter-prediction processes, such as regular motion compensation or affine motion compensation, it may be desirable to utilize a relatively small process grid, such as a 1×1 or 2×2. However, for subsequent inter-prediction-related video coding processes, a small process grid may be unnecessarily computationally complex or otherwise too small to produce the desired results.

[0018]

[0031] Accordingly, this disclosure describes techniques for configuring a video coder to perform motion compensation for a block of video data using a first process grid size, and, for a subsequent inter-prediction process, to perform a subsequent inter-prediction-related video coding process for the block of video data using a second process grid size in response to determining that the block of video data has at least one sample having a motion vector that differs from at least one other sample in the block of a second process grid size. By using two different process grid sizes for the motion compensation and the subsequent inter-prediction-related video coding process, the techniques of this disclosure can prevent motion vector mismatch and reduce complexity when performing the motion compensation and the subsequent inter-prediction-related video coding process.

[0019]

[0032] 1 is a block diagram illustrating an example video encoding and decoding system 100 capable of implementing the techniques of this disclosure. The techniques of this disclosure are generally directed to coding (encoding and / or decoding) video data. Generally, video data includes any data for processing video. Thus, video data may include raw uncoded video, coded video, decoded (e.g., reconstructed) video, and video metadata, such as signaling data.

[0020]

[0033] 1 , in this example, system 100 includes a source device 102 that provides encoded video data to be decoded and displayed by a destination device 116. Specifically, source device 102 provides the video data to destination device 116 via a computer-readable medium 110. Source device 102 and destination device 116 may be or include any of a wide range of devices, such as a desktop computer, a notebook (i.e., laptop) computer, a mobile device, a tablet computer, a set-top box, a telephone handset such as a smartphone, a television, a camera, a display device, a digital media player, a video gaming console, a video streaming device, a broadcast receiver device, etc. In some cases, source device 102 and destination device 116 may be capable of wireless communication and thus may be referred to as wireless communication devices.

[0021]

[0034] In the example of FIG. 1 , source device 102 includes video source 104, memory 106, video encoder 200, and output interface 108. Destination device 116 includes input interface 122, video decoder 300, memory 120, and display device 118. According to this disclosure, video encoder 200 of source device 102 and video decoder 300 of destination device 116 can be configured to apply techniques for determining a minimum process grid for an inter-prediction-related video coding process. Thus, source device 102 represents an example of a video encoding device, while destination device 116 represents an example of a video decoding device. In other examples, the source device and destination device may include other components or configurations. For example, source device 102 may receive video data from an external video source, such as an external camera. Similarly, destination device 116 may interface with an external display device rather than including an integrated display device.

[0022]

[0035] System 100 as shown in FIG. 1 is merely an example. In general, any digital video encoding and / or decoding device can perform techniques for determining a minimum process grid for an inter-prediction-related video coding process. Source device 102 and destination device 116 are merely examples of coding devices, such that source device 102 generates coded video data that destination device 116 transmits to source device 102. This disclosure refers to devices that perform coding (encoding and / or decoding) of data as “coding” devices. Accordingly, video encoder 200 and video decoder 300 represent examples of coding devices, specifically, video encoders and video decoders, respectively. In some examples, source device 102 and destination device 116 may operate in a substantially symmetrical manner, such that source device 102 and destination device 116 each include video encoding and decoding components. Thus, system 100 may support unidirectional or bidirectional video transmission between source device 102 and destination device 116, e.g., for video streaming, video playback, video broadcasting, or video telephony.

[0023]

[0036] Generally, video source 104 represents a source of video data (i.e., raw, unencoded video data) and provides a continuous series of pictures (also called “frames”) of the video data to video encoder 200, which encodes the picture data. Video source 104 of source device 102 may include a video capture device such as a video camera, a video archive containing previously captured raw video, and / or a video feed interface that receives video from a video content provider. As a further alternative, video source 104 may generate computer-graphics-based data as source video, or a combination of live video, archived video, and computer-generated video. In each case, video encoder 200 encodes the captured, pre-captured, or computer-generated video data. Video encoder 200 may reorder the pictures from the order in which they were received (sometimes referred to as “display order”) to a coding order for coding. Video encoder 200 may generate a bitstream containing the encoded video data. Source device 102 may then output the encoded video data via output interface 108 to computer-readable medium 110, for receipt and / or retrieval by input interface 122 of destination device 116, for example.

[0024]

[0037] Memory 106 of source device 102 and memory 120 of destination device 116 represent general-purpose memory. In some examples, memory 106, 120 may store raw video data, e.g., raw video from video source 104 and raw decoded video data from video decoder 300. Additionally or alternatively, memory 106, 120 may store software instructions executable by, e.g., video encoder 200 and video decoder 300, respectively. While memory 106 and memory 120 are shown separate from video encoder 200 and video decoder 300 in this example, it should be understood that video encoder 200 and video decoder 300 may also include internal memory for functionally similar or equivalent purposes. Furthermore, memory 106, 120 may store, e.g., encoded video data output from video encoder 200 and input to video decoder 300. In some examples, portions of memory 106, 120 may be allocated as one or more video buffers, for example, to store raw decoded video data and / or encoded video data.

[0025]

[0038] The computer-readable medium 110 may represent any type of medium or device capable of transferring encoded video data from the source device 102 to the destination device 116. In one example, the computer-readable medium 110 represents a communication medium that enables the source device 102 to transmit encoded video data directly to the destination device 116 in real time, for example, via a radio frequency network or a computer-based network. The output interface 108 may modulate a transmission signal containing the encoded video data, and the input interface 122 may demodulate a received transmission signal in accordance with a communication standard such as a wireless communication protocol. The communication medium may comprise any wireless or wired communication medium, such as the radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network, such as a local area network, a wide area network, or a global network such as the Internet. The communication medium may include routers, switches, base stations, or any other equipment that may be useful for facilitating communication from the source device 102 to the destination device 116.

[0026]

[0039] In some examples, source device 102 may output the encoded data from output interface 108 to storage device 112. Similarly, destination device 116 may access the encoded data from storage device 112 via input interface 122. Storage device 112 may include any of a variety of distributed or locally accessed data storage media, such as a hard drive, a Blu-ray disc, a DVD, a CD-ROM, flash memory, volatile or non-volatile memory, or any other suitable digital storage medium that stores encoded video data.

[0027]

[0040] In some examples, source device 102 may output encoded video data to file server 114 or another intermediate storage device that may store the encoded video data generated by source device 102. Destination device 116 may access the stored video data from file server 114 via streaming or download.

[0028]

[0041] File server 114 may be any type of server device capable of storing encoded video data and transmitting the encoded video data to destination device 116. File server 114 may represent a web server (e.g., for a website), a server configured to provide file transfer protocol services (such as File Transfer Protocol (FTP) or File Delivery over Unidirectional Transport (FLUTE) protocol), a content delivery network (CDN) device, a hypertext transfer protocol (HTTP) server, a Multimedia Broadcast Multicast Service (MBMS) or Enhanced MBMS (eMBMS) server, and / or a network attached storage (NAS) device. The file server 114 may additionally or alternatively implement one or more HTTP streaming protocols, such as Dynamic Adaptive Streaming over HTTP (DASH), HTTP Live Streaming (HLS), Real Time Streaming Protocol (RTSP), HTTP Dynamic Streaming, etc.

[0029]

[0042] Destination device 116 may access the encoded video data from file server 114 through any standard data connection, including an Internet connection. This may include a wireless channel (e.g., a Wi-Fi connection), a wired connection (e.g., a digital subscriber line (DSL), a cable modem, etc.), or a combination of both suitable for accessing encoded video data stored on file server 114. Input interface 122 may be configured to operate according to any one or more of the various protocols mentioned above to retrieve or receive media data from file server 114, or other such protocols to retrieve media data.

[0030]

[0043] Output interface 108 and input interface 122 may represent a wireless transmitter / receiver, a modem, a wired network component (e.g., an Ethernet card), a wireless communication component operating according to any of the various IEEE 802.11 standards, or other physical components. In examples in which output interface 108 and input interface 122 include wireless components, output interface 108 and input interface 122 may be configured to transfer data, such as encoded video data, according to a cellular communication standard, such as 4G, 4G-LTE (Long Term Evolution), LTE-Advanced, 5G, etc. In some examples in which output interface 108 includes a wireless transmitter, output interface 108 and input interface 122 may be configured to transfer data, such as encoded video data, according to other wireless standards, such as the IEEE 802.11 standard, the IEEE 802.15 standard (e.g., ZigBee™), the Bluetooth standard, etc. In some examples, source device 102 and / or destination device 116 may include respective system-on-chip (SoC) devices. For example, source device 102 may include an SoC device that performs the functionality attributed to video encoder 200 and / or output interface 108, and destination device 116 may include an SoC device that performs the functionality attributed to video decoder 300 and / or input interface 122.

[0031]

[0044] The techniques of this disclosure may be applied to video coding supporting any of a variety of multimedia applications, such as over-the-air television broadcast, cable television transmission, satellite television transmission, Internet streaming video transmission such as Dynamic Adaptive Streaming over HTTP (DASH), digital video encoded on a data storage medium, decoding of digital video stored on a data storage medium, or other applications.

[0032]

[0045] The input interface 122 of the destination device 116 receives an encoded video bitstream from the computer-readable medium 110 (e.g., a communications medium, a storage device 112, a file server 114, etc.). The encoded video bitstream may include signaling information defined by the video encoder 200 that is also used by the video decoder 300, such as syntax elements having values ​​that describe the characteristics and / or processing of video blocks or other coded units (e.g., slices, pictures, groups of pictures, sequences, etc.). The display device 118 displays decoded pictures of the decoded video data to a user. The display device 118 may represent any of a variety of display devices, such as a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, or another type of display device.

[0033]

[0046] Although not shown in FIG. 1, in some examples, the video encoder 200 and the video decoder 300 may each be integrated with an audio encoder and / or audio decoder and may include appropriate MUX-DEMUX units or other hardware and / or software to handle multiplexed streams containing both audio and video in a common data stream.

[0034]

[0047] The video encoder 200 and the video decoder 300 may each be implemented as any of a variety of suitable encoder and / or decoder circuits, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware, or any combination thereof. When the techniques are implemented partially in software, a device may store instructions for the software in a suitable non-transitory computer-readable medium and execute the instructions in hardware using one or more processors to implement the techniques of this disclosure. Each of the video encoder 200 and the video decoder 300 may be included in one or more encoders or decoders, any of which may be integrated as part of a combined encoder / decoder (CODEC) in the respective device. Devices including the video encoder 200 and / or the video decoder 300 may implement the video encoder 200 and / or the video decoder 300 in processing circuitry, such as an integrated circuit and / or a microprocessor. Such a device may be a wireless communication device, such as a cellular telephone, or any other type of device described herein.

[0035]

[0048] The video encoder 200 and the video decoder 300 may operate according to a video coding standard such as ITU-T H.265, also known as High Efficiency Video Coding (HEVC), or an extension thereof, such as multiview and / or scalable video coding extensions. Alternatively, the video encoder 200 and the video decoder 300 may operate according to other proprietary or industry standards, such as ITU-T H.266, also known as Generic Video Coding (VVC). In other examples, the video encoder 200 and the video decoder 300 may operate according to a proprietary video codec / format, such as AOMedia Video 1 (AV1), an extension of AV1, and / or a successor version of AV1 (e.g., AV2). In other examples, the video encoder 200 and the video decoder 300 may operate according to other proprietary formats or industry standards. However, the techniques of this disclosure are not limited to any particular coding standard or format. In general, video encoder 200 and video decoder 300 may be configured to perform the techniques of this disclosure in conjunction with any video coding technique that uses inter-predictive coding tools.

[0036]

[0049] Generally, the video encoder 200 and the video decoder 300 may perform block-based coding of pictures. The term “block” generally refers to a structure containing data to be processed (e.g., encoded, decoded, or otherwise used in an encoding and / or decoding process). For example, a block may include a two-dimensional matrix of luminance and / or chrominance data samples. Generally, the video encoder 200 and the video decoder 300 may code video data represented in YUV (e.g., Y, Cb, Cr) format. That is, rather than coding red, green, and blue (RGB) data for picture samples, the video encoder 200 and the video decoder 300 may code luminance and chrominance components, which may include both red and blue chrominance components. In some examples, the video encoder 200 converts received RGB-format data to a YUV representation before encoding, and the video decoder 300 converts the YUV representation to RGB format. Alternatively, pre-processing and post-processing units (not shown) may perform these transformations.

[0037]

[0050] This disclosure may generally refer to coding (e.g., encoding and decoding) a picture as including the process of encoding or decoding data for a picture. Similarly, this disclosure may refer to coding a block of a picture as including the process of encoding or decoding data for the block, e.g., predictive and / or residual coding. A coded video bitstream generally includes a series of values ​​of syntax elements that represent coding decisions (e.g., coding modes) and the partitioning of a picture into blocks. Thus, references to coding a picture or a block should generally be understood as coding values ​​of the syntax elements that form the picture or block.

[0038]

[0051] HEVC defines various blocks, including coding units (CUs), prediction units (PUs), and transform units (TUs). According to HEVC, a video coder (such as video encoder 200) partitions coding tree units (CTUs) into CUs according to a quadtree structure. That is, the video coder partitions CTUs and CUs into four equal, non-overlapping squares, and each node of the quadtree has either zero or four child nodes. A node with no child nodes may be called a "leaf node," and a CU of such a leaf node may include one or more PUs and / or one or more TUs. The video coder may further partition PUs and TUs. For example, in HEVC, a residual quadtree (RQT) represents the partitioning of TUs. In HEVC, a PU represents inter-predicted data, and a TU represents residual data. An intra-predicted CU includes intra-prediction information, such as an intra-mode indication.

[0039]

[0052] As another example, video encoder 200 and video decoder 300 may be configured to operate according to VVC. According to VVC, a video coder (such as video encoder 200) partitions a picture into multiple CTUs. Video encoder 200 may partition the CTUs according to a tree structure, such as a quadtree-binary tree (QTBT) structure or a multi-type tree (MTT) structure. The QTBT structure eliminates the concept of multiple partition types, such as the separation between CUs, PUs, and TUs in HEVC. The QTBT structure includes two levels: a first level partitioned according to quadtree partitioning and a second level partitioned according to binary tree partitioning. The root node of the QTBT structure corresponds to a CTU. The leaf nodes of the binary tree correspond to CUs.

[0040]

[0053] In the MTT partitioning structure, blocks may be partitioned using quadtree (QT) partitioning, binary tree (BT) partitioning, and one or more types of triple tree (TT) (also called ternary tree (TT)) partitioning. A triple tree partitioning or triple tree partitioning is a partitioning in which a block is divided into three sub-blocks. In some examples, a triple tree partitioning or triple tree partitioning divides a block into three sub-blocks without splitting the original block through the center. The partition types in MTT (e.g., QT, BT, and TT) can be symmetric or asymmetric.

[0041]

[0054] When operating according to the AV1 codec, the video encoder 200 and the video decoder 300 may be configured to code video data in blocks. In AV1, the largest coding block that can be processed is called a superblock. In AV1, a superblock can be either 128x128 luma samples or 64x64 luma samples. However, in successor video coding formats (e.g., AV2), a superblock can be defined by a different (e.g., larger) luma sample size. In some examples, a superblock is the top level of a block quadtree. The video encoder 200 may further partition the superblock into smaller coding blocks. The video encoder 200 may partition the superblock and other coding blocks into smaller blocks using square or non-square partitioning. Non-square blocks may include N / 2xN, NxN / 2, N / 4xN, and NxN / 4 blocks. The video encoder 200 and the video decoder 300 may perform separate prediction and transform processes for each of the coding blocks.

[0042]

[0055] AV1 also defines tiles of video data. A tile is a rectangular array of superblocks that may be coded independently of other tiles. That is, video encoder 200 and video decoder 300 may encode and decode coding blocks within a tile, respectively, without using video data from other tiles. However, video encoder 200 and video decoder 300 may perform filtering across tile boundaries. Tiles may be uniform or non-uniform in size. Tile-based coding may enable parallel processing and / or multithreading for encoder and decoder implementations.

[0043]

[0056] In some examples, the video encoder 200 and the video decoder 300 may use a single QTBT or MTT structure to represent each of the luminance and chrominance components, and in other examples, the video encoder 200 and the video decoder 300 may use two or more QTBT or MTT structures, such as one QTBT / MTT structure for the luminance component and another QTBT / MTT structure for both chrominance components (or two QTBT / MTT structures for each chrominance component).

[0044]

[0057] Video encoder 200 and video decoder 300 may be configured to use quadtree partitioning, QTBT partitioning, MTT partitioning, superblock partitioning, or other partitioning structures.

[0045]

[0058] In some examples, a CTU includes a coding tree block (CTB) of luma samples, two corresponding CTBs of chroma samples for a picture having three sample arrays, or a CTB of samples for a picture coded using three separate color planes and syntax structures used to code a monochrome picture or samples. A CTB may be an N×N block of samples for some value of N, partitioned to divide the components into CTBs. A component is a single sample from one of the three arrays (luma and two chroma) that make up a picture in 4:2:0, 4:2:2, or 4:4:4 color format, or a single sample from an array or arrays that make up a picture in monochrome format. In some examples, a coding block is an M×N block of samples for some values ​​of M and N, partitioned to divide the CTB into coding blocks.

[0046]

[0059] Blocks (e.g., CTUs or CUs) may be grouped in various ways within a picture. As an example, a brick may refer to a rectangular region of a CTU row within a particular tile within a picture. A tile may be a rectangular region of CTUs within a particular tile column and a particular tile row within a picture. A tile column refers to a rectangular region of CTUs with a height equal to the height of the picture and a width specified by a syntax element (e.g., in a picture parameter set). A tile row refers to a rectangular region of CTUs with a height specified by a syntax element (e.g., in a picture parameter set) and a width equal to the width of the picture.

[0047]

[0060] In some examples, a tile may be partitioned into multiple bricks, each of which may include one or more CTU rows within the tile. A tile that is not partitioned into multiple bricks may also be referred to as a brick. However, a brick that is a true subset of a tile may not be referred to as a tile. Bricks within a picture may also be arranged as slices. A slice may be an integer number of bricks of a picture that may be contained exclusively within a single network abstraction layer (NAL) unit. In some examples, a slice includes either several complete tiles or only a continuous sequence of complete bricks of one tile.

[0048]

[0061] This disclosure may use "N x N" and "N by N," e.g., 16 x 16 samples or 16 by 16 samples, interchangeably to refer to the sample dimensions of a block (such as a CU or other video block) in the vertical and horizontal dimensions. Generally, a 16 x 16 CU has 16 samples in the vertical direction (y = 16) and 16 samples in the horizontal direction (x = 16). Similarly, an N x N CU generally has N samples in the vertical direction and N samples in the horizontal direction, where N represents a non-negative integer value. Samples within a CU may be arranged in rows and columns. Furthermore, a CU does not necessarily have to have the same number of samples in the horizontal direction as in the vertical direction. For example, a CU may include N x M samples, where M is not necessarily equal to N.

[0049]

[0062] Video encoder 200 encodes video data for a CU that represents prediction and / or residual information and other information. The prediction information indicates how the CU will be predicted to form a predictive block for the CU. The residual information generally represents sample-by-sample differences between the samples of the CU before encoding and the predictive block.

[0050]

[0063] To predict a CU, video encoder 200 may generally form a predictive block for the CU through inter prediction or intra prediction. Inter prediction generally refers to predicting a CU from data of a previously coded picture, and intra prediction generally refers to predicting a CU from previously coded data of the same picture. To perform inter prediction, video encoder 200 may generate a predictive block using one or more motion vectors. Video encoder 200 may generally perform a motion search to identify a reference block that closely matches the CU with respect to the difference between the CU and the reference block, for example. Video encoder 200 may calculate a difference metric using a sum of absolute difference (SAD), a sum of squared differences (SSD), a mean absolute difference (MAD), a mean squared difference (MSD), or other such difference calculation to determine whether the reference block closely matches the current CU. In some examples, video encoder 200 may predict the current CU using unidirectional prediction or bidirectional prediction.

[0051]

[0064] Some examples of VVC also provide an affine motion compensation mode, which may be considered an inter-prediction mode. In affine motion compensation mode, video encoder 200 may determine two or more motion vectors that represent non-translational motion, such as zooming in or out, rotation, perspective movement, or other irregular motion types.

[0052]

[0065] To perform intra prediction, video encoder 200 may select an intra prediction mode to generate a predicted block. Some examples of VVC provide 67 intra prediction modes, including various directional modes, as well as a planar mode and a DC mode. Generally, video encoder 200 selects an intra prediction mode that describes neighboring samples for a current block (e.g., a block of a CU) and predicts samples of the current block therefrom. Assuming that video encoder 200 codes CTUs and CUs in raster scan order (left to right, top to bottom), such samples may generally be above, above and to the left, or to the left of the current block in the same picture as the current block.

[0053]

[0066] The video encoder 200 encodes data representing a prediction mode for the current block. For example, in the case of an inter prediction mode, the video encoder 200 may encode data representing which of various available inter prediction modes is used as well as motion information for the corresponding mode. In the case of unidirectional or bidirectional inter prediction, for example, the video encoder 200 may encode motion vectors using an advanced motion vector prediction (AMVP) mode or a merge mode. The video encoder 200 may use a similar mode to encode motion vectors for an affine motion compensation mode.

[0054]

[0067] AV1 includes two general techniques for encoding and decoding coding blocks of video data. The two general techniques are intra-prediction (e.g., intra-frame prediction or spatial prediction) and inter-prediction (e.g., inter-frame prediction or temporal prediction). In the context of AV1, when predicting a block of a current frame of video data using an intra-prediction mode, the video encoder 200 and the video decoder 300 do not use video data from other frames of the video data. In most intra-prediction modes, the video encoder 200 encodes the block of the current frame based on the difference between sample values ​​in the current block and predicted values ​​generated from reference samples in the same frame. The video encoder 200 determines the predicted values ​​generated from the reference samples based on the intra-prediction mode.

[0055]

[0068] Following prediction, such as intra- or inter-prediction, of a block, the video encoder 200 may calculate residual data for the block. The residual data, such as a residual block, represents sample-by-sample differences between the block and a prediction block for that block formed using a corresponding prediction mode. The video encoder 200 may apply one or more transforms to the residual block to produce transform data in the transform domain rather than the sample domain. For example, the video encoder 200 may apply a discrete cosine transform (DCT), an integer transform, a wavelet transform, or a conceptually similar transform to the residual video data. In addition, the video encoder 200 may apply a secondary transform, such as a mode-dependent non-separable secondary transform (MDNSST), a signal-dependent transform, or a Karhunen-Loeve transform (KLT), following the initial transform. The video encoder 200 produces transform coefficients following application of the one or more transforms.

[0056]

[0069] As described above, following any transformation that produces transform coefficients, the video encoder 200 may perform quantization of the transform coefficients. Quantization generally refers to a process in which transform coefficients are quantized to possibly reduce the amount of data used to represent the transform coefficients, thereby providing further compression. By performing the quantization process, the video encoder 200 may reduce the bit depth associated with some or all of the transform coefficients. For example, the video encoder 200 may truncate an n-bit value to an m-bit value during quantization, where n is greater than m. In some examples, to perform quantization, the video encoder 200 may perform a bitwise right shift of the value to be quantized.

[0057]

[0070] Following quantization, the video encoder 200 may scan the transform coefficients, creating a one-dimensional vector from a two-dimensional matrix containing the quantized transform coefficients. The scan may be designed to place transform coefficients with higher energy (and therefore lower frequency) at the front of the vector and transform coefficients with lower energy (and therefore higher frequency) at the back of the vector. In some examples, the video encoder 200 may use a predefined scan order to scan the quantized transform coefficients to create a serialized vector and then entropy code the quantized transform coefficients of the vector. In other examples, the video encoder 200 may perform adaptive scanning. After scanning the quantized transform coefficients to form the one-dimensional vector, the video encoder 200 may entropy code the one-dimensional vector, for example, according to context-adaptive binary arithmetic coding (CABAC). The video encoder 200 may also entropy code values ​​for syntax elements that describe metadata associated with the encoded video data for use by the video decoder 300 in decoding the video data.

[0058]

[0071] To implement CABAC, video encoder 200 may assign a context in a context model to a symbol to be transmitted. The context may relate, for example, to whether neighboring values ​​of the symbol are zeroed. A probability determination may be based on the context assigned to the symbol.

[0059]

[0072] Video encoder 200 may further generate syntax data, such as block-based syntax data, picture-based syntax data, and sequence-based syntax data, for example, within a picture header, a block header, a slice header, or other syntax data, such as a sequence parameter set (SPS), a picture parameter set (PPS), or a video parameter set (VPS), to video decoder 300. Video decoder 300 may similarly decode such syntax data to determine how to decode the corresponding video data.

[0060]

[0073] In this manner, video encoder 200 may generate a bitstream including syntax elements that describe coded video data, e.g., partitions of a picture into blocks (e.g., CUs) and prediction and / or residual information for the blocks. Finally, video decoder 300 may receive the bitstream and decode the coded video data.

[0061]

[0074] Generally, video decoder 300 performs a reciprocal process to that performed by video encoder 200 to decode encoded video data of a bitstream. For example, video decoder 300 may decode values ​​for syntax elements of a bitstream using CABAC in a manner that is reciprocal but substantially similar to the CABAC encoding process of video encoder 200. The syntax elements may define partition information for the partition of a picture into CTUs and the partition of each CTU according to a corresponding partition structure, such as a QTBT structure, to define the CUs of the CTU. The syntax elements may further define prediction information and residual information for blocks of video data (e.g., CUs).

[0062]

[0075] The residual information may be represented, for example, by quantized transform coefficients. The video decoder 300 may dequantize and inverse transform the quantized transform coefficients of the block to reconstruct a residual block for the block. The video decoder 300 uses the signaled prediction mode (intra-prediction or inter-prediction) and associated prediction information (e.g., motion information for inter-prediction) to form a predictive block for the block. The video decoder 300 can then combine the predictive block and the residual block (sample by sample) to reconstruct the original block. The video decoder 300 may also perform additional processing, such as performing a deblocking process to reduce visual artifacts along block boundaries.

[0063]

[0076] This disclosure may generally refer to “signaling” some information, such as a syntax element. The term “signaling” may generally refer to the communication of values ​​for syntax elements and / or other data used to decode encoded video data. That is, video encoder 200 may signal values ​​for syntax elements within a bitstream. Generally, signaling refers to generating values ​​within a bitstream. As mentioned above, source device 102 may transfer the bitstream to destination device 116 in substantially real time or non-real time, which may occur, for example, when storing syntax elements in storage device 112 for later retrieval by destination device 116.

[0064]

[0077] 2 and 3 are conceptual diagrams illustrating examples of control point motion vectors (CPMVs) for affine motion compensation. Specifically, FIG. 2 shows a current block predicted using three CPMVs V0, V1, and V2 at three corners (e.g., 124, 126, and 128), and FIG. 3 shows a current block 132 predicted using four CPMVs V0, V1, V2, and V3 at four corners (e.g., 130, 132, 134, and 136).

[0065]

[0078] Video encoder 200 and video decoder 300 may be configured to code video data according to an affine motion model. One example of an affine motion model may be expressed as follows:

[0066]

number

[0067]

number

[0068]

number

[0069]

[0079] A simplified four-parameter affine model (for zoom and rotation motion) can be expressed as follows:

[0070]

number

[0071]

[0080] Similarly, a simplified four-parameter affine model of a block is given by two CPMVs at the two corners of the block.

[0072]

number

[0073]

number

[0074]

[0081] The video encoder 200 and the video decoder 300 can be configured to perform sub-block-based affine motion compensation. Given an affine motion model for a block, the video encoder 200 and the video decoder 300 can derive different motion vectors for each pixel in the block. Thus, motion compensation can be performed on a per-pixel basis. However, to reduce complexity, sub-block-based motion compensation is often employed, where the block is divided into a plurality of sub-blocks (having a smaller block size), and each sub-block is associated with one motion vector for motion compensation. The motion vector for each sub-block is derived using the representative coordinates of the sub-block, which are typically the center position. In some embodiments, the block may be divided into non-overlapping sub-blocks. In the following description, the block width is represented as blkW, the block height is represented as blkH, the sub-block width is represented as sbW, and the sub-block height is represented as sbH, such that there are blkH / sbH rows of sub-blocks and blkW / sbW sub-blocks in each row. In a six-parameter affine motion model, the motion vector (referred to as the sub-block motion vector) for the sub-block at the i-th row (0 <= i < blkW / sbW) and the j-th column (0 <= j < blkH / sbH) is derived as follows.

[0075]

Number

[0076]

[0082] The video encoder 200 and the video decoder 300 may be configured to perform prediction refinement with optical flow (PROF). After sub-block-based affine motion compensation is performed, the prediction signal may be refined by adding an offset derived based on pixel-wise motion and the gradient of the prediction signal. The offset at location (m, n) may be calculated as follows:

[0077]

number

[0078]

number

[0079]

number

[0080]

[0083] In the control point-based affine motion model, the affine motion parameters a, b, c, and d are calculated from the CPMV as follows:

[0081]

number

[0082]

[0084] Video encoder 200 and video decoder 300 may be configured to perform overlapped block motion compensation (OBMC). When OBMC is applied, the top and left boundary pixels of a CU are refined using motion information from neighboring blocks using weighted prediction as described in JVET-L0101.

[0083]

[0085] Video encoder 200 and video decoder 300 may be configured to not apply OBMC under certain conditions, such as when OBMC is disabled at the SPS level, when the current block has intra mode or intra block copy (IBC) mode, when LIC is applied to the current block, and when the current luma block area is less than or equal to 32.

[0084]

[0086] Video encoder 200 and video decoder 300 can be configured to perform sub-block boundary OBMC by applying the same blending to top, left, bottom, and right sub-block boundary pixels using motion information of neighboring sub-blocks. OBMC can be enabled for sub-block-based coding tools such as affine AMVP mode, affine merge mode, and subblock-based temporal motion vector prediction (SbTMVP), as well as sub-block-based bilateral matching.

[0085]

[0087] When the OBMC mode is used in a combined intra and inter prediction (CIIP) mode with luma mapping with chroma scaling (LMCS), the video encoder 200 and the video decoder 300 may perform inter blending before LMCS mapping of the inter samples. The LMCS is applied to the blended inter samples that are combined with the intra samples to which the LMCS was applied in the CIIP mode.

[0086]

number

[0087]

[0088] Video encoder 200 and video decoder 300 may be configured to implement LIC, which is an inter-prediction technique for modeling local illumination variations between a current block and a corresponding predicted block as a function of the variation between a current block template and a reference block template. The parameters of the function may be denoted by a scale α and an offset β, which is a linear equation (α ) for compensating for illumination changes. * p[x]+β), where p[x] is the reference sample pointed to by the motion vector at location x on the reference picture. Since α and β can be derived based on the current block template and the reference block template, no signaling overhead is required, except that a LIC flag can be signaled for AMVP mode to indicate the use of LIC.

[0088]

[0089] The LIC proposed in JVET-O0066 is used for uni-predictive inter CUs with some modifications. For example, intra-neighboring samples can be used in LIC parameter derivation, and LIC can be disabled for blocks with fewer than 32 luma samples. In addition, for both non-sub-block and affine modes, LIC parameter derivation can be performed based on the template block samples corresponding to the current CU instead of the partial template block samples corresponding to the first top-left 16x16 unit.

[0089]

[0090] When performing LIC, the video encoder 200 and the video decoder 300 may be configured to generate samples of the reference block template by using motion compensation with block motion vectors without rounding to integer pixel precision.

[0090]

[0091] The video encoder 200 and the video decoder 300 can be configured to perform multi-hypothesis prediction (MHP). In the multi-hypothesis inter-prediction mode (JVET-M0425), one or more additional motion-compensated prediction signals are signaled in addition to the conventional bi-predictive signal. The resulting overall prediction signal is obtained by weighted overlapping on a sample-by-sample basis. The bi-predictive signal p bi and the first additional inter prediction signal / hypothesis h3, the resulting prediction signal p3 is obtained as follows:

[0091]

number

[0092]

[0092] The weighting factor α is specified by the new syntax element add_hyp_weight_idx according to the following mapping:

[0093] [Table 1]

[0094]

[0093] As above, more than one additional prediction signal can be used, and the resulting overall prediction signal is accumulated iteratively with each additional prediction signal.

[0095]

number

[0096] The resulting overall predicted signal is the last p n (i.e., p with the largest index n n ) Within this EE, up to two additional prediction signals can be used (i.e., n is limited to 2).

[0097] The motion parameters of each additional prediction hypothesis can be signaled either explicitly by specifying a reference index, a motion vector predictor index, and a motion vector differential, or implicitly by specifying a merge index. A separate multi-hypothesis merge flag distinguishes between these two signaling modes.

[0098]

[0096] In the case of inter AMVP mode, video encoder 200 and video decoder 300 may be configured to apply MHP only when unequal weights in BCW are selected in bi-predictive mode. A combination of MHP and BDOF may also be possible. In such a case, video encoder 200 and video decoder 300 may be configured to apply BDOF only to the bi-predictive signal portion of the prediction signal, such as the usual first two hypotheses.

[0099]

[0097] Video encoder 200 and video decoder 300 can be configured to perform extended bidirectional motion compensation using out-of-bounds (OOB) prediction samples. In bidirectional motion compensation, OOB prediction samples are discarded, and only non-OOB predictors, if available, are used to generate the final predictor. Specifically, Pos_x i,j and Pos_y i,j indicates the position of one predicted sample in one current block,

[0100]

number

[0101]

number

[0102] After checking the OOB status for each sample, the video encoder 200 and the video decoder 300 may generate the final predicted sample for one bidirectional block as follows:

[0103]

number

[0104]

number

[0105]

number

[0106]

number

[0107]

number

[0108]

number

[0109]

number

[0110]

[0099] The video encoder 200 and the video decoder 300 can also apply an OOB checking process when BCW is enabled.

[0111]

[0100] This sample-adaptive bi-prediction process can only be applied to prediction units for which at least the reference block is first detected as being partially or completely out of bounds. Therefore, the block-level OOB criteria is checked first. If both prediction blocks are non-OOB, the normal bi-prediction process can be performed.

[0112]

[0101] Existing techniques may have potential problems. In current versions of VVC and the enhanced compression model (ECM), an inter-predicted coding block is partitioned into several sub-blocks, and each sub-block may have a motion vector. In some cases, the same partitioning of sub-blocks applies to both luma and chroma blocks, and a chroma sub-block uses the same motion vector as its corresponding luma sub-block. However, it is possible to have different sub-block partitioning for luma and chroma. For example, for an 8x8 affine prediction block with a 4:2:0 format, the luma block may be partitioned into four 4x4 sub-blocks, but the chroma block may remain the same as the original 4x4 chroma block. In this case, each luma sub-block has a motion vector, but the chroma block has a motion vector derived as the average of the two motion vectors of the corresponding luma sub-blocks at the top-left and bottom-right positions.

[0113]

[0102] Figure 4 shows an example of an 8x8 luma block 140 and a corresponding 4x4 chroma block 142. In the example of Figure 4, the affine motion vector (MV5) for the 4x4 chroma block 142 is derived as the average of MV1 and MV4 for the 4x4 luma sub-blocks 144A and 144D, respectively. The 4x4 luma sub-blocks 144B and 144C have motion vectors MV2 and M3, respectively, but in the example of Figure 4, their MVs are not used to determine MV5. MV1-MV4 are used in the motion compensation process to derive the luma prediction block. MV5 is used in the motion compensation process to derive the chroma prediction block. However, MV1-MV5 can also be used in other processes, such as to perform an OOB pixel check. In the current ECM, instead of using chroma MV5 to perform an OOB chroma pixel check, whether a chroma pixel is OOB is determined by using the corresponding luma motion vector.

[0114]

[0103] Figure 5 shows motion vectors used for OOB checks for the luma block 140 and chroma block 142 of Figure 4. Figure 5 shows one example of a mismatch for the motion compensation process between the luma block and the chroma block. It also shows a mismatch between the motion vectors used to check the OOB chroma pixels and the motion vectors used to perform motion compensation for the chroma block. When sub-block partitioning is pixel-based, e.g., when each pixel has its own motion vector, mismatch issues can also occur for other processes, such as when deriving LIC reference template samples.

[0115] To address the problems introduced above, this disclosure describes techniques for determining a minimum process grid for video coding processes such as motion compensation, OOB, and LIC reference template sample derivation. Once the minimum process grid for a process is determined, various techniques are disclosed for deriving motion vectors to be used in the process.

[0116] According to the techniques of this disclosure, the video encoder 200 and the video decoder 300 can be configured to perform a process using pixel-based motion vectors. In such an embodiment, when a coding block has at least one pixel with a motion vector different from other pixel(s), the minimum process grid of the process is determined to be 1×1, which is called a pixel-based process because the motion vector of each pixel is used. The process may be motion compensation, OOB check, or LIC reference template sample derivation. The coding block may be a luma coding block and a chroma coding block.

[0117] For pixel-based motion compensation, video encoder 200 and video decoder 300 may be configured to derive a predictive block using pixel-based prediction, with each pixel having its motion vector. For pixel-based OOB checking, video encoder 200 and video decoder 300 determine whether a pixel is OOB by examining whether the pixel's motion vector points to a location in a reference picture that is outside the reference picture boundary.

[0118]

[0107] Figure 6 shows an example in which the motion vectors for motion compensation are also used to perform an OOB check, for example, to determine whether a pixel is OOB. In the example of Figure 6, the video decoder 300 performs an OOB check for each pixel of the current block 146 when using the pixel's motion compensation motion vector. In the example of Figure 6, pixel 16 of the current block 146 has a bi-motion vector, but the L0 motion vector (MV16_L0) points outside the reference picture 148. Therefore, the video decoder 300 can be configured to predict pixel 16 using only MV16_L1.

[0119] For pixel-based LIC reference template sample derivation, video encoder 200 and video decoder 300 use the motion vectors of corresponding boundary pixels inside the current block to derive a 1×M LIC reference template sample block above the current block, and use the corresponding motion vectors of boundary pixels inside the current block to derive an N×1 LIC reference template sample block to the left of the current block, where M and N represent the LIC template sizes above and to the left of the current block, respectively.

[0120]

[0109] In some embodiments, instead of using the motion vector of a single boundary pixel, the video encoder 200 and video decoder 300 can derive a LIC reference template sample using the average of a subset of pixels along the current block boundary to derive the motion vector.

[0121]

[0110] Figure 7 shows an example in which motion vectors 152 and 154 are used for motion compensation of the current block 156 and are used to derive the top and left reference template sample blocks 158 and 1160, respectively, and 154 for LIC is the same as the motion vector used for motion compensation of pixels 1 and 5, respectively.

[0122] In some embodiments, video encoder 200 and video decoder 300 may apply pixel-based motion compensation to derive template blocks for a decoder-side motion refinement process, which may be, for example, template matching or bilateral matching based.

[0123]

[0112] In the case of the bilateral matching refinement process, the video encoder 200 and the video decoder 300 perform pixel-based motion compensation to derive a template block in the reference pictures L0 and L1, respectively, and to derive refined motion by minimizing the difference between the two templates in L0 and L1.

[0124]

[0113] For the template matching refinement process, the video encoder 200 and the video decoder 300 can perform pixel-based motion compensation to derive a reference template block to the left of or above the current block in the reference picture(s) and to derive refined motion by minimizing the difference between the reference template block and the template block of the current block in the current picture.

[0125] In one embodiment, video encoder 200 and video decoder 300 may apply pixel-based motion compensation to derive template blocks for a decoder-side motion vector predictor (MVP) reordering process. The decoder-side MVP reordering process may be, for example, template matching or bilateral matching based.

[0126]

[0115] For the bilateral matching MVP sorting process, the video encoder 200 and the video decoder 300 can perform pixel-based motion compensation to derive template blocks in the reference pictures L0 and L1, respectively, and to prioritize MVPs with smaller differences between the two templates on L0 and L1.

[0127]

[0116] For the template matching MVP reordering process, the video encoder 200 and the video decoder 300 may perform pixel-based motion compensation to derive a reference template block to the left of or above the current block in the reference picture(s) and to prioritize MVPs that have a smaller difference between the reference template block and the template block of the current block in the current picture.

[0128] According to the techniques of this disclosure, the video encoder 200 and the video decoder 300 may be configured to perform a process using a derived motion vector of a sub-block area. In some embodiments, when a coding block has at least one pixel with a motion vector different from other pixel(s), the video encoder 200 and the video decoder 300 may determine that the minimum process grid of the process is sub-block-based and perform the sub-block process using a motion vector derived from the sub-block. In the sub-block, at least one pixel may have a motion vector different from other pixel(s) used by the motion compensation process. The process may be, for example, an OOB check or LIC reference template sample derivation. The coding block may include a luma coding block and a chroma coding block.

[0129]

[0118] If the process is a motion compensation process and there is at least one pixel that has a differential motion vector compared to other pixels, the block is divided into several sub-blocks and each sub-block predictor is derived by motion compensation using the sub-block motion vector.

[0130]

[0119] In accordance with the techniques of this disclosure, video encoder 200 and video decoder 300 may be configured to perform an OOB pixel checking process using the derived motion vectors.

[0131]

[0120] In this embodiment, when at least one pixel in a sub-block has a motion vector different from the other pixel(s) in the sub-block that is used for the motion compensation process, the OOB pixel check process of the sub-block uses the derived motion vector.

[0132]

[0121] In one embodiment, assuming that a W×H coding block performs pixel-based (affine) motion compensation, for each pixel, there is a motion vector for deriving a predicted pixel. The sbOobW×sbOobH oobSubblock of the coding block checks whether all the reference pixels in the oobSubblock are OOB pixels or not by using the derived motion vector. At least one pixel in the oobSubblock has a motion vector for different motion compensation from the other pixel(s) in the oobSubblock. Here, 1 < sbOobW ≤ W and 1 < sbOobH ≤ H.

[0133]

[0122] In one embodiment, assuming that a W×H coding block is divided into several sbW×sbH sub-blocks and performs sub-block-based motion compensation (MC), for each sub-block, there is a motion vector for deriving a predicted sub-block. The sbOobW×sbOobH oobSubblock of the coding block checks whether all the reference pixels in the oobSubblock are OOB pixels or not by using the derived motion vector. At least one pixel in the oobSubblock has a motion vector for different motion compensation (MC) from the other pixel(s) in the oobSubblock. Here, 1 < sbOobW ≤ W and 1 < sbOobH ≤ H. The division of the oobSubblock is different from the division of the MC sub-block.

[0134]

[0123] In one embodiment, the derived motion vector is the same as the one used for MC of one pixel, for example the top left pixel of the oobSubblock.

[0135]

[0124] In one embodiment, the derived motion vector is the average of a subset of the motion vectors used for MC of a subset of pixels in the oobSubblock.

[0136]

[0125] In one embodiment, the oobSubblock is a chroma block, and the derived motion vector is the same as the motion vector used for MC of one corresponding luma pixel, for example, the luma pixel corresponding to the top-left chroma pixel of the oobSubblock.

[0137]

[0126] In one embodiment, oobSubblock is a chroma block, and the derived motion vector is the average of a subset of the motion vectors used for MC of the corresponding luma pixels.

[0138] 8 shows an example where a motion vector 170 is used to determine whether a pixel is OOB. Motion vector 170 is the motion vector for pixel 1, the top left pixel of the current block 172. Pixels in reference pictures L0 and L1 represent OOB checks in the reference pictures, while solid white pixels represent predicted pixels. It can be seen that pixel 1 has the same predicted pixel and OOB check pixel.

[0139] According to the techniques of this disclosure, video encoder 200 and video decoder 300 may be configured to perform the LIC reference template sample derivation process using the derived motion vector. In some embodiments, when at least one pixel in a sub-block has a motion vector used for the MC process that is different from the motion vectors of other pixel(s) in the sub-block, video encoder 200 and video decoder 300 may perform the LIC reference template sample derivation process for the sub-block using the derived motion vector.

[0140]

[0129] In one embodiment, for a WxH coding block, the video encoder 200 and the video decoder 300 may be configured to perform pixel-based (affine) MC. For each pixel, the video encoder 200 and the video decoder 300 may use a motion vector to derive a predicted pixel. A licSubblock of sbLicWx1 (at the top block boundary) or 1xsbLicH (at the left block boundary) of the coding block may be used to derive sbLicWxP or QxsbLicH LIC reference template samples by using the motion vectors derived above and to the left of the current block, respectively. At least one pixel in the licSubblock has a motion vector for motion compensation that is different from the other pixel(s) in the licSubblock. Here, 1 <sbLicW≦Wであり、1<sbLicH≦Hである。

[0141]

[0130] In one embodiment, a W×H coding block can be divided into several sbW×sbH sub-blocks, and the video encoder 200 and the video decoder 300 can perform sub-block-based motion compensation. For each sub-block, the video encoder 200 and the video decoder 300 can use motion vectors to derive a predicted sub-block. The 1×sbLicH at the left block boundary or sbLicW×1 at the upper block boundary of the coding block can be used to derive sbLicW×P or Q×sbLicH LIC reference template samples by using the motion vectors derived above and to the left of the current block respectively. At least one pixel in the licSubblock has a motion vector for MC that is different from the other pixel(s) in the licSubblock. Here, 1 < sbLicW ≤ W and 1 < sbLicH ≤ H. P and Q represent the height and width of the LIC reference template for the current block above and to the left respectively.

[0142] In some embodiments, the derived motion vector may be the same as one of the motion vectors used for MC of one pixel, e.g., the top-left pixel of licSubblock. In some embodiments, the derived motion vector may be the average of a subset of motion vectors used for MC of a subset of pixels, the pixels being within licSubblock or within a larger sub-block M×sbLicH (at the left block boundary) or within sbLicW×N (at the top block boundary). In some embodiments, licSubblock is a chroma block. The derived motion vector may be the same as one of the motion vectors used for motion compensation of one corresponding luma pixel, e.g., the luma pixel corresponding to the top-left chroma pixel of licSubblock. In some embodiments, licSubblock may be a chroma block. The derived motion vector may be the average of a subset of motion vectors used for motion compensation of the corresponding luma pixels.

[0143] 9 shows an example where the LIC reference template 180 is derived by a subset of pixels 1 to 16. In this example, the dimensions of the licSubblock are sbLicW=4 and P=4. The motion vector derived to derive the LIC reference template may be the same as the motion vector used for MC of pixel 1.

[0144] According to the techniques of this disclosure, video encoder 200 and video decoder 300 may be configured to determine a minimum process grid. In some embodiments, the minimum process grid is predetermined as M×N for the processes, where M is equal to 4 and N is equal to 4, for example. The aforementioned values ​​of sbLicW, sbLicH, sbOobW, and sbOobH may be derived based on the predetermined values ​​of M and N and the current block dimensions W and H.

[0145] In some embodiments, video encoder 200 may signal the minimum process grid to video decoder 300 as a high-level syntax value, such as an SPS, PPS, picture header, or slice header, for each of the processes, such as MC, LIC, and OOB. In some embodiments, the minimum process grid for all processes, such as MC, LIC, and OOB, may be the same. For example, all processes are pixel-based. In some embodiments, the minimum process grid for motion compensation may be pixel-based, but LIC and OOB have a minimum process grid of M×N, where M>1 and / or N>1.

[0146] In some embodiments, the minimum process grid of a process may depend on the block size. For example, when a coding block has dimensions W×H, a pixel-based process can be applied, where W is less than or equal to a threshold and H is less than or equal to a threshold, or W is less than or equal to a threshold. * For example, when a coding block has dimensions W×H, a sub-block based process can be applied, where W is less than or equal to a threshold and H is less than or equal to a threshold, or W is less than or equal to a threshold. * H is less than or equal to the threshold.

[0147] 10 is a block diagram illustrating an example video encoder 200 that can perform the techniques of this disclosure. Figure 10 is provided for illustrative purposes and should not be considered limiting of the techniques broadly illustrated and described in this disclosure. For illustrative purposes, this disclosure describes a video encoder 200 in accordance with VVC and HEVC techniques. However, the techniques of this disclosure may be implemented by video encoding devices configured for other video coding standards and video coding formats, such as AV1 and successors to the AV1 video coding format.

[0148] 10 , the video encoder 200 includes a video data memory 230, a mode select unit 202, a residual generation unit 204, a transform processing unit 206, a quantization unit 208, an inverse quantization unit 210, an inverse transform processing unit 212, a reconstruction unit 214, a filter unit 216, a decoded picture buffer (DPB) 218, and an entropy coding unit 220. Any or all of the video data memory 230, the mode select unit 202, the residual generation unit 204, the transform processing unit 206, the quantization unit 208, the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the filter unit 216, the DPB 218, and the entropy coding unit 220 may be implemented in one or more processors or processing circuits. For example, the units of video encoder 200 may be implemented as one or more circuits or logic elements as part of a hardware circuit, or as part of a processor, ASIC, or FPGA. Moreover, video encoder 200 may include additional or alternative processors or processing circuits that perform these and other functions.

[0149]

[0138] Video data memory 230 may store video data to be encoded by components of video encoder 200. Video encoder 200 may receive video data stored in video data memory 230, for example, from video source 104 (FIG. 1). DPB 218 may function as a reference picture memory that stores reference video data for use in predicting subsequent video data by video encoder 200. Video data memory 230 and DPB 218 may be formed by any of a variety of memory devices, such as dynamic random access memory (DRAM), including synchronous dynamic random access memory (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of memory devices. Video data memory 230 and DPB 218 may be provided by the same memory device or separate memory devices. In various examples, video data memory 230 may be on-chip with other components of video encoder 200, as shown, or may be off-chip relative to those components.

[0150] In this disclosure, references to video data memory 230 should not be construed as limited to memory internal to video encoder 200, unless specifically stated so, or to memory external to video encoder 200, unless specifically stated so. Rather, references to video data memory 230 should be understood as a reference memory that stores video data that video encoder 200 receives for encoding (e.g., video data for a current block to be encoded). Memory 106 of FIG. 1 may also provide temporary storage of outputs from various units of video encoder 200.

[0151] The various units in FIG. 10 are shown to aid in understanding the operations performed by video encoder 200. The units may be implemented as fixed-function circuits, programmable circuits, or a combination thereof. A fixed-function circuit refers to a circuit that provides a specific function, and the operations that may be performed are predefined. A programmable circuit refers to a circuit that may be programmed to perform various tasks, and provides flexibility in the operations that may be performed. For example, a programmable circuit may execute software or firmware that causes the programmable circuit to operate in a manner defined by the software or firmware instructions. Although a fixed-function circuit may execute software instructions (e.g., receive parameters or output parameters), the types of operations that the fixed-function circuit performs are generally invariant. In some examples, one or more of the units may be different circuit blocks (fixed function or programmable), and in some examples, one or more of the units may be an integrated circuit.

[0152]

[0141] Video encoder 200 may include arithmetic logic units (ALUs), elementary function units (EFUs), digital circuits, analog circuits, and / or a programmable core formed from programmable circuits. In examples in which the operations of video encoder 200 are implemented using software executed by programmable circuits, memory 106 (FIG. 1) may store software instructions (e.g., object code) that video encoder 200 receives and executes, or a separate memory (not shown) within video encoder 200 may store such instructions.

[0153]

[0142] The video data memory 230 is configured to store received video data. The video encoder 200 may retrieve pictures of the video data from the video data memory 230 and provide the video data to the residual generation unit 204 and the mode selection unit 202. The video data in the video data memory 230 may be raw video data to be encoded.

[0154] The mode select unit 202 includes a motion estimation unit 222, a motion compensation unit 224, and an intra prediction unit 226. The mode select unit 202 may include additional functional units that perform video prediction according to other prediction modes. By way of example, the mode select unit 202 may include a palette unit, an intra block copy unit (which may be part of the motion estimation unit 222 and / or the motion compensation unit 224), an affine unit, a linear model (LM) unit, etc.

[0155]

[0144] The mode selection unit 202 generally coordinates multiple encoding passes to test combinations of encoding parameters and the resulting rate-distortion values ​​for such combinations. The encoding parameters may include partitioning of CTUs into CUs, prediction modes for CUs, transform types for residual data of CUs, quantization parameters for residual data of CUs, etc. The mode selection unit 202 may ultimately select a combination of encoding parameters that has a better rate-distortion value than the other tested combinations.

[0156] Video encoder 200 may partition a picture retrieved from video data memory 230 into a series of CTUs and encapsulate one or more CTUs within a slice. Mode select unit 202 may partition the CTUs of the picture according to a tree structure, such as the MTT structure, QTBT structure, superblock structure, or quadtree structure described above. As described above, video encoder 200 may form one or more CUs from partitioning the CTUs according to the tree structure. Such CUs may also be generally referred to as "video blocks" or "blocks."

[0157]

[0146] Generally, the mode selection unit 202 also controls its components (e.g., the motion estimation unit 222, the motion compensation unit 224, and the intra prediction unit 226) to generate a prediction block for a current block (e.g., a current CU, or in HEVC, an overlapping portion of a PU and a TU). In the case of inter prediction of the current block, the motion estimation unit 222 may perform a motion search to identify one or more closely matching reference blocks among one or more reference pictures (e.g., one or more previously coded pictures stored in the DPB 218). Specifically, the motion estimation unit 222 may calculate a value representing how similar a potential reference block is to the current block according to, for example, the sum of absolute differences (SAD), the sum of squared differences (SSD), the mean absolute difference (MAD), the mean squared difference (MSD), etc. The motion estimation unit 222 may generally perform these calculations using sample-by-sample differences between the current block and the reference block under consideration. Motion estimation unit 222 may identify the reference block with the lowest value resulting from these calculations, indicating the reference block that most closely matches the current block.

[0158]

[0147] The motion estimation unit 222 may form one or more motion vectors (MVs) that define the position of a reference block in a reference picture relative to the position of a current block in the current picture. The motion estimation unit 222 may then provide the motion vectors to the motion compensation unit 224. For example, in the case of unidirectional inter prediction, the motion estimation unit 222 may provide a single motion vector, while in the case of bidirectional inter prediction, the motion estimation unit 222 may provide two motion vectors. The motion compensation unit 224 may then generate a predictive block using the motion vectors. For example, the motion compensation unit 224 may use the motion vectors to retrieve data of the reference blocks. As another example, if the motion vectors have fractional sample precision, the motion compensation unit 224 may interpolate values ​​for the predictive block according to one or more interpolation filters. Moreover, in the case of bidirectional inter prediction, the motion compensation unit 224 may retrieve data for the two reference blocks identified by the respective motion vectors and combine the retrieved data, for example, through sample-wise averaging or weighted averaging.

[0159]

[0148] When operating according to the AV1 video coding format, the motion estimation unit 222 and the motion compensation unit 224 may be configured to encode coding blocks of video data (e.g., both luma coding blocks and chroma coding blocks) using translational motion compensation, affine motion compensation, overlapped block motion compensation (OBMC), and / or synthetic inter-intra prediction.

[0160] As another example, in the case of intra prediction or intra-predictive coding, intra prediction unit 226 may generate a predictive block from samples neighboring a current block. For example, in the case of a directional mode, intra prediction unit 226 may generally mathematically combine values ​​of neighboring samples and populate these calculated values ​​in a defined direction across the current block to produce a predictive block. As another example, in the case of a DC mode, intra prediction unit 226 may calculate an average of neighboring samples for the current block and generate a predictive block to include this resulting average for each sample of the predictive block.

[0161] When operating according to the AV1 video coding format, intra prediction unit 226 may be configured to encode coding blocks of video data (e.g., both luma coding blocks and chroma coding blocks) using directional intra prediction, non-directional intra prediction, recursive filter intra prediction, chroma-from-luma (CFL) prediction, intra block copy (IBC), and / or color palette mode. Mode select unit 202 may include additional functional units that perform video prediction according to other prediction modes.

[0162] The mode select unit 202 provides the prediction block to the residual generation unit 204. The residual generation unit 204 receives a raw, uncoded version of the current block from the video data memory 230 and the prediction block from the mode select unit 202. The residual generation unit 204 calculates sample-by-sample differences between the current block and the prediction block. The resulting sample-by-sample differences define a residual block for the current block. In some examples, the residual generation unit 204 may also determine differences between sample values ​​in the residual block to generate the residual block using residual differential pulse code modulation (RDPCM). In some examples, the residual generation unit 204 may be formed using one or more subtractor circuits that perform binary subtraction.

[0163] In examples in which the mode select unit 202 partitions CUs into PUs, each PU may be associated with a luma prediction unit and a corresponding chroma prediction unit. The video encoder 200 and the video decoder 300 may support PUs having various sizes. As mentioned above, the size of a CU may refer to the size of the luma coding block of the CU, and the size of a PU may refer to the size of the luma prediction unit of the PU. Assuming that the size of a particular CU is 2N×2N, the video encoder 200 may support a PU size of 2N×2N or N×N for intra prediction, and a symmetric PU size of 2N×2N, 2N×N, N×2N, N×N, or similar for inter prediction. The video encoder 200 and the video decoder 300 may also support asymmetric partitioning of PU sizes of 2N×nU, 2N×nD, nL×2N, and nR×2N for inter prediction.

[0164] In examples where the mode select unit 202 does not further partition the CUs into PUs, each CU may be associated with a luma coding block and a corresponding chroma coding block. As described above, the size of a CU may refer to the size of the luma coding block of the CU. The video encoder 200 and the video decoder 300 may support CU sizes of 2N×2N, 2N×N, or N×2N.

[0165] For other video coding techniques, such as intra block copy mode coding, affine mode coding, and linear model (LM) mode coding, as some examples, mode select unit 202 generates a predictive block for the current block being coded via a respective unit associated with the coding technique. In some examples, such as palette mode coding, mode select unit 202 may not generate a predictive block, but instead may generate syntax elements that indicate how to reconstruct the block based on a selected palette. In such modes, mode select unit 202 may provide these syntax elements to entropy coding unit 220 to be coded.

[0166]

[0155] As described above, the residual generation unit 204 receives video data for a current block and a corresponding predictive block. The residual generation unit 204 then generates a residual block for the current block. To generate the residual block, the residual generation unit 204 calculates sample-by-sample differences between the predictive block and the current block.

[0167] Transform processing unit 206 applies one or more transforms to the residual block to generate a block of transform coefficients (referred to herein as a "transform coefficient block"). Transform processing unit 206 may apply various transforms to the residual block to form the transform coefficient block. For example, transform processing unit 206 may apply a discrete cosine transform (DCT), a directional transform, a Karhunen-Loeve transform (KLT), or a conceptually similar transform to the residual block. In some examples, transform processing unit 206 may perform multiple transforms on the residual block, e.g., a linear transform and a secondary transform such as a rotational transform. In some examples, transform processing unit 206 does not apply a transform to the residual block.

[0168] When operating according to AV1, transform processing unit 206 may apply one or more transforms to the residual block to generate a block of transform coefficients (referred to herein as a "transform coefficient block"). Transform processing unit 206 may apply various transforms to the residual block to form the transform coefficient block. For example, transform processing unit 206 may apply a horizontal / vertical transform combination, which may include a discrete cosine transform (DCT), an asymmetric discrete sine transform (ADST), an inverse ADST (e.g., ADST in reverse order), and an identity transform (IDTX). When using an identity transform, the transform is skipped in one of the vertical or horizontal directions. In some examples, the transform process may be skipped.

[0169] The quantization unit 208 may quantize the transform coefficients in the transform coefficient block to produce a quantized transform coefficient block. The quantization unit 208 may quantize the transform coefficients of the transform coefficient block according to a quantization parameter (QP) value associated with the current block. The video encoder 200 (e.g., via the mode select unit 202) may adjust the degree of quantization applied to the transform coefficient block associated with the current block by adjusting the QP value associated with the CU. Quantization may result in loss of information, and therefore, the quantized transform coefficients may be less accurate than the original transform coefficients produced by the transform processing unit 206.

[0170]

[0159] The inverse quantization unit 210 and the inverse transform processing unit 212 may apply inverse quantization and inverse transform, respectively, to the quantized transform coefficient block to reconstruct a residual block from the transform coefficient block. The reconstruction unit 214 may produce a reconstructed block that corresponds to the current block (possibly with some distortion) based on the reconstructed residual block and the predictive block generated by the mode select unit 202. For example, the reconstruction unit 214 may add samples of the reconstructed residual block to corresponding samples from the predictive block generated by the mode select unit 202 to produce the reconstructed block.

[0171]

[0160] Filter unit 216 may perform one or more filter operations on the reconstructed blocks. For example, filter unit 216 may perform a deblocking operation to reduce blockiness artifacts along the edges of a CU. The operations of filter unit 216 may be skipped in some examples.

[0172] When operating according to AV1, filter unit 216 may perform one or more filter operations on the reconstructed blocks. For example, filter unit 216 may perform a deblocking operation to reduce blockiness artifacts along the edges of a CU. In other examples, filter unit 216 may apply a constrained directional enhancement filter (CDEF), which may be applied after deblocking and may include application of a non-separable, nonlinear, low-pass directional filter based on estimated edge directions. Filter unit 216 may also include a loop restoration filter, which may be applied after the CDEF and may include a separable symmetric normalized Wiener filter or a dual autoinduction filter.

[0173]

[0162] The video encoder 200 stores the reconstructed blocks in the DPB 218. For example, in examples where the operations of the filter unit 216 are not performed, the reconstruction unit 214 may store the reconstructed blocks in the DPB 218. In examples where the operations of the filter unit 216 are performed, the filter unit 216 may store the filtered reconstructed blocks in the DPB 218. The motion estimation unit 222 and the motion compensation unit 224 may retrieve reference pictures formed from the reconstructed (and possibly filtered) blocks from the DPB 218 to inter-predict blocks of a later-encoded picture. Additionally, the intra-prediction unit 226 may use the reconstructed blocks of the current picture in the DPB 218 to intra-predict other blocks in the current picture.

[0174] Generally, entropy encoding unit 220 may entropy encode syntax elements received from other functional components of video encoder 200. For example, entropy encoding unit 220 may entropy encode quantized transform coefficient blocks from quantization unit 208. As another example, entropy encoding unit 220 may entropy encode predictive syntax elements (e.g., motion information for inter-prediction or intra-mode information for intra-prediction) from mode select unit 202. Entropy encoding unit 220 may perform one or more entropy encoding operations on syntax elements, which are another example of video data, to generate entropy-encoded data. For example, entropy encoding unit 220 may perform a context-adaptive variable length coding (CAVLC) operation, a CABAC operation, a variable-to-variable (V2V) coding operation, a syntax-based context-adaptive binary arithmetic coding (SBAC) operation, a Probability Interval Partitioning Entropy (PIPE) coding operation, an Exponential-Golomb coding operation, or another type of entropy coding operation on the data. In some examples, entropy encoding unit 220 may operate in a bypass mode in which syntax elements are not entropy coded.

[0175]

[0164] Video encoder 200 may output a bitstream that includes entropy-encoded syntax elements needed to reconstruct blocks of a slice or picture. Specifically, entropy encoding unit 220 may output the bitstream.

[0176]

[0165] The entropy coding unit 220 may be configured as a symbol-to-symbol adaptive multi-symbol arithmetic coder according to AV1. A syntax element in AV1 includes an alphabet of N elements, and a context (e.g., a probability model) includes a set of N probabilities. The entropy coding unit 220 may store the probabilities as n-bit (e.g., 15-bit) cumulative distribution functions (CDFs). The entropy coding unit 220 may perform recursive scaling to update the context, using an update factor based on the alphabet size.

[0177]

[0166] The operations described above are described with respect to blocks. Such descriptions should be understood as operations on luma coding blocks and / or chroma coding blocks. As described above, in some examples, the luma coding blocks and chroma coding blocks are luma and chroma components of a CU. In some examples, the luma coding blocks and chroma coding blocks are luma and chroma components of a PU.

[0178] In some examples, operations performed with respect to luma coding blocks need not be repeated for chroma coding blocks. As one example, operations identifying motion vectors (MVs) and reference pictures for luma coding blocks need not be repeated to identify MVs and reference pictures for chroma blocks. Rather, the MVs of luma coding blocks may be scaled to determine the MVs of chroma blocks, and the reference pictures may be the same. As another example, the intra prediction process may be the same for luma coding blocks and chroma coding blocks.

[0179]

[0168] Video encoder 200 represents one embodiment of a device configured to encode video data, including a memory configured to store video data and one or more processing units implemented in a circuit configured to determine that a block of video data has been coded using an inter-prediction-related video coding process, determine a minimum process grid for the inter-prediction-related video coding process, and determine a motion vector for the block of video data based on the minimum process grid.

[0180] 11 is a block diagram illustrating an example video decoder 300 that can perform the techniques of this disclosure. Figure 11 is provided for purposes of explanation and does not limit the techniques broadly illustrated and described in this disclosure. For purposes of explanation, this disclosure describes a video decoder 300 in accordance with VVC and HEVC techniques. However, the techniques of this disclosure may be implemented by video coding devices configured for other video coding standards.

[0181] 11 , the video decoder 300 includes a coded picture buffer (CPB) memory 320, an entropy decoding unit 302, a prediction processing unit 304, an inverse quantization unit 306, an inverse transform processing unit 308, a reconstruction unit 310, a filter unit 312, and a DPB 314. Any or all of the CPB memory 320, the entropy decoding unit 302, the prediction processing unit 304, the inverse quantization unit 306, the inverse transform processing unit 308, the reconstruction unit 310, the filter unit 312, and the DPB 314 may be implemented in one or more processors or processing circuits. For example, the units of the video decoder 300 may be implemented as one or more circuits or logic elements as part of a hardware circuit, or as part of a processor, ASIC, or FPGA. Moreover, the video decoder 300 may include additional or alternative processors or processing circuits that perform these and other functions.

[0182] The prediction processing unit 304 includes a motion compensation unit 316 and an intra prediction unit 318. The prediction processing unit 304 may include additional units that perform prediction according to other prediction modes. By way of example, the prediction processing unit 304 may include a palette unit, an intra block copy unit (which may form part of the motion compensation unit 316), an affine unit, a linear model (LM) unit, etc. In other examples, the video decoder 300 may include more, fewer, or different functional components.

[0183] When operating in accordance with AV1, the motion compensation unit 316 may be configured to decode coding blocks of the video data (e.g., both luma coding blocks and chroma coding blocks) using translational motion compensation, affine motion compensation, OBMC, and / or synthetic inter-intra prediction, as described above. The intra prediction unit 318 may be configured to decode coding blocks of the video data (e.g., both luma coding blocks and chroma coding blocks) using directional intra prediction, non-directional intra prediction, recursive filter intra prediction, CFL, IBC, and / or color palette mode, as described above.

[0184] Prediction processing unit 304, e.g., motion compensation unit 316, may perform one or more techniques of this disclosure. For example, prediction processing unit 304 performs motion compensation for a block of video data using a first process grid size, determines a second process grid size for a subsequent inter-prediction-related video coding process that is larger than the first process grid size, and, in response to determining that the block of video data has at least one sample having a motion vector that differs from at least one other sample in the block of the second process grid size, performs the subsequent inter-prediction-related video coding process for the block of video data using the second process grid size.

[0185]

[0174] The CPB memory 320 may store video data, such as an encoded video bitstream, to be decoded by components of the video decoder 300. The video data stored in the CPB memory 320 may be retrieved, for example, from the computer-readable medium 110 (FIG. 1). The CPB memory 320 may include a CPB that stores encoded video data (e.g., syntax elements) from the encoded video bitstream. The CPB memory 320 may also store video data other than syntax elements of coded pictures, such as temporary data representing output from various units of the video decoder 300. The DPB 314 generally stores decoded pictures that the video decoder 300 may output and / or use as reference video data when decoding subsequent data or pictures of the encoded video bitstream. The CPB memory 320 and the DPB 314 may be formed by any of a variety of memory devices, such as DRAM, including SDRAM, MRAM, RRAM, or other types of memory devices. CPB memory 320 and DPB 314 may be provided by the same memory device or separate memory devices. In various examples, CPB memory 320 may be on-chip with other components of video decoder 300 or off-chip relative to those components.

[0186] Additionally or alternatively, in some examples, video decoder 300 may retrieve coded video data from memory 120 (FIG. 1). That is, memory 120 may store data such as those discussed above for CPB memory 320. Similarly, memory 120 may store instructions to be executed by video decoder 300 when some or all of the functionality of video decoder 300 is implemented in software to be executed by processing circuitry of video decoder 300.

[0187]

[0176] The various units shown in Figure 11 are presented to aid in understanding the operations performed by video decoder 300. The units may be implemented as fixed-function circuits, programmable circuits, or a combination thereof. As with Figure 10, fixed-function circuits refer to circuits that provide a specific function and have predefined operations that they can perform. Programmable circuits refer to circuits that can be programmed to perform various tasks and provide flexibility in the operations that they can perform. For example, a programmable circuit may execute software or firmware that causes the programmable circuit to operate in a manner defined by the software or firmware instructions. While a fixed-function circuit may execute software instructions (e.g., receive parameters or output parameters), the types of operations that the fixed-function circuit performs are generally invariant. In some examples, one or more of the units may be different circuit blocks (fixed function or programmable), and in some examples, one or more of the units may be integrated circuits.

[0188]

[0177] Video decoder 300 may include a programmable core formed from ALUs, EFUs, digital circuits, analog circuits, and / or programmable circuits. In examples where the operations of video decoder 300 are performed by software executing on programmable circuits, on-chip or off-chip memory may store instructions (e.g., object code) of the software that video decoder 300 receives and executes.

[0189]

[0178] The entropy decoding unit 302 may receive the encoded video data from the CPB and entropy decode the video data to recover the syntax elements. The prediction processing unit 304, the inverse quantization unit 306, the inverse transform processing unit 308, the reconstruction unit 310, and the filter unit 312 may generate decoded video data based on the syntax elements extracted from the bitstream.

[0190]

[0179] Generally, the video decoder 300 reconstructs a picture on a block-by-block basis. The video decoder 300 may perform a reconstruction operation on each block individually (the block currently being reconstructed, i.e., decoded, may be referred to as the "current block").

[0191] The entropy decoding unit 302 may entropy decode syntax elements that define the quantized transform coefficients of a quantized transform coefficient block, as well as transform information such as a quantization parameter (QP) and / or a transform mode indication(s). The inverse quantization unit 306 may use the QP associated with the quantized transform coefficient block to determine the degree of quantization, and similarly the degree of dequantization that the inverse quantization unit 306 should apply. The inverse quantization unit 306 may, for example, perform a bitwise left-shift operation to dequantize the quantized transform coefficients. The inverse quantization unit 306 may thereby form a transform coefficient block including the transform coefficients.

[0192]

[0181] After the inverse quantization unit 306 forms the transform coefficient blocks, the inverse transform processing unit 308 may apply one or more inverse transforms to the transform coefficient blocks to generate residual blocks associated with the current block. For example, the inverse transform processing unit 308 may apply an inverse DCT, an inverse integer transform, an inverse Karhunen-Loeve transform (KLT), an inverse rotational transform, an inverse transform, or another inverse transform to the transform coefficient blocks.

[0193]

[0182] Furthermore, prediction processing unit 304 generates a predictive block according to the prediction information syntax element entropy decoded by entropy decoding unit 302. For example, if the prediction information syntax element indicates that the current block is inter-predicted, motion compensation unit 316 may generate a predictive block. In this case, the prediction information syntax element may indicate a reference picture in DPB 314 from which to retrieve a reference block, as well as a motion vector that identifies the location of the reference block in the reference picture relative to the location of the current block in the current picture. Motion compensation unit 316 may generally perform the inter-prediction process in a manner substantially similar to that described with respect to motion compensation unit 224 (Figure 10).

[0194]

[0183] As another example, if the prediction information syntax element indicates that the current block is intra-predicted, intra prediction unit 318 may generate a predictive block according to the intra-prediction mode indicated by the prediction information syntax element. Again, intra prediction unit 318 may generally perform the intra-prediction process in a manner substantially similar to that described with respect to intra prediction unit 226 (Figure 10). Intra prediction unit 318 may retrieve data of neighboring samples for the current block from DPB 314.

[0195]

[0184] The reconstruction unit 310 may reconstruct the current block using the predictive block and the residual block. For example, the reconstruction unit 310 may add samples of the residual block to corresponding samples of the predictive block to reconstruct the current block.

[0196]

[0185] Filter unit 312 may perform one or more filter operations on the reconstructed blocks. For example, filter unit 312 may perform a deblocking operation to reduce blockiness artifacts along the edges of the reconstructed blocks. The operations of filter unit 312 are not necessarily performed in all instances.

[0197] The video decoder 300 may store the reconstructed blocks in the DPB 314. For example, in examples where the operations of the filter unit 312 are not performed, the reconstruction unit 310 may store the reconstructed blocks in the DPB 314. In examples where the operations of the filter unit 312 are performed, the filter unit 312 may store the filtered reconstructed blocks in the DPB 314. As described above, the DPB 314 may provide reference information to the prediction processing unit 304, such as samples of the current picture for intra prediction and previously decoded pictures for subsequent motion compensation. Furthermore, the video decoder 300 may output the decoded pictures (e.g., decoded video) from the DPB 314 for later display on a display device, such as the display device 118 of FIG. 1 .

[0198]

[0187] Thus, the video decoder 300 represents one embodiment of a video decoding device that includes a memory configured to store video data and one or more processing units implemented in a circuit that is configured to determine that a block of video data has been coded using an inter-prediction-related video coding process, determine a minimum process grid for the inter-prediction-related video coding process, and determine a motion vector for the block of video data based on the minimum process grid.

[0199] 12 is a flowchart illustrating an example process for encoding a current block in accordance with the techniques of this disclosure. The current block may be or include a current CU. Although described with respect to video encoder 200 (FIGS. 1 and 10), it should be understood that other devices may be configured to perform a process similar to that of FIG. 12.

[0200] In this example, the video encoder 200 first predicts the current block (350). For example, the video encoder 200 may form a predictive block for the current block. As part of performing prediction for the block, the video encoder 200 may determine a minimum process grid for an inter-prediction-related video coding process, as described herein. The video encoder 200 may then calculate a residual block for the current block (352). To calculate the residual block, the video encoder 200 may calculate the difference between the original uncoded block and a predictive block for the current block. The video encoder 200 may then transform the residual block and quantize the transform coefficients of the residual block (354). Next, the video encoder 200 may scan the quantized transform coefficients of the residual block (356). During or following the scan, the video encoder 200 may entropy code the transform coefficients (358). For example, the video encoder 200 may encode the transform coefficients using CAVLC or CABAC. Video encoder 200 may then output the entropy-coded data for the block (360).

[0201] 13 is a flowchart illustrating an example process for decoding a current block of video data in accordance with the techniques of this disclosure. The current block may be or include a current CU. Although described with respect to video decoder 300 (FIGS. 1 and 11), it should be understood that other devices may be configured to perform a process similar to that of FIG. 13.

[0202] The video decoder 300 may receive entropy-coded data for the current block, such as entropy-coded prediction information and entropy-coded data for transform coefficients of a residual block corresponding to the current block (370). The video decoder 300 may entropy decode the entropy-coded data to determine prediction information for the current block and reconstruct transform coefficients of the residual block (372). The video decoder 300 may predict the current block, e.g., using an intra-prediction mode or an inter-prediction mode indicated by the prediction information for the current block, to calculate a predictive block for the current block (374). As part of performing prediction for the block, the video decoder 300 may determine a minimum process grid for an inter-prediction-related video coding process, as described herein. The video decoder 300 may then inverse-scan the reconstructed transform coefficients to create a block of quantized transform coefficients (376). The video decoder 300 may then dequantize the transform coefficients and apply an inverse transform to the transform coefficients to produce a residual block (378). Video decoder 300 may finally decode the current block by combining the predictive block and the residual block (380).

[0203]

[0192] Figure 14 is a flowchart illustrating an example process for decoding a current block of video data in accordance with techniques of this disclosure. The current block may be or include a current CU. Although described with respect to video decoder 300 (Figures 1 and 11), it should be understood that other devices may be configured to perform processes similar to that of Figure 14. In some embodiments, video encoder 200 (Figures 1 and 10) may perform some or all of the aspects of Figure 14 as part of a video encoding process. Video encoder 200 may determine the technique of Figure 14, for example, as part of determining how to encode a block of video data.

[0204] 14, the video decoder 300 performs motion compensation for blocks of video data using a first process grid size (402). In some embodiments, the first process grid size may be as small as 1×1.

[0205] The video decoder 300 determines a second process grid size for a subsequent inter-prediction-related video coding process, the second process grid size being larger than the first process grid size (404). The video decoder 300 may determine the second process grid size, for example, by receiving signaling indicating the second process grid size, by deriving the second process grid size without explicit signaling, or by using a fixed second process grid size. The subsequent inter-prediction-related video coding process may be, for example, local illumination compensation, out-of-bounds checking, or some other such process.

[0206]

[0195] In response to determining that the block of video data has at least one sample having a motion vector that is different from at least one other sample in the block of the second process grid size, the video decoder 300 performs a subsequent inter-prediction related video coding process for the block of video data using the second process grid size (406).

[0207]

[0196] Video decoder 300 outputs a decoded version of the block of video data (408). Video decoder 300 can, for example, display, store for transmission, or later display a picture of the decoded video data that includes the decoded version of the block, or store a picture of the decoded video data that includes the decoded version of the block for use in decoding a subsequent picture of the video data.

[0208]

[0197] The following numbered clauses illustrate one or more aspects of the devices and techniques described in this disclosure.

[0209]

[0198] Clause 1A: A method for coding video data, comprising: determining that a block of video data is to be coded using an inter-prediction-related video coding process; determining a minimum process grid for the inter-prediction-related video coding process; and determining a motion vector for the block of video data based on the minimum process grid.

[0210]

[0199] Clause 2A: The method of clause 1A, wherein the inter-prediction related video coding process includes one of motion compensation, local lighting compensation, or out-of-bounds checking.

[0211]

[0200] Clause 3A: A method as described in clause 1A or 2A, wherein determining a minimum process grid for an inter-prediction related video coding process includes determining that the minimum process grid is equal to 1×1 in response to determining that the block has at least one sample having a motion vector that is different from at least one other sample in the block.

[0212]

[0201] Clause 4A: A method as described in clause 1A or 2A, wherein determining a minimum process grid for an inter-prediction related video coding process includes determining that the minimum process grid is sub-block based in response to determining that the block has at least one sample having a motion vector that is different from at least one other sample in the block.

[0213]

[0202] Clause 5A: The method of clause 4A, wherein determining that the minimum process grid is sub-block based includes determining that the minimum process grid is equal to a size of the sub-block.

[0214]

[0203] Clause 6A: A method described in clause 1A or 2A, wherein determining a minimum process grid for an inter-prediction related video coding process includes receiving one or more syntax elements in a bitstream of video data, the one or more syntax elements indicating the size of the minimum process grid.

[0215]

[0204] Clause 7A: The method described in clause 1A or 2A, wherein determining a minimum process grid for the inter-prediction related video coding process includes determining a minimum process grid for the inter-prediction related video coding process based on a size of the block.

[0216]

[0205] Clause 8A: A method as described in clause 1A or 2A, wherein determining a minimum process grid for an inter-prediction related video coding process includes determining a minimum process grid for the inter-prediction related video coding process based on the inter-prediction related video coding process.

[0217]

[0206] Clause 9A: The method of any one of clauses 1A to 8A, wherein coding comprises decoding.

[0218]

[0207] Clause 10A:- The method of any one of clauses 1A to 8A, wherein coding comprises encoding.

[0219]

[0208] Clause 11A: A device for coding video data, the device comprising one or more means for performing the method according to any one of clauses 1A to 8A.

[0220]

[0209] Clause 12A: The device of clause 11A, wherein the one or more means include one or more processors implemented in circuitry.

[0221]

[0210] Clause 13A: The device of clause 11A or 12A, further comprising a memory for storing video data.

[0222]

[0211] Clause 14A: The device of any one of clauses 11A to 13A, further comprising a display configured to display the decoded video data.

[0223]

[0212] Clause 15A: The device of any one of clauses 11A to 14A, wherein the device includes one or more of a camera, a computer, a mobile device, a broadcast receiver device, or a set-top box.

[0224]

[0213] Clause 16A: The device of any one of clauses 11A to 15A, wherein the device includes a video decoder.

[0225]

[0214] Clause 17A: The device of any one of clauses 11A to 16A, wherein the device includes a video encoder.

[0226]

[0215] Clause 18A: A computer-readable storage medium storing instructions that, when executed, cause one or more processors to perform the method of any one of clauses 1A to 8A.

[0227]

[0216] Clause 19A: A device for encoding video data, comprising: means for determining that a block of the video data is coded using an inter-prediction related video coding process; means for determining a minimum process grid for the inter-prediction related video coding process; and means for deriving a motion vector for the block of the video data based on the minimum process grid.

[0228]

[0217] Clause 1B: A method of decoding video data, comprising: performing motion compensation for a block of video data using a first process grid size; determining a second process grid size for a subsequent inter-prediction-related video coding process, the second process grid size being larger than the first process grid size; determining whether the block of video data has at least one sample having a motion vector that is different from at least one other sample in the block of the second process grid size; and performing the subsequent inter-prediction-related video coding process for the block of video data using the second process grid size in response to determining that the block of video data has at least one sample having a motion vector that is different from at least one other sample in the block of the second process grid size;

[0218] A method comprising: outputting a decoded version of the block of video data.

[0229]

[0219] Clause 2B: The method of clause 1B, wherein the subsequent inter-prediction related video coding process includes local illumination compensation.

[0230]

[0220] Clause 3B: The method of clause 1B, wherein the subsequent inter-prediction related video coding process includes an out-of-bounds check.

[0231]

[0221] Clause 4B: The method of any one of clauses 1B to 3B, wherein the first process grid size is 1x1.

[0232]

[0222] Clause 5B: The method of any one of clauses 1B to 4B, wherein the second process grid size is 4x4 or greater.

[0233]

[0223] Clause 6B: A method according to any one of clauses 1B to 5B, wherein performing motion compensation for a block of video data using a first process grid size includes performing affine motion compensation for the block of video data.

[0234]

[0224] Clause 7B: The method of any one of clauses 1B to 6B, wherein the blocks of video data comprise coding blocks of a coding unit.

[0235]

[0225] Clause 8B: The method of any one of clauses 1B to 7B, wherein determining the second process grid size includes determining the second process grid size to be equal to a size of the sub-block.

[0236]

[0226] Clause 9B: A method according to any one of clauses 1B to 8B, wherein determining a second process grid size for a subsequent inter-prediction related video coding process includes receiving one or more syntax elements in a bitstream of video data, wherein the one or more syntax elements indicate the second process grid size.

[0237]

[0227] Clause 10B: A method according to any one of clauses 1B to 8B, wherein determining a second process grid size for a subsequent inter-prediction related video coding process includes determining a second process grid size for the subsequent inter-prediction related video coding process based on the size of the block.

[0238]

[0228] Clause 11B: A method described in any one of clauses 1B to 8B, wherein determining a second process grid size for a subsequent inter-prediction related video coding process includes determining a second process grid size for the subsequent inter-prediction related video coding process based on the subsequent inter-prediction related video coding process.

[0239]

[0229] Clause 12B: A method according to any one of clauses 1B to 11B, wherein a block of video data includes a plurality of sub-blocks having a plurality of different motion vectors, performing motion compensation for the block of video data using a first process grid size includes predicting each of the plurality of sub-blocks using a corresponding motion vector from the plurality of different motion vectors, and performing a subsequent inter-prediction related video coding process for the block of video data using a second process grid size includes deriving a motion vector based on the plurality of different motion vectors and using the derived motion vector for the subsequent inter-prediction related video coding process.

[0240]

[0230] Clause 13B: The method of clause 12B, wherein deriving a motion vector based on a plurality of different motion vectors includes selecting one of the plurality of different motion vectors as the derived motion vector.

[0241]

[0231] Clause 14B: The method of clause 12B, wherein deriving a motion vector based on a plurality of different motion vectors includes determining an average of two or more of the plurality of different motion vectors.

[0242]

[0232] Clause 15B: The method of any one of clauses 1B to 8B or 10B to 14B, wherein the decoding method is performed as part of a video encoding process.

[0243]

[0233] Clause 16B: A device for decoding video data, comprising one or more memory units configured to store the video data, and one or more processors implemented in a circuit coupled to the one or more memory units, performing motion compensation for a block of the video data using a first process grid size, determining a second process grid size for a subsequent inter-prediction related video coding process, the second process grid size being larger than the first process grid size, determining whether the block of video data has at least one sample having a motion vector that differs from at least one other sample in the block of the second process grid size, and in response to determining that the block of video data has at least one sample having a motion vector that differs from at least one other sample in the block of the second process grid size, performing the subsequent inter-prediction related video coding process for the block of video data using the second process grid size,

[0234] A device comprising: one or more processors configured to output a decoded version of a block of video data.

[0244]

[0235] Clause 17B: The device of clause 16B, wherein the subsequent inter-prediction related video coding process includes local lighting compensation.

[0245]

[0236] Clause 18B: The device of clause 16B, wherein the subsequent inter-prediction related video coding process includes an out-of-bounds check.

[0246]

[0237] Clause 19B: The device of any one of clauses 16B to 18B, wherein the first process grid size is 1x1.

[0247]

[0238] Clause 20B: The device of any one of clauses 16B to 19B, wherein the second process grid size is 4x4 or greater.

[0248]

[0239] Clause 21B: A device described in any one of clauses 16B to 20B, wherein one or more processors are further configured to perform affine motion compensation for the block of video data using a first process grid size.

[0249]

[0240] Clause 22B: The device of any one of clauses 16B to 21B, wherein the blocks of video data comprise coding blocks of a coding unit.

[0250]

[0241] Clause 23B: A device described in any one of clauses 16B to 22B, wherein, to determine the second process grid size, one or more processors are further configured to determine the second process grid size to be equal to the size of the sub-block.

[0251]

[0242] Clause 24B: A device described in any one of clauses 16B to 22B, wherein one or more processors are further configured to receive one or more syntax elements in a bitstream of video data to determine a second process grid size for a subsequent inter-prediction related video coding process, the one or more syntax elements indicating the second process grid size.

[0252]

[0243] Clause 25B: A device described in any one of clauses 16B to 22B, wherein, to determine a second process grid size for a subsequent inter-prediction related video coding process, one or more processors are further configured to determine the second process grid size for the subsequent inter-prediction related video coding process based on the size of the block.

[0253]

[0244] Clause 26B: A device described in any one of clauses 16B to 22B, wherein, in order to determine a second process grid size for a subsequent inter-prediction related video coding process, one or more processors are further configured to determine the second process grid size for the subsequent inter-prediction related video coding process based on the subsequent inter-prediction related video coding process.

[0254]

[0245] Clause 27B: A device described in any one of clauses 16B to 26B, wherein a block of video data includes a plurality of sub-blocks having a plurality of different motion vectors, and wherein, to perform motion compensation for the block of video data using a first process grid size, one or more processors are further configured to predict each of the plurality of sub-blocks using a corresponding motion vector from the plurality of different motion vectors, and, to perform a subsequent inter-prediction related video coding process for the block of video data using a second process grid size, the one or more processors are further configured to derive a motion vector based on the plurality of different motion vectors and use the derived motion vector for the subsequent inter-prediction related video coding process.

[0255]

[0246] Clause 28B: The device described in Clause 27B, wherein to derive a motion vector based on a plurality of different motion vectors, the one or more processors are further configured to select one of the plurality of different motion vectors as the derived motion vector.

[0256]

[0247] Clause 29B: The device described in Clause 27B, wherein to derive a motion vector based on a plurality of different motion vectors, the one or more processors are further configured to determine an average of two or more of the plurality of different motion vectors.

[0257]

[0248] Clause 30B: The device of any one of clauses 16B to 29B, wherein the device includes a video decoder.

[0258]

[0249] Clause 31B: The device of any one of clauses 16B to 30B, further comprising a display configured to display the decoded video data.

[0259]

[0250] Clause 32B: The device of any one of clauses 16B to 31B, wherein the device includes one or more of a camera, a computer, a mobile device, a broadcast receiver device, or a set-top box.

[0260]

[0251] Clause 33B: The device of any one of clauses 16B to 32B, wherein the device includes a video encoder.

[0261]

[0252] Clause 34B: A computer-readable storage medium storing instructions that, when executed by one or more processors, cause the one or more processors to perform motion compensation for a block of video data using a first process grid size; determine a second process grid size for a subsequent inter-prediction related video coding process, the second process grid size being larger than the first process grid size; determine whether the block of video data has at least one sample having a motion vector that is different from at least one other sample in the block of the second process grid size; and, in response to determining that the block of video data has at least one sample having a motion vector that is different from at least one other sample in the block of the second process grid size, perform the subsequent inter-prediction related video coding process for the block of video data using the second process grid size;

[0253] A computer-readable storage medium that outputs a decoded version of a block of video data.

[0262]

[0254] Clause 35B: A device for decoding video data, comprising: means for performing motion compensation for a block of video data using a first process grid size; means for determining a second process grid size for a subsequent inter-prediction related video coding process, the second process grid size being larger than the first process grid size; means for determining whether the block of video data has at least one sample having a motion vector that differs from at least one other sample in the block of the second process grid size; means for performing the subsequent inter-prediction related video coding process for the block of video data using the second process grid size in response to determining that the block of video data has at least one sample having a motion vector that differs from at least one other sample in the block of the second process grid size; and means for outputting a decoded version of the block of video data.

[0263] It should be recognized that in some examples, some acts or events of any of the techniques described herein may be performed in a different order, added, merged, or omitted entirely (e.g., not all described acts or events may be required to practice the techniques). Moreover, in some examples, acts or events may be performed in parallel rather than sequentially, for example, through multithreading, interrupt processing, or multiple processors.

[0264] In one or more examples, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code and executed by a hardware-based processing unit. Computer-readable media may include computer-readable storage media, which correspond to tangible media such as data storage media, or communication media, including any medium that facilitates transfer of a computer program from one place to another, for example, according to a communications protocol. As such, computer-readable media may generally correspond to (1) tangible computer-readable storage media that are non-transitory, or (2) communication media such as a signal or carrier wave. Data storage media may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and / or data structures to implement the techniques described in this disclosure. A computer program product may include a computer-readable medium.

[0265]

[0257] By way of example, and not limitation, such computer-readable storage media may include one or more of RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly referred to as a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included within the definition of medium. However, it should be understood that computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transitory media, but instead cover non-transitory tangible storage media. As used herein, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically using a laser. Combinations of the above should also be included within the scope of computer-readable media.

[0266]

[0258] The instructions may be executed by one or more processors, such as one or more DSPs, general-purpose microprocessors, ASICs, FPGAs, or other equivalent integrated or discrete logic circuitry. Accordingly, the terms "processor" and "processing circuitry" as used herein may refer to either the above structures or any other structure suitable for implementing the techniques described herein. Additionally, in some aspects, the functionality described herein may be provided in dedicated hardware and / or software modules configured for encoding and decoding, or may be incorporated into a combined codec. It is also possible for these techniques to be implemented entirely in one or more circuits or logic elements.

[0267] The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC), or a set of ICs (e.g., a chipset). Although various components, modules, or units have been described in this disclosure to highlight functional aspects of devices configured to implement the disclosed techniques, they do not necessarily require realization by different hardware units. Rather, as described above, the various units may be combined in a codec hardware unit or may be provided by a collection of interoperable hardware units, including one or more processors as described above, in conjunction with suitable software and / or firmware.

[0268]

[0260] Various examples have been described. These and other examples are within the scope of the following claims.

Claims

1. 1. A method for decoding video data, comprising: performing motion compensation for the blocks of video data using a first process grid size; determining a second process grid size for a subsequent inter-prediction related video coding process, the second process grid size being larger than the first process grid size; determining whether the block of video data has at least one sample having a motion vector that is different from at least one other sample in the block of the second process grid size; In response to determining that the block of video data has at least one sample having the different motion vector from at least one other sample in the block of the second process grid size, performing the subsequent inter-prediction associated video coding process for the block of video data using the second process grid size; outputting a decoded version of said block of video data; A method comprising:

2. The method of claim 1 , wherein the subsequent inter-prediction related video coding process includes local illumination compensation.

3. The method of claim 1 , wherein the subsequent inter-prediction related video coding process includes an out-of-bounds check.

4. The method of claim 1 , wherein the first process grid size is 1×1.

5. The method of claim 1 , wherein the second process grid size is 4×4 or greater.

6. 2. The method of claim 1, wherein performing motion compensation for the block of video data using the first process grid size comprises performing affine motion compensation for the block of video data.

7. The method of claim 1 , wherein the blocks of video data comprise coding blocks of a coding unit.

8. The method of claim 1 , wherein determining the second process grid size comprises determining the second process grid size to be equal to a size of a sub-block.

9. 2. The method of claim 1 , wherein determining the second process grid size for the subsequent inter-prediction-related video coding process comprises receiving one or more syntax elements in a bitstream of the video data, the one or more syntax elements indicating the second process grid size.

10. 2. The method of claim 1 , wherein determining the second process grid size for the subsequent inter-prediction-related video coding process comprises determining the second process grid size for the subsequent inter-prediction-related video coding process based on a size of the block.

11. 2. The method of claim 1, wherein determining the second process grid size for the subsequent inter-prediction-related video coding process comprises determining the second process grid size for the subsequent inter-prediction-related video coding process based on the subsequent inter-prediction-related video coding process.

12. the block of video data includes a plurality of sub-blocks having a plurality of different motion vectors; performing the motion compensation for the block of video data using the first process grid size includes predicting each of the plurality of sub-blocks using a corresponding motion vector of the plurality of different motion vectors; performing the subsequent inter-prediction-related video coding process for the block of video data using the second process grid size includes deriving a motion vector based on the plurality of different motion vectors; and using the derived motion vector for the subsequent inter-prediction-related video coding process. The method of claim 1.

13. The method of claim 12 , wherein deriving the motion vector based on the plurality of different motion vectors comprises selecting one of the plurality of different motion vectors as the derived motion vector.

14. The method of claim 12 , wherein deriving the motion vector based on the plurality of different motion vectors comprises determining an average of two or more of the plurality of different motion vectors.

15. The method of claim 1 , wherein the method of decoding is performed as part of a video encoding process.

16. 1. A device for decoding video data, comprising: one or more memory units configured to store video data; one or more processors implemented in circuitry coupled to the one or more memory units, performing motion compensation for the blocks of video data using a first process grid size; determining a second process grid size for a subsequent inter-prediction related video coding process, the second process grid size being larger than the first process grid size; determining whether the block of video data has at least one sample having a motion vector that is different from at least one other sample in the block of the second process grid size; responsive to determining that the block of video data has at least one sample having the different motion vector from at least one other sample in the block of the second process grid size, performing the subsequent inter-prediction associated video coding process for the block of video data using the second process grid size; outputting a decoded version of said block of video data. one or more processors configured to A device comprising:

17. The device of claim 16 , wherein the subsequent inter-prediction related video coding process includes local lighting compensation.

18. The device of claim 16 , wherein the subsequent inter-prediction related video coding process includes an out-of-bounds check.

19. 17. The device of claim 16, wherein the first process grid size is 1x1.

20. The device of claim 16 , wherein the second process grid size is 4×4 or greater.

21. 17. The device of claim 16, wherein to perform motion compensation for the blocks of video data using the first process grid size, the one or more processors are further configured to perform affine motion compensation for the blocks of video data.

22. The device of claim 16 , wherein the blocks of video data comprise coding blocks of a coding unit.

23. 17. The device of claim 16, wherein, to determine the second process grid size, the one or more processors are further configured to determine the second process grid size to be equal to a size of a sub-block.

24. 17. The device of claim 16, wherein the one or more processors are further configured to receive one or more syntax elements in a bitstream of the video data to determine the second process grid size for the subsequent inter-prediction-related video coding process, the one or more syntax elements indicating the second process grid size.

25. 17. The device of claim 16, wherein the one or more processors are further configured to: determine the second process grid size for the subsequent inter-prediction-related video coding process based on a size of the block;

26. 17. The device of claim 16, wherein, to determine the second process grid size for the subsequent inter-prediction-related video coding process, the one or more processors are further configured to determine the second process grid size for the subsequent inter-prediction-related video coding process based on the subsequent inter-prediction-related video coding process.

27. the block of video data includes a plurality of sub-blocks having a plurality of different motion vectors; to perform the motion compensation for the block of video data using the first process grid size, the one or more processors are further configured to predict each of the plurality of sub-blocks using a corresponding motion vector from the plurality of different motion vectors; and performing the subsequent inter-prediction-related video coding process for the block of video data using the second process grid size, the one or more processors further configured to: derive a motion vector based on the plurality of different motion vectors; and use the derived motion vector for the subsequent inter-prediction-related video coding process.

17. The device of claim 16.

28. 28. The device of claim 27, wherein to derive the motion vector based on the plurality of different motion vectors, the one or more processors are further configured to select one of the plurality of different motion vectors as the derived motion vector.

29. 28. The device of claim 27, wherein to derive the motion vector based on the plurality of different motion vectors, the one or more processors are further configured to determine an average of two or more of the plurality of different motion vectors.

30. The device of claim 16 , wherein the device includes a video decoder.

31. 17. The device of claim 16, further comprising a display configured to display the decoded video data.

32. The device of claim 16 , wherein the device comprises one or more of a camera, a computer, a mobile device, a broadcast receiver device, or a set-top box.

33. The device of claim 16 , wherein the device comprises a video encoder.

34. 1. A computer-readable storage medium storing instructions that, when executed by one or more processors, cause the one or more processors to: performing motion compensation for the blocks of video data using a first process grid size; determining a second process grid size for a subsequent inter-prediction related video coding process, the second process grid size being larger than the first process grid size; determining whether the block of video data has at least one sample having a motion vector that is different from at least one other sample in the block of the second process grid size; responsive to determining that the block of video data has at least one sample having the different motion vector from at least one other sample in the block of the second process grid size, performing the subsequent inter-prediction associated video coding process for the block of video data using the second process grid size; outputting a decoded version of said block of video data; A computer-readable storage medium.

35. 1. A device for decoding video data, comprising: means for performing motion compensation for blocks of video data using a first process grid size; means for determining a second process grid size for a subsequent inter-prediction related video coding process, the second process grid size being larger than the first process grid size; means for determining whether the block of video data has at least one sample having a different motion vector than at least one other sample in the block of the second process grid size; means for performing the subsequent inter-prediction associated video coding process for the block of video data using the second process grid size in response to determining that the block of video data has the at least one sample having the different motion vector from the at least one other sample in a block of the second process grid size; means for outputting a decoded version of said block of video data; A device comprising:

Images