Semiconductor device

Abstract

To provide a semiconductor device capable of supplying a signal with sufficient amplitude to a scan line while suppressing power consumption. Another object of one embodiment of the present invention is to provide a semiconductor device in which distortion of a signal supplied to a scan line can be suppressed and rise time or fall time can be shortened while power consumption is suppressed.SOLUTION: A semiconductor device includes a plurality of pixels each including a display element and at least one first transistor, and a scan line driver circuit that supplies a signal for selecting the plurality of pixels to a scan line, in which a pixel electrode layer of the display element, a gate electrode layer, a source electrode layer, and a drain electrode layer of the first transistor, and the scan line driver circuit include a light-transmitting conductive film, and the source electrode layer of the second transistor is connected to the scan line.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to an active matrix semiconductor device. [Background technology]

[0002] An active matrix display device has multiple scanning lines and signal lines in the row and column directions. The lines are routed so that they intersect, and at the intersections there are transistors, pixel electrodes, and storage capacitors. The pixel is formed by a plurality of scanning lines that sequentially drive the pixel and a pixel electrode. The display is controlled by a signal line that supplies a display signal to the display element, and the scanning lines are controlled by a scanning line that controls the scanning lines. A signal line driver circuit for controlling the signal lines is connected to the signal lines. These driving circuits have the same number of output lines as the number of scanning lines and signal lines to sequentially control multiple pixels. It has a force end.

[0003] In recent years, display devices have become increasingly high-definition and large, and the number of scanning lines and signal lines has increased. However, there is a strong need for lower power consumption. A technique for reducing power consumption by reducing the number of outputs of a display driver circuit is disclosed.

[0004] Specifically, a scanning line driving circuit having a scanning line driver IC and a scanning line signal branching circuit; By creating multiple scan line switching elements, the number of output terminals of the scan line driver IC can be reduced. This allows for low power consumption driving, and the duplexing of the scanning line switching elements is also The technology described in Patent Document 1 below can reduce the duty ratio and improve reliability. be. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-311879 Summary of the Invention [Problem to be solved by the invention]

[0006] In the prior art, when the scanning line switching elements are made with a single polarity, the scanning line driving The output signal of the circuit is a scanning line selection signal supplied to the scanning line via the scanning line switching element. The amplitude is greater than the threshold voltage (Vth) of the scanning line switching element than the output signal of the scanning line driving circuit. (scanning line selection signal = output signal of scanning line driving circuit - scanning The scanning line switching element is, for example, a transistor. Here, the scanning line switching element will be described as a transistor.

[0007] The output signal of the scanning line driver circuit is applied to the gate electrode of the transistor and one of the source and drain. The amplitude of the output signal from the scanning line driver circuit is input to the V th (=scanning line selection signal). For example, An output signal from the scanning line driver circuit is input to either the source or drain electrode of the transistor. As the transistor turns on, the source or drain The potential of one electrode changes so as to become the same as the potential of the output signal from the scanning line driving circuit. However, the other electrode of the source or drain of the transistor is connected to the output signal of the scanning line driver circuit. The voltage Vgs between the gate electrode and source of the transistor reaches Vth before it reaches the same potential as the signal. In this case, the transistor is in an off state, and the source or The potential of the other electrode of the drain stops changing. The amplitude of the supplied scanning line selection signal is higher than the Vt of the transistor It may be smaller by h.

[0008] Another example is that the scanning line selection signal may be dull. The rise time or fall time may become longer. These phenomena are due to the above reasons. For example, the gate electrode of a transistor and one of the source or drain electrodes The output signal of the scanning line driving circuit is input to the transistor, and the transistor is turned on. Since the transistor is turned on, the potential of the other electrode of the source or drain becomes equal to the scanning line The potential changes to the same as the potential of the output signal of the driver circuit. At this time, the Vg of the transistor s becomes smaller in response to changes in the potential of the other electrode, the source or drain of the transistor. This can cause distortion in the scan line selection signal, and , the rise or fall time may become longer.

[0009] To solve the above problem, a signal with a higher amplitude than the output signal of the scanning line driver circuit is used. However, a separate signal or power supply voltage is required, which increases power consumption.

[0010] To provide a semiconductor device capable of supplying a signal of sufficient amplitude to a scanning line while suppressing power consumption. Another issue is to suppress distortion of the signal supplied to the scanning line while suppressing power consumption. The object of the present invention is to provide a semiconductor device capable of shortening the rise time or fall time. It shall be one of the following. [Means for solving the problem]

[0011] One embodiment of the present invention is a display device including a plurality of pixels each having a display element and at least one transistor. a scanning line driving circuit that supplies a signal to the scanning line for selecting a specific pixel from the plurality of pixels; The semiconductor device has a pixel electrode layer of a display element and a gate electrode layer of a transistor. The source electrode layer, the drain electrode layer, and the scan line are formed using a light-transmitting conductive film. The scanning line driver circuit is a transistor and a gate electrode layer and a source electrode layer of the transistor. a capacitor element for holding a voltage of the transistor, and a source electrode layer of the transistor is connected to a scan line. There are.

[0012] One aspect of the present invention is a display device including a plurality of pixels each having a display element and at least one first transistor. and a scanning line driver that supplies a signal to the scanning line for selecting a specific pixel from the plurality of pixels. The semiconductor device has a pixel electrode layer of the display element and a gate electrode of the first transistor. The gate electrode layer, the source electrode layer, the drain electrode layer, and the scan line are formed of a light-transmitting conductive film. The scanning line driving circuit uses a second transistor and a gate voltage of the second transistor. a capacitance element for holding a voltage between the electrode layer and the source electrode layer; and a gate electrode of the second transistor. and a third transistor for controlling the connection between the layer and the ground electrode. The source electrode layer of the pixel is connected to the scanning line. [Effects of the Invention]

[0013] According to one aspect of the present invention, a bootstrap operation is used to apply a signal of sufficient amplitude to the scan line. It is possible to provide a high-quality signal, and also to suppress signal distortion and improve rise time or fall time. Furthermore, since it does not require a power supply voltage higher than the input signal, it consumes low power. This also leads to power driving. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a cross-sectional view illustrating a first embodiment. [Figure 2] 1A and 1B are a cross-sectional view and a plan view illustrating a first embodiment. [Figure 3] 1A and 1B are a cross-sectional view and a plan view illustrating a first embodiment. [Figure 4] FIG. 10 is a cross-sectional view illustrating a second embodiment. [Figure 5] FIG. 10 is a cross-sectional view illustrating a second embodiment. [Figure 6] 10A and 10B are a circuit diagram and a timing chart illustrating a third embodiment. [Figure 7] 10A and 10B are a circuit diagram and a timing chart for explaining a fourth embodiment; [Figure 8] FIG. 13 is a circuit diagram illustrating a fifth embodiment. [Figure 9] FIG. 13 is a circuit diagram illustrating a sixth embodiment. [Figure 10] FIG. 13 is a circuit diagram illustrating a seventh embodiment. [Figure 11] FIG. 13 is a circuit diagram illustrating an eighth embodiment. [Figure 12] FIG. 13 is a circuit diagram illustrating a ninth embodiment. [Figure 13] 13 is a timing chart illustrating the ninth embodiment. [Figure 14] FIG. [Figure 15] FIG. [Figure 16] FIG. [Figure 17] Drawings explaining examples of actual products. [Figure 18] Drawings explaining examples of actual products. [Figure 19] FIG. 1 is a cross-sectional view illustrating a first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] The embodiments of the present invention will be described below with reference to the drawings. The present invention is not limited to the above embodiment, and various modifications and variations in form and detail may be made without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the present invention. It should not be construed as being limited to the description of the embodiments.

[0016] (Embodiment 1) A semiconductor device and a manufacturing method of the semiconductor device will be described with reference to FIGS. 1 and 2. shows an example of the cross-sectional structure of two thin film transistors with different structures fabricated on the same substrate. The thin film transistor 1470 shown in FIG. 2A is a bottom gate thin film transistor called a channel etch type. The thin film transistor 1460 is a bottom contact type (inverted coplanar type) This is one of the bottom gate structures known as MOSFETs.

[0017] FIG. 2(B1) shows a channel-etched thin film transistor 1470 disposed in a driver circuit. 2(B1) is a cross-sectional view taken along line C1-C2 in FIG. FIG. 2C is a cross-sectional view taken along line C3-C4 in FIG. 2B1.

[0018] The thin film transistor 1470 arranged in the driver circuit is a channel-etched thin film transistor. A gate electrode layer 1401, a first gate insulating layer 1402, and a second gate insulating layer 1403 are formed on a substrate 1400 having an insulating surface. The edge layer 1402a, the second gate insulating layer 1402b, and at least the channel forming region 1434 , a first high-resistance drain region 1431, and a second high-resistance drain region 1432. The oxide semiconductor layer includes a source electrode layer 1405a and a drain electrode layer 1405b. , an oxide insulating layer 1434 that covers the thin film transistor 1470 and is in contact with the channel forming region 1434 407 is provided.

[0019] A first high-resistance drain region 1431 is self-aligned in contact with the lower surface of the source electrode layer 1405a. In addition, a second high-resistance drain is formed in contact with the lower surface of the drain electrode layer 1405b. The gate region 1432 is formed in a self-aligned manner. The channel forming region 1434 is formed in a The first high-resistance drain region 1401 is in contact with the oxide insulating layer 1407 and has a thin film thickness. 431 and the second high-resistance drain region 1432 (I-type region). .

[0020] In addition, the thin film transistor 1470 has a source electrode layer 1405a It is preferable to use a metal material for the drain electrode layer 1405b.

[0021] In addition, in a liquid crystal display device, when a pixel section and a driving circuit are formed on the same substrate, In the circuit, logic circuits such as inverter circuits, NAND circuits, NOR circuits, and latch circuits are used. The thin-film transistors that make up the sensor, the sense amplifier, the constant voltage generator, the VCO, and other analog components are also included. The thin film transistors that make up the log circuit have only positive polarity between the source and drain electrodes. Therefore, the second high-resistance drain region 1, which is required to have a high breakdown voltage, The width of the first high-resistance drain region 432 may be designed to be wider than the width of the first high-resistance drain region 1431. The first high-resistance drain region 1431 and the second high-resistance drain region 1432 are connected to the gate electrode. The width of the overlap with the pole layer may be increased.

[0022] The thin film transistor 1470 disposed in the driving circuit is a thin film transistor with a single gate structure. Although the above description is given using a transistor, a multi-gate transistor having a plurality of channel forming regions may be used as needed. Thin film transistors with gate structures can also be formed.

[0023] In addition, a conductive layer 1406 is provided so as to overlap the channel formation region 1434. 6 is electrically connected to the gate electrode layer 1401 and set to the same potential. By applying gate voltages from above and below the oxide semiconductor layer disposed between the gate electrode 1401 and the conductive layer 1406, In addition, the conductive layer 1406 can be set to a potential different from that of the gate electrode layer 1401, for example, a fixed potential. When the potential is set to GND or 0V, the electrical characteristics of the TFT, such as the threshold voltage, are controlled. It is possible.

[0024] A protective insulating layer 1408 and a planarizing layer 1409 are provided between the conductive layer 1406 and the oxide insulating layer 1407. An insulating layer 1409 is laminated on the insulating layer 1409 .

[0025] The protective insulating layer 1408 is formed by a first gate insulating layer provided below the protective insulating layer 1408. It is preferable that the insulating film 1402a is in contact with the insulating film 1402a or the insulating film 1402b. Water, hydrogen ions, and OH - It blocks the intrusion of impurities such as The first gate insulating layer 1402a in contact with the protective insulating layer 1408 or the underlying insulating film is nitrided. A silicon film is effective.

[0026] FIG. 2B2 shows a bottom-contact thin film transistor 146 disposed in the pixel. 2(B2) is a cross-sectional view taken along line D1-D2 in FIG. Also, FIG. 2(C) is a cross-sectional view taken along line D3-D4 in FIG. 2(B2).

[0027] The thin film transistor 1460 disposed in the pixel is a bottom-contact thin film transistor. A gate electrode layer 1451, a first gate insulating layer 1452, and a second gate insulating layer 1453 are formed on a substrate 1400 having an insulating surface. a second gate insulating layer 1402b, and an oxide semiconductor layer including a channel formation region. 1454, a source electrode layer 1455a, and a drain electrode layer 1455b. The oxide insulating film 1454 covers the transistor 1460 and is in contact with the top surface and side surfaces of the oxide semiconductor layer 1454. An edge layer 1407 is provided.

[0028] However, liquid crystal display devices are driven by alternating current to prevent deterioration of the liquid crystal. By driving, the polarity of the signal potential applied to the pixel electrode layer is changed to positive or negative at regular intervals. The TFT connected to the pixel electrode layer has a pair of electrodes that alternately switch between the source electrode layer and the drain electrode layer. In this specification, for convenience, one of the thin film transistors of the pixel is referred to as a source electrode layer. One electrode layer is called the source electrode layer and the other is called the drain electrode layer. The electrodes alternately function as source and drain electrode layers. In order to achieve this, the width of the gate electrode layer 1451 of the thin film transistor 1460 arranged in the pixel is driven The width may be narrower than that of the gate electrode layer 1401 of the thin film transistor 1470 in the circuit. In addition, in order to reduce the leakage current, the gate voltage of the thin film transistor 1460 disposed in the pixel is The electrode layer 1451 is formed so as not to overlap with the source electrode layer 1455a or the drain electrode layer 1455b. It may be designed as follows.

[0029] The thin film transistor 1460 disposed in the pixel is a thin film transistor with a single gate structure. Although the explanation has been given using a transistor, a multi-gate transistor having multiple channel forming regions may be used as needed. A thin film transistor having the same structure can also be formed.

[0030] In addition, the oxide semiconductor layer 1454 is formed by removing impurities at least after the oxide semiconductor film is formed. Heat treatment to reduce moisture content (heat treatment for dehydration or dehydrogenation) is carried out. After heat treatment for hydration or dehydrogenation and gradual cooling, The oxide insulating layer 1407 and the like are formed to reduce the carrier concentration of the oxide semiconductor layer 1454. The reduction leads to improvement in the electrical characteristics and reliability of the thin film transistor 1460.

[0031] Note that the oxide semiconductor layer 1454 is formed between the source electrode layer 1455a and the drain electrode layer 14 The oxide semiconductor layer 1454 is formed above and partially overlaps the gate electrode 55b. The electrode layer 1451 is connected to the first gate insulating layer 1402a and the second gate insulating layer 1402b. The channel forming region of the thin film transistor 1460 disposed in the pixel is formed by an oxide. In the compound semiconductor layer 1454, a side surface of the source electrode layer 1455a and a side surface of the source electrode layer 1455a facing the side surface are The area sandwiched between the side of the gate electrode layer 1455b and the second gate insulating layer 1402b and overlaps with the gate electrode layer 1451.

[0032] In addition, the thin film transistor 1460 is a light-transmitting thin film transistor having a high aperture ratio. In order to realize a display device having a source electrode layer 1455a and a drain electrode layer 1455 For b, a light-transmitting conductive film is used.

[0033] A gate electrode layer 1451 of the thin film transistor 1460 is also formed using a light-transmitting conductive film. There are.

[0034] In addition, the pixel in which the thin film transistor 1460 is disposed has a pixel electrode layer 1456 or Other electrode layers (such as capacitor electrode layers) and other wiring layers (such as capacitor wiring layers) are resistant to visible light. A display device having a high aperture ratio is realized by using a light-transmitting conductive film as a gate. The insulating layers 1402a and 1402b and the oxide insulating layer 1407 also transmit visible light. It is preferred to use a membrane.

[0035] In this specification, a film that is transparent to visible light is a film that has a visible light transmittance of 75% or more. It refers to a film with a thickness of 100% or less, and if the film is conductive, it is called a transparent conductive film. Also, a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or the like may be referred to as a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or the like. As a metal oxide applied to other electrode layers and other wiring layers, A conductive film may be used. Translucent to visible light means that the transmittance of visible light is 50% or more and 75% or more. It means that it is below.

[0036] Hereinafter, referring to FIGS. 1(A) to 1(F) and FIG. 2(A), a thin film transistor is formed on the same substrate. The manufacturing steps of the thin film transistor 1470 and the thin film transistor 1460 will be described.

[0037] First, a light-transmitting conductive film is formed on a substrate 1400 having an insulating surface. Gate electrode layers 1401 and 1451 are formed by a photolithography process. The gate electrode layers 1401 and 1451 are made of the same material having light-transmitting properties as the gate electrode layers 1401 and 1451, and the same first photolithography The capacitance wiring layer is formed by a photolithography process. If necessary, a capacitance wiring layer is also formed on the drive circuit. If the resist mask is formed by the ink-jet method, the photomask Since no wiring is used, manufacturing costs can be reduced.

[0038] There is no significant limitation on the substrate that can be used for the substrate 1400 having an insulating surface, but At the very least, it must have heat resistance sufficient to withstand subsequent heat treatment. The substrate 1400 having a surface is made of barium borosilicate glass, aluminoborosilicate glass, or the like. Other glass substrates with strain points between 600° C. and 750° C. can be used.

[0039] In addition, when the temperature of the subsequent heat treatment is high, the distortion point of the glass substrate 1400 is 7. It is advisable to use a substrate having a temperature of 30° C. or higher. Glass materials such as borosilicate glass, aluminoborosilicate glass, and barium borosilicate glass Generally, more barium oxide (BaO) is used than boric acid. By including BaO, a more practical heat-resistant glass can be obtained. It is preferable to use a glass substrate containing a large amount of fluorine.

[0040] Instead of the glass substrate 1400, a ceramic substrate, a quartz substrate, or a sapphire substrate may be used. Alternatively, a substrate made of an insulating material such as a plate may be used. Alternatively, a substrate made of a crystallized glass may be used. Cut.

[0041] In addition, an insulating film serving as a base film is provided between the substrate 1400 and the gate electrode layers 1401 and 1451. The base film has a function of preventing diffusion of impurity elements from the substrate 1400. one or more selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film; It can be formed by a laminated structure of films.

[0042] The gate electrode layers 1401 and 1451 are formed of a conductive material that transmits visible light. For example, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, A l-Ga-Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series , Al-Zn-O, In-O, Sn-O, and Zn-O metal oxides can be applied. The thickness of the gate electrode layer 14 is appropriately selected within the range of 50 nm to 300 nm. The metal oxide film deposition method used for 01 and 1451 is the sputtering method or vacuum deposition method (electron beam The deposition method, arc discharge ion plating method, and spray method are used. When using the sputtering method, a target containing 2% to 10% by weight of SiO2 is used. The transparent conductive film is then coated with SiOx (X>0) which inhibits crystallization. In order to prevent crystallization during the heat treatment for dehydration or dehydrogenation in the process It is possible.

[0043] Next, a gate insulating layer is formed on the gate electrode layers 1401 and 1451 .

[0044] The gate insulating layer is formed by depositing a silicon oxide layer, a nitride layer, or the like using a plasma CVD method or a sputtering method. A silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer can be formed as a single layer or a stacked layer. For example, a film is formed by plasma CVD using SiH4, oxygen, and nitrogen as the film forming gas. A silicon oxynitride layer may be formed.

[0045] In this embodiment, the first gate insulating layer 1402a has a thickness of 50 nm or more and 200 nm or less. and a second gate insulating layer 1402b having a thickness of 50 nm to 300 nm. The first gate insulating layer 1402a is a silicon nitride film or a silicon nitride film having a thickness of 100 nm. A silicon nitride oxide film is used. The second gate insulating layer 1402b is a 100 nm thick silicon nitride film. A silicon oxide film of 1000 nm is used.

[0046] Next, a light-transmitting conductive film is formed over the second gate insulating layer 1402b, and then The source electrode layer 1455a and the drain electrode layer 1455b are formed by the photolithography process of 2. 5b is formed (see FIG. 1(A)). The method for forming the light-transmitting conductive film is sputtering. vacuum deposition (electron beam deposition, etc.), arc discharge ion plating, and spray The conductive film is made of a conductive material that is transparent to visible light, such as For example, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-Ga-Zn-O series, Al- Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn-O system, A Metal oxides such as l-Zn-O, In-O, Sn-O, and Zn-O can be used. The film thickness is appropriately selected within the range of 50 nm to 300 nm. In this case, the film is formed using a target containing 2% by weight or more and 10% by weight or less of SiO2, The transparent conductive film contains SiOx (X>0) which inhibits crystallization, and is then processed in a later process. It is possible to suppress crystallization during heat treatment for dehydration or dehydrogenation. do.

[0047] Note that a resist for forming the source electrode layer 1455a and the drain electrode layer 1455b is used. The resist mask may be formed by an ink-jet method. When formed, no photomask is used, thereby reducing manufacturing costs.

[0048] Next, a second gate insulating layer 1402b, a source electrode layer 1455a, and a drain electrode An oxide semiconductor film having a thickness of 2 nm to 200 nm is formed over the layer 1455b. Even if heat treatment for dehydration or dehydrogenation is performed after the formation of the semiconductor film, the oxide semiconductor layer To keep the oxide semiconductor in an amorphous state, it is preferable to make the film thickness as thin as 50 nm or less. When the oxide semiconductor layer is formed and then subjected to heat treatment, the oxide semiconductor layer is crystallized. It is possible to suppress the occurrence of

[0049] Before forming the oxide semiconductor film by sputtering, argon gas was introduced into the plasma. The reverse sputtering that generates the smear is performed, and the smear is adhered to the surface of the second gate insulating layer 1402b. It is preferable to remove the dust particles that are sputtered. In an argon atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma near the substrate. It is also possible to use nitrogen, helium, oxygen, etc. instead of argon atmosphere. Either may be used.

[0050] The oxide semiconductor film is an In-Ga-Zn-O based non-single crystal film, an In-Sn-Zn-O based film, an I n-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al -Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, In this embodiment, an Sn—O-based or Zn—O-based oxide semiconductor film is used. The film is formed by sputtering using an nO-based oxide semiconductor target. The membrane is heated under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically can be formed by sputtering in an atmosphere of argon and oxygen. When using the sputtering method, a target containing 2% to 10% by weight of SiO2 is used. The oxide semiconductor film is then formed by adding SiOx (X>0) which inhibits crystallization. This prevents crystallization during the heat treatment for dehydration or dehydrogenation that is carried out in the process. This can be done.

[0051] Next, the oxide semiconductor film is subjected to a third photolithography process to form an island-shaped oxide semiconductor layer. Note that the oxide film overlapping the source electrode layer 1455a and the drain electrode layer 1455b is In order to obtain the oxide semiconductor layer, the source electrode layer 145 is removed during etching of the oxide semiconductor layer. 5a and drain electrode layer 1455b are removed. The etching conditions are adjusted as appropriate. The resist mask may be formed by an ink-jet method. Since no photomask is used, manufacturing costs can be reduced.

[0052] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the first heat treatment is 350° C. or higher and lower than the strain point of the substrate, preferably 400° C. or higher. Here, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor layer is heated. After heat treatment under a nitrogen atmosphere, the oxide semiconductor layer was The oxide semiconductor layers 1403 and 1453 are obtained by preventing re-mixing of water and hydrogen (see FIG. 1B). In this embodiment, the heating temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated is Then, use the same furnace until the temperature is high enough to prevent water from entering again. The temperature is gradually cooled in a nitrogen atmosphere until the temperature drops to 00°C or more. Dehydration or dehydrogenation can be carried out under an atmosphere of oxygen (carbon dioxide, neon, argon, etc.) or under reduced pressure. Cut.

[0053] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the gas does not contain water, hydrogen, etc. or rare gases such as helium, neon, argon, etc., with a purity of 6N (99.9999%) or higher Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, Preferably, it is 0.1 ppm or less.

[0054] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized and microcrystalline. It may be a crystalline or polycrystalline film.

[0055] The first heat treatment of the oxide semiconductor layer is performed after the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is removed from the heating device. The wafer is then taken out and subjected to a photolithography process.

[0056] In addition, before the formation of the oxide semiconductor film, an inert gas atmosphere (nitrogen, helium, neon) Heat treatment (400°C or higher) in an oxygen atmosphere or reduced pressure (argon, etc.) The gate insulating layer is then formed by removing impurities such as hydrogen and water contained in the layer. That's fine.

[0057] Next, a metal conductive film is formed on the second gate insulating layer 1402b, and then a fourth photo A resist mask 1436 is formed by a lithography process, and selective etching is performed. A metal electrode layer 1435 is formed (see FIG. 1(C)). Materials for the metal conductive film include Al, Elements selected from Cr, Cu, Ta, Ti, Mo, and W, or elements containing the above elements The alloys may be alloys of the above elements or combinations of the above elements.

[0058] The metal conductive film may be a titanium layer, an aluminum layer on the titanium layer, and a titanium layer on the aluminum layer. or a molybdenum layer on an aluminum layer and a molybdenum layer on the aluminum layer. It is preferable to use a three-layer laminate structure in which a molybdenum layer is laminated on a metal layer. The film may have a single layer, a two-layer structure, or a laminated structure of four or more layers.

[0059] Note that the oxide semiconductor layer 1453 and the source electrode layer 14 In order to selectively remove the metal conductive film overlapping the drain electrode layer 1455a and the drain electrode layer 1455b, During etching of the metal conductive film, the oxide semiconductor layer 1453, the source electrode layer 1455a, and The materials and etching conditions are adjusted so that the drain electrode layer 1455b is not removed. Also, a resist mask for forming a metal electrode layer 1435 is formed by inkjet printing. If the resist mask is formed by the ink-jet method, the photomask Since no external power supply is used, manufacturing costs can be reduced.

[0060] Next, the resist mask 1436 is removed, and a resist is formed by a fifth photolithography process. A mask 1437 is formed, and selective etching is performed to form the source electrode layer 1405a and A drain electrode layer 1405b is formed (see FIG. 1(D)). In the etching process, only a portion of the oxide semiconductor layer is etched, leaving an acid layer with a groove (depression). The oxide semiconductor layer 1433 is formed by etching. The resist mask may be formed by an inkjet method. When the film is formed by the method described above, no photomask is used, and therefore the manufacturing cost can be reduced.

[0061] Next, the resist mask 1437 was removed, and the top surface and the side surface of the oxide semiconductor layer 1453 were The oxide insulating layer 1433 is in contact with the groove (recess) of the oxide semiconductor layer 1433. Form 407.

[0062] The oxide insulating layer 1407 has a thickness of at least 1 nm and is formed by a method such as a sputtering method. The oxide insulating layer 1407 is formed by an appropriate method that prevents impurities such as water and hydrogen from being mixed into the oxide insulating layer 1407. In this embodiment, the oxide insulating layer 1407 is a 300-nm-thick silicon oxide film. The film is formed by sputtering. The substrate temperature during film formation is between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. The film is formed under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically The target can be used in an atmosphere of oxygen (argon for example) and oxygen. A silicon dioxide target or a silicon target can be used. For example, a silicon target A silicon oxide film is formed by sputtering in an oxygen and nitrogen atmosphere using the above. The oxide insulating layer 1407 formed in contact with the oxide semiconductor layer with reduced resistance can be , hydrogen ions, OH - It does not contain impurities such as An inorganic insulating film that blocks the insulating film is used, typically a silicon oxide film, a silicon nitride oxide film, or an aluminum oxide film. A film, aluminum oxide nitride, or the like is used.

[0063] Then, a second heat treatment (preferably The temperature is 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower (see FIG. 1(E)). For example, the second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. As a result, the grooves of the oxide semiconductor layer 1433 and the top and side surfaces of the oxide semiconductor layer 1453 are The oxide insulating layer 1407 is heated in contact with the oxide insulating layer 1407.

[0064] Through the above steps, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After the resistance of the oxide semiconductor film is reduced by heat treatment for oxidation, a part of the oxide semiconductor film is selectively treated with excess oxygen. As a result, the channel formation region 1434 overlapping with the gate electrode layer 1401 is The first high-resistance drain region 1431 is I-shaped and overlaps the source electrode layer 1405a. The second high-resistance drain region 1432 overlapping the drain electrode layer 1405b is formed in a self-aligned manner. The oxide semiconductor layer 1453 overlapping with the gate electrode layer 1451 has an i-type structure as a whole. The oxide semiconductor layer 1454 is formed as follows.

[0065] Note that the oxide semiconductor layer overlapping with the drain electrode layer 1405b (and the source electrode layer 1405a) In the conductor layer, a second high-resistance drain region 1432 (or a first high-resistance drain region 1433) is formed. 431), the reliability of the driver circuit can be improved. Specifically, by forming the second high-resistance drain region 1432, the drain electrode layer The conductivity is gradually increased from the second high-resistance drain region 1432 to the channel forming region. Therefore, the drain electrode layer 1405b can be provided with a high When the gate electrode layer 1401 and the drain electrode 1402 are connected to a wiring that supplies a power supply potential VDD, Even if a high electric field is applied between the drain electrode layer 1405b and the high-resistance drain region, the high-resistance drain region acts as a buffer. This prevents a local high electric field from being applied, and improves the breakdown voltage of the transistor. do.

[0066] In addition, an oxide semiconductor layer overlapping with the drain electrode layer 1405b (and the source electrode layer 1405a) In the conductor layer, a second high-resistance drain region 1432 (or a first high-resistance drain region 1433) is formed. 431), the channel forming region 1434 when the driver circuit is formed. The leakage current can be reduced.

[0067] Next, a protective insulating layer 1408 is formed over the oxide insulating layer 1407 (see FIG. 1F). In this embodiment, a silicon nitride film is formed by RF sputtering. is suitable for mass production and is therefore preferred as a method for forming the protective insulating layer 1408. 08 is water, hydrogen ions, OH - It does not contain impurities such as The inorganic insulating film used is a silicon nitride film, an aluminum nitride film, a silicon nitride oxide film, and The protective insulating layer 1408 is formed of a thin film, such as aluminum oxynitride, or the like. It is an insulating film.

[0068] The protective insulating layer 1408 is formed by a first gate insulating layer provided below the protective insulating layer 1408. It is preferable that the insulating film is in contact with the insulating film 1402a or the insulating film that serves as the base. Water, hydrogen ions, and OH - It blocks the intrusion of impurities such as The first gate insulating layer 1402a or the insulating film serving as a base, which is in contact with the protective insulating layer 1408, It is effective to use a silicon nitride film. By providing such a silicon nitride film, the reliability of the display device is improved.

[0069] Next, a planarizing insulating layer 1409 is formed over the protective insulating layer 1408. 09 includes polyimide, acrylic, benzocyclobutene, polyamide, epoxy, etc. In addition to the above organic materials, low dielectric constant materials can be used. low-k materials, siloxane resins, PSG (phosphor glass), BPSG (phosphor boro) In addition, multiple insulating films made of these materials can be stacked. A planarization insulating layer 1409 may be formed by performing a process similar to that described above.

[0070] The siloxane resin is a Si-O- formed material that is made from a siloxane material as a starting material. It corresponds to a resin containing Si bonds. Siloxane resins contain organic groups (e.g., alkane) as substituents. Alternatively, an alkyl group or an aryl group, or a fluoro group may be used. It's okay to be there.

[0071] The method for forming the planarization insulating layer 1409 is not particularly limited, and may be a sputtering method, SOG method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, Clean printing, offset printing, etc.), doctor knife, roll coater, curtain coater A knife coater or the like can be used.

[0072] Next, a sixth photolithography step is performed to form a resist mask, and a planarization insulating layer The drain 1409, the protective insulating layer 1408, and the oxide insulating layer 1407 are etched. A contact hole reaching the electrode layer 1455b is formed. Contact holes reaching the gate electrode layers 1401 and 1451 are also formed. A resist mask for forming a contact hole reaching the ink electrode layer 1455b is then applied. If the resist mask is formed by the ink jet method, the photomask Since no disks are used, manufacturing costs can be reduced.

[0073] Next, the resist mask is removed, and then a light-transmitting conductive film is formed. The conductive film material is indium oxide (In2O3) or indium oxide tin oxide composite. Gold (In2O3-SnO2, abbreviated as ITO) is deposited by sputtering or vacuum deposition. Another material for the transparent conductive film is Al-Zn-O containing nitrogen. non-single crystal film, that is, Al-Zn-ON non-single crystal film and Zn-O non-single crystal film containing nitrogen. A crystalline film or a nitrogen-containing Sn-Zn-O-based non-single crystal film may also be used. The composition ratio (atomic %) of zinc in the nON-based non-single crystal film is 47 atomic % or less, and the non-single crystal film The aluminum composition ratio (atomic %) in the non-single crystal film is larger than that in the The composition ratio (atomic %) of nitrogen in the non-single crystal film is larger than that in the non-single crystal film. Etching is performed using a hydrochloric acid solution. However, etching ITO in particular leaves residue. Therefore, indium oxide zinc oxide alloy (In2 O3-ZnO) may also be used.

[0074] The composition ratio of the light-transmitting conductive film is expressed in atomic percent. -(EPMA:Electron Probe X-ray MicroAnalyze The evaluation will be carried out by analysis using the

[0075] Next, a seventh photolithography step is performed to form a resist mask and apply etching. The unnecessary portions are removed to form the pixel electrode layer 1456 and the conductive layer 1406 (FIG. 2(A) )reference.).

[0076] Through the above process, the thin film transistor 1470 and the thin film transistor 1471 are formed on the same substrate using seven masks. and the thin film transistor 1460 are separately fabricated in the driver circuit or pixel portion. In addition, the first gate insulating layer 1402a and the second gate insulating layer 1402b are formed by dielectric films. In addition, a storage capacitor formed by a capacitance wiring layer and a capacitance electrode layer can also be formed on the same substrate. The thin film transistor 1460 and the storage capacitor are arranged in a matrix corresponding to each pixel. A pixel portion is formed by the above-mentioned, and a driver circuit having a thin film transistor 1470 is arranged around the pixel portion. By this, it is possible to form one of the substrates for manufacturing an active matrix display device. For convenience, this type of substrate is referred to as an active matrix substrate in this specification.

[0077] The pixel electrode layer 1456 is formed by the planarization insulating layer 1409, the protective insulating layer 1408, and the oxide film. The insulating layer 1407 is electrically connected to the capacitor electrode layer through a contact hole formed in the insulating layer 1407. The capacitor electrode layer is formed using the same light-transmitting material and process as the drain electrode layer 1455b. It can be formed by

[0078] The conductive layer 1406 is provided so as to overlap with the channel formation region 1434 of the oxide semiconductor layer. By this, a bias-thermal stress test (hereinafter referred to as In the BT test, the threshold voltage of the thin film transistor 1470 before and after the BT test was The conductive layer 1406 can reduce the amount of change in the value voltage. It may be the same as or different from 1401 and serves as a second gate electrode layer. The potential of the conductive layer 1406 can be set to GND, 0 V, or in a floating state. may be.

[0079] In this embodiment mode, the thin film transistor 1470 used in the driver circuit has a channel forming The conductive layer 1406 is located at a position overlapping the region 1434, but the thin film transistor used for the driver circuit The transistor does not necessarily have to have the conductive layer 1406. The thin film transistor 1470 and the thin film transistor without the conductive layer 1406 are the same as those described above. By using this process, it is possible to form them on the same substrate.

[0080] In the semiconductor device according to one embodiment of the present invention, A source electrode layer, a drain electrode layer, a pixel electrode layer of a display element, and further, a scanning line and a signal line By forming the wiring layer using a light-transmitting conductive film, the aperture ratio of the pixel can be increased. Note that a thin film transistor used in a driver circuit does not necessarily have to be made of an oxide semiconductor. However, it is not necessary to use the thin film transistor 1470 used in the driver circuit as the thin film transistor of the pixel. When the transistor 1460 is formed on the same substrate, a thin film transistor is used as shown in this embodiment mode. The thin film transistor 1470 is preferably formed using an oxide semiconductor, as is the thin film transistor 1460. In this case, the number of steps can be reduced, which is desirable. The thin film transistor 1470 is a unipolar transistor together with the thin film transistor 1460 of the pixel.

[0081] In addition, a resist mask for forming a pixel electrode layer 1456 is formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask is not required. Therefore, the manufacturing cost can be reduced.

[0082] Next, an active matrix in which a capacitance element and a thin film transistor are fabricated using the above process is formed. An example of the cross-sectional structure of a trix substrate is shown in FIG.

[0083] In FIG. 19, a thin film transistor 1470 of a driver circuit and a thin film transistor of a pixel portion are formed on the same substrate. In addition to the capacitor 1460, the capacitor 1502 of the pixel and the capacitor 1505 of the driver circuit are also shown. By using the above process, the capacitor element can be fabricated by using a thin film transistor as well as a photoresist. This can be fabricated without increasing the number of masks or steps. In the display area, the scanning lines, signal lines, and capacitance wiring layer are all transparent. It is made of a conductive film that has a high aperture ratio. The formed driving circuit can use metal wiring to reduce wiring resistance.

[0084] In FIG. 19, a thin film transistor 1470 is a channel-etched thin film transistor provided in a driver circuit. The thin film transistor 1456 is electrically connected to the pixel electrode layer 1456. Reference numeral 460 denotes a bottom-contact thin film transistor provided in a pixel portion.

[0085] The light-transmitting material is the same as that of the gate electrode layer 1451 of the thin film transistor 1460. The capacitor wiring layer 1500 formed in this step includes a first gate insulating layer 1402a, which serves as a dielectric, The capacitor electrode layer 1501 overlaps with the second gate insulating layer 1402b, and the capacitor element 1 The capacitor electrode layer 1501 is connected to the source electrode of the thin film transistor 1460. The light-transmitting material and the process are the same as those of the electrode layer 1455a or the drain electrode layer 1455b. Therefore, the thin film transistor 1460 has a light-transmitting property, and The capacitor element 1502 of each pixel also has light-transmitting properties, which can improve the aperture ratio.

[0086] It is important for the capacitor element 1502 to have light-transmitting properties in order to improve the aperture ratio. In small LCD panels of 100 inches or less, the number of scanning lines is increased to improve the image quality. In order to achieve high definition, a high aperture ratio can be achieved even if the pixel size is made smaller. In addition, a light-transmitting film is used as a component of the thin film transistor 1460 and the capacitor 1502. By using this, a wide viewing angle can be achieved, and high performance can be achieved even if one pixel is divided into multiple sub-pixels. That is, even if a high density group of thin film transistors is arranged, the aperture ratio can be This allows for a large display area, ensuring a sufficient display area. When the pixel has two to four sub-pixels and a capacitor element 1502, the thin film transistor In addition to the capacitor having a light-transmitting property, each capacitor element 1502 also has a light-transmitting property. , the aperture ratio can be improved.

[0087] The capacitor element 1502 is provided below the pixel electrode layer 1456. is electrically connected to the pixel electrode layer 1456 .

[0088] In this embodiment, a capacitor element 150 is formed by using a capacitor electrode layer 1501 and a capacitor wiring layer 1500. However, the structure of the pixel capacitance element is not particularly limited. , a capacitance wiring layer is not provided, and the pixel electrode layer is connected to the scanning lines of the adjacent pixels by a planarizing insulating layer and a protective insulating layer. and a capacitance element is formed by stacking the first gate insulating layer and the second gate insulating layer therebetween. good.

[0089] In addition, when an active matrix type liquid crystal display device is manufactured, A liquid crystal layer is provided between the substrate and the counter substrate on which the counter electrode is provided, and an active matrix The substrate and the counter substrate are fixed together. The counter electrode is electrically connected to the counter substrate. A common electrode is provided on the active matrix substrate, and a terminal electrode electrically connected to the common electrode is provided. This terminal electrode is set to a fixed potential, such as GND or 0V, and the common electrode is set to a fixed potential. The terminal electrode is made of the same light-transmitting material as the pixel electrode layer 1456. It can be achieved.

[0090] In addition, the same light-transmitting material as the gate electrode layer 1401 of the thin film transistor 1470 and The capacitor wiring layer 1503 formed in the same process is the first gate insulating layer 140 which serves as a dielectric. 2a, overlapping with the capacitor electrode layer 1504 via the second gate insulating layer 1402b, A capacitor element 1505 is formed. Note that the capacitor electrode layer 1504 is formed in the thin film transistor 1470. a material having the same light-transmitting property as the source electrode layer 1405a or the drain electrode layer 1405b; and are formed in the same process.

[0091] (Embodiment 2) One embodiment of a semiconductor device and a manufacturing method thereof will be described with reference to FIGS.

[0092] Figures 3(A) to 3(C) show two thin film transistors with different structures fabricated on the same substrate. 3A to 3C show an example of a cross-sectional structure of the thin film transistor 24. 10 is a type of bottom gate structure called a channel etch type, and is a thin film transistor 2420 is a bottom gate structure called a channel protection type (also called a channel stop type) The thin film transistor 2410 and the thin film transistor 2420 are inverted staggered thin film transistors. It is also called a membrane transistor.

[0093] FIG. 3(A1) shows a channel-etched thin film transistor 2410 disposed in a driver circuit. 3(A1) is a plan view, and FIG. 3(B) is a cross-sectional view taken along line C1-C2 in FIG. 3(A1). FIG. 3C is a cross-sectional view taken along line C3-C4 in FIG. 3A1.

[0094] The thin film transistor 2410 arranged in the driving circuit is a channel etch type thin film transistor. 2400 having an insulating surface, a gate electrode layer 2411, a first gate insulating layer 2412, a second gate insulating layer 2413, a first gate insulating layer 2414, a second gate insulating layer 2415, a first gate insulating layer 2416, a second gate insulating layer 2417, a first gate insulating layer 2418, a second gate insulating layer 2419, a first gate insulating layer 2420, a second gate insulating layer 24 The edge layer 2402a, the second gate insulating layer 2402b, and at least the channel forming region 2413 , a first high-resistance drain region 2414a, and a second high-resistance drain region 2414b. the oxide semiconductor layer 2412, the source electrode layer 2415a, and the drain electrode layer 2415b. In addition, an oxide film that covers the thin film transistor 2410 and is in contact with the channel forming region 2413 is included. A nitride insulating layer 2416 is provided.

[0095] The first high-resistance drain region 2414a is self-aligned in contact with the lower surface of the source electrode layer 2415a. In addition, a second high-resistance drain electrode is formed in contact with the lower surface of the drain electrode layer 2415b. The drain region 2414b is formed in a self-aligned manner. The first high-resistance drain region is in contact with the oxide insulating layer 2416 and has a thin film thickness. and a region having a higher resistance than the second high-resistance drain region 2414a (I-type region )

[0096] In addition, the thin film transistor 2410 has a source electrode layer 2415a It is preferable to use a metal material for the drain electrode layer 2415b.

[0097] In addition, in a liquid crystal display device, when a pixel section and a driving circuit are formed on the same substrate, In the circuit, logic circuits such as inverter circuits, NAND circuits, NOR circuits, and latch circuits are used. The thin-film transistors that make up the sensor, the sense amplifier, the constant voltage generator, the VCO, and other analog components are also included. The thin film transistors that make up the log circuit have only positive polarity between the source and drain electrodes. Therefore, the second high resistance drain, which is required to have a high breakdown voltage, The width of the region 2414b is set wider than the width of the other first high-resistance drain region 2414a. In addition, the first high-resistance drain region 2414a and the second high-resistance drain region 2414b may be formed. The width of the region 2414b overlapping the gate electrode layer may be increased.

[0098] The thin film transistor 2410 disposed in the driving circuit is a thin film transistor with a single gate structure. Although the above description is given using a transistor, a multi-gate transistor having a plurality of channel forming regions may be used as needed. Thin film transistors with gate structures can also be formed.

[0099] In addition, a conductive layer 2417 is provided so as to overlap the channel formation region 2413. 7 is electrically connected to the gate electrode layer 2411 and set to the same potential. By applying gate voltages from above and below the oxide semiconductor layer disposed between the gate electrode 1 and the conductive layer 2417, In addition, the conductive layer 2417 can be set to a potential different from that of the gate electrode layer 2411, for example, a fixed potential. When the potential is set to GND or 0V, the electrical characteristics of the TFT, such as the threshold voltage, are controlled. It is possible.

[0100] In addition, a protective insulating layer 2403 and a planarizing layer 2404 are provided between the conductive layer 2417 and the oxide insulating layer 2416. An insulating layer 2404 is laminated.

[0101] The protective insulating layer 2403 is a first gate insulating layer provided under the protective insulating layer 2403. It is preferable that the insulating film 2402a is in contact with the insulating film 2402a or the insulating film 2402b. Water, hydrogen ions, and OH - It blocks the intrusion of impurities such as The first gate insulating layer 2402a in contact with the protective insulating layer 2403 or the insulating film serving as the base is nitrided. A silicon film is effective.

[0102] FIG. 3(A2) shows a channel protective thin film transistor 2420 disposed in a pixel. 3(A2) is a cross-sectional view taken along line D1-D2 in FIG. FIG. 3C is a cross-sectional view taken along line D3-D4 in FIG. 3A2.

[0103] The thin film transistor 2420 disposed in the pixel is a channel protection type thin film transistor. A gate electrode layer 2421, a first gate insulating layer 2422, and a second gate insulating layer 2423 are formed on a substrate 2400 having an insulating surface. 402a, the second gate insulating layer 2402b, the oxide semiconductor layer 24 22, an oxide insulating layer 2426 serving as a channel protection layer, a source electrode layer 2425a, and a drain electrode layer 2425b. The insulating layer 2426 is in contact with and protects the source electrode layer 2425a and the drain electrode layer 2425b. An insulating layer 2403 and a planarization insulating layer 2404 are stacked. A pixel electrode layer 2427 in contact with the drain electrode layer 2425b is provided on the pixel electrode layer 404. It is electrically connected to the thin film transistor 2420 .

[0104] In addition, the oxide semiconductor layer 2422 is formed by removing water, which is an impurity, at least after the oxide semiconductor film is formed. Heat treatment (heat treatment for dehydration or dehydrogenation) is carried out to reduce the amount of carbon dioxide. After heat treatment for hydrogenation or dehydrogenation and subsequent gradual cooling, an oxide insulating film is formed in contact with the oxide semiconductor layer. Reducing the carrier concentration in the oxide semiconductor layer by forming an insulating layer or the like is effective for thin-film transistors. This leads to improved electrical characteristics and reliability of the sta 2420.

[0105] The channel formation region of the thin film transistor 2420 disposed in the pixel is formed in the oxide semiconductor layer 2 422, the oxide insulating layer 2426 which is a channel protection layer and the gate electrode layer 2 The thin film transistor 2420 is formed by the oxide insulating layer 2426. In order to protect the source and drain electrode layers 2425a and 2425b, In the etching step, the oxide semiconductor layer 2422 can be prevented from being etched.

[0106] In addition, the thin film transistor 2420 is a light-transmitting thin film transistor having a high aperture ratio. In order to realize a display device having the above structure, the source electrode layer 2425a and the drain electrode layer 2425b are A light-transmitting conductive film is used.

[0107] A gate electrode layer 2421 of the thin film transistor 2420 is also formed using a light-transmitting conductive film. There are.

[0108] In addition, a pixel electrode layer 2427 or Other electrode layers (such as capacitor electrode layers) and other wiring layers (such as capacitor wiring layers) are resistant to visible light. A display device having a high aperture ratio is realized by using a light-transmitting conductive film as a gate. The insulating layers 2402a and 2402b and the oxide insulating layer 2426 are also transparent to visible light. It is preferred to use a membrane.

[0109] In this specification, a film that is transparent to visible light is a film that has a visible light transmittance of 75% or more. It refers to a film with a thickness of 100% or less, and if the film is conductive, it is called a transparent conductive film. Also, a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or the like may be referred to as a gate electrode layer, a source electrode layer, a drain electrode layer, a pixel electrode layer, or the like. As a metal oxide applied to other electrode layers and other wiring layers, A conductive film may be used. Translucent to visible light means that the transmittance of visible light is 50% or more and 75% or more. It means that it is below.

[0110] 4 and 5(A) to 5(E), the thin film transistor 24 The steps for fabricating the thin film transistor 10 and the thin film transistor 2420 will be described.

[0111] First, a light-transmitting conductive film is formed on a substrate 2400 having an insulating surface, and then a first Gate electrode layers 2411 and 2421 are formed by a photolithography process. The gate electrode layers 2411 and 2421 are made of the same material having light-transmitting properties as the gate electrode layers 2411 and 2421, and the same first photolithography. The capacitance wiring layer is formed by a photolithography process. If necessary, a capacitance wiring layer is also formed on the drive circuit. If the resist mask is formed by the ink-jet method, the photomask Since no wiring is used, manufacturing costs can be reduced.

[0112] There is no significant limitation on the substrate that can be used for the substrate 2400 having an insulating surface, but At the very least, it must have heat resistance sufficient to withstand subsequent heat treatment. The same glass substrate as in Embodiment Mode 1 can be used for the substrate 2400 having a surface.

[0113] Instead of the glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. A substrate made of an insulating material may be used, and other materials such as crystallized glass may also be used.

[0114] In addition, an insulating film serving as a base film is provided between the substrate 2400 and the gate electrode layers 2411 and 2421. The underlayer has a function of preventing diffusion of impurity elements from the substrate 2400. one or more selected from a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film; It can be formed by a laminated structure of films.

[0115] The gate electrode layers 2411 and 2421 are formed of a conductive material that transmits visible light. For example, In-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, A l-Ga-Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series , Al-Zn-O, In-O, Sn-O, and Zn-O metal oxides can be applied. The thickness of the gate electrode layer 24 is appropriately selected within the range of 50 nm to 300 nm. The metal oxide film deposition method used in 11 and 2421 is the sputtering method or the vacuum deposition method (electron beam The deposition method, arc discharge ion plating method, and spray method are used. When using the sputtering method, a target containing 2% to 10% by weight of SiO2 is used. The transparent conductive film is then coated with SiOx (X>0) which inhibits crystallization. In order to prevent crystallization during the heat treatment for dehydration or dehydrogenation in the process It is possible.

[0116] Next, a gate insulating layer is formed on the gate electrode layers 2411 and 2421 .

[0117] The gate insulating layer is formed by depositing a silicon oxide layer, a nitride layer, or the like using a plasma CVD method or a sputtering method. A silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer can be formed as a single layer or a stacked layer. For example, a film is formed by plasma CVD using SiH4, oxygen, and nitrogen as the film forming gas. A silicon oxynitride layer may be formed.

[0118] In this embodiment, the first gate insulating layer 2402a has a thickness of 50 nm or more and 200 nm or less. and a second gate insulating layer 2402b having a thickness of 50 nm to 300 nm. The first gate insulating layer 2402a is a silicon nitride film or a silicon nitride film having a thickness of 100 nm. A silicon nitride oxide film is used. The second gate insulating layer 2402b is a 100 nm thick silicon nitride film. A silicon oxide film of 1000 nm is used.

[0119] an oxide semiconductor film having a thickness of 2 nm to 200 nm over the second gate insulating layer 2402b; After the formation of the oxide semiconductor film 2430, a film for dehydration or dehydrogenation is formed. In order to make the oxide semiconductor film amorphous even after heat treatment, the thickness of the oxide semiconductor film must be 50 nm or less. By reducing the thickness of the oxide semiconductor film, it is possible to reduce the thickness of the oxide semiconductor film after the oxide semiconductor layer is formed. When heat treatment is performed, crystallization can be suppressed.

[0120] Note that before the oxide semiconductor film 2430 was formed by a sputtering method, argon gas was introduced. Then, reverse sputtering is performed to generate plasma, and a thin film is attached to the surface of the second gate insulating layer 2402b. It is preferable to remove the dust adhering to the target. Without using a quartz crystal, a voltage was applied to the substrate side using an RF power supply in an argon atmosphere to generate plasma near the substrate. This is a method of modifying the surface by forming a mask. Note that nitrogen or helium atmosphere can be used instead of argon atmosphere. , oxygen, etc. may also be used.

[0121] The oxide semiconductor film 2430 is an In—Ga—Zn—O-based non-single-crystal film, an In—Sn—Zn— O-based, In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, S n-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In In this embodiment, an In-O-based, Sn-O-based, or Zn-O-based oxide semiconductor film is used. The film is formed by sputtering using a Ga-Zn-O oxide semiconductor target. The compound semiconductor film 2430 is formed under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or Formed by sputtering in an atmosphere of rare gas (typically argon) and oxygen In addition, when using the sputtering method, the SiO2 content is 2% by weight or more and 10% by weight or less. The oxide semiconductor film 2430 is formed using a target. X>0) and crystallize during the heat treatment for dehydration or dehydrogenation in the subsequent process. This can prevent the problem from occurring.

[0122] Next, the oxide semiconductor film 2430 is subjected to a second photolithography process to form an island-shaped oxide film. The oxide semiconductor layer is then processed into an island-shaped oxide semiconductor layer. If the resist mask is formed by the ink jet method, the photoresist Since no mask is used, manufacturing costs can be reduced.

[0123] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the first heat treatment is 350° C. or higher and lower than the strain point of the substrate, preferably 400° C. or higher. Here, the substrate is placed in an electric furnace, which is a type of heat treatment apparatus, and the oxide semiconductor layer is heated. After heat treatment under a nitrogen atmosphere, the oxide semiconductor layer was The oxide semiconductor layers 2431 and 2432 are obtained by preventing re-mixing of water and hydrogen (see FIG. 4B). In this embodiment, the heating temperature T at which the oxide semiconductor layer is dehydrated or dehydrogenated is Then, use the same furnace until the temperature is high enough to prevent water from entering again. The temperature is gradually cooled in a nitrogen atmosphere until the temperature drops to 00°C or more. The dehydration or dehydrogenation is carried out under an atmosphere of oxygen (carbon dioxide, neon, argon, etc.) or under reduced pressure.

[0124] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the gas does not contain water, hydrogen, etc. or rare gases such as helium, neon, argon, etc., with a purity of 6N (99.9999%) or higher Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, Preferably, it is 0.1 ppm or less.

[0125] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may be crystallized and microcrystalline. It may be a crystalline or polycrystalline film.

[0126] The first heat treatment of the oxide semiconductor layer is performed after the oxide semiconductor layer is processed into an island-shaped oxide semiconductor layer. In this case, after the first heat treatment, the heating device The substrate is then removed from the mold and subjected to a photolithography process.

[0127] Before the oxide semiconductor film 2430 is formed, an inert gas atmosphere (nitrogen or helium) is used. Heat treatment (400°C or higher) in an oxygen atmosphere or under reduced pressure. The gate insulating layer is then subjected to a thermal treatment (below the strain point of the substrate) to remove impurities such as hydrogen and water contained in the layer. It may also be an edge layer.

[0128] Next, a second gate insulating layer 2402b and an oxide semiconductor layer 2431 and an oxide semiconductor layer 2432 were formed on the second gate insulating layer 2402b. After forming the metal conductive film, a resist mask 243 is formed by a third photolithography process. 3a and 2433b are formed, and selectively etched to form metal electrode layers 2434 and 2435 (See FIG. 4(C)). The material of the metal conductive film is Al, Cr, Cu, Ta, An element selected from Ti, Mo, and W, or an alloy containing the above elements, or There are alloys that combine elements.

[0129] The metal conductive film may be a titanium layer, an aluminum layer on the titanium layer, and a titanium layer on the aluminum layer. or a molybdenum layer on an aluminum layer and a molybdenum layer on the aluminum layer. It is preferable to use a three-layer laminate structure in which a molybdenum layer is laminated on a metal layer. The film may have a single layer, a two-layer structure, or a laminated structure of four or more layers.

[0130] In addition, a resist mask for forming metal electrode layers 2434 and 2435 is formed by inkjet printing. If the resist mask is formed by the ink-jet method, the photomask Since no external power supply is used, manufacturing costs can be reduced.

[0131] Next, the resist masks 2433a and 2433b are removed, and a fourth photolithography Resist masks 2436a and 2436b are formed by the process, and selective etching is performed. The source electrode layer 2415a and the drain electrode layer 2415b are formed by the above-mentioned method (see FIG. 4(D)). In the fourth photolithography step, only a part of the oxide semiconductor layer 2431 is etched. The oxide semiconductor layer 2437 is etched to have a groove (depression). Resist masks 2436a and 2436b are applied to form grooves (recesses) in the substrate layer 2431. The resist mask may be formed by an ink-jet method. Since no photomask is used, manufacturing costs can be reduced.

[0132] Next, the resist masks 2436a and 2436b are removed, and a fifth photolithography A resist mask 2438 is formed to cover the oxide semiconductor layer 2437. The metal electrode layer 2435 on the body layer 2432 is removed (see FIG. 4(E)).

[0133] In the fifth photolithography step, the metal electrode layer 2432 overlapping with the oxide semiconductor layer 2432 is removed. In order to remove the oxide semiconductor layer 243 during etching of the metal electrode layer 2435, The materials and etching conditions are adjusted appropriately so that the second layer 2 is not removed.

[0134] The oxide semiconductor layer 2437 is in contact with the top surface and the side surface of the oxide semiconductor layer 2432 and has a groove (a recess ) and forming an oxide insulating layer 2439 as a protective insulating film in contact with the insulating film.

[0135] The oxide insulating layer 2439 has a thickness of at least 1 nm and is formed by a method such as a sputtering method. The oxide insulating layer 2439 is formed by an appropriate method that prevents impurities such as water and hydrogen from being mixed into the oxide insulating layer 2439. In this embodiment, the oxide insulating layer 2439 is formed using a silicon oxide film having a thickness of 300 nm. The film is formed by sputtering. The substrate temperature during film formation is between room temperature and 300°C. In this embodiment, the temperature is set to 100° C. The film is formed under a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically The target can be used in an atmosphere of oxygen (argon for example) and oxygen. A silicon dioxide target or a silicon target can be used. For example, a silicon target A silicon oxide film is formed by sputtering in an oxygen and nitrogen atmosphere using the above. The oxide insulating layer 2439 formed in contact with the oxide semiconductor layer with low resistance can be , hydrogen ions, OH - It does not contain impurities such as An inorganic insulating film that blocks the insulating film is used, typically a silicon oxide film, a silicon nitride oxide film, or an aluminum oxide film. A film, aluminum oxide nitride, or the like is used.

[0136] Then, a second heat treatment (preferably The temperature is 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower (see FIG. 5(A)). For example, the second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. As a result, the grooves of the oxide semiconductor layer 2437 and the top and side surfaces of the oxide semiconductor layer 2432 The oxide insulating layer 2439 is heated in contact with the oxide insulating layer 2439.

[0137] Through the above steps, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After the resistance of the oxide semiconductor film is reduced by heat treatment for oxidation, a part of the oxide semiconductor film is selectively treated with excess oxygen. As a result, the channel formation region 2413 overlapping with the gate electrode layer 2411 is a first high-resistance drain region 2414a that is I-shaped and overlaps with a source electrode layer 2415a; The second high-resistance drain region 2414b overlapping the drain electrode layer 2415b is formed in a self-aligned manner. The oxide semiconductor layer 2432 overlapping with the gate electrode layer 2421 is entirely formed in an I The oxide semiconductor layer 2422 is formed as a mold.

[0138] However, when the high-resistance (i-type) oxide semiconductor layer 2422 is exposed, When heat treatment is performed under nitrogen, inert gas atmosphere, or reduced pressure, the resistance becomes high (I type Since the resistance of the oxide semiconductor layer 2422 is reduced, Heat treatment performed while the surface is exposed should be performed in an oxygen gas, N2O gas atmosphere, or ultra-dry air. (dew point under atmospheric pressure is -40°C or less, preferably -60°C or less).

[0139] Note that the oxide semiconductor layer overlapping with the drain electrode layer 2415b (and the source electrode layer 2415a) In the conductor layer, a second high-resistance drain region 2414b (or a first high-resistance drain region 2414c) is formed. 414a), the reliability of the drive circuit can be improved. Specifically, by forming the second high-resistance drain region 2414b, the drain voltage The electrode layer 2415b is connected to the second high-resistance drain region 2414b and the channel forming region 2413. It is possible to create a structure in which the conductivity can be changed stepwise over time. When the gate electrode layer 2415b is connected to a wiring that supplies a high power supply potential VDD, Even when a high electric field is applied between the gate electrode layer 2411 and the drain electrode layer 2415b, a high resistance drain The drain region acts as a buffer to prevent localized high electric fields from being applied, improving the breakdown voltage of the transistor. It is possible to achieve a more precise configuration.

[0140] In addition, an oxide semiconductor layer overlapping with the drain electrode layer 2415b (and the source electrode layer 2415a) In the conductor layer, a second high-resistance drain region 2414b (or a first high-resistance drain region 2414c) is formed. 414a) in the channel forming region 2413 when forming a driver circuit. Therefore, the leakage current can be reduced.

[0141] Next, resist masks 2440a and 2440b are formed by a sixth photolithography process. b, and the oxide insulating layer 2439 is selectively etched to form the oxide insulating layers 2416 and The oxide insulating layer 2426 is formed on the oxide semiconductor layer 24 (see FIG. 5B). It is provided on the channel forming region of 22 and functions as a channel protection layer. When an oxide insulating layer is used as the gate insulating layer 2402b as in the embodiment, the oxide insulating layer The etching process of 2439 also etches a part of the gate insulating layer 2402b. The thickness of the oxide insulating layer 2402b may be reduced. When a nitride insulating film with a high selectivity to 439 is used, the gate insulating layer 2402b is partially etched. This can prevent the device from being accessed.

[0142] Next, a light-transmitting conductive film was formed over the oxide semiconductor layer 2422 and the oxide insulating layer 2426. After forming the film, a source electrode layer 2425a and a drain electrode layer 2425b are formed by a seventh photolithography process. A light-transmitting conductive film is formed on the conductive layer 2425b (see FIG. 5C). The methods are sputtering, vacuum deposition (electron beam deposition, etc.), arc discharge ion plating, etc. The conductive film is made of a material that is transparent to visible light. Conductive materials such as In-Sn-Zn-O, In-Al-Zn-O, Sn-Ga- Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, S n-Zn-O, Al-Zn-O, In-O, Sn-O, and Zn-O metal oxides The thickness of the film is appropriately selected within the range of 50 nm to 300 nm. In addition, when using a sputtering method, a target containing 2% by weight or more and 10% by weight or less of SiO2 is used. The transparent conductive film is formed using a SiOx (X>0) that inhibits crystallization. This prevents crystallization during the heat treatment for dehydration or dehydrogenation in the subsequent process. It can be suppressed.

[0143] Note that a resist for forming the source electrode layer 2425a and the drain electrode layer 2425b The mask may be formed by an ink-jet method. This eliminates the need for a photomask, thereby reducing manufacturing costs.

[0144] Next, the oxide insulating layers 2416 and 2426, the source electrode layer 2425a, and the drain electrode layer A protective insulating layer 2403 is formed on the insulating film 2425b. In this embodiment, an RF sputtering method is used. The RF sputtering method is suitable for mass production, so the protective insulating layer 2403 The protective insulating layer 2403 is preferably formed by a method of forming a film using moisture, hydrogen ions, or oxygen ions. Ya, OH - It is an inorganic insulator that does not contain impurities such as chlorine and other substances and blocks their penetration from the outside. Using insulating films, silicon nitride film, aluminum nitride film, silicon nitride oxide film, aluminum oxide nitride film Of course, the protective insulating layer 2403 is a light-transmitting insulating film.

[0145] The protective insulating layer 2403 is a first gate insulating layer provided under the protective insulating layer 2403. It is preferable that the insulating film 2402a or the insulating film that serves as the base be in contact with the substrate. Water, hydrogen ions, and OH - It blocks the intrusion of impurities such as The first gate insulating layer 2402a in contact with the protective insulating layer 2403 or the insulating film serving as a base It is effective to use a silicon nitride film. By providing such a silicon nitride film, the reliability of the display device is improved.

[0146] Next, a planarization insulating layer 2404 is formed over the protective insulating layer 2403. 04 includes polyimide, acrylic, benzocyclobutene, polyamide, epoxy, etc. In addition to the above organic materials, low dielectric constant materials can be used. low-k materials, siloxane resins, PSG (phosphor glass), BPSG (phosphor boro) In addition, multiple insulating films made of these materials can be stacked. A planarization insulating layer 2404 may be formed by performing a process similar to that described above.

[0147] The siloxane resin is a Si-O- formed material that is made from a siloxane material as a starting material. It corresponds to a resin containing Si bonds. Siloxane resins contain organic groups (e.g., alkane) as substituents. Alternatively, an alkyl group or an aryl group, or a fluoro group may be used. It's okay to be there.

[0148] The method for forming the planarization insulating layer 2404 is not particularly limited, and may be a sputtering method, SOG method, spin coating, dip coating, spray coating, droplet ejection method (inkjet method, Clean printing, offset printing, etc.), doctor knife, roll coater, curtain coater A knife coater or the like can be used.

[0149] Next, an eighth photolithography step is performed to form a resist mask and a planarization insulating layer The drain electrode layer 2425b is reached by etching the protective insulating layer 2404 and the protective insulating layer 2403. A contact hole 2441 is formed (see FIG. 5(D)). Contact holes reaching the gate electrode layers 2411 and 2421 are also formed by etching. A resist mask for forming a contact hole reaching the drain electrode layer 2425b is applied. The resist mask may be formed by an ink-jet method. Since no photomask is used, manufacturing costs can be reduced.

[0150] Next, the resist mask is removed, and then a light-transmitting conductive film is formed. The conductive film material is indium oxide (In2O3) or indium oxide tin oxide composite. Gold (In2O3-SnO2, abbreviated as ITO) is deposited by sputtering or vacuum deposition. Another material for the transparent conductive film is Al-Zn-O containing nitrogen. non-single crystal film, that is, Al-Zn-O non-single crystal film and Zn-ON non-single crystal film containing nitrogen. A crystalline film or a nitrogen-containing Sn-Zn-O-based non-single crystal film may also be used. The composition ratio (atomic %) of zinc in the nON-based non-single crystal film is 47 atomic % or less, and the non-single crystal film The aluminum composition ratio (atomic %) in the non-single crystal film is larger than that in the The composition ratio (atomic %) of nitrogen in the non-single crystal film is larger than that in the non-single crystal film. Etching is performed using a hydrochloric acid solution. However, etching ITO in particular leaves residue. Therefore, indium oxide zinc oxide alloy (In2 O3-ZnO) may also be used.

[0151] The composition ratio of the light-transmitting conductive film is expressed in atomic percent. -(EPMA:Electron Probe X-ray MicroAnalyze The evaluation will be carried out by analysis using the

[0152] Next, a ninth photolithography step is performed to form a resist mask and apply etching. The unnecessary portions are removed to form the pixel electrode layer 2427 and the conductive layer 2417 (FIG. 5(E) )reference.).

[0153] By the above process, the thin film transistor 2410 and the thin film transistor 2411 are formed on the same substrate using nine masks. and the thin film transistor 2420 are separately fabricated in the driver circuit or pixel portion. The thin film transistor 2410 for the driving circuit has a first high resistance drain region 241 4a, the second high-resistance drain region 2414b, and the oxide including the channel forming region 2413. A channel-etched thin film transistor including a compound semiconductor layer 2412 is used as a thin film transistor for a pixel. The transistor 2420 is a channel-protective thin film transistor including an oxide semiconductor layer 2422 that is entirely i-type. It is a membrane transistor.

[0154] The first gate insulating layer 2402a and the second gate insulating layer 2402b are dielectrics, and The storage capacitor formed by the capacitor wiring layer and the capacitor electrode layer can also be formed on the same substrate. The film transistor 2420 and the storage capacitor are arranged in a matrix corresponding to each pixel. and a driver circuit having a thin film transistor 2410 is arranged around the pixel portion. This can be used as one of the substrates for manufacturing an active matrix display device. For convenience, this type of substrate is referred to as an active matrix substrate in this specification.

[0155] Note that the pixel electrode layer 2427 is formed over the planarizing insulating layer 2404 and the protective insulating layer 2403. The capacitor electrode layer is electrically connected to the capacitor electrode layer through the contact hole. The source electrode layer 2425a and the drain electrode layer 2425b are made of the same light-transmitting material and process. It can be formed in a process.

[0156] The conductive layer 2417 is provided at a position overlapping with the channel formation region 2413 of the oxide semiconductor layer 2412. By providing a bias-thermal stress test to check the reliability of thin film transistors, In the test (hereinafter referred to as BT test), the thin film transistor 2410 In addition, the conductive layer 2417 can reduce the amount of change in the threshold voltage of the gate. It may be the same as or different from the first gate electrode layer 2411 and functions as a second gate electrode layer. In addition, the potential of the conductive layer 2417 can be set to GND, 0 V, or a floating state. It may be in a locking state.

[0157] In this embodiment mode, the thin film transistor 2410 used in the driver circuit has a channel forming A conductive layer 2417 is provided at a position overlapping the region 2413, but it is a thin film transistor used for a driving circuit. The transistor does not necessarily have to have the conductive layer 2417. The thin film transistor 2410 and the thin film transistor without the conductive layer 2417 are the same as those described above. By using this process, it is possible to form them on the same substrate.

[0158] Furthermore, the thin film transistors used in the driver circuits do not necessarily have to use oxide semiconductors. However, the thin film transistor 2410 used in the driver circuit is replaced with the thin film transistor 242 When the thin film transistor 2410 is formed on the same substrate as the thin film transistor 2410 shown in this embodiment mode, In order to reduce the number of steps, it is preferable to form the thin film transistor 2420 using an oxide semiconductor. In this case, the thin film transistor 2410 used in the driver circuit is This, together with the thin film transistor 2420, constitutes a unipolar transistor.

[0159] In addition, a resist mask for forming the pixel electrode layer 2427 is formed by an ink-jet method. If the resist mask is formed by the inkjet method, a photomask is not required. Therefore, the manufacturing cost can be reduced.

[0160] (Embodiment 3) In this embodiment, an example of a semiconductor device capable of dividing one signal into a plurality of signals is described. Here, as an example, we will explain how to split one signal into three signals. However, the present invention is not limited to this, and one signal may be divided into two or more signals. good.

[0161] First, the structure of the semiconductor device of this embodiment mode will be described with reference to FIG.

[0162] The circuit 100 includes a circuit 110, a circuit 120, and a circuit 130. The circuit 110 includes a scan line The semiconductor device includes a transistor 111 corresponding to a switching element, a circuit 112, and a capacitor 114. The circuit 120 includes a transistor 121 corresponding to a scanning line switching element, a circuit 12 2 and a capacitor element 124. The circuit 130 includes a transistor corresponding to a scanning line switching element. The semiconductor device includes a transistor 131, a circuit 132, and a capacitor 134. 141, wiring 142, and wiring 143 are connected to the signal IN, the signal CK1, the signal CK2, and the signal CK3, and the wiring 151, wiring 152, and wiring 153 propagate the signal OU. T1, signal OUT2 and signal OUT3 are carried, respectively.

[0163] Next, the connection relationships will be described.

[0164] The circuit 100 is connected to a wiring 140, a wiring 141, a wiring 142, and a wiring 143. The circuit 110 is connected to a wiring 140, a wiring 141, and a wiring 151. The circuit 20 is connected to the wiring 140, the wiring 142, and the wiring 152. The wiring 140 is connected to the wiring 143 and the wiring 153. 110, circuit 120, and circuit 130.

[0165] Next, the operation of the semiconductor device of FIG. 6A will be described with reference to the timing chart of FIG. 6B. This will be explained in light of the above.

[0166] The timing chart of FIG. 6B includes a period T1, a period T2, and a period T3. Signal IN is the input signal to circuit 100. Signals CK1, CK2, and CK3 are , and are input signals to the circuit 110, the circuit 120, and the circuit 130. UT2 and signal OUT3 are output signals from circuits 110, 120, and 130. is.

[0167] First, the operation of the semiconductor device in FIG. 6A in the period T1 will be described. indicates that signal IN is at H level, signal CK1 is at H level, signal CK2 is at L level, and signal CK3 is at This causes the transistor 111 included in the circuit 110 to turn on. The signal OUT1 becomes H level, the signal OUT2 becomes L level, and the signal OUT3 becomes L level.

[0168] Next, in a period T2, the signal IN is at the H level, the signal CK1 is at the L level, and the signal CK2 is at the H level. Then, the signal CK3 goes low. Then, the transistor 121 included in the circuit 120 is turned on, signal OUT1 is at L level, signal OUT2 is at H level, and signal OUT3 is It will be at L level.

[0169] Next, in a period T3, the signal IN is at the H level, the signal CK1 is at the L level, and the signal CK2 is at the L level. Then, the signal CK3 goes high. Then, the transistor 131 included in the circuit 130 is turned on, signal OUT1 is at L level, signal OUT2 is at L level, and signal OUT3 is at It becomes H level.

[0170] The signals OUT1 and OU output from the circuits 110, 120, and 130 are T2 and signal OUT3 are used as scanning line selection signals and are sent from the scanning line driving circuit to the corresponding scanning lines. are entered respectively.

[0171] As described above, the signal IN can be divided into a plurality of signals. , the capacitor 114, the capacitor 124, and the capacitors included in the circuit 120 and the circuit 130. Due to the capacitive coupling of the capacitor 134, the amplitudes of the signals OUT1, OUT2, and OUT3 are The amplitudes of the signals CK1, CK2, and CK3 are the same.

[0172] In addition, the gate voltages of the transistors 111, 121, and 131 are The potential of the pole is controlled by the bootstrap operation to the signals OUT1, OUT2, and O. It increases depending on the potential of UT3. That is, by increasing the Vgs of the transistor, or Since the output voltage can be kept large, the distortion of the signal OUT can be reduced. can shorten the rise time or fall time of the signal OUT.

[0173] In addition, there is no need to use a signal with a larger amplitude than the signal IN or a separate power supply voltage. This makes it possible to reduce power consumption.

[0174] (Fourth embodiment) In this embodiment, a specific example of the third embodiment will be described.

[0175] First, the structure of the semiconductor device of this embodiment mode will be described with reference to FIG.

[0176] The circuit 100 includes a circuit 110, a circuit 120, and a circuit 130. The circuit 110 includes a The transistor 111, the transistor 113, the transistor 115, and the capacitor element 114 are included. The circuit 120 includes a transistor 121, a transistor 123, a transistor 125, and a The circuit 130 includes a transistor 131, a transistor 133, and a capacitor 124. , a transistor 135, and a capacitor 134. In addition, a wiring 140, a wiring 141, The wiring 142, the wiring 143, and the wiring 240 are connected to the signal IN1, the signal CK1, the signal CK2, and the signal The signal CK3 and the signal IN2 are transmitted through the wiring 151, the wiring 152, and the wiring 153 propagates the signals OUT1, OUT2, and OUT3, respectively.

[0177] Next, the connection relationships will be described.

[0178] The circuit 100 includes a wiring 140, a wiring 141, a wiring 142, a wiring 143, and a wiring 240. The circuit 110 includes a wiring 140, a wiring 141, a wiring 240, and a wiring 151. The circuit 120 is connected to the wiring 140, the wiring 142, the wiring 240, and the wiring 15. The circuit 130 is connected to the wiring 140, the wiring 143, the wiring 240, and the wiring 141. 53. That is, the wiring 140 and the wiring 240 are connected to the circuit 110 and the circuit 12. 0 and the circuit 130.

[0179] The gate electrode of the transistor 111 included in the circuit 110 is connected to the source of the transistor 115. One of the source or drain electrodes of the transistor is connected to one of the electrodes of the capacitor 114. One of the source and drain electrodes of the transistor 111 is connected to the wiring 141. The other electrode of the source or drain of the capacitor 11 is connected to the wiring 151 and the other electrode of the capacitor 114. The gate electrode of the transistor 115 is connected to the wiring 140 and the transistor 115. The other electrode of the source or drain of the transistor 115 is connected to the One of the source and drain electrodes is connected to the gate electrode of the transistor 111 and the capacitor 1 The gate electrode of the transistor 113 is connected to one electrode of the wiring 240. The source or drain electrode of the transistor 113 is connected to the A gate electrode, one of a source electrode and a drain electrode of the transistor 115, and a capacitor 114 and the other of the source or drain of the transistor 113. The electrode is connected to a GND (ground) electrode.

[0180] The gate electrode of the transistor 121 included in the circuit 120 is connected to the source of the transistor 125. One of the source or drain electrodes of the transistor is connected to one of the electrodes of the capacitor 124. One of the source and drain electrodes of the transistor 121 is connected to the wiring 142. The other electrode of the source or drain of the capacitor 124 is connected to the wiring 152 and the other electrode of the capacitor 124. The gate electrode of the transistor 125 is connected to the wiring 140 and the transistor 125. The other electrode of the source or drain of the transistor 125 is connected to the One of the source and drain electrodes is connected to the gate electrode of the transistor 121 and the capacitor 1 The gate electrode of the transistor 123 is connected to one electrode of the wiring 240. The source or drain electrode of the transistor 123 is connected to the A gate electrode, one of the source and drain electrodes of the transistor 125, and a capacitor 124 and the other of the source or drain of the transistor 123. The electrode is connected to a GND (ground) electrode.

[0181] The gate electrode of the transistor 131 included in the circuit 130 is connected to the source of the transistor 135. One of the source or drain electrodes of the transistor is connected to one of the electrodes of the capacitor 134. One of the source and drain electrodes of the transistor 131 is connected to the wiring 143. The other electrode of the source or drain of the capacitor 134 is connected to the wiring 153 and the other electrode of the capacitor 134. The gate electrode of the transistor 135 is connected to the wiring 140 and the transistor 135. The other electrode of the source or drain of the transistor 135 is connected to the One of the source and drain electrodes is connected to the gate electrode of the transistor 131 and the capacitor 1 The gate electrode of the transistor 133 is connected to one electrode of the wiring 240. The source or drain electrode of the transistor 133 is connected to the A gate electrode, one of the source and drain electrodes of the transistor 135, and a capacitor 134 and the other of the source or drain of the transistor 133. The electrode is connected to a GND (ground) electrode.

[0182] Next, the operation of the semiconductor device of FIG. 7A will be described with reference to the timing chart of FIG. 7B. This will be explained in light of the above.

[0183] The timing chart of FIG. 7B includes periods T1, T2, T3, T4, and The signal IN1 is an input signal to the first stage circuit 100. The signal IN1 has a period T5 and a period T6. The signal IN2 is an input signal to the second stage circuit 100. The signals CK1, CK2, and The signal CK3 is a signal to the circuit 110, the circuit 120, and the circuit 130 included in the first stage circuit 100. The input signal is the circuit 110, the circuit 120, and the circuit The signals OUT1, OUT2, and OUT3 are input signals to the first stage. 1. The circuit 100 includes a circuit 110, a circuit 120, and a circuit 130. The signals OUT1, OUT2, and OUT3 are used as scanning line selection signals to are input to the corresponding scanning lines.

[0184] First, the operation of the semiconductor device in FIG. 7A during the period T1 will be described. indicates that signal IN1 is at H level, signal IN2 is at L level, signal CK1 is at H level, and signal CK2 is at L level. Then, the signal CK3 goes to the L level. 111 is turned on, signal OUT1 is at H level, signal OUT2 is at L level, and signal OU T3 becomes L level.

[0185] Next, during a period T2, the signal IN1 is at H level, the signal IN2 is at L level, and the signal CK1 is at L level. Then, the signal CK2 goes to H level and the signal CK3 goes to L level. The transistor 121 included in the signal OUT1 is turned on, the signal OUT2 is at the L level, and the signal OUT3 is at the At this time, the transistor included in the circuit 110 The transistor 111 remains on.

[0186] Next, during a period T3, the signal IN1 is at H level, the signal IN2 is at L level, and the signal CK1 is at L level. Then, the signal CK2 goes to the L level, and the signal CK3 goes to the H level. The transistor 131 included in the signal OUT1 is turned on, the signal OUT2 is at the L level, and the signal OUT3 is at the At this time, the transistor included in the circuit 110 The transistor 111 and the transistor 121 included in the circuit 120 are kept on.

[0187] That is, during the period T3, the transistors 111, 121, and 1 31 are all in the ON state. If this continues, the signals CK1 and CK When the signal CK3 and the signal CK2 become H level, the signals OUT1, OUT2 and OUT 3 may become H level, resulting in poor scan line selection.

[0188] Next, during a period T4, the signal IN1 is at the L level, the signal IN2 is at the H level, and the signal CK1 is at the H level. signal CK2 becomes L level, signal CK3 becomes L level. signal IN2 becomes H level. Then, the transistor 113 included in the circuit 110 and the transistor 120 included in the circuit 120 The transistor 123 and the transistor 133 included in the circuit 130 are turned on. The other electrode of the transistor's source or drain is connected to the GND electrode. The potential of either the source or drain electrode is also at the L level. a transistor 111 connected to one of the source and drain electrodes of the transistor The gate electrodes of the transistors 121 and 131 also become L level. As a result, even if the signal CK1 becomes H level during the period T4, the signal OUT 1 can maintain the L level.

[0189] In the periods T5 and T6, similarly to the period T4, when the signal IN2 is at the H level, In this case, the transistor 111, the transistor 121, and the transistor 131 are turned off. Therefore, even if the signals CK2 and CK3 become H level, the signals OUT2 and OUT3 remain The signal OUT3 can be maintained at the L level. As when the signal IN1 is input, the signal OU output from the second stage circuit 100 T4, signal OUT5, and signal OUT6 go to H level in sequence.

[0190] The transistors 111, 121, and 131 are turned off. In this case, the signals OUT1, OUT2, and OUT3 are connected to the signals CK1 and CK2. CK2 and signal CK3 become H level at the same time, and the scanning line selection It may become defective.

[0191] (Embodiment 5) In this embodiment, another specific example of the third embodiment will be described.

[0192] First, the configuration of the semiconductor device of this embodiment will be described with reference to FIG.

[0193] The circuit 100 includes a circuit 110, a circuit 120, and a circuit 130. The circuit 110 includes a Transistor 111, transistor 113, transistor 115, transistor 116, and , and a capacitor 114. The circuit 120 includes a transistor 121, a transistor 123, The circuit 130 includes a transistor 125, a transistor 126, and a capacitor 124. , transistor 131, transistor 133, transistor 135, transistor 136 and a capacitor 134. In addition, a wiring 140, a wiring 141, a wiring 142, and a wiring 14 3 and the wiring 240 transmits the signals IN1, CK1, CK2, CK3 and I N2, and the wiring 151, wiring 152, and wiring 153 are used to transmit the signal OUT 1, signal OUT2, and signal OUT3 are propagated, respectively.

[0194] Next, the connection relationships will be described.

[0195] The circuit 100 includes a wiring 140, a wiring 141, a wiring 142, a wiring 143, and a wiring 240. The circuit 110 includes a wiring 140, a wiring 141, a wiring 240, and a wiring 151. The circuit 120 is connected to the wiring 140, the wiring 142, the wiring 240, and the wiring 15. The circuit 130 is connected to the wiring 140, the wiring 143, the wiring 240, and the wiring 141. 53. That is, the wiring 140 and the wiring 240 are connected to the circuit 110 and the circuit 12. 0 and the circuit 130.

[0196] The gate electrode of the transistor 111 included in the circuit 110 is connected to the source of the transistor 115. One of the source or drain electrodes of the transistor is connected to one of the electrodes of the capacitor 114. One of the source and drain electrodes of the transistor 111 is connected to the wiring 141. The other electrode of the source or drain of the transistor 11 is connected to a wiring 151 and a One of the source and drain electrodes is connected to the other electrode of the capacitor 114 . The gate electrode of the transistor 115 is connected to the wiring 140 and the source or The other electrode of the drain is connected to one of the source and drain of the transistor 115. The electrode of the transistor 111 is connected to a gate electrode of the transistor 111 and one electrode of the capacitor 114. The gate electrode of the transistor 113 is connected to the wiring 240. One of the source and drain electrodes of the transistor 111 is connected to the gate electrode of the transistor 112 and the One of the source and drain electrodes of the capacitor 115 is connected to one of the electrodes of the capacitor 114. The other electrode of the source or drain of the transistor 113 is connected to GND (ground). The gate electrode of the transistor 116 is connected to the wiring 143. One of the source and drain electrodes of the transistor 116 is connected to the wiring 151 and the transistor The other electrode of the source or drain of the capacitor 111 and the other electrode of the capacitor 114 The other electrode of the source or drain of the transistor 116 is connected to GND (ground). The sensor is connected to a ground electrode.

[0197] The gate electrode of the transistor 121 included in the circuit 120 is connected to the source of the transistor 125. One of the source or drain electrodes of the transistor is connected to one of the electrodes of the capacitor 124. One of the source and drain electrodes of the transistor 121 is connected to the wiring 142. The other electrode of the source or drain of transistor 21 is connected to a wiring 152 and a One of the source and drain electrodes is connected to the other electrode of the capacitor 124 . The gate electrode of the transistor 125 is connected to the wiring 140 and the source or The other electrode of the drain is connected to one of the source and drain of the transistor 125. The electrode of the transistor 121 is connected to a gate electrode of the transistor 121 and one electrode of the capacitor 124. The gate electrode of the transistor 123 is connected to the wiring 240. One of the source and drain electrodes of the transistor 121 is connected to the gate electrode of the transistor 122 and the One of the source or drain electrodes of the capacitor 125 is connected to one of the electrodes of the capacitor 124. The other electrode of the source or drain of the transistor 123 is connected to GND (ground). The gate electrode of the transistor 126 is connected to the wiring 141. One of the source and drain electrodes of the transistor 126 is connected to the wiring 152 and the transistor The other electrode of the source or drain of the capacitor 121 is connected to one electrode of the capacitor 124. The other electrode of the source or drain of the transistor 126 is connected to GND (ground). The electrode is connected to the

[0198] The gate electrode of the transistor 131 included in the circuit 130 is connected to the source of the transistor 135. One of the source or drain electrodes of the transistor is connected to one of the electrodes of the capacitor 134. One of the source and drain electrodes of the transistor 131 is connected to the wiring 143. The other electrode of the source or drain of the transistor 31 is connected to a wiring 153 and a One of the source and drain electrodes is connected to the other electrode of the capacitor 134 . The gate electrode of the transistor 135 is connected to the wiring 140 and the source or The other electrode of the drain is connected to one of the source and drain of the transistor 135. The electrode of the transistor 131 is connected to a gate electrode of the transistor 131 and one electrode of the capacitor 134. The gate electrode of the transistor 133 is connected to the wiring 240. One of the source and drain electrodes of the transistor 131 is connected to the gate electrode of the transistor 132 and the One of the source or drain electrodes of the capacitor 135 is connected to one of the electrodes of the capacitor 134. The other electrode of the source or drain of the transistor 133 is connected to GND (ground). The gate electrode of the transistor 136 is connected to the wiring 142. One of the source and drain electrodes of the transistor 136 is connected to the wiring 153 and the transistor The other electrode of the source or drain of the capacitor 131 is connected to one electrode of the capacitor 134. The other electrode of the source or drain of the transistor 136 is connected to GND (ground). The electrode is connected to the

[0199] Next, the operation of the semiconductor device of FIG. 8 will be described with reference to the timing chart of FIG. explain.

[0200] The timing chart of FIG. 7B includes periods T1, T2, T3, T4, and The signal IN1 is an input signal to the first stage circuit 100. The signal IN1 has a period T5 and a period T6. The signal IN2 is an input signal to the second stage circuit 100. The signals CK1, CK2, and The signal CK3 is a signal to the circuit 110, the circuit 120, and the circuit 130 included in the first stage circuit 100. The input signal is the circuit 110, the circuit 120, and the circuit 111 included in the second-stage circuit 100. The signals OUT1, OUT2, and OUT3 are input signals to the first stage. The signals are output from the circuits 110, 120, and 130 included in the circuit 100. Signals OUT1, OUT2, and OUT3 are output from the scanning line driving circuit as scanning line selection signals. are input to the corresponding scanning lines.

[0201] First, the operation of the semiconductor device in FIG. 8 during the period T1 will be described. Signal IN1 is at H level, signal IN2 is at L level, signal CK1 is at H level, and signal CK2 is at L level. Then, the signal CK3 goes low. Then, the transistor 111 included in the circuit 110 is turned on, signal OUT1 is at H level, signal OUT2 is at L level, and signal OUT3 is At this time, the transistor 126 included in the circuit 120 is turned on. , the signal OUT2 becomes L level.

[0202] Next, during a period T2, the signal IN1 is at H level, the signal IN2 is at L level, and the signal CK1 is at L level. Then, the signal CK2 goes to H level and the signal CK3 goes to L level. The transistor 121 included in the signal OUT1 is turned on, the signal OUT2 is at the L level, and the signal OUT3 is at the At this time, the transistor included in the circuit 110 The transistor 111 remains on. The switch is turned on, and the signal OUT3 goes low.

[0203] Next, during a period T3, the signal IN1 is at H level, the signal IN2 is at L level, and the signal CK1 is at L level. Then, the signal CK2 goes to the L level, and the signal CK3 goes to the H level. The transistor 131 included in the signal OUT1 is turned on, the signal OUT2 is at the L level, and the signal OUT3 is at the At this time, the transistor included in the circuit 110 The transistor 111 and the transistor 121 included in the circuit 120 are kept on. In addition, the transistor 116 included in the circuit 110 is turned on, and the signal OUT1 is at the L level. It becomes a lu.

[0204] Next, during a period T4, the signal IN1 is at the L level, the signal IN2 is at the H level, and the signal CK1 is at the H level. signal CK2 becomes L level, signal CK3 becomes L level. signal IN2 becomes H level. Then, the transistor 113 included in the circuit 110 and the transistor 120 included in the circuit 120 The transistor 123 and the transistor 133 included in the circuit 130 are turned on. The other electrode of the transistor's source or drain is connected to the GND electrode. The potential of either the source or drain electrode is also at the L level. a transistor 111 connected to one of the source and drain electrodes of the transistor The gate electrodes of the transistors 121 and 131 also become L level. As a result, even if the signal CK1 becomes H level during the period T4, the signal OUT 1 can be maintained at the L level. Also, as in the period T1, the signal CK1 can be maintained at the H level. Therefore, the transistor 126 included in the circuit 120 is turned on, and the signal O UT2 becomes L level.

[0205] In the periods T5 and T6, similarly to the period T4, when the signal IN2 is at the H level, In this case, the transistor 111, the transistor 121, and the transistor 131 are turned off. Therefore, even if the signals CK2 and CK3 become H level, the signals OUT2 and OUT3 remain During the period T5, the signal OUT3 can be maintained at the L level. The transistor 136 included in the circuit 110 is turned on during the period T6. Since the transistor 116 is turned on, the signals OUT3 and OUT1 become L level.

[0206] Thus, the signals OUT1, OUT2, and OUT3 are included in the circuit 110. a transistor 116 included in the circuit 120, a transistor 126 included in the circuit 130, When the transistor 136 included in the It can be suppressed.

[0207] (Sixth embodiment) In this embodiment, another semiconductor device capable of dividing one signal into a plurality of signals is An example will be described. In this embodiment, the transistors of the signal IN and the signal CK in the third embodiment are The connection to the star has been swapped.

[0208] First, the configuration of the semiconductor device of this embodiment will be described with reference to FIG.

[0209] The circuit 100 includes a circuit 110, a circuit 120, and a circuit 130. The circuit 110 is a trans. The circuit 120 includes a transistor 111, a circuit 112, and a capacitor 114. The circuit 130 includes a transistor 131, a circuit 122, and a capacitor 124. , a circuit 132, and a capacitor 134. In addition, a wiring 140, a wiring 141, and a wiring 14 2 and the wiring 143 transmit the signal IN, the signal CK1, the signal CK2, and the signal CK3, respectively. The wiring 151, the wiring 152, and the wiring 153 are transmitting the signals OUT1 and OUT 2 and signal OUT3, respectively.

[0210] Next, the connection relationships will be described.

[0211] The circuit 100 is connected to a wiring 140, a wiring 141, a wiring 142, and a wiring 143. The circuit 110 is connected to a wiring 140, a wiring 141, and a wiring 151. The circuit 20 is connected to the wiring 140, the wiring 142, and the wiring 152. The wiring 140 is connected to the wiring 143 and the wiring 153. 110, circuit 120, and circuit 130.

[0212] Next, the operation of the semiconductor device of FIG. 9 will be described with reference to the timing chart of FIG. 6(B). explain.

[0213] The timing chart of FIG. 6B includes a period T1, a period T2, and a period T3. Signal IN is the input signal to circuit 100. Signals CK1, CK2, and CK3 are , and are input signals to the circuit 110, the circuit 120, and the circuit 130. UT2 and signal OUT3 are output signals from circuits 110, 120, and 130. is.

[0214] First, the operation of the semiconductor device in FIG. 9 during the period T1 will be described. Signal IN is H level, signal CK1 is H level, signal CK2 is L level, signal CK3 is L level Then, the transistor 111 included in the circuit 110 is turned on, and the signal O UT1 goes to H level, signal OUT2 goes to L level, and signal OUT3 goes to L level.

[0215] Next, in a period T2, the signal IN is at the H level, the signal CK1 is at the L level, and the signal CK2 is at the H level. Then, the signal CK3 goes low. Then, the transistor 121 included in the circuit 120 is turned on, signal OUT1 is at L level, signal OUT2 is at H level, and signal OUT3 is It will be at L level.

[0216] Next, in a period T3, the signal IN is at the H level, the signal CK1 is at the L level, and the signal CK2 is at the L level. Then, the signal CK3 goes high. Then, the transistor 131 included in the circuit 130 is turned on, signal OUT1 is at L level, signal OUT2 is at L level, and signal OUT3 is at It becomes H level.

[0217] The signals OUT1 and OU output from the circuits 110, 120, and 130 are T2 and signal OUT3 are used as scanning line selection signals and are sent from the scanning line driving circuit to the corresponding scanning lines. are entered respectively.

[0218] As described above, the signal IN can be divided into a plurality of signals. , the capacitor 114, the capacitor 124, and the capacitors included in the circuit 120 and the circuit 130. Due to the capacitive coupling of the capacitor 134, the amplitudes of the signals OUT1, OUT2, and OUT3 are The amplitudes of the signals CK1, CK2, and CK3 are the same.

[0219] In addition, the gate voltages of the transistors 111, 121, and 131 are The potential of the pole is controlled by the bootstrap operation to the signals OUT1, OUT2, and O. It increases depending on the potential of UT3. That is, by increasing the Vgs of the transistor, or Since the output voltage can be kept large, the distortion of the signal OUT can be reduced. can shorten the rise time or fall time of the signal OUT.

[0220] In addition, there is no need to use a signal with a larger amplitude than the signal IN or a separate power supply voltage. This makes it possible to reduce power consumption.

[0221] (Embodiment 7) In this embodiment, a specific example of the fourth embodiment will be described.

[0222] First, the configuration of the semiconductor device of this embodiment will be described with reference to FIG.

[0223] The circuit 100 includes a circuit 110, a circuit 120, and a circuit 130. The circuit 110 includes a The transistor 111, the transistor 113, the transistor 115, and the capacitor element 114 are included. The circuit 120 includes a transistor 121, a transistor 123, a transistor 125, and a The circuit 130 includes a transistor 131, a transistor 133, and a capacitor 124. , a transistor 135, and a capacitor 134. In addition, a wiring 140, a wiring 141, The wiring 142 and the wiring 143 transmit the signal IN, the signal CK1, the signal CK2, and the signal CK3. The wiring 151, wiring 152, and wiring 153 are respectively propagating the signal OUT1, the signal OUT2, and the signal OUT3. Signals OUT2 and OUT3 are propagated through the respective terminals.

[0224] Next, the connection relationships will be described.

[0225] The circuit 100 is connected to a wiring 140, a wiring 141, a wiring 142, and a wiring 143. The circuit 110 is connected to a wiring 140, a wiring 141, and a wiring 151. The circuit 20 is connected to the wiring 140, the wiring 142, and the wiring 152. The wiring 140 is connected to the wiring 143 and the wiring 153. 110, circuit 120, and circuit 130.

[0226] The gate electrode of the transistor 111 included in the circuit 110 is connected to the source of the transistor 115. One of the source or drain electrodes of the transistor is connected to one of the electrodes of the capacitor 114. One of the source and drain electrodes of the transistor 111 is connected to the wiring 140. The other electrode of the source or drain of the capacitor 11 is connected to the wiring 151 and the other electrode of the capacitor 114. The gate electrode of the transistor 115 is connected to the wiring 141 and the transistor 115. The other electrode of the source or drain of the transistor 115 is connected to the One of the source and drain electrodes is connected to the gate electrode of the transistor 111 and the capacitor 1 The gate electrode of the transistor 113 is connected to one electrode of the wiring 142. The source or drain electrode of the transistor 113 is connected to the A gate electrode, one of a source electrode and a drain electrode of the transistor 115, and a capacitor 114 and the other of the source or drain of the transistor 113. The electrode is connected to a GND (ground) electrode.

[0227] The gate electrode of the transistor 121 included in the circuit 120 is connected to the source of the transistor 125. One of the source or drain electrodes of the transistor is connected to one of the electrodes of the capacitor 124. One of the source and drain electrodes of the transistor 121 is connected to the wiring 140. The other electrode of the source or drain of the capacitor 124 is connected to the wiring 152 and the other electrode of the capacitor 124. The gate electrode of the transistor 125 is connected to the wiring 142 and the transistor 125. The other electrode of the source or drain of the transistor 125 is connected to the One of the source and drain electrodes is connected to the gate electrode of the transistor 121 and the capacitor 1 The gate electrode of the transistor 123 is connected to one electrode of the wiring 143. The source or drain electrode of the transistor 123 is connected to the A gate electrode, one of the source and drain electrodes of the transistor 125, and a capacitor 124 and the other of the source or drain of the transistor 123. The electrode is connected to a GND (ground) electrode.

[0228] The gate electrode of the transistor 131 included in the circuit 130 is connected to the source of the transistor 135. One of the source or drain electrodes of the transistor is connected to one of the electrodes of the capacitor 134. One of the source and drain electrodes of the transistor 131 is connected to the wiring 140. The other electrode of the source or drain of the capacitor 134 is connected to the wiring 153 and the other electrode of the capacitor 134. The gate electrode of the transistor 135 is connected to the wiring 143 and the transistor 135. The other electrode of the source or drain of the transistor 135 is connected to the One of the source and drain electrodes is connected to the gate electrode of the transistor 131 and the capacitor 1 The gate electrode of the transistor 133 is connected to one electrode of the wiring 141. The source or drain electrode of the transistor 133 is connected to the A gate electrode, one of the source and drain electrodes of the transistor 135, and a capacitor 134 and the other of the source or drain of the transistor 133. The electrode is connected to a GND (ground) electrode.

[0229] Next, the operation of the semiconductor device of FIG. 10 will be described with reference to the timing chart of FIG. 6(B). I will explain.

[0230] The timing chart in FIG. 6B includes a period T1, a period T2, and a period T3. IN is an input signal to the circuit 100. The signals CK1, CK2, and CK3 are These are input signals to the circuit 110, the circuit 120, and the circuit 130. T2 and signal OUT3 are output signals from circuits 110, 120, and 130. The signals OUT1, OUT2, and OUT3 are used as scanning line selection signals. The signals are input to the corresponding scanning lines from the drive circuit.

[0231] First, the operation of the semiconductor device in FIG. 10 during the period T1 will be described. Signal IN is H level, signal CK1 is H level, signal CK2 is L level, signal CK3 is L level. Then, the transistor 111 included in the circuit 110 is turned on, and the signal OUT1 is at H level, signal OUT2 is at L level, and signal OUT3 is at L level. At this time, the transistor 111 included in the circuit 110 is kept on.

[0232] Next, in a period T2, the signal IN is at the H level, the signal CK1 is at the L level, and the signal CK2 is at the H level. Then, the signal CK3 goes low. Then, the transistor 121 included in the circuit 120 is turned on, signal OUT1 is at L level, signal OUT2 is at H level, and signal OUT3 is At this time, the transistor 113 included in the circuit 110 is turned on. The other electrode of the source or drain of the transistor 113 is connected to the GND electrode. Therefore, the potential of either the source or drain electrode is also at the L level. The gate of transistor 111 is connected to one of the source and drain electrodes of transistor 113. The gate electrode also becomes L level, and the transistor 111 is turned off. Even if the signal IN is at H level, the signal OUT1 can remain at L level. In addition, the transistor 121 included in the circuit 120 remains on.

[0233] Next, in a period T3, the signal IN is at the H level, the signal CK1 is at the L level, and the signal CK2 is at the L level. Then, the signal CK3 goes high. Then, the transistor 131 included in the circuit 130 is turned on, signal OUT1 is at L level, signal OUT2 is at L level, and signal OUT3 is at At this time, the transistor 123 included in the circuit 120 is turned on. The other electrode of the source or drain of the transistor 123 is connected to the GND electrode. Therefore, the potential of either the source or drain electrode is also at the L level. The gate of transistor 121 is connected to one of the source and drain electrodes of transistor 123. The gate electrode also becomes L level, and the transistor 121 is turned off. Even if the signal IN is at H level, the signal OUT2 can remain at L level. In addition, the transistor 131 included in the circuit 130 remains on.

[0234] Similarly, when the next period begins, the transistor 131 is turned off using the signal CK1. state, and the signal OUT3 can be maintained at the L level.

[0235] The transistors 111, 121, and 131 are turned off. When the signal IN is not configured as an H level, the signals OUT1, OUT2, and OUT3 are This may cause the signal to go to H level during the period when the signal is in the low level, resulting in poor scan line selection.

[0236] (Embodiment 8) In this embodiment, another specific example of the fourth embodiment will be described.

[0237] First, the configuration of the semiconductor device of this embodiment will be described with reference to FIG.

[0238] The circuit 100 includes a circuit 110, a circuit 120, and a circuit 130. The circuit 110 includes a Transistor 111, transistor 113, transistor 115, transistor 116, and , and a capacitor 114. The circuit 120 includes a transistor 121, a transistor 123, The circuit 130 includes a transistor 125, a transistor 126, and a capacitor 124. , transistor 131, transistor 133, transistor 135, transistor 136 and a capacitor 134. In addition, a wiring 140, a wiring 141, a wiring 142, and a wiring 143 propagates the signal IN, the signal CK1, the signal CK2, and the signal CK3, respectively. , the wiring 151, the wiring 152, and the wiring 153 are connected to the signals OUT1, OUT2, and OUT3 are propagated respectively.

[0239] Next, the connection relationships will be described.

[0240] The circuit 100 is connected to a wiring 140, a wiring 141, a wiring 142, and a wiring 143. The circuit 110 is connected to a wiring 140, a wiring 141, and a wiring 151. The circuit 20 is connected to the wiring 140, the wiring 142, and the wiring 152. The wiring 140 is connected to the wiring 143 and the wiring 153. 110, circuit 120, and circuit 130.

[0241] The gate electrode of the transistor 111 included in the circuit 110 is connected to the source of the transistor 115. One of the source or drain electrodes of the transistor is connected to one of the electrodes of the capacitor 114. One of the source and drain electrodes of the transistor 111 is connected to the wiring 140. The other electrode of the source or drain of the transistor 11 is connected to a wiring 151 and a One of the source and drain electrodes is connected to the other electrode of the capacitor 114 . The gate electrode of the transistor 115 is connected to the wiring 141 and the source or The other electrode of the drain is connected to one of the source and drain of the transistor 115. The electrode of the transistor 111 is connected to a gate electrode of the transistor 111 and one electrode of the capacitor 114. The gate electrode of the transistor 113 is connected to the wiring 142. One of the source and drain electrodes of the transistor 111 is connected to the gate electrode of the transistor 112 and the One of the source and drain electrodes of the capacitor 115 is connected to one of the electrodes of the capacitor 114. The other electrode of the source or drain of the transistor 113 is connected to GND (ground). The gate electrode of the transistor 116 is connected to the wiring 143. One of the source and drain electrodes of the transistor 116 is connected to the wiring 151 and the transistor The other electrode of the source or drain of the capacitor 111 and the other electrode of the capacitor 114 The other electrode of the source or drain of the transistor 116 is connected to GND (ground). The sensor is connected to a ground electrode.

[0242] The gate electrode of the transistor 121 included in the circuit 120 is connected to the source of the transistor 125. One of the source or drain electrodes of the transistor is connected to one of the electrodes of the capacitor 124. One of the source and drain electrodes of the transistor 121 is connected to the wiring 140. The other electrode of the source or drain of transistor 21 is connected to a wiring 152 and a One of the source and drain electrodes is connected to the other electrode of the capacitor 124 . The gate electrode of the transistor 125 is connected to the wiring 142 and the source or The other electrode of the drain is connected to one of the source and drain of the transistor 125. The electrode of the transistor 121 is connected to a gate electrode of the transistor 121 and one electrode of the capacitor 124. The gate electrode of the transistor 123 is connected to the wiring 143. One of the source and drain electrodes of the transistor 121 is connected to the gate electrode of the transistor 122 and the One of the source or drain electrodes of the capacitor 125 is connected to one of the electrodes of the capacitor 124. The other electrode of the source or drain of the transistor 123 is connected to GND (ground). The gate electrode of the transistor 126 is connected to the wiring 141. One of the source and drain electrodes of the transistor 126 is connected to the wiring 152 and the transistor The other electrode of the source or drain of the capacitor 121 and the other electrode of the capacitor 124 The other electrode of the source or drain of the transistor 126 is connected to GND (ground). The sensor is connected to a ground electrode.

[0243] The gate electrode of the transistor 131 included in the circuit 130 is connected to the source of the transistor 135. One of the source or drain electrodes of the transistor is connected to one of the electrodes of the capacitor 134. One of the source and drain electrodes of the transistor 131 is connected to the wiring 140. The other electrode of the source or drain of the transistor 31 is connected to a wiring 153 and a One of the source and drain electrodes is connected to the other electrode of the capacitor 134 . The gate electrode of the transistor 135 is connected to the wiring 143 and the source or The other electrode of the drain is connected to one of the source and drain of the transistor 135. The electrode of the transistor 131 is connected to a gate electrode of the transistor 131 and one electrode of the capacitor 134. The gate electrode of the transistor 133 is connected to the wiring 141. One of the source and drain electrodes of the transistor 131 is connected to the gate electrode of the transistor 132 and the One of the source or drain electrodes of the capacitor 135 is connected to one of the electrodes of the capacitor 134. The other electrode of the source or drain of the transistor 133 is connected to GND (ground). The gate electrode of the transistor 136 is connected to the wiring 142. One of the source and drain electrodes of the transistor 136 is connected to the wiring 153 and the transistor The other electrode of the source or drain of the capacitor 131 and the other electrode of the capacitor 134 The other electrode of the source or drain of the transistor 136 is connected to GND (ground). The sensor is connected to a ground electrode.

[0244] Next, the operation of the semiconductor device of FIG. 11 will be described with reference to the timing chart of FIG. 6(B). I will explain.

[0245] The timing chart of FIG. 6B includes a period T1, a period T2, and a period T3. Signal IN is the input signal to circuit 100. Signals CK1, CK2, and CK3 are , and are input signals to the circuit 110, the circuit 120, and the circuit 130. UT2 and signal OUT3 are output signals from circuits 110, 120, and 130. is.

[0246] First, the operation of the semiconductor device in FIG. 11 during the period T1 will be described. Signal IN is H level, signal CK1 is H level, signal CK2 is L level, signal CK3 is L level. Then, the transistor 111 included in the circuit 110 is turned on, and the signal OUT1 is at H level, signal OUT2 is at L level, and signal OUT3 is at L level. When this occurs, the transistor 126 included in the circuit 120 is turned on, and the signal OUT2 is at the L level. It becomes a lu.

[0247] Next, in a period T2, the signal IN is at the H level, the signal CK1 is at the L level, and the signal CK2 is at the H level. Then, the signal CK3 goes low. Then, the transistor 121 included in the circuit 120 is turned on, signal OUT1 is at L level, signal OUT2 is at H level, and signal OUT3 is At this time, the transistor 113 included in the circuit 110 is turned on. The other electrode of the source or drain of the transistor 113 is connected to the GND electrode. Therefore, the potential of either the source or drain electrode is also at the L level. The gate of transistor 111 is connected to one of the source and drain electrodes of transistor 113. The gate electrode also becomes L level, and the transistor 111 is turned off. Even if the signal IN is at H level, the signal OUT1 can remain at L level. Also, the transistor 136 included in the circuit 130 is turned on, and the signal OUT3 is set to L. It becomes a level.

[0248] Next, in a period T3, the signal IN is at the H level, the signal CK1 is at the L level, and the signal CK2 is at the L level. Then, the signal CK3 goes high. Then, the transistor 131 included in the circuit 130 is turned on, signal OUT1 is at L level, signal OUT2 is at L level, and signal OUT3 is at At this time, the transistor 123 included in the circuit 120 is turned on. The other electrode of the source or drain of the transistor 123 is connected to the GND electrode. Therefore, the potential of either the source or drain electrode is also at the L level. The gate of transistor 121 is connected to one of the source and drain electrodes of transistor 123. The gate electrode also becomes L level, and the transistor 121 is turned off. Even if the signal IN is at H level, the signal OUT2 can remain at L level. Also, the transistor 116 included in the circuit 110 is turned on, and the signal OUT1 is set to L. It becomes a level.

[0249] Similarly, when the next period begins, the transistor 131 is turned off using the signal CK1. state, and the signal OUT3 can be maintained at the L level.

[0250] Thus, the signals OUT1, OUT2, and OUT3 are included in the circuit 110. a transistor 116 included in the circuit 120, a transistor 126 included in the circuit 130, When the transistor 136 included in the It can be suppressed.

[0251] (Embodiment 9) In this embodiment, a driver circuit including a structure according to one embodiment of the present invention will be described.

[0252] First, regarding the configuration of the semiconductor device of this embodiment, the circuit 100 shown in FIG. 6 will be taken as an example. , will be described with reference to FIG.

[0253] The shift register 2000 sequentially outputs a plurality of signals. 0 is a circuit according to one embodiment of the present invention, in which one signal is divided into three signals and output. The wiring 140 outputs the output signals from the shift register 2000 in one signal. The n-th set of wirings 151 to 153 is transmitted to the n-th stage circuit 100. These signals propagate through UT1 to OUT3.

[0254] Next, the connection relationships will be described.

[0255] The shift register 2000 is connected to the wiring 140. , and are connected to wiring 151, wiring 152, and wiring 153.

[0256] Next, the operation of the semiconductor device of FIG. 12 will be explained with reference to the timing chart of FIG. Reveal.

[0257] The timing chart in Fig. 13 shows one frame period of the driving circuit. The signal ut1 is an input signal to the first stage circuit 100. The signal SRout2 is an input signal to the second stage circuit 100. 00. The signal SRoutN is an input signal to the n-th stage circuit 100. The pulses of these signals SRout1 to SRoutN appear during the subframe. The signals CK1, CK2, and CK3 represent the first to nth stages. These are the input signals to the circuit 100. The pulses of these signals CK1 to CK3 appear The period indicates a scanning line selection period. The signals OUT1 to OUT3n are from the first stage to the nth stage. This is the output signal from the circuit 100 in the second stage.

[0258] Only when the sequentially input signals SRout and CK both become H level, the signal O UT becomes H level. In other words, in one frame period, signals SRout1 to SRoutN When the signal OUT1 is input, signals OUT1 to OUT3n are output. In this period, scanning lines 1 to 3n can be controlled. Similarly, the signal SRout and the signal CK are input and the signal OUT is output. The image is processed and displayed at 60 frames per second.

[0259] In this embodiment, the circuit 100 shown in FIG. 6 is taken as an example, and the following in the scanning line driving circuit is described. Although the circuit configuration provided on the output side of the shift register has been described, one embodiment of the present invention The semiconductor device according to the present invention may use a circuit 100 shown in FIGS.

[0260] (Embodiment 10) In this embodiment, an example of a cross-sectional structure of a display device will be described.

[0261] 14A is an example of a top view of a display device. The driver circuit portion 5392 is formed with a scanning line driver. circuits, signal line driver circuits, and the like.

[0262] FIG. 14(B) shows an example of a cross section of the driving circuit portion 5392 (cross section AB in FIG. 14(A)). FIG. 14B shows, as an example, a substrate 5401, a conductive layer 5402a, a conductive layer 5402b, and a conductive layer 540c. 2b, insulating layer 5403, conductive layer 5404a, conductive layer 5404b, semiconductor layer 5405, insulating a layer 5406, a conductive layer 5407, a liquid crystal layer 5408, an insulating layer 5409, a conductive layer 5410, and A substrate 5411 is shown. The conductive layer 5402a is formed on the substrate 5401, for example. For example, the conductive layer 5402b is formed on the conductive layer 5402a. 3 is formed on a substrate 5401, a conductive layer 5402a, and a conductive layer 5402b, for example. For example, the conductive layer 5404a is formed on the insulating layer 5403. For example, the conductive layer 5404b is formed on the conductive layer 5404a. For example, the insulating layer 5406 is formed on the insulating layer 5403. 03, is formed over the conductive layer 5404a, the conductive layer 5404b, and the semiconductor layer 5405. For example, the conductive layer 5407 is formed in the opening of the insulating layer 5406 and over the insulating layer 5406. The liquid crystal layer 5408 is formed on the insulating layer 5406, for example. For example, the conductive layer 409 is formed on the insulating layer 5406 and the conductive layer 5407. For example, the substrate 5410 is formed on the liquid crystal layer 5408 and the insulating layer 5409. 5411 is located on the conductive layer 5410, for example.

[0263] FIG. 14C shows an example of a cross-sectional view of the pixel portion 5393 (cross-section along CD in FIG. 14A). FIG. 14C shows, for example, a substrate 5401, a conductive layer 5402a, an insulating layer 5403, Conductive layer 5404a, semiconductor layer 5405, insulating layer 5406, conductive layer 5407, liquid crystal layer 540 8, a conductive layer 5410, and a substrate 5411. The conductive layer 5402a is, for example, a conductive layer The insulating layer 5403 is formed on the substrate 5401. For example, the insulating layer 5403 is formed on the substrate 5401 and the conductive layer 54 The conductive layer 5404a is formed on the insulating layer 5403, for example. For example, the semiconductor layer 5405 is formed over the insulating layer 5403. 5406 is, for example, a semiconductor layer 5405 on the insulating layer 5403, the conductive layer 5404a, and the semiconductor layer 5405. For example, the conductive layer 5407 is formed in the opening of the insulating layer 5406 and the insulating layer 5407. The liquid crystal layer 5408 is formed on the insulating layer 5406 and the conductive layer 5408. The conductive layer 5410 is formed on the liquid crystal layer 5408, for example. The substrate 5411 is, for example, located on the conductive layer 5410.

[0264] The conductive layer 5402a and the conductive layer 5402b are, for example, gate electrodes or gate wirings. The insulating layer 5403 can function as a gate insulating film, for example. The conductive layer 5404a and the conductive layer 5404b can have both functions. The insulating film can function as a wiring, an electrode of a transistor, an electrode of a capacitor, or the like. The insulating layer 5406 functions as an interlayer film or a planarization film, for example. The conductive layer 5407 can be, for example, a wiring, a pixel electrode, a light-transmitting electrode, or a The insulating layer 5409 can function as a reflective electrode. The conductive layer 5410 can function as, for example, a counter electrode, a common electrode, or the like. It can function as a conducting electrode or a reflecting electrode.

[0265] Here, the conductive layer 5402a and the conductive layer 5404a are formed using a light-transmitting material, for example. The conductive layer 5402b and the conductive layer 5404 can be formed using the conductive layer 5402b. For example, b is a material that is more conductive than the material used for the conductive layer 5402a or the conductive layer 5404a. For example, the conductive layer 5402b and the conductive layer 5402c can be formed using a material with high conductivity. The electrical layer 5404b can be formed using a material that has a light-blocking property. In the driver circuit portion 5392, the resistance of the wiring can be reduced. Improve power consumption, increase drive frequency, or reduce drive voltage. On the other hand, in the pixel portion 5393, wiring, an electrode of a transistor, and / or The electrodes of the storage capacitor can be made translucent. This allows the size of the aperture to be increased, which reduces power consumption and improves the resolution of the pixel area. However, the present embodiment is not limited to this. For example, the conductive layer 5402a and the conductive layer 5404a are formed using a light-blocking material. As another example, in the pixel portion 5393, the gate wiring is As with the wiring of the portion 5392, a laminated structure of a conductive layer 5402a and a conductive layer 5402b is formed. Alternatively, the source wiring can be formed by, for example, forming a conductive layer 5404a and a conductive layer 540b. In this way, the signal (e.g., video) input to the pixel can be The delay or distortion of the video signal or the scanning line selection signal can be reduced. For example, either one of the conductive layer 5402a and the conductive layer 5402b and the conductive layer 5404a and the conductive layer 5404b may be used. Either one or both of the conductive layers 5404b and 5404c may be omitted. As another example, the transistor portion of the driver circuit portion 5392 and the transistor portion of the pixel portion 5393 In either or both of the transistor portions, the gate electrode is connected to the conductive layer 5402a. As another example, a stacked structure with the conductive layer 5402b can be used. can be formed under conductive layer 5402a. 4b can be formed under the conductive layer 5404a. 5405 is formed on the insulating layer 5403, and the conductive layer 5402a is formed on the insulating layer 5403 and It can be formed on the semiconductor layer 5405 .

[0266] For example, an oxide semiconductor can be used for the semiconductor layer. For example, a conductor often has a light-transmitting property. By combining these, the aperture ratio of the pixel can be improved. For example, the semiconductor layer may be a single crystal semiconductor, a polycrystalline semiconductor, or the like. Conductors, microcrystalline (microcrystalline or nanocrystalline) semiconductors, amorphous For example, a single-crystal semiconductor or various non-single-crystal semiconductors can be used.

[0267] As an example of the display element, a light-emitting element (such as an EL element) can be used. FIG. 15A shows an example of a display using a light-emitting element as a display element. 14(B) shows an example of a cross-sectional view of a driver circuit portion 5392 of a display device. An insulating layer 5412 is formed on the edge layer 5406 and the conductive layer 5407. 412, an insulating layer 5409 and a filler material 5414 are formed thereon. 5(B) shows, as an example, a pixel portion 5 of a display device in the case where a light-emitting element is used as a display element. 14(C) shows an example of a cross-sectional view of the insulating layer 5406 and the conductive layer 393. An insulating layer 5412 is formed on the layer 5407, and an insulating layer 5412 is formed on the opening The light-emitting layer 5413 is formed, and a conductive layer is formed on the insulating layer 5412 and the light-emitting layer 5413. 5410 is formed, and a filler material 5414 is formed on the conductive layer 5410. For example, the insulating layer 5412 can function as a partition wall. However, the example of this embodiment is not limited to this.

[0268] As an example of the display element, there is an element that displays by moving particles (e.g., For example, electrophoretic elements, particle migration elements, or electronic liquid powders can be used. In this way, electronic paper can be manufactured. 5 shows an example of a cross-sectional view of a drive circuit portion 5392 of a display device when an electrophoretic element is used as a pixel. In a part of the driving circuit section 5392, the electrophoretic element is formed by an insulating layer 5406 and a conductive layer 5407. 10. An insulating layer 5409 is formed to cover the electrophoretic element. FIG. 16B shows an example of a display device using an electrophoretic element as a display element. An example of a cross-sectional view of a pixel portion 5393 of the device is shown. The electrophoretic element is disposed between the capsule 5415 and the electrophoretic element 5410. It is composed of a liquid 5416, particles 5417, and particles 5418. The particles 5417 and 5418 are, for example, in a capsule 5415. For example, the liquid 5416 is often insulating. One of the particles 5417 and 5418 is positively charged, and the other is negatively charged. One of the particles 5417 and 5418 is white, and the other is black. However, the present embodiment is not limited to this example. For example, particles The particles 5417 and 5418 are not limited to white or black, but may be different colors (e.g., red, green) from each other. , blue, magenta, yellow, cyan, etc.).

[0269] The display device of this embodiment improves the performance of the driver circuit and also improves the aperture ratio of the pixel. By using the configurations shown in the third to ninth embodiments for this driver circuit, This will further reduce power consumption, improve driving frequency, and improve pixel resolution. can be done.

[0270] (Embodiment 11) In this embodiment, an example of an electronic device will be described.

[0271] 17(A) to 17(H) and 18(A) to 18(D) are diagrams showing electronic devices. These electronic devices are made up of a housing 5000, a display unit 5001, a speaker 5003, an LED light pump 5004, operation keys 5005 (including a power switch or an operation switch), connection terminal 5006, Sensor 5007 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light , liquid, magnetic, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow (including functions to measure volume, humidity, gradient, vibration, odor or infrared), microphone 5008, etc.

[0272] FIG. 17(A) shows a mobile computer, which includes, in addition to the above, a switch 5009 , an infrared port 5010, etc. FIG. 17(B) shows a portable terminal equipped with a recording medium. A portable image reproducing device (for example, a DVD reproducing device) is also included. The display unit 5002, the recording medium reading unit 5011, etc. It is a group-type display, and in addition to the above, it has a second display unit 5002, a support unit 5012 , earphones 5013, etc. FIG. 17(D) shows a portable gaming machine. In addition to the above, it may have a recording medium reading unit 5011, etc. It is a projector, and in addition to the above, has a light source 5033, a projection lens 5034, etc. FIG. 17(F) shows a portable gaming machine, which, in addition to the above, has a second display. 17G shows a TV. It is a TV receiver, and in addition to the components described above, may also have a tuner, an image processor, and the like. FIG. 17(H) shows a portable television receiver, which, in addition to the above, is capable of transmitting and receiving signals. 18A is a display, and the upper part In addition to the above, a support base 5018 and the like may be provided. In addition to the above, there is an external connection port 5019, a shutter button 5015, an image receiving 18C shows a computer, which may have the above-mentioned In addition to the above, there is a pointing device 5020, an external connection port 5019, a reader / writer 5021, etc. FIG. 18(D) shows a mobile phone, Other items include antennas and One-Seg (one-segment partial reception service for mobile phones and mobile terminals) It may also have a tuner for the radio wave receiving device.

[0273] The electronic devices shown in FIGS. 17(A) to 17(H) and 18(A) to 18(D) are used in various For example, various information (still images, videos, text images, etc.) can be displayed. Functions that display information on the display unit, touch panel function, calendar, date or time display function, etc. function, the function to control processing by various software (programs), wireless communication function, The ability to connect to various computer networks using wired communication functions, and the ability to connect to various computer networks using wireless communication functions the function of transmitting or receiving various data, the program recorded on the recording medium, or It can have a function to read out data and display it on the display unit. In electronic devices with displays, one display is used primarily to display image information, and another The function of displaying text information mainly on one display unit, or displaying images that take parallax into account on multiple displays By displaying a stereoscopic image, the device can have the function of displaying a stereoscopic image. In electronic devices with an image unit, there are functions for taking still images, taking videos, and The function to automatically or manually correct the captured image, and to store the captured image on a recording medium (external or internal to the camera). The image capturing device may have functions such as storing the captured image in a memory (storage), displaying the captured image on a display unit, etc. The electronic devices shown in FIGS. 17(A) to 17(H) and 18(A) to 18(D) have The functions that can be implemented are not limited to these, and various other functions can be implemented.

[0274] The electronic device described in this embodiment has a display unit for displaying some information. The electronic device of this embodiment and the semiconductor of any one of the first to fourth embodiments are characterized in that: By combining it with a device, a shift register, or a display device, reliability and walking This allows for improved accuracy, cost reduction, larger display area, and higher resolution display area. do.

[0275] Next, application examples of the semiconductor device will be described.

[0276] FIG. 18(E) shows an example in which a semiconductor device is integrated with a building. E) is a housing 5022, a display unit 5023, a remote control device 5024 as an operation unit, a speaker 5025, etc. The semiconductor device is a wall-mounted type that is integrated with the building and is installed in a It can be installed without requiring a large space.

[0277] FIG. 18(F) shows another example in which a semiconductor device is provided inside a building as an integral part of the building. The display panel 5026 is attached to the unit bath 5027. The viewer can then view the display panel 5026.

[0278] In this embodiment, a wall and a unit bath are used as examples of buildings. The configuration is not limited to this, and the semiconductor device can be installed in various structures.

[0279] Next, an example in which the semiconductor device is integrated with a moving object will be described.

[0280] FIG. 18G is a diagram showing an example in which the semiconductor device is provided in an automobile. The cable 5028 is attached to the body 5029 of the automobile and is connected to the body of the automobile or the inside or outside of the automobile. The information entered from the navigation function can be displayed on demand. It may have.

[0281] FIG. 18(H) is a diagram showing an example in which a semiconductor device is integrated with a passenger airplane. FIG. 18(H) shows a display panel 5031 mounted on a ceiling 5030 above the seats of a passenger airplane. The display panel 5031 is attached to the ceiling 5. 030 and the hinge part 5032 are attached together. This allows passengers to view the display panel 5031. The display panel 5031 is operated by passengers. It has the function of displaying information by

[0282] In this embodiment, an automobile body and an airplane body are exemplified as moving bodies. However, this is not limited to motorcycles, four-wheeled vehicles (including cars, buses, etc.), trains (mono It can be installed on a variety of things, including rails, railways, ships, etc. [Explanation of symbols]

[0283] 100 circuits 110 circuits 111 Transistor 112 circuits 113 Transistor 114 Capacitor element 115 transistors 116 transistors 120 circuits 121 Transistor 122 circuits 123 Transistor 124 Capacitor element 125 transistors 126 transistors 130 circuits 131 Transistor 132 circuits 133 Transistor 134 Capacitor element 135 transistors 136 transistors 140 Wiring 141 Wiring 142 Wiring 143 Wiring 151 Wiring 152 Wiring 153 Wiring 240 Wiring 1400 board 1401 gate electrode layer 1402a Gate insulating layer 1402b Gate insulating layer 1403 Oxide semiconductor layer 1405a Source electrode layer 1405b Drain electrode layer 1406 Conductive layer 1407 Oxide insulating layer 1408 Protective insulation layer 1409 Planarizing insulating layer 1431 First high-resistivity drain region 1432 Second high-resistivity drain region 1433 Oxide semiconductor layer 1434 Channel formation region 1435 Metal electrode layer 1436 Resist mask 1437 Resist mask 1451 gate electrode layer 1453 Oxide semiconductor layer 1454 Oxide semiconductor layer 1455a Source electrode layer 1455b Drain electrode layer 1456 Pixel electrode layer 1460 Thin Film Transistor 1470 Thin-Film Transistor 1500 capacitive wiring layer 1501 Capacitive electrode layer 1502 Capacitor element 1503 Capacitive wiring layer 1504 Capacitive electrode layer 1505 Capacitive element 2000 shift registers 2400 board 2402a Gate insulating layer 2402b Gate insulating layer 2405b Drain electrode layer 2403 Protective insulation layer 2404 Planarizing insulating layer 2410 Thin Film Transistor 2411 Gate electrode layer 2412 Oxide semiconductor layer 2413 Channel formation region 2414a First high-resistivity drain region 2414b Second high-resistivity drain region 2415a Source electrode layer 2415b Drain electrode layer 2416 Oxide insulating layer 2417 Conductive layer 2420 Thin Film Transistor 2421 Gate electrode layer 2422 Oxide semiconductor layer 2425a Source electrode layer 2425b Drain electrode layer 2426 Oxide insulating layer 2427 Pixel electrode layer 2430 Oxide semiconductor film 2431 Oxide semiconductor layer 2432 Oxide semiconductor layer 2433a Resist mask 2434 Metal electrode layer 2435 Metal electrode layer 2436a Resist mask 2437 Oxide semiconductor layer 2438 Resist mask 2439 Oxide insulating layer 2440a resist mask 2441 Contact Hole 5000 cabinets 5001 Display section 5002 Display section 5003 Speaker 5004 LED lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Support stand 5019 External connection port 5020 pointing device 5021 Reader / Writer 5022 Housing 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display Panel 5027 Unit bath 5028 Display Panel 5029 Car Body 5030 Ceiling 5031 Display Panel 5032 Hinge part 5033 Light source 5034 Projection lens 5391 Circuit Board 5392 Drive circuit section 5393 Pixel section 5401 Circuit Board 5403 Insulation layer 5405 Semiconductor layer 5406 Insulation layer 5407 Conductive layer 5408 Liquid crystal layer 5409 Insulation layer 5410 Conductive layer 5411 Circuit Board 5412 Insulation layer 5413 Light-emitting layer 5414 Filling material 5415 capsules 5416 Liquid 5417 particles 5418 particles 5402a Conductive layer 5402b Conductive layer 5404a conductive layer 5404b conductive layer

Claims

1. It has a circuit of the kth order (where k is an integer greater than or equal to 1), a circuit of the k+1th order, and a circuit of the k+2nd order. The circuit k comprises a first transistor, a second transistor, and a first capacitive element. The circuit k+1 comprises a third transistor, a fourth transistor, and a second capacitive element. The circuit k+2 comprises a fifth transistor, a sixth transistor, and a third capacitive element. Either the source or the drain of the first transistor is always in contact with the first clock signal line. The source or drain of the first transistor, the other of which is always in contact with the first output signal line, Either the source or the drain of the second transistor is always in contact with the gate of the first transistor. The source or drain of the second transistor, the other of which is always in contact with the first signal line, The first terminal of the first capacitive element is always in electrical contact with the gate of the first transistor. The second terminal of the first capacitive element is always in electrical contact with the first output signal line. Either the source or the drain of the third transistor is always in contact with the second clock signal line. The source or drain of the third transistor, the other of which is always in contact with the second output signal line, Either the source or drain of the fourth transistor is always in contact with the gate of the third transistor. The source or drain of the fourth transistor, the other of which is always in conductivity with the first signal line, The first terminal of the second capacitive element is always in electrical contact with the gate of the third transistor. The second terminal of the second capacitive element is always in conductivity with the second output signal line. Either the source or the drain of the fifth transistor is always in contact with the third clock signal line. The source or drain of the fifth transistor, the other of which is always in contact with the third output signal line, Either the source or drain of the sixth transistor is always in contact with the gate of the fifth transistor. The source or drain of the sixth transistor, the other of which is always in conductivity with the first signal line, The first terminal of the third capacitive element is always in electrical contact with the gate of the fifth transistor. The second terminal of the third capacitive element is always in conductivity with the third output signal line. When the first signal line is in a conductive state with the gate of the first transistor, at least through the channel formation region of the second transistor, the gate of the second transistor is supplied with a potential that turns on the second transistor for a period of time. When the first signal line is in conduction with the gate of the third transistor, at least through the channel formation region of the fourth transistor, the gate of the fourth transistor is supplied with a potential that turns on the fourth transistor for a period of time. When the first signal line is in conduction with the gate of the fifth transistor, at least through the channel forming region of the sixth transistor, the gate of the sixth transistor is supplied with a potential that turns on the sixth transistor for a period of time. The signal from the first output signal line is not input to the k+1 circuit. The signal from the first output signal line is not input to the k+2 circuit. The signal from the second output signal line is not input to the circuit k. The signal from the second output signal line is not input to the k+2 circuit. The signal from the third output signal line is not input to the circuit k. The signal of the third output signal line is a semiconductor device that is not input to the k+1 circuit.

2. It has a circuit of the kth order (where k is an integer greater than or equal to 1), a circuit of the k+1th order, and a circuit of the k+2nd order. The circuit k comprises a first transistor, a second transistor, and a first capacitive element. The circuit k+1 comprises a third transistor, a fourth transistor, and a second capacitive element. The circuit k+2 comprises a fifth transistor, a sixth transistor, and a third capacitive element. Either the source or the drain of the first transistor is always in contact with the first clock signal line. The source or drain of the first transistor, the other of which is always in contact with the first output signal line, Either the source or the drain of the second transistor is always in contact with the gate of the first transistor. The source or drain of the second transistor, the other of which is always in contact with the first signal line, The first terminal of the first capacitive element is always in electrical contact with the gate of the first transistor. The second terminal of the first capacitive element is always in electrical contact with the first output signal line. Either the source or the drain of the third transistor is always in contact with the second clock signal line. The source or drain of the third transistor, the other of which is always in contact with the second output signal line, Either the source or drain of the fourth transistor is always in contact with the gate of the third transistor. The source or drain of the fourth transistor, the other of which is always in conductivity with the first signal line, The first terminal of the second capacitive element is always in electrical contact with the gate of the third transistor. The second terminal of the second capacitive element is always in conductivity with the second output signal line. Either the source or the drain of the fifth transistor is always in contact with the third clock signal line. The source or drain of the fifth transistor, the other of which is always in contact with the third output signal line, Either the source or drain of the sixth transistor is always in contact with the gate of the fifth transistor. The source or drain of the sixth transistor, the other of which is always in conductivity with the first signal line, The first terminal of the third capacitive element is always in electrical contact with the gate of the fifth transistor. The second terminal of the third capacitive element is always in conductivity with the third output signal line. When the first signal line is in a conductive state with the gate of the first transistor, at least through the channel formation region of the second transistor, the gate of the second transistor is supplied with a potential that turns on the second transistor for a period of time. When the first signal line is in conduction with the gate of the third transistor, at least through the channel formation region of the fourth transistor, the gate of the fourth transistor is supplied with a potential that turns on the fourth transistor for a period of time. When the first signal line is in conduction with the gate of the fifth transistor, at least through the channel forming region of the sixth transistor, the gate of the sixth transistor is supplied with a potential that turns on the sixth transistor for a period of time. The signal from the first output signal line is not input to the k+1 circuit. The signal from the first output signal line is not input to the k+2 circuit. The signal from the second output signal line is not input to the circuit k. The signal from the second output signal line is not input to the k+2 circuit. The signal from the third output signal line is not input to the circuit k. The signal from the third output signal line is not input to the k+1 circuit. A semiconductor device in which at least one of the first to sixth transistors has a bottom-gate transistor structure.

Images