Pixel and electronic device

Abstract

To provide an electronic device including a pixel with improved display quality.SOLUTION: A first transistor including a first electrode, a second electrode, a gate electrode, and a lower gate electrode, a second transistor connected between a data line and the gate electrode of the first transistor, and a fifth transistor connected between the first node and the first electrode of the first transistor; (5) a sixth transistor connected between the second electrode of the first transistor and a second driving voltage line, (6) a seventh transistor connected between the first electrode and the lower gate electrode of the first transistor, (7) a first capacitor connected between the gate electrode and the second electrode of the first transistor, and (8) a second capacitor connected between the lower gate electrode and the second electrode of the first transistor.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to electronic devices that include pixels. [Background technology]

[0002] Among electronic devices, light-emitting electronic devices display images using light-emitting elements that generate light through the recombination of electrons and holes. Such light-emitting electronic devices have advantages of fast response speed and low power consumption.

[0003] An emissive electronic device includes pixels connected to data lines and scan lines. A pixel generally includes a light emitting element and a pixel circuit for controlling the amount of current flowing through the light emitting element. The pixel circuit controls the amount of current flowing through the light emitting element in response to a data signal. In this case, light of a predetermined brightness is generated in accordance with the amount of current flowing through the light emitting element. Summary of the Invention [Problem to be solved by the invention]

[0004] It is an object of the present invention to provide an electronic device including pixels with improved display quality. [Means for solving the problem]

[0005] According to one aspect of the present invention to achieve this object, a pixel includes: (1) a light-emitting element including an anode connected to a first driving voltage line and a cathode connected to a first node; (2) a first transistor including a first electrode, a second electrode, a gate electrode, and a bottom gate electrode; (3) a second transistor connected between a data line and the gate electrode of the first transistor; (4) a fifth transistor connected between the first node and the first electrode of the first transistor; (5) a sixth transistor connected between the second electrode of the first transistor and a second driving voltage line; (6) a seventh transistor connected between the first electrode and the bottom gate electrode of the first transistor; (7) a first capacitor connected between the gate electrode and the second electrode of the first transistor; and (8) a second capacitor connected between the bottom gate electrode and the second electrode of the first transistor.

[0006] In one embodiment, the second transistor includes a gate electrode that receives a first scan signal, the fifth transistor includes a gate electrode that receives a first light-emitting signal, the sixth transistor includes a gate electrode that receives a second light-emitting signal, and the seventh transistor includes a gate electrode that receives a second scan signal.

[0007] In an embodiment, the pixel may further include a third transistor connected between a third driving voltage line receiving a first initialization voltage and the gate electrode of the first transistor, and a fourth transistor connected between a fourth driving voltage line receiving a second initialization voltage and the first electrode of the first transistor.

[0008] In one embodiment, the second initialization voltage may have a higher voltage level than the first initialization voltage.

[0009] In one embodiment, the second initialization voltage may have a higher voltage level than the second driving voltage received on the second driving voltage line.

[0010] In one embodiment, the third transistor may include a gate electrode that receives the second light-emitting signal, and the fourth transistor may include a gate electrode that receives a third scan signal.

[0011] In one embodiment, the third transistor, the fourth transistor, the fifth transistor, and the seventh transistor may be turned on during an initialization period.

[0012] In one embodiment, during the initialization period, the threshold voltage of the first transistor may be negatively shifted.

[0013] In one embodiment, the first transistor, the third transistor, the sixth transistor, and the seventh transistor may be turned on during the compensation period.

[0014] In one embodiment, the threshold voltage of the first transistor may be set to 0V during the compensation period.

[0015] In one embodiment, the second transistor and the sixth transistor may be turned on during a write period.

[0016] In an embodiment, the fourth transistor may be turned on during the light emitting device initialization period.

[0017] In one embodiment, the first transistor, the fifth transistor, and the sixth transistor may be turned on during a light-emitting period.

[0018] In one embodiment, each of the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the seventh transistor may be an N-type transistor.

[0019] According to one aspect of the present invention, a pixel includes a light emitting element including an anode connected to a first driving voltage line and a cathode connected to a first node; a first transistor including a first electrode, a second electrode, a gate electrode, and a lower gate electrode; a second transistor connected between a data line and the second node; a third transistor connected between the second node and a third driving voltage line; a fourth transistor connected between a fourth driving voltage line and the first node; a fifth transistor connected between the first node and the first electrode of the first transistor; a sixth transistor connected between the second electrode of the first transistor and a second driving voltage line; a seventh transistor connected between the first electrode and the gate electrode of the first transistor; a first capacitor connected between the gate electrode of the first transistor and the second node; and a second capacitor connected between a fifth driving voltage line and the second node.

[0020] In one embodiment, the second transistor includes a gate electrode that receives a first scan signal, the third transistor and the seventh transistor each include a gate electrode that receives a third scan signal, the fourth transistor includes a gate electrode that receives a second scan signal, the fifth transistor includes a gate electrode that receives a first light-emitting signal, and the sixth transistor includes a gate electrode that receives a second light-emitting signal.

[0021] In one embodiment, the third transistor, the fourth transistor, the fifth transistor, and the seventh transistor may be turned on during an initialization period.

[0022] In one embodiment, the first transistor, the third transistor, the sixth transistor, and the seventh transistor may be turned on during the compensation period.

[0023] In one embodiment, the initialization period and the compensation period may be alternately repeated twice.

[0024] In one embodiment, the second transistor may be turned on during a write period.

[0025] In an embodiment, the fourth transistor may be turned on during the light emitting device initialization period.

[0026] In one embodiment, the first transistor, the fifth transistor, and the sixth transistor may be turned on during a light-emitting period.

[0027] According to one aspect of the present invention, an electronic device includes a display panel including pixels and a data driving circuit for providing a data signal to the pixels, the pixels including: (1) a light-emitting element including an anode connected to a first driving voltage line and a cathode connected to a first node, (2) a first transistor including a first electrode, a second electrode, a gate electrode, and a bottom gate electrode, (3) a second transistor connected between a data line transmitting the data signal and the gate electrode of the first transistor, (4) a fifth transistor connected between the first node and the first electrode of the first transistor, (5) a sixth transistor connected between the second electrode of the first transistor and a second driving voltage line, (6) a seventh transistor connected between the first electrode and the bottom gate electrode of the first transistor, (7) a first capacitor connected between the gate electrode and the second electrode of the first transistor, and (8) a second capacitor connected between the bottom gate electrode and the second electrode of the first transistor.

[0028] In one embodiment, the second transistor includes a gate electrode that receives a first scan signal, the fifth transistor includes a gate electrode that receives a first light-emitting signal, the sixth transistor includes a gate electrode that receives a second light-emitting signal, and the seventh transistor includes a gate electrode that receives a second scan signal.

[0029] In one embodiment, the pixel may further include: (1) a third transistor connected between a third driving voltage line receiving a first initialization voltage and the gate electrode of the first transistor, the third transistor including a gate electrode receiving the second light-emitting signal; and (2) a fourth transistor connected between a fourth driving voltage line receiving a second initialization voltage and the first electrode of the first transistor, the fourth transistor including a gate electrode receiving a third scan signal.

[0030] In one embodiment, the display device may further include: (1) a scan driving circuit that provides the first scan signal, the second scan signal, and the third scan signal; (2) a light emitting driving circuit that provides the first light emitting signal and the second light emitting signal; and (3) a voltage generator that provides a first driving voltage, a second driving voltage, the first initialization voltage, and the second initialization voltage to the first to fourth driving voltage lines.

[0031] In one embodiment, the third transistor, the fourth transistor, the fifth transistor, and the seventh transistor may be turned on during an initialization period, and the threshold voltage of the first transistor may be negatively shifted during the initialization period.

[0032] In one embodiment, during the compensation period, the first transistor, the third transistor, the sixth transistor, and the seventh transistor may be turned on, and during the compensation period, the threshold voltage of the first transistor may be set to 0V. [Effects of the Invention]

[0033] In a pixel having such a configuration, a change in characteristics due to deterioration of the light emitting element is not transmitted to the first transistor, and therefore, it is possible to prevent a decrease in display quality due to deterioration of the light emitting element.

[0034] Furthermore, since the threshold voltage of the first transistor can be set to 0V during the initialization period and the compensation period, the influence of the threshold voltage of the first transistor can be minimized. [Brief explanation of the drawings]

[0035] [Figure 1] 1 is a block diagram of an electronic device according to one embodiment of the present invention. [Figure 2] FIG. 2 is a circuit diagram of a pixel according to an embodiment of the present invention. [Figure 3] 4 is a timing diagram illustrating an operation of a pixel according to an embodiment of the present invention. [Figure 4A] 1 is a circuit diagram (1) illustrating the operation of a pixel according to an embodiment of the present invention. [Figure 4B] FIG. 2 is a circuit diagram (2) for explaining the operation of a pixel according to one embodiment of the present invention. [Figure 4C] FIG. 3 is a circuit diagram (3) for explaining the operation of a pixel according to one embodiment of the present invention. [Figure 4D] FIG. 4 is a circuit diagram (4) for explaining the operation of a pixel according to one embodiment of the present invention. [Figure 4E] FIG. 5 is a circuit diagram (5) for explaining the operation of a pixel according to one embodiment of the present invention. [Figure 5] 10 is a diagram illustrating an example of a threshold voltage Vth of a first transistor depending on a body-source voltage of the first transistor; [Figure 6] 1 is a block diagram of an electronic device according to one embodiment of the present invention. [Figure 7] FIG. 2 is a circuit diagram of a pixel according to an embodiment of the present invention. [Figure 8] 4 is a timing diagram illustrating an operation of a pixel according to an embodiment of the present invention. [Figure 9A] 1 is a circuit diagram (1) illustrating the operation of a pixel according to an embodiment of the present invention. [Figure 9B] FIG. 2 is a circuit diagram (2) for explaining the operation of a pixel according to one embodiment of the present invention. [Figure 9C] FIG. 3 is a circuit diagram (3) for explaining the operation of a pixel according to one embodiment of the present invention. [Figure 9D]FIG. 4 is a circuit diagram (4) for explaining the operation of a pixel according to one embodiment of the present invention. [Figure 9E] FIG. 5 is a circuit diagram (5) for explaining the operation of a pixel according to one embodiment of the present invention. [Figure 10] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention; [Figure 11A] 11 is an enlarged cross-sectional view of a display panel according to an embodiment of the present invention, taken along an enlarged area AA in FIG. 10. FIG. [Figure 11B] 11 is an enlarged cross-sectional view of a display panel according to an embodiment of the present invention, enlarging a region BB in FIG. 10. FIG. [Figure 12] 1 is a cross-sectional view of a display panel according to an embodiment of the present invention; [Figure 13A] 1 is an enlarged plan view (1) of a partial area of ​​a display panel according to an embodiment of the present invention. [Figure 13B] FIG. 2 is an enlarged plan view (2) of a partial area of ​​a display panel according to an embodiment of the present invention. [Figure 13C] FIG. 3 is an enlarged plan view (3) of a partial area of ​​a display panel according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0036] In this specification, when a certain component (or region, layer, portion, etc.) is described as being "on," "coupled," or "bonded" to another component, it means that it can be directly disposed / coupled / bonded to the other component, or that a third component can be disposed therebetween.

[0037] The same reference numerals refer to the same elements. Also, in the drawings, thickness, ratio, and dimensions of elements are exaggerated for efficient explanation of technical content. "And / or" includes all one or more combinations that the associated configurations can define.

[0038] Terms such as "first," "second," etc. may be used to describe various components, but the components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, a first component may be referred to as a "second component," and similarly, a second component may be referred to as a "first component" without departing from the scope of the present invention. A singular expression includes a plural expression unless the context clearly dictates otherwise.

[0039] Furthermore, terms such as "under," "below," "on," and "above" are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0040] The use of terms such as "comprise" or "have" is intended to specify the presence of a stated feature, number, step, operation, component, part, or combination thereof, but should be understood as not precluding the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0041] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention belongs. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning they have in the context of the relevant art, and should not be interpreted as being overly ideal or overly formal unless explicitly defined herein.

[0042] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0043] FIG. 1 is a block diagram of an electronic device DD according to one embodiment of the present invention.

[0044] Referring to FIG. 1, the electronic device DD includes a display panel DP, a driving controller 100, a data driving circuit 200, a scan driving circuit 300, a light emitting driving circuit 400, and a voltage generator 500.

[0045] The drive controller 100 receives the image signal RGB and the control signal CTRL. The drive controller 100 converts the image signal RGB into an image data signal DS and outputs it. The drive controller 100 outputs a scan control signal SCS, a data control signal DCS, and a light emission drive control signal ECS.

[0046] The data driving circuit 200 receives a data control signal DCS and an image data signal DS from the driving controller 100. The data driving circuit 200 converts the image data signal DS into a data signal and outputs the data signal to a plurality of data lines DL1-DLm, which will be described later.

[0047] The scan driving circuit 300 receives a scan control signal SCS from the driving controller 100. The scan driving circuit 300 can output scan signals to the first scan lines GWL1-GWLn, the second scan lines GCL1-GCLn, and the third scan lines GIL1-GILn in response to the scan control signal SCS.

[0048] The light emitting drive circuit 400 receives a light emitting control signal ECS from the drive controller 100. The light emitting drive circuit 400 can output light emitting signals to the first light emitting lines EML11-EML1n and the second light emitting lines EML21-EML2n in response to the light emitting control signal ECS.

[0049] The voltage generator 500 generates voltages necessary for the operation of the display panel DP. In this embodiment, the voltage generator 500 can generate a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VREF, and a second initialization voltage Vcint, which are necessary for the operation of the display panel DP.

[0050] The display panel DP includes first scan lines GWL1-GWLn, second scan lines GCL1-GCLn, third scan lines GIL1-GILn, first light emitting lines EML11-EML1n, second light emitting lines EML21-EML2n, data lines DL1-DLm, and pixels PX.

[0051] The display panel DP includes an active area AA and a non-active area NAA. In one embodiment, the pixels PX are disposed in the active area AA of the display panel DP, and the scan driving circuit 300 and the emission driving circuit 400 are disposed in the non-active area NAA of the display panel DP.

[0052] In one embodiment, the scan driving circuit 300 is arranged adjacent to a first side of the active area AA. The first scan lines GWL1-GWLn, second scan lines GCL1-GCLn, and third scan lines GIL1-GILn extend from the scan driving circuit 300 in a first direction DR1. The light emitting driving circuit 400 is arranged adjacent to a second side of the active area AA. The first light emitting lines EML11-EML1n and second light emitting lines EML21-EML2n extend from the light emitting driving circuit 400 in the opposite direction of the first direction DR1.

[0053] The first scan lines GWL1-GWLn, second scan lines GCL1-GCLn, third scan lines GIL1-GILn, and first light emitting lines EML11-EML1n and second light emitting lines EML21-EML2n are spaced apart from one another in the second direction DR2. The data lines DL1-DLm extend from the data driving circuit 200 in a direction opposite to the second direction DR2 and are spaced apart from one another in the first direction DR1.

[0054] 1, the scan driving circuit 300 and the emission driving circuit 400 are arranged facing each other across the pixel PX, but the present invention is not limited to this. For example, the scan driving circuit 300 and the emission driving circuit 400 may be arranged adjacent to each other in the non-active area NAA of the display panel DP. In one embodiment, the scan driving circuit 300 and the emission driving circuit 400 may be configured as a single circuit.

[0055] The pixels PX are electrically connected to the first scan lines GWL1-GWLn, the second scan lines GCL1-GCLn, the third scan lines GIL1-GILn, the first light-emitting lines EML11-EML1n, the second light-emitting lines EML21-EML2n, and the data lines DL1-DLm, respectively.

[0056] Each of the pixels PX may be electrically connected to three scan lines and two light-emitting lines. For example, as shown in FIG. 1, the pixels PX in the first row may be connected to the first scan line GWL1, the second scan line GCL1, the third scan line GIL1, the first light-emitting line EML11, and the second light-emitting line EML21. The pixels PX in the i-th row may be connected to the first scan line GWLi, the second scan line GCLi, the third scan line GILi, the first light-emitting line EML1i, and the second light-emitting line EML2i. The pixels in the n-th row may be connected to the first scan line GWLn, the second scan line GCLn, the third scan line GILn, the first light-emitting line EML1n, and the second light-emitting line EML2n.

[0057] Each of the plurality of pixels PX may include a light-emitting element ED (see FIG. 2) and a plurality of transistors T1-T7 (see FIG. 2) that control the light emission of the light-emitting element ED. The scan driving circuit 300 and the light-emitting driving circuit 400 may include transistors formed through the same process as the plurality of transistors T1-T7.

[0058] FIG. 2 is a circuit diagram of a pixel PX according to an embodiment of the present invention.

[0059] FIG. 2 exemplarily illustrates a circuit diagram of a pixel PX connected to the jth data line DLj among the data lines DL1-DLm, the first scan line GWLi among the first scan lines GWL1-GWLn, the second scan line GCLi among the second scan lines GCL1-GCLn, the third scan line GILi among the third scan lines GIL1-GILn, the first light-emitting line EML1i among the first light-emitting lines EML11-EML1n, and the second light-emitting line EML2i among the second light-emitting lines EML21-EML2n shown in FIG. 1.

[0060] Each of the plurality of pixels PX shown in FIG. 1 may include the same circuit configuration as the pixel PX shown in FIG.

[0061] Referring to FIG. 2, a pixel PX of an electronic device according to an embodiment includes at least one light emitting element ED, first to seventh transistors T1, T2, T3, T4, T5, T6, and T7, a first capacitor Cst, and a second capacitor Cth.

[0062] In one embodiment, the light emitting element ED may be a light emitting diode. In this embodiment, an example in which one pixel PX includes one light emitting element ED will be described.

[0063] In this embodiment, each of the first to seventh transistors T1-T7 may be an N-type transistor having an oxide semiconductor as a semiconductor layer. However, the present invention is not limited to this, and at least one of the first to seventh transistors T1-T7 may be a P-type transistor having an LTPS (low-temperature polycrystalline silicon) semiconductor layer. In addition, the circuit configuration of the pixel PX according to the present invention is not limited to that shown in FIG. 2 and may be modified.

[0064] The first scan line GWLi, the second scan line GCLi, and the third scan line GILi transmit the first scan signal GWi, the second scan signal GCi, and the third scan signal GIi, respectively, provided from the scan driving circuit 300 (see FIG. 1).

[0065] The first light-emitting line EML1i and the second light-emitting line EML2i may transmit the first light-emitting signal EM1i and the second light-emitting signal EM2i provided from the light-emitting driving circuit 400 (see FIG. 1).

[0066] The data line DLj transmits a data signal Dj provided from the data driving circuit 200 (see FIG. 1). The data signal Dj may have a voltage level corresponding to the image signal RGB input to the electronic device DD (see FIG. 1). The first to fourth driving voltage lines VL1, VL2, VL3, and VL4 may transmit a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VREF, and a second initialization voltage Vcint.

[0067] The light emitting element ED is connected between the first driving voltage line VL1 and the first node N1, that is, the anode of the light emitting element ED is connected to the first driving voltage line VL1, and the cathode is connected to the first node N1.

[0068] The first transistor T1 includes a first electrode D, a second electrode S, a gate electrode G, and a bottom gate electrode BG, which may be referred to as a body electrode or a back-gate electrode.

[0069] The second transistor TT2 is connected between the data line DLj and the gate electrode G of the first transistor T1, and includes a gate electrode connected to the first scan line GWLi.

[0070] The third transistor T3 is connected between the third driving voltage line VL3 and the gate electrode G of the first transistor T1, and includes a gate electrode connected to the second scan line GCLi.

[0071] The fourth transistor T4 is connected between the fourth driving voltage line VL4 and the first node N1, and includes a gate electrode connected to the third scan line GILi.

[0072] The fifth transistor T5 is connected between the first node N1 and the first electrode D of the first transistor T1, and includes a gate electrode connected to the first light-emitting line EML1i.

[0073] The sixth transistor T6 is connected between the second electrode S of the first transistor T1 and the second driving voltage line VL2, and includes a gate electrode connected to the second light-emitting line EML2i.

[0074] The seventh transistor T7 is connected between the first electrode D of the first transistor T1 and the bottom gate electrode BG of the first transistor T1, and includes a gate electrode connected to the second scan line GCLi.

[0075] The first capacitor Cst is connected between the gate electrode G of the first transistor T1 and the second electrode S of the first transistor T1.

[0076] The second capacitor Cth is connected between the bottom gate electrode BG of the first transistor T1 and the second electrode S of the first transistor T1.

[0077] FIG. 3 is a timing diagram illustrating the operation of the pixel PX according to an embodiment of the present invention.

[0078] 4A to 4E are circuit diagrams illustrating the operation of a pixel PX according to an embodiment of the present invention.

[0079] Referring to Figures 3 and 4A, during the initialization period PI, each of the first light-emitting signal EM1i, the second scan signal GCi, and the third scan signal GIi is at an active level (e.g., a high level), and each of the second light-emitting signal EM2i and the first scan signal GWi is at an inactive level (e.g., a low level).

[0080] While the first light-emitting signal EM1i, the second scan signal GCi, and the third scan signal GIi are at a high level, the third, fourth, fifth, and seventh transistors T3, T4, T5, and T7 are turned on.

[0081] Therefore, during the initialization period PI, a first initialization voltage VREF is transmitted to the gate electrode G of the first transistor T1 through the third transistor T3. Also, during the initialization period PI, a second initialization voltage Vcint is transmitted to the bottom gate electrode BG of the first transistor T1 through the fourth, fifth, and seventh transistors T4, T5, and T7. That is, during the initialization period PI, the first initialization voltage VREF may be transmitted to the gate electrode G of the first transistor T1, and the second initialization voltage Vcint may be transmitted to the bottom gate electrode BG of the first transistor T1. The initialization period PI may be a period in which each of the gate electrode G and bottom gate electrode BG of the first transistor T1 is initialized to a predetermined voltage.

[0082] In one embodiment, the second initialization voltage Vcint may be higher than the first initialization voltage VREF and the second driving voltage ELVSS. When the voltage level of the bottom gate electrode BG of the first transistor T1 increases, the body-source voltage (referred to as Vbs) of the first transistor T1 becomes higher than 0 V (Vbs>0). As a result, the threshold voltage Vth of the first transistor T1 may shift negatively during the initialization period PI. Referring to FIGS. 3 and 4B, during the compensation period PC, the second light-emitting signal EM2i and the second scan signal GCi are each at an active level (e.g., a high level), and the first light-emitting signal EM1i, the first scan signal GWi, and the third scan signal GIi are each at an inactive level (e.g., a low level).

[0083] While the second light-emitting signal EM2i and the second scan signal GCi are at a high level, the third, sixth, and seventh transistors T3, T6, and T7 are turned on.

[0084] Therefore, during the compensation period PC, the first initialization voltage VREF is transmitted to the gate electrode G of the first transistor T1 through the third transistor T3, and the second driving voltage ELVSS is transmitted to the bottom gate electrode BG of the first transistor T1 through the sixth, first, and seventh transistors T6, T1, and T7.

[0085] That is, during the compensation period PC, the first initialization voltage VREF may be transmitted to the gate electrode G of the first transistor T1, and the second driving voltage ELVSS may be transmitted to the bottom gate electrode BG of the first transistor T1.

[0086] FIG. 5 is a graph showing an example of the threshold voltage Vth of the first transistor T1 depending on the body-source voltage Vbs of the first transistor T1.

[0087] 4B and 5, the voltage levels of the body-source voltages Vbs1, Vbs2, Vbs3, Vbs4, Vbs5, and Vbs6 of the first transistor T1 have a relationship of Vbs1>Vbs2>Vbs3>Vbs4>Vbs5>Vbs6.

[0088] That is, the higher the body-source voltage Vbs of the first transistor T1, the more negatively the threshold voltage Vth of the first transistor T1 shifts, and the lower the body-source voltage Vbs of the first transistor T1, the more positively the threshold voltage Vth of the first transistor T1 shifts.

[0089] 3 and 4B, when the second driving voltage ELVSS is applied to the bottom gate electrode BG of the first transistor T1, the body-source voltage Vbs of the first transistor T1 decreases. While the body-source voltage Vbs of the first transistor T1 decreases, the threshold voltage Vth of the first transistor T1 changes in a positive direction.

[0090] First, during the initialization period PI, the threshold voltage Vth of the first transistor T1 is shifted negatively, and then the threshold voltage Vth of the first transistor T1 shifts positively. After that, when the threshold voltage Vth of the first transistor T1 becomes 0V, no further current flows through the first transistor T1.

[0091] A first initialization voltage VREF and a second driving voltage ELVSS may be applied to a first electrode and a second electrode of the first capacitor Cst, respectively.

[0092] When no current flows through the first transistor T1, the voltage of the bottom gate electrode BG of the first transistor T1 and the second driving voltage ELVSS may be transmitted to the first electrode and the second electrode of the second capacitor Cth, respectively.

[0093] After the initialization period PI and the compensation period PC, the threshold voltage Vth of the first transistor T1 may be set to 0 V. That is, the threshold voltage Vth of the first transistor T1 may be compensated.

[0094] On the other hand, the voltage of the lower gate electrode BG of the first transistor T1, that is, the body voltage, is stored in the second capacitor Cth.

[0095] Referring to Figures 3 and 4C, during the write period PW, the second light-emitting signal EM2i and the first scan signal GWi are each at an active level (e.g., a high level), and the first light-emitting signal EM1i, the second scan signal GCi, and the third scan signal GIi are each at an inactive level (e.g., a low level).

[0096] While the second light-emitting signal EM2i and the first scan signal GWi are at a high level, the second and sixth transistors T2 and T6 are turned on.

[0097] Therefore, during the write period PW, the data signal Dj transmitted through the data line DLj is transmitted to the gate electrode G of the first transistor T1 and the first electrode of the first capacitor Cst through the second transistor TT2. Also, during the write period PW, the second driving voltage ELVSS may be transmitted to the second electrode of the first capacitor Cst and the second electrode of the second capacitor Cth.

[0098] That is, during the write period PW, the data signal Dj can be transferred to the first electrode of the first capacitor Cst.

[0099] Referring to Figures 3 and 4D, during the light emitting element initialization period PEI, the third scan signal GIi is at an active level (e.g., a high level), and each of the first light emitting signal EM1i, the second light emitting signal EM2i, the first scan signal GWi, and the second scan signal GCi is at an inactive level (e.g., a low level).

[0100] While the third scan signal GIi is at a high level, the fourth transistor T4 is turned on.

[0101] The second initialization voltage Vcint from the fourth driving voltage line VL4 can be transmitted to the cathode of the light emitting element ED through the fourth transistor T4.

[0102] Therefore, during the initialization period PEI, the cathode of the light emitting element ED can be initialized with the second initialization voltage Vcint.

[0103] Referring to Figures 3 and 4E, during the light-emitting period PE, each of the first light-emitting signal EM1i and the second light-emitting signal EM2i is at an active level (e.g., a high level), and each of the first scan signal GWi, the second scan signal GCi, and the third scan signal GIi is at an inactive level (e.g., a low level).

[0104] While the first light-emitting signal EM1i and the second light-emitting signal EM2i are at a high level, the fifth and sixth transistors T5 and T6 are turned on.

[0105] Meanwhile, if the voltage corresponding to the data signal Dj stored in the first capacitor Cst is transmitted to the gate electrode G of the first transistor T1, a current path can be formed between the first driving voltage line VL1 and the second driving voltage line VL2 through the light emitting element ED and the fifth, first, and sixth transistors T5, T1, and T6.

[0106] Therefore, during the light-emitting period PE, a current corresponding to the data signal Dj flows through the light-emitting element ED, causing the light-emitting element ED to emit light.

[0107] The characteristics of the light emitting element ED in the pixel PX may change over time. A current (referred to as Ids) flows between the first electrode D and the second electrode S of the first transistor T1 depending on the gate-source voltage (referred to as Vgs) of the first transistor T1. If the light emitting element ED is connected to the second electrode S of the first transistor T1, a change in the characteristics of the light emitting element ED will change the gate-source voltage Vgs of the first transistor T1, which may affect the current Ids of the first transistor T1.

[0108] As described above, since the light emitting element ED in the pixel PX is connected to the first electrode D of the first transistor T1 through the fifth transistor T5, the change in characteristics due to the degradation of the light emitting element ED is not transmitted to the first transistor T1, thereby preventing the degradation of the display quality due to the degradation of the light emitting element ED.

[0109] Furthermore, during the initialization period PI (see FIG. 3) and the compensation period PC, the threshold voltage Vth of the first transistor T1 may be set to 0 V. That is, the threshold voltage Vth of the first transistor T1 in each of the plurality of pixels PX (see FIG. 1) may be set to a uniform value. As a result, it is possible to prevent degradation of image quality due to deviation in the threshold voltage Vth of the first transistor T1 in each of the plurality of pixels PX (see FIG. 1).

[0110] FIG. 6 is a block diagram of an electronic device DDa according to one embodiment of the present invention.

[0111] Referring to FIG. 6, the electronic device DDa includes a display panel DPa, a driving controller 100a, a data driving circuit 200a, a scan driving circuit 300a, a light emitting driving circuit 400a, and a voltage generator 500a.

[0112] Among the components of the electronic device DDa shown in FIG. 6, the same components as those of the electronic device DD shown in FIG. 1 are denoted by the same reference numerals.

[0113] The drive controller 100a receives the image signal RGB and the control signal CTRL. The drive controller 100a converts the image signal RGB into an image data signal DS and outputs it. The drive controller 100a outputs a scan control signal SCS, a data control signal DCS, and a light emission drive control signal ECS.

[0114] The data driving circuit 200a receives a data control signal DCS and an image data signal DS from the driving controller 100a. The data driving circuit 200a converts the image data signal DS into a data signal and outputs the data signal to a plurality of data lines DL1-DLm, which will be described later.

[0115] The scan driving circuit 300a receives a scan control signal SCS from the driving controller 100a and outputs scan signals to the first scan lines GWL1-GWLn, the second scan lines GCL1-GCLn, and the third scan lines GRL1-GRLn in response to the scan control signal SCS.

[0116] The light emission drive circuit 400a receives a light emission control signal ECS from the drive controller 100a. In response to the light emission control signal ECS, the light emission drive circuit 400a can output light emission signals to the first light emission lines EML11-EML1n and the second light emission lines EML21-EML2n.

[0117] The voltage generator 500a generates voltages necessary for the operation of the display panel DPa. In this embodiment, the voltage generator 500a can generate a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VREF, a second initialization voltage Vcint, and a compensation voltage Vcomp, which are necessary for the operation of the display panel DPa.

[0118] The display panel DPa includes first scan lines GWL1-GWLn, second scan lines GCL1-GCLn, third scan lines GRL1-GRLn, first light-emitting lines EML11-EML1n, second light-emitting lines EML21-EML2n, data lines DL1-DLm, and pixels PXa.

[0119] The display panel DPa includes an active area AA and a non-active area NAA. In one embodiment, the pixels PX are disposed in the active area AA of the display panel DPa, and the scan driving circuit 300a and the emission driving circuit 400a are disposed in the non-active area NAA of the display panel DPa.

[0120] In one embodiment, the scan driving circuit 300a is arranged adjacent to a first side of the active area AA. The first scan lines GWL1-GWLn, second scan lines GCL1-GCLn, and third scan lines GRL1-GRLn extend from the scan driving circuit 300a in a first direction DR1. The light emitting driving circuit 400a is arranged adjacent to a second side of the active area AA. The first light emitting lines EML11-EML1n and second light emitting lines EML21-EML2n extend from the light emitting driving circuit 400a in the opposite direction to the first direction DR1.

[0121] The first scan lines GWL1-GWLn, second scan lines GCL1-GCLn, third scan lines GRL1-GRLn, and first light emitting lines EML11-EML1n and second light emitting lines EML21-EML2n are spaced apart from each other in the second direction DR2. The data lines DL1-DLm extend from the data driving circuit 200a in a direction opposite to the second direction DR2 and are spaced apart from each other in the first direction DR1.

[0122] 6, the scan driving circuit 300a and the emission driving circuit 400a are arranged opposite each other across the pixel PXa, but the present invention is not limited to this. For example, the scan driving circuit 300a and the emission driving circuit 400a may be arranged adjacent to each other in the inactive area NAA of the display panel DPa. In one embodiment, the scan driving circuit 300a and the emission driving circuit 400a may be configured as a single circuit.

[0123] The pixels PX are electrically connected to the first scan lines GWL1-GWLn, the second scan lines GCL1-GCLn, the third scan lines GRL1-GRLn, the first light-emitting lines EML11-EML1n, the second light-emitting lines EML21-EML2n, and the data lines DL1-DLm, respectively.

[0124] Each of the pixels PX may be electrically connected to three scan lines and two light-emitting lines. For example, as shown in FIG. 1, the pixels PX in the first row may be connected to the first scan line GWL1, the second scan line GCL1, the third scan line GIL1, the first light-emitting line EML11, and the second light-emitting line EML21. The pixels PX in the i-th row may be connected to the first scan line GWLi, the second scan line GCLi, the third scan line GILi, the first light-emitting line EML1i, and the second light-emitting line EML2i. The pixels in the n-th row may be connected to the first scan line GWLn, the second scan line GCLn, the third scan line GILn, the first light-emitting line EML1n, and the second light-emitting line EML2n.

[0125] Each of the plurality of pixels PX may include a light-emitting element ED (see FIG. 7) and a plurality of transistors TT1-TT7 (see FIG. 7) that control the light emission of the light-emitting element ED. The scan driving circuit 300a and the light-emitting driving circuit 400a may include transistors formed through the same process as the plurality of transistors TT1-TT7.

[0126] FIG. 7 is a circuit diagram of a pixel PXa according to one embodiment of the present invention.

[0127] FIG. 7 exemplarily illustrates a circuit diagram of a pixel PX connected to the jth data line DLj among the data lines DL1-DLm, the first scan line GWLi among the first scan lines GWL1-GWLn, the second scan line GCLi among the second scan lines GCL1-GCLn, the third scan line GRLi among the third scan lines GRL1-GRLn, the first light-emitting line EML1i among the first light-emitting lines EML11-EML1n, and the second light-emitting line EML2i among the second light-emitting lines EML21-EML2n shown in FIG. 1.

[0128] Each of the plurality of pixels PXa shown in FIG. 6 may include the same circuit configuration as the pixel PXa shown in FIG.

[0129] Referring to FIG. 7, a pixel PXa of an electronic device according to an embodiment includes at least one light emitting element ED, first to seventh transistors TT1, TT2, TT3, TT4, TT5, TT6, and TT7, a first capacitor Cst, and a second capacitor Chold.

[0130] In one embodiment, the light emitting element ED may be a light emitting diode. In this embodiment, an example in which one pixel PXa includes one light emitting element ED will be described.

[0131] In this embodiment, each of the first to seventh transistors TT1-TT7 may be an N-type transistor having an oxide semiconductor as a semiconductor layer. However, the present invention is not limited to this, and at least one of the first to seventh transistors TT1-TT7 may be a P-type transistor having an LTPS (low-temperature polycrystalline silicon) semiconductor layer. In addition, the circuit configuration of pixel PXA according to the present invention is not limited to that shown in FIG. 7 and may be modified.

[0132] The first scan line GWLi, the second scan line GCLi, and the third scan line GRLi transmit the first scan signal GWi, the second scan signal GCi, and the third scan signal GRi, respectively, provided from the scan driving circuit 300a (see FIG. 6).

[0133] The first light-emitting line EML1i and the second light-emitting line EML2i may transmit the first light-emitting signal EM1i and the second light-emitting signal EM2i provided from the light-emitting driving circuit 400a (see FIG. 6).

[0134] The data line DLj transmits a data signal Dj provided from the data driving circuit 200a (see FIG. 6). The data signal Dj may have a voltage level corresponding to the image signal RGB input to the electronic device DDa (see FIG. 6). The first to fifth driving voltage lines VL1, VL2, VL3, VL4, and VL5 may transmit a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VREF, a second initialization voltage Vcint, and a compensation voltage Vcomp.

[0135] The light emitting element ED is connected between the first driving voltage line VL1 and the first node N11, that is, the anode of the light emitting element ED is connected to the first driving voltage line VL1, and the cathode is connected to the first node N11.

[0136] The first transistor TT1 includes a first electrode D, a second electrode S, a gate electrode G, and a bottom gate electrode BG. The bottom gate electrode BG may be referred to as a body electrode.

[0137] The bottom gate electrode BG of the first transistor TT1 is connected to a fifth driving voltage line VL5.

[0138] The second transistor TT2 is connected between the data line DLj and a second node N12, and includes a gate electrode connected to the first scan line GWLi.

[0139] The third transistor TT3 is connected between the second node N12 and the third driving voltage line VL3, and includes a gate electrode connected to the third scan line GRLi.

[0140] The fourth transistor TT4 is connected between the fourth driving voltage line VL4 and the first node N11, and includes a gate electrode connected to the second scan line GCLi.

[0141] The fifth transistor TT5 is connected between the first node N11 and the first electrode D of the first transistor TT1, and includes a gate electrode connected to the first light-emitting line EML1i.

[0142] The sixth transistor TT6 is connected between the second electrode S of the first transistor TT1 and the second driving voltage line VL2, and includes a gate electrode connected to the second light-emitting line EML2i.

[0143] The seventh transistor TT7 is connected between the first electrode D of the first transistor TT1 and the gate electrode G of the first transistor T1, and includes a gate electrode connected to the third scan line GRLi.

[0144] The first capacitor Cst is connected between the second node N12 and the gate electrode G of the first transistor TT1.

[0145] The second capacitor Chold is connected between the fifth driving voltage line VL5 and the second node N12.

[0146] FIG. 8 is a timing diagram illustrating the operation of the pixel PXa according to one embodiment of the present invention.

[0147] 9A to 9E are circuit diagrams illustrating the operation of a pixel PXa according to an embodiment of the present invention.

[0148] Referring to Figures 8 and 9A, during the first initialization period TI1, the first light-emitting signal EM1i, the second scan signal GCi, and the third scan signal GRi are each at an active level (e.g., a high level), and the second light-emitting signal EM2i and the first scan signal GWi are each at an inactive level (e.g., a low level).

[0149] While the first light-emitting signal EM1i, the second scan signal GCi, and the third scan signal GRi are at a high level, the third, fourth, fifth, and seventh transistors TT3, TT4, TT5, and TT7 are turned on.

[0150] Therefore, during the first initialization period TI1, a first initialization voltage VREF is transmitted to the second node N12, i.e., the first electrode of the first capacitor Cst and the first electrode of the second capacitor Chold, through the third transistor TT3. Also, during the first initialization period TI1, a second initialization voltage Vcint is transmitted to the gate electrode G of the first transistor TT1 and the second electrode of the first capacitor Cst through the fourth, fifth, and seventh transistors TT4, TT5, and TT7. That is, during the first initialization period TI1, the second initialization voltage Vcint is transmitted to the gate electrode G of the first transistor T1, and the first initialization voltage VREF is transmitted to the second node N12. The first initialization period TI1 may be a period in which the gate electrode G of the first transistor T1 and the second node N12 are initialized to a predetermined voltage. In one embodiment, a compensation voltage Vcomp is applied to the bottom gate electrode BG of the first transistor TT1 and the second electrode of the second capacitor Chold.

[0151] During the first compensation period TC1, the second light-emitting signal EM2i and the third scan signal GRi are each at an active level (e.g., a high level), and the first light-emitting signal EM1i, the first scan signal GWi, and the second scan signal GCi are each at an inactive level (e.g., a low level).

[0152] While the second light-emitting signal EM2i and the third scan signal GRi are at a high level, the third, sixth, and seventh transistors TT3, TT6, and TT7 are turned on.

[0153] Therefore, during the first compensation period TC1, the first initialization voltage VREF is transferred to the second node N12, that is, the first electrode of the first capacitor Cst and the first electrode of the second capacitor Chold, through the third transistor T3.

[0154] In the first initialization period TI1, when the second initialization voltage Vcint is transmitted to the gate electrode G of the first transistor TT1, the first transistor TT1 is turned on.

[0155] When the second light-emitting signal EM2i transitions to a high level while the first transistor TT1 is turned on, the sixth transistor TT6 is turned on, so that a current path can be formed from the gate electrode G of the first transistor TT1 to the second driving voltage line VL2 through the seventh, first, and sixth transistors TT7, TT1, and TT6.

[0156] At this time, the gate electrode G and the first electrode D of the first transistor TT1 are electrically connected to form a diode-connected state. As a result, the voltage of the gate electrode G of the first transistor TT1, i.e., the voltage of the second electrode of the first capacitor Cst, is reduced by an amount corresponding to the threshold voltage (Vth) of the first transistor TT1. For example, the voltage of the second electrode of the first capacitor Cst may be ELVDD-Vth.

[0157] During the second initialization period TI2, the operation of the pixel PXa is the same as that of the first initialization period TI1 described with reference to FIG. 9A, and therefore, a duplicated description will be omitted.

[0158] During the second compensation interval TC2, the operation of the pixel PXa is the same as that during the first compensation interval TC1 described with reference to FIG. 9B, and therefore, a duplicated description will be omitted.

[0159] The first initialization interval TI1, the first compensation interval TC1, the second initialization interval TI2, and the second initialization interval TI3 are sequentially repeated, so that the compensation effect on the threshold voltage Vth of the first transistor TT1 can be increased.

[0160] 8, the initialization period is repeated twice and the compensation period is repeated twice. That is, the initialization period and the compensation period are alternately repeated twice. However, the present invention is not limited to this. Each of the initialization period and the compensation period may be repeated one or more times.

[0161] Referring to Figures 8 and 9C, during the write period TW, the first scan signal GWi is at an active level (e.g., a high level), and each of the first light-emitting signal EM1i, the second light-emitting signal EM2i, the second scan signal GCi, and the third scan signal GRi is at an inactive level (e.g., a low level).

[0162] While the first scan signal GWi is at a high level, the second transistor TT2 is turned on.

[0163] Therefore, during the write period TW, the data signal Dj transmitted through the data line DLj is transmitted to the second node N12 through the second transistor TT2.

[0164] When the voltage of the first electrode of the first capacitor Cst rises from the first initialization voltage VREF by an amount equivalent to the voltage of the data signal Dj, the voltage of the second electrode of the first capacitor Cst also rises from ELVDD-Vth by an amount equivalent to the voltage of the data signal Dj.

[0165] Referring to Figures 8 and 9D, during the light emitting element initialization period TEI, the second scan signal GCi is at an active level (e.g., a high level), and each of the first light emitting signal EM1i, the second light emitting signal EM2i, the first scan signal GWi, and the third scan signal GRi is at an inactive level (e.g., a low level).

[0166] While the second scan signal GCi is at a high level, the fourth transistor TT4 is turned on.

[0167] The second initialization voltage Vcint from the fourth driving voltage line VL4 can be transmitted to the cathode of the light emitting element ED through the fourth transistor TT4.

[0168] Therefore, during the initialization period TEI, the cathode of the light emitting element ED can be initialized with the second initialization voltage Vcint.

[0169] Referring to Figures 8 and 9E, during the light-emitting period TE, each of the first light-emitting signal EM1i and the second light-emitting signal EM2i is at an active level (e.g., a high level), and each of the first scan signal GWi, the second scan signal GCi, and the third scan signal GRi is at an inactive level (e.g., a low level).

[0170] While the first light-emitting signal EM1i and the second light-emitting signal EM2i are at a high level, the fifth and sixth transistors TT5 and TT6 are turned on.

[0171] On the other hand, during the write period TW, the voltage of the second electrode of the first capacitor Cst, i.e., the voltage of the gate electrode G of the first transistor TT1, has risen by the voltage corresponding to the data signal Dj, so the first transistor TT1 is turned on.

[0172] Therefore, a current path may be formed between the first driving voltage line VL1 and the second driving voltage line VL2 through the light emitting element ED and the fifth, first, and sixth transistors TT5, TT1, and TT6.

[0173] As a result, during the light-emitting period PE, a current corresponding to the data signal Dj flows through the light-emitting element ED, causing the light-emitting element ED to emit light.

[0174] The characteristics of the light emitting element ED in the pixel PX may change over time. A current (referred to as Ids) flows between the first electrode D and the second electrode S of the first transistor TT1 depending on the gate-source voltage (referred to as Vgs) of the first transistor TT1. If the light emitting element ED is connected to the second electrode S of the first transistor TT1, a change in the characteristics of the light emitting element ED will change the gate-source voltage Vgs of the first transistor TT1, which may affect the current Ids of the first transistor TT1.

[0175] As described above, since the light emitting element ED in the pixel PXa is connected to the first electrode D of the first transistor TT1 through the fifth transistor TT5, the change in characteristics due to the degradation of the light emitting element ED is not transmitted to the first transistor TT1, thereby preventing the degradation of the display quality due to the degradation of the light emitting element ED.

[0176] Furthermore, during the initialization periods TI1 and TI2 and the compensation periods TC1 and TC2, the voltage of the second electrode of the first capacitor Cst is lowered by an amount corresponding to the threshold voltage Vth of the first transistor TT1. As a result, the current Ids between the first electrode D and the second electrode S of the first transistor TT1 can be determined regardless of the threshold voltage Vth of the first transistor TT1. As a result, it is possible to prevent degradation of image quality due to deviation in the threshold voltage Vth of the first transistor TT1 of each of the plurality of pixels PXa (see FIG. 6).

[0177] FIG. 10 is a cross-sectional view of a display panel DP according to an embodiment of the present invention.

[0178] Referring to FIG. 10, the display panel DP may include a base layer BL, a circuit element layer DP-CL arranged on the base layer BL, an upper insulating layer UIL, connecting wiring CN, a display element layer DP-ED, and an encapsulation layer ESL.

[0179] FIG. 10 illustrates one transistor TR and one capacitor C1 in the pixel PX (see FIG. 2). The transistor TR corresponds to the transistor connected to the light emitting element ED through the connecting line CN, i.e., the transistor connected to the node corresponding to the cathode CE of the light emitting element ED (e.g., the first node N1 in FIG. 2). Specifically, the transistor TR may correspond to the fifth transistor T5 in FIG. 2 or the fifth transistor TT5 in FIG. 7. Meanwhile, although not shown, the other transistors T1, T2, T3, T4, T6, T7, TT1, TT2, TT3, TT4, TT6, and TT7 constituting the pixel PX may have the same structure as the transistor TR illustrated in FIG. 10. However, this is merely an example, and the other transistors T1, T2, T3, T4, T6, T7, TT1, TT2, TT3, TT4, TT6, and TT7 constituting the pixel PX may have a different structure from the transistor TR, and the present invention is not limited to any one embodiment.

[0180] The lower conductive layer BML may be disposed overlapping (stacked) the transistor TR and covered by a first insulating layer 10. At least one of an inorganic barrier layer and a buffer layer may further be disposed between the lower conductive layer BML and the base layer BL.

[0181] In this embodiment, the lower conductive layer BML may be connected to the source of the transistor TR through a source electrode pattern W1. In this case, the lower conductive layer BML may be synchronized with the source of the transistor TR. However, this is merely an example, and the lower conductive layer BML may be connected to the gate of the transistor TR and synchronized with the gate. Alternatively, the lower conductive layer BML may be connected to another electrode and independently receive a constant voltage or a pulse signal. Alternatively, the lower conductive layer BML may be provided in a form isolated from other conductive patterns. The lower conductive layer BML according to an embodiment of the present invention may be provided in various forms and is not limited to any one embodiment.

[0182] A transistor TR may be disposed on the first insulating layer 10. The transistor TR may include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP may be disposed on the first insulating layer 10. The semiconductor pattern SP may include a source region SR, a drain region DR, and a channel region CHR, which are divided according to the degree of conductivity.

[0183] The display panel according to this embodiment may further include a source electrode pattern W1 and a drain electrode pattern W2 connected to the source region SR and the drain region DR, respectively. Specifically, the source electrode pattern W1 and the drain electrode pattern W2 may each be integrally formed with one of the lines constituting the pixel PX (see FIG. 2), and are not limited to any one embodiment.

[0184] The second insulating layer 20 may overlap a plurality of pixels in common and cover the semiconductor pattern SP. The gate electrode GE may be disposed on the second insulating layer 20. The gate electrode GE may correspond to the gate of the transistor TR.

[0185] A third insulating layer 30 may be disposed on the gate electrode GE, and a fourth insulating layer may be disposed on the third insulating layer 30. The plurality of conductive patterns may include a first capacitor electrode CPE1 and a second capacitor electrode CPE2.

[0186] The first capacitor electrode CPE1 and the second capacitor electrode CPE2 constitute a capacitor C1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 may be spaced apart by a second insulating layer 20 interposed therebetween.

[0187] In an embodiment of the present invention, the first capacitor electrode CPE1 and the semiconductor pattern SP may have an integral shape, and the second capacitor electrode CPE2 and the gate electrode GE may have an integral shape.

[0188] In one embodiment, capacitor C1 may correspond to the first capacitor Cst shown in FIG.

[0189] A fourth insulating layer 40 may be disposed on the third insulating layer 30. A source electrode pattern W1 and a drain electrode pattern W2 may be disposed on the fourth insulating layer 40. The source electrode pattern W1 may be connected to a source region SR of the transistor TR through a first contact hole CNT1, and the source region SR of the source electrode pattern W1 and the semiconductor pattern SP may function as the source of the transistor TR. The drain electrode pattern W2 may be connected to a drain region DR of the transistor TR through a second contact hole CNT2, and the drain electrode pattern W2 and the drain region DR of the semiconductor pattern SP may function as the drain of the transistor TR. A fifth insulating layer 50 may be disposed on the source electrode pattern W1 and the drain electrode pattern W2.

[0190] A connecting wire CN may be disposed on the fifth insulating layer 50. The connecting wire CN may electrically connect the transistor TR and the light emitting element ED. The connecting wire CN may be a connection node connecting the transistor TR and the light emitting element ED. That is, the connecting wire CN may correspond to the first node N1 shown in FIG. 2 or the first node N11 shown in FIG. 7. However, this is merely an example, and the connecting wire CN may be defined as a connection node with various elements constituting the pixel PX depending on the design of the pixel PX, as long as it can be connected to the light emitting element ED, and is not limited to any one embodiment.

[0191] An upper insulating layer UIL may be disposed on the interconnection wiring CN. The upper insulating layer UIL may be disposed on the fifth insulating layer 50 to cover the interconnection wiring CN. The upper insulating layer UIL may be an organic layer. For example, the upper insulating layer UIL may include common general-purpose polymers such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyl disiloxane), PMMA (Polymethyl methacrylate), and PS (Polystyrene), polymer derivatives having a phenol-based group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine-based polymers, p-xylene-based polymers, vinyl alcohol-based polymers, and blends thereof.

[0192] The upper insulating layer UIL may have an opening exposing at least a portion of the connecting wire CN. The connecting wire CN may be electrically connected to the light emitting element ED through a portion exposed from the upper insulating layer UIL. That is, the connecting wire CN may electrically connect the transistor TR and the light emitting element ED. This will be described in detail later. Meanwhile, in the display panel DP according to an embodiment of the present invention, the upper insulating layer UIL may be omitted or may be provided in a plurality, and is not limited to any one embodiment.

[0193] A display element layer DP-ED may be disposed on the upper insulating layer UIL. The display element layer DP-ED may include a pixel defining layer PDL, a light-emitting element ED, and a separator SPR. The light-emitting element ED may include an anode AE, an intermediate layer IML, and a cathode CE.

[0194] In this embodiment, the anode AE ​​may be disposed on the upper insulating layer UIL. The anode AE ​​may be a semi-transparent, transparent, or reflective electrode. According to one embodiment of the present invention, the anode AE ​​may include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), and aluminum-doped zinc oxide (AZO). For example, the anode AE ​​may include an ITO / Ag / ITO stacked structure. The anode AE ​​may be connected to the first driving voltage line VL1 (see FIG. 2) and may receive the first driving voltage ELVDD (see FIG. 2).

[0195] The pixel defining layer PDL may define a light emitting opening OP-PDL that exposes at least a portion of the anode AE. A plurality of light emitting openings OP-PDL may be provided and disposed corresponding to each light emitting element. All components of the light emitting element ED may be disposed overlapping each other in the light emitting opening OP-PDL, and the light emitted by the light emitting element ED may be substantially displayed in the light emitting opening OP-PDL.

[0196] The intermediate layer IML may be disposed between the anode AE ​​and the cathode CE. The intermediate layer IML may include an emitting layer EML and a functional layer FNL. The light-emitting element ED may include the intermediate layer IML in various structures and is not limited to any one embodiment. For example, the functional layer FNL may be provided as a plurality of layers, or as two or more layers separated by the emitting layer EML. Alternatively, in one embodiment, the functional layer FNL may be omitted. While FIG. 10 illustrates an embodiment in which the emitting layer EML and the functional layer FNL have different shapes, the present invention is not limited thereto, and the emitting layer EML and the functional layer FNL may be arranged in the same shape on a plane.

[0197] The functional layer FNL may be disposed between the anode AE ​​and the cathode CE. Specifically, the functional layer FNL may be disposed between the anode AE ​​and the emitting layer EML, or between the cathode CE and the emitting layer EML. Alternatively, the functional layer FNL may be disposed both between the anode AE ​​and the emitting layer EML and between the cathode CE and the emitting layer EML. In this embodiment, the emitting layer EML is illustrated as being inserted within the functional layer FNL. However, this is merely an example, and the functional layer FNL may include a layer disposed between the emitting layer EML and the anode AE ​​and / or a layer disposed between the emitting layer EML and the cathode CE. A plurality of each of these layers may be provided, and the present invention is not limited to any one embodiment. The functional layer FNL may include a hole control layer and an electron control layer. At least a portion of the hole control layer may be disposed between the anode AE ​​and the emitting layer EML, and at least a portion of the electron control layer may be disposed between the emitting layer EML and the cathode CE.

[0198] The cathode CE may be disposed on the intermediate layer IML. As described above, the cathode CE may be connected to the connection line CN to be electrically connected to the pixel PX. That is, the cathode CE may be electrically connected to the transistor TR through the connection line CN.

[0199] As described above, the connecting wire CN may include a driving connection portion CDP and an emission connection portion CEP. The driving connection portion CDP may be a portion of the connecting wire CN connected to the transistor TR. In this embodiment, the driving connection portion CDP may penetrate the fifth insulating layer 50 and be electrically connected to the drain region DR of the semiconductor pattern SP through the drain electrode pattern W2. The emission connection portion CEP may be a portion of the connecting wire CN connected to the light emitting element ED. The emission connection portion CEP may be defined in an area exposed from the sixth insulating layer 60 and may be a portion to which the cathode CE is connected. Here, a tip portion TP may be defined in the emission connection portion CEP.

[0200] FIG. 11A is an enlarged cross-sectional view of a display panel according to an embodiment of the present invention, enlarging a region BA in FIG.

[0201] The light-emitting connection part CEP of the connecting wire CN will be described in more detail with reference to FIGS. 10 and 11A. As shown in FIGS. 10 and 11A, the connecting wire CN may have a three-layer structure. Specifically, the connecting wire CN may include a first layer L1, a second layer L2, and a third layer L3 sequentially stacked along the third direction DR3. The second layer L2 may include a different material from the first layer L1. The second layer L2 may also include a different material from the third layer L3. The second layer L2 may have a relatively thicker thickness than the first layer L1. The second layer L2 may also have a relatively thicker thickness than the third layer L3. The second layer L2 may include a highly conductive material. In one embodiment, the second layer L2 may include aluminum (Al).

[0202] Meanwhile, the first layer L1 may include a material having a lower etching rate than the second layer L2. That is, the second layer L2 may be composed of a material having a high etching selectivity relative to the first layer L1. In one embodiment, the first layer L1 may include titanium (Ti), and the second layer L2 may include aluminum (Al). In this case, the side surface L1_W of the first layer L1 may be defined outward from the side surface L2_W of the second layer L2. That is, the light emitting connection portion CEP of the connecting wire CN may have a shape in which the side surface L1_W of the first layer L1 protrudes outward from the side surface L2_W of the second layer L2. That is, the light emitting connection portion CEP of the connecting wire CN may have a shape in which the side surface L2_W of the second layer L2 is recessed inward from the side surface L1_W of the first layer L1.

[0203] In addition, the third layer L3 may include a material having a lower etching rate than the second layer L2. That is, the third layer L3 and the second layer L2 may be made of materials having a high etching selectivity relative to each other. In one embodiment, the third layer L3 may include titanium (Ti), and the second layer L2 may include aluminum (Al). In this case, the side surface L3_W of the third layer L3 may be defined outward from the side surface L2_W of the second layer L2. That is, the light emitting connection portion CEP of the connecting wire CN may have a shape in which the side surface L3_W of the third layer L3 protrudes outward from the side surface L2_W of the second layer L2. That is, the light emitting connection portion CEP of the connecting wire CN may have an undercut shape or an overhang structure, and a tip portion TP of the light emitting connection portion CEP may be defined by the protruding portion of the third layer L3 compared to the second layer L2.

[0204] The upper insulating layer UIL and the pixel defining layer PDL may expose at least a portion of the tip portion TP and at least a portion of the second side surface L2_W. Specifically, a first opening OP1 exposing one side of the connecting line CN may be defined in the upper insulating layer UIL, and a second opening OP2 overlapping the first opening OP1 may be defined in the pixel defining layer PDL. The planar area of ​​the second opening OP2 may be larger than the planar area of ​​the first opening OP1. However, the present invention is not limited thereto. As long as at least a portion of the tip portion TP and at least a portion of the second side surface L2_W can be exposed, the planar area (area in a plan view) of the second opening OP2 may be smaller than or equal to the planar area of ​​the first opening OP1.

[0205] An intermediate layer IML may be disposed on the pixel defining layer PDL. The intermediate layer IML may also be disposed on a portion of the upper insulating layer UIL exposed by the second opening OP2 of the pixel defining layer PDL. The intermediate layer IML may also be disposed on a portion of the connecting wire CN exposed by the first opening OP1 of the upper insulating layer UIL. As shown in FIG. 13A, the intermediate layer IML may include one end IN1 disposed along the upper surface of the fifth insulating layer 50 and the other end IN2 disposed along the upper surfaces of the connecting wire CN and the chip portion TP. That is, in cross section, the intermediate layer IML may have a shape that is partially disconnected from the chip portion TP in the region where the light emitting connection portion CEP is defined. However, in plan view, the intermediate layer IML may have an integral shape that is entirely connected within the region defined by the separator SPR (see FIG. 13A).

[0206] A cathode CE may be disposed on the intermediate layer IML. The cathode CE may also be disposed on a portion of the upper insulating layer UIL exposed by the second opening OP2 in the pixel defining layer PDL. The cathode CE may also be disposed on a portion of the connecting line CN exposed by the first opening OP1 in the upper insulating layer UIL. As shown in FIG. 11A, the cathode CE may include one end EN1 of the cathode CE disposed along the upper surface of the fifth insulating layer 50 and the other end EN2 disposed along the upper surfaces of the connecting line CN and the tip portion TP. That is, in cross section, the cathode CE may have a shape that is partially disconnected from the tip portion TP in the region where the light-emitting connection portion CEP is defined. However, in plan view, the cathode CE may have an integral shape that is entirely connected within the region defined by the separator SPR as a closed curve (see FIG. 13A).

[0207] Meanwhile, one end EN1 of the cathode CE may be disposed along the side surface of the second layer L2 and may contact the side surface L2_W of the second layer L2. Specifically, due to the difference in deposition angle between the cathode CE and the intermediate layer IML, the cathode CE may be formed to contact the side surface L2_W of the second layer L2 exposed from the intermediate layer IML by the tip portion TP. That is, the cathode CE may be connected to the connecting line CN without a separate patterning process for the intermediate layer IML, and therefore the light emitting element ED may be electrically connected to the transistor TR through the connecting line CN.

[0208] Furthermore, in this embodiment, the other end IN2 of the intermediate layer IML and the other end EN2 of the cathode CE are illustrated as covering the side L3_W of the third layer L3, but this is shown as an example, and at least a portion of the side L3_W of the third layer L3 may be exposed from the other end IN2 of the intermediate layer IML and / or the other end EN2 of the cathode CE.

[0209] The display panel DP according to this embodiment may include a separator SPR. The separator SPR may be disposed on a pixel definition layer PDL. In one embodiment, the cathode CE and the intermediate layer IML may be formed by common deposition on a plurality of pixels through an open mask. In this case, the cathode CE and the intermediate layer IML may be divided by the separator SPR. As described above, the separator SPR may have a closed line shape corresponding to each light-emitting portion, and therefore the cathode CE and the intermediate layer IML may have a divided shape for each light-emitting portion. In other words, the cathode CE and the intermediate layer IML may be electrically independent for each adjacent pixel.

[0210] FIG. 11B is an enlarged cross-sectional view of a display panel according to an embodiment of the present invention, enlarging the area BB in FIG.

[0211] The separator SPR will be described in more detail with reference to Figures 10 and 11B. As shown in Figure 11B, the separator SPR may have an inverted tapered shape. That is, the angle θ (hereinafter referred to as the taper angle) formed by the side surface SPR_W of the separator SPR with respect to the upper surface of the pixel defining layer PDL may be an obtuse angle. However, this is merely an example, and the taper angle θ may be set in various ways as long as the separator SPR can electrically disconnect the cathode CE for each pixel. Furthermore, the separator SPR may have a structure similar to that of the tip portion TP, and is not limited to any one embodiment.

[0212] In one embodiment, the separator SPR may include an insulating material, particularly an organic insulating material. The separator SPR may also include an inorganic insulating material, or may be composed of multiple layers of organic and inorganic insulating materials. Depending on the embodiment, the separator SPR may also include a conductive material. That is, as long as the separator SPR can electrically disconnect the cathode CE for each pixel, there is no particular limitation on the type of material.

[0213] A dummy layer UP may be disposed on the separator SPR. The dummy layer UP may include a first dummy layer UP1 disposed on the separator SPR and a second dummy layer UP2 disposed on the first dummy layer UP1. The first dummy layer UP1 may be formed in the same process as the intermediate layer IML and may include the same material as the intermediate layer UP1. The second dummy layer UP2 may be formed in the same process as the cathode CE and may include the same material as the intermediate layer UP1. That is, the first dummy layer UP1 and the second dummy layer UP2 may be formed simultaneously during the formation of the intermediate layer IML and the cathode CE. In another embodiment, the display panel DP may not include the dummy layer UP.

[0214] 11B, in one embodiment, the cathode CE includes a first end EN1a, and the second dummy layer UP2 includes a second end EN2a. The first end EN1a may be spaced apart from the separator SPR and positioned on the pixel defining layer PDL, and the second end EN2a may be spaced apart from the first end EN1a and positioned on the side surface SPR_W of the separator SPR. Although FIG. 11B illustrates the first end EN1a as being spaced apart from the side surface SPR_W of the separator SPR by a predetermined distance, the present invention is not limited thereto. The first end EN1a may also contact the side surface SPR_W of the separator SPR as long as it is electrically disconnected from the second end EN2a. Furthermore, even if the first end EN1a and the second end EN2a are connected without being distinguished from each other, the thickness of the portion formed along the side surface SPR_W of the separator SPR is thin, and if the electrical resistance is high, the cathode CE may be electrically disconnected between adjacent pixels, and the cathode CE may be considered to be divided by the separator SPR.

[0215] According to the present invention, the cathode CE and the intermediate layer IML can be divided into pixels by forming the cathode CE and the intermediate layer IML thinly or not formed on the side surface SPR_W of the separator SPR without a separate patterning process for the cathode CE and the intermediate layer IML. Furthermore, as long as the cathode CE and the intermediate layer IML can be electrically disconnected between adjacent pixels, the shape of the separator SPR can be variously modified and is not limited to any one embodiment.

[0216] Figure 12 is a cross-sectional view of a display panel according to an embodiment of the present invention. For ease of explanation, Figure 12 shows a cross-sectional view of a region corresponding to Figure 10. Hereinafter, the same components as those described in Figure 10 will be assigned the same reference numerals, and duplicated explanations will be omitted.

[0217] The display panel DP-1 illustrated in Fig. 12 may further include a capping pattern CPP compared to the display panel DP illustrated in Fig. 10. The capping pattern CPP may be disposed on the upper insulating layer UIL. The capping pattern CPP may also be disposed on a portion of the connecting wire CN exposed by the first opening OP1 in the upper insulating layer UIL. The capping pattern CPP may be disposed to overlap the connecting wire CN, specifically, the light emitting connection part CEP and / or the tip part TP.

[0218] 12, when viewed in cross section, the capping pattern CPP may have a shape that is partially disconnected from the tip portion TP in the region where the light emitting connection portion CEP is defined. However, when viewed in plan, the capping pattern CPP may have a shape that is entirely connected within the region defined by the separator SPR as a closed line (see FIG. 13A). Meanwhile, one end of the partially disconnected capping pattern CPP may contact a side surface of the second connecting wire layer L2, and the other end of the capping pattern CPP may be disposed on top of the third connecting wire layer L3 to cover the tip portion TP.

[0219] The capping pattern CPP may include a conductive material. Therefore, the cathode CE may be electrically connected to the connecting wire CN through the capping pattern CPP. That is, the capping pattern CPP may contact the side of the connecting wire second layer L2, and then the cathode CE may contact the capping pattern CPP, thereby electrically connecting them all. Because the capping pattern CPP is disposed relatively outward from the connecting wire second layer L2, the cathode CE may be electrically connected to the second layer L2 simply by being connected to the capping pattern CPP instead of the side of the second layer L2, which may make it easier to form a connection between the connecting wire CN and the cathode CE.

[0220] In addition, the capping pattern CPP may include a material having a relatively lower reactivity than the second connecting wiring layer L2. For example, the capping pattern CPP may include copper (Cu), silver (Ag), transparent conductive oxide, etc. The relatively lower reactivity of the capping pattern CPP protects the sides of the second connecting wiring layer L2, thereby preventing oxidation of the material included in the second layer L2. Furthermore, during the etching process for patterning the anode AE, it is possible to prevent the silver (Ag) component included in the anode AE ​​layer from being reduced and remaining as particles that cause defects.

[0221] In one embodiment, the capping pattern CPP may be formed through the same process as the anode AE ​​and may include the same material as the anode AE, but this is merely an example, and the capping pattern CPP may be formed through a different process than the anode AE ​​or may include other materials, and is not limited to any one embodiment.

[0222] Figures 13A to 13C are enlarged plan views of a portion of a display panel according to an embodiment. Figures 13A to 13C may correspond to enlarged plan views of the display panels DP and DP-1 according to the embodiments described above in Figures 10 to 12. Figure 13A illustrates an area in which a total of four light emitting units are arranged in two rows and two columns, and Figure 13B illustrates an enlarged view of a portion of Figure 13A. Figure 13C illustrates some components of Figure 13A in an exaggerated manner or omitted. The present invention will now be described with reference to Figures 13A to 13C.

[0223] Figure 13A shows two rows and two columns of light emitting units UT11, UT12, UT21, and UT22. The first row Rk light emitting unit includes light emitting units constituting the first row, first column light emitting unit UT11 and the first row, second column light emitting unit UT12, and the second row Rk+1 light emitting unit includes light emitting units constituting the second row, first column light emitting unit UT21 and the second row, second column light emitting unit UT22. Figure 13B shows the first row Rk light emitting unit. Figures 13A to 13C show a separator SPR, a plurality of light emitting units EP1, EP2, and EP3 arranged in an area partitioned by the separator SPR, connecting wires CN1, CN2, and CN3, anodes AE, and cathodes CE in the display panel configuration.

[0224] As described above, each of the light-emitting portions EP1, EP2, and EP3 may correspond to the light-emitting opening OP-PDL (see FIG. 10). That is, each of the light-emitting portions EP1, EP2, and EP3 is an area where light is emitted by a light-emitting element, and may correspond to a unit that forms an image displayed on the display panel DP (see FIG. 10). More specifically, each of the light-emitting portions EP1, EP2, and EP3 may correspond to an area defined by the light-emitting opening OP-PDL (see FIG. 10), particularly an area defined by the bottom surface of the light-emitting opening OP-PDL.

[0225] The light-emitting units EP1, EP2, and EP3 may include a first light-emitting unit EP1, a second light-emitting unit EP2, and a third light-emitting unit EP3. The first light-emitting unit EP1, the second light-emitting unit EP2, and the third light-emitting unit EP3 may emit a first color light, a second color light, and a third color light, respectively, and the first, second, and third color lights may be lights of different colors. For example, the first light-emitting unit EP1 may emit red light, the second light-emitting unit EP2 may emit green light, and the third light-emitting unit EP3 may emit blue light, but the color combinations are not limited thereto. Furthermore, at least two of the light-emitting units EP1, EP2, and EP3 may emit light of the same color. For example, the first, second, and third light-emitting units EP1, EP2, and EP3 may all emit blue light or all emit white light.

[0226] Meanwhile, the third light-emitting unit EP3, which emits a third color light among the light-emitting units EP1, EP2, and EP3, may include two sub-light-emitting units EP31 and EP32 spaced apart from each other in the second direction DR2. However, this is merely an example, and the third light-emitting unit EP3 may be provided in a single pattern having an integrated shape like the other light-emitting units EP1 and EP2, and at least one of the other light-emitting units EP1 and EP2 may include a plurality of spaced-apart sub-light-emitting units, and is not limited to any one embodiment.

[0227] The light-emitting portion in the first row Rk includes light-emitting portions EP1, EP2, and EP3 that constitute the light-emitting unit UT11 in the first row and first column and the light-emitting unit UT12 in the first row and second column, and the light-emitting portion in the second row Rk+1 includes light-emitting portions EP1, EP2, and EP3 that constitute the light-emitting unit UT21 in the second row and first column and the light-emitting unit UT22 in the second row and second column. A portion of the light-emitting portions in the first row Rk and a portion of the light-emitting portions in the second row Rk+1 may have symmetrical shapes. For example, the first light-emitting unit EP1 and the second light-emitting unit EP2 of the light-emitting unit UT21 in the second row and the first column and the first light-emitting unit EP1 and the second light-emitting unit EP2 of the light-emitting unit UT11 in the first row and the first column may have a shape and an arrangement that is line-symmetrical with respect to an axis along the second direction DR2, and the third light-emitting unit EP3 of the light-emitting unit UT21 in the second row and the first column and the third light-emitting unit EP3 of the light-emitting unit UT11 in the first row and the first column may have a shape and an arrangement that is line-symmetrical with respect to an axis aligned in the first direction DR1, but this is merely an example and is not limiting.

[0228] The light emitting unit UT11 in the first row and first column will now be described. For ease of explanation, FIG. 13B illustrates a plurality of cathodes CE_1, CE_2, and CE_3, a plurality of pixel driving units PXCR, PXCG, and PXCB, and a plurality of connecting wires CN1, CN2, and CN3. The cathodes CE_1, CE_2, and CE_3 may be electrically disconnected by separators SPR. In this embodiment, one light emitting unit UT may include three light emitting parts EP1, EP2, and EP3. Therefore, the light emitting unit UT may include three cathodes CE_1, CE_2, and CE_3 (hereinafter referred to as first to third cathodes), three pixel driving units PXCR, PXCG, and PXCB, and three connecting wires CN1, CN2, and CN3. However, this is merely an example, and the number and arrangement of the light emitting units UT may be variously designed and are not limited to any one embodiment.

[0229] The first to third pixel driving units PXCR, PXCG, and PXCB are electrically connected to the light emitting elements constituting the first to third light emitting units EP1, EP2, and EP3, respectively. In this specification, "connected" refers to not only being connected by direct physical contact but also being electrically connected.

[0230] 13B, each of the regions in which the pixel driving units PXCR, PXCG, and PXCB are partitioned (defined) on a plane may correspond to a unit in which transistors and capacitors constituting a pixel PX (see FIG. 3A) for driving a light emitting element of the pixel are repeatedly arranged. For example, each of the first to third pixel driving units PXCR, PXCG, and PXCB may include first to seventh transistors T1-T7, a first capacitor Cst, and a second capacitor Cth shown in FIG.

[0231] The first to third pixel driving units PXCR, PXCG, and PXCB may be sequentially arranged along the first direction DR1. Meanwhile, the arrangement positions of the first to third pixel driving units PXCR, PXCG, and PXCB may be designed independently, regardless of the positions and shapes of the first to third light emitting units EP1, EP2, and EP3.

[0232] For example, the first to third pixel driving units PXCR, PXCG, and PXCB may be arranged in a region defined by the separator SPR, i.e., a position different from that of the first to third cathodes CE_1, CE_2, and CE_3, or may be designed to have a shape and area different from that of the first to third cathodes CE_1, CE_2, and CE_3. Alternatively, the first to third pixel driving units PXCR, PXCG, and PXCB may be arranged to overlap the positions of the first to third light emitting units EP1, EP2, and EP3, respectively, and may be designed to have a shape having an area similar to that of the region defined by the separator SPR, e.g., the first to third cathodes CE_1, CE_2, and CE_3.

[0233] In this embodiment, the first to third pixel driving units PXCR, PXCG, and PXCB are each illustrated as a rectangle, the first to third light emitting units EP1, EP2, and EP3 are each arranged in a different shape with a smaller area, and the first to third cathodes CE_1, CE_2, and CE_3 are arranged at positions overlapping the first to third light emitting units EP1, EP2, and EP3 and are illustrated as having an irregular shape.

[0234] 13B, the first pixel driver PXCR may be arranged to partially overlap the first light emitter EP1, the second light emitter EP2, and other adjacent light emitters. The second pixel driver PXCG may be arranged to overlap the first light emitter EP1, the second light emitter EP2, and the third light emitter EP3. The third pixel driver PXCB may be arranged to overlap the third light emitter EP3. However, this is merely an example, and the positions and arrangements of the first to third pixel drivers PXCR, PXCG, and PXCB may be designed in various shapes and arrangements independent of the light emitters EP1, EP2, and EP3, and are not limited to any one embodiment.

[0235] A plurality of connection wires CN may be provided and spaced apart from each other. Each connection wire CN may electrically connect one of the pixel drivers PXCR, PXCG, and PXCB to a corresponding light emitting element. Specifically, the connection wire CN may correspond to a first node N1 (see FIG. 2) where the light emitting element ED (see FIG. 10) is connected to the fifth transistor T5 (see FIG. 2).

[0236] The connecting wire CN may include a first connecting portion (or a light emitting connecting portion CEP) and a second connecting portion (or a driving connecting portion CDP). The light emitting connecting portion CEP may be provided on one side of the connecting wire CN, and the driving connecting portion CDP may be provided on the other side of the connecting wire CN.

[0237] The driving connection part CDP may be a part of the connecting wire CN that is connected to the transistor TR. In this embodiment, the driving connection part CDP may be connected to one electrode of the transistor TR. Specifically, the driving connection part CDP may be connected to a first electrode of the fifth transistor T5 shown in FIG. 2. Therefore, the position of the driving connection part CDP may correspond to the position of the transistor TR (see FIG. 10) that is physically connected to the connecting wire CN. The emission connection part CEP may be a part of the connecting wire CN that is connected to the light emitting element. In this embodiment, the emission connection part CEP may be connected to the cathode CE (see FIG. 10) of the light emitting element.

[0238] The light emitting unit UT may include first to third connecting wires CN1, CN2, and CN3. The first connecting wire CN1 connects the light emitting element forming the first light emitting portion EP1 to the first pixel driving circuit PXCR, the second connecting wire CN2 connects the light emitting element forming the second light emitting portion EP2 to the second pixel driving circuit PXCG, and the third connecting wire CN3 connects the light emitting element forming the third light emitting portion EP3 to the third pixel driving circuit PXCB.

[0239] Specifically, the first to third connecting wires CN1, CN2, and CN3 may connect the first to third cathodes CE_1, CE_2, and CE_3 to the first to third pixel driving units PXCR, PXCG, and PXCB, respectively. The first connecting wire CN1 may include a first driving connection part CDP1 connected to the first pixel driving unit PXCR and a first light-emitting connection part CEP1 connected to the first cathode CE_1. The second connecting wire CN2 may include a second driving connection part CDP2 connected to the second pixel driving unit PXCG and a second light-emitting connection part CEP2 connected to the second cathode CE_2. The third connecting wire CN3 may include a third driving connection part CDP3 connected to the third pixel driving unit PXCB and a third light-emitting connection part CEP3 connected to the third cathode CE_3.

[0240] The first to third driving connection parts CDP1, CDP2, and CDP3 may be aligned along the first direction DR1. As described above, the first to third driving connection parts CDP1, CDP2, and CDP3 may correspond to the positions of the transistors constituting the first to third pixel driving parts PXCR, PXCG, and PXCB, respectively. According to the present invention, the shape, position, and arrangement of the pixel driving parts of all pixels can be easily configured and designed regardless of the shape, size, or emission color of the light emitting part.

[0241] In this embodiment, the first to third light emitting connection parts CEP1, CEP2, and CEP3 may be disposed at positions that do not overlap with the light emitting parts EP1, EP2, and EP3 in a plan view. As will be described later, each of the light emitting connection parts CEP1, CEP2, and CEP3 of the connecting wiring CN is a portion to which the light emitting element ED (see FIG. 10) is connected and a portion where the tip part TP (see FIG. 10) is defined, and therefore may be disposed at a position that does not overlap with the light emitting opening OP-PDL (see FIG. 10). That is, the light emitting connection parts CEP1, CEP2, and CEP3 can be arranged at positions spaced apart from the light emitting parts EP1, EP2, and EP3 in each of the cathodes CE_1, CE_2, and CE_3, and the cathodes CE_1, CE_2, and CE_3 can include a portion that protrudes from the light emitting parts EP1, EP2, and EP3 on a plane in order to connect to the connecting wirings CN1, CN2, and CN3 at the positions where the light emitting connection parts CEP1, CEP2, and CEP3 are arranged.

[0242] For example, the first cathode CE_1 may include a protrusion shaped to protrude from the first light emitting portion EP1 at a position not overlapping with the first light emitting portion EP1 in order to connect to the first connecting wiring CN1 at the position where the first light emitting connection portion CEP1 is disposed, and the first light emitting connection portion CEP1 may be provided on the protrusion.

[0243] In addition, the first pixel driver PXCR, particularly the first driver connection part CDP1 where the first connecting line CN1 is connected to the transistor TR (see FIG. 10), may be defined at a position not overlapping the first light emitting part EP1 in a plan view. According to this embodiment, the first connecting line CN1 is disposed in the first light emitting part EP1, so that the first cathode CE_1 and the first pixel driver PXCR, which are spaced apart from each other, can be easily connected.

[0244] Meanwhile, the third pixel driving unit PXCB, particularly the third driving connection unit CDP3 where the third connecting line CN3 is connected to the transistor TR, may be defined at a position not overlapping the third emission connection unit CEP3 in a plan view and may be disposed at a position overlapping the third emission unit EP3. According to this embodiment, since the third cathode CE_3 and the third pixel driving unit PXCB are connected through the third connecting line CN3, restrictions imposed by the position and shape of the third emission unit EP3 are reduced in designing the third pixel driving unit PXCB, and design freedom may be improved.

[0245] 13A again, the light emitting unit in the second row Rk+1 may be configured such that the light emitting units UT11 and UT12 in the first row have a shape and arrangement that are symmetrical with respect to an axis along the first direction DR1 or the second direction DR2. In this case, depending on the shape and arrangement of the light emitting units UT11 and UT12 in the first row, the light emitting units UT21 and UT22 in the second row may be configured such that the light emitting units UT11 and UT12 in the first row are substantially shifted in the first direction DR1 or the second direction DR2. That is, the light emitting unit UT21 in the second row and first column may have the same shape as the light emitting unit UT12 in the first row and second column, and the light emitting unit UT22 in the second row and second column may have the same shape as the light emitting unit UT11 in the first row and first column.

[0246] Therefore, the shape and arrangement of the connecting wires CN-c arranged in the second row, first column light emitting unit UT21 may be the same as the connecting wires CN1, CN2, and CN3 arranged in the first row, second column light emitting unit UT12. Similarly, the shape and arrangement of the connecting wires CN-d arranged in the second row, second column light emitting unit UT22 may be the same as the connecting wires CN1, CN2, and CN3 arranged in the first row, first column light emitting unit UT11.

[0247] 13C, the anode AE ​​of a light emitting device according to an embodiment of the present invention may be provided in common to the plurality of light emitting portions EP1, EP2, and EP3. That is, the anode AE ​​may be formed as a single layer that is integrated across the entire display area DA, and therefore the anode AE ​​layer may be disposed overlapping the separator SPR. Alternatively, the anodes AE of the light emitting devices may be formed as independent conductive patterns that are spaced apart from each other and electrically connected to each other through other conductive layers, and therefore the anode AE ​​patterns may be disposed overlapping the separator SPR.

[0248] As described above, the anode AE ​​may receive the first driving voltage ELVDD (see FIG. 2) to provide a common voltage to all the light emitting units. The anode AE ​​may be connected to the first driving voltage line VL1 (see FIG. 2) that provides the first driving voltage ELVDD (see FIG. 2) in the non-display area NDA, or may be connected to the first driving voltage line VL1 (see FIG. 2) in the display area DA, and is not limited to any one embodiment. In the latter case, the first driving voltage line VL1 may be disposed in the non-display area NDA (see FIG. 1), and the anode AE ​​may have a shape that extends to the non-display area NDA (see FIG. 1).

[0249] 10 and 12, the anode AE ​​is illustrated as overlapping the light emitting opening OP-PDL but not overlapping the separator SPR, but as illustrated in Fig. 13C, the anode AE ​​of the light emitting device may have a one-piece shape and a mesh or lattice shape with openings defined in some regions. That is, as long as the same first driving voltage ELVDD (see Fig. 2) can be applied to each anode AE ​​of the plurality of light emitting devices, the shape of the anode AE ​​may be various and is not limited to any one embodiment.

[0250] Meanwhile, according to this embodiment, the anode AE ​​may have a plurality of openings OP-AE defined therein, and the openings OP-AE may penetrate the anode AE ​​layer. The openings OP-AE in the anode AE ​​layer may be disposed at positions not overlapping the light-emitting portion EP, and may be generally disposed at positions overlapping the separator SPR. The openings facilitate the discharge of gas generated from organic layers disposed below the anode AE, such as the upper insulating layer UIL (see FIG. 10). Therefore, during the manufacturing process of the display panel DP, gas generated from the organic layers disposed below the light-emitting element ED can be sufficiently discharged, and the amount of gas discharged from the organic layers after manufacturing can be reduced, thereby slowing down the rate at which the light-emitting element ED deteriorates.

[0251] According to this embodiment, by including a connecting wire between the light emitting element ED and the pixel driver, the light emitting element ED can be easily connected to the pixel driver by changing only the shape of the cathode CE without changing the arrangement or shape of the light emitting portion, which improves the design freedom for the arrangement of the pixel driver and easily increases the area of ​​the light emitting portion or the resolution of the display panel DP.

[0252] Although the present invention has been described above with reference to preferred embodiments, it will be understood by those skilled in the art or those with ordinary knowledge in the art that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims.

[0253] According to a preferred specific embodiment, it is as follows:

[0254] The background and issues of this case are as follows (i) to (v).

[0255] (i) Organic light-emitting display panels, which have organic light-emitting diodes (OLEDs) arranged in a matrix, are widely used in smartphones, tablet PCs, smartwatches, and other devices due to their excellent properties such as light weight, thinness, and high luminous efficiency.

[0256] (ii) However, organic light-emitting devices (OLEDs) have the problem of being easily deteriorated by oxygen, moisture, etc. To prevent such deterioration, organic light-emitting devices with an inverted structure (inverted OLEDs) are also widely used. "Development of Air-Stable Inverted Organic EL Devices" NHK STRL R&D, May 2014, Report 02 https: / / www.nhk.or.jp / strl / publica / rd / 145 / 6.html

[0257] (iii) On the other hand, as the organic light emitting device (OLED) gradually deteriorates, the hue of the emitted light may become misaligned, resulting in a decrease in display quality.

[0258] (iv) As a result of extensive research into the causes of such degradation in display quality, the present inventors have come to realize that fluctuations in the body-source voltage (Vbs) of the drive transistor (T1) may occur due to changes in the anode potential of the organic light-emitting element (OLED) accompanying degradation of the organic light-emitting element (OLED).

[0259] (v) As shown in FIG. 5 of the present application, the threshold voltage (Vth) of the driving transistor (T1) may shift as the body-source voltage (Vbs) shifts.

[0260] In a specific embodiment of the present application, at least one of the following A1 to A3 or A1 to A5 is particularly preferred.

[0261] A1: The potential of the anode (AE) of the organic light emitting element (OLED) and the gate (G) of the driving transistor (T1) are initialized together (FIGS. 4A and 9A).

[0262] A1-1 At this time, the first initialization transistor (T3) is turned on, and the first initialization voltage (VREF) is applied to the gate (G) of the driving transistor (T1), or to the other electrode (second node N12) of the capacitor (Cst) whose one electrode is connected to the gate electrode (G) of the driving transistor (T1).

[0263] A1-2 At the same time, the second initialization transistor (T4) is turned on to apply the second initialization voltage (Vcint) to the anode (AE) of the organic light emitting element (OLED), and the first emission control transistor (T5) and the second initialization transistor (T7) are turned on. The first light emitting control transistor T5 connects the drain electrode D of the driving transistor T1 and the anode AE ​​of the organic light emitting element OLED.

[0264] A2 Next, with the first initialization transistor (T3) and the second initialization transistor (T7) turned on, the first light-emitting control transistor (T5) is turned off to initialize the lower gate electrode (BG) or gate electrode (G) of the driving transistor (T1), and at the same time, the gate electrode (G) or lower gate electrode (BG) of the driving transistor (T1) is also initialized. (Figures 4B and 9B of the present application)

[0265] A2-1 For this purpose, the gate electrode (G) or the lower gate electrode (BG) of the driving transistor (T1) and the second initialization transistor (T7) are diode-connected. A2-2: A second drive voltage (ELVSS) is applied to the gate electrode (G) or the bottom gate electrode (BG) of the drive transistor (T1) by diode connection.

[0266] A2-3 When the gate electrode (G) of the driving transistor (T1) is connected in a diode configuration, a separate compensation voltage (Vcomp) is constantly applied to the bottom gate electrode (BG). A2-4 Furthermore, the second node (N12) is connected to the power supply of the compensation voltage (Vcomp) via a second node holding capacitor (Chold).

[0267] A3 The write transistor (T2) is turned on to write a data signal to the gate electrode (G) of the drive transistor (T1) or the other electrode (second node N12) of the capacitor (Cst) connected thereto. (Figures 4C and 9C of the present application)

[0268] A4: Only the second initialization transistor (T4) is turned on to apply the second initialization voltage (Vcint) to the anode (AE) of the organic light emitting device (OLED). (Fig. 4D and Fig. 9D of the present application)

[0269] A5: Only the second initialization transistor (T4) is turned on to apply the second initialization voltage (Vcint) to the anode (AE) of the organic light emitting element (OLED). (Figs. 4E and 9E of the present application) [Explanation of symbols]

[0270] DD electronic device DP display panel PX pixels ED light emitting element T1-T7 First to seventh transistors Cst 1st capacitor Chold Second Capacitor

Claims

1. a light emitting device including an anode connected to a first driving voltage line and a cathode connected to a first node; a first transistor including a first electrode, a second electrode, a gate electrode, and a bottom gate electrode; a second transistor connected between a data line and the gate electrode of the first transistor; a fifth transistor connected between the first node and the first electrode of the first transistor; a sixth transistor connected between the second electrode of the first transistor and a second driving voltage line; a seventh transistor connected between the first electrode and the bottom gate electrode of the first transistor; a first capacitor connected between the gate electrode and the second electrode of the first transistor; a second capacitor connected between the bottom gate electrode and the second electrode of the first transistor;

2. the second transistor includes a gate electrode that receives a first scan signal; the fifth transistor includes a gate electrode that receives a first light-emitting signal; the sixth transistor includes a gate electrode that receives a second light-emitting signal; The pixel of claim 1 , wherein the seventh transistor includes a gate electrode that receives a second scan signal.

3. a third transistor connected between a third driving voltage line receiving a first initialization voltage and the gate electrode of the first transistor; The pixel of claim 1 , further comprising: a fourth transistor coupled between a fourth driving voltage line receiving a second initialization voltage and the first node.

4. The pixel of claim 3 , wherein the second initialization voltage has a voltage level higher than the first initialization voltage.

5. The pixel of claim 3 , wherein the second initialization voltage has a voltage level higher than the second driving voltage received on the second driving voltage line.

6. the third transistor includes a gate electrode that receives the second scan signal; The pixel of claim 3 , wherein the fourth transistor includes a gate electrode that receives a third scan signal.

7. The pixel of claim 3 , wherein the third transistor, the fourth transistor, the fifth transistor, and the seventh transistor are turned on during an initialization period.

8. The pixel of claim 7 , wherein a threshold voltage of the first transistor is negatively shifted during the initialization period.

9. The pixel of claim 8 , wherein the first transistor, the third transistor, the sixth transistor, and the seventh transistor are turned on during the compensation period.

10. The pixel of claim 9 , wherein the threshold voltage of the first transistor is set to 0V during the compensation period.

11. The pixel of claim 3 , wherein the second transistor and the sixth transistor are turned on during a write period.

12. The pixel of claim 3 , wherein the fourth transistor is turned on during a light emitting element initialization period.

13. a light emitting device including an anode connected to a first driving voltage line and a cathode connected to a first node; a first transistor including a first electrode, a second electrode, a gate electrode, and a bottom gate electrode; a second transistor coupled between the data line and a second node; a third transistor connected between the second node and a third driving voltage line; a fourth transistor connected between a fourth driving voltage line and the first node; a fifth transistor connected between the first node and the first electrode of the first transistor; a sixth transistor connected between the second electrode of the first transistor and a second driving voltage line; a seventh transistor connected between the first electrode and the gate electrode of the first transistor; a first capacitor connected between the gate electrode of the first transistor and the second node; a second capacitor coupled between a fifth driving voltage line and the second node;

14. the second transistor includes a gate electrode that receives a first scan signal; each of the third transistor and the seventh transistor includes a gate electrode receiving a third scan signal; the fourth transistor includes a gate electrode that receives a second scan signal; the fifth transistor includes a gate electrode that receives a first light-emitting signal; The pixel of claim 13 , wherein the sixth transistor comprises a gate electrode that receives a second light-emitting signal.

15. The pixel of claim 13 , wherein the third transistor, the fourth transistor, the fifth transistor, and the seventh transistor are turned on during an initialization period.

16. The pixel of claim 15 , wherein the first transistor, the third transistor, the sixth transistor, and the seventh transistor are turned on during a compensation period.

17. The pixel of claim 16 , wherein the initialization period and the compensation period are alternately repeated twice.

18. The pixel of claim 13 , wherein the second transistor is turned on during a write interval.

19. The pixel of claim 13 , wherein the fourth transistor is turned on during a light emitting element initialization period.

20. a display panel including pixels; a data driving circuit for providing a data signal to the pixel; The pixel is a light emitting device including an anode connected to a first driving voltage line and a cathode connected to a first node; a first transistor including a first electrode, a second electrode, a gate electrode, and a bottom gate electrode; a second transistor connected between a data line transmitting the data signal and the gate electrode of the first transistor; a fifth transistor connected between the first node and the first electrode of the first transistor; a sixth transistor connected between the second electrode of the first transistor and a second driving voltage line; a seventh transistor connected between the first electrode and the bottom gate electrode of the first transistor; a first capacitor connected between the gate electrode and the second electrode of the first transistor; a second capacitor coupled between the bottom gate electrode and the second electrode of the first transistor.

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