Display device

Abstract

To provide a display device capable of suppressing deterioration in reliability.SOLUTION: According to an embodiment, a display device includes a substrate, an inorganic insulating layer disposed over a display region and a peripheral region outside the display region above the substrate, an organic insulating layer disposed on the inorganic insulating layer, and a rib layer disposed above the organic insulating layer and formed of an inorganic material. A lower electrode having a peripheral edge portion covered with the rib layer, an organic layer including a light-emitting layer disposed on the lower electrode, an upper electrode covering the organic layer, a first partition wall having a first lower portion disposed on the rib layer in the display region and a first upper portion protruding from a side surface of the first lower portion, and a base having identification information and disposed between the inorganic insulating layer and the organic insulating layer in the peripheral region, the rib layer includes a first opening overlapping the pedestal in a plan view in the peripheral region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have come into practical use. Technology to prevent deterioration in the reliability of such display devices is needed. Summary of the Invention [Problem to be solved by the invention]

[0003] An object of the present invention is to provide a display device capable of suppressing a decrease in reliability. [Means for solving the problem]

[0004] According to one embodiment, a display device includes a substrate, an inorganic insulating layer arranged above the substrate, spanning a display area for displaying an image and a peripheral area outside the display area, an organic insulating layer arranged on the inorganic insulating layer, a rib layer arranged above the organic insulating layer and made of an inorganic material, a lower electrode arranged on the organic insulating layer in the display area and having a peripheral portion covered by the rib layer, an organic layer including a light-emitting layer arranged on the lower electrode, an upper electrode covering the organic layer, a first partition having, in the display area, a first lower portion arranged on the rib layer and a first upper portion protruding from a side of the first lower portion, and a base arranged between the inorganic insulating layer and the organic insulating layer in the peripheral area and having identification information, wherein the rib layer has a first opening in the peripheral area that overlaps with the base in a planar view.

[0005] According to one embodiment, a display device includes a substrate, an inorganic insulating layer arranged above the substrate, spanning a display area for displaying an image and a peripheral area outside the display area, an organic insulating layer arranged on the inorganic insulating layer, a rib layer arranged above the organic insulating layer and formed of an inorganic material, a lower electrode arranged on the organic insulating layer in the display area and having a peripheral portion covered by the rib layer, an organic layer including a light-emitting layer arranged on the lower electrode, an upper electrode covering the organic layer, a first partition having a first lower portion arranged on the rib layer in the display area and a first upper portion protruding from a side of the first lower portion, and a protective layer arranged above the rib layer in the peripheral area and having identification information. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device. [Figure 2] FIG. 2 is a diagram showing an example of a layout of sub-pixels. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line 3-3 in FIG. [Figure 4] FIG. 4 is a cross-sectional view showing an example of the configuration of the display device taken along line 4-4 in FIG. [Figure 5] FIG. 5 is a plan view showing an example of the configuration of the peripheral area. [Figure 6] FIG. 6 is a schematic cross-sectional view of the display device taken along line 6-6 in FIG. [Figure 7A] FIG. 7A is a schematic cross-sectional view showing a manufacturing process of a display device. [Figure 7B] FIG. 7B is a schematic cross-sectional view showing a manufacturing process of the display device. [Figure 7C] FIG. 7C is a schematic cross-sectional view showing a manufacturing process of the display device. [Figure 7D] FIG. 7D is a schematic cross-sectional view showing a manufacturing process of the display device. [Figure 7E] FIG. 7E is a schematic cross-sectional view showing a manufacturing process of the display device. [Figure 7F]FIG. 7F is a schematic cross-sectional view showing a manufacturing process of the display device. [Figure 7G] FIG. 7G is a schematic cross-sectional view showing a manufacturing process of the display device. [Figure 7H] FIG. 7H is a schematic cross-sectional view showing a manufacturing process of the display device. [Figure 8A] FIG. 8A is a schematic cross-sectional view showing a manufacturing process of a display device. [Figure 8B] FIG. 8B is a schematic cross-sectional view showing a manufacturing process of the display device. [Figure 8C] FIG. 8C is a schematic cross-sectional view showing a manufacturing process of the display device. [Figure 8D] FIG. 8D is a schematic cross-sectional view showing a manufacturing process of the display device. [Figure 8E] FIG. 8E is a schematic cross-sectional view showing a manufacturing process of the display device. [Figure 8F] FIG. 8F is a schematic cross-sectional view showing a manufacturing process of the display device. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a manufacturing process of a display device. [Figure 10] FIG. 10 is a cross-sectional view showing a display device of a comparative example. [Figure 11] FIG. 11 is a plan view showing another example of the configuration of the peripheral region shown in FIG. [Figure 12] FIG. 12 is a schematic cross-sectional view of the display device taken along line 12-12 in FIG. [Figure 13] FIG. 13 is a cross-sectional view showing another example of the configuration of the display device shown in FIG. [Figure 14] FIG. 14 is a plan view showing an example of the configuration of the peripheral area of ​​the display device shown in FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view of the display device taken along line 15-15 in FIG. [Figure 16] FIG. 16 is a cross-sectional view showing another example of the configuration of the display device shown in FIG. [Figure 17] FIG. 17 is a diagram showing an example of the configuration of the peripheral area of ​​the display device shown in FIG. [Figure 18]FIG. 18 is a schematic cross-sectional view of the display device taken along line 18-18 in FIG. [Figure 19] FIG. 19 is a diagram showing another example of the configuration of the peripheral area shown in FIG. [Figure 20] FIG. 20 is a schematic cross-sectional view of the display device taken along line 20-20 in FIG. [Figure 21] FIG. 21 is a cross-sectional view showing another example of the configuration of the peripheral region shown in FIG. [Figure 22] FIG. 22 is a schematic cross-sectional view of the display device taken along line 22-22 in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0007] An embodiment will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0008] In the drawings, mutually perpendicular X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the first direction X, the direction along the Y axis is referred to as the second direction Y, and the direction along the Z axis is referred to as the third direction Z. Viewing various elements parallel to the third direction Z is referred to as a planar view.

[0009] The display device according to this embodiment is an organic electroluminescence display device having organic light-emitting diodes (OLEDs) as display elements, and can be installed in televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and the like.

[0010] FIG. 1 is a diagram showing an example of the configuration of a display device DSP.

[0011] The display device DSP includes a display panel PNL having a display area DA for displaying an image and a peripheral area SA outside the display area DA, on an insulating substrate 10. The substrate 10 may be made of glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to rectangular, and may be other shapes such as square, circle, or ellipse.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes a plurality of subpixels SP. In one example, the pixel PX includes a first color subpixel SP1, a second color subpixel SP2, and a third color subpixel SP3. The first color, second color, and third color are different from each other. Note that the pixel PX may include subpixels SP of another color, such as white, in addition to the subpixels SP1, SP2, and SP3, or instead of any of the subpixels SP1, SP2, and SP3.

[0014] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0015] The gate electrode of the pixel switch 2 is connected to the scanning line GL. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the anode of the display element DE.

[0016] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0017] The display element DE is an organic light-emitting diode (OLED) as a light-emitting element, and may be called an organic EL element.

[0018] The peripheral area SA has a plurality of terminals TE arranged in one direction. In the illustrated example, the plurality of terminals TE are arranged along the first direction X and each of the terminals TE extends in the second direction Y, but this is not limiting. Such a plurality of terminals TE are electrically connected to, for example, a flexible printed circuit board or an IC chip.

[0019] The peripheral area SA further includes a base 114 having identification information 200 of the display device DSP. In the illustrated example, the multiple terminals TE and the base 114 are aligned along the first direction X. The identification information 200 is information necessary for product management, such as the product's serial number or lot number. The identification information 200 is formed, for example, as a two-dimensional code, and the information can be obtained by reading the identification information 200 with a scanner or the like.

[0020] FIG. 2 is a diagram showing an example of the layout of the subpixels SP1, SP2, and SP3.

[0021] In the illustrated example, the subpixels SP2 and SP3 are aligned in the second direction Y. The subpixels SP1 and SP2 are aligned in the first direction X, and the subpixels SP1 and SP3 are aligned in the first direction X.

[0022] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with a column in which the subpixels SP2 and the subpixels SP3 are alternately arranged in the second direction Y, and a column in which multiple subpixels SP1 are arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0023] The layout of the subpixels SP1, SP2, and SP3 is not limited to the example in Fig. 2. As another example, the subpixels SP1, SP2, and SP3 in each pixel PX may be arranged in order in the first direction X.

[0024] In the display area DA, a rib layer 5 and partition walls 6 are arranged. The rib layer 5 has openings AP11, AP12, and AP13 in the subpixels SP1, SP2, and SP3, respectively.

[0025] The partition wall 6 overlaps with the rib layer 5 in a plan view. The partition wall 6 is formed in a lattice shape surrounding the openings AP11, AP12, and AP13. It can also be said that the partition wall 6 has openings in the subpixels SP1, SP2, and SP3, similar to the rib layer 5. The partition wall 6 is conductive and electrically connected to the terminal TE of the common potential among the multiple terminals TE shown in FIG. 1 .

[0026] The subpixels SP1, SP2, and SP3 include display elements DE1, DE2, and DE3, respectively, as the display element DE.

[0027] The display element DE1 of the subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each of which overlaps with the opening AP11. The peripheral portion of the lower electrode LE1 is covered with a rib layer 5. The lower electrode LE1, the organic layer OR1, and the upper electrode UE1 are surrounded by a partition wall 6 in a planar view. The peripheral portions of the organic layer OR1 and the upper electrode UE1 overlap with the rib layer 5 in a planar view. The organic layer OR1 includes, for example, a light-emitting layer that emits light in the blue wavelength range.

[0028] The display element DE2 of the subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each of which overlaps with the opening AP12. The peripheral portion of the lower electrode LE2 is covered with a rib layer 5. The lower electrode LE2, the organic layer OR2, and the upper electrode UE2 are surrounded by a partition wall 6 in a planar view. The peripheral portions of the organic layer OR2 and the upper electrode UE2 overlap with the rib layer 5 in a planar view. The organic layer OR2 includes a light-emitting layer that emits light in, for example, a green wavelength region.

[0029] The display element DE3 of the subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each of which overlaps with the opening AP13. The peripheral portion of the lower electrode LE3 is covered with a rib layer 5. The lower electrode LE3, the organic layer OR3, and the upper electrode UE3 are surrounded by a partition wall 6 in a planar view. The peripheral portions of the organic layer OR3 and the upper electrode UE3 overlap the rib layer 5 in a planar view. The organic layer OR3 includes, for example, a light-emitting layer that emits light in the red wavelength range.

[0030] In the illustrated example, the outlines of the lower electrodes LE1, LE2, and LE3 are indicated by dotted lines, and the outlines of the organic layers OR1, OR2, and OR3 and the upper electrodes UE1, UE2, and UE3 are indicated by dashed-dotted lines. Note that the outlines of the illustrated lower electrodes, organic layers, and upper electrodes do not necessarily reflect their exact shapes.

[0031] The lower electrodes LE1, LE2, and LE3 correspond to, for example, the anodes of the display elements DE. The upper electrodes UE1, UE2, and UE3 correspond to the cathodes of the display elements DE or a common electrode, and are in contact with the partition walls 6.

[0032] The lower electrode LE1 is electrically connected to the pixel circuit 1 of the subpixel SP1. The lower electrode LE2 is electrically connected to the pixel circuit 1 of the subpixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the subpixel SP3.

[0033] In the illustrated example, the areas of the openings AP11, AP12, and AP13 are different from one another. The area of ​​the opening AP11 is larger than the area of ​​the opening AP12, and the area of ​​the opening AP12 is larger than the area of ​​the opening AP13. In other words, the area of ​​the lower electrode LE1 exposed from the opening AP11 is larger than the area of ​​the lower electrode LE2 exposed from the opening AP12, and the area of ​​the lower electrode LE2 exposed from the opening AP12 is larger than the area of ​​the lower electrode LE3 exposed from the opening AP13.

[0034] FIG. 3 is a schematic cross-sectional view of the display device DSP taken along line 3-3 in FIG.

[0035] The substrate 10 has a main surface (lower surface) 10A and a main surface (upper surface) 10B opposite the main surface 10A. The main surfaces 10A and 10B are surfaces that are approximately parallel to the XY plane. The circuit layer 11 is disposed on the main surface 10B of the substrate 10. The circuit layer 11 includes various circuits such as the pixel circuit 1 shown in FIG. 1 and various wirings such as scanning lines GL, signal lines SL, and power supply lines PL. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 flattens out any irregularities caused by the circuit layer 11.

[0036] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12 and spaced apart from one another. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. An opening AP11 in the rib layer 5 overlaps the lower electrode LE1, an opening AP12 overlaps the lower electrode LE2, and an opening AP13 overlaps the lower electrode LE3. The peripheral portions of the lower electrodes LE1, LE2, and LE3 are covered with the rib layer 5. The lower electrodes LE1, LE2, and LE3 are connected to the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively, through contact holes provided in the organic insulating layer 12. Note that the contact holes in the organic insulating layer 12 are not shown in FIG. 3.

[0037] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5, and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. Both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61. Such a shape of the partition wall 6 is called an overhanging shape.

[0038] In the illustrated example, the lower portion 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. Both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0039] The upper portion 62 has a first thin film 65 disposed on the axial layer 64 and a second thin film 66 disposed on the first thin film 65. Both ends of the first thin film 65 and the second thin film 66 protrude from the side surfaces of the axial layer 64.

[0040] The organic layer OR1 is in contact with the lower electrode LE1 through the opening AP11, covers the lower electrode LE1 exposed from the opening AP11, and has its peripheral edge located on the rib layer 5. The upper electrode UE1 covers the organic layer OR1 and is in contact with the lower part 61.

[0041] The organic layer OR2 is in contact with the lower electrode LE2 through the opening AP12, covers the lower electrode LE2 exposed from the opening AP12, and has its peripheral edge located on the rib layer 5. The upper electrode UE2 covers the organic layer OR2 and is in contact with the lower part 61.

[0042] The organic layer OR3 is in contact with the lower electrode LE3 through the opening AP13, covers the lower electrode LE3 exposed from the opening AP13, and has its peripheral edge located on the rib layer 5. The upper electrode UE3 covers the organic layer OR3 and is in contact with the lower part 61.

[0043] In the illustrated example, subpixel SP1 has a cap layer CP1 and a sealing layer SE1, subpixel SP2 has a cap layer CP2 and a sealing layer SE2, and subpixel SP3 has a cap layer CP3 and a sealing layer SE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers that improve the extraction efficiency of light emitted from the organic layers OR1, OR2, and OR3, respectively. Note that the cap layers CP1, CP2, and CP3 may be omitted.

[0044] The cap layer CP1 is disposed on the upper electrode UE1. The cap layer CP2 is disposed on the upper electrode UE2. The cap layer CP3 is disposed on the upper electrode UE3.

[0045] The sealing layer SE1 is disposed on the cap layer CP1, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP1. The sealing layer SE2 is disposed on the cap layer CP2, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP2. The sealing layer SE3 is disposed on the cap layer CP3, is in contact with the partition wall 6, and continuously covers each component of the subpixel SP3.

[0046] In the following description, a multilayer body including an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as a laminate film FL1, a multilayer body including an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as a laminate film FL2, and a multilayer body including an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as a laminate film FL3.

[0047] Ends of the sealing layers SE1, SE2, and SE3 are each located on the partition wall 6. In the example shown, the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP2 is spaced apart from the sealing layer SE2 on the partition wall 6. In addition, the sealing layer SE1 on the partition wall 6 between the subpixels SP1 and SP3 is spaced apart from the sealing layer SE3 on the partition wall 6.

[0048] In the illustrated example, gaps are formed between the sealing layers SE1, SE2, and SE3 and the upper portion 62 of the partition wall 6. Although not illustrated, stacked films FL1, FL2, and FL3 may be disposed in at least a portion of these gaps.

[0049] The partition wall 6 and the sealing layers SE1, SE2, and SE3 are covered with a resin layer 13. The resin layer 13 fills the cavities between the sealing layers SE1, SE2, and SE3 and the partition wall 6. The resin layer 13 is covered with a sealing layer 14. The sealing layer 14 is covered with a resin layer 15.

[0050] The rib layer 5, sealing layers SE1, SE2, SE3, and sealing layer 14 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3).

[0051] The lower portion 61 of the partition wall 6 is formed of a conductive material and is electrically connected to the upper electrodes UE1, UE2, and UE3. The bottom layer 63 is formed of a titanium-based material such as titanium or a titanium compound. The shaft layer 64 is formed of a material different from the bottom layer 63 and the upper portion 62, and is formed of an aluminum-based material such as aluminum or an aluminum compound.

[0052] The upper portion 62 of the partition wall 6 is formed of, for example, a conductive material, but may also be formed of an insulating material. The upper portion 62 is formed of a material different from that of the lower portion 61. The first thin film 65 is formed of, for example, a titanium-based material such as titanium or a titanium compound. The second thin film 66 is formed of, for example, an oxide conductive material such as indium tin oxide (ITO).

[0053] The lower electrodes LE1, LE2, and LE3 are multilayer structures including a transparent layer made of an oxide conductive material such as indium tin oxide (ITO) and a reflective layer made of a metal material such as silver. In one example, the lower electrodes LE1, LE2, and LE3 are multilayer structures including a reflective layer between a pair of transparent layers.

[0054] The organic layer OR1 includes an emitting layer EM1. The organic layer OR2 includes an emitting layer EM2. The organic layer OR3 includes an emitting layer EM3. The emitting layers EM1, EM2, and EM3 are formed of different materials. In one example, the emitting layer EM1 is formed of a material that emits light in the blue wavelength region, the emitting layer EM2 is formed of a material that emits light in the green wavelength region, and the emitting layer EM3 is formed of a material that emits light in the red wavelength region. Each of the organic layers OR1, OR2, and OR3 includes multiple functional layers such as a hole injection layer, a hole transport layer, an electron blocking layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0055] The upper electrodes UE1, UE2, and UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg).

[0056] The cap layers CP1, CP2, and CP3 are multilayer structures made up of multiple thin films, all of which are transparent and have different refractive indices.

[0057] Figure 4 is a cross-sectional view showing an example of the configuration of the display device DSP taken along line 4-4 in Figure 1. Subpixels SP2 and SP3 of the display area DA are not shown in Figure 4. Here, the cross sections of the display area DA and the peripheral area SA will be described.

[0058] In the display region DA, the main surface 10B of the substrate 10 is covered with an inorganic insulating layer 111. The inorganic insulating layer 111 includes various circuits such as the pixel circuit 1 shown in FIG. 1 and various wirings such as the scanning lines GL, the signal lines SL, and the power supply lines PL. In the display region DA, the inorganic insulating layer 111 is covered with an organic insulating layer 112. The inorganic insulating layer 111 and the organic insulating layer 112 are included in the circuit layer 11 shown in FIG. 3. In the display region DA, a conductive layer 113 is disposed on the organic insulating layer 112. The conductive layer 113 includes a first conductive layer 1131 disposed on the organic insulating layer 112 and a second conductive layer 1132 disposed on the first conductive layer 1131. The conductive layer 113 is formed for each subpixel SP. In the display region DA, the organic insulating layer 12 covers the organic insulating layer 112 and the conductive layer 113. In the display area DA, a lower electrode LE1 and lower electrodes LE2 and LE3 (not shown) are disposed on the organic insulating layer 12. The peripheral edges of the lower electrode LE1 and lower electrodes LE2 and LE3 (not shown) are covered with a rib layer 5. Although not shown, in the display area DA, partition walls 6, stacked films FL1, FL2, and FL3, sealing layers SE1, SE2, SE3, and 14, and resin layers 13 and 15 are formed on the rib layer 5.

[0059] The lower electrode LE1 is electrically connected to the pixel circuit 1 of the subpixel SP1 via the conductive layer 113 of the subpixel SP1. The lower electrode LE2 is electrically connected to the pixel circuit 1 of the subpixel SP2 via the conductive layer 113 of the subpixel SP2. The lower electrode LE3 is electrically connected to the pixel circuit 1 of the subpixel SP3 via the conductive layer 113 of the subpixel SP3.

[0060] In the peripheral region SA, the main surface 10B of the substrate 10 is covered with an inorganic insulating layer 111. In the peripheral region SA, a pedestal 114 is disposed on the inorganic insulating layer 111. The pedestal 114 includes a first pedestal 1141 disposed on the inorganic insulating layer 111 and a second pedestal 1142 disposed on the first pedestal. The pedestal 114 includes a surface 114a facing the main surface 10B of the substrate 10 and a surface 114b opposite the surface 114a. In the peripheral region SA, an organic insulating layer 12 covers the inorganic insulating layer 111 and the pedestal 114. In the peripheral region SA, a rib layer 5 is disposed on the organic insulating layer 12. In the peripheral region SA, the rib layer 5 has an opening AP21 that overlaps the pedestal 114 in a plan view. Note that in the example shown in FIG. 4, no layer is formed on the rib layer 5 in the peripheral region SA, but this is not limiting.

[0061] The inorganic insulating layer 111 and the organic insulating layer 12 are disposed, for example, across the display area DA and the peripheral area SA.

[0062] The first conductive layer 1131 of the conductive layer 113 is formed of, for example, a metal multilayer film. The first conductive layer 1131 is a multilayer body including, for example, a first layer made of a titanium-based material such as titanium or a titanium compound, a second layer formed on the first layer and made of an aluminum-based material such as aluminum or an aluminum compound, and a third layer formed on the second layer and made of a titanium-based material such as titanium or a titanium compound.

[0063] The second conductive layer 1132 of the conductive layer 113 is formed of a conductive material different from that of the first conductive layer 1131. The second conductive layer 1132 is formed of an oxide conductive material such as indium tin oxide (ITO).

[0064] The first pedestal 1141 is formed of, for example, a metal multilayer film. The first conductive layer 1141 is a laminate including, for example, a first layer made of a titanium-based material such as titanium or a titanium compound, a second layer formed on the first layer and made of an aluminum-based material such as aluminum or an aluminum compound, and a third layer formed on the second layer and made of a titanium-based material such as titanium or a titanium compound.

[0065] The second seat 1142 is formed of a conductive material different from that of the first seat 1141. The second seat 1142 is formed of an oxide conductive material such as indium tin oxide (ITO), for example.

[0066] The first conductive layer 1131 and the first pedestal 1141 may be formed together using the same material, and the second conductive layer 1132 and the second pedestal 1142 may be formed together using the same material.

[0067] Fig. 5 is a plan view showing an example of the configuration of the peripheral area SA shown in Fig. 4. In Fig. 5, the rib layer 5 is indicated by dots. Fig. 6 is a schematic cross-sectional view of the display device DSP taken along line 6-6 in Fig. 5.

[0068] 5, the rib layer 5 has an opening AP21 that overlaps with the pedestal 114 in a plan view. The organic insulating layer 12 is exposed from the rib layer 5 in the opening AP21.

[0069] The base 114 has a surface 114a facing the main surface 10B of the substrate 10 and a surface 114b opposite to the surface 114a. The base 114 has, for example, a rectangular shape in a plan view. In the example shown in FIGS. 5 and 6, the opening AP21 has a rectangular shape larger than the base 114 in a plan view, but is not limited to this.

[0070] The base 114 has identification information 200. The identification information 200 is formed as a plurality of through-holes TH1 that penetrate the first base 1141 and the second base 1142 in the third direction Z, as shown in Figures 5 and 6. The plurality of through-holes TH1 are, for example, aligned in the first direction X and the second direction Y according to a predetermined rule, and form a two-dimensional code in plan view.

[0071] The identification information 200 may be formed as a plurality of through holes penetrating either the first base 1141 or the second base 1142. Alternatively, the identification information 200 may be formed as a plurality of recesses formed on at least one of the surfaces 114a and 114b of the base 114. Alternatively, the identification information 200 may be formed by discoloring a plurality of locations on at least one of the surfaces 114a and 114b of the base 114.

[0072] Next, an example of a method for manufacturing the display device DSP will be described. Figures 7A to 7H are schematic cross-sectional views showing the manufacturing process of the display device DSP.

[0073] First, as shown in Fig. 7A, an inorganic insulating layer 111 is formed across the display area DA and the peripheral area SA on the main surface 10B of the substrate 10. Next, as shown in Fig. 7B, an organic insulating layer 112 is formed on the inorganic insulating layer 111 in the display area DA.

[0074] After the step of forming the organic insulating layer 112, as shown in Fig. 7C, a first conductive layer 1131 is formed on the organic insulating layer 112 in the display area DA. Furthermore, a first pedestal 1141 is formed on the inorganic insulating layer 111 in the peripheral area SA. The first conductive layer 1131 and the first pedestal 1141 may be formed at the same time using the same material.

[0075] After the step of forming the first conductive layer 1131 and the first pedestal 1141, as shown in FIG. 7D , in the display area DA, a second conductive layer 1132 is formed on the first conductive layer 1131. Furthermore, in the peripheral area SA, a second pedestal 1142 is formed on the first pedestal 1141. The second conductive layer 1132 and the second pedestal 1142 may be formed at the same time using the same material. As a result, the conductive layer 113 is formed in the display area DA, and the pedestal 114 is formed in the peripheral area SA.

[0076] 7E, after the step of forming the second conductive layer 1132 and the second pedestal 1142, an organic insulating layer 12 is formed to cover the organic insulating layer 112 and the conductive layer 113 in the display area DA, and the inorganic insulating layer 111 and the pedestal 114 in the peripheral area SA. The organic insulating layer 12 may be formed across the display area DA and the peripheral area SA.

[0077] After the step of forming the organic insulating layer 12, as shown in Fig. 7F, in the display area DA, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12. In Fig. 7F, the lower electrodes LE2 and LE3 are not shown.

[0078] After the step of forming the lower electrodes LE1, LE2, and LE3, a rib layer 5 is formed in the display area DA to cover the peripheral edges of the lower electrode LE1 and the lower electrodes LE2 and LE3 (not shown), as shown in Fig. 7G. In addition, a rib layer 5 is formed on the organic insulating layer 12 in the peripheral area SA.

[0079] After the step of forming the rib layer 5, as shown in Fig. 7H, an opening AP21 is formed in the rib layer 5 in the peripheral area SA by patterning or the like. The step of forming the opening AP21 may be performed at any stage after the step of forming the rib layer 5. Note that the openings AP11, AP12, and AP13 in the rib layer 5 in the display area DA may be formed simultaneously with the opening AP21, or may be formed in a step separate from the step of forming the opening AP21.

[0080] 8A to 8F are schematic cross-sectional views showing the manufacturing process of the display device DSP. Here, the display area DA will be explained. In FIGS. 8A to 8F, the substrate 10 and the circuit layer 11 are not shown.

[0081] After the step of forming the rib layer 5, the partition walls 6 and the display elements DE are formed in the display area DA. First, as shown in Fig. 8A, the partition walls 6 are formed, each having a lower portion 61 located on the rib layer 5 and an upper portion 62 located on the lower portion 61.

[0082] Next, the display element DE1 is formed. First, as shown in Fig. 8B, the organic layer OR1, the upper electrode UE1, and the cap layer CP1 are formed in this order on the lower electrode LE1, to form a laminated film FL1.

[0083] The organic layer OR1, the upper electrode UE1, and the cap layer CP1 are each formed by vapor deposition using the partition walls 6 as a mask. The stacked film FL1 is divided into multiple parts by the overhanging partition walls 6. Such a stacked film FL1 is also formed on the lower electrodes LE2 and LE3.

[0084] Thereafter, the sealing layer SE1 is formed on the laminated film FL1 by chemical vapor deposition (CVD). The sealing layer SE1 continuously covers the partition walls 6 and each of the divided portions of the laminated film FL1.

[0085] 8C, a resist RS patterned into a predetermined shape is formed on the sealing layer SE1. The resist RS overlaps the subpixel SP1 and part of the partition wall 6 around it.

[0086] Next, as shown in FIG. 8D, etching is performed using the resist RS as a mask, and the sealing layer SE1 and stacked film FL1 exposed by the resist RS are sequentially removed. This exposes the upper portion 62 of the partition wall 6. The stacked film FL1 covered with the resist RS remains in the subpixel SP1, the lower electrode LE2 is exposed in the subpixel SP2, and the lower electrode LE3 is exposed in the subpixel SP3. The etching includes wet etching and dry etching, which are performed sequentially on the sealing layer SE1, cap layer CP1, upper electrode UE1, and organic layer OR1. After these etching steps, the resist RS is removed. This forms a display element DE1 in the subpixel SP1.

[0087] Next, as shown in FIG. 8E, display element DE2 is formed. The procedure for forming display element DE2 is the same as that for forming display element DE1. That is, a stacked film FL2 is formed on the lower electrode LE2, and a sealing layer SE2 is formed on the stacked film FL2. Then, a resist is formed on the sealing layer SE2, and the sealing layer SE2 and the stacked film FL1 are patterned by etching using this resist as a mask. After this patterning, the resist is removed. As a result, display element DE2 is formed in subpixel SP2, and the lower electrode LE3 of subpixel SP3 is exposed.

[0088] Next, as shown in FIG. 8F, display element DE3 is formed. The procedure for forming display element DE3 is the same as the procedure for forming display element DE1. That is, a stacked film FL3 is formed on the lower electrode LE3, and a sealing layer SE3 is formed on the stacked film FL3. Then, a resist is formed on the sealing layer SE3, and the sealing layer SE3 and the stacked film FL3 are patterned by etching using this resist as a mask. After this patterning, the resist is removed. This forms display element DE3 in subpixel SP3.

[0089] Thereafter, the resin layer 13, the sealing layer 14, and the resin layer 15 shown in Fig. 3 are formed in this order in the display area DA, thus completing the display device DSP.

[0090] In the above manufacturing process, it is assumed that display element DE1 is formed first, then display element DE2 is formed, and finally display element DE3 is formed, but the order in which display elements DE1, DE2, and DE3 are formed is not limited to this example.

[0091] 9A to 9C are schematic cross-sectional views showing the manufacturing process of the display device DSP. Here, the peripheral area SA will be described.

[0092] Next, identification information 200 is formed on base 114 in peripheral area SA. As shown in Fig. 9, laser light 310 is irradiated from laser irradiation device 300 toward base 114. In the example shown in Fig. 9, surface 114b of base 114 and laser irradiation device 300 are arranged to face each other.

[0093] The laser light 310 passes through the organic insulating layer 12 and forms a through-hole TH1 that penetrates the first pedestal 1141 and the second pedestal 1142 in the third direction Z. In this way, the identification information 200 is formed on the pedestal 114.

[0094] Although not shown, the surface 114a of the base 114 and the laser irradiation device 300 may be arranged to face each other, and laser light may be irradiated onto the surface 114a. At this time, the laser light 310 passes through the substrate 10 and the inorganic insulating layer 111, and forms a through-hole TH1 that penetrates the first base 1141 and the second base 1142 in the third direction Z.

[0095] The step of forming the identification information 200 may be performed at any stage after the step of forming the base 114.

[0096] Fig. 10 is a cross-sectional view showing a display device DSP' of a comparative example. Fig. 10(a) is a cross-sectional view of the display device DSP' before the identification information 200 is formed, and Fig. 10(b) is a cross-sectional view of the display device DSP' after the identification information 200 is formed.

[0097] The display device DSP' of the comparative example differs from the display device DSP of the embodiment in that the rib layer 5 does not have an opening AP21 that overlaps with the base 114 in plan view.

[0098] 10 , in the display device DSP′ of the comparative example, the rib layer 5 overlapping the base 114 in plan view may be damaged by the laser light 310 from the laser irradiation device 300, and at least a part of the rib layer 5 may peel off from the organic insulating layer 12. Such peeling of the rib layer 5 may cause a reading error when reading the identification information 200 with a scanner or the like. Furthermore, the peeled rib layer 5 may fly off and come into contact with the terminals TE or the like, causing a connection failure of the display device DSP.

[0099] In the display device DSP according to this embodiment, the rib layer 5 has an opening AP21 that overlaps with the base 114 in a plan view. This prevents the rib layer 5 from being damaged by irradiation with the laser light 310, and prevents the rib layer 5 from peeling off from the organic insulating layer 12 and the peeled rib layer 5 from scattering.

[0100] As described above, according to this embodiment, it is possible to suppress a decrease in reliability in reading the identification information 200. It is also possible to suppress a decrease in reliability of the display device DSP.

[0101] Fig. 11 is a plan view showing another example of the configuration of the peripheral area SA shown in Fig. 5. Fig. 12 is a schematic cross-sectional view of the display device DSP taken along line 12-12 in Fig. 11. (a) of Fig. 12 is a cross-sectional view of the display device DSP before the identification information 200 is formed, and (b) of Fig. 12 is a cross-sectional view of the display device DSP after the identification information 200 has been formed.

[0102] The configuration example shown in Fig. 11 differs from the configuration example shown in Fig. 5 in that it further includes partition walls 7. The above description will be used to cite the same configuration as the configuration example shown in Fig. 5, and a description thereof will be omitted. In Fig. 11, the partition walls 7 are indicated by hatching. Also, in Fig. 11, the size of the partition walls 7 is schematically shown enlarged.

[0103] 11, the partition walls 7 are formed on the rib layer 5 in the peripheral region SA and overlap the rib layer 5 in a plan view. The partition walls 7 are preferably formed on the rib layer 5 close to the outer edge of the opening AP21. The distance L from the outer edge of the opening AP21 to the end of the upper portion 72 of the partition wall 7 is, for example, 5 μm to 60 μm.

[0104] 11 and 12, the partition wall 7 is formed so as to surround the opening AP21. It can also be said that the partition wall 7 has an opening that overlaps with the opening AP21. The shape of the partition wall 7 is not limited to the example shown in the drawings. For example, a plurality of partition walls 7 may be arranged so as to surround the opening AP21 as a whole, and in this case, the plurality of partition walls 7 may be arranged spaced apart from each other.

[0105] The partition wall 7 has a structure similar to that of the partition wall 6 shown in Fig. 3. As shown in Fig. 12, the partition wall 7 includes a lower portion 71 disposed on the rib layer 5 and an upper portion 72 disposed on the lower portion 71. The upper portion 72 has a width greater than that of the lower portion 71. Both ends of the upper portion 72 protrude beyond the side surfaces of the lower portion 71.

[0106] In the illustrated example, the lower part 71 has a bottom layer 73 disposed on the rib layer 5 and a shaft layer 74 disposed on the bottom layer 73. For example, the bottom layer 73 is formed thinner than the shaft layer 74. Both ends of the bottom layer 73 protrude from the side surfaces of the shaft layer 74. The upper portion 72 has a first thin film 75 disposed on an axial layer 74 and a second thin film 76 disposed on the first thin film 75. Both ends of the first thin film 75 and the second thin film 76 protrude from the side surfaces of the axial layer 74.

[0107] The lower portion 71 of the partition wall 7 is made of, for example, a conductive material. The bottom layer 73 is made of, for example, a titanium-based material such as titanium or a titanium compound. The shaft layer 74 is made of a material different from the bottom layer 73 and the upper portion 72, and is made of, for example, an aluminum-based material such as aluminum or an aluminum compound.

[0108] The upper portion 72 of the partition wall 7 is formed of, for example, a conductive material, but may also be formed of an insulating material. The upper portion 72 is formed of a material different from that of the lower portion 71. The first thin film 75 is formed of, for example, a titanium-based material such as titanium or a titanium compound. The second thin film 76 is formed of, for example, an oxide conductive material such as indium tin oxide (ITO).

[0109] The base 114 has identification information 200. The identification information 200 is formed as, for example, a plurality of through-holes TH1 that penetrate the base 114 in the third direction Z, as shown in Figures 11 and 12, but is not limited to this.

[0110] In the manufacture of the display device DSP, the partition walls 7 may be formed at any time after the rib layer 5 is formed, but are preferably formed before the display elements DE are formed. The partition walls 7 may be formed simultaneously with the partition walls 6.

[0111] 11, the partition walls 7 are formed on the rib layer 5, and the rib layer 5 is held down by the partition walls 7, which can prevent the rib layer 5 from peeling off from the organic insulating layer 12. Furthermore, in this configuration example, the same effects as in the configuration example shown in FIG.

[0112] Fig. 13 is a cross-sectional view showing another example of the configuration of the display device DSP shown in Fig. 3. The description above will be used to cite and omit explanation of the same configuration as the example shown in Fig. 3.

[0113] The configuration example shown in Fig. 13 differs from the display device DSP shown in Fig. 3 in that it further includes wiring TL. The wiring TL is formed on the sealing layer 14 and is located, for example, directly above the partition wall 6. Such wiring TL functions, for example, as sensor wiring for detecting an object approaching the display device DSP. The wiring TL is covered with a resin layer 15.

[0114] The wiring TL is formed of a metal material such as aluminum, titanium, molybdenum, etc. In one example, the wiring TL is a multilayer body including an aluminum layer between a pair of titanium layers.

[0115] Fig. 14 is a plan view showing an example of the configuration of the peripheral area SA of the display device DSP shown in Fig. 13. Fig. 15 is a schematic cross-sectional view of the display device DSP taken along line 15-15 in Fig. 14. (a) of Fig. 15 is a cross-sectional view of the display device DSP before the identification information 200 is formed, and (b) of Fig. 15 is a cross-sectional view of the display device DSP after the identification information 200 has been formed.

[0116] The configuration example shown in Fig. 14 differs from the configuration example shown in Fig. 5 in that it further includes a protective layer 8. The description above is used to cite the same configuration as the configuration example shown in Fig. 5, and therefore a description thereof will be omitted.

[0117] 14 and 15, the organic insulating layer 12 has an opening AP22 that overlaps with the opening AP21 in a plan view. The opening AP22 penetrates in the third direction Z to the pedestal 114. In the opening AP22, a surface 114b of the pedestal 114 is exposed from the organic insulating layer 12.

[0118] The protective layer 8 is disposed in the opening AP22. The protective layer 8 contacts the surface 114b exposed from the organic insulating layer 12 at the opening AP22. In the example shown in FIGS. 14 and 15, the protective layer 8 covers the organic insulating layer 12 between the edge of the opening AP21 and the edge of the opening AP22 and on the side surface of the opening AP22. The protective layer 8 is formed collectively, for example, from the same material as the wiring TL shown in FIG. 13.

[0119] At least one of the base 114 and the protective layer 8 has identification information 200. The identification information 200 is formed as a plurality of through-holes TH1 that penetrate the base 114 and the protective layer 8 in the third direction Z at the opening AP22, for example, as shown in Fig. 14 and Fig. 15 . That is, the protective layer 8 has identification information 200 that overlaps with the identification information 200 of the base 114.

[0120] In this configuration example, the same effects as those in the configuration example shown in FIG. 5 can be obtained.

[0121] FIG. 16 is a cross-sectional view showing another example of the configuration of the display device DSP shown in FIG.

[0122] The configuration example shown in Figure 16 differs from the display device DSP shown in Figure 4 in that the conductive layer 113 has only a first conductive layer 1131 and does not have a second conductive layer 1132, the base 114 has only a first base 1141 and does not have a second base 1142, and it further has a protective layer 8.

[0123] The first conductive layer 1131 is disposed on the organic insulating layer 112 and is covered with the organic insulating layer 112. The first seat 1141 is disposed on the inorganic insulating layer 111 and contacts the protective layer 8 at the opening AP22.

[0124] Fig. 17 is a diagram showing an example of the configuration of the peripheral area SA of the display device DSP shown in Fig. 16. Fig. 18 is a schematic cross-sectional view of the display device DSP taken along line 18-18 in Fig. 17.

[0125] 17 and 18, the organic insulating layer 12 has an opening AP22 that overlaps with the opening AP21 in a plan view. The opening AP22 penetrates to the pedestal 114. The first pedestal 1141 is exposed from the organic insulating layer 12 in the opening AP22.

[0126] The protective layer 8 is disposed in the opening AP22. The protective layer 8 contacts the first seat 1141 exposed from the organic insulating layer 12 at the opening AP22.

[0127] At least one of the first seat 1141 and the protective layer 8 has identification information 200. The identification information 200 is formed as a plurality of through-holes TH1 that penetrate the first seat 1141 and the protective layer 8 in the third direction Z in the opening AP22, for example, as shown in FIG.

[0128] In this configuration example, the same effects as those in the configuration example shown in FIG. 5 can be obtained.

[0129] Fig. 19 is a diagram showing another example of the configuration of the peripheral area SA shown in Fig. 5. Fig. 20 is a schematic cross-sectional view of the display device DSP taken along line 20-20 in Fig. 19. (a) of Fig. 20 is a cross-sectional view of the display device DSP before the identification information 200 is formed, and (b) of Fig. 20 is a cross-sectional view of the display device DSP after the identification information 200 has been formed.

[0130] The configuration example shown in Fig. 19 differs from the configuration example shown in Fig. 5 in that the rib layer 5 does not have an opening AP21 and a protective layer 8 is formed on the rib layer 5. The description above is used to cite the same configuration as the configuration example shown in Fig. 5 and will not be repeated here.

[0131] 19 and 20, the protective layer 8 is disposed on the rib layer 5 in the peripheral region SA. In a plan view, the protective layer 8 overlaps with the base 114. In the example shown in Fig. 19, the protective layer 8 has a rectangular shape with the same size as the base 114, but is not limited to this.

[0132] At least one of the base 114 and the protective layer 8 has identification information 200. For example, as shown in Fig. 20 , the identification information 200 is formed as a plurality of through holes TH1 that penetrate the base 114 in the third direction Z and a plurality of through holes TH2 that penetrate the protective layer 8 in the third direction Z. Each of the plurality of through holes TH1 and each of the plurality of through holes TH2 overlap each other in a plan view. That is, the identification information 200 of the protective layer 8 overlaps the identification information 200 of the base 114.

[0133] The plurality of through holes TH1 and the plurality of through holes TH2 are arranged in the first direction X and the second direction Y according to a predetermined rule, for example, as shown in FIG. 19, and form a two-dimensional code in plan view.

[0134] 19, a protective layer 8 overlapping the base 114 is provided on the rib layer 5. In this way, the rib layer 5 overlapping the base 114 in plan view is protected by the protective layer 8. Therefore, even if the rib layer 5 is damaged by irradiation of the base 114 with laser light when forming the identification information 200, the rib layer 5 can be prevented from peeling off from the organic insulating layer 12. Furthermore, even if the rib layer 5 peels off, the peeled rib layer 5 can be prevented from scattering.

[0135] In this way, also in the configuration example shown in FIG. 19, it is possible to suppress a decrease in reliability in reading the identification information, and it is also possible to suppress a decrease in reliability of the display device DSP.

[0136] Fig. 21 is a cross-sectional view showing another example of the configuration of the peripheral area SA shown in Fig. 19. Also, Fig. 22 is a schematic cross-sectional view of the display device DSP taken along line 22-22 in Fig. 21. (a) of Fig. 22 is a cross-sectional view of the display device DSP before the identification information 200 is formed, and (b) of Fig. 22 is a cross-sectional view of the display device DSP after the identification information 200 has been formed.

[0137] The configuration example shown in Fig. 21 differs from the configuration example shown in Fig. 19 in that the display device DSP does not include the base 114. The description above will be used to cite and omit the description of the same configuration as the configuration example shown in Fig. 19.

[0138] 21 and 22, the protective layer 8 is disposed on the rib layer 5. The protective layer 8 has identification information 200. For example, as shown in FIGS. 21 and 22, the identification information 200 is formed as a plurality of through holes TH2 that penetrate the protective layer 8 in the third direction Z. In this configuration example as well, the same effects as those in the configuration example shown in FIG. 19 can be obtained.

[0139] As described above, according to this embodiment, it is possible to provide a manufacturing method for a display device that can suppress a decrease in reliability.

[0140] All display device manufacturing methods that can be implemented by a person skilled in the art by making appropriate design modifications based on the display device manufacturing method described above as an embodiment of the present invention also fall within the scope of the present invention as long as they include the gist of the present invention.

[0141] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0142] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0143] DSP…display device 10…board 5...Rib layer AP11, AP12, AP13, AP21, AP22...Openings 6...Partition wall 61...Lower part 62...Upper part 63...Bottom layer 64...Axial layer 7...Partition wall 71...Lower part 72...Upper part 73...Bottom layer 74...Axial layer 8…Protective layer 10... Substrate 11... Circuit layer 111... Inorganic insulating layer 112... Organic insulating layer 113...Conductive layer 1131...First conductive layer 1132...Second conductive layer 114...Pedestal 1141...1st pedestal 1142...2nd pedestal TH1, TH2…Through hole 12...Organic insulating layer SP1, SP2, SP3...subpixels DE1, DE2, DE3...Display element (organic EL element) LE1, LE2, LE3…lower electrode UE1, UE2, UE3...upper electrode OR1, OR2, OR3…Organic layer CP1, CP2, CP3...cap layer SE1, SE2, SE3...Sealing layer DA: Display area SA: Surrounding area 200...Identification information 300...Laser irradiation device

Claims

1. A substrate; an inorganic insulating layer disposed above the substrate across a display area where an image is displayed and a peripheral area outside the display area; an organic insulating layer disposed on the inorganic insulating layer; a rib layer formed of an inorganic material and disposed above the organic insulating layer; a lower electrode disposed on the organic insulating layer in the display area and having a peripheral edge portion covered with the rib layer; an organic layer including a light-emitting layer disposed on the lower electrode; an upper electrode covering the organic layer; a first partition wall having a first lower portion disposed on the rib layer in the display area and a first upper portion protruding from a side surface of the first lower portion; a base having identification information and disposed between the inorganic insulating layer and the organic insulating layer in the peripheral region; The display device, wherein the rib layer has a first opening in the peripheral region that overlaps with the base in a plan view.

2. The display device according to claim 1 , further comprising: a second partition wall in the peripheral region, the second partition wall having a second lower portion disposed on the rib layer and a second upper portion protruding from a side surface of the second lower portion.

3. The display device according to claim 2 , wherein the second partition wall surrounds the first opening in a plan view.

4. the organic insulating layer has, in the peripheral region, a second opening that overlaps with the first opening in a plan view and penetrates to the pedestal; The display device according to claim 1 , further comprising a protective layer disposed at the second opening and in contact with the base.

5. The display device according to claim 4 , wherein the protective layer has identification information that overlaps with the identification information of the base in a plan view.

6. A substrate; an inorganic insulating layer disposed above the substrate across a display area where an image is displayed and a peripheral area outside the display area; an organic insulating layer disposed on the inorganic insulating layer; a rib layer formed of an inorganic material and disposed above the organic insulating layer; a lower electrode disposed on the organic insulating layer in the display area and having a peripheral edge portion covered with the rib layer; an organic layer including a light-emitting layer disposed on the lower electrode; an upper electrode covering the organic layer; a first partition wall having a first lower portion disposed on the rib layer in the display area and a first upper portion protruding from a side surface of the first lower portion; a protective layer having identification information, the protective layer being disposed above the rib layer in the peripheral region.

7. the insulating layer is disposed between the inorganic insulating layer and the organic insulating layer in the peripheral region, and the insulating layer has a base having identification information; the protective layer overlaps the base in a plan view, The display device according to claim 6 , wherein the identification information on the protective layer is superimposed on the identification information on the base in a plan view.

8. The display device according to claim 1 , wherein the base comprises a first base formed of a metal multilayer film.

9. the base further includes a second base disposed on the first base, The display device according to claim 8 , wherein the second seat is made of a conductive oxide material different from that of the first seat.

10. The display device according to claim 1 , wherein the identification information of the base is a plurality of through holes formed in the base.

11. The display device according to claim 6 , wherein the identification information of the protective layer is a plurality of through holes formed in the protective layer.

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