Array substrate, display panel and display device thereof

Abstract

An array substrate, a display panel thereof and a display device are provided.SOLUTION: The array substrate includes a substrate, a plurality of sub-pixels, a driving reset voltage line and a light-emitting reset voltage line, wherein the plurality of sub-pixels are arranged in a plurality of rows and a plurality of columns, at least one of the plurality of sub-pixels includes a pixel circuit, and each pixel circuit includes a driving circuit, a voltage adjusting circuit, a driving reset circuit and a light-emitting reset circuit. The driving circuit is configured to provide a driving current to a light-emitting device, the voltage adjusting circuit is configured to electrically connect a control terminal of the driving circuit to a driving reset circuit, the driving reset circuit is configured to reset the control terminal of the driving circuit, the light-emitting reset circuit is configured to reset the light-emitting device, a driving reset voltage line is coupled to a driving reset voltage terminal and configured to provide a driving reset voltage to the driving reset voltage terminal, and a light-emitting reset voltage line is coupled to the light-emitting reset voltage terminal and configured to provide the light-emitting reset voltage to the light-emitting reset voltage terminal.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] This disclosure claims priority to a PCT international application entitled "Array substrate, display panel thereof, and display device," filed on February 10, 2021, with PCT international application number PCT / CN2021 / 076577, the entire contents of which are incorporated herein by reference.

[0002] TECHNICAL FIELD The embodiments of the present disclosure relate to the field of display technology, and in particular to an array substrate, a display panel thereof, and a display device. [Background technology]

[0003] Organic Light-Emitting Diode (OLED) display panels have features such as self-luminance, high efficiency, vivid colors, thinness, power saving, curl resistance, and a wide temperature range, and are gradually being applied to large displays, lighting, automotive displays, etc. Summary of the Invention [Means for solving the problem]

[0004] Embodiments of the present disclosure provide an array substrate and a related display panel and display device.

[0005] A first aspect of the present disclosure provides an array substrate including a substrate. The array substrate includes a plurality of sub-pixels disposed on the substrate and arranged in a plurality of rows and columns. At least one of the plurality of sub-pixels includes a pixel circuit. Each pixel circuit includes a drive circuit, a voltage adjustment circuit, a drive reset circuit, and a light emission reset circuit. The drive circuit includes a control end, a first end, and a second end and is configured to provide a drive current to a light emitting element. The voltage adjustment circuit is coupled to the control end of the drive circuit, a first node, and a voltage adjustment control signal input end, and is configured to conduct the control end of the drive circuit with the first node under control of a voltage adjustment control signal from the voltage adjustment control signal input end. The drive reset circuit is coupled to the drive reset control signal input end, the first node, and a drive reset voltage end, and is configured to provide a drive reset voltage from the drive reset voltage end to the voltage adjustment circuit to reset the control end of the drive circuit under control of a drive reset control signal from the drive reset control signal input end. The light emitting reset circuit is coupled to the light emitting reset control signal input terminal, the light emitting element, and the light emitting reset voltage terminal, and is configured to provide a light emitting reset voltage from the light emitting reset voltage terminal to the light emitting element under control of a light emitting reset control signal from the light emitting reset control signal input terminal to reset the light emitting element. The array substrate further includes a driving reset voltage line and a light emitting reset voltage line. The driving reset voltage line is coupled to the driving reset voltage terminal and configured to provide a driving reset voltage. The light emitting reset voltage line is coupled to the light emitting reset voltage terminal and configured to provide the light emitting reset voltage.

[0006] In an embodiment of the present disclosure, the drive circuit includes a drive transistor. The voltage adjustment circuit includes a voltage adjustment transistor. The drive reset circuit includes a drive reset transistor. The luminescence reset circuit includes a luminescence reset transistor. A first pole of the drive transistor is coupled to a first end of the drive circuit, a gate of the drive transistor is coupled to a control end of the drive circuit, and a second pole of the drive transistor is coupled to a second end of the drive circuit. A first pole of the voltage adjustment transistor is coupled to a control end of the drive circuit, a gate of the voltage adjustment transistor is coupled to a voltage adjustment control signal input end, and a second pole of the voltage adjustment transistor is coupled to a first node. A first pole of the drive reset transistor is coupled to a drive reset voltage end, a gate of the drive reset transistor is coupled to a drive reset control signal input end, and a second pole of the drive reset transistor is coupled to a first node. A first pole of the luminescence reset transistor is coupled to a luminescence reset voltage end, a gate of the luminescence reset transistor is coupled to a luminescence reset control signal input end, and a second pole of the luminescence reset transistor is coupled to a first end of the luminescence element. An active layer of the voltage adjustment transistor includes an oxide semiconductor material. The active layers of the drive transistor and the drive reset transistor include silicon semiconductor material.

[0007] In an embodiment of the present disclosure, the active layer of the light-emitting reset transistor comprises an oxide semiconductor material.

[0008] In an embodiment of the present disclosure, the array substrate further includes a first active semiconductor layer and a second active semiconductor layer, wherein the first active semiconductor layer is located on the substrate and includes a silicon semiconductor material, and the second active semiconductor layer is located on a side of the first active semiconductor layer away from the substrate, is insulated and isolated from the first active semiconductor layer, and includes an oxide semiconductor material.

[0009] In an embodiment of the present disclosure, the first active semiconductor layer includes an active layer of a driving transistor and an active layer of a driving reset transistor. The second active semiconductor layer includes a first portion and a second portion arranged along the column direction. The first portion of the second active semiconductor includes an active layer of a voltage adjustment transistor. The second portion of the second active semiconductor includes an active layer of an emission reset transistor.

[0010] In an embodiment of the present disclosure, the first portion of the second active semiconductor and the second portion of the second active semiconductor are aligned along the column direction.

[0011] In an embodiment of the present disclosure, the pixel circuit further includes a data writing circuit, a compensation circuit, a memory circuit, and a light-emitting control circuit. The data writing circuit is coupled to the data signal input terminal, the scan signal input terminal, and the first terminal of the drive circuit, and is configured to provide a data signal from the data signal input terminal to the first terminal of the drive circuit under control of a scan signal from the scan signal input terminal. The compensation circuit is coupled to the second terminal of the drive circuit, the first node, and the compensation control signal input terminal, and is configured to perform threshold compensation for the drive circuit in response to a compensation control signal from the compensation control signal input terminal. The memory circuit is coupled to the first power supply voltage terminal and the control terminal of the drive circuit, and is configured to store a voltage difference between the first power supply voltage terminal and the control terminal of the drive circuit. The light-emitting control circuit is coupled to the light-emitting control signal input terminal, the first power supply voltage terminal, the first and second terminals of the drive circuit, the light-emitting reset circuit, and the light-emitting element, and is configured to apply a first power supply voltage from the first power supply voltage terminal to the drive circuit and apply a driving current generated by the drive circuit to the light-emitting element under control of a light-emitting control signal from the light-emitting control signal input terminal.

[0012] In an embodiment of the present disclosure, the data write circuit includes a data write transistor. The compensation circuit includes a compensation transistor. The storage circuit includes a storage capacitor. The light emission control circuit includes a first light emission control transistor and a second light emission control transistor. A first pole of the data write transistor is coupled to a data signal input terminal, a gate of the data write transistor is coupled to a scan signal input terminal, and a second pole of the data write transistor is coupled to a first terminal of the drive circuit. A first pole of the compensation transistor is coupled to a second terminal of the drive circuit, a gate of the compensation transistor is coupled to a compensation control signal input terminal, and a second pole of the compensation transistor is coupled to a first node. A first pole of the storage capacitor is coupled to a first power supply voltage terminal, and a second pole of the storage capacitor is coupled to a drive circuit control terminal, and is configured to store a voltage difference between the first power supply voltage terminal and the control terminal of the drive circuit. A first pole of the first light-emitting control transistor is coupled to a first power supply voltage terminal, a gate of the first light-emitting control transistor is coupled to a light-emitting control signal input terminal, a second pole of the first light-emitting control transistor is coupled to a first terminal of the drive circuit, a first pole of the second light-emitting control transistor is coupled to a second terminal of the drive circuit, a gate of the second light-emitting control transistor is coupled to the light-emitting control signal input terminal, and a second pole of the second light-emitting control transistor is coupled to a first pole of the light-emitting element.

[0013] In the embodiment of the present disclosure, the first active semiconductor layer includes active layers of a data writing transistor, a compensation transistor, a first light-emitting control transistor, and a second light-emitting control transistor.

[0014] In the embodiment of the present disclosure, the light emission reset control signal and the light emission control signal are the same signal.

[0015] In the embodiment of the present disclosure, the scan signal and the compensation control signal are the same signal.

[0016] In an embodiment of the present disclosure, the array substrate further includes a first conductive layer, the first conductive layer being located between the first active semiconductor layer and the second active semiconductor layer and insulated and isolated from the first active semiconductor layer and the second active semiconductor layer. The first conductive layer includes a driving reset control signal line, a scan signal line, a gate of a driving transistor, a first pole of a storage capacitor, and a light-emitting control signal line, arranged in order along the column direction. The driving reset control signal line is coupled to the driving reset control signal input terminal and configured to provide a driving reset control signal thereto. The scan signal line is coupled to the scan signal input terminal and the compensation control signal input terminal and configured to provide a scan signal to the scan signal input terminal and a compensation control signal to the compensation control signal input terminal. The first pole of the storage capacitor and the gate of the driving transistor are integrally configured. The light-emitting control signal line is coupled to the light-emitting control signal input terminal and configured to provide a light-emitting control signal thereto.

[0017] In an embodiment of the present disclosure, the portion where the orthogonal projection of the drive reset control signal line onto the substrate overlaps with the orthogonal projection of the first active semiconductor layer onto the substrate is the gate of the drive reset transistor, the portion where the orthogonal projection of the scan signal line onto the substrate overlaps with the orthogonal projection of the first active semiconductor layer onto the substrate is the gate of the compensation transistor and the gate of the data write transistor, and the portion where the orthogonal projection of the light emission control signal line onto the substrate overlaps with the orthogonal projection of the first active semiconductor layer onto the substrate is the gate of the first light emission control transistor and the gate of the second light emission control transistor.

[0018] In an embodiment of the present disclosure, the array substrate further includes a second conductive layer, the second conductive layer being located between the first conductive layer and the second active semiconductor layer and insulated and isolated from the first conductive layer and the second active semiconductor layer. The second conductive layer includes a voltage adjustment control signal line, a second pole of a storage capacitor, a first power supply voltage line, and a light emission reset control signal line arranged along the column direction. The voltage adjustment control signal line is coupled to a voltage adjustment control signal input terminal and configured to provide a voltage adjustment control signal thereto. The first power supply voltage line is coupled to a first power supply voltage terminal and configured to provide a first power supply voltage thereto. Orthogonal projections of the second pole of the storage capacitor and the first pole of the storage capacitor onto the substrate at least partially overlap. The second pole of the storage capacitor and the first power supply voltage line are integrally formed. The light emission reset control signal line is coupled to the light emission reset control signal input terminal and configured to provide a light emission reset control signal thereto.

[0019] In an embodiment of the present disclosure, a portion where the orthogonal projection of the voltage adjustment control signal line onto the substrate overlaps with the orthogonal projection of the second active semiconductor layer onto the substrate is a first control pole of the voltage adjustment transistor, and a portion where the orthogonal projection of the light-emitting control signal line onto the substrate overlaps with the orthogonal projection of the second active semiconductor layer onto the substrate is a first control pole of the light-emitting reset transistor. In an embodiment of the present disclosure, the array substrate further includes a third conductive layer located on a side of the second active semiconductor layer away from the substrate and insulated and isolated from the second active semiconductor layer, and the third conductive layer includes a voltage adjustment control signal line, a light emission reset control signal line, and a light emission reset voltage line arranged along the column direction.

[0020] In an embodiment of the present disclosure, the portion where the orthogonal projection of the voltage-adjusting control signal line on the substrate overlaps with the orthogonal projection of the second active semiconductor layer on the substrate is the second control pole of the voltage-adjusting transistor. The portion where the orthogonal projection of the light-emitting control signal line on the substrate overlaps with the orthogonal projection of the second active semiconductor layer on the substrate is the second control pole of the light-emitting reset transistor. The light-emitting reset voltage line is coupled to the second active semiconductor layer through a via to form the first pole of the light-emitting reset transistor.

[0021] In an embodiment of the present disclosure, the array substrate further includes a fourth conductive layer, the fourth conductive layer being located on a side of the third conductive layer away from the substrate and insulated and isolated from the third conductive layer, the fourth conductive layer including a first connection portion, a second connection portion, a third connection portion, a fourth connection portion, a fifth connection portion, a sixth connection portion, a seventh connection portion, and an eighth connection portion. The first connection portion operates as a driving reset voltage line. The first connection portion is coupled to a drain region of the driving reset transistor through a via to form a first pole of the driving reset transistor. The second connection portion is coupled to an emission reset voltage line through a via. The third connection portion is coupled to a drain region of the data write transistor through a via to form a first pole of the data write transistor. The fourth connection portion is coupled to a source region of the driving reset transistor and a source region of the compensation transistor through vias to form a second pole of the driving reset transistor and a second pole of the compensation transistor, respectively. The fourth connection is coupled to the source region of the voltage-regulating transistor through a via to form a second pole of the voltage-regulating transistor. The fifth connection is coupled to the gate of the drive transistor and the first pole of the storage capacitor through a via, and the fifth connection is coupled to the drain region of the voltage-regulating transistor through a via to form a first pole of the voltage-regulating transistor. The sixth connection is coupled to the drain region of the first light-emitting control transistor through a via to form a first pole of the first light-emitting control transistor. The seventh connection is coupled to the source region of the second light-emitting control transistor through a via to form a second pole of the second light-emitting control transistor, and the seventh connection is coupled to the source region of the light-emitting reset transistor through a via to form a second pole of the light-emitting reset transistor. The eighth connection is coupled to the source region of the light-emitting reset transistor through a via to form a first pole of the light-emitting reset transistor.

[0022] In an embodiment of the present disclosure, the array substrate further includes a fifth conductive layer located on a side of the fourth conductive layer away from the substrate and insulated and isolated from the fourth conductive layer. The fifth conductive layer includes a data signal line, a first power supply voltage line, and a second power supply voltage line arranged along the column direction. The data signal line extends along the column direction and is coupled to the third connection portion of the fourth conductive layer through a via.

[0023] The first power supply voltage line extends along the column direction and is coupled to the third connection portion of the fourth conductive layer through a via, and the second power supply voltage line extends along the column direction and is coupled to the seventh connection portion of the fourth conductive layer through a via.

[0024] A second aspect of the present disclosure provides a display panel including the array substrate of any of the first aspects.

[0025] A third aspect of the present disclosure provides a display device including any of the display panels of the second aspect.

[0026] Further aspects and scope of the application will become apparent from the description provided herein. It should be noted that each aspect of the present application may be practiced alone or in combination with one or more other aspects. In addition, the description and specific examples herein are for illustrative purposes only and are not intended to limit the scope of the present application.

[0027] The accompanying drawings described herein are only used for illustrating selected embodiments, not all possible implementations, and are not intended to limit the scope of the present application. [Brief explanation of the drawings]

[0028] [Figure 1] FIG. 2 is a block diagram of an array substrate of the present disclosure. [Figure 2] FIG. 2 is a block diagram of a sub-pixel according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a schematic diagram of the pixel circuit of FIG. 2 in an embodiment of the present disclosure. [Figure 4]4 is a timing diagram of signals driving the pixel circuit of FIG. 3 in accordance with an embodiment of the present disclosure; [Figure 5] 2A and 2B are schematic plan views of each layer of an array substrate according to an embodiment of the present disclosure. [Figure 6] 2A and 2B are schematic plan views of each layer of an array substrate according to an embodiment of the present disclosure. [Figure 7] 2A and 2B are schematic plan views of each layer of an array substrate according to an embodiment of the present disclosure. [Figure 8] 2A and 2B are schematic plan views of each layer of an array substrate according to an embodiment of the present disclosure. [Figure 9] 2A and 2B are schematic plan views of each layer of an array substrate according to an embodiment of the present disclosure. [Figure 10] 2A and 2B are schematic plan views of each layer of an array substrate according to an embodiment of the present disclosure. [Figure 11] 2A and 2B are schematic plan views of each layer of an array substrate according to an embodiment of the present disclosure. [Figure 12] 1 is a schematic diagram of a planar configuration of a pixel circuit including a stacked active semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer. [Figure 13] 13 is a schematic diagram of a cross-sectional configuration of an array substrate taken along line A1A2 in FIG. 12 in the embodiment of the present disclosure. [Figure 14] 13 is a schematic diagram of a cross-sectional configuration of an array substrate taken along line A1A2 in FIG. 12 in the embodiment of the present disclosure. [Figure 15] FIG. 2 is a block diagram of an array substrate according to an embodiment of the present disclosure. [Figure 16] FIG. 2 is a block diagram of an array substrate according to an embodiment of the present disclosure. [Figure 17] FIG. 2 is a block diagram of an array substrate according to an embodiment of the present disclosure. [Figure 18] 1 is a schematic diagram of a planar configuration of a pixel circuit including a stacked masking layer, an active semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer. [Figure 19] FIG. 1 is a schematic diagram illustrating a configuration of a display panel according to an embodiment of the present disclosure. [Figure 20] FIG. 1 is a schematic diagram illustrating a configuration of a display device according to an embodiment of the present disclosure. [Figure 21] FIG. 2 is a schematic diagram of a pixel circuit according to an embodiment of the present disclosure. [Figure 22] FIG. 2 is a schematic diagram of a masking layer in an embodiment of the present disclosure. [Figure 23] 1 is a plan view of a pixel circuit according to an embodiment of the present disclosure. [Figure 24] 1 is a plan view of a pixel circuit according to an embodiment of the present disclosure. [Figure 25] 1 is a plan view of a pixel circuit according to an embodiment of the present disclosure. [Figure 26] FIG. 2 is a schematic diagram of a cross-sectional configuration of an array substrate in an embodiment of the present disclosure. [Figure 27] FIG. 2 is a schematic diagram illustrating a circuit configuration of a pixel driving circuit in an embodiment of an array substrate according to the present disclosure. [Figure 28] FIG. 28 is a timing diagram of each node in the driving method of the pixel driving circuit of FIG. 27. [Figure 29] FIG. 1 is a configuration diagram of an embodiment of an array substrate according to the present disclosure. [Figure 30] FIG. 30 is a diagram illustrating the configuration of a light-shielding layer in FIG. 29. [Figure 31] FIG. 30 is a diagram showing the configuration of a first active layer in FIG. 29. [Figure 32] FIG. 30 is a diagram showing the configuration of the first gate layer in FIG. 29. [Figure 33] FIG. 30 is a diagram showing the configuration of the second gate layer in FIG. 29. [Figure 34] FIG. 30 is a diagram showing the configuration of a second active layer in FIG. 29. [Figure 35] FIG. 30 is a diagram showing the configuration of the third gate layer in FIG. 29. [Figure 36] FIG. 30 is a diagram showing the configuration of a first source / drain layer in FIG. 29. [Figure 37] FIG. 30 is a diagram showing the configuration of a light-shielding layer and a first active layer in FIG. 29. [Figure 38] FIG. 30 is a diagram showing the configuration of a light-shielding layer, a first active layer, and a first gate layer in FIG. 29. [Figure 39] FIG. 30 is a diagram showing the configuration of a light-shielding layer, a first active layer, a first gate layer, and a second gate layer in FIG. 29. [Figure 40] FIG. 30 is a diagram showing the configuration of a light-shielding layer, a first active layer, a first gate layer, a second gate layer, and a second active layer in FIG. 29. [Figure 41] FIG. 30 is a diagram showing the configuration of a light-shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, and a third gate layer in FIG. 29. [Figure 42] FIG. 1 is a configuration diagram of an embodiment of an array substrate according to the present disclosure. [Figure 43] FIG. 43 is a diagram showing the configuration of a second source / drain layer in FIG. 42. [Figure 44] FIG. 1 is a configuration diagram of an embodiment of an array substrate according to the present disclosure. [Figure 45] FIG. 45 is a diagram showing the configuration of a second source / drain layer in FIG. 44. [Figure 46] FIG. 10 is a schematic diagram of a configuration of a second initial signal line in another embodiment of the array substrate of the present disclosure. [Figure 47] FIG. 10 is a schematic diagram of a configuration of a second initial signal line in another embodiment of the array substrate of the present disclosure. [Figure 48] 43 is a cross-sectional view of the portion of dotted line B in FIG. 42. DETAILED DESCRIPTION OF THE INVENTION

[0029] Corresponding reference numerals indicate corresponding parts or features throughout the various views of these accompanying drawings.

[0030] First, please note that, unless the context clearly indicates otherwise, the singular forms of words used in this specification and the appended claims include the plural, and vice versa. Thus, references to the singular generally include the plural of the corresponding term. Similarly, the words "comprises" and "comprises" are to be interpreted as inclusive, rather than exclusive. Similarly, the terms "comprises" and "or" are to be interpreted inclusively, unless otherwise specified herein. When the term "examples" is used herein, particularly when following a group of terms, the "examples" are merely exemplary and explanatory and should not be considered exclusive or broad.

[0031] Additionally, the terms "a," "an," "the," "said," and "one or more" indicate the presence of one or more elements / components / etc., "plurality" means two or more, and the terms "comprise," "comprising," "including," and "having" are used to indicate open-ended inclusion and mean that more of the listed elements / components / etc. may be present. The terms "first," "second," and "third" are used as descriptive terms only and do not quantitatively limit their subject matter.

[0032] Additionally, in the accompanying drawings, thicknesses and areas of layers may be exaggerated for clarity. When a layer, region, or component is referred to as "on" another component, it means that it is located directly on the other component, or there may be other components in between. Conversely, when a component is said to be "directly" on another component, it means that there are no other intervening components.

[0033] In a typical array substrate, a reset voltage is supplied from the same reset voltage line to reset the light-emitting element and the pixel circuit. The value of the reset voltage is set taking into consideration the energy consumption level of the pixel circuit, the display effect after correction, and the non-illuminating state of the light-emitting element after reset. In this case, the power consumption of the pixel circuit, the display effect after correction, and the charging time of the light-emitting element after reset are not simultaneously optimized, which affects the power consumption, response speed, accuracy, and display effect of the pixel circuit.

[0034] At least some embodiments of the present disclosure provide an array substrate including two reset voltage lines: a driving reset voltage line and an emitting reset voltage line. The driving reset voltage line is coupled to a driving reset voltage terminal to provide a driving reset voltage. The emitting reset voltage line is coupled to a emitting reset voltage terminal to provide a emitting reset voltage. The driving reset voltage can be set taking into account the power consumption level and reset effect of the pixel circuit. When power consumption is relatively low, the pixel circuit can be more completely reset, improving the display effect. The emitting reset voltage line is coupled to the emitting reset voltage terminal to provide a emitting reset voltage. The emitting reset voltage is set to turn off the emitting element, thereby shortening the charging time until the emitting element turns on, increasing the response speed of the pixel circuit to an emitting signal, shortening the response time, and possibly improving accuracy.

[0035] Array substrates provided by embodiments of the present disclosure are described below in conjunction with the accompanying drawings, without limitation, and as described below, different features in these specific embodiments can be combined with each other without contradiction to result in new embodiments, all of which also fall within the scope of protection of the present disclosure.

[0036] FIG. 1 is a schematic diagram illustrating an array substrate 10 according to the present disclosure. As shown in FIG. 1, the array substrate 10 includes a substrate 300 and subpixels SPX arranged on the substrate 300 in multiple rows and columns. The substrate may be a glass substrate, a plastic substrate, or the like. The display area of ​​the substrate 300 includes a plurality of pixel units PX, each of which may include a plurality of subpixels SPX, e.g., three. The subpixels SPX are spaced apart along a row direction X and a column direction Y. The row direction X and the column direction Y are perpendicular to each other. At least one of the subpixels SPX includes a pixel circuit. The array substrate 10 also includes a driving reset voltage line and a light-emitting reset voltage line. The driving reset signal line is coupled to a driving reset voltage terminal and configured to provide a driving reset voltage thereto. The light-emitting reset voltage line is coupled to a light-emitting reset voltage terminal and configured to provide a light-emitting reset voltage thereto. Hereinafter, the voltage settings and positions of the driving reset signal line and the light-emitting reset control signal line will be described in detail with reference to circuit diagrams 5 to 11.

[0037] In the embodiment of the present disclosure, each pixel circuit includes a driving circuit, a voltage adjusting circuit, a driving reset circuit, a light emitting reset circuit, a data writing circuit, a compensation circuit, a memory circuit, and a light emitting control circuit. The pixel circuit will be described in detail below with reference to FIG. 2.

[0038] 2 shows a block diagram of a subpixel SPX according to some embodiments of the present disclosure. As shown in FIG. 2, the subpixel SPX includes a pixel circuit 100 and a light-emitting element 200. The pixel circuit 100 includes a drive circuit 110, a voltage adjustment circuit 120, a drive reset circuit 130, a light-emitting reset circuit 140, a data write circuit 150, a compensation circuit 160, a memory circuit 170, and a light-emitting control circuit 180.

[0039] 2, the driving circuit 110 includes a control end G, a first end F, and a second end S. The driving circuit 110 is configured to provide a driving current to the light emitting element 200 under the control of a control signal from the control end G.

[0040] The voltage adjustment circuit 120 is coupled to the control end G of the driving circuit 110, the first node N1, and the voltage adjustment control signal input end Stv. The voltage adjustment circuit 120 is configured to electrically connect the control end G of the driving circuit 110 to the first node N1 under the control of the voltage adjustment control signal from the voltage adjustment control signal input end.

[0041] The driving reset circuit 130 is coupled to the driving reset control signal input terminal Rst1, the first node N1, and the driving reset voltage terminal Vinit1, and is configured to provide a driving reset voltage from the driving reset voltage terminal Vinit1 to the voltage adjusting circuit 120 under the control of the driving reset control signal from the driving reset control signal input terminal Rst1 to reset the control terminal G of the driving circuit 110.

[0042] The light emitting reset circuit 140 is coupled to the light emitting reset control signal input terminal Rst2, the light emitting element 200, and the light emitting reset voltage terminal Vinit2. Furthermore, the light emitting reset circuit 140 is also coupled to the light emitting control circuit 180. The light emitting reset circuit 140 is configured to provide the light emitting reset voltage from the light emitting reset voltage terminal Vinit2 to the light emitting element 200 under the control of the light emitting reset control signal from the light emitting reset control signal input terminal Rst2 to reset the anode of the light emitting element 200.

[0043] The data write circuit 150 is coupled to a data signal input terminal Data, a scan signal input terminal Gate, and a first terminal F of the driving circuit 110. The data write circuit 150 is configured to provide a data signal from the data signal input terminal Data to the first terminal F of the driving circuit 110 under the control of a scan signal from the scan signal input terminal Gate.

[0044] The compensation circuit 160 is coupled to the second end S, the first node N1, and the compensation control signal input terminal Com of the drive circuit 110. The compensation circuit 160 is configured to provide threshold compensation to the drive circuit 110 in response to a compensation control signal from the compensation control signal input terminal Com.

[0045] In the embodiment of the present disclosure, the scan signal from the scan signal input terminal Gate and the compensation control signal from the compensation control signal input terminal Com are the same signal.

[0046] The storage circuit 170 is coupled to the first power supply voltage terminal VDD and the control terminal G of the driving circuit 110. The storage circuit 170 is configured to store a voltage difference between the first power supply voltage terminal VDD and the control terminal G of the driving circuit 110.

[0047] The light emission control circuit 180 is coupled to the light emission control signal input terminal EM, the first power supply voltage terminal VDD, the first terminal F and the second terminal S of the drive circuit 110, the light emission reset circuit 140, and the light emitting element 200. The light emission control circuit 180 is configured to apply a first power supply voltage from the first power supply voltage terminal VDD to the drive circuit 110 and apply a drive current generated by the drive circuit 110 to the light emitting element 200 under the control of the light emission control signal from the light emission control signal input terminal EM.

[0048] In some embodiments of the present disclosure, the light emission reset control signal from the light emission reset control signal input terminal Rst2 and the light emission control signal from the light emission control signal input terminal EM may be the same signal.

[0049] Additionally or alternatively, in some embodiments of the present disclosure, the emission reset control signal from the emission reset control signal input terminal Rst2 and the scan signal from the scan signal input terminal Gate may be the same signal.

[0050] The light emitting element 200 is coupled to the second power supply voltage terminal VSS, the light emitting reset circuit 140, and the light emitting control circuit 180. The light emitting element 200 emits light when driven by a driving current generated by the driving circuit 110. For example, the light emitting element 200 may be a light emitting diode or the like. The light emitting diode may be an organic light emitting diode (OLED) or a quantum dot light emitting diode (QLED) or the like.

[0051] In an embodiment of the present disclosure, the voltage adjustment control signal, scan signal, drive reset control signal, light emission reset control signal, compensation control signal, light emission control signal, and compensation control signal may be square waves, and the high level value may range from 0 to 15V, and the low level value may range from 0 to 15V, for example, the high level is 7V and the low level is -7V. The data signal may range from 0 to 8V, for example, 2 to 5V. The first power supply voltage Vdd may range from 3 to 6V. The second power supply voltage Vss may range from 0 to -6V.

[0052] Figure 3 shows a schematic diagram of the pixel circuit 100 of Figure 2. As shown in Figure 3, the drive circuit 110 includes a drive transistor T1, the voltage adjustment circuit 120 includes a voltage adjustment transistor T2, the drive reset circuit 130 includes a drive reset transistor T3, the light emission reset circuit 140 includes a light emission reset transistor T4, the data write circuit 150 includes a data write transistor T5, the compensation circuit 160 includes a compensation transistor T6, the storage circuit 170 includes a storage capacitor C, and the light emission control circuit 180 includes a first light emission control transistor T7 and a second light emission control transistor T8.

[0053] As shown in FIG. 3, a first pole of the driving transistor T1 is coupled to a first end F of the driving circuit 110, a second pole of the driving transistor T1 is coupled to a second end S of the driving circuit 110, and a gate of the driving transistor T1 is coupled to a control end G of the driving circuit 110. A first pole of the voltage-regulating transistor T2 is coupled to the control terminal G of the driving circuit 110, a gate of the voltage-regulating transistor T2 is coupled to the voltage-regulating control signal input terminal Stv, and a second pole of the voltage-regulating transistor T2 is coupled to the first node N1.

[0054] A first pole of the driving reset transistor T3 is coupled to the driving reset voltage terminal Vinit1, a gate of the driving reset transistor T3 is coupled to the driving reset control signal input terminal Rst1, and a second pole of the driving reset transistor T3 is coupled to the first node N1. A first pole of the light-emitting reset transistor T4 is coupled to the light-emitting reset voltage terminal Vinit2, a gate of the light-emitting reset transistor T4 is coupled to the light-emitting reset control signal input terminal Rst2, and a second pole of the light-emitting reset transistor T4 is coupled to the anode of the light-emitting element 200. Furthermore, the second pole of the light-emitting reset transistor T4 is further coupled to the second pole of the second light-emitting control transistor T8.

[0055] A first pole of the data write transistor T5 is coupled to the data signal input terminal Data, a gate of the data write transistor T5 is coupled to the scan signal input terminal Gate, and a second pole of the data write transistor T5 is coupled to the first terminal F of the drive circuit 110.

[0056] A first pole of the compensation transistor T6 is coupled to the second terminal S of the driving circuit 110, a gate of the compensation transistor T6 is coupled to the compensation control signal input terminal Com, and a second pole of the compensation transistor T6 is coupled to the first node N1.

[0057] A first pole of the storage capacitor C is coupled to a first power supply voltage terminal VDD, and a second pole of the storage capacitor C is coupled to a control terminal G of the drive circuit 110. The storage capacitor is configured to store a voltage difference between the first power supply voltage terminal VDD and the control terminal G of the drive circuit 110.

[0058] A first pole of the first light-emitting control transistor T7 is coupled to the first power supply voltage terminal VDD, a gate of the first light-emitting control transistor T7 is coupled to the light-emitting control signal input terminal EM, and a second pole of the first light-emitting control transistor T7 is coupled to the first terminal F of the drive circuit 110.

[0059] A first pole of the second light-emitting control transistor T8 is coupled to the second end S of the drive circuit 110, a gate of the second light-emitting control transistor T8 is coupled to the light-emitting control signal input end EM, and a second pole of the second light-emitting control transistor T8 is coupled to the anode of the light-emitting element 200.

[0060] In the embodiment of the present disclosure, the active layers of the voltage adjustment transistor T2 and the light-emitting reset transistor T4 may include an oxide semiconductor material, such as a metal oxide semiconductor material, and the active layers of the driving transistor T1, the driving reset transistor T3, the data write transistor T5, the compensation transistor T6, the first light-emitting control transistor T7, and the second light-emitting control transistor T8 may include a silicon semiconductor material.

[0061] In the embodiment of the present disclosure, when the light-emitting reset control signal and the light-emitting control signal are the same signal, the light-emitting reset transistor T4, the first light-emitting control transistor T7, and the second light-emitting control transistor T8 may be transistors of different types. For example, the light-emitting reset transistor T4 is an N-type transistor, while the first light-emitting control transistor T7 and the second light-emitting control transistor T8 are P-type transistors. The voltage adjustment transistor T2 may be an N-type transistor. The driving transistor T1, the driving reset transistor T3, the data write transistor T5, and the compensation transistor T6 may be P-type transistors.

[0062] In an embodiment of the present disclosure, when the light-emitting reset control signal and the light-emitting control signal are the same signal, the light-emitting reset transistor T4 and the data write transistor T5 are the same type of transistor. For example, the light-emitting reset transistor T4 and the data write transistor T5 are P-type transistors. The voltage adjustment transistor T2 may be an N-type transistor. The driving transistor T1, the driving reset transistor T3, the compensation transistor T6, the first light-emitting control transistor T7, and the second light-emitting control transistor T8 may be P-type transistors.

[0063] The transistors used in the embodiments of the present disclosure may be either P-type or N-type transistors. The electrodes of the selected type of transistor are appropriately connected to the electrodes of the corresponding transistors in the embodiments of the present disclosure, and corresponding high or low voltages are supplied to the corresponding voltage terminals. For example, in the case of an N-type transistor, its input terminal is the drain, its output terminal is the source, and its control terminal is the gate. In the case of a P-type transistor, its input terminal is the source, its output terminal is the drain, and its control terminal is the gate. Different types of transistors have different levels of control signals at their control terminals. For example, in the case of an N-type transistor, when the control signal is high, the N-type transistor is conductive, and when it is low, the N-type transistor is off. In the case of a P-type transistor, when the control signal is low, the P-type transistor is conductive, and when it is high, the P-type transistor is off. Examples of oxide semiconductors include indium gallium zinc oxide (IGZO). Silicon semiconductor materials can include low temperature polysilicon (LTPS) or amorphous silicon (e.g., hydrogenated amorphous silicon). Low temperature polysilicon refers to polysilicon crystallized from amorphous silicon, typically at temperatures below 600°C.

[0064] Furthermore, in the embodiments of the present disclosure, the pixel circuit of the sub-pixel may have a structure including other numbers of transistors, such as an 8T2C structure, a 7T1C structure, a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, in addition to the 8T1C (i.e., eight transistors and one capacitor) structure shown in FIG. 4, but is not limited to the embodiments of the present disclosure.

[0065] Figure 4 is a timing diagram of signals that drive the pixel circuit of Figure 3. As shown in Figure 3, the operation process of the pixel circuit 100 consists of three stages: a first stage P1, a second stage P2, and a third stage P3.

[0066] Hereinafter, the operation process of the pixel circuit of FIG. 4 will be described with reference to FIG. 3, taking as an example the case where the light emitting reset control signal and the light emitting control signal are the same signal, the voltage adjustment control signal and the scan signal are the same signal, the voltage adjustment transistor T2 and the light emitting reset transistor T4 are N-type transistors, and the driving transistor T1, the driving reset transistor T3, the data writing transistor T5, the compensation transistor T6, the first light emitting control transistor T7 and the second light emitting control transistor T8 are P-type transistors.

[0067] 4, in the first stage P1, a low level driving reset control signal RST, a high level scan signal GA, a high level light emitting control signal EMS, a high level voltage adjustment control signal STV, and a low level data signal DA are input. As shown in FIG. 4, the light emitting control signal EMS rises earlier than the start point of the first stage P1, i.e., earlier than the rise of the voltage adjustment control signal STV.

[0068] In the first phase P1, the gate of the driving reset transistor T3 receives a low-level driving reset control signal RST, causing the driving reset transistor T3 to conduct, thereby applying the driving reset voltage VINT1 to the first node N1. The gate of the voltage adjustment transistor T2 receives a high-level voltage adjustment control signal STV, causing the voltage adjustment transistor T2 to conduct, thereby applying the driving reset voltage VINT1 from the first node N1 to the gate of the driving transistor T1, resetting the gate of the driving transistor T1 and preparing the driving transistor T1 for data writing in the second phase P2. In embodiments of the present disclosure, the value of the driving reset voltage VINT1 can be set lower, for example, by increasing the reverse voltage of the first power supply voltage Vdd. This increases the difference between the gate of the driving transistor T1 and the voltage of the first pole in the second phase, thereby accelerating the data writing and compensation process in the second phase. Note that the effect of the driving reset voltage VINT1 on the driving transistor T1 tends to saturate as the driving reset voltage VINT1 increases in the reverse direction. The data writing and compensation process will be described later in the second phase P2. Also, in the first phase P1, the voltage of one pole of the storage capacitor C is the first power supply voltage Vdd, and the voltage of the other pole is the driving reset voltage VINT1, and the storage capacitor C is charged. In the embodiment of the present disclosure, the value of the driving reset voltage VINT1 may be in the range of −1 to −5 V, for example, −3 V, taking into account the impact of energy consumption of the data writing, compensation, and storage capacitor C charging circuits and the hardware limitations of the power supply. This reduces the time required for data writing and compensation while keeping the circuit energy consumption low, thereby improving the compensation effect during a certain period of time, for example, during the second phase P2, and thereby improving the display effect.

[0069] In the first stage P1, the gate of the light-emitting reset transistor T4 receives a high-level light-emitting control signal EMS, causing the light-emitting reset transistor T4 to conduct. This applies the light-emitting reset voltage VINT2 to the anode of the OLED, resetting the anode and preventing it from emitting light before the third stage P3. In the embodiment of the present disclosure, the value of the light-emitting reset voltage VINT2 is set so that the OLED is in a non-illuminated state, i.e., so that the OLED is positively biased to a near-on state. Specifically, when the second power supply voltage Vss ranges from 0 to -6 V, the value of the light-emitting reset voltage VINT2 ranges from -2 to -6 V, for example, and may be equal to the second power supply voltage Vss. This shortens the charging time of the PN junction of the OLED before lighting and shortens the response time of the OLED to the light-emitting signal. When the desired brightness is consistent, the probability of OLED brightness differences is reduced. As a result, brightness uniformity is improved and low-frequency flicker and low-gradation mura are reduced.

[0070] In the first stage P1, the gate of the data write transistor T5 receives a high-level scan signal GA, turning the data write transistor T5 off. The gate of the compensation transistor T6 receives a high-level scan signal GA, turning the compensation transistor T6 off. The gate of the first light-emitting control transistor T7 receives a high-level light-emitting control signal EMS, turning the first light-emitting control transistor T7 off. The gate of the second light-emitting control transistor T8 receives a high-level light-emitting control signal EMS, turning the second light-emitting control transistor T8 off.

[0071] In the second stage P2, a high level driving reset control signal RST, a low level scan signal GA, a high level light emitting control signal EMS, a high level voltage adjustment control signal STV and a high level data signal DA are input.

[0072] In the second phase P2, the gate of the data write transistor T5 receives the scan signal GA at a low level, causing the data write transistor T5 to conduct, thereby writing the high-level data signal DA to the first pole of the driving transistor T1, i.e., the first terminal F of the driving circuit 110. The gate of the compensation transistor T6 receives the scan signal GA at a low level, causing the compensation transistor T3 to conduct, thereby writing the high-level data signal DA at the first terminal F to the first node N1. The gate of the voltage adjustment transistor T2 receives the voltage adjustment control signal STV at a high level, causing the voltage adjustment transistor T2 to conduct, thereby writing the high-level data signal DA at the first node N1 to the gate of the driving transistor T1, i.e., the control terminal G of the driving circuit 110. Since the data write transistor T5, the driving transistor T1, the compensation transistor T6 and the voltage adjustment transistor T2 are all conductive, the data signal DA passes through the data write transistor T5, the driving transistor T1, the compensation transistor T6 and the voltage adjustment transistor T2 to recharge the storage capacitor C, that is, charge the gate of the driving transistor T1, that is, charge the control terminal G, and the voltage of the gate of the driving transistor T1 gradually increases.

[0073] In the second stage P2, the data write transistor T5 is conductive, so the voltage at the first terminal F is maintained at Vda. At the same time, due to the characteristics of the driving transistor T1 itself, when the voltage at the control terminal G rises to Vda+Vth, the driving transistor T1 is turned off, and the charging process is terminated. Here, Vda is the voltage of the data signal DA, and Vth is the threshold voltage of the driving transistor T1. In this embodiment, the driving transistor T1 is illustrated as a P-type transistor, so the threshold voltage Vth can be negative.

[0074] After the second stage P2, the voltage of the gate of the driving transistor T1 is Vda+Vth, that is, the voltage information of the data signal DA and the threshold voltage Vth is stored in the storage capacitor C, and in the subsequent third stage P3, it is used to compensate the threshold voltage of the driving transistor T1.

[0075] In the second stage P2, the gate of the driving reset transistor T3 receives a high-level driving reset control signal RST, turning the driving reset transistor T3 off. The gate of the light-emitting reset transistor T4 receives a high-level light-emitting reset control signal EMS, turning the light-emitting reset transistor T4 off. The gate of the first light-emitting control transistor T7 receives a high-level light-emitting control signal EMS, turning the first light-emitting control transistor T7 off. The gate of the second light-emitting control transistor T8 receives a high-level light-emitting control signal EMS, turning the second light-emitting control transistor T8 off.

[0076] In the third stage P3, a high level driving reset control signal RST, a high level scan signal GA, a low level light emitting control signal EMS, a low level voltage adjustment control signal STV, and a low level data signal DA are input. As shown in FIG. 4, in the embodiment of the present disclosure, the low level light emitting control signal EMS may be a low level effective pulse width modulation signal. As shown in FIG. 4, the fall of the light emitting control signal EMS is slower than the end point of the second stage P1, i.e., slower than the fall of the voltage adjustment control signal STV.

[0077] In the third stage P3, the gate of the first light-emitting control transistor T7 receives the light-emitting control signal EMS. According to an embodiment of the present disclosure, the light-emitting control signal EMS may be pulse-width modulated. When the light-emitting control signal EMS is at a low level, the first light-emitting control transistor T7 is conductive and applies the first power supply voltage Vdd to the first terminal F. The gate of the second light-emitting control transistor T8 receives the light-emitting control signal EMS. When the light-emitting control signal EMS is at a low level, the second light-emitting control transistor T8 is conductive and applies the driving current generated by the driving transistor T1 to the anode of the OLED.

[0078] In the third stage P3, the gate of the voltage adjustment transistor T2 receives the low-level voltage adjustment control signal Stv, turning off the voltage adjustment transistor T2. As described above, the active layer of the voltage adjustment transistor T2 contains an oxide semiconductor material, and its leakage current is 10-16 to 10-19 A. Compared with single-gate low-temperature polysilicon transistors and double-gate low-temperature polysilicon transistors, this has a smaller leakage current, further reducing electrical leakage from the memory circuit and improving brightness uniformity.

[0079] In the third stage P3, the gate of the light-emitting reset transistor T4 receives the light-emitting control signal EMS. When the light-emitting control signal EMS is at a high level, the light-emitting reset transistor T4 is conductive. A light-emitting reset voltage is provided to the anode of the OLED to reset the anode of the OLED. If the light-emitting control signal EMS is a pulse-width modulation signal, the anode of the OLED can be reset before each light emission of the OLED controlled by the light-emitting control signal EMS, thereby further improving brightness uniformity.

[0080] In addition, the gate of the driving reset transistor T3 receives a high level driving reset control signal RST, turning the driving reset transistor T3 off. The gate of the data write transistor T5 receives a high level scanning signal GA, turning the data write transistor T5 off. The gate of the compensation transistor T6 receives a high level scanning signal GA, turning the compensation transistor T6 off.

[0081] In the third stage P3, since the first light-emitting control transistor T7 is conductive, the voltage at the first terminal F is the first power supply voltage Vdd, and the voltage at the control terminal G is Vda+Vth, so it is understood that the driving transistor T1 is also conductive.

[0082] In the third stage P3, the anode and cathode of the OLED are applied with the first power supply voltage Vdd (high voltage) and the second power supply voltage Vss (low voltage), and the OLED emits light by being driven by the driving current generated by the driving transistor T1.

[0083] From the formula for the saturation current for driving transistor T1, the drive current ID for driving the OLED to emit light is calculated using the following formula: ID=K ( VGS - Vth ) 2 =K [ ( Vda + Vth - Vdd ) - Vth ] 2 =K ( Vda - Vdd ) 2

[0084] In the above formula, Vth is the threshold voltage of the drive transistor T1, VGS is the voltage between the gate and source of the drive transistor T1, and K is a constant. From the above formula, it can be seen that the drive current ID flowing through the OLED is not related to the threshold voltage Vth of the drive transistor T1, but only to the voltage Vda of the data signal DA, which makes it possible to correct the threshold voltage Vth of the drive transistor T1, solves the problem of threshold voltage drift of the drive transistor T1 due to process or long-term operation, eliminates the impact on the drive current ID, and improves the display effect.

[0085] For example, K in the above formula is expressed as follows: K = 0.5nCox(W / L),

[0086] Here, n is the electron mobility of the driving transistor T1, Cox is the unit gate capacitance of the driving transistor T1, W is the channel width of the driving transistor T1, and L is the channel length of the driving transistor T1.

[0087] In some embodiments of the present disclosure, the emission reset control signal RST, the compensation control signal COM, and the scan signal GA may be the same signal. The voltage adjustment transistor T2 is an N-type transistor, and the driving transistor T1, the driving reset transistor T3, the emission reset transistor T4, the data write transistor T5, the compensation transistor T6, the first emission control transistor T7, and the second emission control transistor T8 are P-type transistors. The operation process of the pixel circuit differs from the above embodiments in that, in the first stage P1, the emission reset transistor T4 receives a high-level scan signal GA, turning off. Since the emission reset voltage VINT2 is not provided to the anode of the light-emitting element OLED, the anode of the light-emitting element OLED is not reset. In the second stage P2, the emission reset transistor T4 receives a low-level scan signal GA, turning on. The emission reset voltage VINT2 is provided to the anode of the light-emitting element OLED, resetting the anode of the light-emitting element OLED. Other operation processes of the pixel circuit in the first time period P1, the second time period P2 and the third time period P3 are the same as those in the above embodiment, and therefore will not be described here.

[0088] Note that the relationship between the driving reset control signal RST, the scan signal GA, the light emitting control signal EMS, the voltage adjustment control signal STV, and the data signal DA and each stage is merely exemplary. The high level or low level periods of the driving reset control signal RST, the scan signal GA, the light emitting control signal EMS, the voltage adjustment control signal STV, and the data signal DA are merely exemplary. For example, the high level periods of the light emitting control signal EMS are the same.

[0089] 5 to 11 are schematic plan views of each layer of an array substrate according to an embodiment of the present disclosure. A description will be given of one pixel circuit shown in Fig. 3 as an example. In this pixel circuit, the light-emitting reset control signal RST and the light-emitting control signal EMS are the same signal, the voltage adjustment control signal COM and the scan signal GA are the same signal, and the voltage adjustment transistor T2 and the light-emitting reset transistor T4 are metal oxide transistors.

[0090] The positional relationship of each circuit in the pixel circuit on the substrate will be described later with reference to the accompanying Figures 5 to 11. Those skilled in the art will understand that the scales in the accompanying Figures 5 to 11 are drawing scales for easily expressing the positions of components and should not be considered as the actual scales of the components. The dimensions of the components can be selected by those skilled in the art based on practical requirements, and the present disclosure is not particularly limited in this regard.

[0091] In the embodiment of the present disclosure, the array substrate includes a first active semiconductor layer 310 located on a substrate 300 .

[0092] FIG. 5 is a schematic plan view of a first active semiconductor layer 310 on an array substrate in an embodiment of the present disclosure. In an exemplary embodiment of the present disclosure, the driving transistor T1, the driving reset transistor T3, the light-emitting reset transistor T4, the data write transistor T5, the compensation transistor T6, the first light-emitting control transistor T7, and the second light-emitting control transistor T8 in the pixel circuit are silicon transistors, for example, low-temperature polysilicon transistors. In an exemplary embodiment of the present disclosure, the first active semiconductor layer 310 is used to form the active regions of the driving transistor T1, the driving reset transistor T3, the light-emitting reset transistor T4, the data write transistor T5, the compensation transistor T6, the first light-emitting control transistor T7, and the second light-emitting control transistor T8. In an exemplary embodiment of the present disclosure, the first active semiconductor layer 310 includes a channel region pattern and a doped region pattern (i.e., a first source / drain region and a second source / drain region) of the transistor. In an embodiment of the present disclosure, the channel region pattern and the doped region pattern of each transistor are integrally formed.

[0093] In FIG. 5, dotted blocks indicate source / drain regions and channel regions in the first active semiconductor layer 310 that are used for each transistor.

[0094] As shown in FIG. 5, the first active semiconductor layer 310 includes, in the Y direction (column direction) and the X direction (row direction), a channel region T3-c of the driving reset transistor T3, a channel region T5-c of the data write transistor T5, a channel region T6-c of the compensation transistor T6, a channel region T1-c of the driving transistor T1, a channel region T7-c of the first light-emitting control transistor T7, and a channel region T8-c of the second light-emitting control transistor T8, in that order.

[0095] In an exemplary embodiment of the present disclosure, the first active semiconductor layer for the transistors may be composed of an integrally formed low-temperature polycrystalline silicon layer. The source and drain regions of each transistor may be made conductive by doping or the like to achieve electrical connection of the respective structures. That is, the first active semiconductor layer of the transistors is a monolithic pattern formed from p-silicon or n-silicon, and each transistor in the same pixel circuit includes a doped region pattern (i.e., a source region s and a drain region d) and a channel region pattern. The active layers of different transistors are separated from each other by doping structures.

[0096] 5, the first active semiconductor layer 310 further includes, along the Y direction and the X direction, a drain region T3-d of the driving reset transistor T3, a drain region T5-d of the data write transistor T5, a source region of the driving reset transistor T3 and a source region T3-s / T6-s of the compensation transistor T6, a source region T5-s of the data write transistor T5, a source region of the driving transistor T1 and a source region T1-s / T7-s of the first light-emitting control transistor T7, a drain region of the compensation transistor T6 and a drain region T6-d / T1-d / T8-d of the second light-emitting control transistor T8, a drain region T7-d of the first light-emitting control transistor T7, and a source region T8-s of the second light-emitting control transistor T8, in that order.

[0097] In the exemplary embodiment of the present disclosure, the first active semiconductor layer 310 may be formed of a silicon semiconductor material such as amorphous silicon or polycrystalline silicon. The source and drain regions may be regions containing n-type impurities or p-type impurities. For example, the source and drain regions of the first light-emitting control transistor T7, the data write transistor T5, the driving transistor T1, the compensation transistor T6, and the second light-emitting control transistor T8 may all be regions containing p-type impurities.

[0098] In the embodiment of the present disclosure, the array substrate further includes a first conductive layer 320 located on the side of the first active semiconductor layer away from the substrate.

[0099] 6 is a schematic plan view of a first conductive layer 320 of an array substrate in an embodiment of the present disclosure. As shown in FIG. 6, the first conductive layer 320 includes a driving reset control signal line RSTL1, a scan signal line GAL, a first pole C1 of a capacitor C, and an emission control signal line EML, which are arranged in this order along the Y direction. The first conductive layer 320 further includes a driving reset control signal line RSTL1' of an adjacent pixel circuit along the Y direction. The function of the driving reset control signal line RSTL1' of the adjacent pixel circuit on the adjacent pixel circuit is the same as the function of the driving reset control signal line RSTL1 on this pixel circuit, so a description thereof will be omitted here.

[0100] In the embodiment of the present disclosure, the light emitting control signal line EML and the light emitting control signal input terminal EM are configured to provide a light emitting control signal EMS to the light emitting control signal input terminal EM.

[0101] In an embodiment of the present disclosure, the scan signal line GAL is coupled to the scan signal input terminal Gate and the compensation control signal input terminal Com, and is configured to provide the scan signal GA to the scan signal input terminal Gate and to provide the compensation control signal COM to the compensation control signal input terminal Com.

[0102] In the embodiment of the present disclosure, the first pole C1 of the capacitor C and the gate T1-g of the driving transistor T1 are integrally formed.

[0103] In the embodiment of the present disclosure, the driving reset control signal line RSTL1 is coupled to the driving reset control signal input terminal Rst1 and configured to provide the driving reset control signal RST to the driving reset control signal input terminal Rst1.

[0104] 5 and 6, in an embodiment of the present disclosure, a portion where the orthogonal projection of the drive reset control signal line RSTL1 onto the substrate overlaps with the orthogonal projection of the portion 311 of the first active semiconductor layer 310 onto the substrate is the gate T3-g of the drive reset transistor T3 in the pixel circuit. A portion where the orthogonal projection of the scan signal line GAL onto the substrate overlaps with the orthogonal projection of the portion 311 of the first active semiconductor layer 310 onto the substrate is the gate T6-g of the compensation transistor T6 and the gate T5-g of the data write transistor T5 in the pixel circuit. A portion where the orthogonal projection of the first pole C1 of the capacitor C onto the substrate overlaps with the orthogonal projection of the portion 311 of the first active semiconductor layer 310 onto the substrate is the gate T1-g of the drive transistor T1 in the pixel circuit. The areas where the orthogonal projection of the light-emission control signal line EML onto the substrate overlaps with the orthogonal projection of portion 311 of the first active semiconductor layer 310 onto the substrate are the gate T7-g of the first light-emission control transistor T7 and the gate T8-g of the second light-emission control transistor T8 in the pixel circuit, respectively.

[0105] 6, in the Y direction, the gate T3-g of the driving reset transistor T3, the gate T6-g of the compensation transistor T6, and the gate T5-g of the data write transistor T5 are located on a first side of the gate T1-g of the driving transistor T1, and the gate T7-g of the first light-emitting control transistor T7 and the gate T8-g of the first light-emitting control transistor T8 are located on a second side of the gate T1-g of the driving transistor T1.

[0106] The first and second sides of the gate T1-g of the driving transistor T1 are opposite sides of the gate T1-g of the driving transistor T1 in the Y direction. For example, as shown in FIG. 6, in the XY plane, the first side of the gate T1-g of the driving transistor T1 may be the upper side of the gate T1-g of the driving transistor T1. The second side of the gate T1-g of the driving transistor T1 may be the lower side of the gate T1-g of the driving transistor T1. In the present disclosure, the "lower side" refers to, for example, the side to which an IC of the array substrate is attached. For example, the lower side of the gate T1-g of the driving transistor T1 may be the side of the gate T1-g of the driving transistor T1 that is closer to the IC (not shown) of the gate T1-g of the driving transistor T1. The upper side is the side facing the lower side, and may be, for example, the side away from the IC of the gate T1-g of the driving transistor T1.

[0107] Specifically, the gate T3-g of the driving reset transistor T3 is located above the gate T6-g of the compensation transistor T6 and the gate T5-g of the data write transistor T5. The gate T3-g of the driving reset transistor T3 and the gate T1-gt of the driving transistor T1 are aligned in the Y direction.

[0108] 6, in the X direction, the gate T5-g of the data write transistor T5 and the gate T7-g of the first light-emitting control transistor T7 are located on the third side of the gate T1-g of the driving transistor T1, and the gate T6-g of the compensation transistor T6 and the gate T8-g of the second light-emitting control transistor T8 are located on the fourth side of the gate T1-g of the driving transistor T1.

[0109] The third side and the fourth side of the gate T1-g of the driving transistor T1 are opposite sides of the gate T1-g of the driving transistor T1 in the X direction. For example, as shown in FIG. 6, in the XY plane, the third side of the gate T1-g of the driving transistor T1 may be on the left side of the gate T1-g of the driving transistor T1. The fourth side of the gate T1-g of the driving transistor T1 may be on the right side of the gate T1-g of the driving transistor T1.

[0110] Specifically, the gate T7-g of the first light-emitting control transistor T7 is located to the left of the gate T5-g of the data write transistor T5, and the gate T8-g of the second light-emitting control transistor T8 is located to the right of the gate T6-g of the compensation transistor T6.

[0111] The active regions of the transistors shown in FIG. 6 correspond to the regions where the first conductive layer 320 and the first active semiconductor layer 310 overlap.

[0112] In an embodiment of the present disclosure, the array substrate further includes a second conductive layer located on a side of the first conductive layer away from the substrate and insulated and isolated from the first conductive layer.

[0113] 7 is a schematic plan view of a second conductive layer 330 on an array substrate according to an embodiment of the present disclosure. As shown in FIG. 7, the second conductive layer 330 includes a voltage adjustment control signal line STVL, a second capacitor C2, a first power supply voltage line VDL, and a light emission reset control signal line RSTL2, which are arranged along the Y direction. The second conductive layer 330 also includes a light emission reset control signal line RSTL2' of an adjacent pixel circuit along the Y direction. The function of the light emission reset control signal line RSTL2' of the adjacent pixel circuit on the adjacent pixel circuit is the same as the function of the light emission reset control signal line RSTL2 on the adjacent pixel circuit, and therefore a description thereof will be omitted here.

[0114] In an embodiment of the present disclosure, referring to FIGS. 6 and 7, the projections of the second pole C2 of the capacitor C and the first pole C1 of the capacitor C onto the substrate at least partially overlap.

[0115] In an embodiment of the present disclosure, as shown in FIG. 7 , the first power supply voltage line VDL extends in the X direction and is integral with the second pole C2 of the capacitor C. The first power supply voltage line is coupled to the first power supply voltage terminal VDD and configured to provide the first power supply voltage Vdd thereto. The voltage adjustment control signal line STVL is coupled to the voltage adjustment control signal input terminal Stv and configured to provide the voltage adjustment control signal STV thereto. The light emitting reset control signal line RSTL2 is coupled to the light emitting reset control signal input terminal Rst2 and configured to provide the light emitting reset control signal thereto. In an embodiment of the present disclosure, the light emitting reset control signal and the scan signal EMS are the same signal.

[0116] In the embodiment of the present disclosure, as shown in FIG. 7 , the voltage adjustment control signal line STVL is located on the first side of the capacitor's second pole C2 in the Y direction. The first power supply signal line VDL and the light emission reset control signal line RSTL2 are located on the second side of the capacitor's second pole C2. Similar to the description of the first and second sides of the gate T1-g of the drive transistor T1 above, the first and second sides of the capacitor's second pole C2 are opposite sides of the capacitor's second pole C2 in the Y direction. The first side of the capacitor's second pole C2 is the upper side of the capacitor's second pole C2 in the Y direction, and the second side of the capacitor's second pole C2 is the lower side of the capacitor's second pole C2 in the Y direction.

[0117] Specifically, in the Y direction, the voltage adjustment control signal line STVL is located above the second pole C2 of the capacitor, and the first power supply signal line VDL and the light emission reset control signal line RSTL2 are located below the second pole C2 of the capacitor.

[0118] In an embodiment of the present disclosure, as shown in Figure 7, a first gate T2-g1 of the voltage adjustment transistor T2 is provided on the voltage adjustment control signal line STVL. A first gate T4-g1 of the light emission reset transistor T4 is provided on the light emission reset control signal line RSTL2. The locations of the first gate T2-g1 of the voltage adjustment transistor T2 and the first gate T4-g1 of the light emission reset transistor T4 will be described in detail below with reference to Figure 8.

[0119] Specifically, as shown in FIG. 7, in the Y direction, the first gate T2-g1 of the voltage adjustment transistor T2 is located on a first side of the first gate T4-g1 of the light-emitting reset transistor T4. Similar to the description of the first side of the gate T1-g of the drive transistor T1 above, the first side of the first gate T4-g1 of the light-emitting reset transistor T4 is located above the first gate T4-g1 of the light-emitting reset transistor T4. In other words, the first gate T2-g1 of the voltage adjustment transistor T2 is located above the first gate T4-g1 of the light-emitting reset transistor T4. In the X direction, the first gate T2-g1 of the voltage adjustment transistor T2 and the first gate T4-g1 of the light-emitting reset transistor T4 are located at the same position.

[0120] In an embodiment of the present disclosure, the array substrate further includes a second active semiconductor layer located on a side of the second conductive layer away from the substrate and electrically isolated from the second conductive layer.

[0121] FIG. 8 illustrates a schematic plan view of a second active semiconductor layer 340 on an array substrate according to an embodiment of the present disclosure. As illustrated in FIG. 8, the second active semiconductor layer 340 includes a first portion 341 and a second portion 342, arranged in order in the Y direction. The first portion 341 of the second active semiconductor layer 340 and the second portion 342 of the second active semiconductor layer 340 are aligned with each other. In the exemplary embodiment of the present disclosure, the second active semiconductor layer 340 is used to form the active layers of the voltage-adjusting transistor T2 and the light-emitting reset transistor T4. Specifically, the first portion 341 of the second active semiconductor layer 340 is used to form the active layer of the voltage-adjusting transistor T2. The second portion 342 of the second semiconductor layer 340 is used to form the active layer of the voltage-adjusting transistor T7. In an exemplary embodiment of the present disclosure, similar to the first active semiconductor layer 310, the second active semiconductor layer 340 includes a channel pattern and a doped region pattern of the transistor (i.e., a first source / drain region and a second source / drain region of the transistor).

[0122] In FIG. 8, the dotted blocks indicate the areas for the source / drain regions and channel regions of each transistor in the second active semiconductor layer 340.

[0123] 8, the first portion 341 of the second active semiconductor layer 340 includes, in order along the Y direction, a source region T2-s of the voltage adjustment transistor T2, a channel region T2-c of the voltage adjustment transistor T2, and a drain region T2-d of the voltage adjustment transistor T2. The second portion 342 of the second active semiconductor layer 340 includes, in order along the Y direction, a source region T4-s of the light-emitting reset transistor T4, a channel region T4-c of the light-emitting reset transistor T4, and a drain region T4-d of the light-emitting reset transistor T4.

[0124] 7 and 8, in the embodiment of the present disclosure, the portion where the orthogonal projection of the voltage adjustment control signal line STVL onto the substrate overlaps with the orthogonal projection of the second active semiconductor layer 340 onto the substrate is the first gate T2-g1 of the voltage adjustment transistor T2. The channel region T8-c of the voltage adjustment transistor T2 and the projection of the first gate T2-g1 of the voltage adjustment transistor T2 onto the substrate completely overlap. The portion where the orthogonal projection of the light-emitting control signal line RSTL2 onto the substrate overlaps with the orthogonal projection of the second active semiconductor layer 340 onto the substrate is the first gate T4-g1 of the light-emitting reset transistor T4. The channel region T4-c of the light-emitting reset transistor T4 and the projection of the first gate T4-g1 of the light-emitting reset transistor T4 onto the substrate completely overlap.

[0125] In an exemplary embodiment of the present disclosure, the second active semiconductor layer 340 may be formed of an oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide). The source and drain regions may be regions containing n-type impurities or p-type impurities. For example, the source and drain regions of the voltage adjustment transistor T2 and the light-emitting reset transistor T4 are both regions containing n-type impurities.

[0126] In an embodiment of the present disclosure, the array substrate further includes a third conductive layer located on a side of the second active semiconductor layer away from the substrate and insulated and isolated from the second active semiconductor layer.

[0127] 9 is a schematic plan view of a third conductive layer 350 on an array substrate according to an embodiment of the present disclosure. As shown in FIG. 9, the third conductive layer 350 includes a voltage adjustment control signal line STVL, a light emitting reset control signal line RSTL2, and a light emitting reset voltage line VINL2. The third conductive layer 350 also includes a light emitting reset control signal line RSTL2' and a light emitting reset voltage line VINL2' of an adjacent pixel circuit along the Y direction. The functions of the light emitting reset control signal line RSTL2' and the light emitting reset voltage line VINL2' of an adjacent pixel circuit on the adjacent pixel circuit are the same as those of the light emitting reset control signal line RSTL2 and the light emitting reset voltage line VINL2 on the adjacent pixel circuit, and therefore will not be described here.

[0128] Specifically, as shown in FIG. 9, the voltage adjustment control signal line STVL, the light emission reset control signal line RSTL2, and the light emission reset voltage line VINL2 are provided in this order in the Y direction.

[0129] 9, in the embodiment of the present disclosure, the second gate T2-g2 of the voltage adjustment transistor T2 is provided on the voltage adjustment control signal line STVL. The second gate T4-g2 of the light-emitting reset transistor T4 is provided on the light-emitting reset control signal line RSTL2. Specifically, the portion where the orthogonal projection of the voltage adjustment control signal line STVL onto the substrate overlaps with the orthogonal projection of the second active semiconductor layer 340 onto the substrate is the second gate T2-g2 of the voltage adjustment transistor T2. The portion where the orthogonal projection of the light-emitting reset control signal line RSTL2 onto the substrate overlaps with the orthogonal projection of the second active semiconductor layer 340 onto the substrate is the second gate T4-g2 of the light-emitting reset transistor T4.

[0130] Similar to the first gate T2-g1 of the voltage adjustment transistor T2 and the first gate T4-g1 of the light-emitting reset transistor T4 shown in FIG. 7, as shown in FIG. 9, in the Y direction, the second gate T2-g2 of the voltage adjustment transistor T2 is located on a first side of the second gate T4-g2 of the light-emitting reset transistor T4. The first side of the second gate T4-g2 of the light-emitting reset transistor T4 is above the second gate T4-g2 of the light-emitting reset transistor T4. That is, the second gate T2-g2 of the voltage adjustment transistor T2 is located above the second gate T4-g2 of the light-emitting reset transistor T4. In the X direction, the second gate T2-g2 of the voltage adjustment transistor T2 and the second gate T4-g2 of the light-emitting reset transistor T4 are located at the same position.

[0131] 7, 8, and 9, in the embodiment of the present disclosure, the projections of the second gate T2-g2 of the voltage adjusting transistor T2, the channel region T2-c of the voltage adjusting transistor T2, and the first gate T2-g1 of the voltage adjusting transistor T2 onto the substrate completely overlap. The projections of the second gate T4-g2 of the emission reset transistor T4, the channel region T4-c of the emission reset transistor T4, and the first gate T4-g1 of the emission reset transistor T4 onto the substrate completely overlap.

[0132] In the embodiments of the present disclosure, an insulating layer or a dielectric layer is provided between adjacent active semiconductor layers and conductive layers, or between adjacent conductive layers. Specifically, an insulating layer or a dielectric layer (described below with reference to cross-sectional views) is provided between the first active semiconductor layer 310 and the first conductive layer 320, between the first conductive layer 320 and the second conductive layer 330, between the second conductive layer 330 and the second active semiconductor layer 340, between the second active semiconductor layer 340 and the third conductive layer 350, between the third conductive layer 350 and the fourth conductive layer 360 (described below with reference to FIG. 12), and between the fourth conductive layer 360 and the fifth conductive layer 370 (described below with reference to FIG. 11).

[0133] The vias referred to below are vias in insulating or dielectric layers that penetrate between adjacent active semiconductor layers and conductive layers or are provided between adjacent conductive layers. Specifically, the vias are vias in the insulating or dielectric layers that penetrate between the first active semiconductor layer 310 and the first conductive layer 320, between the first conductive layer 320 and the second conductive layer 330, between the second conductive layer 330 and the second active semiconductor layer 340, between the second active semiconductor layer 340 and the third conductive layer 350, between the third conductive layer 350 and the fourth conductive layer 360, and between the fourth conductive layer 360 and the fifth conductive layer 370.

[0134] In the drawings of the present disclosure, regions corresponding to vias are indicated by white circles. Referring to FIG. 9, the light-emitting reset voltage line VINL2 is coupled to the second active semiconductor layer 340 through a via 3501 to form the first pole T4-1 of the light-emitting reset transistor T4. Specifically, referring to FIGS. 8 and 9, the light-emitting reset voltage line VINL2 in FIG. 9 overlaps with the projection onto the substrate of the drain region T7-d of the light-emitting reset transistor T4 in the second portion 342 in FIG. 8. The light-emitting reset voltage line VINL2 is coupled to the drain region T4-d of the light-emitting reset transistor T4 through the via 3501.

[0135] In an embodiment of the present disclosure, the array substrate further includes a fourth conductive layer located on a side of the third conductive layer away from the substrate and insulated and isolated from the third conductive layer.

[0136] FIG. 10 is a schematic plan view of a fourth conductive layer 360 in an array substrate according to an embodiment of the present disclosure. As shown in FIG. 10 , the fourth conductive layer 360 includes a first connection portion 361, a second connection portion 362, a third connection portion 363, a fourth connection portion 364, a fifth connection portion 365, a sixth connection portion 366, a seventh connection portion 367, and an eighth connection portion 368. The fourth conductive layer 360 also includes a ninth connection portion 369 of an adjacent pixel circuit along the Y direction. The ninth connection portion 369 and its via 3691 may be the first connection portion 361 and its via 3611 of an adjacent pixel circuit. The specific connection method and function are similar to those of the first connection portion 361 and its via 3611 of the pixel circuit, and therefore will not be described here. For the sake of clarity, the first connection portion 361 and its via 3611 of the adjacent pixel circuit are provided as described above.

[0137] In the embodiment of the present disclosure, the second connection portion 362, the third connection portion 363, the fourth connection portion 364, the fifth connection portion 365, the sixth connection portion 366, the seventh connection portion 367, and the eighth connection portion 368 are provided on the second side of the first connection portion 361. Similar to the second side of the gate T1-g of the driving transistor T1, in the XY coordinate system, the second side of the first connection portion 361 is the lower side of the first connection portion 361. That is, the second connection portion 362, the third connection portion 363, the fourth connection portion 364, the fifth connection portion 365, the sixth connection portion 366, the seventh connection portion 367, and the eighth connection portion 368 are provided on the lower side of the first connection portion 361. The third connection portion 363 and the sixth connection portion 366 are provided in order along the Y direction. The second connection portion 362, the fourth connection portion 364, the fifth connection portion 365, the seventh connection portion 367, and the eighth connection portion 368 are arranged in this order along the Y direction. The second connection portion 362, the fourth connection portion 364, the fifth connection portion 365, the seventh connection portion 367, and the eighth connection portion 368 are located on the third side of the third connection portion 363 and the sixth connection portion 366. Similar to the third side of the gate T1-g of the driving transistor T1 described above, the third side of the third connection portion 363 and the sixth connection portion 366 is to the right of the third connection portion 363 and the sixth connection portion 366 in the XY plane. In other words, the second connection portion 362, the fourth connection portion 364, the fifth connection portion 365, the seventh connection portion 367, and the eighth connection portion 368 are located on the right of the third connection portion 363 and the sixth connection portion 366.

[0138] The first connection portion 361 is coupled to the first active semiconductor layer 310 through a via 3611. Specifically, the first connection portion 361 is coupled to the drain region T3-d of the driving reset transistor T3 through the via 3611, forming a first pole T3-1 of the driving reset transistor T3. The first connection portion 361 operates as a driving reset voltage line VINL1.

[0139] The second connection portion 362 is coupled to the third conductive layer 350 through a via 3621. Specifically, the second connection portion 362 is coupled to the light emission reset voltage line VINL2 through the via 3621.

[0140] The third connection portion 363 is coupled to the first active semiconductor layer 310 through a via 3631. Specifically, the third connection portion 363 is coupled to the drain region T5-d of the data write transistor T5 through the via 3631, forming a first pole T5-1 of the data write transistor T5.

[0141] The fourth connection portion 364 is coupled to the first active semiconductor layer 310 through a via 3641. Specifically, the fourth connection portion 364 is coupled to the source region T3-s / T6-s of the driving reset transistor T3 and the source region T3-s / T6-s of the compensation transistor T6 through the via 3641, forming a second pole of the driving reset transistor T3 and a second pole T3-2 / T6-2 of the compensation transistor T6. The fourth connection portion 364 is coupled to the second active semiconductor layer 340 through a via 3642. Specifically, the fourth connection portion 364 is coupled to the source region T2-s of the voltage adjustment transistor T2 through the via 3642, forming a second pole T2-2 of the voltage adjustment transistor T2.

[0142] The fifth connection 365 is coupled to the third conductive layer 330 through a via 3651. The fifth connection 365 is coupled to the second conductive layer 320 through a via 3652. Specifically, the fifth connection 365 is coupled to the gate T1-g of the driving transistor T1 and the first pole C1 of the capacitor C through the via 3652. The fifth connection 365 is coupled to the second active semiconductor layer 340 through a via 3653. Specifically, the fifth connection 365 is coupled to the drain region T2-d of the voltage-regulating transistor T2 through the via 3653, forming the first pole T2-1 of the voltage-regulating transistor T2.

[0143] The sixth connection portion 366 is coupled to the first active semiconductor layer 310 through a via 3662. Specifically, the sixth connection portion 366 is coupled to the drain region T7-d of the first light-emitting control transistor T7 through the via 3662, forming a first pole T7-1 of the first light-emitting control transistor T7.

[0144] The seventh connection portion 367 is coupled to the first active semiconductor layer 310 through a via 3671. Specifically, the seventh connection portion 367 is coupled to the source region T8-s of the second light-emitting control transistor T8 through the via 3671, forming a second pole T8-2 of the second light-emitting control transistor T8. The seventh connection portion 367 is coupled to the second active semiconductor layer 340 through a via 3672. Specifically, the seventh connection portion 367 is coupled to the source region T4-s of the light-emitting reset transistor T4 through the via 3672, forming a second pole T4-2 of the light-emitting reset transistor T4.

[0145] The eighth connection portion 368 is coupled to the second active semiconductor layer 340 via a via 3681. Specifically, the eighth connection portion 368 is coupled to the source region T4-d of the light-emitting reset transistor T4 via the via 3681, forming a first pole T4-1 of the light-emitting reset transistor T4. The eighth connection portion 368 and its via 3682 may also serve as the second connection portion 362 and its via 3621 of an adjacent pixel circuit along the Y direction. The specific connection method and function thereof are similar to those of the second connection portion 362 and its via 3621 of the pixel circuit, and therefore will not be described here. For the purpose of illustrating the drawing, the second connection portion 362 and its via 3621 of the adjacent pixel circuit are provided as described above.

[0146] In an embodiment of the present disclosure, the array substrate further includes a fifth conductive layer located on a side of the fourth conductive layer away from the substrate and insulated and isolated from the fourth conductive layer.

[0147] FIG. 11 is a schematic plan view of a fifth conductive layer 370 in an array substrate according to an embodiment of the present disclosure. As shown in FIG. 11, the fifth conductive layer includes a data signal line DAL, a first power supply voltage line VDL, and a second power supply voltage line VSL arranged along the row direction X. The data signal line DAL extends in the column direction Y and is coupled to the third connection portion 363 of the fourth conductive layer 360 via a via 3711. The first power supply voltage line VDL extends in the column direction Y and is coupled to the third connection portion 363 of the fourth conductive layer 360 via a via 3721. The second power supply voltage line VSL extends in the column direction Y and is coupled to the seventh connection portion 367 of the fourth conductive layer 360 via a via 3731. In this embodiment of the present disclosure, the second power supply voltage line VSL extends in the column direction Y for a distance shorter than those of the data signal line DAL and the first power supply voltage line VDL. The second power supply voltage line VSL may be the cathode of a light emitting element, for example, an OLED.

[0148] In the embodiment of the present disclosure, the first power supply voltage line VDL has a closed rectangular component 371. Referring to Figures 8 and 11, the orthogonal projection onto the substrate of the second side of the rectangular component 371 extending in the Y direction, which is arranged along the row direction X, overlaps with the orthogonal projection onto the substrate of the first portion 341 of the second active semiconductor layer 340. This configuration isolates the second active semiconductor layer 340 from the sealing layer arranged adjacent to the fifth conductive layer 370 on the side of the fifth conductive layer 370 away from the substrate, and prevents hydrogen in the sealing layer from destabilizing the properties of the oxide material, such as the metal oxide material, in the second active semiconductor layer 340.

[0149] In the embodiment of the present disclosure, the orthogonal projection of the second power supply voltage line VSL onto the substrate overlaps with the orthogonal projection onto the substrate of the second portion 342 of the second active semiconductor layer 340. The configuration and operation of the second power supply voltage line VSL are similar to those of the first power supply voltage line VDL described above, and can isolate the second active semiconductor layer 340 from the encapsulation layer adjacent to the fifth conductive layer 370 on the side of the fifth conductive layer 370 away from the substrate, thereby preventing hydrogen in the encapsulation layer from destabilizing the properties of oxide materials, such as metal oxide materials, in the second active semiconductor layer 340.

[0150] 12 shows a schematic diagram of a planar configuration including a pixel circuit (here, an array substrate) of a stacked first active semiconductor layer, a first conductive layer, a second conductive layer, a second active semiconductor layer, a third conductive layer, and a fourth conductive layer. As shown in FIG. 12, the schematic diagram 380 of the planar configuration includes a first active semiconductor layer 310, a first conductive layer 320, a second conductive layer 330, a second active semiconductor layer 340, a third conductive layer 350, a fourth conductive layer 360, and a fifth conductive layer 370. For clarity, Figure 12 shows the gate T1-g of the drive transistor T1, the gate T2-g of the voltage adjustment transistor T2, the gate T3-g of the drive reset transistor T3, the gate T4-g of the light-emission reset transistor T4, the gate T5-g of the data write transistor T5, the gate T6-g of the compensation transistor T6, the first plate C1 of the storage capacitor C, the gate T7-g of the first light-emission control transistor T7, and the gate T8-g of the second light-emission control transistor T8. Figure 12 also shows a line break A1A2 passing through the array substrate where the via 3651, the gate T6-g of the compensation transistor T6, and the gate T2-g of the voltage adjustment transistor T2 are located. A cross-sectional view taken along line A1A2 will now be described with reference to Figure 13.

[0151] 13 shows a schematic diagram of a cross-sectional configuration of an array substrate taken along line A1A2 in FIG. 12 in an embodiment of the present disclosure. As shown in FIG. 13, referring to FIGS. 5 to 12, the array substrate 10 includes a substrate 300, a first buffer layer 101 located on the substrate 300, and a first active semiconductor layer 310 located on the first buffer layer 101. The cross-sectional view shows a channel region T6-c of a compensation transistor T6 included in the first active semiconductor layer 310.

[0152] 13 , the array substrate 10 further includes a first gate insulating layer 102 covering the first buffer layer 101 and the first active semiconductor layer 310, and a first conductive layer 320 located on a side of the first gate insulating layer 102 away from the substrate 300. The cross section shows a scan signal line GAL included in the first conductive layer 320. As shown in FIG. 13 , a portion where the orthogonal projection of the scan signal line GAL onto the substrate 300 overlaps with the orthogonal projection onto the substrate 300 of the channel region T6-c of the compensation transistor T6 included in the first active semiconductor layer 310 is the gate T6-g of the compensation transistor T6.

[0153] 13 , the array substrate 10 further includes a first interlayer insulating layer 103 located on the side of the first conductive layer 320 away from the substrate 300, and a second conductive layer 330 located on the side of the first interlayer insulating layer 103 away from the substrate 300. The cross-sectional view shows a voltage adjustment control signal line STVL and a connection portion 331 included in the second conductive layer. The voltage adjustment control signal line STVL includes a first gate T2-g1 of the voltage adjustment transistor T2.

[0154] 13 , the array substrate 10 further includes a second interlayer insulating layer 104 located on a side of the second conductive layer 330 away from the substrate 300, a second buffer layer 105 covering the second interlayer insulating layer 104, and a second active semiconductor layer 340 located on a side of the second buffer layer 105 away from the substrate 300. The cross-sectional view shows the channel region T2-c of the voltage-adjusting transistor T2, whose orthogonal projection onto the substrate 300 overlaps with the orthogonal projection onto the substrate 300 of the first gate T2-g1 of the voltage-adjusting transistor T2 on the voltage-adjusting control signal line STVL.

[0155] 13 , the array substrate 10 further includes a second gate insulating layer 106 covering the second active semiconductor layer 340 and the second buffer layer 105, and a third conductive layer 350 located on the side of the second gate insulating layer 106 away from the substrate 300. The cross-sectional view shows that the third conductive layer 350 includes a voltage adjustment control signal line STVL. As shown in FIG. 13 , a portion where the orthogonal projection of the voltage adjustment control signal line STVL onto the substrate 300 overlaps with the orthogonal projection onto the substrate 300 of the channel region T2-c of the voltage adjustment transistor T2 included in the second active semiconductor layer 320 is the second gate T2-g2 of the voltage adjustment transistor T2.

[0156] 13 , the array substrate 10 further includes a third interlayer insulating layer 107 covering the third conductive layer 350 and the second gate insulating layer 106, and a fourth conductive layer 360 located on the side of the third interlayer insulating layer 107 away from the substrate 300. Referring to FIG. 10 , the cross-sectional view includes a fifth connection portion 365. The fifth connection portion 365 is coupled to the connection portion 331 on the second conductive layer 330 through a via 3651.

[0157] 13, in the embodiment of the present disclosure, the array substrate 10 further includes a first planar layer 108 covering the fourth conductive layer 360 and the third interlayer insulating layer 107, and a fifth conductive layer 370 located on the side of the first planar layer 108 away from the substrate 300. The cross-sectional view shows the first power supply voltage line VDL.

[0158] In the embodiment of the present disclosure, as shown in FIG. 13, the array substrate 10 further includes a fifth conductive layer 370 and a second planar layer 109 covering the first planar layer 108 .

[0159] 14 shows a schematic diagram of a cross-sectional configuration of an array substrate taken along line A1A2 in FIG. 12 in an embodiment of the present disclosure. In the embodiment of the present disclosure, as shown in FIG. 14, the array substrate 10 further includes a masking layer 400 located between the substrate 100 and the first buffer layer 101.

[0160] When the substrate 300 is a light-transmitting substrate, the masking layer 400 is configured to at least partially block light incident on the active semiconductor layer of the pixel circuit transistor from the side of the substrate 300 where the pixel circuit is not provided, in order to prevent light degradation of the transistor. On the other hand, the masking layer 400 is configured to prevent particles emitted from the substrate from entering the pixel circuit. Furthermore, if the emitted particles enter the active semiconductor layer, they can degrade the performance of the transistor. Furthermore, if the particles are charged particles, once embedded in the pixel circuit structure (e.g., the dielectric layer of the circuit structure), they can interfere with various signal voltages input to the pixel circuit, affecting display performance. For example, when the substrate 300 is a polyimide substrate, it is undesirable for the polyimide material to always contain various impurity ions. Therefore, during thermal exposure processes (e.g., growth of the active semiconductor layer, sputtering or evaporation of conductive layers such as metals) in the fabrication of the array substrate, these impurity ions are released from the substrate 300 and enter the pixel circuit.

[0161] In some embodiments of the present disclosure, the masking layer 400 may not be biased (i.e., overhanging). A voltage bias may be applied to the masking layer 400 to further improve the shielding effect. According to some embodiments of the present disclosure, the voltage applied to the masking layer may be a constant voltage. The voltage applied to the masking layer may be any of a first power supply voltage Vdd (anode voltage of the light-emitting element), a second power supply voltage Vss (cathode voltage of the light-emitting element), a driving reset voltage VINT1, etc. According to some embodiments of the present disclosure, the voltage applied to the masking layer may be selected from the ranges of −10V to +10V, −5V to +5V, −3V to +3V, −1V to +1V, or −0.5V to +0.5V. According to some embodiments of the present disclosure, the voltage applied to the masking layer may be selected from the ranges of −0.3V, −0.2V, 0V, 0.1V, 0.2V, 0.3V, or 10.1V. According to an embodiment of the present disclosure, the voltage applied to the masking layer may be greater than the second power supply voltage Vss and less than the first power supply voltage Vdd, or the voltage applied to the masking layer may be greater than the driving reset voltage VINT1 and less than the first power supply voltage Vdd.

[0162] FIG. 15 is a schematic block diagram of an array substrate according to an embodiment of the present disclosure. FIG. 15 illustrates a configuration of a masking layer 400a. In this configuration, the masking layer 400a completely covers the substrate 300 in the area of ​​the array substrate 10 having pixel cells (i.e., the display area). The cross-sectional structure of FIG. 14 corresponds to this configuration. By completely covering the display area of ​​the array substrate, optimal protection of the masking layer can be achieved.

[0163] 16 is a schematic block diagram of an array substrate according to an embodiment of the present disclosure. Figure 16 shows another configuration of a masking layer 400b that does not completely cover the substrate 300 in the region having pixel cells (i.e., the display region) of the array substrate 10. In this configuration, the masking layer 400b includes first strips 401 extending along the row direction X and spaced apart from each other along the column direction Y, and second strips 402 extending along the column direction Y and spaced apart from each other along the row direction X. The first strips 401 and the second strips 402 have the same width (i.e., the size in the direction perpendicular to the direction in which the strips extend). Note that the orthogonal projection onto the substrate 300 of the portion where the first strip 401 and the second strip intersect at least partially overlaps with the orthogonal projection onto the substrate 300 of the active region 3101 of the drive transistor T1 (i.e., the channel region T1-c, source region T1-s, and drain region T1-d that constitute the drive transistor T1 of the first active semiconductor layer 310). This configuration not only sufficiently protects the active region of the drive transistor T1, which is an important part of the pixel circuit, but also ensures the continuity of the entire masking layer 400b and reduces undesired overlap between the masking layer 400b and wiring on the array substrate 10, thereby reducing undesired parasitic effects such as parasitic capacitance.

[0164] FIG. 17 shows a block diagram of an array substrate according to an embodiment of the present disclosure. FIG. 17 shows the configuration of another masking layer 400c, which is similar to the configuration of the masking layer 400b in FIG. 16. Similarly, the masking layer 400c does not completely cover the substrate 300 in the region of the array substrate 10 having pixel units (i.e., the display region). In this configuration, the masking layer 400b includes a body 410 located at each subpixel, a first connection portion 420 for connecting to the body 410 along the row direction X, and a second connection portion 430 for connecting to the body 410 along the column direction Y. The size Sc1 of the first connection portion 420 along the column direction is smaller than the size Sb1 of the body 410 along the column direction, and the size Sc2 of the second connection portion 430 along the row direction is smaller than the size Sb2 of the body 410 along the row direction. Note that in this disclosure, the term "size" refers to the maximum size of a component. This configuration further reduces unwanted overlap between the masking layer and the wiring on the array substrate, thereby suppressing potential parasitic capacitance.

[0165] In an embodiment of the present disclosure, the size Sc1 of the first connection portion 420 along the column direction may be the same as the size Sc2 of the second connection portion 430 along the row direction. Note that the size Sc1 of the first connection portion 420 along the column direction may be different from the size Sc2 of the second connection portion 430 along the row direction. The size Sc1 of the first connection portion 420 along the column direction may be smaller than the size Sc2 of the second connection portion 430 along the row direction.

[0166] The inventors have found that the data line DAL (shown in FIG. 11 ) of the pixel cell extending in the column direction Y is more sensitive to parasitic interference than the gate signal lines (drive reset control signal line RSTL1, scan signal line GAL, light emission control signal line EML) of the pixel circuit extending in the row direction X. Therefore, by reducing the size Sc1 of the first connecting portion 420 along the column direction and increasing the size Sc2 of the second connecting portion 430 along the row direction, it is possible to ensure conductivity of the entire masking layer while suppressing the influence of parasitic effects, and therefore it is possible to ensure that when a voltage bias is applied to the blocking layer, the bias voltage is uniform across the entire blocking layer.

[0167] 18 shows a plan view of a pixel circuit including a masking layer, an active semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked together. In the plan view 381 shown in FIG. 18, a masking layer 401c has the configuration shown in FIG. 17. The masking layer 401c includes a body 411 located in each subpixel, a first connection portion 421 for connection to the body 411 along the row direction, and a second connection portion 431 for connection to the body 410 along the column direction. The size Sc1 of the first connection portion 421 along the column direction is smaller than the size Sb1 of the body 410 along the column direction, and the size Sc2 of the second connection portion 430 along the row direction is smaller than the size Sb2 of the body 410 along the column direction. In this configuration, the shape and size of the body 411 are configured to at least partially overlap the active region 3101 of the drive transistor T1 and at least partially overlap the fifth connection 365 of the fourth conductive layer 360 in a direction perpendicular to the substrate. In the embodiment of the present disclosure, at least 10% of the area of ​​the fifth connection overlaps with the body 411 in a direction perpendicular to the substrate. For illustrative purposes, FIG. 18 only shows a state in which the body 411 completely overlaps the active region 3101 of the drive transistor T1 and the fifth connection 365 of the fourth conductive layer 360, but this does not limit the scope of the present disclosure. Because the fifth connection 365 is connected to the gate of the drive transistor T1, masking the fifth connection 365 can effectively prevent charged particles from affecting the gate voltage of the drive transistor T1 and ensure proper image display.

[0168] Furthermore, in the masking layer configurations shown in FIGS. 17 and 18 , the size (width) Sc2 of the second connecting portions 430, 431 along the row direction may be variable along the column direction. In the embodiments of the present disclosure, the width of the portion of the second connecting portion overlapping with the wiring extending in the row direction for signals having a relatively high frequency may be larger than the width of the portion of the second connecting portion overlapping with the wiring extending in the row direction for signals having a relatively low frequency. Examples of wiring extending in the row direction for signals having a relatively high frequency include the light-emission control signal line EML and the scan signal line GAL. The higher the signal frequency, the greater the parasitic effect. In this manner, this configuration can effectively reduce the masking layer's restriction on interference with high-frequency signals. Similarly, the width of the portion of the first connecting portion overlapping with the wiring extending in the column direction for signals having a relatively low frequency may be larger than the width of the portion of the first connecting portion overlapping with the wiring extending in the column direction for signals having a relatively low frequency.

[0169] Furthermore, in the embodiments of the present disclosure, the width of the portion where the second connection portion overlaps with the wiring extending in the row direction and having a certain signal may be larger than the width of the portion where the second connection portion overlaps with the wiring extending in the row direction and having no certain signal. Similarly, the width of the portion where the first connection portion overlaps with the wiring extending in the column direction and having a certain signal may be larger than the width of the portion where the first connection portion overlaps with the wiring extending in the column direction and having no certain signal. FIG. 19 is a schematic diagram showing the structure of a display panel according to an embodiment of the present disclosure. As shown in FIG. 19, a display panel 700 may include an array substrate 20 according to any embodiment of the present disclosure or an array substrate including pixel circuits 100 according to any embodiment of the present disclosure.

[0170] For example, the display panel 700 may include other components such as a timing controller, a signal decoding circuit, a voltage conversion circuit, etc., which may be, for example, conventional components already available, and therefore will not be described in detail here.

[0171] For example, the display panel 700 may be a rectangular panel, a circular panel, an elliptical panel, a polygonal panel, etc. Furthermore, the display panel 700 may be not only a flat panel but also a curved panel or even a spherical panel. For example, the display panel 700 may have a touch function, i.e., the display panel 700 may be a touch display panel.

[0172] An embodiment of the present disclosure provides a display device including the display panel according to any of the embodiments of the present disclosure.

[0173] 20 is a schematic diagram illustrating a configuration of a display device according to an embodiment of the present disclosure. As shown in FIG. 20, a display device 800 may include a display panel 700 according to any of the embodiments described in the present disclosure.

[0174] The display device 800 may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.

[0175] 21 shows a pixel circuit with a 7T1C structure consisting of seven transistors and one capacitor. In the pixel circuit, the active layers of transistors T1 and T2 are made of an oxide semiconductor material, and transistors T1 and T2 may be N-type oxide transistors. The active layers of transistors T3 to T7 are made of a silicon semiconductor material, for example, low-temperature polycrystalline silicon.

[0176] Figure 22 shows a masking layer for the circuit shown in Figure 21. Figure 26 shows the location of the masking layer 0, which in this embodiment is located between the active semiconductor layer and the substrate, and is insulated and isolated from at least the active semiconductor layer.

[0177] FIG. 23 shows the planar configuration of each functional layer (semiconductor layer and conductive layer) of a pixel circuit including a light-shielding layer. The oxide semiconductors T1 and T2 have a mirror image design, and the masking layer masks the silicon semiconductor material. As shown in FIG. 23, the planar configuration of the pixel circuit including the light-shielding layer also has a mirror image design as a whole. In embodiments of the present disclosure, the mirror image design may be, for example, the planar configuration of the pixel circuit including the light-shielding layer shown in FIGS. 24 and 29. Here, as shown in FIG. 23, Da is the data signal terminal Data[m] access point in FIG. 21, Vinit_OLED is the initial signal terminal Vinit_OLED access point in FIG. 21, N1 is the potential point of node N1 in FIG. 21, where N1 is located in the first source-drain layer, N4 is the potential point of node N4 in FIG. 21, ELVDD is the power supply terminal potential point in FIG. 21, and ELVDD is located in the first source-drain layer. The masking layer satisfies at least one of the following conditions:

[0178] 1. The masking layer body is covered with silicon semiconductor material, and the area of ​​the masking layer covering the N1 node is greater than 10%, so as to stabilize the N1 node. 2. To reduce the parasitic capacitance on the oxide film, there is no overlap between the masking layer and the oxide film channel, or the overlap area is less than 90%. 3. The overlapping area between the masking layer and the initialization signal line is minimized to reduce the load on the initialization signal line. In this configuration, the overlap is limited to the alignment above and to the side, avoiding alignment within the arc at the T7 position. For example, as shown in FIG. 29, the orthogonal projection of the conductive portion 47 onto the substrate is bent and extended to reduce the overlap between the light-shielding layer and the second initialization signal line Vinit2. 4. The initialization signal line can be thinned at the position where it overlaps with the masking layer, and the masking layer can also be thinned in the same way.

[0179] 24 shows a planar configuration of a pixel circuit according to one embodiment of the present disclosure. The connecting lines along the row and column directions of the masking layer avoid the scan lines and other parasitic effects. N1 in FIG. 24 is the potential point of node N1 in FIG. 21, where N1 is located in the first source-drain layer.

[0180] According to an embodiment of the present disclosure, biasing of the masking layer can be achieved in the following manner.

[0181] 1. The signal line can be extended to the periphery for constant potential connection, and electrically connected via a signal line around the periphery. It does not have to be a full circle, as long as signal access is possible. The wrap can be achieved using one or more layers of gate1, gate2, SD1, SD2, and ITO layers. This method is shown in Figure 25. 2. Electrical connections are made in the AA area, but other signal connection holes must be avoided.

[0182] Example 3: When using a VDD or Vint signal, it is possible to connect the VDD line and the Vint line by drilling a hole at the position where they overlap.

[0183] In a specific embodiment, the SD1 and SD2 layers are source / drain electrode layers, and the material thereof may include a metal material such as molybdenum, aluminum, copper, titanium, niobium, any one of these, an alloy thereof, or a molybdenum / titanium alloy or laminate, or may be a titanium / aluminum / titanium laminate.

[0184] In a specific implementation, the gate1 and gate2 layers are gate electrode film layers, and can be made of the same material and / or the same layer as the gate of the oxide transistor. For example, the material can be molybdenum, aluminum, copper, titanium, niobium, any one of these or an alloy thereof, a molybdenum / titanium alloy, a laminate, etc. The potential applied to the masking layer may be the same potential as that applied to the power supply line VDD (voltage source potential), or the same potential as that applied to the initialization signal line, or the same potential as that applied to the cathode (cathode potential VSS), or another fixed potential, for example, a fixed potential in the range of -10V to +10V, or for example, a fixed potential in the range of -5V to +5V, or for example, a fixed potential in the range of 3V to +3V, or for example, a fixed potential in the range of -1V to +1V, or for example, a fixed potential in the range of -0.5V to +0.5V, or for example, a fixed potential in the range of 0V, or for example, a fixed potential in the range of 0.1V, or for example, a fixed potential in the range of 10.1V, or for example, a fixed potential in the range of 0.2V, or for example, a fixed potential in the range of -0.2V, or for example, a fixed potential in the range of 0.3V, or for example, a fixed potential in the range of -0.3V.

[0185] Specifically, the potential applied to the light-shielding layer is greater than the potential applied to the cathode (cathode potential VSS) and less than the potential applied to the power supply line VDD, or greater than the potential applied to the initialization signal line and less than the potential applied to the power supply line VDD.

[0186] Specifically, the masking layer can be made of an amorphous silicon material, a metal material, an oxide semiconductor material such as IGZO, a polycrystalline silicon material, a semiconductor material after being made conductive, or the like.

[0187] 27 is a schematic diagram of a circuit configuration of a pixel driving circuit in an embodiment of an array substrate of the present disclosure. The pixel driving circuit may include a driving transistor T3, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. Here, the first pole of the fourth transistor T4 is connected to the data signal terminal Da, the second pole is connected to the first pole of the driving transistor T3, the gate is connected to the second gate driving signal terminal G2, the first pole of the fifth transistor T5 is connected to the first power supply terminal VDD, the second pole is connected to the first pole of the driving transistor DT, the gate is connected to the enable signal terminal EM, the gate of the driving transistor T3 is connected to node N, the first pole of the second transistor T2 is connected to node N, the second pole is connected to the second pole of the driving transistor T3, and the gate is connected to the first gate driving signal terminal G The sixth transistor T6 has a first pole connected to the second pole of the driving transistor T3, a second pole connected to the first pole of the seventh transistor T7, a gate connected to the enable signal terminal EM, a second pole of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and a gate connected to the second reset signal terminal Re2. The first transistor T1 has a first pole connected to the node N, a second pole connected to the first initial signal terminal Vinit1, and a gate connected to the first reset signal terminal Re1. A capacitor C is connected between the first power supply terminal VDD and the node N. The pixel driving circuit includes an emitting unit OLED that drives the emitting unit OLED to emit light, and the emitting unit OLED may be connected between the second pole of the sixth transistor T6 and the second power supply terminal VSS. Here, the first transistor T1 and the second transistor T2 may be N-type metal oxide transistors, which have a small leakage current and prevent the node N from leaking current through the first transistor T1 and the second transistor T2 during the light-emitting stage.In addition, the driving transistor T3, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be low-temperature polysilicon transistors, which have high carrier mobility and can realize a display panel with high resolution, high response rate, high pixel density, and high aperture ratio. The first initial signal terminal and the second initial signal terminal can output the same or different voltage signals according to actual circumstances.

[0188] 28 shows a timing diagram of each node in the driving method of the pixel driving circuit of FIG. 27. Here, G1 indicates the timing of the first gate driving signal terminal G1, G2 indicates the timing of the second gate driving signal terminal G2, Re1 indicates the timing of the first reset signal terminal Re1, Re2 indicates the timing of the second reset signal terminal Re2, EM indicates the timing of the enable signal terminal EM, and Da indicates the timing of the data signal terminal Da. The driving method of the pixel driving circuit includes a first reset stage t1, a compensation stage t2, a second reset stage T3, and a light-emitting stage t4. First reset stage t1: The first reset signal terminal Re1 outputs a high-level signal, the first transistor T1 is conductive, and the first initial signal terminal Vinit1 inputs an initial signal to the node N. Compensation stage t2: The first gate driving signal terminal G1 outputs a high-level signal, the second gate driving signal terminal G2 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 output a driving signal to the data signal terminal Da to write a voltage Vdata+Vth to the node N, where Vdata is the voltage of the driving signal and Vth is the threshold voltage of the driving transistor T3. Second reset stage t3: The second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs an initial signal to the second pole of the sixth transistor T6. Light-emitting stage t4: The enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light according to the voltage Vdata+Vth stored in the capacitor C. The driving transistor output current formula is I=(μWCox / 2L)(Vgs-Vth).2 where μ is the carrier mobility, Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. In the pixel driving circuit of the present disclosure, the output current I of the driving transistor is expressed as I=(μWCox / 2L)(Vdata+Vth-Vdd-Vth). 2 The pixel drive circuit can avoid the influence of the drive transistor threshold on its output current.

[0189] The array substrate includes a substrate, a light-shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, and a first source / drain layer, which are stacked in this order. As shown in FIGS. 29-41, FIG. 29 is a structural diagram of an embodiment of an array substrate of the present disclosure. FIG. 30 is a structural diagram of the light-shielding layer in FIG. 29. FIG. 31 is a structural diagram of the first active layer in FIG. 29. FIG. 32 is a structural diagram of the first gate layer in FIG. 29. FIG. 33 is a structural diagram of the second gate layer in FIG. 29. FIG. 34 is a structural diagram of the second active layer in FIG. 29. FIG. 35 is a structural diagram of the third gate layer in FIG. 29. FIG. 36 is a structural diagram of the first source / drain layer in FIG. 29. FIG. 37 is a structural diagram of the light-shielding layer and the first active layer in FIG. 29. FIG. 38 is a structural diagram of the light-shielding layer, the first active layer, and the first gate layer in FIG. 29. Figure 39 is a configuration diagram of the light-shielding layer, first active layer, first gate layer, and second gate layer in Figure 29. Figure 40 is a configuration diagram of the light-shielding layer, first active layer, first gate layer, second gate layer, and second active layer in Figure 29. Figure 41 is a configuration diagram of the light-shielding layer, first active layer, first gate layer, second gate layer, second active layer, and third gate layer in Figure 29.

[0190] As shown in Figures 29, 30, 37, 38, 39, 40, and 41, the light-shielding layer includes a plurality of overlapping units 0 and connection portions 02 connected between the overlapping units 0. Here, the overlapping units 0 include two light-shielding portions 01 arranged symmetrically along dotted line A, where dotted line A extends in a second direction Y. As shown in Figure 30, the light-shielding portion 01 may include a first light-shielding portion 011, a second light-shielding portion 012, a third light-shielding portion 013, and a fourth light-shielding portion 014. Here, the orthogonal projections of the second light-shielding portion 012 and the third light-shielding portion 013 onto the substrate extend in the second direction Y, and the orthogonal projection of the fourth light-shielding portion 014 onto the substrate extend in the first direction X. The second light-shielding portion 012 and the third light-shielding portion 013 are connected to both sides of the first light-shielding portion 011 in the second direction Y, and the orthogonal projection of the second light-shielding portion 012 onto the substrate and the orthogonal projection of the third light-shielding portion 013 onto the substrate are spaced a predetermined distance apart in the first direction X. The fourth light-shielding portion 014 is located on one side of the first light-shielding portion in the first direction X. In the same overlapping unit 0, two first light-shielding portions 011 adjacent in the first direction X are connected. In two overlapping units 0 adjacent in the first direction X, two adjacent light-shielding portions 011 are connected by their respective fourth light-shielding portions 014. Two adjacent light-shielding portions 01 in the second direction Y are connected by a connecting portion 02, where the connecting portion 02 is connected to the second light-shielding portion 012 and the third light-shielding portion 013 of the two light-shielding portions 01, respectively, and the orthogonal projection of the connecting portion 02 onto the substrate extends in the first direction X. The first direction X and the second direction Y may intersect; for example, the first direction X is the row direction and the second direction is the column direction.

[0191] 29, 31, 37, 38, 39, 40, and 41, the first active layer may include active portions 54, 53, 55, and 57. Here, active portion 54 is used to form the channel region of the fourth transistor T4, active portion 53 is used to form the channel region of the drive transistor T3, active portion 55 is used to form the channel region of the fifth transistor T5, and active portion 57 is used to form the channel region of the seventh transistor T7. The first active layer may be formed of a polycrystalline silicon semiconductor material.

[0192] As shown in Figures 29, 32, 38, 39, 40, and 41, the first gate layer may include a second gate drive signal line G2, an enable signal line EM, a second reset signal line Re2, and a conductive portion 11. Orthogonal projections of the second gate drive signal line G2, the enable signal line EM, and the second reset signal line Re2 onto the substrate extend in a first direction X. Here, the second gate drive signal line G2 is used to provide the second gate drive signal terminal of Figure 27, the enable signal line EM is used to provide the enable signal terminal of Figure 27, and the second reset signal line Re2 is used to provide the second reset signal terminal of Figure 27. The orthogonal projection of the second gate drive signal line G2 onto the substrate covers the orthogonal projection of the active portion 54 onto the substrate, and a portion of the second gate drive signal line G2 is used to form the gate of the fourth transistor T4. The orthogonal projection of the enable signal line EM onto the substrate covers the orthogonal projection of the active portion 55 onto the substrate, and the configuration of a portion of the enable signal line EM is used to form the gate of the fifth transistor T5. The orthogonal projection of the second reset signal line Re2 onto the substrate covers the orthogonal projection of the active portion 57 onto the substrate, and the configuration of a portion of the second reset signal line Re2 is used to form the gate of the seventh transistor T7. The orthogonal projection of the conductive portion 11 onto the substrate covers the orthogonal projection of the active portion 53 onto the substrate, and the conductive portion 11 is used to form the gate of the drive transistor T3. The conductive portion 11 can also form an electrode of the capacitor C. Here, the first active layer can be doped using the first gate layer as a mask so that the first active layer covered by the first gate layer forms a semiconductor structure and the portion not covered by the first gate layer forms a conductor structure.

[0193] As shown in FIGS. 29, 33, 39, 40, and 41, the second gate layer may include a first initial signal line Vinit1, a first reset signal line Re1, a first gate drive signal line G1, a conductive portion 21, and a connecting portion 22. The first initial signal line Vinit1, the first reset signal line Re1, and the first gate drive signal line G1 are all orthogonally projected onto the substrate in a first direction. Here, the first initial signal line Vinit1 is used to provide the first initial signal terminal of FIG. 27, the first reset signal line Re1 is used to provide the first reset signal terminal of FIG. 27, and the first gate drive signal line G1 is used to provide the first gate drive signal terminal of FIG. 27. The conductive portion 21 is the other electrode of the capacitor C. Adjacent conductive portions 21 in the first direction X are connected by a connecting portion 22, and through-holes 211 may be formed in the conductive portions 21.

[0194] 29, 34, 40, and 41, the second active layer includes an active portion 6, which includes an active portion 61 and an active portion 62, where the active portion 61 forms a channel region of the first transistor T1, and the active portion 62 forms a channel region of the second transistor T2. Here, as shown in FIG. 40, the active portion 6 is located on the side of the active portion 61 away from the active portion 62 and is connected to the first initial signal line Vinit1 through a via 71, and is connected to the second pole of the first transistor T1 and the first initial signal line Vinit1. Here, the second active layer may be formed of a metal oxide semiconductor material, such as indium gallium zinc oxide.

[0195] As shown in Figures 29, 35, and 41, the third gate layer may include gate lines 3Re1, 3G1, and 3Re1. Here, the orthogonal projection of the gate line 3Re1 onto the substrate extends in a first direction, and the orthogonal projection of the gate line 3Re1 onto the substrate and the orthogonal projection of the first reset signal line Re1 onto the substrate at least partially overlap. The gate line 3Re1 is connected to the first reset signal line Re1 by at least one via, which is located in the non-display area or the display area of ​​the display panel. The orthogonal projection of the gate line 3G1 onto the substrate extends in a first direction, and the orthogonal projection of the gate line 3G1 onto the substrate at least partially overlaps with the orthogonal projection of the first gate drive signal line G1 onto the substrate. The gate line 3G1 is connected to the first gate drive signal line G1 by at least one via, which is located in the non-display area or the display area of ​​the display panel. The second active layer can be formed by making it conductive using the third gate layer as a mask, i.e., the portion of the second active layer covered with the third gate layer can form a semiconductor structure, and the portion not covered with the third gate layer can form a conductor structure.

[0196] 29 and 36, the first source-drain layer may include conductive portions 41, 42, 43, 44, 45, 46, 47, and a second initial signal line Vinit2. The second initial signal line Vinit2 is connected to the conductive portion 47 and used to provide the second initial signal terminal of FIG. 27. The orthogonal projection of the second initial signal line Vinit2 onto the substrate partially overlaps with the orthogonal projection of the first reset signal line Re1 onto the substrate. The conductive portion 41 is connected to the active portion 6 through a via 72 and to the first initial signal line Vinit1 through a via 73, which connects the second pole of the first transistor T1 and the first initial signal line Vinit1. The conductive portion 41 further improves the contact efficiency between the active portion 6 and the first initial signal line Vinit1. Conductive portion 42 is connected to a position between active portions 61 and 62 of active portion 6 through via 7, and is also connected to conductive portion 11 through via 75, and is connected to the first electrode of first transistor T1 and the gate of driving transistor T3. Here, via 75 penetrates through hole 211 on conductive portion 21, and the conductor embedded in via 75 is not connected to conductive portion 21. Conductive portion 43 is connected to connection portion 22 through via 76, and is also connected to the first active layer on the side of active portion 55 through via 77, and is connected to capacitor C and the first electrode of fifth transistor T5. Conductive portion 44 is connected to the first active layer between active portions 57 and 56 through via 78, and is connected to the second electrode of sixth transistor T6, where conductive portion 44 is used to connect to the anode of the light-emitting unit. Conductive portion 45 is connected to the side of active portion 62 of active portion 6 away from active portion 61 through via 710, and is connected to the first active layer on the side of active portion 53 through via 711, and is used for the second pole of second transistor T2 and the second pole of drive transistor T3. Conductive portion 46 is connected to connection portion 22 through via 712, and may be connected to a power supply line for providing the first power supply signal terminal VDD in FIG. 27. Conductive portion 47 is connected to the first active layer on the side of active portion 57 through via 79, and is connected to the second initial signal line Vinit2 and the second pole of seventh transistor T7.

[0197] 29 and 39, in this exemplary embodiment, the orthogonal projection of the fourth light-shielding portion 014 onto the substrate and the orthogonal projection of the connecting portion 22 onto the substrate at least partially overlap with each other. This configuration minimizes the sheltering effect of the fourth light-shielding portion 014 on light rays, improving the transmittance of the array substrate.

[0198] 29 and 39, the orthogonal projection of the connection portion 02 onto the substrate and the orthogonal projection of the first reset signal line Re1 onto the substrate at least partially overlap. This configuration also minimizes the light shelter effect of the connection portion 02, improving the transmittance of the array substrate. Furthermore, because the first reset signal line Re1 is located in the second gate layer and has a large distance from the light-shielding layer, the capacitive coupling effect of the connection portion 02 with the first reset signal line Re1 is small. Compared to providing the connection portion 02 below the gate line in the first gate layer, this configuration can reduce the capacitive coupling effect of the connection portion 02 with the gate line.

[0199] 29, 33, and 39, the second gate layer further includes a protrusion 23 connected to the first initial signal line Vinit1. The protrusion 23 includes a side edge 231, and the first initial signal line Vinit1 includes a side edge 232 connected to the side edge 231. An angle between the side edge 231 and the side edge 232 on the substrate may be less than 180 degrees. The orthogonal projection of the protrusion 23 on the substrate and the orthogonal projection of the second light-shielding portion 012 on the substrate at least partially overlap. The protrusion 23 reduces the resistance of the first initial signal line Vinit1. Furthermore, the orthogonal projection of the protrusion 23 on the substrate and the orthogonal projection of the second light-shielding portion 012 on the substrate at least partially overlap, thereby minimizing the light-shielding effect of the protrusion 23 on the array substrate. In another exemplary embodiment, by providing a protrusion of a similar structure on a gate extending in another row direction, the protrusion can reduce the resistance of the gate line without affecting the light transmittance of the array substrate.

[0200] In this exemplary embodiment, the light-shielding layer may have a conductor structure. For example, the light-shielding layer may be a metal light-shielding layer. The light-shielding layer may be connected to any of the stabilized voltage sources, such as the first power signal terminal VDD, the second power signal terminal VSS, the first initial signal terminal Vinit1, and the second initial signal terminal Vinti2, shown in FIG. 27 . Here, the light-shielding layer may be connected to the stabilized power source in the non-display area or the display area of ​​the array substrate. The stabilized voltage source may also be supplied from another power source. As shown in FIG. 29 , the orthogonal projection of the conductive portion 42 onto the substrate and the orthogonal projection of the third light-shielding portion 013 onto the substrate at least partially overlap. Since the third light-shielding portion 013 is connected to the stabilized power source, the third light-shielding portion 013 has a voltage adjusting function for the conductive portion 42. At the same time, since the conductive portion 42 is connected to the gate (conductive portion 11) of the driving transistor T3, i.e., the third light-shielding portion 013 has a voltage stabilizing effect on the gate of the driving transistor T3, this configuration reduces voltage fluctuations at the gate of the driving transistor T3 during the light-emitting stage.

[0201] 29, the orthogonal projection of the first light-shielding portion 011 onto the substrate substrate covers the orthogonal projection of the active portion 53 onto the substrate substrate, and the first light-shielding portion 011 has a light-shielding effect on the active portion 53, thereby reducing fluctuations in the output characteristics of the drive transistor T3 due to illumination of the active portion 53. Furthermore, the orthogonal projection of the first light-shielding portion 011 onto the substrate substrate can also cover the orthogonal projection of the gate (conductive portion 11) of the drive transistor T3 onto the substrate substrate, so the first light-shielding portion 011 has a voltage stabilizing effect on the gate of the drive transistor T3, thereby suppressing voltage fluctuations at the gate of the drive transistor T3 during the light-emitting stage. As shown in FIG. 29, the orthogonal projection of the first light-shielding portion 011 onto the substrate substrate and the orthogonal projection of the conductive portion 42 onto the substrate substrate at least partially overlap, and the first light-shielding portion 011 can further stabilize the voltage at the gate of the drive transistor T3. The area of ​​the gate (conductive portion 11) and conductive portion 42 of the driving transistor covered by the light-shielding layer may be 50% or more of the total area of ​​the conductive portion 11 and conductive portion 42, for example, 60% to 70%, 80% to 90%, or any numerical range therebetween, or all of these.

[0202] The array substrate may further include a second source / drain layer and an anode layer, the second source / drain layer being located on the side of the first source / drain layer away from the substrate, and the anode layer being located on the side of the second source / drain layer away from the substrate. The second source / drain layer includes a data signal line for providing the data signal terminal and a power line for providing the first power signal terminal, as shown in FIG. 27. Both the data signal line and the power line are orthogonally projected onto the substrate and extend in the second direction Y. The anode layer may form the anode of the light-emitting unit.

[0203] In this exemplary embodiment, the array further includes a second source-drain layer, as shown in FIGS. 42 and 43. FIG. 42 is a structural diagram of an embodiment of an array substrate of the present disclosure. FIG. 43 is a structural diagram of the second source-drain layer of FIG. 42. The second source-drain layer includes a data line Da and a power line VDD, and the orthogonal projections of the data line Da and the power line VDD onto the substrate extend in the second direction Y. The data line Da is used to provide the data signal terminal of FIG. 27, and the power line VDD is used to provide the first power signal terminal of FIG. 27. As shown in FIG. 42, the power line VDD is connected to the connection portion 22 through a via 713 and connected to the first power signal terminal and the capacitor C. The data line is connected to a first active layer on one side of the active portion 54 through a via 714 and connected to the first pole and the data signal terminal of the fourth transistor T4. Here, the power supply line VDD includes extension portions 91 and 92 distributed in its extension direction, and the size of the extension portion 91 in the first direction X when orthogonally projected onto the substrate may be larger than the size of the extension portion 92 in the first direction X when orthogonally projected onto the substrate. The orthogonal projection of the extension portion 91 onto the substrate can cover the channel regions of the first transistor and the second transistor. This configuration shields and shields the transistors from light via the power supply line VDD, while reducing the resistance of the power supply line VDD.

[0204] As shown in Figures 44 and 45, Figure 44 is a configuration diagram of one embodiment of the array substrate of the present disclosure. Figure 45 is a configuration diagram of the second source-drain layer of Figure 44. Here, the second source-drain layer shown in Figure 45 differs from the second source-drain layer shown in Figure 43 in that the extension portion 91 not only covers the channel regions of the first transistor and the second transistor, but also covers the channel regions of the sixth transistor T6 and the driving transistor T3.

[0205] 46 and 47 are schematic diagrams illustrating the structure of the second initial signal line in other embodiments of the array substrate of the present disclosure. In other exemplary embodiments, the second initial signal line Vinit2 may be a parallel grid line or a folded line, and may be designed based on consideration of the voltage drop of the initialization signal line.

[0206] Figure 48 is a cross-sectional view of a portion taken along dotted line B in Figure 42. The array substrate further includes a first insulating layer 82, a second insulating layer 83, a third insulating layer 84, a fourth insulating layer 85, a sixth insulating layer 86, a dielectric layer 87, a passivation layer 88, and a first flat layer 89. Here, the substrate 81, the light-shielding layer, the first insulating layer 82, the first active layer, the second insulating layer 83, the first gate layer, the third insulating layer 84, the second gate layer, the fourth insulating layer 85, the second active layer, the fifth insulating layer 86, the third gate layer, the dielectric layer 87, the first source / drain layer, the passivation layer 88, the first flat layer 89, and the second source / drain layer are stacked in this order. Here, the first insulating layer 82 may include at least one of a silicon oxide layer and a silicon nitride layer, and the thickness of the first insulating layer 82 may be 2500-3500 angstroms. The second insulating layer 83 may be a silicon oxide layer, and the thickness of the second insulating layer 83 may be 1000-2000 angstroms. The third insulating layer 84 may be an interlayer insulating layer or an interlayer dielectric layer, and the third insulating layer 84 may be a silicon nitride layer, and the thickness of the third insulating layer 84 may be 1000-2000 angstroms. The fourth insulating layer 85 includes a silicon oxide layer and a silicon nitride layer, and the thickness of the silicon oxide layer may be 3000-4000 angstroms, and the thickness of the silicon nitride layer may be 500-1000 angstroms. The fifth insulating layer 86 may be a silicon oxide layer, and the thickness of the fifth insulating layer 86 may be 1000-1700 angstroms. The dielectric layer 87 may include a silicon oxide layer and a silicon nitride layer, and the silicon oxide layer may have a thickness of 1500-2500 Angstroms, and the silicon nitride layer may have a thickness of 2500-3500 Angstroms. A second planar layer may be provided on the side of the second source / drain layer away from the substrate, and the anode layer may be located on the side of the second planar layer away from the substrate, and a light-emitting unit layer may be provided on the side of the anode layer away from the substrate, and the light-emitting unit layer may include an electron injection layer, an organic light-emitting layer, a hole injection layer, etc.

[0207] The display panel and display device provided by the embodiments of the present disclosure have the same or similar beneficial effects as the array substrate provided by the previous embodiments of the present disclosure, but since the array substrate has been described in detail in the previous embodiments, a description thereof will be omitted here.

[0208] The foregoing description of the preferred embodiment has been given for purposes of illustration and description, and is not intended to be exhaustive or limiting of the present invention. Individual elements or features of a particular embodiment are generally not limited to a particular embodiment, but where appropriate, these elements and features, even if not specifically shown or described, may be interchangeable and utilized in selected embodiments. The same may be varied in many ways. Such variations are not to be considered outside the scope of the present invention, and all are intended to be included within the scope of the present invention.

Claims

1. A display panel, the display panel including a pixel driving circuit, the pixel driving circuit including a driving transistor, the display panel further including a substrate, a light-shielding layer, a first gate layer, and a second source-drain layer; the light-shielding layer is located on one side of the substrate, and the light-shielding layer has a grid structure; the first gate layer is located on a side of the light-shielding layer away from the substrate, the first gate layer includes a first conductive portion, and the first conductive portion is used to form a gate of the driving transistor; the second source-drain layer is located on a side of the first gate layer that is away from the substrate, and the second source-drain layer includes a power supply line; an orthogonal projection of the power supply line onto the substrate and an orthogonal projection of the first conductive portion onto the substrate at least partially overlap, and an orthogonal projection of the light-shielding layer onto the substrate and an orthogonal projection of the first conductive portion onto the substrate at least partially overlap, the pixel driving circuit further includes a first transistor and a second transistor, a first pole of the first transistor is connected to a gate of the driving transistor, a second pole of the first transistor is connected to a first initial signal line, a first pole of the second transistor is connected to the gate of the driving transistor, and a second pole of the second transistor is connected to a second pole of the driving transistor; the display panel further includes a second active layer; the second active layer is located between the first gate layer and the second source / drain layer, the second active layer includes a first active portion and a second active portion, the first active portion is used to form a channel region of the first transistor, and the second active portion is used to form a channel region of the second transistor; An orthogonal projection of the light-shielding layer onto the substrate and an orthogonal projection of the first active portion onto the substrate do not overlap, and an orthogonal projection of the light-shielding layer onto the substrate and an orthogonal projection of the second active portion onto the substrate do not overlap. A display panel characterized by:

2. the pixel driving circuit further includes a second transistor, a first pole of the second transistor connected to the gate of the driving transistor and a second pole of the second transistor connected to the second pole of the driving transistor; the display panel further includes a first source-drain layer; the first source-drain layer is located between the first gate layer and the second source-drain layer, the first source-drain layer includes a second conductive portion, the second conductive portion is connected to a first electrode of the second transistor, and the second conductive portion is connected to the first conductive portion through a via; The orthogonal projection of the light-shielding layer onto the substrate and the orthogonal projection of the second conductive portion onto the substrate at least partially overlap with each other.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

3. The first source-drain layer further includes a fourth conductive portion, the fourth conductive portion being connected to the second pole of the second transistor through a first via, and the fourth conductive portion being further connected to the second pole of the drive transistor through a second via.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

4. the display panel further includes a light-emitting unit, and the pixel driving circuit further includes a seventh transistor, a first pole of the seventh transistor being connected to a first electrode of the light-emitting unit and a second pole of the seventh transistor being connected to a second initial signal line; the display panel further includes a first source-drain layer; the first source-drain layer is located between the first gate layer and the second source-drain layer, the first source-drain layer includes the second initial signal line and a seventh conductive portion, the seventh conductive portion is connected to the second initial signal line; an orthogonal projection of the second initial signal line onto the substrate extends along a first direction, an orthogonal projection of the seventh conductive portion onto the substrate extends while bending along a second direction, and the first direction and the second direction intersect; the seventh conductive portion includes a first child conductive portion and a second child conductive portion distributed along its extension direction, the first child conductive portion is connected between the second initial signal line and the second child conductive portion, the light-shielding layer includes a third light-shielding portion, and an orthogonal projection of the third light-shielding portion onto the substrate extends along the second direction; The orthogonal projection of the first daughter conductive portion onto the substrate and the orthogonal projection of the third light-shielding portion onto the substrate overlap, and the orthogonal projection of the second daughter conductive portion onto the substrate is located on one side in the first direction of the orthogonal projection of the third light-shielding portion onto the substrate.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

5. An orthogonal projection of the second conductive portion onto the substrate and an orthogonal projection of a via connecting the second conductive portion and the first conductive portion onto the substrate overlap in a first projection area, and an orthogonal projection of the power supply line onto the substrate covers the first projection area.

3. The display panel according to claim 2.

6. the light-shielding layer includes a plurality of first light-shielding portions, a second light-shielding portion, a third light-shielding portion, and a first connection portion, and the first light-shielding portions adjacent to each other in a second direction are connected by the second light-shielding portion, the third light-shielding portion, and the first connection portion; an orthogonal projection of the second light-shielding portion onto the substrate and an orthogonal projection of the third light-shielding portion onto the substrate extend along a second direction, an orthogonal projection of the first connection portion onto the substrate extend along a first direction, the first connection portion is connected between the second light-shielding portion and the third light-shielding portion, and the first direction and the second direction intersect; the pixel driving circuit further includes a first transistor, a first pole of the first transistor is connected to a gate of the driving transistor, a second pole of the first transistor is connected to a first initial signal line, and a gate of the first transistor is connected to a first reset signal line; the display panel further includes a second gate layer; the second gate layer is located between the first gate layer and the second source / drain layer, the second gate layer includes the first reset signal line, and an orthogonal projection of the first reset signal line onto the substrate extends along the first direction; An orthogonal projection of the first connection portion onto the substrate and an orthogonal projection of the first reset signal line onto the substrate at least partially overlap with each other.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

7. the gate of the first transistor is further connected to a gate line; a dimension of the first connection portion in the first direction when orthogonally projected onto the substrate is larger than a dimension of the first reset signal line in the second direction when orthogonally projected onto the substrate; and / or a dimension of the first connection portion in the first direction of orthogonal projection onto the substrate is larger than a dimension of the gate line in the second direction of orthogonal projection onto the substrate.

7. The display panel according to claim 6, wherein the first and second electrodes are arranged parallel to each other.

8. The light-shielding layer is connected to a stable voltage source.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

9. The area of ​​the first conductive portion and the second conductive portion covered by the light-shielding layer is greater than 50% of the total area of ​​the first conductive portion and the second conductive portion.

3. The display panel according to claim 2.

10. The power supply line includes a first extension and a second extension, and a dimension of the first extension in a first direction of orthogonal projection onto the substrate is larger than a dimension of the second extension in the first direction of orthogonal projection onto the substrate.

4. The display panel according to claim 3.

11. The first extension covers the first via.

11. The display panel according to claim 10.

12. the pixel driving circuit further includes a first transistor and a second transistor, a first pole of the first transistor is connected to a gate of the driving transistor, a second pole of the first transistor is connected to the first initial signal line, a first pole of the second transistor is connected to the gate of the driving transistor, and a second pole of the second transistor is connected to the second pole of the driving transistor; The orthogonal projection of the first extension onto the substrate covers the orthogonal projection of the channel region of the first transistor and the channel region of the second transistor onto the substrate.

11. The display panel according to claim 10.

13. the pixel driving circuit further includes a capacitor, a first electrode of the capacitor is connected to the gate of the driving transistor, a second electrode of the capacitor is connected to the power supply line, and the first conductive portion is multiplexed as the first electrode of the capacitor; the display panel further includes a second gate layer, the second gate layer being located between the first gate layer and the second source-drain layer, the second gate layer including a plurality of third conductive portions and a second connection portion; an orthogonal projection of the third conductive portion onto the substrate and an orthogonal projection of the first conductive portion onto the substrate at least partially overlap each other, and the third conductive portion is used to form a second electrode of the capacitor; the second connection portion is connected between the third conductive portions adjacent in a first direction, An orthogonal projection of the power supply line onto the substrate and an orthogonal projection of the second connection portion onto the substrate at least partially overlap with each other.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

14. The third conductive portion includes a first side edge, the first side edge is connected to the second connection portion, and an orthogonal projection of the power supply line onto the substrate covers at least a part of a structure of an orthogonal projection of the first side edge onto the substrate.

14. The display panel according to claim 13.

15. The first conductive portion includes a second side, an orthogonal projection of the second side onto the substrate extends along a second direction, and an orthogonal projection of the power line onto the substrate covers at least a portion of the structure of the orthogonal projection of the second side onto the substrate.

14. The display panel according to claim 13.

16. the pixel driving circuit further includes a fifth transistor, a first pole of the fifth transistor being connected to the power supply line, a second pole of the fifth transistor being connected to the first pole of the driving transistor, and a gate of the fifth transistor being connected to an enable signal line; the first gate layer further includes the enable signal line; an orthogonal projection of the enable signal line onto the substrate extends along a first direction; the display panel further includes a first source-drain layer; the first source-drain layer is located between the second gate layer and the second source-drain layer, the first source-drain layer includes a sixth conductive portion, the sixth conductive portion is connected to the second connection portion and the power supply line through vias, and an orthogonal projection of the sixth conductive portion onto the substrate and an orthogonal projection of the enable signal line onto the substrate at least partially overlap with each other.

14. The display panel according to claim 13.

17. The display panel further includes a light-emitting unit, and the pixel driving circuit further includes a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor: a first pole of the first transistor connected to the gate of the drive transistor, and a second pole of the first transistor connected to a first initial signal line; a first pole of the second transistor connected to the gate of the drive transistor, and a second pole of the second transistor connected to the second pole of the drive transistor; a first pole of the fourth transistor is connected to a data line, and a second pole of the fourth transistor is connected to a first pole of the drive transistor; a first pole of the fifth transistor is connected to the power supply line, and a second pole of the fifth transistor is connected to a first pole of the drive transistor; a first electrode of the sixth transistor is connected to a second electrode of the driving transistor, and a second electrode of the sixth transistor is connected to a first electrode of the light-emitting unit; A first pole of the seventh transistor is connected to a first electrode of the light-emitting unit, and a second pole of the seventh transistor is connected to a second initial signal line; The first transistor and the second transistor are N-type transistors, and the drive transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are P-type transistors.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

18. A display device comprising a display panel according to any one of claims 1 to 17. A display device characterized by:

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