Display device

Abstract

To improve transmittance of a display device.SOLUTION: Embodiments of the present disclosure relate to a display device, and more particularly, to a display device including a substrate, a first metal pattern disposed in a non-transmissive area and including a transparent material, a first data line disposed on the substrate and disposed over the non-transmissive area and at least one transmissive area among a plurality of transmissive areas, and a first active layer disposed on the first metal pattern and overlapping the first metal pattern, thereby improving transmittance of an optical area.SELECTED DRAWING: Figure 1a

Description

[Technical Field]

[0001] TECHNICAL FIELD An embodiment of the present disclosure relates to a display device. [Background technology]

[0002] 2. Description of the Related Art As the information society develops, the demand for display devices for displaying images is increasing in various ways. In recent years, various display devices such as liquid crystal display devices and organic light emitting display devices have been utilized.

[0003] The display area is an area where an image is displayed. The display area may include a general display area and an optical area. The display device may include an optical device disposed in the optical area. The higher the transmittance of the optical area, the more improved the sensing capability of the optical device. Summary of the Invention [Problem to be solved by the invention]

[0004] Embodiments of the present disclosure can improve the transmittance of the optical area through a display panel that includes transparent metal.

[0005] Embodiments of the present disclosure can improve the transmittance of non-transmissive areas through a display panel that includes transparent metal.

[0006] The embodiments of the present disclosure can improve the transmittance of the transmissive area through a display panel including a transparent metal.

[0007] Embodiments of the present disclosure can provide a display device capable of lowering power consumption as the transmittance of the optical region is improved. [Means for solving the problem]

[0008] An embodiment of the present disclosure can provide a display device including: a substrate including a display area where an image is displayed, the display area including an optical area including a general area and a plurality of transmissive areas, the optical area further including a non-transmissive area that is the outer periphery of the plurality of transmissive areas; a first metal pattern disposed on the substrate and in the non-transmissive area and including a transparent material; a first data line disposed on the substrate and spanning the non-transmissive area and at least one transmissive area of ​​the plurality of transmissive areas; and a first active layer disposed on the first metal pattern and overlapping the first metal pattern.

[0009] An embodiment of the present disclosure can provide a display device including: a substrate including a display area where an image is displayed, the display area including an optical area including a general area and a plurality of transmissive areas, the optical area further including a non-transmissive area that is an outline of the plurality of transmissive areas; a first sub-pixel located on the substrate, disposed in the non-transmissive area, and including a first transistor; a second sub-pixel located on the substrate, disposed in the non-transmissive area, and including a second transistor; a first data line connected to the first sub-pixel and disposed across the non-transmissive area and at least one transmissive area of ​​the plurality of transmissive areas; a second data line connected to the second sub-pixel and disposed across the non-transmissive area and at least one transmissive area of ​​the plurality of transmissive areas; and a first metal pattern located in the non-transmissive area, located below the first transistor and the second transistor, overlapping with at least a portion of the first transistor and at least a portion of the second transistor, and having a line shape. [Effects of the Invention]

[0010] According to the embodiments of the present disclosure, the transmittance of the optical region can be improved through a display panel including a transparent metal.

[0011] According to the embodiments of the present disclosure, the transmittance of the non-transmissive area can be improved through a display panel including a transparent metal.

[0012] According to the embodiment of the present disclosure, the transmittance of the transmissive region can be improved through a display panel including a transparent metal.

[0013] According to the embodiments of the present disclosure, a display device capable of reducing power consumption can be provided as the transmittance of the optical region is improved. [Brief explanation of the drawings]

[0014] [Figure 1a] 1 illustrates a display device according to an embodiment of the present disclosure. [Figure 1b] 1 illustrates a display device according to an embodiment of the present disclosure. [Figure 1c] 1 illustrates a display device according to an embodiment of the present disclosure. [Figure 2] FIG. 1 is a configuration diagram of a display device system according to an embodiment of the present disclosure. [Figure 3] 1 illustrates a display panel according to an embodiment of the present disclosure. [Figure 4] 1 illustrates signal lines disposed on a display panel according to an embodiment of the present disclosure. [Figure 5] 1 shows a general area, a first optical area, and a second optical area in a display panel according to an embodiment of the present disclosure. [Figure 6] 6 is a cross-sectional view of the general area AB shown in FIG. 5. [Figure 7] FIG. 2 is a diagram of a pixel alignment layer and a lower metal layer according to an embodiment of the present disclosure. [Figure 8] 1 is a plan view of several areas of the optical region where metal patterns are disposed according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a cross-sectional view of the CD region shown in FIG. 8. [Figure 10] FIG. 9 is a cross-sectional view of the EF region shown in FIG. [Figure 11] FIG. 9 is a cross-sectional view of the GH region shown in FIG. 8. [Figure 12] 1 is a plan view of several areas of the optical region where metal patterns are disposed according to an embodiment of the present disclosure. [Figure 13] FIG. 13 is a cross-sectional view of the IJ region shown in FIG. [Figure 14] FIG. 13 is a cross-sectional view of the KL region shown in FIG. [Figure 15] FIG. 2 is a plan view of an optical area in which a metal pattern is disposed according to an embodiment of the present disclosure. [Figure 16] FIG. 2 is a plan view of an optical area in which a metal pattern is disposed according to an embodiment of the present disclosure. [Figure 17] FIG. 2 is a plan view of an optical area in which a metal pattern is disposed according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0015] Some embodiments of the present disclosure will be described in detail below with reference to exemplary drawings. When adding reference numerals to components in each drawing, identical components may be assigned the same numerals as much as possible, even if they appear in different drawings. Note that, in describing the present disclosure, if a specific description of related publicly known configurations or functions is deemed to obscure the gist of the present disclosure, such detailed description will be omitted. When terms such as "comprise," "have," and "consist" are used in this specification, other parts may be added unless "only" is used. When a component is expressed as singular, it may also include plurals unless otherwise explicitly stated.

[0016] Furthermore, when describing components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. are used. These terms are used only to distinguish the components from other components, and do not limit the nature, order, sequence, number, etc. of the components.

[0017] When two or more components are described as being "coupled," "coupled," or "connected" in a description of the positional relationship of components, it should be understood that the two or more components may be directly "coupled," "coupled," or "connected," but that the two or more components may also be "coupled," "coupled," or "connected" to other components through further "intervening" connections. Here, the other components may be included in one or more of the two or more components that are "coupled," "coupled," or "connected" to each other.

[0018] In describing the temporal relationship between components, methods of operation, methods of production, etc., when a temporal or sequential relationship is described using, for example, "after," "following," "next," or "before," this may also include cases where the relationship is not consecutive, unless "immediately" or "directly" is used.

[0019] On the other hand, when a numerical value or its corresponding information (e.g., level, etc.) relating to a component is mentioned, the numerical value or its corresponding information may be interpreted as including a range of error that may occur due to various factors (e.g., process factors, internal or external impact, noise, etc.) even if there is no other explicit statement.

[0020] Various embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0021] 1a, 1b and 1c show a display device 100 according to an embodiment of the present disclosure.

[0022] 1a, 1b, and 1c, a display device 100 according to an embodiment of the present disclosure may include a display panel 110 for displaying images, and one or more optical-electronic devices 11, 12.

[0023] The display panel 110 may include a display area DA where an image is displayed and a non-display area NDA where an image is not displayed. A plurality of sub-pixels and various signal lines for driving the plurality of sub-pixels may be arranged in the display area DA. The non-display area NDA may be an area outside the display area DA. Various signal lines may be arranged in the non-display area NDA, and various driving circuits may be connected to the non-display area NDA. The non-display area NDA may be bent so as to be invisible from the front surface, or may be covered by a case (not shown). The non-display area NDA is also called a bezel or bezel area.

[0024] The display device 100 according to the embodiment of the present disclosure may include one or more electronic devices 11, 12 located below (on the opposite side of the viewing surface) the display panel 110. Here, the one or more electronic devices 11, 12 may be provided separately from the display panel 110.

[0025] The one or more optical-electronic devices 11, 12 may be devices that can receive light transmitted through the display panel 110 and perform a predetermined operation using the received light.

[0026] For example, the one or more optical / electronic devices 11, 12 may include one or more of an imaging device such as a camera (image sensor), a proximity sensor, a detection sensor such as an illuminance sensor, etc. Here, for example, the detection sensor may be an infrared sensor.

[0027] Light necessary for the operation of one or more electronic devices 11, 12 can enter the front surface (viewing surface) of display panel 110 and be transmitted through display panel 110 to one or more electronic devices 11, 12 located below (opposite the viewing surface) display panel 110. For example, light necessary for the operation of one or more electronic devices 11, 12 and transmitted through display panel 110 can include one or more of visible light, infrared light, ultraviolet light, etc.

[0028] 1a, 1b, and 1c, in a display panel 110 according to an embodiment of the present disclosure, a display area DA may include a general area NA and one or more optical areas OA1, OA2, which may overlap one or more electronic devices 11, 12.

[0029] 1a, the display area DA can include a general area NA and a first optical area OA1, where at least a part of the first optical area OA1 can overlap with the first electronic device 11.

[0030] 1b, the display area DA may include a general area NA, a first optical area OA1, and a second optical area OA2. In the example of FIG. 1b, the general area NA may be present between the first optical area OA1 and the second optical area OA2. Here, at least a portion of the first optical area OA1 may overlap with the first electronic device 11, and at least a portion of the second optical area OA2 may overlap with the second electronic device 12.

[0031] 1c, the display area DA may include a general area NA, a first optical area OA1, and a second optical area OA2. In the example of FIG. 1c, the general area NA does not exist between the first optical area OA1 and the second optical area OA2. That is, the first optical area OA1 and the second optical area OA2 are adjacent to each other. Here, at least a portion of the first optical area OA1 may overlap the first electronic device 11, and at least a portion of the second optical area OA2 may overlap the second electronic device 12.

[0032] One or more optical regions OA1, OA2 must have both an image display structure and a light-transmitting structure. That is, since one or more optical regions OA1, OA2 are part of the display area DA, one or more optical regions OA1, OA2 must have sub-pixel light-emitting regions for image display arranged therein. Furthermore, one or more optical regions OA1, OA2 must have a light-transmitting structure for transmitting light to one or more electronic devices 11, 12.

[0033] One or more electronic devices 11, 12 are positioned behind (below, opposite the viewing surface) the display panel 110 and receive light transmitted through the display panel 110.

[0034] The one or more electronic devices 11, 12 are not exposed on the front (viewing surface) of the display panel 110. Therefore, when a user looks at the front of the display device 110, the electronic devices 11, 12 are not visible to the user.

[0035] For example, the first electronic device 11 may be a camera that receives light in the visible wavelength band (visible light), and the second electronic device 12 may be a sensor such as a proximity sensor or an illuminance sensor. For example, the sensor may be an infrared sensor that detects light in the infrared wavelength band (infrared light). Conversely, the first electronic device 11 may be a sensor, and the second electronic device 12 may be a camera.

[0036] For convenience of explanation, the following description will be given taking the example that the first electronic device 11 is a camera and the second electronic device 12 is an infrared-based sensing sensor, where the camera can be a camera lens or an image sensor.

[0037] When first electronic device 11 is a camera, this camera is located behind (below) display panel 110, but may be a front camera that captures an image in front of display panel 110. Therefore, while looking at the viewing surface of display panel 110, the user can take a photo (self-photograph) via a camera that is not visible on the viewing surface.

[0038] The general area NA and one or more optical areas OA1 and OA2 included in the display area DA may be areas where an image can be displayed. However, the general area NA is an area where a light-transmitting structure does not need to be formed, and one or more optical areas OA1 and OA2 may be areas where a light-transmitting structure should be formed.

[0039] Therefore, one or more optical regions OA1, OA2 should have a transmittance above a certain level, and the general region NA may have no light transmittance or a low transmittance below a certain level.

[0040] For example, one or more optical areas OA1, OA2 and the general area NA may differ from each other in terms of resolution, subpixel arrangement structure, number of subpixels per unit area, electrode structure, line structure, electrode arrangement structure, or line arrangement structure, etc.

[0041] For example, the number of subpixels per unit area in one or more optical areas OA1 and OA2 may be smaller than the number of subpixels per unit area in the general area NA. That is, the resolution of one or more optical areas OA1 and OA2 may be lower than the resolution of the general area NA. Here, the number of subpixels per unit area may be synonymous with resolution, pixel density, or pixel integration. For example, the unit of the number of subpixels per unit area may be PPI (Pixels Per Inch), which means the number of pixels within 1 inch.

[0042] For example, the number of subpixels per unit area in the first optical area OA1 may be less than the number of subpixels per unit area in the general area NA, and the number of subpixels per unit area in the second optical area OA2 may be equal to or greater than the number of subpixels per unit area in the first optical area OA1 but less than the number of subpixels per unit area in the general area NA.

[0043] Meanwhile, as one method for increasing the transmittance of at least one of the first optical area OA1 and the second optical area OA2, the pixel density differential design method can be applied, as described above. According to the pixel density differential design method, the display panel 110 can be designed so that the number of subpixels per unit area in at least one of the first optical area OA1 and the second optical area OA2 is smaller than the number of subpixels per unit area in the general area NA.

[0044] However, in some cases, a pixel size differential design method can be applied as another method for increasing the transmittance of at least one of the first optical region OA1 and the second optical region OA2. According to the pixel size differential design method, the display panel 110 can be designed so that the number of subpixels per unit area in at least one of the first optical region OA1 and the second optical region OA2 is the same as or similar to the number of subpixels per unit area in the general region NA, but the size of each subpixel SP (i.e., the light-emitting region size) arranged in at least one of the first optical region OA1 and the second optical region OA2 is smaller than the size of each subpixel SP (i.e., the light-emitting region size) arranged in the general region NA.

[0045] For ease of explanation, the following description will be made on the assumption that the pixel density differential design method is applied among two methods (pixel density differential design method and pixel size differential design method) for increasing the transmittance of at least one of the first optical area OA1 and the second optical area OA2. Therefore, hereinafter, a small number of subpixels per unit area may be expressed as a small subpixel size, and a large number of subpixels per unit area may be expressed as a large subpixel size.

[0046] The first optical area OA1 can have various shapes such as a circle, an ellipse, a square, a hexagon, or an octagon. The second optical area OA2 can have various shapes such as a circle, an ellipse, a square, a hexagon, or an octagon. The first optical area OA1 and the second optical area OA2 can have the same shape or different shapes.

[0047] 1c, when the first optical area OA1 and the second optical area OA2 are adjacent to each other, the entire optical area including the first optical area OA1 and the second optical area OA2 may have various shapes, such as a circle, an ellipse, a rectangle, a hexagon, an octagon, etc. For convenience of explanation, the following description will be given assuming that each of the first optical area OA1 and the second optical area OA2 is a circle.

[0048] In the display device 100 according to the embodiment of the present disclosure, if the first electronic device 11 that is not exposed to the outside and is hidden below the display panel 100 is a camera, the display device 100 according to the embodiment of the present disclosure can be said to be a display to which UDC (Under Display Camera) technology is applied.

[0049] Accordingly, in the case of the display device 100 according to the embodiment of the present disclosure, a reduction in the area of ​​the display area DA does not occur because a notch or a camera hole for exposing a camera does not need to be formed in the display panel 110. As a result, because a notch or a camera hole for exposing a camera does not need to be formed in the display panel 110, the size of the bezel area can be reduced, design restrictions are eliminated, and design freedom can be increased.

[0050] In the display device 100 according to an embodiment of the present disclosure, even though one or more electronic devices 11, 12 are hidden and positioned behind the display panel 110, the one or more electronic devices 11, 12 can receive light normally and perform their predetermined functions normally.

[0051] Furthermore, in the display device 100 according to an embodiment of the present disclosure, although one or more electronic devices 11, 12 are hidden behind the display panel 110 and overlap with the display area DA, normal image display is possible in one or more optical areas OA1, OA2 that overlap with the one or more electronic devices 11, 12 in the display area DA.

[0052] The above-described first optical area OA1 is designed to be a transmissive area, and therefore the image display characteristics in the first optical area OA1 may be different from the image display characteristics in the general area NA.

[0053] Furthermore, when the first optical area OA1 is designed to improve the image display characteristics, the transmittance of the first optical area OA1 may be reduced.

[0054] Therefore, an embodiment of the present disclosure presents a structure of the first optical area OA1 that can improve the transmittance in the first optical area OA1 without causing any variation in image quality between the first optical area OA1 and the general area NA.

[0055] In addition, the embodiment of the present disclosure presents a structure of the second optical area OA2 that can improve the image quality in the second optical area OA2 and improve the transmittance in the second optical area OA2, not only for the first optical area OA1 but also for the second optical area OA2.

[0056] Furthermore, in the display device 100 according to the embodiment of the present disclosure, the first optical area OA1 and the second optical area OA2 are similar in that they are light-transmittable areas, but may be used in different ways.

[0057] Therefore, in the display device 100 according to an embodiment of the present disclosure, the structure of the first optical area OA1 and the structure of the second optical area OA2 are basically similar or identical, but may differ from each other in terms of resolution, subpixel arrangement structure, number of subpixels per unit area, electrode structure, line structure, electrode arrangement structure, or line arrangement structure, etc.

[0058] FIG. 2 is a system configuration diagram of a display device 100 according to an embodiment of the present disclosure.

[0059] 2, the display device 100 is a component for displaying an image and may include a display panel 110 and a display driving circuit. The display driving circuit is a circuit for driving the display panel 110 and may include a data driving circuit 220, a gate driving circuit 230, a display controller 240, etc.

[0060] The display panel 110 may include a display area DA where an image is displayed and a non-display area NDA where an image is not displayed. The non-display area NDA may be an outer periphery of the display area DA and may also be referred to as a bezel area. All or part of the non-display area NDA may be an area visible from the front surface of the display device 100, or may be a curved area that is not visible from the front surface of the display device 100.

[0061] The display panel 110 may include a substrate 210 and a plurality of sub-pixels SP disposed on the substrate 210. In addition, the display panel 110 may further include various types of signal lines to drive the plurality of sub-pixels SP.

[0062] The display device 100 according to the embodiment of the present disclosure may be a liquid crystal display device or a self-emissive display device in which the display panel 110 emits light. When the display device 100 according to the embodiment of the present disclosure is a self-emissive display device, each of the plurality of subpixels SP may include a light-emitting element. For example, the display device 100 according to the embodiment of the present disclosure may be an organic light-emitting display device in which the light-emitting elements are organic light-emitting diodes (OLEDs). As another example, the display device 100 according to the embodiment of the present disclosure may be an inorganic light-emitting display device in which the light-emitting elements are inorganic-based light-emitting diodes. As yet another example, the display device 100 according to the embodiment of the present disclosure may be a quantum dot display device in which the light-emitting elements are quantum dots, which are semiconductor crystals that emit light themselves.

[0063] The structure of each of the subpixels SP may vary depending on the type of display device 100. For example, if the display device 100 is a self-emitting display device that emits light from the subpixels SP, each subpixel SP may include a light-emitting element that emits light from itself, one or more transistors, and one or more capacitors.

[0064] For example, some types of signal lines may include a plurality of data lines (DL) that transmit data signals (also called data voltages or video signals) and a plurality of gate lines GL that transmit gate signals (also called scan signals).

[0065] The plurality of data lines DL and the plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be arranged extending in a first direction. Each of the plurality of gate lines GL may be arranged extending in a second direction. Here, the first direction may be a column direction, and the second direction may be a row direction. Alternatively, the first direction may be a row direction, and the second direction may be a column direction. For convenience of explanation, the following description will be given assuming that each of the plurality of data lines DL is arranged in a column direction, and each of the plurality of gate lines GL is arranged in a row direction.

[0066] The data driving circuit 220 is a circuit for driving a plurality of data lines DL and can output data signals to the plurality of data lines DL. The gate driving circuit 230 is a circuit for driving a plurality of gate lines GL and can output gate signals to the plurality of gate lines GL.

[0067] The display controller 240 is a device for controlling the data driving circuit 220 and the gate driving circuit 230, and can control the driving timing for the plurality of data lines DL and the driving timing for the plurality of gate lines GL.

[0068] The display controller 240 can provide data drive control signals DCS to the data drive circuit 220 to control the data drive circuit 220, and can provide gate drive control signals GCS to the gate drive circuit 230 to control the gate drive circuit 230.

[0069] The display controller 240 can receive input image data from the host system 250 and provide image data to the data driving circuit 220 based on the input image data.

[0070] The data driving circuit 220 can receive digital image data (Data) from the display controller 240, convert the received image data (Data) into analog data signals, and output the analog data signals to a plurality of data lines DL.

[0071] The gate driving circuit 230 is supplied with a first gate voltage corresponding to a turn-on level voltage and a second gate voltage corresponding to a turn-off level voltage, along with various gate driving control signals GCS, and can generate gate signals and supply the generated gate signals to multiple gate lines GL.

[0072] Meanwhile, at least one of the data driving circuit 220 and the gate driving circuit 230 may be disposed in the display area DA of the display panel 110. For example, at least one of the data driving circuit 220 and the gate driving circuit 230 may be disposed so as not to overlap the sub-pixels SP, or may be disposed so as to partially or completely overlap the sub-pixels SP.

[0073] The data driving circuit 220 may be connected to one side (e.g., the upper or lower side) of the display panel 110. Depending on the driving method, panel design method, etc., the data driving circuit 220 may be connected to both sides (e.g., the upper and lower sides) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110.

[0074] The gate driving circuit 230 may be connected to one side (e.g., the left or right side) of the display panel 110. Depending on the driving method, panel design method, etc., the gate driving circuit 230 may be connected to both sides (e.g., the left and right sides) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110.

[0075] The display controller 240 may be implemented as a separate component from the data driver circuitry 220, or may be integrated with the data driver circuitry 220 and implemented as an integrated circuit.

[0076] The display controller 240 may be a timing controller used in conventional display technology, or may be a control device that can also perform other control functions including a timing controller, or may be a control device different from the timing controller, or may be a circuit within the control device.

[0077] The display controller 240 may be mounted on a printed circuit board, a flexible printed circuit, or the like, and may be electrically connected to the data driving circuit 220 and the gate driving circuit 230 via the printed circuit board, the flexible printed circuit, or the like.

[0078] The display device 100 according to an embodiment of the present disclosure may include a touch sensor and a touch sensing circuit that senses the touch sensor to detect whether a touch has occurred by a touch object such as a finger or a pen and detect the touch position, in order to provide not only an image display function but also a touch sensing function.

[0079] The touch sensing circuit may include a touch driving circuit 260 that drives and senses the touch sensor and generates and outputs touch sensing data, and a touch controller 270 that can sense the occurrence of a touch and detect the touch position using the touch sensing data.

[0080] The touch sensor may include a plurality of touch electrodes, and may further include a plurality of touch lines for electrically connecting the plurality of touch electrodes to the touch driving circuit 260.

[0081] The touch sensor may be present outside the display panel 110 in the form of a touch panel, or may be present inside the display panel 110. When the touch sensor is present outside the display panel 110 in the form of a touch panel, the touch sensor is called an external type. When the touch sensor is an external type, the touch panel and the display panel 110 can be fabricated separately and combined during an assembly process. The external type touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0082] If the touch sensor is present inside the display panel 110, the touch sensor may be formed on the substrate 210 along with signal lines and electrodes related to display driving during the manufacturing process of the display panel 110.

[0083] The touch driving circuit 260 may supply a touch driving signal to at least one of the plurality of touch electrodes, sense the at least one of the plurality of touch electrodes, and generate touch sensing data.

[0084] The touch sensing circuit can perform touch sensing using a self-capacitance sensing method or a mutual-capacitance sensing method.

[0085] The touch driving circuit 260 and the touch controller 270 included in the touch sensing circuit may be realized by separate devices or may be realized by a single device, and the touch driving circuit 260 and the data driving circuit 220 may be realized by separate devices or may be realized by a single device.

[0086] The display device 100 may further include a power supply circuit that supplies various power sources to the display driving circuit and / or the touch sensing circuit.

[0087] As described above, the display area DA of the display panel 110 may include a general area NA and one or more optical areas OA1 and OA2. The general area NA and one or more optical areas OA1 and OA2 are areas where an image can be displayed. However, the general area NA is an area where a light-transmitting structure does not need to be formed, while the one or more optical areas OA1 and OA2 are areas where a light-transmitting structure should be formed.

[0088] As mentioned above, in the display panel 110, the display area DA can include one or more optical areas OA1, OA2 along with a general area NA, but for ease of explanation, we will assume that the display area DA includes both the first optical area OA1 and the second optical area OA2 (Figures 1b and 1c).

[0089] FIG. 3 illustrates a display panel 110 according to an embodiment of the present disclosure.

[0090] 3, a plurality of sub-pixels SP may be arranged in the display area DA of the display panel 110. The sub-pixels SP may be arranged in a general area NA, a first optical area OA1, and a second optical area OA2 included in the display area DA.

[0091] Referring to FIG. 3, each of the plurality of sub-pixels SP may include a light-emitting element ED and a sub-pixel circuit SPC configured to drive the light-emitting element ED.

[0092] Referring to FIG. 3, the sub-pixel circuit SPC may include a drive transistor DT for driving the light-emitting element ED, a scan transistor ST for transmitting a data voltage Vdata to the drive transistor DT, and a storage capacitor Cst for maintaining a constant voltage during one frame.

[0093] The drive transistor DT may include a first node N1, a second node N2, and a third node N3.

[0094] The first node N1 may be electrically connected to the light emitting element ED, the second node N2 may be connected to the scan transistor ST, and the third node N3 may be connected to the driving voltage line VDDL.

[0095] The first node N1 may be electrically connected to the pixel electrode PE of the light emitting element ED, the second node N2 may be applied with a data voltage VDATA, and the third node N3 may be applied with a driving voltage VDD.

[0096] The first node N1 may be a source node or a drain node, the second node N2 may be a gate node, and the third node N3 may be a drain node or a source node. For convenience of explanation, the following will take as an example a case where, in the driving transistor DT, the first node N1 is a source node, the second node N2 is a gate node, and the third node N3 is a drain node.

[0097] The light emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE.

[0098] The pixel electrode PE may be an electrode disposed in each sub-pixel SP. For example, the pixel electrode PE may be electrically connected directly or indirectly (through another transistor) to the first node N1 of the drive transistor DT of each sub-pixel SP.

[0099] The common electrode CE may be an electrode commonly disposed for multiple subpixels SP. For example, the common electrode CE may be electrically connected to a base voltage line VSSL. A base voltage VSS, which is a type of common driving voltage, may be applied to the common electrode CE via the base voltage line VSSL.

[0100] For example, the pixel electrode PE may be an anode electrode and the common electrode CE may be a cathode electrode. Conversely, the pixel electrode PE may be a cathode electrode and the common electrode CE may be an anode electrode. For convenience of explanation, it is assumed below that the pixel electrode PE is an anode electrode and the common electrode CE is a cathode electrode.

[0101] The interlayer EL can include an emitting layer EML and a common interlayer EL_COM.

[0102] For example, the emitting layer EML may be disposed in each of the plurality of subpixels SP, or, for another example, may be disposed in common to the plurality of subpixels SP. The common intermediate layer EL_COM may be disposed in common across the plurality of subpixels SP.

[0103] The luminescent layer EML can be disposed for each luminescent region EA, and the common intermediate layer EL_COM can be disposed in common across the luminescent regions EA and the non-luminescent region.

[0104] The common intermediate layer EL_COM may include a first common intermediate layer COM1 and a second common intermediate layer COM2. The first common intermediate layer COM1 is disposed between the pixel electrode PE and the emitting layer EML and may include at least one layer (e.g., an organic layer). The second common intermediate layer COM2 is disposed between the emitting layer EML and the common electrode CE and may include at least one layer (e.g., an organic layer).

[0105] For example, the first common intermediate layer COM1 may include a hole injection layer (HIL) and a hole transport layer (HTL), etc. The second common intermediate layer COM2 may include an electron transport layer (ETL) and an electron injection layer (EIL), etc.

[0106] The hole injection layer injects holes from the pixel electrode PE into the hole transport layer, and the hole transport layer transports the holes to the emitting layer EML; the electron injection layer injects electrons into the electron transport layer at the common electrode CE, and the electron transport layer can transport the electrons to the emitting layer EML.

[0107] Each light-emitting element ED can be configured by an overlapping portion of a pixel electrode PE, an emitting layer EML in the intermediate layer EL, and a common electrode CE. Each light-emitting element ED can form a predetermined emitting area EA. For example, the emitting area EA can be defined as an area where the pixel electrode PE, the emitting layer EML in the intermediate layer EL, and the common electrode CE overlap.

[0108] For example, the light-emitting element ED may be an organic light-emitting diode (OLED) based on an organic material, an inorganic light-emitting diode based on an inorganic material, or a quantum dot light-emitting element, etc. When the light-emitting element ED is an organic light-emitting diode, the light-emitting layer EL in the light-emitting element ED may include an organic layer containing an organic material.

[0109] The scan transistor SCT is controlled to be turned on and off by a scan signal SC, which is a type of gate signal applied via a scan signal line GL, which is a type of gate line GL, and can be electrically connected between the second node N2 of the drive transistor DT and the data line DL.

[0110] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DT.

[0111] The subpixel circuit SPC may have a 2T (Transistor) 1C (Capacitor) structure including two transistors DT and ST and one capacitor Cst, as shown in FIG. 3, and may further include one or more transistors or one or more capacitors in some cases.

[0112] The storage capacitor Cst may be an external capacitor intentionally designed outside the drive transistor DT, rather than a parasitic capacitor that may exist between the first node N1 and the second node N2 of the drive transistor DT. Each of the drive transistor DT and the scan transistor ST may be an n-type transistor or a p-type transistor.

[0113] Since the circuit elements (particularly, the light-emitting elements ED realized by the organic light-emitting diodes OLED containing organic materials) in each subpixel SP are vulnerable to external moisture and oxygen, a sealing layer 310 for preventing external moisture and oxygen from penetrating into the circuit elements (particularly, the light-emitting elements ED) can be disposed on the display panel 110. The sealing layer 310 can be disposed in a manner that covers the light-emitting elements ED.

[0114] Referring to FIG. 3, the display device 100 according to an embodiment of the present disclosure may include a touch sensor layer 320 including a plurality of sensor electrodes for sensing a user's touch, a touch drive circuit 260 configured to sense the plurality of sensor electrodes, and a touch controller 270 configured to determine the presence or absence of a touch or touch coordinates using the sensing result (touch sensing data) of the touch drive circuit 260.

[0115] The touch sensor layer 320 may be embedded within the display panel 110. For example, the touch sensor layer 320 may be disposed on the encapsulation layer 310 within the display panel 110.

[0116] The display panel 110 may further include a plurality of touch pads TP to which the touch drive circuit 260 is electrically connected, and a plurality of touch routing wirings for electrically connecting a plurality of sensor electrodes included in the touch sensor layer 320 to the plurality of touch pads TP to which the touch drive circuit 260 is connected.

[0117] FIG. 4 shows signal lines SL arranged on a display panel 110 according to an embodiment of the present disclosure.

[0118] Referring to FIG. 4, a display panel 110 according to an embodiment of the present disclosure may include a plurality of sub-pixels SP and a plurality of signal lines 410, 450 for driving the sub-pixels SP.

[0119] 4, each of the plurality of sub-pixels SP includes a light-emitting element ED and a sub-pixel circuit SPC for driving the light-emitting element ED. The light-emitting element ED may form a light-emitting area EA.

[0120] Referring to FIG. 4, a plurality of signal lines 410, 450 can supply various drive signals to a plurality of sub-pixels SP, which are required to drive the sub-pixels SP.

[0121] For example, the various driving signals may include a data signal Vdata for driving the data line DL, a scan signal SC for driving the gate line GL, etc. The various driving signals may further include a driving voltage for driving the driving voltage line and a base voltage for driving the common base voltage line.

[0122] Therefore, the plurality of signal lines may include a plurality of data lines DL for supplying data signals Vdata and a plurality of gate lines GL for supplying gate signals such as scan signals SC, etc. The plurality of signal lines may further include a drive voltage line and a base voltage line.

[0123] Referring to FIG. 4, the display area DA can include a general area NA, a first optical area OA1, and a second optical area OA2.

[0124] 4, the general area NA, the first optical area OA1, and the second optical area OA2 may each include a plurality of light-emitting areas EA, and a plurality of light-emitting elements ED and a plurality of sub-pixel circuits SPC may be arranged in each of the general area NA, the first optical area OA1, and the second optical area OA2.

[0125] Referring to FIG. 4, the plurality of signal lines 410, 450 may include a plurality of general signal lines 450 and a plurality of specific signal lines 410.

[0126] The plurality of general signal lines 450 may be signal lines that are arranged only in the general area NA without passing through the first optical area OA1 and the second optical area OA2.

[0127] The plurality of specific signal lines 410 may be signal lines that pass through at least one of the first optical area OA1 and the second optical area OA2.

[0128] For example, the plurality of general signal lines 450 may include a plurality of data lines 470 and a plurality of gate lines 460 that do not pass through the first optical area OA1 and the second optical area OA2.

[0129] For example, the plurality of specific signal lines 410 may include a plurality of data lines 430, 440 and a plurality of gate lines 420 passing through at least one of the first optical area OA1 and the second optical area OA2.

[0130] FIG. 5 shows a general area NA, a first optical area OA1, and a second optical area OA2 in a display panel 110 according to an embodiment of the present disclosure.

[0131] 5, a display panel 110 according to an embodiment of the present disclosure may include a display area DA where an image is displayed and a non-display area NDA where an image is not displayed. The display area DA may include a first optical area OA1, a second optical area OA2, and a general area NA.

[0132] The first optical area OA1, the second optical area OA2, and the general area NA are included in the display area DA, and therefore can have a display structure. For example, the first optical area OA1, the second optical area OA2, and the general area NA can each include multiple light-emitting areas.

[0133] Furthermore, the first optical region OA1 and the second optical region OA2 are regions that can transmit light, and the general region NA may be a region that cannot transmit light or has very little light transmission. The general region NA may refer to a region that cannot transmit light and excludes the first optical region OA1 and the second optical region OA2. Here, light transmission may mean that light passes between the front and rear surfaces of the display panel 110.

[0134] The first optical area OA1 may be an area overlapping with the first electronic device 11. The second optical area OA2 may be an area overlapping with the second electronic device 12.

[0135] The first optical area OA1 and the second optical area OA2 may each have a light-transmitting structure. However, the first optical area OA1 and the second optical area OA2 may have different structural characteristics. For example, the transmittance of the first optical area OA1 may be higher than the transmittance of the second optical area OA2. The resolution or the number of subpixels per unit area of ​​the first optical area OA1 may be lower than the resolution or the number of subpixels per unit area of ​​the second optical area OA2.

[0136] The first electronic device 11 can perform a predetermined operation using light in a first wavelength band among the light transmitted through the first optical area OA1, and the second electronic device 12 can perform a predetermined operation using light in a second wavelength band different from the first wavelength band among the light transmitted through the second optical area OA2.

[0137] The first wavelength band may include one or more of a visible wavelength band, an infrared wavelength band, an ultraviolet wavelength band, etc. The second wavelength band may include one or more of a visible wavelength band, an infrared wavelength band, an ultraviolet wavelength band, etc., but may be different from the first wavelength band.

[0138] For example, the first electronic device 11 may be a camera, and the second electronic device 12 may be a sensor. The first electronic device 11 may perform a camera operation using light in a visible wavelength band corresponding to a first wavelength band among light transmitted through the first optical region OA1. The second electronic device 12 may perform a sensing operation using light in an infrared wavelength band corresponding to a second wavelength band among light transmitted through the second optical region OA2.

[0139] 5, each of the first optical area OA1 and the second optical area OA2 may be circular or octagonal, etc. Without being limited thereto, each of the first optical area OA1 and the second optical area OA2 may have various shapes, such as an ellipse, a polygon, or an irregular shape.

[0140] The first optical area OA1 and the second optical area OA2 may have the same shape as each other. Alternatively, the first optical area OA1 and the second optical area OA2 may have different shapes from each other.

[0141] 5, the display area DA can include multiple light-emitting areas EA. Since the general area NA, the first optical area OA1, and the second optical area OA2 are areas included in the display area DA, the general area NA, the first optical area OA1, and the second optical area OA2 can each include multiple light-emitting areas EA.

[0142] The plurality of light-emitting regions EA may include light-emitting regions that emit light of three or more colors, for example, a first color-light-emitting region that emits light of a first color, a second color-light-emitting region that emits light of a second color, and a third color-light-emitting region that emits light of a third color.

[0143] For example, if the first color light is red light, the second color light is green light, and the third color light is blue light, the first color light-emitting region may be called the red light-emitting region EA_R, the second color light-emitting region may be called the green light-emitting region EA_G, and the third color light-emitting region may be called the blue light-emitting region EA_B.

[0144] The red light-emitting region EA_R, the green light-emitting region EA_G, and the blue light-emitting region EA_B may have the same size (light-emitting area size), or at least one of the red light-emitting region EA_R, the green light-emitting region EA_G, and the blue light-emitting region EA_B may have a size (light-emitting area size) different from the remaining portions.

[0145] As described above, the first color, the second color, and the third color may be various colors as different colors, for example, the first color, the second color, and the third color may include red, green, and blue. For convenience of explanation, the following description will be given assuming that the first color is red, the second color is green, and the third color is blue. However, the present invention is not limited to this example.

[0146] When the first color is red, the second color is green, and the third color is blue, the size (light-emitting area size) of the blue light-emitting region EA_B may be the largest among the sizes (light-emitting area sizes) of the red light-emitting region EA_R, the green light-emitting region EA_G, and the blue light-emitting region EA_B.

[0147] The light-emitting element ED disposed in the red light-emitting region EA_R may include an emitting layer EML that emits red light. The light-emitting element ED disposed in the green light-emitting region EA_G may include an emitting layer EML that emits green light. The light-emitting element ED disposed in the blue light-emitting region EA_B may include an emitting layer EML that emits blue light.

[0148] Among the light-emitting layer EML that emits red light, the light-emitting layer EML that emits green light, and the light-emitting layer EML that emits blue light, the organic material contained in the light-emitting layer EML that emits blue light may be the most susceptible to deterioration. As a result, by designing the size of the blue light-emitting region EA_B to be the largest, the current density supplied to the light-emitting element ED arranged in the blue light-emitting region EA_B may be the smallest. Therefore, the degree of deterioration of the light-emitting element ED arranged in the blue light-emitting region EA_B may be similar to the degree of deterioration of the light-emitting element ED arranged in the red light-emitting region EA_R and the degree of deterioration of the light-emitting element ED arranged in the green light-emitting region EA_G.

[0149] Therefore, the variation in deterioration between the light-emitting element ED arranged in the red light-emitting region EA_R, the light-emitting element ED arranged in the green light-emitting region EA_G, and the light-emitting element ED arranged in the blue light-emitting region EA_B is eliminated or reduced, thereby improving image quality.

[0150] 5, each of the plurality of first transmission regions TA1 included in the first optical region OA1 can have various shapes such as a circle, an ellipse, a polygon, or an irregular shape, and each of the plurality of second transmission regions TA2 included in the second optical region OA2 can have various shapes such as a circle, an ellipse, a polygon, or an irregular shape.

[0151] The transmissive regions TA1 and TA2 may have a relatively higher transmittance than the non-transmissive region NTA. To achieve this, the common electrode CE corresponding to the transmissive regions TA1 and TA2 may be removed by etching. Furthermore, the transmissive regions TA1 and TA2 may not be provided with metal for the transistors shown in FIG. 3. Therefore, the transmissive regions TA1 and TA2 may be regions from which the common electrode CE has been removed by etching, and may be the same as the transmissive regions TA1 and TA2 and non-transmissive region NTA shown in FIG. 5, for example. Furthermore, the transmissive regions TA1 and TA2 may be regions in which no metal for the transistors has been provided, and may be the same as the transmissive region TA and non-transmissive region NTA shown in FIG. 7, for example.

[0152] The first transmission regions TA1 may have the same shape. Alternatively, some of the first transmission regions TA1 may have a different shape from the rest of the first transmission regions TA1. The second transmission regions TA2 may have the same shape. Alternatively, some of the second transmission regions TA2 may have a different shape from the rest of the second transmission regions TA2.

[0153] The first and second transmission regions TA1 and TA2 may have the same shape, or may have different shapes.

[0154] 5, the general area NA may correspond entirely to a non-transmitting area. That is, the general area NA may include a non-transmitting area NTA that includes multiple luminous areas EA. In other words, the entire general area NA may be a non-transmitting area NTA, and the general area NA may not include a transmissive area TA.

[0155] The first optical region OA1 may further include a non-transmitting region NTA including a plurality of light-emitting regions EA, and a plurality of first transmissive regions TA1. The non-transmitting region NTA included in the first optical region OA1 may be a region that does not transmit light at all, or may be a region that transmits light with a transmittance lower than that of the first transmissive region TA1.

[0156] The second optical area OA2 may further include a non-transmitting area NTA including a plurality of light-emitting areas EA, and a plurality of second transmissive areas TA2. The non-transmitting areas NTA included in the second optical area OA2 may be areas through which no light is transmitted, or may be areas through which light is transmitted with a transmittance lower than that of the second transmissive areas TA2.

[0157] Meanwhile, the common electrode CE may include a plurality of common electrode holes CH1, CH2 corresponding to the plurality of openings. The plurality of common electrode holes CH1, CH2 may be formed in the first optical area OA1 and the second optical area OA2. That is, the positions where the plurality of common electrode holes CH1, CH2 are formed may be the first optical area OA1 and the second optical area OA2.

[0158] 5, the positions where the common electrode holes CH1 and CH2 are formed in the common electrode CE can correspond to the first transmission regions TA1 included in the first optical region OA1, respectively. The positions where the common electrode holes CH1 and CH2 are formed in the common electrode CE can correspond to the second transmission regions TA2 included in the second optical region OA2, respectively. This can improve the transmittance of each of the first optical region OA1 and the second optical region OA2.

[0159] 5, the area AB is shown in the general area NA. A cross-sectional view of the area AB will be described below.

[0160] FIG. 6 is a cross-sectional view of the area AB of the general area NA shown in FIG.

[0161] Referring to FIG. 6, a display panel 110 according to an embodiment of the present disclosure may include a transistor portion, a light emitting element portion, and an encapsulation portion, but the embodiment of the present disclosure is not limited thereto.

[0162] The substrate 210 may be a single layer or a multilayer. When the substrate 210 is a multilayer, the substrate 210 may include a first substrate 601, an intermediate layer 602, and a second substrate 603. The intermediate layer 602 may be located between the first substrate 601 and the second substrate 603. For example, each of the first substrate 601 and the second substrate 603 may be a polyimide (PI) layer, although the embodiment of the present disclosure is not limited thereto. The intermediate layer 602 may be an inorganic insulating layer, although the embodiment of the present disclosure is not limited thereto. When an electric charge is charged in the first substrate 601, which is a polyimide layer, the intermediate layer 602 can block the charge from affecting a transistor disposed on the second substrate 603 through the second substrate 603, which is also a polyimide layer.

[0163] Furthermore, the intermediate layer 602 can block moisture components from penetrating through the first substrate 601 to the upper portion. For example, the intermediate layer 602 can be made of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof, or can be formed from a double layer of silicon dioxide (SiO2) and silicon nitride (SiNx), but is not limited thereto.

[0164] The transistor section may include a substrate 210, insulating layers 610, 611, 612, 613, 614, 615, and 616 on the substrate 210, thin film transistors TFT1 and TFT2, a storage capacitor Cst, and various electrodes or signal wirings.

[0165] The thin film transistors TFT1 and TFT2 included in the transistor section can include a first thin film transistor TFT1 and a second thin film transistor TFT2.

[0166] The first thin film transistor TFT1 may include a first active layer ACT1, a first electrode E1a, a second electrode E1b, and a third electrode E1c. The first active layer ACT1 may be a first semiconductor layer, although embodiments of the present disclosure are not limited thereto. For example, the first active layer ACT1 may be composed of an oxide semiconductor, amorphous silicon, polysilicon, low-temperature polysilicon (LTPS), or the like, although embodiments of the present disclosure are not limited thereto. The first thin film transistor TFT1 may be implemented as a p-channel transistor or an n-channel transistor, although embodiments of the present disclosure are not limited thereto.

[0167] The first electrode E1a may be a gate electrode, the second electrode E1b may be a source electrode or a drain electrode, and the third electrode E1c may be a drain electrode or a source electrode. Hereinafter, for convenience of explanation, the first electrode E1a may be a first gate electrode E1a, the second electrode E1b may be a first source electrode E1b, and the third electrode E1c may be a first drain electrode E1c. However, embodiments of the present disclosure are not limited thereto.

[0168] The second thin film transistor TFT2 may include a second active layer ACT2, a fourth electrode E2a, a fifth electrode E2b, and a sixth electrode E2c. The second active layer ACT2 may be a second semiconductor layer, although embodiments of the present disclosure are not limited thereto. For example, the second active layer ACT2 may be composed of an oxide semiconductor, amorphous silicon, polysilicon, low-temperature polysilicon (LTPS), or the like, although embodiments of the present disclosure are not limited thereto. The second thin film transistor TFT2 may be implemented as a p-channel transistor or an n-channel transistor, although embodiments of the present disclosure are not limited thereto.

[0169] For example, one of the first thin film transistor TFT1 and the second thin film transistor TFT2 may be configured with an oxide semiconductor as an active layer. As another example, one of the first thin film transistor TFT1 and the second thin film transistor TFT2 may be configured with low-temperature polysilicon as an active layer. As yet another example, the first thin film transistor TFT1 and the second thin film transistor TFT2 may be configured with an oxide semiconductor as an active layer. As yet another example, the first thin film transistor TFT1 and the second thin film transistor TFT2 may be configured with low-temperature polysilicon as an active layer. As yet another example, the drive transistor DT of the first thin film transistor TFT1 and the second thin film transistor TFT2 may be configured with an oxide semiconductor as an active layer, and the scan transistor ST may be configured with low-temperature polysilicon as an active layer. As yet another example, the drive transistor DT of the first thin film transistor TFT1 and the second thin film transistor TFT2 may be configured with low-temperature polysilicon as an active layer, and the scan transistor ST may be configured with an oxide semiconductor as an active layer. In yet another example, the transistors included in the gate-in-panel (GIP) type gate drive circuit 140 may be configured with an oxide semiconductor or low-temperature polysilicon as their active layers. In yet another example, all the transistors configured on the substrate 210 and the transistors included in the gate-in-panel (GIP) type gate drive circuit 130 may be configured with an oxide semiconductor as their active layers.

[0170] The fourth electrode E2a may be a gate electrode, the fifth electrode E2b may be a source electrode or a drain electrode, and the sixth electrode E2c may be a drain electrode or a source electrode. Hereinafter, for convenience of explanation, the fourth electrode E2a may be a second gate electrode E2a, the fifth electrode E2b may be a second source electrode E2b, and the sixth electrode E2c may be a second drain electrode E2c. However, embodiments of the present disclosure are not limited thereto.

[0171] The second active layer ACT2 of the second thin film transistor TFT2 may be located higher from the substrate 210 than the first active layer ACT1 of the first thin film transistor TFT1.

[0172] A first buffer layer 611 may be disposed below the first active layer ACT1 of the first thin film transistor TFT1, and a second buffer layer 614 may be disposed below the second active layer ACT2 of the second thin film transistor TFT2. For example, the first active layer ACT1 of the first thin film transistor TFT1 may be located on the first buffer layer 611, and the second active layer ACT2 of the second thin film transistor TFT2 may be located on the second buffer layer 614. The second buffer layer 614 may be disposed higher than the first buffer layer 611.

[0173] The storage capacitor Cst may be disposed in various metal layers in the display panel 110. For example, the storage capacitor Cst may include a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2.

[0174] The light element portion may include a plurality of light emitting elements ED disposed on at least one planarization layer 621, 622, 623. Each of the plurality of light emitting elements ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE.

[0175] The capping layer 640 may be disposed on the common electrode CE. The capping layer 640 may further enhance the luminous efficiency of the display panel 110 by utilizing the microcavity effect.

[0176] The encapsulation portion may include an encapsulation layer 310 on the plurality of light-emitting elements ED. The encapsulation layer 310 may be a single layer or multiple layers, but the embodiment of the present disclosure is not limited thereto.

[0177] The structure or vertical structure of the display panel 110 according to an embodiment of the present disclosure will be described in further detail below with reference to FIG.

[0178] 6, a second buffer layer 611 can be disposed on the substrate 210. The first buffer layer 611 can be a single layer or a multi-layer, although embodiments of the present disclosure are not limited thereto. When the first buffer layer 611 is a multi-layer, the first buffer layer 611 can include an upper buffer layer 611a and a lower buffer layer 611b.

[0179] A first active layer ACT1 of the first thin film transistor TFT1 may be disposed on the first buffer layer 611. The first active layer ACT1 may include a channel region in which a channel is formed, a source connection region on one side of the channel region, and a drain connection region on the other side of the channel region.

[0180] A first insulating layer 612 may be disposed on the first active layer ACT1 of the first thin film transistor TFT1. A first gate electrode E1a of the first thin film transistor TFT1 may be disposed on the first insulating layer 612. A second insulating layer 613 may be disposed on the first gate electrode E1a of the first thin film transistor TFT1. The first insulating layer 612 may be a gate insulating layer, although embodiments of the present disclosure are not limited thereto. The second insulating layer 613 may be an interlayer insulating layer, although embodiments of the present disclosure are not limited thereto.

[0181] A second buffer layer 614 may be disposed on the second insulating layer 613 .

[0182] A second active layer ACT2 of the second thin film transistor TFT2 may be disposed on the second buffer layer 614. The second active layer ACT2 may include a channel region in which a channel is formed, a source connection region on one side of the channel region, and a drain connection region on the other side of the channel region.

[0183] The third insulating layer 615 may be disposed on the second active layer ACT2 of the second thin film transistor TFT2. The second gate electrode E2a of the second thin film transistor TFT2 may be disposed thereon. The fourth insulating layer 616 may be disposed on the second gate electrode E2a of the second thin film transistor TFT2. The third insulating layer 615 may be a gate insulating layer, although embodiments of the present disclosure are not limited thereto. The fourth insulating layer 616 may be an interlayer insulating layer, although embodiments of the present disclosure are not limited thereto.

[0184] The first source electrode E1b and the first drain electrode E1c of the first thin film transistor TFT1 and the second source electrode E2b and the second drain electrode E2c of the second thin film transistor TFT2 may be disposed on the fourth insulating layer 616.

[0185] The first source electrode E1b and the first drain electrode E1c of the first thin film transistor TFT1 can be connected to the source connection region and the drain connection region of the first active layer ACT1, respectively, through holes in the fourth insulating layer 616, the third insulating layer 615, the second buffer layer 614, the second insulating layer 613, and the first insulating layer 612.

[0186] The second source electrode E2b and the second drain electrode E2c of the second thin film transistor TFT2 may be connected to the source connection region and the drain connection region of the second active layer ACT2, respectively, through holes in the fourth insulating layer 616 and the third insulating layer 615.

[0187] The first source electrode E1b and the first drain electrode E1c of the first thin film transistor TFT1 and the second source electrode E2b and the second drain electrode E2c of the second thin film transistor TFT2 may include a first metal and be disposed in a first metal layer, where the first metal and the first metal layer may be referred to as a first source-drain metal and a first source-drain metal layer.

[0188] 6, for example, the storage capacitor Cst may be formed by a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2. In some cases, the storage capacitor Cst may be formed by three or more capacitor electrodes, or may have a configuration in which two or more capacitors are connected in parallel.

[0189] The first capacitor electrode CAPE1 and the second capacitor electrode CAPE2 may be disposed on various metal layers disposed within the display panel 110, respectively.

[0190] For example, the first capacitor electrode CAPE1 may include the same first gate metal as the first gate electrode E1a of the first thin film transistor TFT1 on the first insulating layer 612 and may be disposed within the first gate metal layer, although embodiments of the present disclosure are not limited thereto.

[0191] For example, the second capacitor electrode CAPE2 can be disposed on the second insulating layer 613.

[0192] The second source electrode E2b of the second thin film transistor TFT2 may be electrically connected to the second capacitor electrode CAPE2 through holes in the fourth insulating layer 616, the third insulating layer 615, and the second buffer layer 614.

[0193] For example, the first thin film transistor TFT1 may be the scan transistor ST in FIG. 2, and the second thin film transistor TFT2 may be the drive transistor DT in FIG.

[0194] 6, the transistor portion may further include a first shield metal 651 disposed on the substrate 210. The first shield metal 651 may overlap the first active layer ACT1 of the first thin film transistor TFT1. The first shield metal 651 may be disposed below the first active layer ACT1 of the first thin film transistor TFT1. For example, the first shield metal 651 may be disposed between the substrate 210 and the first buffer layer 611, or between the upper buffer layer 611a and the lower buffer layer 611b.

[0195] The transistor portion may further include a second shield metal 652 disposed on the substrate 210. The second shield metal 652 may overlap the second active layer ACT2 of the second thin film transistor TFT2. The second shield metal 652 may be disposed below the second active layer ACT2 of the second thin film transistor TFT2.

[0196] For example, the second shield metal 652 can be disposed in a metal layer between the second insulating layer 613 and the second buffer layer 614. The second shield metal 652 may be disposed in the same metal layer as the second capacitor CAPE2, although embodiments of the present disclosure are not limited thereto.

[0197] As another example, the second shield metal 652 may be disposed in the same first gate metal layer as the first gate electrode E1a of the first thin film transistor TFT1.

[0198] At least one planarization layer can be disposed on the first thin film transistor TFT1 and the second thin film transistor TFT2. The example of Figure 6 shows a case where three planarization layers 621, 622, and 623 are disposed on the first thin film transistor TFT1 and the second thin film transistor TFT2. In some cases, two planarization layers may be disposed on the first thin film transistor TFT1 and the second thin film transistor TFT2, but the embodiment of the present disclosure is not limited thereto.

[0199] 6, a first planarization layer 621 may be disposed on the first source electrode E1b and the first drain electrode E1c of the first thin film transistor TFT1 and the second source electrode E2b and the second drain electrode E2c of the second thin film transistor TFT2. For example, the first planarization layer 621 may be disposed on the first thin film transistor TFT1 and the second thin film transistor TFT2. For example, the first planarization layer 621 may be disposed so as to cover both the first thin film transistor TFT1 and the second thin film transistor TFT2.

[0200] 6, the relay electrode RE may be disposed on the first planarization layer 621. The relay electrode RE may electrically connect the second source electrode E2b of the second thin film transistor TFT2 and the pixel electrode PE.

[0201] The relay electrode RE can be electrically connected to the second source electrode E2b of the second thin film transistor TFT2 through a hole in the first planarization layer 621. The second source electrode E2b of the second thin film transistor TFT2 can be electrically connected to the second capacitor electrode CAPE2 of the storage capacitor Cst.

[0202] The relay electrode RE may be disposed in a second metal layer on the first planarization layer 621 and may include a second metal. The second metal and the second metal layer may be referred to as a second source-drain metal and a second source-drain metal layer.

[0203] The second planarization layer 622 may be disposed on the first planarization layer 621. The second planarization layer 622 may be disposed on the relay electrode RE.

[0204] 6, the light emitting element portion may be disposed on the second planarization layer 622. The light emitting element ED may be formed on the second planarization layer 622. The light emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The light emitting region of the light emitting element ED may be formed in a region where the pixel electrode PE, the intermediate layer EL, and the common electrode CE overlap and contact each other.

[0205] The pixel electrode PE may be disposed on the second planarization layer 622. The pixel electrode PE may be electrically connected to the relay electrode RE through a hole in the second planarization layer 622.

[0206] The bank 631 may be disposed on the second planarization layer 622. The opening of the bank 631 may expose a portion of the pixel electrode PE to form a light-emitting region. For example, the opening of the bank 631 may overlap a portion of the pixel electrode PE. The bank 631 may be made of a material containing a black pigment or an organic material such as a benzocyclobutene resin, a polyimide resin, an acrylic resin, or a photosensitive polymer, but the embodiment of the present disclosure is not limited thereto.

[0207] Spacers 632 may be disposed on the banks 631. The spacers 632 may prevent damage due to contact with a micro metal mask used in the process. The spacers 632 may be made of a material containing a black pigment or an organic material such as a benzocyclobutene resin, a polyimide resin, an acrylic resin, or a photosensitive polymer, but the embodiments of the present disclosure are not limited thereto.

[0208] An intermediate layer EL of the light-emitting element ED may be disposed on a portion of the pixel electrode PE and the spacer 632. A common electrode CE may be disposed on the intermediate layer EL.

[0209] 6, the encapsulation portion may be disposed on the light emitting element portion and may be located on the common electrode CE. The encapsulation portion may include an encapsulation layer 310 formed on the common electrode CE.

[0210] The sealing layer 310 can prevent moisture and oxygen from penetrating into the light-emitting element ED. For example, the sealing layer 310 can prevent moisture and oxygen from penetrating into the organic material contained in the intermediate layer EL of the light-emitting element ED. The sealing layer 310 may be configured as a single layer or multiple layers, but the embodiment of the present disclosure is not limited thereto.

[0211] 6 , by way of example, the sealing layer 310 may include a first inorganic sealing layer 311, a first organic sealing layer 312, and a second inorganic sealing layer 313, although embodiments of the present disclosure are not limited thereto. For example, the first inorganic sealing layer 311 and the second inorganic sealing layer 313 may include inorganic layers, and the first organic sealing layer 312 may include an organic layer, although embodiments of the present disclosure are not limited thereto.

[0212] The display panel 110 according to the embodiment of the present disclosure may include a built-in touch sensor. In this case, the display panel 110 according to the embodiment of the present disclosure may include a touch sensor layer 320 formed on the encapsulation layer 310. The touch sensor layer 320 may be a touch unit.

[0213] 6, the touch sensor layer 320 may include a plurality of touch electrodes TE, and may include a first touch metal TM1 and a second touch metal TM2 to form the plurality of touch electrodes TE. In an embodiment of the present disclosure, the layer on which the second touch metal TM2 is disposed may be referred to as a sensor metal layer, and the layer on which the first touch metal TM1 is disposed may be referred to as a bridge metal layer.

[0214] The touch sensor layer 320 may further include insulating layers, such as a touch buffer layer 321 on the encapsulation layer 310 and a touch interlayer insulating layer 322 on the touch buffer layer 321. Here, the touch buffer layer 321 may be omitted.

[0215] The first touch metal TM1 may be disposed between the touch buffer layer 321 and the touch inter-layer insulating layer 322. The second touch metal TM2 may be disposed between the touch inter-layer insulating layer 322 and the protection layer 653.

[0216] Each of the plurality of touch electrodes TE may be made of the second touch metal TM2. Each of the plurality of touch electrodes TE may be a mesh-type electrode having a plurality of openings, although the embodiment of the present disclosure is not limited thereto.

[0217] The plurality of touch electrodes TE may include a first touch electrode TE1 and a second touch electrode TE2. The second touch metal TM2 included in the first touch electrode TE1 may be electrically connected via the first touch metal TM1. For example, the second touch metals TM2 spaced apart from each other may be electrically connected by the first touch metal TM1 to form one first touch electrode TE1.

[0218] The first touch metal TM1 may be disposed on the touch buffer layer 321. The touch interlayer insulating layer 322 may be disposed on the first touch metal TM1. The second touch metal TM2 may be disposed on the touch interlayer insulating layer 322. A portion of the second touch metal TM2 may be connected to the corresponding first touch metal TM1 through a hole in the touch interlayer insulating layer 322.

[0219] 6, the first touch metal TM1 and the second touch metal TM2 may be disposed so as not to overlap the light-emitting element ED. The first touch metal TM1 and the second touch metal TM2 may overlap the bank 631.

[0220] A plurality of second touch metals TM2 can configure one touch electrode TE. The plurality of second touch metals TM2 may be arranged in a mesh shape and electrically connected. A part of the second touch metals TM2 and another part of the second touch metals TM2 are electrically connected via the first touch metal TM1 to configure one touch electrode TE.

[0221] The configuration arranged in the general area NA will be described, and the configuration arranged in the optical areas OA1 and OA2 will be described below.

[0222] FIG. 7 is a diagram of a pixel array layer 720 and a bottom metal layer 710 according to an embodiment of the present disclosure.

[0223] Referring to FIG. 7, a pixel array layer 720 and a lower metal layer 710 disposed in the second optical area OA2 can be seen.

[0224] A lower metal layer 710 can be disposed on the substrate. The lower metal layer 710 can include a metal material. The lower metal layer 710 can be an opaque metal or a transparent metal.

[0225] The lower metal layer 710 may include a plurality of metal patterns 711, 712, and 713. The plurality of metal patterns 711, 712, and 713 may be the same as the metal patterns shown in FIGS. 8 to 17. The plurality of metal patterns 711, 712, and 713 may be line-shaped. Although the plurality of metal patterns 711, 712, and 713 are line-shaped, they may include breaks. A detailed description of the plurality of metal patterns 711, 712, and 713 will be provided later.

[0226] A pixel array layer 720 may be disposed on the lower metal layer 710 .

[0227] The pixel array layer 720 is a layer in which a plurality of sub-pixels SP are arranged. Referring to Fig. 7, the pixel array layer 720 may include a plurality of light-emitting areas EA. Referring to Fig. 7, the plurality of light-emitting areas EA may include a first light-emitting area (EA of SP1) and a second light-emitting area (EA of SP2).

[0228] 7, a pixel array layer 720 may be disposed on a lower metal layer 710. The pixel array layer 720 may be disposed on the lower metal layer 710, and the lower portion of the pixel array layer 720 may be protected by the lower metal layer 710. For example, charge may be accumulated in a structure disposed below the lower metal layer 710, and the corresponding charge may be prevented from affecting the pixel array layer 720.

[0229] The plan view of the first region 500 shown in FIG. 5 will now be described with reference to FIG.

[0230] FIG. 8 is a plan view of a partial area 500 of the optical area OA2 in which metal patterns 810 and 820 are arranged according to an embodiment of the present disclosure.

[0231] Referring to FIG. 8, a structure for a transistor can be arranged in the non-transparent region NTA2, and the region in which the structure for a transistor can be arranged is indicated by a rectangle within the non-transparent region NTA2.

[0232] 8, a transmissive region TA2 can be seen. A plurality of transmissive regions TA2 can be defined by a common electrode CE. The common electrode CE can include a plurality of common electrode holes CH2. Each of the regions in which the plurality of common electrode holes CH2 are arranged can be a transmissive region TA2.

[0233] The light emitting regions EA can be arranged so as not to overlap with the transmissive regions TA2. Referring to Fig. 8, the light emitting regions EA can be arranged outside the transmissive region TA2.

[0234] 8, a plurality of data lines DL can be seen. The plurality of data lines DL may extend from the non-transmissive region NTA2 to the transmissive region TA2. The plurality of data lines DL may extend in a second direction DR2.

[0235] The second data line 432 can be positioned closer to the first data line 431 than the third data line 433. The fourth data line 434 can be positioned closer to the third data line 433 than the fifth data line 435. The sixth data line 436 can be positioned closer to the fifth data line 435 than the seventh data line 437.

[0236] The first data line 431, the second data line 432, the third data line 433, and the fourth data line 434 may extend from the fourth transmissive region TA2d to the first transmissive region TA2a. The first data line 431, the second data line 432, the third data line 433, and the fourth data line 434 may be disposed in the first transmissive region TA2a and the fourth transmissive region TA2d.

[0237] The second data line 435, the sixth data line 436, the seventh data line 437, and the eighth data line 438 may extend from the third transmissive region TA2c to the second transmissive region TA2b, and the fifth data line 435, the sixth data line 436, the seventh data line 437, and the eighth data line 438 may be disposed in the second transmissive region TA2b and the third transmissive region TA2c.

[0238] 8, each of the plurality of data lines DL may be disposed in the non-transmissive region NTA2, and the plurality of data lines DL may be disposed in at least one of the plurality of transmissive regions TA2. The plurality of data lines DL may be disposed across the non-transmissive region NTA2 and at least one of the transmissive regions TA2.

[0239] A plurality of data lines DL may extend from the non-transmissive region NTA2 to the transmissive region TA2. Each of the plurality of data lines DL may include multiple layers of metal wiring. In this case, the portion of the data line disposed in the transmissive region TA2 may include a transparent material. In this case, the transmittance of the transmissive region TA2 may be further improved. The portion of the data line disposed in the non-transmissive region NTA2 may include a transparent material or an opaque material. If the portion of the data line disposed in the non-transmissive region NTA2 includes a transparent material, the transmittance of the non-transmissive region NTA2 may be further improved.

[0240] Referring to FIG. 8, multiple data lines DL can be arranged across the metal patterns 810, 820.

[0241] Referring to FIG. 8, a first metal pattern 810 and a second metal pattern 820 may be disposed in the non-transmissive area NTA2.

[0242] The first metal pattern 810 and the second metal pattern 820 shown in FIG. 8 may be included in the lower metal layer 710 shown in FIG.

[0243] Referring to FIG. 8, the first metal pattern 810 and the second metal pattern 820 may extend in a first direction DR1.

[0244] 8, first metal pattern 810 may be arranged spaced apart from second metal pattern 820. First metal pattern 810 may be arranged spaced apart from second metal pattern 820 with fourth transmissive region TA2d interposed therebetween. First metal pattern 810 may be arranged spaced apart from second metal pattern 820 with third transmissive region TA2c interposed therebetween.

[0245] 8, second metal pattern 820 may be disposed between first transmissive region TA2a and fourth transmissive region TA2d. Also, first metal pattern 810 may be disposed between second transmissive region TA2b and third transmissive region TA2c. That is, second metal pattern 820 may extend in first direction DR1 between transmissive regions TA2.

[0246] Referring to FIG. 8, the metal patterns 810 and 820 may overlap multiple data lines DL.

[0247] Referring to FIG. 8, the second metal pattern 820 may overlap the fifth data line 435 and the sixth data line 436 in the first intersection region 831 .

[0248] Referring to FIG. 8, the second metal pattern 820 may overlap the seventh data line 437 and the eighth data line 438 in the second intersection region 832 .

[0249] 8, the first metal pattern 810 and the second metal pattern 820 may have a line shape. The first metal pattern 810 and the second metal pattern 820 may have a curved line shape.

[0250] 8, the first metal pattern 810 and the second metal pattern 820 may extend in a first direction DR1 while a predetermined pattern is repeated. The first metal pattern 810 and the second metal pattern 820 may be a line shape without breaks.

[0251] Referring to FIG. 8, the second metal pattern 820 may include a first pattern portion 820a, a second pattern portion 820b, and a third pattern portion 820c.

[0252] The first pattern portion 820a may be disposed closer to the third transmissive region TA2c than the second pattern portion 820b. The first pattern portion 820a may extend in the first direction DR1, and the first pattern portion 820a may overlap with the fifth data line 435. The first pattern portion 820a may also overlap with the sixth data line 436.

[0253] The second pattern portion 820b may be disposed closer to the second transmissive region TA2b than the first pattern portion 820a. The second pattern portion 820b may be U-shaped. The second pattern portion 820b may be a portion that connects the first pattern portion 820a and the third pattern portion 820c.

[0254] The third pattern portion 820c may be disposed closer to the third transmissive region TA2c than the second pattern portion 820b. The third pattern portion 820c may extend in the first direction DR1, and the third pattern portion 820c may overlap with the seventh data line 437. The third pattern portion 820c may also overlap with the eighth data line 438.

[0255] 8, a CD region shown in a plan view of the display panel 110 can be seen. The CD region is a region that crosses the second metal pattern 820, the blue light-emitting region EA_B, the second data line 432, and the first data line 431. Referring to FIG. 9, a cross-sectional view of the display panel 110 including the metal patterns 810 and 820 will be described.

[0256] Referring to FIG. 8, the EF region and the GH region can be seen in the plan view of the display panel 110. The EF region is a region that crosses the second metal pattern 820, the third data line 433, and the fourth data line 434. The GH region is a region that crosses the second metal pattern 820 and the third data line 433. Referring to FIGS. 10 and 11, cross-sectional views of the region where the metal pattern and the data line DL overlap will be described below.

[0257] FIG. 9 is a cross-sectional view of the CD region shown in FIG.

[0258] 9, the substrate 210, the insulating layers 610, the planarization layer 620, the sealing layer 310, and the touch sensor layer 320 are shown, which are the same as those shown in FIG. 6. Of the configurations shown in FIG. 9, descriptions of the same configurations as those shown in FIG. 6 may be omitted.

[0259] The following description will be centered on the cross-sectional view shown in FIG. 9, but FIG. 8 will also be referenced when necessary.

[0260] Referring to FIG. 9, the substrate 210 can be placed in contact with a first buffer layer 611 .

[0261] Charge can accumulate where the substrate 210 and the first buffer layer 611 come into contact.

[0262] If charges are accumulated at the contact point between the substrate 210 and the first buffer layer 611, the charges may affect the first active layer ACT1 and the second active layer ACT2.

[0263] Referring to FIG. 9, the second metal pattern 820 may be disposed between the first buffer layer 611 and the substrate 210 .

[0264] As the second metal pattern 820 is located between the first buffer layer 611 and the substrate 210, it can prevent charges from affecting the first active layer ACT1.

[0265] The second metal pattern 820 can prevent the charge from affecting the first active layer ACT1, so the charge on the upper side of the second metal pattern 820 can be smaller than the charge on the lower side of the second metal pattern 820.

[0266] A second metal pattern 820 may be disposed below the first active layer ACT1.

[0267] A portion of the second metal pattern 820 can be arranged to completely overlap the first active layer ACT1. That is, as a portion of the second metal pattern 820 completely overlaps the first active layer ACT1, the second metal pattern 820 can more effectively block charges from affecting the first active layer ACT1.

[0268] The area of ​​the first active layer ACT1 may be larger than the area of ​​the second active layer ACT2. In this case, the effect of charges on the first active layer ACT1 may be larger than the effect of charges on the second active layer ACT2. That is, when the second metal pattern 820 is disposed under the first active layer ACT1, the subpixel SP including the first active layer ACT1 can be driven more stably. In this case, the first active layer ACT1 may be made of low-temperature polysilicon, and the second active layer ACT2 may be made of an oxide semiconductor, but the first active layer ACT1 and the second active layer ACT2 are not limited thereto.

[0269] Meanwhile, the second metal pattern 820 can be disposed in the non-transmissive region NTA2. The non-transmissive region NTA2 may have a lower transmittance than the transmissive region TA2. The optical device is disposed in the optical regions OA1 and OA2, and the higher the transmittance of the optical regions OA1 and OA2, the better the sensing performance of the optical device. Therefore, the transmittance of the transmissive region TA2 needs to be increased, and the transmittance of the non-transmissive region NTA2 also needs to be increased.

[0270] The second metal pattern 820 may be an opaque metal, but if the second metal pattern 820 is a transparent metal, the transmittance of the non-transmitting area NTA2 can be further improved.

[0271] 8 and 9, the second metal pattern 820 may have a line shape including a zigzag pattern. In this case, the second metal pattern 820 may overlap the first active layer ACT1 included in each of the plurality of subpixels. That is, the second metal pattern 820 may extend in the first direction DR1 while having a line shape including a zigzag pattern. In this case, the second metal pattern 820 may be disposed to pass under the first active layer ACT1.

[0272] Referring to FIG. 8 , the second metal pattern 820 may have a line shape and extend in the first direction DR1. In this case, the second metal pattern 820 may extend in the first direction DR1 to the general area NA shown in FIG. 6 . In this case, the first shield metal 651 shown in FIG. 6 may be part of the second metal pattern 820, and the first shield metal 651 may be a transparent metal. However, unlike this, the second metal pattern 820 may be disposed only in the optical areas OA1 and OA2, spaced apart from the first shield metal 651 shown in FIG. 6 . In this case, the second metal pattern 820 shown in FIG. 9 may be a transparent metal, and the first shield metal 651 shown in FIG. 6 may be an opaque metal, although it is disposed in the same layer as the second metal pattern 820.

[0273] 9, the second metal pattern 820 may be disposed on the same layer as a part of the data line DL, and may be disposed on the same layer as a part of the first data line 431 and a part of the second data line 432.

[0274] 9, the first data line 431 may be disposed in the transmissive region TA2. In this case, the first data line 431 may include a transparent material. If the first data line 431 includes a transparent material, the transmittance of the transmissive region TA2 can be further improved.

[0275] The first data line 431 is disposed in the transmissive region TA2, and the common electrode CE may not be disposed in the transmissive region TA2, so that a portion of the first data line 431 may not overlap with the common electrode CE.

[0276] 9, the second data line 432 may be disposed in the non-transmissive area NTA2. In this case, the second data line 432 may be made of an opaque metal or a transparent metal. If the second data line 432 is made of a transparent metal, the transmittance of the non-transmissive area NTA2 can be further improved.

[0277] FIG. 10 is a cross-sectional view of the EF region shown in FIG.

[0278] 8, the EF region is a region that separates the second metal pattern 820, the third data line 433, and the fourth data line 434. A cross-sectional view of the EF region is shown in FIG.

[0279] Referring to FIG. 10, a second metal pattern 820 may be disposed on the substrate 210 .

[0280] Referring to FIG. 10, the second metal pattern 820 may be disposed in the EF region, spaced apart from the data line.

[0281] Referring to FIG. 10, the data lines can be disposed on the second planarization layer 622 .

[0282] 8, the second metal pattern 820 extends in a first direction DR1, and the data line DL extends in a second direction DR2, so that the second metal pattern 820 and the data line DL can cross each other. When the second metal pattern 820 and the data line DL cross each other, the second metal pattern 820 can overlap with the data line DL. When the second metal pattern 820 is disposed only on a specific layer, the data line DL may be disposed so as to overlap with the second metal pattern 820 via metal wiring disposed on multiple layers. When multiple data lines DL are disposed only on a specific layer, the second metal pattern 820 may be disposed so as to overlap with the data line DL via metal wiring disposed on multiple layers.

[0283] In the following, a structure in which the data line DL includes metal wiring portions arranged in multiple layers and the data line DL overlaps with the second metal pattern 820 will be described.

[0284] FIG. 11 is a cross-sectional view of the GH region shown in FIG.

[0285] 8, the GH region is the region separating the third data line 433 and the second metal pattern 820. A cross-sectional view of the GH region is shown in FIG.

[0286] 11, the third data line 433 may include a first wiring portion 433a, a second wiring portion 433b, a third wiring portion 433c, a fourth wiring portion 433d, and a fifth wiring portion 433e. The third data line 433 may include multiple wiring portions, which may be referred to as a jumping wiring structure.

[0287] The first wiring portion 433a can be disposed on the substrate 210. The first wiring portion 433a may be disposed on the same layer as the layer on which the second metal pattern 820 is disposed. The first wiring portion 433a may be a transparent metal or an opaque metal.

[0288] A portion of the second wiring portion 433b can be disposed on the first planarization layer 621. A portion of the second wiring portion 433b can be electrically connected to the first wiring portion 433a through a contact hole formed in the insulating layers 610. The second wiring portion 433b can be an opaque metal. The first wiring portion 433a can include the first source-drain metal shown in FIG. 6. The second wiring portion 433b can overlap the first wiring portion 433a and the third wiring portion 433c.

[0289] A portion of the third wiring portion 433c may be disposed on the second planarization layer 622. A portion of the third wiring portion 433c may be electrically connected to the second wiring portion 433b through a contact hole formed on the second planarization layer 622. The third wiring portion 433c may be an opaque metal. The third wiring portion 433c may include the second source-drain metal shown in FIG. 6. A portion of the third wiring portion 433c may be disposed so as to overlap the second metal pattern 820. The third wiring portion 433c may extend from a portion connected to the second wiring portion 433b to a portion connected to the fourth wiring portion 433d, and the extending third wiring portion 433c may be disposed so as to overlap the second metal pattern 820.

[0290] A portion of the fourth wiring portion 433d can be disposed on the first planarization layer 621. A portion of the fourth wiring portion 433d may be electrically connected to the third wiring portion 433c through a contact hole formed in the insulating layers 610. The fourth wiring portion 433d may be an opaque metal. The first wiring portion 433a may include the first source-drain metal shown in FIG. 6. The fourth wiring portion 433d may overlap with the third wiring portion 433c and the fifth wiring portion 433e.

[0291] The fifth wiring portion 433e can be disposed on the substrate 210. The fifth wiring portion 433e may be disposed on the same layer as the layer on which the second metal pattern 820 is disposed. The fifth wiring portion 433e may be a transparent metal or an opaque metal.

[0292] The first wiring portion 433a and the fifth wiring portion 433e may be made of a transparent metal or an opaque metal. The first wiring portion 433a and the fifth wiring portion 433e are arranged in the non-transparent area NTA2, and may be made of a transparent metal. In this case, the transmittance of the non-transparent area NTA2 can be further improved.

[0293] The above-described features of the third data line 433 can be applied to all of the data lines DL included in the plurality of data lines DL. The third data line 433 has been described as including the first wiring portion 433a to the fifth wiring portion 433e.

[0294] However, the third data line 433 does not necessarily have to include the third wiring portion 433c and the fourth wiring portion 433d. In this case, the second wiring portion 433b can be arranged in the same manner as the third wiring portion 433c, and the second wiring portion 433b may be arranged on the first planarization layer 621, electrically connected to the first wiring portion 433a and the fifth wiring portion 433e, and overlap with the second metal pattern 820.

[0295] Furthermore, when an additional planarization layer is disposed on the second planarization layer 622, the third data line 433 may further include an additional wiring portion in addition to the fifth wiring portion 433e.

[0296] FIG. 12 is a plan view of a partial area 500 of the optical area OA2 in which metal patterns 1210 and 1220 are arranged according to an embodiment of the present disclosure.

[0297] FIG. 13 is a cross-sectional view of the IJ region shown in FIG.

[0298] Unlike the metal patterns 1210, 1220 shown in FIG. 8, the metal patterns 1210, 1220 shown in FIG. 12 may include at least one break point.

[0299] 12 , the first metal pattern 1210 may include a plurality of metal islands 1211, 1212, 1213, 1214, and 1215. For example, the first metal pattern 1210 may include a first metal island 1211, a second metal island 1212, a third metal island 1213, a fourth metal island 1214, and a fifth metal island 1215. The second metal pattern 1220 may include a sixth metal island 1221, a seventh metal island 1222, an eighth metal island 1223, a ninth metal island 1224, and a tenth metal island 1225.

[0300] At least one data line DL can be disposed between the island metals, and with reference to Figure 12, two data lines DL can be disposed between the island metals.

[0301] 12, the first data line 431 and the second data line 432 may be disposed between the first metal island 1211 and the second metal island 1212. The second data line 432 and the third data line 433 may be disposed between the second metal island 1212 and the third metal island 1213.

[0302] 12, the first data line 431 and the second data line 432 may be disposed between the fifth metal island 1215 and the sixth metal island 1221. The second data line 432 and the third data line 433 may be disposed between the sixth metal island 1221 and the seventh metal island 1222. Repetitive description will be omitted.

[0303] Referring to FIG. 12, the IJ region can be seen. FIG. 13 shows a cross-sectional view of the IJ region. The configuration shown in FIG. 13 may be the same as the configuration shown in FIG. 9. A description of the same configuration as the configuration shown in FIG. 9 among the configurations shown in FIG. 13 may be omitted. Referring to FIG. 13, similar to the second metal pattern 1220 of FIG. 9, the second metal pattern 1220 of FIG. 13 may also be disposed below the first active layer ACT1. In this case, the second metal pattern 1220 may be disposed in the non-transmitting region NTA2. The second metal pattern 1220 may be a transparent metal. When the second metal pattern 1220 is a transparent metal, the transmittance of the non-transmitting region NTA2 can be further improved.

[0304] 12, the KL region can be seen. The KL region is a region that separates the sixth metal island 1221, the first data line 431, the second data line 432, and the seventh metal island 1222. A cross-sectional view of the KL region is shown in FIG. 14.

[0305] FIG. 14 is a cross-sectional view of the KL region shown in FIG.

[0306] 14, the sixth metal island 1221 may be disposed in the same layer as the first data line 431 and the second data line 432. Based on the horizontal direction, the sixth metal island 1221 may be disposed apart from the first data line 431 and the second data line 432.

[0307] 14, the seventh metal island 1222 may be disposed in the same layer as the first data line 431 and the second data line 432. Based on the horizontal direction, the seventh metal island 1222 may be disposed apart from the first data line 431 and the second data line 432.

[0308] 12 and 14, the metal patterns 1210 and 1220 can include multiple break points. Thus, the first metal pattern 1210 can include multiple metal islands 1211, 1212, 1213, 1214, and 1215, and the second metal pattern 1220 can also include multiple metal islands 1221, 1222, 1223, 1224, and 1225.

[0309] When the metal pattern is arranged as Irish metal, the metal pattern does not need to overlap the data line DL. The metal pattern can extend in a first direction DR1, and the data line DL can extend in a second direction DR2, and at least a portion of the metal pattern can include a broken shape at the point where the metal pattern and the data line DL intersect. This allows the data line DL to be arranged on the same layer as the metal pattern.

[0310] That is, the metal pattern disposed in the non-transmissive region NTA2 may be a transparent metal, thereby improving the transmittance of the non-transmissive region NTA2. Also, the data line DL disposed in the non-transmissive region NTA2 may be a transparent metal, in which case the transmittance of the non-transmissive region NTA2 can be further improved.

[0311] However, the data line DL may be designed so that only a portion is made of transparent metal and the other portion includes opaque metal, as will be described with reference to FIG.

[0312] FIG. 15 is a plan view of an optical region in which a metal pattern is disposed according to an embodiment of the present disclosure.

[0313] Referring to FIG. 15, the metal patterns 1210 and 1220 shown in FIG. 15 are the same as the metal patterns shown in FIG.

[0314] Referring to FIG. 15, the plurality of data lines DL may include transparent wiring portions 431b and 432b and opaque wiring portions 431a, 431c, 432a and 432c.

[0315] The transparent wiring portions 431b and 432b may be disposed in the transmissive region TA2. The transparent wiring portions 431b and 432b may be disposed in the same layer as the metal patterns 1210 and 1220.

[0316] The opaque wiring portions 431a, 431c, 432a, and 432c may be disposed in the non-transparent area NTA2. The opaque wiring portions 431a, 431c, 432a, and 432c may be disposed in a layer higher than the layer in which the metal patterns 1210 and 1220 are disposed. The opaque wiring portions 431a, 431c, 432a, and 432c may be connected to the transparent wiring portions 431b and 432b, and the opaque wiring portions 431a, 431c, 432a, and 432c may be connected to the transparent wiring portions 431b and 432b via the jumping wiring structure shown in FIG.

[0317] For example, the transparent wiring portions 431b and 432b are disposed in the transmissive region TA2 and may be disposed in the same layer as the metal patterns 1210 and 1220. The opaque wiring portions 431a, 431c, 432a, and 432c may be located in a higher layer than the transparent wiring portions 431b and 432b, and for example, the opaque wiring portions 431a, 431c, 432a, and 432c may be disposed on the first planarization layer 621 or the second planarization layer 622. The opaque wiring portions 431a, 431c, 432a, and 432c may include a first source-drain metal or a second source-drain metal.

[0318] The opaque wiring portions 431a, 431c, 432a, and 432c may be disposed on the first planarization layer 621 or the second planarization layer 622, and may extend from the non-transmissive region NTA2 toward the transmissive region TA2. In this case, the opaque wiring portions 431a, 431c, 432a, and 432c may be connected to the transparent wiring portions 431b and 432b through contact holes formed in the insulating layer, and the transparent wiring portions 431b and 432b may extend into the transmissive region TA2.

[0319] 15, the opaque wiring portions 431a, 431c, 432a, and 432c may be disposed only in the non-transmissive region NTA2. The transparent wiring portions 431b and 432b may be disposed in the transmissive region TA2 and may extend to a portion of the non-transmissive region NTA2. If the opaque wiring portions 431a, 431c, 432a, and 432c extend to a portion of the transmissive region TA2, the transmittance of the transmissive region TA2 may be reduced. To prevent this, the transparent wiring portions 431b and 432b may extend from the transmissive region TA2 to a portion of the non-transmissive region NTA2.

[0320] 16 and 17 are plan views of optical regions on which metal patterns are disposed according to embodiments of the present disclosure.

[0321] Referring to FIG. 16, the first optical area OA1 can include a plurality of transmissive areas TA2 and non-transmissive areas NTA1.

[0322] Referring to FIG. 16, the plurality of transmissive regions TA1 may include a first transmissive region TA1a, a second transmissive region TA1b, a third transmissive region TA1c, and a fourth transmissive region TA1d.

[0323] The plurality of transmissive areas TA1 may correspond to common electrode holes CH1, which are areas where a portion of the common electrode CE is removed.

[0324] The second transmissive region TA1b may be arranged in line with the first transmissive region TA1a in the first direction DR1.

[0325] The third transmissive region TA1c may be aligned with the fourth transmissive region TA1d in the second direction DR2. The third transmissive region TA1c may be located at the upper right corner of the first transmissive region TA1a. The third transmissive region TA1c may be located at the upper left corner of the second transmissive region TA1b.

[0326] The fourth transmissive region TA1d may be located at the lower right corner of the first transmissive region TA1a, and the fourth transmissive region TA1d may be located at the lower left corner of the second transmissive region TA1b.

[0327] The light-emitting area EA can be located in the non-transmissive area NTA1. The light-emitting area EA may be disposed between the transmissive areas TA2.

[0328] The light-emitting area EA can be located between the transmissive areas TA2 arranged in a line in the first direction DR1.

[0329] The light-emitting area EA can be located between the transmissive areas TA2 arranged in a line in the second direction DR2.

[0330] Metal patterns 1611, 1612, and 1613 can be disposed in the non-transparent area NTA1.

[0331] The metal patterns 1611, 1612, 1613 may extend in a first direction DR1.

[0332] The metal patterns 1611, 1612, and 1613 do not necessarily have to be disposed in the transmissive area TA1.

[0333] The metal patterns 1611, 1612, 1613 may have a curved line shape.

[0334] For example, the upper end of the first transmissive region TA1a may be positioned relatively higher than the lower end of the third transmissive region TA1c. In this case, the first metal pattern 1611 may extend to pass above the first transmissive region TA1a. The first metal pattern 1611 may extend in the first direction DR1 and may extend to pass below the third transmissive region TA1c. Referring to FIG. 16, it can be seen that the first metal pattern 1611 has a curved line shape.

[0335] A plurality of data lines DL may extend from the non-transmissive area NTA1 to the transmissive area TA1.

[0336] The multiple data lines DL may extend in a second direction DR2.

[0337] The first data line group 441 may be arranged to pass through the first transmissive area TA1a, and may include four data lines.

[0338] The second data line group 442 may be arranged to pass through the third transmissive area TA1c and the fourth transmissive area TA1d. The second data line group 442 may include four data lines.

[0339] The third data line group 443 may be arranged to pass through the second transmissive area TA1b, and the third data line group 443 may include four data lines.

[0340] The fourth data line group 444 may be arranged to pass through the transmissive area TA2. The fourth data line group 444 may include four data lines.

[0341] 16, the metal patterns 1611, 1612, and 1613 may extend in a first direction DR1, and the plurality of data lines DL may extend in a second direction DR2. Therefore, the metal patterns 1611, 1612, and 1613 may overlap the plurality of data lines DL. Alternatively, the metal patterns 1611, 1612, and 1613 may cross the plurality of data lines DL. The data lines DL may have the jumping wiring structure shown in FIG. 11. In the region where the data lines DL overlap the metal patterns, portions of the data lines may be disposed on the metal patterns.

[0342] The metal patterns 1611, 1612, and 1613 may be made of transparent metal, which can further improve the transmittance of the non-transmissive area NTA1.

[0343] The plurality of data lines DL may include a transparent metal, which can improve the transmittance of the transmissive area TA1 and the non-transmissive area NTA1.

[0344] Referring to FIG. 17, metal patterns 1711, 1712, 1713, and 1714 may be arranged to extend in a second direction DR2.

[0345] Referring to FIG. 17, a first metal pattern 1711 may be disposed between the first data line group 441 and the second data line group 442 .

[0346] Referring to FIG. 17, the second metal pattern 1712 may be disposed between the second data line group 442 and the third data line group 443 .

[0347] Referring to FIG. 17, the third metal pattern 1713 may be disposed between the third data line group 443 and the fourth data line group 444 .

[0348] Referring to FIG. 17, a fourth metal pattern 1714 may be disposed to the right of the fourth data line group 444 .

[0349] The multiple data lines DL may extend in a second direction DR2.

[0350] The data lines DL may be arranged spaced apart from the metal patterns 1611, 1612, and 1613.

[0351] The metal patterns 1611, 1612, and 1613 may include a transparent material, which can improve the transmittance of the non-transmissive area NTA1.

[0352] The data lines DL may include a transparent material, which can improve the transmittance of the non-transmissive area NTA1 and the transmissive area TA1.

[0353] The metal patterns 1611, 1612, 1613 shown in FIGS. 16 and 17 can be disposed between the substrate 210 and the first buffer layer 611 shown in FIG.

[0354] Some of the data lines DL shown in FIG. 16 can be disposed between the substrate 210 and the first buffer layer 611 shown in FIG.

[0355] The multiple data lines DL shown in FIG. 17 can be disposed between the substrate 210 and the first buffer layer 611 shown in FIG.

[0356] The above-described embodiment of the present disclosure can be briefly described as follows.

[0357] An embodiment of the present disclosure can provide a display device including: a substrate including a display area where an image is displayed, the display area including an optical area including a general area and a plurality of transmissive areas, the optical area further including a non-transmissive area that is the outline of the plurality of transmissive areas; a first metal pattern disposed on the substrate and in the non-transmissive area and including a transparent material; a first data line disposed on the substrate and spanning the non-transmissive area and at least one transmissive area of ​​the plurality of transmissive areas; and a first active layer disposed on the first metal pattern and overlapping the first metal pattern.

[0358] The first data line may extend from a first transmissive region included in the plurality of transmissive regions to the non-transmissive region, a portion of the first data line located in the first transmissive region may include a transparent material, and a portion of the first data line located in the non-transmissive region may include the transparent material or an opaque material different from the transparent material.

[0359] The first data line may further include a first wiring portion disposed on the same layer as the first metal pattern, extending from a first transmissive region included in the plurality of transmissive regions to the non-transmissive region, and including the transparent material; a second wiring portion disposed on the first metal pattern, electrically connected to the first wiring portion, and including an opaque material; and a third wiring portion disposed on the same layer as the first metal pattern, extending from the non-transmissive region to the second transmissive region, electrically connected to the second wiring portion, and including the transparent material.

[0360] The display device may further include an optical device disposed below the substrate, at least a portion of which is disposed in the first transmission region, and the first wiring portion and the third wiring portion may overlap with the optical device.

[0361] The light-emitting device may further include an optical device disposed below the substrate, at least a portion of which is disposed in the non-transmitting region, and the first metal pattern may overlap the optical device.

[0362] The first metal pattern can include a first island metal disposed in the same layer as the first data line, and a second island metal disposed in the same layer as the first data line but spaced apart from the first island metal with the first data line in between.

[0363] The first data line may extend from the non-transmissive region to the first transmissive region, but may be arranged to pass through a region between the first metal island and the second metal island, and may include the transparent material.

[0364] The first data line is arranged to pass through a region between the first island metal and the second island metal, and can include a transparent wiring portion that is arranged in a first transmissive region included in the plurality of transmissive regions and includes the transparent material, and an opaque wiring portion that is arranged in the non-transmissive region, is electrically connected to the transparent wiring portion, and includes an opaque material.

[0365] The first metal pattern and the first data line may be spaced apart from each other, and the first metal pattern and the first data line may be arranged to extend in the same direction.

[0366] The amount of charge under the first metal pattern may be greater than the amount of charge above the first metal pattern.

[0367] The semiconductor device may further include a second active layer containing a material different from that contained in the first active layer, and the area of ​​the first active layer may be larger than the area of ​​the second active layer.

[0368] An embodiment of the present disclosure can provide a display device including: a substrate including a display area where an image is displayed, the display area including an optical area including a general area and a plurality of transmissive areas, the optical area further including a non-transmissive area that is an outline of the plurality of transmissive areas; a first sub-pixel located on the substrate, disposed in the non-transmissive area, and including a first transistor; a second sub-pixel located on the substrate, disposed in the non-transmissive area, and including a second transistor; a first data line connected to the first sub-pixel and disposed across the non-transmissive area and at least one transmissive area of ​​the plurality of transmissive areas; a second data line connected to the second sub-pixel and disposed across the non-transmissive area and at least one transmissive area of ​​the plurality of transmissive areas; and a first metal pattern located in the non-transmissive area, located below the first transistor and the second transistor, and overlapping with at least a portion of the first transistor and at least a portion of the second transistor, the first metal pattern having a line shape.

[0369] The first metal pattern may include a transparent material.

[0370] The first metallic pattern may extend over the general area.

[0371] The display device may further include a second metal pattern disposed in the same layer as the first metal pattern, disposed in the general area, and including an opaque material.

[0372] The first metal pattern may have a curved line shape.

[0373] The first metal pattern may have a line shape without breaks.

[0374] The first metal pattern may have a line shape with at least one break point.

[0375] The first data line and the second data line may include the same transparent material as the first metal pattern.

[0376] The first metal pattern may intersect with the first data line and the second data line in a first region and a second region, respectively; the first data line includes a first opaque line portion disposed in the first region and a first transparent line portion disposed in a region different from the first region; the first opaque line portion and the first transparent line portion may be electrically connected via a first contact hole in an insulating layer disposed between the first opaque line portion and the first transparent line portion; the second data line includes a second opaque line portion disposed in the second region and a second transparent line portion disposed in a region different from the second region; and the second opaque line portion and the second transparent line portion may be electrically connected via a second contact hole in the insulating layer disposed between the second opaque line portion and the second transparent line portion.

[0377] The above description merely exemplifies the technical idea of ​​the present disclosure, and various modifications and variations are possible by a person having ordinary skill in the art to which the present disclosure pertains, without departing from the essential characteristics of the present disclosure. Furthermore, the embodiments shown in the present disclosure are for the purpose of explanation, and do not limit the technical idea of ​​the present disclosure, and therefore the scope of the technical idea of ​​the present disclosure is not limited by these embodiments. [Explanation of symbols]

[0378] 100 display device 110 Display panel 220 Data drive circuit 230 Gate drive circuit 240 Controller

Claims

1. a substrate including a display area in which an image is displayed, the display area including an optical area including a general area and a plurality of transmissive areas, the optical area further including a non-transmissive area that is an outer periphery of the plurality of transmissive areas; a first metal pattern disposed on the substrate and disposed in the non-transmissive area, the first metal pattern including a transparent material; a first data line disposed on the substrate and extending across the non-transmissive region and at least one of the plurality of transmissive regions; a first active layer disposed on and overlapping the first metal pattern.

2. the first data line extends from a first transmissive region included in the plurality of transmissive regions to the non-transmissive region; a portion of the first data line located in the first transmissive region includes a transparent material; The display device according to claim 1 , wherein a portion of the first data line located in the non-transmissive region includes the transparent material or an opaque material different from the transparent material.

3. The first data line is a first wiring portion that is disposed in the same layer as the first metal pattern, extends from a first transmissive region included in the plurality of transmissive regions to the non-transmissive region, and includes the transparent material; a second wiring portion disposed on the first metal pattern and electrically connected to the first wiring portion, the second wiring portion including an opaque material; 2. The display device according to claim 1, further comprising: a third wiring portion disposed in the same layer as the first metal pattern, extending from the non-transmissive region to the second transmissive region, electrically connected to the second wiring portion, and including the transparent material.

4. an optical device disposed beneath the substrate, the optical device being at least partially disposed in the first transmissive region; The display device according to claim 3 , wherein the first wiring portion and the third wiring portion are overlapped with the optical device.

5. an optical device disposed below the substrate and at least a portion of which is disposed in the non-transmissive region; The display device according to claim 1 , wherein the first metal pattern overlaps the optical device.

6. The first metal pattern comprises: a first island metal disposed in the same layer as the first data line; 2. The display device according to claim 1, further comprising a second island metal disposed in the same layer as the first data line but spaced apart from the first island metal with the first data line interposed therebetween.

7. 7. The display device of claim 6, wherein the first data line extends from the non-transmissive region to the transmissive region, passes through a region between the first metal island and the second metal island, and includes the transparent material.

8. The first data line is a transparent wiring portion that is disposed so as to pass through a region between the first metal island and the second metal island, that is disposed in a first transmission region included in the plurality of transmission regions, and that includes the transparent material; The display device according to claim 6 , further comprising: an opaque wiring portion that is disposed in the non-transmissive region, electrically connected to the transparent wiring portion, and that includes an opaque material.

9. the first metal pattern and the first data line are spaced apart from each other; The display device according to claim 1 , wherein the first metal pattern and the first data line are arranged to extend in the same direction.

10. The display device of claim 1 , wherein the amount of charge under the first metal pattern is greater than the amount of charge above the first metal pattern.

11. further comprising a second active layer comprising a material different from the material comprised in the first active layer; The display device according to claim 1 , wherein the area of ​​the first active layer is larger than the area of ​​the second active layer.

12. a substrate including a display area in which an image is displayed, the display area including an optical area including a general area and a plurality of transmissive areas, the optical area further including a non-transmissive area that is an outer periphery of the plurality of transmissive areas; a first subpixel disposed on the substrate and in the non-transmissive region, the first subpixel including a first transistor; a second sub-pixel disposed on the substrate and in the non-transmissive region, the second sub-pixel including a second transistor; a first data line connected to the first subpixel and disposed across the non-transmissive region and at least one transmissive region of the plurality of transmissive regions; a second data line connected to the second subpixel and disposed across the non-transmissive region and at least one of the plurality of transmissive regions; a first metal pattern having a line shape, disposed in the non-transmissive region, positioned below the first transistor and the second transistor, and overlapping with at least a portion of the first transistor and at least a portion of the second transistor.

13. The display device of claim 12 , wherein the first metal pattern comprises a transparent material.

14. 13. The display device of claim 12, wherein the first metal pattern extends over the general area.

15. 13. The display device of claim 12, further comprising a second metal pattern disposed in the same layer as the first metal pattern, disposed in the general area, and comprising an opaque material.

16. The display device of claim 12 , wherein the first metal pattern has a curved line shape.

17. The display device according to claim 12 , wherein the first metal pattern has a line shape without breaks.

18. The display device of claim 12 , wherein the first metal pattern has a line shape with at least one break point.

19. The display device of claim 12 , wherein the first data line and the second data line comprise the same transparent material as the first metal pattern.

20. the first metal pattern intersects with the first data line and the second data line in a first region and a second region, respectively; the first data line includes a first opaque line portion disposed in the first region and a first transparent line portion disposed in a region different from the first region, and the first opaque line portion and the first transparent line portion are electrically connected to each other through a first contact hole in an insulating layer disposed between the first opaque line portion and the first transparent line portion; 20. The display device of claim 19, wherein the second data line includes a second opaque line portion arranged in the second region and a second transparent line portion arranged in a region different from the second region, and the second opaque line portion and the second transparent line portion are electrically connected via a second contact hole in the insulating layer arranged between the second opaque line portion and the second transparent line portion.

Images