Semiconductor device and method of manufacturing the same

Abstract

Various embodiments of the present invention relate to integrated circuits (ICs). To reduce defects between a semiconductor layer and a substrate, to improve crystal quality of the semiconductor layer, and to reduce a dark current of a photodetector.SOLUTION: The IC comprises a substrate comprising a first material. The semiconductor layer is provided on the substrate and includes a second material different from the first material. The buffer layer is disposed between the semiconductor layer and the substrate. The buffer layer includes a first material and a second material.SELECTED DRAWING: Figure 1

Description

[Background technology]

[0001] An image sensor is a solid-state device configured to convert incident light into an electrical signal. This electrical signal is sent to a processor, which converts it into data that can be stored and / or viewed by the user. Integrated chips (ICs) containing image sensors are used in a wide range of modern electronic devices, including mobile phones, cameras, and medical devices. Summary of the Invention [Problem to be solved by the invention]

[0002] Image sensor integrated chips (ICs) may include photodetectors configured to detect infrared (IR) radiation. This allows the image sensor IC to be used for time-of-flight (TOF) depth sensing and other suitable applications. However, image sensor ICs are typically constructed with silicon-based photodetectors. Silicon has a large bandgap, meaning that the absorption coefficient of silicon decreases as the wavelength of radiation increases. As a result, silicon-based photodetectors can have low quantum efficiency (QE) for IR radiation. To improve the QE for IR radiation, silicon-based photodetectors can be replaced with germanium-based photodetectors. Because germanium has a smaller bandgap than silicon, it has higher absorption in the IR spectrum than silicon. Therefore, germanium-based photodetectors have a high QE for IR radiation.

[0003] A method for forming a germanium-based photodetector may include etching a silicon substrate to form a trench extending to the silicon substrate, forming a germanium layer in the trench in contact with the silicon substrate, and forming a photodetector in the germanium layer. However, it is known that the difference in lattice constant between the silicon substrate and the germanium layer can cause defects (e.g., dislocation defects) to occur along the interface between the silicon substrate and the germanium layer. These defects can degrade the crystalline quality of the germanium layer and cause dark current leakage within the photodetector, thereby reducing the photodetector's signal-to-noise ratio (SNR), quantum efficiency (QE), and the like. This can result in a reduced ability to accurately detect IR radiation. [Means for solving the problem]

[0004] In some embodiments, the present invention provides an integrated chip (IC) that includes a substrate including a first material, a semiconductor layer disposed on the substrate and including a second material different from the first material, and a buffer layer disposed between the semiconductor layer and the substrate and including the first material and the second material.

[0005] The present invention, in some embodiments, provides an integrated chip (IC) that includes a substrate having a top surface, a germanium layer disposed on the top surface of the substrate, an isolation structure disposed within the substrate and on an opposing side of the germanium layer, a buffer layer disposed between the top surface of the substrate and the germanium layer, the buffer layer comprising silicon and germanium, and a passivation layer in contact with the top surface of the germanium layer and comprising epitaxial silicon.

[0006] In some embodiments, the present invention provides a method for forming an integrated chip (IC), the method including: forming a buffer layer on a substrate, the substrate including a first material, the buffer layer including the first material and a second material different from the first material; forming a semiconductor layer on the buffer layer, the semiconductor layer including the second material; and forming a passivation layer along a top surface of the semiconductor layer, the passivation layer including the first material. [Effects of the Invention]

[0007] Some embodiments of the present invention relate to an integrated chip (IC) including a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. The substrate includes a first material (e.g., silicon), and the semiconductor layer includes a second material (e.g., germanium) different from the first material. The buffer layer is disposed between the substrate and the semiconductor layer and includes the first material and the second material. By including the first material and the second material, the buffer layer can mitigate problems caused by the difference in lattice constant between the semiconductor layer and the substrate. This reduces defects between the semiconductor layer and the substrate, improves the crystal quality of the semiconductor layer, and reduces the dark current of the photodetector. As a result, the SNR, QE, and overall performance of the photodetector can be improved. [Brief explanation of the drawings]

[0008] Aspects of the present invention are best understood by reading the following detailed description in conjunction with the accompanying drawings. The figures are drawn to clearly show relevant aspects of the embodiments. The figures may show relationships between various structures and / or elements within the embodiments. It is noted that the figures are not necessarily drawn to scale. In some instances, dimensions of various features may be arbitrarily expanded or reduced for clarity of illustration. [Figure 1] 1A-1C illustrate cross-sectional views of some embodiments of an integrated chip (IC) with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 2A]10A-10C show various views of several other embodiments of an IC that includes a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 2B] 10A-10C show various views of several other embodiments of an IC that includes a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 3A] 2A-2B show various views of some other embodiments of the IC of FIGS. [Figure 3B] 2A-2B show various views of some other embodiments of the IC of FIGS. [Figure 4A] 10A-10C show various views of several other embodiments of an IC that includes a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 4B] 10A-10C show various views of several other embodiments of an IC that includes a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 5A] 4A-4B show various views of some other embodiments of the present invention. [Figure 5B] 4A-4B show various views of some other embodiments of the present invention. [Figure 6A] 2A-2C illustrate cross-sectional views of some other embodiments of the IC of FIG. 1. [Figure 6B] 2A-2C illustrate cross-sectional views of some other embodiments of the IC of FIG. 1. [Figure 7A] 2A-2B, in which the buffer layer comprises multiple buffer films. [Figure 7B] 2A-2B, in which the buffer layer comprises multiple buffer films. [Figure 7C] 6B illustrates a cross-sectional view of some other embodiments of the IC of FIG. 6A, in which the buffer layer comprises multiple buffer films. [Figure 7D] 10A-10C show various cross-sectional views of several other embodiments of an IC that includes a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 7E] 10A-10C show various cross-sectional views of several other embodiments of an IC that includes a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 7F] 10A-10C show various cross-sectional views of several other embodiments of an IC that includes a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 8A] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 8B] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 9A] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 9B] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 10A] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 10B] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 11A] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 11B] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 12A] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 12B]1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 13A] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 13B] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 14A] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 14B] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 15A] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 15B] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 16A] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 16B] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 17A] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 17B] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 18A]1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 18B] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 19A] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 19B] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 20A] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 20B] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 21A] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 21B] 1A-1C show a series of various views of several embodiments of a method for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 22] 1A-1C illustrate flow diagrams of several embodiments of methods for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. [Figure 23] 10A-10C illustrate a series of cross-sectional views of several other embodiments of methods for forming an IC with a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 24] 10A-10C illustrate a series of cross-sectional views of several other embodiments of methods for forming an IC with a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 25]10A-10C illustrate a series of cross-sectional views of several other embodiments of methods for forming an IC with a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 26] 10A-10C illustrate a series of cross-sectional views of several other embodiments of methods for forming an IC with a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 27] 10A-10C illustrate a series of cross-sectional views of several other embodiments of methods for forming an IC with a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 28] 10A-10C illustrate a series of cross-sectional views of several other embodiments of methods for forming an IC with a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 29] 10A-10C illustrate a series of cross-sectional views of several other embodiments of methods for forming an IC with a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 30] 10A-10C illustrate a series of cross-sectional views of several other embodiments of methods for forming an IC with a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 31] 10A-10C illustrate a series of cross-sectional views of several other embodiments of methods for forming an IC with a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 32] 10A-10C illustrate a series of cross-sectional views of several other embodiments of methods for forming an IC with a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 33] 10A-10C illustrate a series of cross-sectional views of several other embodiments of methods for forming an IC with a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 34] 10A-10C illustrate a series of cross-sectional views of several other embodiments of methods for forming an IC with a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 35] 10A-10C illustrate a series of cross-sectional views of several other embodiments of methods for forming an IC with a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 36] 10A-10C illustrate a series of cross-sectional views of several other embodiments of methods for forming an IC with a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 37] 10A-10C illustrate a series of cross-sectional views of several other embodiments of methods for forming an IC with a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 38] 10A-10C illustrate a series of cross-sectional views of several other embodiments of methods for forming an IC with a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 39] 10A-10C illustrate a series of cross-sectional views of several other embodiments of methods for forming an IC with a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 40] 10A-10C illustrate a series of cross-sectional views of several other embodiments of methods for forming an IC with a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 41] 10A-10C illustrate a series of cross-sectional views of several other embodiments of methods for forming an IC with a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 42] 10A-10C illustrate a series of cross-sectional views of several other embodiments of methods for forming an IC with a buffer layer disposed between the substrate and the semiconductor layer of the photodetector. [Figure 43] 1A-1C illustrate flow diagrams of several embodiments of methods for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. DETAILED DESCRIPTION OF THE INVENTION

[0009] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. To simplify the present invention, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, a first feature formed on a second feature may include an embodiment in which the first and second features are formed in direct contact with each other, and may also include an embodiment in which an additional feature is formed between the first and second features, such that the first and second features do not need to be in direct contact with each other. Furthermore, the present invention may describe various examples by repeating symbols and / or wording. This repetition is for the purposes of brevity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0010] Additionally, spatially relative terms such as "bottom," "lower," "lower side," "upper," and "top" may be used herein to facilitate describing the relationship of one element or feature to another, as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein may be interpreted similarly. In some embodiments, the terms "about" and / or "approximately" may be interpreted to mean ±10% or ±5%, while in other embodiments, the terms "about" and / or "approximately" may be interpreted to mean within normal manufacturing tolerances for a given manufacturing flow.

[0011] FIG. 1 illustrates a cross-sectional view 100 of some embodiments of an integrated chip (IC) that includes a buffer layer 108 disposed between a substrate 102 and a semiconductor layer 110 of a photodetector 104 .

[0012] The IC includes a substrate 102 having one or more surfaces defining a trench that extends to a top surface 102t of the substrate 102. For example, the substrate 102 includes opposing sidewalls 102s1, 102s2 and a bottom surface 102ls that defines the trench. The photodetector 104 includes a semiconductor layer 110 disposed within a recess and one or more doped regions 118, 120. The substrate 102 includes a first material, and the semiconductor layer 110 includes a second material that is different from the first material. In some embodiments, the first material is or includes silicon, crystalline silicon, and / or other semiconductor materials. In some embodiments, the majority of the substrate 102 includes a first doping type (e.g., p-type). In various embodiments, the second material is or includes germanium, silicon germanium (SiGe) with a high concentration of germanium, silicon carbide (SiC), or the like. In further embodiments, semiconductor layer 110 consists essentially of germanium, silicon germanium, or silicon carbide. In some embodiments, semiconductor layer 110 is largely undoped. For example, semiconductor layer 110 is or includes the intrinsic form of a second material (e.g., includes intrinsic germanium). In further embodiments, semiconductor layer 110 is largely undoped at a concentration of about 5.69e15 to 9.4e14 atoms / cm. 3 It comprises a first doping type (eg, p-type) having the following doping concentrations, or other suitable values:

[0013] The intermediate layer 106 extends along opposing sidewalls 102s1, 102s2 of the substrate 102 and along the bottom surface 102ls that defines the trench. The intermediate layer 106 is disposed between the substrate 102 and the semiconductor layer 110. The intermediate layer 106 is made of the same material as the substrate 102 and a different material from the second material of the semiconductor layer 110. The intermediate layer 106 is or includes, for example, silicon, epitaxial silicon, or another semiconductor material. In various embodiments, the intermediate layer 106 is undoped. In some embodiments, the top surface of the intermediate layer 106 is aligned with the top surface 102t of the substrate 102.

[0014] The buffer layer 108 is disposed along opposing sidewalls and a bottom surface of the semiconductor layer 110. The buffer layer 108 is disposed between the intermediate layer 106 and the semiconductor layer 110. In some embodiments, the buffer layer 108 is in direct contact with the opposing sidewalls and a bottom surface of the semiconductor layer 110. Furthermore, the buffer layer 108 includes a first material (e.g., silicon) and a second material (e.g., germanium). In various embodiments, the buffer layer 108 is undoped. In various embodiments, the buffer layer 108 is a single continuous layer that extends continuously from the inner surface of the intermediate layer 106 to the outer surface of the semiconductor layer 110. In such embodiments, a first concentration of the first material (e.g., silicon) in the buffer layer 108 may decrease continuously from the intermediate layer 106 to the semiconductor layer 110, and a second concentration of the second material (e.g., germanium) in the buffer layer 108 may increase continuously from the intermediate layer 106 to the semiconductor layer 110. In further embodiments, buffer layer 108 may include multiple individual buffer films (not shown) having different concentrations of the first and second materials. In various embodiments, the top surface of buffer layer 108 is aligned with the top surface of semiconductor layer 110. Additionally, the top surfaces of buffer layer 108 and semiconductor layer 110 may be recessed a non-zero distance below top surface 102t of substrate 102.

[0015] In some embodiments, when the first material of the substrate 102 is silicon and the second material of the semiconductor layer 110 is germanium, the buffer layer 108 is silicon germanium (e.g., Si x Ge 1-x , where x ranges from 1 to 0). In such embodiments, buffer layer 108 may include a relatively thin (e.g., 2 to 3 nanometers (nm) thick or less) region or film comprising silicon along intermediate layer 106, with the remainder of buffer layer 108 being Si x Ge 1-xwhere x ranges from 0.995 to 0. In a further embodiment, when semiconductor layer 110 comprises silicon germanium and substrate 102 comprises silicon, buffer layer 108 comprises silicon germanium. In such an embodiment, the concentration of germanium in semiconductor layer 110 may be greater than the maximum concentration of germanium in buffer layer 108. In yet another embodiment, when semiconductor layer 110 comprises silicon carbide and substrate 102 comprises silicon, buffer layer 108 comprises silicon germanium (e.g., Si x C 1-x , where x ranges from 1 to 0).

[0016] A passivation layer 112 is disposed on the buffer layer 108 and the semiconductor layer 110. In some embodiments, the passivation layer 112 extends continuously along the top surface of the buffer layer 108 and the top surface of the semiconductor layer 110 to the opposing inner sidewalls of the intermediate layer 106. The passivation layer 112 comprises the same material as the substrate 102 and a different material from the second material of the semiconductor layer. The passivation layer 112 may comprise, for example, silicon, epitaxial silicon, or other suitable material. In various embodiments, the passivation layer 112 is largely undoped. The passivation layer 112 may also be referred to as a capping layer or a protective layer. Isolation structures 114 are disposed on opposing sides of the semiconductor layer 110 and extend from the top surface 102t of the substrate 102 to a point below the intermediate layer 106. The isolation structure 114 is configured to improve optical and / or electrical isolation between the photodetector 104 and an adjacent photodetector (not shown). Additionally, a dielectric structure 116 is disposed on the substrate 102.

[0017] In various embodiments, the photodetector 104 further comprises a first doped region 118 and a second doped region 120. The first doped region 118 has a first doping type (e.g., p-type) and the second doped region 120 has a second doping type (e.g., n-type) opposite the first doping type. In various embodiments, the first doped region 118 and the second doped region 120 extend from the passivation layer 112 to the semiconductor layer 110. In various embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa. In some embodiments, the doping concentration of each of the first doped region 118 and the second doped region 120 is between about 1e16 and 1e17 atoms / cm. 3 or any other suitable value.

[0018] During operation of the IC, electromagnetic radiation incident on the semiconductor layer 110 can generate electron-hole pairs within the semiconductor layer 110. Applying a bias voltage to the first doped region 118 and the second doped region 120 can create an electric field within the semiconductor layer 110. This electric field can cause electrons released by the creation of electron-hole pairs to migrate to the second doped region 120, thereby generating a photocurrent. The generated photocurrent can be detected and / or read by readout circuitry (not shown). Thus, the photodetector 104 is configured to convert incident electromagnetic radiation into an electrical signal. The semiconductor layer 110, which includes a second material (e.g., germanium) having a relatively small bandgap (e.g., smaller than that of silicon), increases the absorption of IR radiation (e.g., radiation having a wavelength in the range of approximately 700 to 3,000 nm) by the photodetector 104. As a result, the photodetector 104, which includes the semiconductor layer 110 including the second material (e.g., germanium), improves the quantum efficiency (QE) of the photodetector 104 for IR radiation. In some embodiments, the photodetector 104 may be configured as a PIN photodiode, a PN photodiode, an avalanche photodiode, a depth sensor, or the like.

[0019] In various embodiments, the first lattice constant of the substrate 102 is different from the second lattice constant of the semiconductor layer 110. The buffer layer 108 includes a compound of the first material and the second material, and the lattice constant of the buffer layer 108 ranges between the first lattice constant and the second lattice constant. The lattice constant of the buffer layer 108 is more closely matched to the second lattice constant of the semiconductor layer 110 than to the first lattice constant of the substrate 102. As a result, the buffer layer 108 is configured to reduce defects between the substrate 102 and the semiconductor layer 110 and provide a good structural foundation that facilitates the formation or growth of a high crystalline quality semiconductor layer 110. Thus, the buffer layer 108, which includes a compound of the first material and the second material and is disposed along the horizontal and vertical interfaces between the substrate 102 and the semiconductor layer 110, can reduce leakage current (e.g., dark current) in the photodetector 104 and improve the performance of the photodetector 104.

[0020] In various embodiments, during IC fabrication, an etching process (e.g., dry etching) is performed on the substrate 102 to form opposing sidewalls 102s1, 102s2 and a bottom surface 102ls of the substrate 102 that define a recess. Ion bombardment from the etching process can result in crystalline defects (e.g., dangling bonds) along the opposing sidewalls 102s1, 102s2 and / or the bottom surface 102ls of the substrate 102. In some embodiments, the intermediate layer 106 is formed or grown by an epitaxial process along the opposing sidewalls 102s1, 102s2 and the bottom surface 102ls of the substrate 102. The intermediate layer 106 is configured to passivate crystalline defects from the etching process and provide a better structural foundation for subsequent layers (e.g., the buffer layer 108, the semiconductor layer 110, and / or the passivation layer 112) that are formed on the intermediate layer 106. As a result, the buffer layer 108, the semiconductor layer 110, and / or the passivation layer 112 each have higher crystalline quality and further reduced leakage current, which can further improve the performance of the photodetector 104.

[0021] The thickness 122 of the intermediate layer 106 is, for example, 40 nm or more, in the range of about 40 nm to 50 nm, or any other suitable value. In some embodiments, a thickness 122 of 40 nm or more facilitates growing the intermediate layer 106 on the substrate 102 with high crystalline quality that matches the crystalline structure of the substrate 102. As a result, the intermediate layer 106 can mitigate problems due to crystalline defects along the surface of the substrate 102 that defines the recess, thereby providing a better structural foundation for forming the buffer layer 108 and the semiconductor layer 110. In some embodiments, a thickness 122 of 50 nm or less increases the space for the semiconductor layer 110 within the recess, which can improve the quantum efficiency (QE) of the photodetector 104.

[0022] The thickness 124 of the buffer layer 108 is greater than 10 nm, in the range of about 10 nm to 100 nm, in the range of about 30 nm to 100 nm, or other suitable value. In some embodiments, a thickness 124 of 10 nm or greater facilitates growing the buffer layer 108 with high crystalline quality and sufficient thickness to provide a good structural foundation for forming the semiconductor layer 110 with reduced defects between the substrate 102 and the semiconductor layer 110. In some embodiments, a thickness 124 of 100 nm or less facilitates reducing the size of the photodetector 104 and increasing the space within the recess for the semiconductor layer 110, thereby improving the quantum efficiency (QE) of the photodetector 104. In various embodiments, the thickness 124 of the buffer layer 108 is less than the thickness 122 of the intermediate layer 106.

[0023] The thickness 126 of the semiconductor layer 110 may be, for example, 1 micrometer (μm) or greater, in the range of approximately 1 μm to 1.4 μm, or any other suitable value. In some embodiments, a thickness 126 of 1 μm or greater may increase the area over which the photodetector 104 detects electromagnetic radiation of interest (e.g., IR radiation), thereby improving the quantum efficiency (QE) of the photodetector 104. In some embodiments, a thickness 126 of 1.4 μm or less may reduce damage to the substrate 102 during an etching process used to form the recesses (e.g., by reducing the power and / or duration of the etching process used to form the recesses) and / or facilitate reducing the size of the photodetector 104.

[0024] In some embodiments, the ratio of thickness 124 of buffer layer 108 to thickness 126 of semiconductor layer 110 is in the range of 0.01 to 0.10. In various embodiments, a ratio of thickness 124 to thickness 126 of 0.01 or greater facilitates that buffer layer 108 is thick enough to provide a good structural foundation for semiconductor layer 110 and reduces defects between substrate 102 and semiconductor layer 110. In further embodiments, a ratio of thickness 124 to thickness 126 of 0.10 or less facilitates that buffer layer 108 better matches the second lattice constant of semiconductor layer 110 while simultaneously improving the quantum efficiency (QE) of photodetector 104. For example, buffer layer 108 may have lower absorption of IR radiation than semiconductor layer 110, and a ratio of thickness 124 to thickness 126 of 0.10 or less facilitates that semiconductor layer 110 is thick enough to improve absorption of IR radiation.

[0025] In various embodiments, the passivation layer 112 is in direct contact with the top surfaces of the semiconductor layer 110 and the buffer layer 108. In further embodiments, the top surface of the passivation layer 112 is flush with the top surface 102t of the substrate 102. The passivation layer 112 is configured to mitigate damage to the buffer layer 108 and / or the semiconductor layer 110 during IC fabrication. For example, the passivation layer 112 can mitigate damage to the buffer layer 108 and the semiconductor layer 110 during one or more etching processes (e.g., wet etching) performed on the substrate 102 after forming the semiconductor layer 110. This can improve the performance and reliability of the photodetector 104. The thickness 128 of the passivation layer 112 is, for example, greater than 40 nm, in the range of approximately 40 nm to 50 nm, or other suitable value. In some embodiments, a thickness 128 of 40 nm or greater facilitates the passivation layer 112 being thick enough to protect the semiconductor layer 110. In some embodiments, thickness 128 is 50 nm or less, which may increase the detection area of ​​photodetector 104, thereby improving the quantum efficiency (QE) of photodetector 104. In some embodiments, thickness 128 of passivation layer 112 is greater than thickness 124 of buffer layer 108. In some embodiments, thickness 128 of passivation layer 112 is equal to thickness 122 of intermediate layer 106.

[0026] FIG. 2A shows a cross-sectional view 200a of an IC according to another embodiment of the IC of FIG.

[0027] In some embodiments, the photodetector 104 comprises a semiconductor layer 110, a plurality of first contact regions 206, a second contact region 202, a plurality of outer lateral wells 208, and an intermediate well region 204. A majority of the substrate 102 comprises a first doping type (e.g., p-type). The plurality of first contact regions 206 are disposed within the substrate 102 and on opposite sides of the semiconductor layer 110. The plurality of first contact regions 206 comprise a second doping type (e.g., n-type). In various embodiments, each of the first contact regions 206 is spaced apart between the semiconductor layer 110 and a corresponding surface of the isolation structure 114. The first contact regions 206 are laterally offset from the intermediate layer 106. Furthermore, the first contact regions 206 extend continuously from the top surface 102t of the substrate 102 to a point below the top surface 102t.

[0028] Each outer lateral well of the plurality of outer lateral wells 208 is disposed below a corresponding contact region of the plurality of first contact regions 206 and extends continuously laterally from below the corresponding contact region to the semiconductor layer 110. In various embodiments, the outer lateral wells 208 extend laterally from the substrate 102, through corresponding upper regions of the intermediate layer 106 and the buffer layer 108, and to the semiconductor layer 110. The plurality of outer lateral wells 208 include a second doping type (e.g., n-type). It should be understood that for ease of illustration, at least a portion of the outer lateral wells 208 extending into the intermediate layer 106, the buffer layer 108, and the semiconductor layer 110 is shown in phantom.

[0029] The second contact region 202 is disposed within the passivation layer 112 and the semiconductor layer 110. The second contact region 202 has a first doping type (e.g., p-type). It should be understood that the second contact region 202 is shown in phantom lines for ease of illustration. The second contact region 202 extends continuously from the top surface of the passivation layer 112 to an upper region of the semiconductor layer 110. The second contact region 202 extends from the passivation layer 112 to the substrate 102 and the upper regions of the intermediate layer 106 and the buffer layer 108. In some embodiments, the width of the second contact region 202 is greater than the width of the passivation layer 112 and the width of the semiconductor layer 110.

[0030] The intermediate well region 204 is disposed within the semiconductor layer 110 below the passivation layer 112. The intermediate well region 204 comprises a first doping type (e.g., p-type). In some embodiments, the intermediate well region 204 extends continuously from the top surface of the semiconductor layer 110 to a point below the top surface of the semiconductor layer 110. In some embodiments, the majority of the semiconductor layer 110 offset from the intermediate well region 204 and the second contact region 202 comprises the first doping type (e.g., p-type) having a doping concentration lower than that of the intermediate well region 204. In yet another embodiment, the majority of the semiconductor layer 110 is undoped. The intermediate well region 204 is spaced apart between the outer lateral wells 208. The bottom of the intermediate well region 204 is disposed below the bottom of the outer lateral wells 208.

[0031] A dielectric structure 116 is disposed on the top surface 102t of the substrate 102. In some embodiments, the dielectric structure 116 includes one or more dielectric layers, each of which may include silicon dioxide, silicon carbide, silicon nitride, other dielectric materials, or any combination thereof. A plurality of conductive contacts 216 are disposed on the dielectric structure 116. The conductive contacts 216 are disposed over and electrically connected to corresponding regions of the first and second contact regions 206, 202. A plurality of conductive wires 218 are disposed on the dielectric structure 116 and are disposed over the conductive contacts 216. The conductive contacts and wires 216, 218 may be or include, for example, copper, aluminum, tungsten, ruthenium, titanium nitride, tantalum nitride, other conductive materials, or any combination thereof.

[0032] An isolation structure 114 is disposed within the substrate 102 and continuously covers the periphery of the semiconductor layer 110. In some embodiments, the isolation structure 114 includes an upper isolation doped region 210 and a lower isolation doped region 212 disposed below the upper isolation doped region 210. The upper isolation doped region 210 and the lower isolation doped region 212 are doped regions of the substrate 102, each having a first doping type (e.g., p-type). In various embodiments, the doping concentration of the upper isolation doped region 210 is higher than the doping concentration of the lower isolation doped region 212. Furthermore, the doping concentration of the lower isolation doped region 212 is higher than the doping concentration of the majority of the substrate 102. The isolation structure 114 is configured to improve electrical isolation between the photodetector 104 and other photodetectors (not shown) disposed within the substrate 102.

[0033] During operation of the IC, electromagnetic radiation incident on the semiconductor layer 110 can generate electron-hole pairs in the semiconductor layer 110. Applying a bias voltage to the first and second contact regions 206, 202 can create an electric field in the semiconductor layer 110. This electric field can cause emitted electrons (e.g., emitted by the creation of electron-hole pairs) to migrate toward the outer lateral well 208, thereby generating a photocurrent that can be detected and / or read by readout circuitry (not shown). Thus, in some embodiments, emitted electrons can migrate laterally from a central region of the semiconductor layer 110 (e.g., from the central well region 204) to the outer lateral well 208. A buffer layer 108 comprising a compound of a first material (e.g., silicon) and a second material (e.g., germanium) can mitigate defects (e.g., dislocation defects) at the interface between the semiconductor layer 110 and the substrate 102. In some embodiments, the outer lateral well 208 extends from the substrate 102 through the sidewalls of the intermediate layer 106, the buffer layer 108, and the semiconductor layer 110, thereby reducing defects and mitigating leakage current in the photodetector 104. For example, an increased number of defects at the interface between the semiconductor layer 110 and the substrate 102 can result in a large number of free charge carries (e.g., due to thermal generation) in the outer lateral well 208, increasing dark leakage current. In such embodiments, it can be difficult to distinguish between free charge carries and electrons released into the semiconductor layer 110 by incident electromagnetic radiation. Therefore, the buffer layer 108, including a compound of the first and second materials and spaced between the substrate 102 and the semiconductor layer 110, can reduce leakage current and improve the performance of the photodetector 104 (e.g., improve QE, SNR, etc.). In some embodiments, the photodetector 104 is configured as a PN photodiode, a PIN photodiode, etc.

[0034] In some embodiments, the intermediate well region 204, the majority of the substrate 102, the second contact region 202, the upper isolation doped region 210, and the lower isolation doped region 212 include a first dopant (e.g., boron, aluminum, gallium, etc.) having a first doping type (e.g., p-type). In various embodiments, the doping concentration of the second contact region 202 is higher than the doping concentration of the intermediate well region 204. The doping concentration of the second contact region 202 may be, for example, about 1e17 to 1e18 atoms / cm. 3 The doping concentration of the intermediate well region 204 may be, for example, about 1e16 to 1e17 atoms / cm 3 or other suitable values. In some embodiments, the doping concentration of the upper isolation doped region 210 is higher than the doping concentration of the lower isolation doped region 212. The doping concentration of the upper isolation doped region 210 may be, for example, about 1e18 to 1e20 atoms / cm 3 The doping concentration of the lower isolation doped region 212 may be, for example, about 1e16 to 1e18 atoms / cm 3 or any other suitable value.

[0035] In some embodiments, the first contact region 206 and the outer lateral well 208 include a second dopant (e.g., arsenic, antimony, phosphorous, etc.) having a second doping type (e.g., n-type). In some embodiments, the doping concentration of the first contact region 206 is higher than the doping concentration of the outer lateral well 208. The doping concentration of the first contact region 206 may be, for example, about 1e18 to 1e19 atoms / cm. 3 The doping concentration of the outer lateral well 208 may be, for example, about 1e16 to 1e17 atoms / cm 3 In various embodiments, the doping concentration of the first contact region 206 is higher than the doping concentration of the second contact region 202.

[0036] Figure 2B shows a top view 200b of some embodiments of the IC of Figure 2A. The cross-sectional view 200a of Figure 2A can be taken, for example, along line A-A' in Figure 2B. The top view 200b of Figure 2B can be taken, for example, along line A-A' in Figure 2A.

[0037] 2B , buffer layer 108 extends laterally continuously around the periphery of semiconductor layer 110. Intermediate layer 106 extends laterally continuously around the periphery of buffer layer 108. Isolation structures 114 extend laterally continuously around the periphery of semiconductor layer 110 and are laterally offset from intermediate layer 106. In some embodiments, intermediate well region 204 is aligned with the center of semiconductor layer 110.

[0038] The plurality of outer lateral wells 208 includes an individual outer lateral well disposed on each side of the semiconductor layer 110. For example, in some embodiments, the semiconductor layer 110 has a rectangular shape in a top view, and the plurality of outer lateral wells 208 includes an individual outer lateral well on each of the four sides of the semiconductor layer 110. It should be understood that the semiconductor layer 110 may have other shapes in a top view. In various embodiments, the plurality of first contact regions 206 includes individual contact regions on corresponding outer lateral wells in the plurality of outer lateral wells 208. In further embodiments, each outer lateral well 208 is laterally offset from a corresponding side of the intermediate well region 204 by a non-zero distance, e.g., greater than the thickness of the buffer layer 108.

[0039] 3A-3B show a cross-sectional view 300a and a top view 300b of an IC according to another embodiment of the IC of FIGS. 2A-2B. The cross-sectional view 300a of FIG. 3A can be taken, for example, along line A-A' in FIG. 3B. The top view 300b of FIG. 3B can be taken, for example, along line A-A' in FIG. 3A.

[0040] In some embodiments, the isolation structures 114 include a dielectric material disposed in trenches that extend to the top surface 102t of the substrate 102. The dielectric material of the isolation structures 114 may be or include, for example, silicon dioxide, silicon oxynitride, silicon nitride, silicon carbide, other dielectric materials, or any combination thereof.

[0041] 4A and 4B show a cross-sectional view 400a and a top view 400b corresponding to another embodiment of FIG. 1, in which the photodetector 104 is configured as an avalanche photodiode (APD), a single-photon avalanche diode (SPAD), etc. The cross-sectional view 400a of FIG. 4A can be taken, for example, along line A-A' in FIG. 4B. The top view 400b of FIG. 4B can be taken, for example, along line A-A' in FIG. 4A.

[0042] 4A , in some embodiments, the photodetector 104 includes a semiconductor layer 110, a first avalanche well 404, a second avalanche well 412, a vertical connection well 406, a first contact region 405, a second contact region 402, and a guard ring region 410. The bottom well 402 is disposed within the substrate 102 below the first avalanche well 404. The first avalanche well 404 is disposed below the semiconductor layer 110. The bottom well 402 includes a first doping type (e.g., p-type), and the first avalanche well 404 includes a second doping type (e.g., n-type). The first contact region 405 is disposed within the substrate 102 on an opposite side of the semiconductor layer 110 and includes the second doping type (e.g., n-type). In some embodiments, the first contact region 405 is annular and extends laterally around the semiconductor layer 110 (e.g., as shown in FIG. 4B ). The vertical connection well 406 is disposed in the substrate 102 and extends continuously vertically from the first contact region 405 to the first avalanche well 404. The vertical connection well 406 comprises a second doping type (e.g., n-type). In some embodiments, in a top view, the vertical connection well 406 is annular and extends laterally around the semiconductor layer 110.

[0043] The second avalanche well 412 is disposed within the substrate 102 between the semiconductor layer 110 and the first avalanche well 404. The second avalanche well 412 has a first doping type (e.g., p-type). The second contact region 202 is disposed within the passivation layer 112 and the semiconductor layer 110. The second contact region 202 has a first doping type (e.g., p-type). It should be understood that the second contact region 202 is shown in phantom lines for ease of illustration. The second contact region 202 extends continuously from the top surface of the passivation layer 112 to an upper region of the semiconductor layer 110. In some embodiments, the width of the second contact region 202 is narrower than the width of the semiconductor layer 110. Furthermore, the guard ring region 410 is disposed within the semiconductor layer 110. It should be understood that the guard ring region 410 is shown in phantom lines for ease of illustration. In some embodiments, the guard ring region 410 extends continuously from the top surface of the passivation layer 112, through the semiconductor layer 110 and the buffer layer 108, and to the bottom surface of the intermediate layer 106. In various embodiments, the guard ring region 410 is annular in top view. The guard ring region 410 comprises a first doping type (e.g., p-type).

[0044] The doped surface region 408 is disposed within the substrate 102 along the sidewalls and underside of the intermediate layer 106. The doped surface region 408 comprises a first doping type (e.g., p-type). In some embodiments, the thickness of the doped surface region 408 along the intermediate layer 106 is approximately 500 angstroms, approximately 450-550 angstroms, or another suitable value. In various embodiments, the doped surface region 408 comprises a doping concentration higher than the majority of the substrate 102, which can passivate crystalline defects along the surface of the substrate 102 that define the recess. In such embodiments, the crystalline defects are formed, for example, by an etching process (e.g., dry etching) used to form the recess in the substrate 102. By passivating the crystalline defects, the doped surface region 408 can further reduce the dark current of the photodetector 104. In some embodiments, the isolation structure 114 includes an upper isolation doped region 210 and a lower isolation doped region 212 disposed below the upper isolation doped region 210. The isolation structure 114 can be configured as shown and / or described in FIGS. 2A-2B.

[0045] In some embodiments, during operation of the IC, the first contact region 405 is configured as a cathode of the photodetector 104, and the second contact region 202 is configured as an anode of the photodetector 104. Electromagnetic radiation incident on the semiconductor layer 110 can generate electron-hole pairs within the semiconductor layer 110. The photodetector 104 can be reverse-biased via the plurality of conductive contacts and wires 216, 218. For example, the photodetector 104 can be reverse-biased above its breakdown voltage. As a result, a high electric field is generated across the photodetector 104, causing emitted charge carriers (e.g., electrons emitted from the generated electron-hole pairs) to migrate toward and accelerate in the avalanche region between the first and second avalanche wells 404, 412. This triggers an avalanche current, increasing the electrical signal generated by the incident electromagnetic radiation and enabling improved detection of the incident electromagnetic radiation. The buffer layer 108, which includes a compound of a first material (e.g., silicon) and a second material (e.g., germanium), can reduce defects (e.g., dislocation defects) at the interface between the semiconductor layer 110 and the substrate 102. In some embodiments, the second avalanche well 412 is disposed between the semiconductor layer 110 and the first avalanche well 404, thereby reducing the leakage current of the photodetector 104. Thus, the buffer layer 108, which includes a compound of the first material and the second material and is spaced apart between the substrate 102 and the semiconductor layer 110, can reduce the leakage current and improve the performance of the photodetector 104 (e.g., improve QE, SNR, etc.).

[0046] In various embodiments, the doped surface region 408 is laterally offset and continuously covers a central region of the semiconductor layer 110. This can, to some extent, facilitate the induction of charge carries from the semiconductor layer 110 to the first and second avalanche wells 404, 412. In further embodiments, the guard ring region 410 is annular in top view (e.g., as shown in FIG. 4B ), which can help more uniformly redistribute the electric field within the photodetector 104. Additionally, the guard ring region 410 can separate the central region of the semiconductor layer 110 from outer regions of the semiconductor layer 110. As a result, premature breakdown of the photodetector 104 can be mitigated, leakage current can be further reduced, and the stability and performance of the photodetector 104 can be improved.

[0047] In some embodiments, the bottom well 402, the doped surface region 408, the majority of the substrate 102, the second contact region 202, the guard ring region 410, and the second avalanche well 412 include a first dopant (e.g., boron, aluminum, gallium, etc.) having a first doping type (e.g., p-type). In various embodiments, the doping concentration of the second contact region 202 is higher than the doping concentration of the guard ring region 410 and / or higher than the doping concentration of the second avalanche well 412. The doping concentration of the second contact region 202 may be, for example, about 1e17 to 1e18 atoms / cm. 3 The doping concentration of the guard ring region 410 may be, for example, about 1e16 to 1e17 atoms / cm 3 The doping concentration of the doped surface region 408 may be, for example, between about 1e18 and 2e19 atoms / cm. 3 or any other suitable value. The doping concentration of the second avalanche well 412 may be, for example, about 3.5e17 atoms / cm 3 , about 1e17~1e18 atoms / cm 3 or any other suitable value.

[0048] In some embodiments, the first contact region 405, the vertical connection well 406, and the first avalanche well 404 include a second dopant (e.g., arsenic, antimony, phosphorous, etc.) having a second doping type (e.g., n-type). In some embodiments, the doping concentration of the first contact region 405 is higher than the doping concentration of the vertical connection well 406 and / or higher than the doping concentration of the first avalanche well 404. The doping concentration of the first contact region 405 may be, for example, about 1e18 to 1e19 atoms / cm. 3 The doping concentration of the first avalanche well 404 may be, for example, about 1e17 to 1e18 atoms / cm 3 The doping concentration of the vertical contact well 406 may be, for example, about 4e17 to 8e17 atoms / cm 3 or any other suitable value.

[0049] 4B , in some embodiments, the doped surface region 408 extends laterally continuously along the periphery of the intermediate layer 106. The first contact region 405 extends laterally continuously along the periphery of the intermediate layer 106 and is laterally spaced apart from the intermediate layer 106. Additionally, the guard ring region 410 is annular and surrounds the periphery of the second contact region 202.

[0050] Figures 5A-5B show a cross-sectional view 500a and a top view 500b corresponding to another embodiment of the IC of Figures 4A-4B. The cross-sectional view 500a of Figure 5A can be taken, for example, along line A-A' in Figure 5B, and the top view 500b of Figure 5B can be taken, for example, along line A-A' in Figure 5A.

[0051] In some embodiments, the isolation structures 114 include a dielectric material disposed in a trench that extends to the top surface 102t of the substrate 102. The dielectric material of the isolation structures 114 may be or include, for example, silicon dioxide, silicon oxynitride, silicon nitride, silicon carbide, other dielectric materials, or any combination thereof. In various embodiments, the bottom surfaces of the isolation structures 114 are aligned with the bottom surfaces of the vertical contact wells 406 and / or the second avalanche well 412.

[0052] FIG. 6A shows a cross-sectional view 600a of an IC according to another embodiment of the IC of FIG.

[0053] In some embodiments, the top surface of the intermediate layer 106 is vertically offset from the top surface 102t of the substrate 102 by a vertical distance 602. The vertical distance 602 may be, for example, within a range of approximately 40-50 nm or any other suitable value. In various embodiments, the vertical distance 602 is equal to the thickness 128 of the passivation layer 112. In various embodiments, the top segment 604 of the substrate 102 extends continuously from the top surface of the intermediate layer 106 to the outer sidewalls of the passivation layer 112. In some embodiments, this further improves the ability of the passivation layer 112 to be properly grown and / or formed on the semiconductor layer 110 and reduces damage to the buffer layer 108 and / or the semiconductor layer 110 during IC fabrication. In further embodiments, the top surface of the intermediate layer 106 is vertically aligned with the top surfaces of the semiconductor layer 110 and the buffer layer 108. In some embodiments, the outer sidewalls of the passivation layer 112 are aligned with the outer sidewalls of the buffer layer 108. Additionally, a plurality of conductive contacts 216 and a plurality of conductive wires 218 are disposed within the dielectric structure 116 and coupled to the first and second doped regions 118, 120.

[0054] FIG. 6B shows a cross-sectional view 600b corresponding to another embodiment of the IC of FIG. 6A, in which the outer sidewalls of the passivation layer 112 are aligned with the outer sidewalls of the semiconductor layer 110.

[0055] 7A-7B show a cross-sectional view 700a and a top view 700b of an IC according to another embodiment of the IC of FIGS. 2A-2B, in which buffer layer 108 includes multiple buffer films 702-706.

[0056] 7A , in some embodiments, the buffer layer 108 includes a first buffer film 702, a second buffer film 704, and a third buffer film 706. The first buffer film 702 is disposed between the intermediate layer 106 and the second buffer film 704. The second buffer film 704 is disposed between the first buffer film 702 and the third buffer film 706. The third buffer film 706 is disposed between the second buffer film 704 and the semiconductor layer 110. In various embodiments, the top surfaces of the first, second, and third buffer films 702, 704, 706 are coplanar with each other and / or with the top surface of the semiconductor layer 110.

[0057] The substrate 102 includes a first material, and the semiconductor layer 110 includes a second material different from the first material. The buffer films 702-706 include a compound of the first material (e.g., silicon) and a second material (e.g., germanium), with the first and second materials having different concentrations. In some embodiments, the concentration of the first material decreases discretely throughout the buffer layer 108 from the first buffer film 702 to the third buffer film 706, and the concentration of the second material increases discretely throughout the buffer layer 108 from the first buffer film 702 to the third buffer film 706. For example, the concentration of the first material in the first buffer film 702 is higher than the concentration of the first material in the second buffer film 704, which is higher than the concentration of the first material in the third buffer film 706. Furthermore, the concentration of the second material in the first buffer film 702 is lower than the concentration of the second material in the second buffer film 704, which in turn is lower than the concentration of the second material in the third buffer film 706. This variation in the concentrations of the first and second materials throughout the plurality of buffer films 702-706 facilitates growing the buffer layer 108 with high crystalline quality and can better match the second lattice constant of the semiconductor layer 110, thereby reducing leakage current in the photodetector 104. In some embodiments, the first buffer film 702 is Si 0.75 Ge 0.25 The second buffer film 704 contains Si 0.50 Ge 0.50 and the third buffer film 706 contains Si 0.25 Ge 0.75 However, it should be understood that multiple buffer films 702-706 including other concentrations of the first and second materials are within the scope of the present invention.

[0058] In various embodiments, the lattice constant of the first buffer film 702 is larger than the first lattice constant of the substrate 102, the lattice constant of the second buffer film 704 is larger than the lattice constant of the first buffer film 702, and the lattice constant of the third buffer film 706 is larger than the lattice constant of the second buffer film 704. Thus, the lattice constant of the buffer layer 108 increases discretely by at least a factor of two from the first buffer film 702 to the third buffer film 706. This reduces strain throughout the buffer layer 108 and improves the structural integrity of the buffer layer 108. In various embodiments, the lattice constant of the intermediate layer 106 is equal to the first lattice constant of the substrate 102. In some embodiments, the second lattice constant of the semiconductor layer 110 is larger than the lattice constant of the third buffer film 706.

[0059] In various embodiments, the thicknesses of the first, second, and third buffer films 702-706 are each within a range of 10 nm to 30 nm, or other suitable values. In various embodiments, the thickness of the first buffer film 702 is less than the thickness of the second buffer film 704, which is less than the thickness of the third buffer film 706. This facilitates, to some extent, the buffer layer 108 to further reduce defects between the semiconductor layer 110 and the substrate 102, thereby further reducing leakage current in the photodetector 104. In various embodiments, the thickness of the second buffer film 704 is at least 10% greater than the thickness of the first buffer film 702, and the thickness of the third buffer film 706 is at least 10% greater than the thickness of the second buffer film 704. Thus, the thicknesses of the multiple buffer films 702-706 increase discretely from the first buffer film 702 to the third buffer film 706. Although Figure 7A illustrates another embodiment of the IC of Figure 2A, it should be understood that the buffer layer 108 of any of Figures 3A-3B, 4A-4B, and / or 5A-5B may be configured as shown and / or described in Figure 7A.

[0060] 7B, the intermediate layer 106 continuously covers the periphery of the first buffer film 702. The first buffer film 702 continuously covers the periphery of the second buffer film 704. The second buffer film 704 continuously covers the periphery of the third buffer film 706.

[0061] FIG. 7C illustrates a cross-sectional view 700c of some other embodiments of the IC of FIG. 6A, in which buffer layer 108 includes multiple buffer films 702-706, as shown and / or described in FIG. 7A.

[0062] FIG. 7D shows a cross-sectional view 700d of some other embodiments of the IC of FIGS. 4A and 4B, in which the semiconductor layer 110 is disposed on the top surface 102t of the substrate 102.

[0063] In some embodiments, the substrate 102 includes a base substrate 710 and an upper substrate layer 712 disposed on the base substrate 710. The base substrate 710 may be or include, for example, silicon, monocrystalline silicon, other semiconductor materials, or any combination thereof. The upper substrate layer 712 may be or include, for example, silicon, epitaxial silicon, other semiconductor materials, or any combination thereof. In some embodiments, the thickness of the upper substrate layer 712 is less than the thickness of the base substrate 710. In various embodiments, the base substrate 710 and the upper substrate layer 712 both include a first material (e.g., silicon). The base substrate 710 and / or the upper substrate layer 712 may have a first doping type (e.g., p-type).

[0064] In various embodiments, the photodetector 104 includes a semiconductor layer 110, a first avalanche well 404, a second avalanche well 412, an avalanche well extension region 714, a vertical connection well 406, a first contact region 405, and a second contact region 202. The semiconductor layer 110 is disposed over a substrate 102. The first avalanche well 404 is disposed in a base substrate 710. In some embodiments, the first avalanche well 404 extends continuously along the top surface of the base substrate 710. The avalanche well extension region 714 is disposed in an upper substrate layer 712 along the top of the first avalanche well 404. The avalanche well extension region 714 is aligned with a central region of the first avalanche well 404. The second avalanche well 412 has a vertical connection well 406 disposed in the upper substrate layer 712 above the avalanche well extension region 714. The vertical connection well 406 is disposed in the upper substrate layer 712 and extends from the first contact region 405 to the first avalanche well 404. In various embodiments, the vertical connection well 406 and the first contact region 405 are each annular in top view (e.g., as shown and / or described in FIG. 4B ). The avalanche well extension region 714 has a second doping type (e.g., n-type). In various embodiments, the width of the avalanche well extension region 714 is narrower than the width of the second avalanche well 412, and the avalanche well extension region 714 is configured to enhance and / or better confine emitted charge carriers in the avalanche region between the first avalanche well 404 and the second avalanche well 412.

[0065] The semiconductor layer 110 is disposed above a top surface 102t of the substrate 102. The top surface 102t of the substrate 102 may be defined by the top surface of the upper substrate layer 712. In various embodiments, the bottom surface of the semiconductor layer 110 is vertically offset a non-zero distance from the top surface 102t of the substrate 102. The buffer layer 108 is disposed between the top surface 102t of the substrate 102 and the semiconductor layer 110. In some embodiments, the outer sidewalls of the buffer layer 108 are aligned with the outer sidewalls of the semiconductor layer 110. In various embodiments, the passivation layer 112 is in direct contact with the top surface 110t and the outer sidewalls of the semiconductor layer 110. Furthermore, the passivation layer 112 is in direct contact with the outer sidewalls of the buffer layer 108. In some embodiments, the bottom surface of the passivation layer 112 is aligned with the bottom surface of the buffer layer 108. The passivation layer 112 continuously covers and contacts the periphery of the semiconductor layer 110. The passivation layer 112 is disposed on the top surface 110t and outer sidewalls of the semiconductor layer 110 and on the outer sidewalls of the buffer layer 108, thereby reducing damage to the buffer layer 108 and / or the semiconductor layer 110. In various embodiments, the second contact region 202 is disposed within the semiconductor layer 110 and may extend into the passivation layer 112.

[0066] The etch stop layer 718 extends along opposing sidewalls and a top surface of the passivation layer 112, which is disposed over the substrate 102. The etch stop layer 718 may be or include, for example, silicon nitride, silicon carbide, other dielectric materials, or any combination thereof. The dielectric structure 116 is disposed over and laterally surrounds the semiconductor layer 110. In some embodiments, the bottom surface of the conductive contact 216 disposed on the first contact region 405 is disposed below the bottom surface of the semiconductor layer 110 and / or is aligned with the bottom surface of the buffer layer 108.

[0067] The upper substrate layer 712 includes a first material (e.g., silicon), and the semiconductor layer 110 includes a second material (e.g., germanium). Because the buffer layer 108 includes a compound of the first and second materials, the lattice constant of the buffer layer 108 is well-matched to the lattice constant of the semiconductor layer 110. Therefore, the buffer layer 108 provides a good structural foundation for forming or growing the semiconductor layer 110 with high crystalline quality. Furthermore, disposing the semiconductor layer 110 on the top surface 102t of the substrate 102 can reduce defects, for example, between the outer sidewalls of the semiconductor layer 110 and the substrate 102. In addition, the semiconductor layer 110 disposed on the top surface 102t can reduce leakage current in the outer regions of the semiconductor layer 110 and enhance optical and / or electrical isolation between the photodetector 104 and other photodetectors (not shown) on and / or within the substrate 102, thereby improving the performance of the photodetector 104.

[0068] 7E shows a cross-sectional view 700e of some other embodiments of the IC of FIG. 7D , in which isolation structures 114 are disposed in the substrate 102 on opposite sides of the first avalanche well 404 and upper doped surface regions 720 are disposed in the upper substrate layer 712. In various embodiments, the isolation structures 114 extend continuously from the top surface 102t to the base substrate 710. The upper doped surface regions 720 have a first doping type (e.g., p-type) and a higher doping concentration than the majority of the substrate 102. Furthermore, the upper doped surface regions 720 are laterally offset and continuously cover a central region and laterally aligned regions of the semiconductor layer 110. This facilitates the induction of charge carriers from the semiconductor layer 110 to the first and second avalanche wells 404, 412.

[0069] FIG. 7F illustrates a cross-sectional view 700f of some other embodiments of the IC of FIG. 7D, where the buffer layer 108 includes multiple buffer films 702-706 as shown and / or described in FIG. 7A.

[0070] 8A-8B through 21A-21B show a series of various views of several embodiments of methods for forming an integrated chip (IC) with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. The views suffixed with "A" show cross-sectional views of the IC during various formation processes. The views suffixed with "B" show top views cut along line A-A' in the views suffixed with "A."

[0071] While the various diagrams shown in Figures 8A-8B through 21A-21B are described with respect to a method of forming an IC, it should be understood that the structures shown in Figures 8A-8B through 21A-21B are not limited to the method of formation and may exist independently of the method. Furthermore, while Figures 8A-8B through 21A-21B are described as a series of operations, it should be understood that these operations are not limiting in that the order of operations may be changed in other embodiments, and that the disclosed methods are applicable to other structures. In other embodiments, some of the operations shown and / or described may be omitted in whole or in part.

[0072] As shown in cross-sectional views 800a and top views 800b of FIGS. 8A-8B, a substrate 102 is provided, and a bottom well 402 and a first avalanche well 404 are formed in the substrate 102. The substrate 102 includes a first material that may be doped with a first dopant having a first doping type (e.g., p-type). In some embodiments, the first material is or includes silicon, crystalline silicon, or other semiconductor material. In some embodiments, forming the bottom well 402 includes performing a first doping process to implant a first dopant (e.g., boron, aluminum, gallium, etc.) having the first doping type (e.g., p-type) into the substrate 102. The first doping process may include, for example, a blanket implantation process. In some embodiments, forming the first avalanche well 404 includes forming an implant mask 802 on the substrate 102; performing a second doping process to implant a second dopant (e.g., arsenic, antimony, phosphorus, etc.) having a second doping type (e.g., n-type) into the substrate 102 with the implant mask 802 in place; and removing the implant mask 802.

[0073] 9A-9B, a vertical contact well 406 is formed in the substrate 102. In some embodiments, forming the vertical contact well 406 includes forming an implant mask 902 on the substrate 102; performing a doping process with the implant mask 902 in place to implant a second dopant (e.g., arsenic, antimony, phosphorous, etc.) having a second doping type (e.g., n-type) into the substrate 102; and removing the implant mask 902.

[0074] 10A-10B, a bottom isolation doped region 212 is formed in the substrate 102. The bottom isolation doped region 212 extends continuously around the vertical connection well 406. In some embodiments, forming the bottom isolation doped region 212 includes forming an implant mask 1002 on the substrate 102; performing a doping process with the implant mask 1002 in place to implant a first dopant (e.g., boron, aluminum, gallium, etc.) having a first doping type (e.g., p-type) into the substrate 102; and removing the implant mask 1002.

[0075] 11A-11B, a first contact region 405 is formed in the substrate 102 over the vertical connection well 406. In some embodiments, forming the first contact region 405 includes forming an implant mask 1102 on the substrate 102; performing a doping process with the implant mask 1102 in place to implant a second dopant (e.g., arsenic, antimony, phosphorous, etc.) having a second doping type (e.g., n-type) into the substrate 102; and removing the implant mask 1102.

[0076] 12A-12B, an upper isolation doped region 210 is formed in the substrate 102 above the lower isolation doped region 212, thereby forming or defining the isolation structure 114. In some embodiments, forming the upper isolation doped region 210 includes forming an implant mask 1202 on the substrate 102; performing a doping process with the implant mask 1202 in place to implant a first dopant (e.g., boron, aluminum, gallium, etc.) having a first doping type (e.g., p-type) into the substrate 102; and removing the implant mask 1202.

[0077] As shown in cross-sectional views 1300a and top views 1300b of FIGS. 13A-13B, a patterning process is performed on substrate 102 to form recesses 1304 in substrate 102. Recesses 1304 are defined by opposing sidewalls 102s1, 102s2 and a bottom surface 102ls of substrate 102. In some embodiments, the patterning process includes forming a masking layer 1302 on substrate 102; performing an etching process on substrate 102 with masking layer 1302 in place; and removing masking layer 1302. In some embodiments, the etching process includes dry etching (e.g., reactive ion etching, plasma etching, etc.) or other suitable etching process.

[0078] 14A-14B, a second avalanche well 412 is formed in the substrate 102 above the first avalanche well 404. In some embodiments, forming the second avalanche well 412 includes forming an implant mask 1402 on the substrate 102; performing a doping process with the implant mask 1402 in place to implant a first dopant (e.g., boron, aluminum, gallium, etc.) having a first doping type (e.g., p-type) into the substrate 102; and removing the implant mask 1402.

[0079] As shown in cross-sectional view 1500a and top view 1500b in Figures 15A-15B, doped surface region 408 is formed in substrate 102. In some embodiments, forming doped surface region 408 includes forming an implant mask 1502 on substrate 102; performing a doping process with implant mask 1502 in place to implant a first dopant (e.g., boron, aluminum, gallium, etc.) having a first doping type (e.g., p-type) into substrate 102; and removing implant mask 1502.

[0080] As shown in cross-sectional view 1600a and top view 1600b of FIGS. 16A-16B, an intermediate layer 106 and a buffer layer 108 are formed in recess 1304. Intermediate layer 106 is formed along opposing sidewalls 102s1, 102s2 and bottom surface 102ls of substrate 102. Buffer layer 108 is formed on intermediate layer 106. In some embodiments, intermediate layer 106 comprises a first material (e.g., silicon) and is undoped. In some embodiments, buffer layer 108 comprises a compound of a first material (e.g., silicon) and a second material (e.g., germanium) different from the first material. In various embodiments, buffer layer 108 is undoped.

[0081] In some embodiments, the intermediate layer 106 is formed by a first epitaxial process that selectively grows the intermediate layer 106 along the surface of the substrate 102 that defines the recess 1304. The first epitaxial process may be or include, for example, molecular beam epitaxy (MBE), chemical vapor deposition (CVD), vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), or other suitable deposition or growth process. In some embodiments, the buffer layer 108 is formed by a second epitaxial process that selectively grows the buffer layer 108 along the surface of the intermediate layer 106 in the recess 1304. The second epitaxial process may be or include, for example, MBE, CVD, VPE, LPE, or other suitable deposition or growth process. In various embodiments, prior to forming the intermediate layer 106, a dielectric layer (not shown) and / or a masking layer (not shown) may be formed along the top surface 102t of the substrate 102 and laterally offset from the recess 1304. In such embodiments, the dielectric layer and / or masking layer facilitates selective formation of the intermediate layer 106 in the recess 1304 because the intermediate layer 106 preferentially grows on the semiconductor surface rather than the dielectric surface. Additionally, the dielectric layer and / or masking layer may be removed after forming the buffer layer 108.

[0082] In some embodiments, the second epitaxial process utilized to form the buffer layer 108 includes performing a CVD process using a first precursor gas (e.g., silane (SiH4)), a second precursor gas (e.g., germane (GeH4)), and / or a carrier gas (e.g., hydrogen (H2)). In such embodiments, the CVD process is performed at a temperature range of approximately 300-700°C and a pressure range of approximately 5-60 Torr. In various embodiments, during the second epitaxial process, a first flow rate of the first precursor gas (e.g., silane (SiH4)) may be decreased over the duration of the second epitaxial process, and a second flow rate of the second precursor gas (e.g., germane (GeH4)) may be continuously increased over the duration of the second epitaxial process. In such embodiments, at the start of the epitaxial process, a first initial flow rate of a first precursor gas (e.g., silane (SiH4)) is greater than a second initial flow rate of a second precursor gas (e.g., germane (GeH4)). As a result, in some embodiments, a first concentration of a first material (e.g., silicon) in the buffer layer 108 may decrease continuously in a first direction from the bottom surface of the buffer layer 108 away from the lower surface 1021 of the substrate, and a second concentration of a second material (e.g., germanium) in the buffer layer 108 may increase continuously in the first direction from the bottom surface of the buffer layer 108.

[0083] 17A-17B illustrate an alternative embodiment of a process that can be performed in place of the process illustrated in cross-sectional view 1600a and top view 1600b of FIGS. 16A-16B, in which a first buffer film 702, a second buffer film 704, and a third buffer film 706 are vertically stacked to form a buffer layer 108. The intermediate layer 106 is formed along opposing sidewalls 102s1, 102s2, and a bottom surface 102ls of the substrate 102. The buffer layer 108 is formed on the intermediate layer 106 by forming a first buffer film 702 on the intermediate layer 106; forming a second buffer film 704 on the first buffer film 702; and forming a third buffer film 706 on the second buffer film 704.

[0084] In some embodiments, the intermediate layer 106 is formed by a first epitaxial process that selectively grows the intermediate layer 106 along the surface of the substrate 102 that defines the recess 1304. In some embodiments, forming the buffer layer 108 includes performing a second epitaxial process to form a first buffer film 702 on the intermediate layer 106; performing a third epitaxial process to form a second buffer film 704 on the first buffer film 702; and performing a fourth epitaxial process to form a third buffer film 706 on the second buffer film 704. In various embodiments, the first, second, third, and fourth epitaxial processes are each separate epitaxial processes that are or include MBE, CVD, VPE, LPE, or other suitable deposition or growth processes.

[0085] In some embodiments, the second, third, and fourth epitaxial processes may each include performing a CVD process on the intermediate layer 106 using a first precursor gas (e.g., silane (SiH)), a second precursor gas (e.g., germane (GeH)), and / or a carrier gas (e.g., hydrogen (H)) at a temperature range of about 300-700°C and a pressure range of about 5-60 Torr. In various embodiments, the flow rates of the first precursor gas and the second precursor gas during the second, third, and fourth epitaxial processes are different from one another. As a result, the first, second, and third buffer films 702, 704, and 706 each have different concentrations of the first material (e.g., silicon) and the second material (e.g., germanium). For example, a first flow rate of a first precursor gas (e.g., silane (SiH4)) during the second epitaxial process is greater than a second flow rate of the first precursor gas (e.g., silane (SiH4)) during the third epitaxial process, and the second flow rate of the first precursor gas (e.g., silane (SiH4)) during the second epitaxial process is greater than a third flow rate of the first precursor gas (e.g., silane (SiH4)) during the third epitaxial process. In some embodiments, a fourth flow rate of the second precursor gas (e.g., germane (GeH4)) during the second epitaxial process is less than a fifth flow rate of the second precursor gas (e.g., germane (GeH4)) during the third epitaxial process, and the fifth flow rate of the second precursor gas (e.g., germane (GeH4)) during the second epitaxial process is less than a sixth flow rate of the second precursor gas (e.g., germane (GeH4)) during the third epitaxial process. As a result of the different flow rates of the first and second precursor gases during the second, third, and fourth epitaxial processes, the concentrations of the first and second materials in the first, second, and third buffer films 702, 704, 706 are different from one another. For example, in some embodiments, the first buffer film 702 is made of Si 0.75 Ge 0.25 The second buffer film 704 contains Si 0.50 Ge 0.50 and the third buffer film 706 contains Si 0.25 Ge0.75 However, it should be understood that multiple buffer films 702-706 including other concentrations of the first and second materials are within the scope of the present invention.

[0086] As shown in cross-sectional views 1800a and top views 1800b of Figures 18A-18B, semiconductor layer 110 is formed on buffer layer 108, filling the recess (1304 in Figures 16A-16B). In some embodiments, the method of Figures 8A-8B through Figures 21A-21B can proceed from Figures 8A-8B through Figures 16A-16B to Figures 18A-18B to Figures 21A-21B, or from Figures 8A-8B through Figures 16A-16B to Figures 17A-17B to Figures 21A-21B.

[0087] In some embodiments, forming the semiconductor layer 110 includes performing an epitaxial process to form the semiconductor layer 110 on the buffer layer 108 and performing a planarization process on the semiconductor layer 110. In some embodiments, the epitaxial process is or includes MBE, CVD, VPE, LPE, or other suitable deposition or growth process. In various embodiments, the planarization process is a chemical mechanical planarization (CMP) process or other suitable planarization process. The semiconductor layer 110 includes a second material (e.g., germanium) different from the first material of the substrate 102. Furthermore, the semiconductor layer 110 may be doped with a first doping type (e.g., p-type). In some embodiments, the first contact region 405, the vertical contact well 406, the first and second avalanche wells 404, 412, and the semiconductor layer 110 at least partially form the photodetector 104.

[0088] In some embodiments, the epitaxial process utilized to form the semiconductor layer 110 includes performing a CVD process using a precursor gas (e.g., germane (GeH4)) and / or a carrier gas (e.g., hydrogen (H2)) at a temperature range of approximately 300-700°C and a pressure range of approximately 5-60 Torr. In various embodiments, the epitaxial process may further include flowing a dopant precursor gas (e.g., diborane (B2H4)) to in-situ dope the semiconductor layer 110 with a first doping type (e.g., p-type). In various embodiments, forming the semiconductor layer on the buffer layer 108 can reduce defects between the substrate 102 and the semiconductor layer 110 and improve the crystalline quality of the semiconductor layer 110, thereby improving the performance of the photodetector 104.

[0089] 19A-19B, a passivation layer 112 is formed on the semiconductor layer 110 and the buffer layer 108. In some embodiments, forming the passivation layer 112 includes performing an etching process (e.g., dry etching and / or wet etching) on ​​the buffer layer 108 and the semiconductor layer 110 to recess top surfaces of the buffer layer 108 and the semiconductor layer 110 below the top surface 102t of the substrate; performing an epitaxial process (e.g., MBE, CVD, VPE, LPE, etc.) to form the passivation layer 112 on the substrate 102, the buffer layer 108, and the semiconductor layer 110; and performing a planarization process (e.g., CMP process) on the passivation layer 112.

[0090] As shown in cross-sectional view 2000a and top view 2000b of FIGS. 20A-20B, guard ring region 410 and second contact region 202 are formed in passivation layer 112 and semiconductor layer 110. In some embodiments, guard ring region 410 is formed before second contact region 202. It should be understood that in cross-sectional view 2000a of FIG. 20A, second contact region 202 and guard ring region 410 are shown in phantom lines for ease of illustration. In various embodiments, second contact region 202 extends continuously from the top surface of passivation layer 112 to semiconductor layer 110. In some embodiments, guard ring region 410 extends continuously from the top surface of passivation layer 112, through semiconductor layer 110 and buffer layer 108, and to the bottom surface of intermediate layer 106.

[0091] In some embodiments, forming the guard ring region 410 includes forming a first implant mask (not shown) on the substrate 102; performing a first doping process to implant a first dopant (e.g., boron, aluminum, gallium, etc.) having a first doping type (e.g., p-type) into the semiconductor layer 110 with the first implant mask in place; and removing the first implant mask. In various embodiments, forming the second contact region 202 includes forming a second implant mask (not shown) on the substrate 102; performing a doping process to implant a first dopant (e.g., boron, aluminum, gallium, etc.) having a first doping type (e.g., p-type) into the semiconductor layer 110 with the second implant mask in place; and removing the second implant mask. In some embodiments, the doping concentration of the second contact region 202 is higher than the doping concentration of the guard ring region 410.

[0092] 21A-21B, a dielectric structure 116, a plurality of conductive contacts 216, and a plurality of conductive wires 218 are formed on a substrate 102. The plurality of conductive contacts 216 are formed in the dielectric structure 116. The plurality of conductive wires 218 are formed in the dielectric structure 116 on the plurality of conductive contacts 216.

[0093] FIG. 22 illustrates a flow diagram of some embodiments of a method 2200 for forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. While method 2200 is illustrated and / or described as a series of acts or events, it should be understood that method 2200 is not limited to the illustrated order or acts. Thus, in some embodiments, acts may be performed in an order different from that illustrated and / or may be performed simultaneously. Furthermore, in some embodiments, an illustrated act or event may be subdivided into multiple acts or events, which may be performed separately or simultaneously with other acts or sub-acts. In some embodiments, some of the illustrated acts or events may be omitted, and other acts or events not illustrated may be included.

[0094] In operation 2202, a substrate including a first material is provided. Figures 8A-8B show various views corresponding to some embodiments of operation 2202.

[0095] A first avalanche well is formed in the substrate in operation 2204. Figures 8A-8B show various views corresponding to some embodiments of operation 2204.

[0096] In operation 2206, a vertical contact well and a first contact region are formed in the substrate and on opposite sides of the first avalanche well. Figures 9A-9B and 11A-11B show various views corresponding to some embodiments of operation 2206.

[0097] In operation 2208, a substrate is patterned to form a recess in the substrate and over the first avalanche well. Figures 13A-13B show various views corresponding to some embodiments of operation 2208.

[0098] A second avalanche well is formed in the substrate above the first avalanche well and below the recess in operation 2210. Figures 14A-14B show various views corresponding to some embodiments of operation 2210.

[0099] In Operation 2212, an intermediate layer is formed on a surface of the substrate defining the recess, the intermediate layer comprising a first material. Figures 16A-16B show various views corresponding to some embodiments of Operation 2212. Additionally, Figures 17A-17B show various views corresponding to some other embodiments of Operation 2212.

[0100] In operation 2214, a buffer layer is formed on the intermediate layer. The buffer layer includes a compound of a first material and a second material different from the first material. Figures 16A-16B show various views corresponding to some embodiments of operation 2214. Additionally, Figures 17A-17B show various views corresponding to some other embodiments of operation 2214.

[0101] In operation 2216, a semiconductor layer is formed over the buffer layer, filling the remainder of the recess. The semiconductor layer comprises a second material. Figures 18A-18B show various views corresponding to some embodiments of operation 2216.

[0102] In operation 2218, a passivation layer is formed over the buffer layer and the semiconductor layer. The passivation layer includes a first material. Figures 19A-19B show various views corresponding to some embodiments of operation 2218.

[0103] Second contact regions and guard ring regions are formed in the semiconductor layer in operation 2220. Figures 20A-20B show various views corresponding to several embodiments of operation 2220.

[0104] In operation 2222, a plurality of conductive contacts and a plurality of conductive wires are formed on the substrate and coupled to the first and second contact regions. Figures 21A-21B show various views corresponding to some embodiments of operation 2222.

[0105] Figures 23-29 illustrate a series of cross-sectional views 2300-2900 of several other embodiments of methods for forming an integrated chip (IC) with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. While cross-sectional views 2300-2900 shown in Figures 23-29 are described with respect to methods for forming an IC, it should be understood that the structures shown in Figures 23-29 are not limited to the methods and may exist independently of the methods. Furthermore, while Figures 23-29 are described as a series of operations, it should be understood that these operations are not limiting in that the order of operations may be changed in other embodiments, and that the disclosed methods are applicable to other structures. In other embodiments, some of the operations shown and / or described may be omitted in whole or in part.

[0106] As shown in cross-sectional view 2300 of FIG. 23 , isolation structures 114 are formed in substrate 102. In some embodiments, substrate 102 includes a first material (e.g., silicon) and has a first doping type (e.g., p-type). In some embodiments, forming isolation structures 114 includes forming a masking layer (not shown) on top surface 102t of substrate 102; etching substrate 102 with the masking layer in place to form one or more trenches extending into substrate 102; depositing (e.g., by CVD, physical vapor deposition (PVD), atomic layer deposition (ALD)) an isolation material (e.g., one or more dielectric materials such as silicon dioxide, silicon nitride, silicon carbide, etc.) in the one or more trenches; and performing a planarization process (e.g., a CMP process) on the isolation material. In various embodiments, the masking layer may be removed before or after depositing the isolation material in the one or more trenches.

[0107] As shown in cross-sectional view 2400 of Figure 24, recess 2402 is formed in substrate 102. Recess 2402 can be formed, for example, by the operations shown and / or described in Figures 13A-13B.

[0108] As shown in cross-sectional view 2500 of Figure 25, intermediate layer 106 and buffer layer 108 are formed over recess 2402. In some embodiments, intermediate layer 106 and buffer layer 108 can be formed by the operations shown and / or described in Figures 16A-16B, for example. In other embodiments, intermediate layer 106 and buffer layer 108 can be formed by the operations shown and / or described in Figures 17A-17B, for example. In various embodiments, buffer layer 108 includes a compound of a first material and a second material, and intermediate layer 106 includes the first material.

[0109] As shown in cross-sectional view 2600 of Figure 26, a semiconductor layer 110 is formed in the recess (2402 in Figure 25) on the buffer layer 108. The semiconductor layer 110 includes a second material. The semiconductor layer 110 can be formed, for example, by the operations shown and / or described in Figures 18A-18B.

[0110] 27, a passivation layer 112 is formed on the buffer layer 108 and the semiconductor layer 110. The passivation layer 112 can be formed, for example, by the process shown and / or described in Figures 19A-19B.

[0111] 28 , a first doped region 118 and a second doped region 120 are formed in the passivation layer 112 and the semiconductor layer 110. In some embodiments, forming the first doped region 118 includes forming a first implantation mask (not shown) on the substrate 102; performing a first doping process with the first implantation mask in place to implant a first dopant (e.g., boron, aluminum, gallium, etc.) having a first doping type (e.g., p-type) into the semiconductor layer 110; and removing the first implantation mask. In some embodiments, forming the second doped region 120 includes forming a second implant mask on the substrate 102; performing a second doping process with the second implant mask in place to implant a second dopant (e.g., arsenic, antimony, phosphorus, etc.) having a second doping type (e.g., n-type) into the semiconductor layer 110; and removing the second implant mask.

[0112] 29, a dielectric structure 116, a plurality of conductive contacts 216, and a plurality of conductive wires 218 are formed on a substrate 102. The plurality of conductive contacts 216 are formed in the dielectric structure 116. The plurality of conductive wires 218 are formed in the dielectric structure 116 on the plurality of conductive contacts 216.

[0113] 30-42 illustrate a series of cross-sectional views 3000-4200 of several other embodiments of methods for forming an integrated chip (IC) with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. While the cross-sectional views 3000-4200 illustrated in FIGS. 30-42 are described with respect to a method for forming an IC, it should be understood that the structures illustrated in FIGS. 30-42 are not limited to the method and may exist independently of the method. Furthermore, while FIGS. 30-42 are described as a series of operations, it should be understood that these operations are not limiting in that the order of operations may be changed in other embodiments, and that the disclosed methods are applicable to other structures. In other embodiments, some of the operations illustrated and / or described may be omitted in whole or in part.

[0114] As shown in cross-sectional view 3000 of Figure 30, a base substrate 710 of substrate 102 is provided. Base substrate 710 may be or include, for example, silicon, single crystal silicon, a silicon-on-insulator (SOI) substrate, or other suitable semiconductor substrate material. In various embodiments, base substrate 710 has a first doping type (e.g., p-type).

[0115] 31 , a first avalanche well 404 is formed in a base wafer 710. In some embodiments, forming the first avalanche well 404 includes forming an implant mask 3102 on the base wafer 710; performing a doping process with the implant mask 3102 in place to implant a second dopant (e.g., arsenic, antimony, phosphorous, etc.) having a second doping type (e.g., n-type) into the base wafer 710; and removing the implant mask 3102. In some embodiments, a doping concentration of the first avalanche well 404 is about 1e17 to 1e18 atoms / cm. 3 or any other suitable value.

[0116] As shown in cross-sectional view 3200 of Figure 32, an upper substrate layer 712 of substrate 102 is formed on a base substrate 710. The upper substrate layer 712 may be formed by, for example, MBE, CVD, VPE, LPE, or any other suitable deposition or growth process. The upper substrate layer 712 includes a first material (e.g., silicon). In some embodiments, the upper substrate layer 712 has a first doping type (e.g., p-type).

[0117] 33, a vertical connection well 406 and a first contact region 405 are formed in the substrate 102. In some embodiments, forming the vertical connection well 406 and the first contact region 405 includes forming an implant mask 3302 on the substrate 102; performing a first doping process with the implant mask 3302 in place to implant a second dopant (e.g., arsenic, antimony, phosphorous, etc.) having a second doping type (e.g., n-type) into the upper substrate layer 712, thereby defining or forming the vertical connection well 406; performing a second doping process with the implant mask 3302 in place to implant a second dopant (e.g., arsenic, antimony, phosphorous, etc.) having a second doping type (e.g., n-type) into the upper substrate layer 712, thereby defining or forming the first contact region 405; and removing the implant mask 3302. In some embodiments, the doping concentration of the first contact region 405 is higher than the doping concentration of the vertical contact well 406. The doping concentration of the first contact region 405 is, for example, about 1e19 to 1e20 atoms / cm 3 or any other suitable value. The doping concentration of the vertical contact well 406 is, for example, about 1e16 to 1e17 atoms / cm 3 or any other suitable value.

[0118] 34, an avalanche well extension region 714 is formed in the substrate 102. In some embodiments, forming the avalanche well extension region 714 includes forming an implant mask 3402 on the substrate 102; performing a doping process with the implant mask 3402 in place to implant a second dopant (e.g., arsenic, antimony, phosphorous, etc.) having a second doping type (e.g., n-type) into the substrate 102; and removing the implant mask 3402. The doping concentration of the avalanche well extension region 714 may be, for example, about 1e17 to 1e18 atoms / cm. 3 In some embodiments, the doping concentration of the avalanche well extension region 714 is equal to the doping concentration of the first avalanche well 404.

[0119] 35, a second avalanche well 412 is formed in the substrate 102. In some embodiments, forming the second avalanche well 412 includes forming an implant mask 3502 on the substrate 102; performing a doping process with the implant mask 3502 in place to implant a first dopant (e.g., boron, aluminum, gallium, etc.) having a first doping type (e.g., p-type) into the upper substrate layer 712; and removing the implant mask 3502. The doping concentration of the second avalanche well 412 may be, for example, about 1e16 to 1e17 atoms / cm. 3 or any other suitable value. In some embodiments, the doping concentration of the second avalanche well 412 is lower than the doping concentration of the avalanche well extension region 714.

[0120] 36, an upper doped surface region 720 is formed in the substrate 102. In some embodiments, forming the upper doped surface region 720 includes forming an implant mask 3602 on the substrate 102; performing a doping process with the implant mask 3602 in place to implant a first dopant (e.g., boron, aluminum, gallium, etc.) having a first doping type (e.g., p-type) into the substrate 102; and removing the implant mask 3602. The doping concentration of the upper doped surface region 720 may be, for example, about 1e15 to 1e17 atoms / cm. 3 or any other suitable value.

[0121] 37, isolation structures 114 are formed in the substrate 102 on opposite sides of the first avalanche well 404. In some embodiments, the isolation structures 114 are formed as shown and / or described in FIGS.

[0122] As shown in cross-sectional view 3800 of FIG. 38 , a buffer layer 108 and a semiconductor layer 110 are formed on the top surface 102t of the substrate 102. In some embodiments, the buffer layer 108 includes a compound of a first material (e.g., silicon) and a second material (e.g., germanium) different from the first material. In various embodiments, the buffer layer 108 is undoped. The buffer layer 108 can be deposited on the substrate 102 by an epitaxial process, such as MBE, CVD, VPE, LPE, or other suitable deposition or growth process. In various embodiments, the epitaxial process used to form the buffer layer 108 can be configured as the second epitaxial process described in FIGS. 16A-16B . In other embodiments, the buffer layer 108 can be formed as shown and / or described in FIGS. 17A-17B . The semiconductor layer 110 is formed on the buffer layer 108. In some embodiments, the semiconductor layer 110 is deposited by, for example, MBE, CVD, VPE, LPE, or other suitable deposition or growth process. The semiconductor layer 110 includes a second material (eg, germanium).

[0123] 39, a patterning process is performed on the buffer layer 108 and the semiconductor layer 110. In some embodiments, the patterning process includes forming a masking layer 3902 on the semiconductor layer 110; performing an etching process (e.g., plasma etching, reactive ion etching, etc.) on the buffer layer 108 and the semiconductor layer 110; and removing the masking layer 3902.

[0124] 40 , a passivation layer 112 is formed on the semiconductor layer 110 and the buffer layer 108. In some embodiments, forming the passivation layer 112 includes depositing or growing the passivation layer 112 (e.g., by MBE, CVD, VPE, LPE, etc.) on the substrate 102 and the semiconductor layer 110; and performing an etching process (e.g., plasma etching, reactive ion etching, or other suitable etching) on ​​the passivation layer 112 to remove portions of the passivation layer 112 in areas of the substrate 102 that are offset from the semiconductor layer 110. In various embodiments, the passivation layer 112 is in direct contact with a top surface and outer sidewalls of the semiconductor layer 110 and the outer sidewalls of the buffer layer 108. In some embodiments, the bottom surface of the passivation layer 112 is aligned with the bottom surface of the buffer layer 108.

[0125] 40 , a second contact region 202 is formed in the semiconductor layer 110 and / or the passivation layer 112. In some embodiments, forming the second contact region 202 includes forming an implantation mask (not shown) on the substrate 102; performing a doping process to implant a first dopant (e.g., boron, aluminum, gallium, etc.) having a first doping type (e.g., p-type) into the semiconductor layer 110 and / or the passivation layer 112; and removing the implantation mask. It should be understood that in the cross-sectional view 4000 of FIG. 40 , the second contact region 202 is shown in phantom for ease of illustration. In some embodiments, the first contact region 405, the vertical connection well 406, the first and second avalanche wells 404, 412, the avalanche well extension region 714, and the semiconductor layer 110 at least partially form the photodetector 104.

[0126] As shown in cross-sectional view 4100 of FIG. 41 , an etch stop layer 718 is formed on the substrate 102. In some embodiments, the etch stop layer 718 is formed on the substrate 102 by, for example, a PVD process, a CVD process, an ALD process, or other suitable growth or deposition process. In various embodiments, the etch stop layer 718 is formed to a thickness that is less than a thickness of the passivation layer 112. Furthermore, the etch stop layer 718 is formed along opposing sidewalls and a top surface of the passivation layer 112. In some embodiments, the bottom surface of the etch stop layer 718 is aligned with the bottom surface of the passivation layer 112 and the bottom surface of the buffer layer 108.

[0127] As shown in cross-sectional view 4200 of FIG. 42, a dielectric structure 116, a plurality of conductive contacts 216, and a plurality of conductive wires 218 are formed on substrate 102.

[0128] 43 illustrates a flow diagram of some embodiments of a method 4300 of forming an IC with a buffer layer disposed between a substrate and a semiconductor layer of a photodetector. While method 4300 is illustrated and / or described as a series of acts or events, it should be understood that method 4300 is not limited to the illustrated order or acts. Thus, in some embodiments, acts may be performed in an order different from that illustrated and / or may be performed simultaneously. Furthermore, in some embodiments, an illustrated act or event may be subdivided into multiple acts or events, which may be performed separately or simultaneously with other acts or sub-acts. In some embodiments, some of the illustrated acts or events may be omitted, and other acts or events not illustrated may be included.

[0129] In operation 4302, a first avalanche well is formed in a base substrate. Figure 31 shows a cross-sectional view 3100 corresponding to some embodiments of operation 4302.

[0130] In operation 4304, an upper substrate layer comprising a first material is formed on the base substrate. Figure 32 shows a cross-sectional view 3200 corresponding to some embodiments of operation 4304.

[0131] In operation 4306, a vertical contact well and a first contact region are formed in the upper substrate layer and on opposite sides of the first avalanche well. Figure 33 shows a cross-sectional view 3300 corresponding to some embodiments of operation 4306.

[0132] In operation 4308, an avalanche well extension region is formed in the top substrate layer and over the first avalanche well. Figure 34 shows a cross-sectional view 3400 corresponding to some embodiments of operation 4308.

[0133] A second avalanche well is formed in the top substrate layer and over the avalanche well extension region in operation 4310. Figure 35 shows a cross-sectional view 3500 corresponding to some embodiments of operation 4310.

[0134] In operation 4312, a buffer layer is formed on the top substrate layer. The buffer layer includes a compound of a first material and a second material different from the first material. Figure 38 shows a cross-sectional view 3800 corresponding to some embodiments of operation 4312.

[0135] In an operation 4314, a semiconductor layer is formed on the buffer layer. The semiconductor layer comprises a second material. Figure 38 shows a cross-sectional view 3800 corresponding to some embodiments of operation 4314.

[0136] A patterning process is performed on the buffer layer and the semiconductor layer in operation 4316. Figure 39 shows a cross-sectional view 3900 corresponding to some embodiments of operation 4316.

[0137] In operation 4318, a passivation layer is formed on the semiconductor layer and the buffer layer. The passivation layer includes a first material and extends along sidewalls of the buffer layer and sidewalls of the semiconductor layer. Figure 40 shows a cross-sectional view 4000 corresponding to some embodiments of operation 4318.

[0138] In an operation 4320, a second contact region is formed in the semiconductor layer. Figure 40 shows a cross-sectional view 4000 corresponding to some embodiments of operation 4320.

[0139] In operation 4322, a plurality of conductive contacts and a plurality of conductive wires are formed on the substrate and coupled to the first and second contact regions. Figure 42 shows a cross-sectional view 4200 corresponding to some embodiments of operation 4322.

[0140] Thus, in some embodiments, the present invention relates to an integrated chip (IC) comprising a buffer layer disposed between a substrate and a semiconductor layer of a photodetector, the substrate comprising a first material and the semiconductor layer comprising a second material different from the first material, the buffer layer comprising a compound of the first material and the second material.

[0141] In some embodiments, the present invention provides an integrated chip (IC). The IC includes a substrate including a first material; a semiconductor layer disposed on the substrate and including a second material different from the first material; and a buffer layer disposed between the semiconductor layer and the substrate and including the first material and the second material. In some embodiments, the first material is silicon and the second material is germanium. In some embodiments, the buffer layer includes a first buffer film, a second buffer film, and a third buffer film, the first buffer film being disposed between the substrate and the second buffer film, and the third buffer film being disposed between the second buffer film and the semiconductor layer, wherein the concentration of the first material in the first buffer film is higher than the concentration of the first material in the second buffer film, and the concentration of the first material in the third buffer film is lower than the concentration of the first material in the second buffer film. In some embodiments, the concentration of the second material in the first buffer film is lower than the concentration of the second material in the second buffer film, the concentration of the second material in the third buffer film is higher than the concentration of the second material in the second buffer film, the thickness of the first buffer film is smaller than the thickness of the second buffer film, and the thickness of the third buffer film is greater than the thickness of the second buffer film. In some embodiments, the first concentration of the first material in the buffer layer decreases discretely by at least a factor of three in a first direction from the substrate to the semiconductor layer, and the second concentration of the second material in the buffer layer increases discretely by at least a factor of three in the first direction. In some embodiments, the ratio of the thickness of the buffer layer to the thickness of the semiconductor layer is within a range of 0.01 to 0.10. In some embodiments, the substrate includes opposing sidewalls defining a recess, the semiconductor layer is disposed in the recess, and the IC further includes an intermediate layer disposed in the recess between the buffer layer and the substrate, the intermediate layer comprising the first material. In some embodiments, the IC further includes a passivation layer covering an upper surface of the semiconductor layer and an upper surface of the buffer layer, the passivation layer contacting an inner sidewall of the intermediate layer and having an upper surface aligned with the upper surface of the substrate, the passivation layer comprising a first material.In some embodiments, the IC further includes: a plurality of first contact regions disposed in the substrate and laterally offset from the intermediate layer, the first contact regions being spaced apart on opposite sides of the semiconductor layer; a second contact region disposed in the semiconductor layer; and a plurality of outer lateral wells disposed in the semiconductor layer and below the plurality of first contact regions, the outer lateral wells extending continuously laterally from below a corresponding first contact region through the intermediate layer and the buffer layer to the semiconductor layer, wherein the doping type of the first contact regions and the outer lateral wells is different from the doping type of the second contact regions.

[0142] In some embodiments, the present invention provides an integrated circuit (IC). The IC includes a substrate having an upper surface, a germanium layer disposed on the upper surface of the substrate, an isolation structure disposed within the substrate and on an opposing side of the germanium layer, a buffer layer disposed between the upper surface of the substrate and the germanium layer, the buffer layer comprising silicon and germanium, and a passivation layer in contact with the upper surface of the germanium layer, the buffer layer comprising epitaxial silicon. In some embodiments, the lattice constant of the buffer layer increases discretely by at least a factor of two in a direction from a bottom surface of the buffer layer toward a bottom surface of the germanium layer. In some embodiments, the concentration of germanium in the buffer layer increases continuously in a first direction from the bottom surface of the buffer layer toward the bottom surface of the germanium layer, and the concentration of silicon in the buffer layer decreases continuously in a first direction from the bottom surface of the buffer layer toward the bottom surface of the germanium layer. In some embodiments, the substrate includes a first doping type, and the IC further includes: a first avalanche well disposed within the substrate and below the germanium layer, the first avalanche well including a second doping type opposite the first doping type; a first contact region disposed within the substrate and laterally surrounding the germanium layer, the first contact region being offset from the buffer layer and including the second doping type; a vertical connection well disposed within the substrate, extending continuously from the first contact region to the first avalanche well, the vertical connection well including the second doping type; and a second avalanche well disposed within the substrate, between the germanium layer and the second avalanche well, the second avalanche well including the first doping type. In some embodiments, the substrate includes opposing sidewalls extending from a top surface of the substrate to a top surface thereof and defining a recess, the germanium layer and the buffer layer are disposed within the recess, and the IC further includes an intermediate layer contacting the opposing sidewalls of the substrate, the intermediate layer being disposed between the substrate and the buffer layer, the intermediate layer having a thickness greater than a thickness of the buffer layer, and the passivation layer having a thickness greater than a thickness of the buffer layer. In some embodiments, a bottom surface of the germanium layer is located vertically above the top surface of the substrate, and outer sidewalls of the germanium layer are aligned with outer sidewalls of the buffer layer.In some embodiments, the passivation layer contacts the outer sidewalls of the germanium layer and the outer sidewalls of the buffer layer, and the bottom surface of the passivation layer is aligned with the bottom surface of the buffer layer.

[0143] In some embodiments, the invention includes a method of forming an IC, the method including: forming a buffer layer on a substrate, the substrate including a first material, the buffer layer including the first material and a second material different from the first material; forming a semiconductor layer on the buffer layer, the semiconductor layer including the second material; and forming a passivation layer along a top surface of the semiconductor layer, the passivation layer including the first material. In some embodiments, the method further includes: forming a first avalanche well in the substrate and below the semiconductor layer; forming a vertical connection well in the substrate and on an opposite side of the first avalanche well; forming a first contact region in the substrate and on the vertical connection well, wherein, in a top view, the vertical connection well and the first contact region are annular; forming a second avalanche well in the substrate and on the first avalanche well; and forming a second contact region in the semiconductor layer, wherein the second contact region and the second avalanche well comprise a first doping type, and the first avalanche well, the vertical connection well, and the first contact region comprise a second doping type opposite the first doping type. In some embodiments, forming the buffer layer includes epitaxially growing a first buffer film on the substrate; epitaxially growing a second buffer film on the first buffer film; and epitaxially growing a third buffer film on the second buffer film, wherein the first buffer film, the second buffer film, and the third buffer film have concentrations of a first material and a second material different from one another, and the first buffer film, the second buffer film, and the third buffer film each have a thickness less than a thickness of the passivation layer. In some embodiments, the method further includes first etching the substrate to form a recess; and forming an intermediate layer lining the recess, wherein the intermediate layer includes the first material, the intermediate layer is formed by a first epitaxial process, and the buffer layer is formed by a second epitaxial process, the thickness of the intermediate layer is greater than a thickness of the buffer layer, the buffer layer is formed on the intermediate layer in the recess, and the semiconductor layer is formed in the recess.

[0144] The foregoing outlines features of some embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art will readily appreciate that they may use this disclosure as a basis for designing or modifying other processes and structures which carry out the same purposes and / or achieve the same advantages as the embodiments presented herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made to the present disclosure without departing from the spirit and scope of the present disclosure. [Industrial Applicability]

[0145] The present invention provides a novel integrated chip (IC) and method for forming the same. [Explanation of symbols]

[0146] 100, 200a, 300a, 400a, 500a, 600a, 600b, 700a, 700c, 700d, 700e, 700f, 800a, 900a, 1000a, 1100a, 1200a, 1300a, 1400a, 1500a, 1600a, 1700a, 1800a, 1900a, 2000a, 2100a, 2300, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100, 3200, 3300, 3400, 3500, 3600, 3700, 3800, 3900, 4000, 4100, 4200: Cross section 102: Circuit board 102s1, 102s2: Side wall 102ls: Bottom surface 102t:Top surface 104: Photodetector 106: Middle class 108: Buffer layer 110: Semiconductor layer 112: Passivation layer 114: Isolation structure 116: Dielectric structure 118, 120: doped region 122, 124, 126, 128: Thickness 200b, 300b, 400b, 500b, 700b, 800b, 900b, 1000b, 1100b, 1200b, 1300b, 1400b, 1500b, 1600b, 1700b, 1800b, 1900b, 2000b, 2100b: Top view 202: Second contact region 204: Intermediate well region 206, 405: first contact region 208: Outer lateral well 210: Upper isolation doped region 212: Lower isolation doped region 216: Conductive contact 218: Conductive wire 402: Bottom well 404: First Avalanche Well 406: Vertical connection well 408: Doped surface region 410: Guard ring area 412: Second Avalanche Well 602: Vertical distance 604: Upper segment 702, 704, 706: Buffer film 710: Base board 712: Top substrate layer 714: Avalanche Well Expansion Area 718: Etching stop layer 720: upper doped surface region 802, 902, 1002, 1102, 1202, 1402, 1502, 3102, 3302, 3402, 3502, 3602: Injection masks 1302, 3902: Masking layers 1304, 2402: recessed parts 2200, 4300: Method 2202, 2204, 2206, 2208, 2210, 2212, 2214, 2216, 2218, 2220, 2222, 4302, 4304, 4306, 4308, 4310, 4312, 4314, 4316, 4318, 4320, 4322: Operation

Claims

1. a substrate comprising a first material; a semiconductor layer disposed on the substrate, the semiconductor layer comprising a second material different from the first material; a buffer layer disposed between the semiconductor layer and the substrate, the buffer layer including the first material and the second material; An integrated chip (IC) comprising:

2. the first material is silicon and the second material is germanium; 10. The IC of claim 1.

3. the buffer layer includes a first buffer film, a second buffer film, and a third buffer film, the first buffer film being disposed between the substrate and the second buffer film, the third buffer film being disposed between the second buffer film and the semiconductor layer, a concentration of the first material in the first buffer film being higher than a concentration of the first material in the second buffer film, and a concentration of the first material in the third buffer film being lower than the concentration of the first material in the second buffer film; 10. The IC of claim 1.

4. a concentration of the second material in the first buffer film is lower than a concentration of the second material in the second buffer film, a concentration of the second material in the third buffer film is higher than a concentration of the second material in the second buffer film, a thickness of the first buffer film is smaller than a thickness of the second buffer film, and a thickness of the third buffer film is greater than the thickness of the second buffer film; The IC of claim 3.

5. a first concentration of the first material in the buffer layer decreases discretely by at least a factor of three in a first direction from the substrate toward the semiconductor layer, and a second concentration of the second material in the buffer layer increases discretely by at least a factor of three in the first direction; 10. The IC of claim 1.

6. the ratio of the thickness of the buffer layer to the thickness of the semiconductor layer is in the range of 0.01 to 0.10; 10. The IC of claim 1.

7. The substrate includes opposing sidewalls defining a recess, the semiconductor layer is disposed within the recess, and the IC includes: an intermediate layer disposed in the recess between the buffer layer and the substrate, the intermediate layer comprising the first material; 10. The IC of claim 1.

8. a passivation layer covering an upper surface of the semiconductor layer and an upper surface of the buffer layer, the passivation layer contacting an inner sidewall of the intermediate layer and having an upper surface aligned with an upper surface of the substrate, the passivation layer comprising the first material; 8. The IC of claim 7.

9. a plurality of first contact regions disposed in the substrate and laterally offset from the intermediate layer, the first contact regions being spaced apart on opposite sides of the semiconductor layer; a second contact region disposed within the semiconductor layer; a plurality of outer lateral wells disposed within the substrate and disposed beneath the plurality of first contact regions, the outer lateral wells extending continuously laterally from beneath corresponding first contact regions through the intermediate layer and the buffer layer to the semiconductor layer, wherein the doping type of the first contact regions and the outer lateral wells is different from the doping type of the second contact regions; 8. The IC of claim 7.

10. a substrate including a top surface; a germanium layer disposed on the top surface of the substrate; isolation structures disposed within the substrate and on opposing sides of the germanium layer; a buffer layer disposed between the top surface of the substrate and the germanium layer, the buffer layer comprising silicon and germanium; a passivation layer in contact with an upper surface of the germanium layer and comprising epitaxial silicon; An integrated chip (IC) comprising:

11. the lattice constant of the buffer layer discretely increases by at least a factor of two in a direction from the bottom surface of the buffer layer toward the bottom surface of the germanium layer; The IC of claim 10.

12. a concentration of germanium in the buffer layer continuously increasing in a first direction from a bottom surface of the buffer layer to a bottom surface of the germanium layer, and a concentration of silicon in the buffer layer continuously decreasing in the first direction from the bottom surface of the buffer layer; The IC of claim 10.

13. The substrate includes a first doping type, and the IC includes: a first avalanche well disposed in the substrate and below the germanium layer, the first avalanche well including a second doping type opposite the first doping type; a first contact region disposed in the substrate and laterally covering the germanium layer, the first contact region being offset from the buffer layer and comprising the second doping type; a vertical connection well disposed in the substrate, extending continuously from the first contact region to the first avalanche well, the vertical connection well including the second doping type; a second avalanche well disposed in the substrate, the second avalanche well being disposed between the germanium layer and the second avalanche well and including the first doping type; The IC of claim 10 further comprising:

14. the substrate includes opposing sidewalls that extend from a top surface of the substrate to the top surface and define a recess, the germanium layer and the buffer layer are disposed within the recess, and the IC includes: further comprising an intermediate layer contacting the opposing sidewalls of the substrate, the intermediate layer being disposed between the substrate and the buffer layer, the intermediate layer having a thickness greater than a thickness of the buffer layer, and the passivation layer having a thickness greater than the thickness of the buffer layer; The IC of claim 10.

15. a bottom surface of the germanium layer is located vertically above a top surface of the substrate, and an outer sidewall of the germanium layer is aligned with an outer sidewall of the buffer layer; The IC of claim 10.

16. the passivation layer contacts the outer sidewalls of the germanium layer and the outer sidewalls of the buffer layer, and the bottom surface of the passivation layer is aligned with the bottom surface of the buffer layer.

16. The IC of claim 15.

17. 1. A method for forming an integrated chip (IC), comprising: forming a buffer layer on a substrate, the substrate comprising a first material, the buffer layer comprising the first material and a second material different from the first material; forming a semiconductor layer on the buffer layer, the semiconductor layer comprising the second material; forming a passivation layer along a top surface of the semiconductor layer, the passivation layer comprising the first material; A method comprising:

18. forming a first avalanche well in the substrate and below the semiconductor layer; forming a vertical contact well in the substrate and on an opposite side of the first avalanche well; forming a first contact region in the substrate and on the vertical connection well, wherein, in a top view, the vertical connection well and the first contact region are annular; forming a second avalanche well in the substrate and over the first avalanche well; forming a second contact region in the semiconductor layer, the second contact region and the second avalanche well comprising a first doping type; further comprising the first avalanche well, the vertical contact well, and the first contact region include a second doping type opposite the first doping type; 18. The method of claim 17.

19. forming the buffer layer epitaxially growing a first buffer film on the substrate; epitaxially growing a second buffer film on the first buffer film; epitaxially growing a third buffer film on the second buffer film, wherein the first material and the second material in the first buffer film, the second buffer film, and the third buffer film have different concentrations, and the thicknesses of the first buffer film, the second buffer film, and the third buffer film are each smaller than the thickness of the passivation layer; 18. The method of claim 17.

20. performing a first etching on the substrate to form a recess; forming an intermediate layer lining the recess, wherein the intermediate layer includes the first material, the intermediate layer is formed by a first epitaxial process, and the buffer layer is formed by a second epitaxial process, and the thickness of the intermediate layer is greater than the thickness of the buffer layer; the buffer layer is formed on the intermediate layer in the recess, and the semiconductor layer is formed in the recess.

18. The method of claim 17.

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