Control apparatus, information processing apparatus, and method

Abstract

To optimize, in a configuration in which a plurality of quantum bits to be cross-resonated are arranged on different chips, timing of control for cross-resonating the quantum bits or timing of reading from the quantum bits.SOLUTION: A control device comprising: a control circuit that performs a process of outputting a control signal for cross-resonating a plurality of quantum bits arranged on different chips to any of the plurality of quantum bits; a readout circuit that performs a process of outputting a readout signal for performing readout from the plurality of quantum bits to each of the plurality of quantum bits; and an adjustment circuit that adjusts an interval between an output of the control signal and an output of the readout signal according to a delay between the plurality of quantum bits.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a control device, an information processing device, and a method. [Background technology]

[0002] Conventionally, there is known a computer system that has multiple lattices on the same substrate, each having a configuration in which multiple quantum bits are arranged vertically and horizontally. This computer system performs calculations using the multiple lattices by connecting quantum bits facing each other between adjacent lattices (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2022 / 004274 Summary of the Invention [Problem to be solved by the invention]

[0004] A quantum logic gate used in quantum computers is a cross-resonant gate, in which multiple qubits are coupled. In a configuration in which multiple qubits that are cross-resonating are arranged on the same chip, the coupling between the multiple qubits that are cross-resonating is closed within the same chip, so the transmission delay between those qubits is relatively small.

[0005] However, in a configuration where multiple quantum bits that are cross-resonated are located on different chips, there is a risk of large transmission delays between the quantum bits that are cross-resonated, making it difficult to optimize (create) the timing for controlling the cross-resonation of those quantum bits or the timing for reading from those quantum bits.

[0006] The present disclosure aims to optimize the timing of control for cross-resonating multiple quantum bits or the timing of readout from those quantum bits in a configuration in which the quantum bits to be cross-resonated are each located on different chips. [Means for solving the problem]

[0007] In one aspect of the present disclosure, a control circuit that outputs a control signal to any one of a plurality of quantum bits that are arranged on different chips and that causes the quantum bits to cross-resonate; a readout circuit that processes outputting a readout signal for reading from the plurality of quantum bits to each of the plurality of quantum bits; There is provided a control device comprising: an adjustment circuit that adjusts the interval between the output of the control signal and the output of the readout signal in accordance with the delay between the plurality of quantum bits.

[0008] In another aspect of the present disclosure, Multiple qubits, each located on a different chip, a control circuit that outputs a control signal to any one of the plurality of quantum bits to cause the plurality of quantum bits to cross-resonate; a readout circuit that processes outputting a readout signal for reading from the plurality of quantum bits to each of the plurality of quantum bits; An information processing device is provided, comprising: an adjustment circuit that adjusts the interval between the output of the control signal and the output of the readout signal in accordance with the delay between the plurality of quantum bits.

[0009] In another aspect of the present disclosure, A method is provided for adjusting the interval between a process of outputting a control signal to one of a plurality of quantum bits to cross-resonate the quantum bits and a process of outputting a read signal to each of the plurality of quantum bits to read from the plurality of quantum bits, the read signal being output to each of the plurality of quantum bits, in accordance with the delay between the quantum bits located on different chips. [Effects of the Invention]

[0010] According to the present disclosure, in a configuration in which multiple quantum bits to be cross-resonated are arranged on different chips, the timing of control to cross-resonate those quantum bits or the timing of readout from those quantum bits can be optimized. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 10 is a diagram illustrating a cross resonant gate. [Figure 2] 1 is a diagram illustrating an example of the configuration of an information processing device according to a first embodiment. [Figure 3] 10 is a timing chart showing a first comparative example in which both the control timing and the read timing are fixed without being adjusted. [Figure 4] 10 is a timing chart showing a second comparative example in which both the control timing and the read timing are fixed without being adjusted. [Figure 5] 10 is a timing chart showing an example of adjusting the control timing and the read timing. [Figure 6] FIG. 2 is a diagram illustrating a specific configuration example of a control device according to the first embodiment. [Figure 7] 10 is a flowchart illustrating an example of a method for adjusting control timing and read timing. [Figure 8] FIG. 10 is a diagram illustrating an example of the configuration of an information processing device according to a second embodiment. [Figure 9] FIG. 2 is a diagram illustrating an example of a hardware configuration of a control device. DETAILED DESCRIPTION OF THE INVENTION

[0012] First, quantum computers and cross resonant gates are described.

[0013] A quantum computer has multiple qubits that form one-quantum logic gates such as Pauli gates and two-quantum logic gates such as CNOT gates, and performs calculations using these quantum logic gates. One of the two-quantum logic gates is the cross-resonant gate, which induces quantum entanglement.

[0014] 1 is a diagram illustrating a cross resonant gate. Cross resonant gate 70 has control qubit 71 to which control signal S is input, and target qubit 72 that is coupled to control qubit 71 via transmission line 73. Control qubit 71 and target qubit 72 have different resonant frequencies (also called "resonant frequencies" or "eigenfrequencies").

[0015] A control signal S for operating a cross resonant gate that couples the control qubit 71 and the target qubit 72 is input to the control qubit 71. In the cross resonant gate, to induce quantum entanglement between the control qubit 71 and the target qubit 72, which are adjacent to each other, a control signal S having the same frequency as the frequency at which the target qubit 72 resonates (resonant frequency) is input to the control qubit 71. This causes the state of the target qubit 72 to change depending on the quantum state of the control qubit 71. The control signal S may be, for example, a microwave.

[0016] Next, an information processing device that performs calculations using cross resonant gates will be described.

[0017] Fig. 2 is a diagram showing an example configuration of an information processing device according to the first embodiment. The information processing device 101 shown in Fig. 2 includes a plurality of quantum bits (hereinafter also referred to as "plural quantum bits q") including a first quantum bit 11 and a second quantum bit 21. The information processing device 101 is a quantum computer that processes information using the plurality of quantum bits q and outputs the processing result to the outside. In Fig. 2, quantum bits other than the first quantum bit 11 and the second quantum bit 21 among the plurality of quantum bits q are omitted from the illustration.

[0018] The information processing device 101 operates the first quantum bit 11 and the second quantum bit 21 as a cross resonant gate 400. In this example, when the first quantum bit 11 and the second quantum bit 21 are operated as the cross resonant gate 400, the first quantum bit 11 operates as a control quantum bit, and the second quantum bit 21 operates as a target quantum bit.

[0019] The first quantum bit 11 and the second quantum bit 21 are arranged on different chips. The first quantum bit 11 is arranged on the first chip 10. The second quantum bit 21 is arranged on the second chip 20. The first chip 10 is a substrate on which a plurality of quantum bits including the first quantum bit 11 is provided. The second chip 20 is a substrate on which a plurality of quantum bits including the second quantum bit 21 is provided.

[0020] First qubit 11 and second qubit 21 are each superconducting qubits such as transmons, but are not limited to this.

[0021] The information processing apparatus 101 includes a first cooling unit 201, a second cooling unit 202, external wiring 401, a computer 600, and a control device 301. Note that the computer 600 does not necessarily have to be included as a component of the information processing apparatus 101.

[0022] The first refrigerator 201 cools the first quantum bit 11. The first refrigerator 201 has a chamber that houses the first chip 10 on which the first quantum bit 11 is arranged, and cools the first chip 10 in the chamber together with the first quantum bit 11. The second refrigerator 202 cools the second quantum bit 21. The second refrigerator 202 has a chamber that houses the second chip 20 on which the second quantum bit 21 is arranged, and cools the second chip 20 in the chamber together with the second quantum bit 21. The first refrigerator 201 and the second refrigerator 202 are, for example, dilution refrigerators that use heat of dilution generated when liquid helium 3 is diluted with liquid helium 4. The first refrigerator 201 or the second refrigerator 202 may be a device that cools quantum bits using another cooling method.

[0023] External wiring 401 connects first refrigerator 201 and second refrigerator 202. External wiring 401 has a portion exposed to the outside of first refrigerator 201 and the outside of second refrigerator 202. A specific example of external wiring 401 is a coaxial cable. First quantum bit 11 in first refrigerator 201 and second quantum bit 21 in second refrigerator 202 are coupled via external wiring 401.

[0024] The computer 600 is a host computer for controlling the multiple quantum bits q. The computer 600 generates commands cmd for controlling the multiple quantum bits q and transmits them to the control device 301, and receives data d representing the readout results of the multiple quantum bits q from the control device 301. The computer 600 processes the data d and outputs the processing results to an external device such as a display. The computer 600 is connected to the control device 301 by wire or wirelessly.

[0025] The control device 301 generates a plurality of signals for a plurality of quantum bits q in accordance with a command cmd input from the computer 600 and outputs the signals to the first refrigerator 201 and the second refrigerator 202 via one or more lines. After outputting the signals for the plurality of quantum bits q, the control device 301 acquires readout results of the plurality of quantum bits q via one or more lines. The control device 301 outputs data d representing the readout results of the plurality of quantum bits q acquired via one or more lines to the computer 600.

[0026] The control device 301 includes a control circuit 30 , a read circuit 40 and an adjustment circuit 60 .

[0027] The control circuit 30 generates a plurality of signals for a plurality of quantum bits q and outputs them to one or a plurality of lines in accordance with a command cmd input from the computer 600. The control circuit 30 controls the cross-resonance of a plurality of quantum bits (first quantum bit 11 and second quantum bit 21) arranged on different chips.

[0028] In controlling the cross resonance of the first quantum bit 11 and the second quantum bit 21, the control circuit 30 generates and outputs a control signal S that causes the first quantum bit 11 and the second quantum bit 21 to operate as a cross resonance gate 400. The control signal S includes, for example, a drive pulse p1. The drive pulse p1 is a microwave pulse having the same frequency as the frequency at which the second quantum bit 21 resonates (the resonant frequency), and is input to the first quantum bit 11.

[0029] The readout circuit 40 reads out data from a plurality of quantum bits q. The readout circuit 40 reads out each state from the first quantum bit 11 and the second quantum bit 21 in accordance with the input of the control signal S.

[0030] The readout circuit 40 generates and outputs a read-in signal ri1 for reading out the state of the first quantum bit 11. The readout circuit 40 receives a readout signal ro1 representing the result of reading out the state of the first quantum bit 11 in response to the input of the read-in signal ri1. The readout circuit 40 outputs data d representing the result of reading out the state of the first quantum bit 11 to the computer 600 based on the readout signal ro1.

[0031] Similarly, the readout circuit 40 generates and outputs a read-in signal ri2 for reading out the state of the second quantum bit 21. The readout circuit 40 receives a readout signal ro2 representing the result of reading out the state of the second quantum bit 21 in response to the input of the read-in signal ri2. The readout circuit 40 outputs data d representing the result of reading out the state of the second quantum bit 21 to the computer 600 based on the readout signal ro2.

[0032] The adjustment circuit 60 adjusts one or both of the control timing ts for controlling the first quantum bit 11 and the second quantum bit 21 to cross-resonate, and the read timing tr for reading from the first quantum bit 11 and the second quantum bit 21.

[0033] 3 is a timing chart showing a first comparative example in which both the control timing ts and the read timing tr are fixed without adjustment. The waiting time Tw represents the time from when the control circuit 30 outputs the control signal S (driving pulse p1) until the read circuit 40 outputs the read-in signals ri1 and ri2 or receives the read-out signals ro1 and ro2.

[0034] The control circuit 30 controls the first quantum bit 11 and the second quantum bit 21 to cross-resonate at a control interval Ts. ts1 and ts2 correspond to the control timing ts at which this control is performed, and in this example, represent the output timing of the control signal S (drive pulse p1). The readout circuit 40 reads from the first quantum bit 11 and the second quantum bit 21 after the waiting time Tw has elapsed. Tr1 and tr2 correspond to the readout timing tr at which this reading is performed, and in this example, represent the output timing of read-in signals ri1 and ri2 or the reception timing of read-out signals ro1 and ro2.

[0035] In FIG. 3, the control timing ts is fixed, so the control interval Ts is a fixed time (unchanging time), and the read timing tr is fixed, so the waiting time Tw is a fixed time (unchanging time).

[0036] Control circuit 30 outputs drive pulse p1 of control signal S for each gate operation. As a result, quantum information of first quantum bit 11 is propagated to second quantum bit 21, and the state of second quantum bit 21 changes depending on the quantum state of first quantum bit 11. For example, when the state of first quantum bit 11 is 0, the state of second quantum bit 21 does not change. On the other hand, when the state of first quantum bit 11 is 1, the state of second quantum bit 21 is inverted.

[0037] A transmission delay (information propagation delay D) occurs between the first quantum bit 11 and the second quantum bit 21. In each gate operation, the readout circuit 40 takes into account the occurrence and variability of the delay D, and reads out the solution (data d) corresponding to the drive pulse p1 of the control signal S by receiving readout signals ro1 and ro2 after outputting read-in signals ri1 and ri2.

[0038] However, when the first qubit 11 and the second qubit 21 are placed on different chips, the information propagation path between the two bits becomes longer, and the delay D and its variability increase, compared to when the two bits are placed on the same chip. When the delay D increases, the timing at which the state of each qubit is determined in response to the input of the control signal S increases. Therefore, when the waiting time Tw is fixed, depending on the timing of the readout, the correct solution may not be obtained, and the readout accuracy may decrease.

[0039] 4 is a timing chart showing a second comparative example in which both the control timing ts and the read timing tr are fixed without adjustment. FIG. 4 shows a case in which the delay D increases compared to FIG. 3. In FIG. 4, in order to obtain a correct solution corresponding to the control signal S, the waiting time Tw is set to a fixed time that takes into account the increase in the delay D. However, even if the delay D becomes maximum due to aging or environmental changes, in order to obtain a correct solution corresponding to the control signal S, the control interval Ts is set to the maximum fixed time that takes into account the maximum value of the delay D. As a result, it takes a long time to obtain a correct solution corresponding to the control signal S, making it difficult to shorten the calculation time of the information processing device (to speed up calculations).

[0040] Therefore, the control device 301 according to the first embodiment includes an adjustment circuit 60 that adjusts one or both of the control timing ts and the readout timing tr to be shorter or longer depending on the result of measuring the delay D between the first quantum bit 11 and the second quantum bit 21.

[0041] FIG. 5 is a timing chart showing an example of adjusting the control timing ts and the read timing tr.

[0042] The adjustment circuit 60 may measure the delay D and adjust the read timing tr (e.g., the output timing of the read-in signals ri1 and ri2) to be shorter or longer depending on the measurement result of the delay D. By measuring the delay D, the adjustment circuit 60 can adjust the read timing tr to the optimal timing according to the actual variation in the delay D, and can therefore adjust the waiting time Tw to the optimal time according to the actual variation in the delay D. Because the read timing tr and waiting time Tw are optimized to such optimal values, the readout circuit 40 can obtain a correct solution according to the input of the control signal S. As a result, the accuracy of reading out the states of the first quantum bit 11 and the second quantum bit 21 is improved.

[0043] The adjustment circuit 60 may measure the delay D and adjust the control timing ts (e.g., the output timing of the drive pulse p1 of the control signal S) to be shorter or longer depending on the measurement result of the delay D. By measuring the delay D, the adjustment circuit 60 can adjust the control timing ts to the optimal timing depending on the actual variation in the delay D, and therefore can adjust the control interval Ts to the optimal time depending on the actual variation in the delay D. Because the control timing ts and the control interval Ts are optimized to such optimal values, the readout circuit 40 can obtain a correct solution depending on the input of the control signal S. As a result, the accuracy of reading out the states of the first quantum bit 11 and the second quantum bit 21 is improved. Furthermore, because the adjustment circuit 60 can shorten the control interval Ts to the optimal time at which a correct solution depending on the input of the control signal S is obtained, the calculation time of the control device 301 and the information processing device 101 is reduced, and the operation speed is increased.

[0044] Adjustment circuit 60 may not adjust control timing ts but may leave control interval Ts set to a fixed time, and adjust readout timing tr to be shorter or longer depending on the measurement result of delay D. This improves the accuracy of reading out the states of first quantum bit 11 and second quantum bit 21, as described above.

[0045] Alternatively, adjustment circuit 60 may not adjust readout timing tr, but may leave waiting time Tw set to a fixed time, and adjust control timing ts to be shorter or longer depending on the measurement result of delay D. This improves the accuracy of reading out the states of first quantum bit 11 and second quantum bit 21, as described above.

[0046] The waiting time Tw is set taking into consideration the delay D. The adjustment circuit 60 can set an appropriate waiting time Tw by identifying the delay D. To identify the delay D, the adjustment circuit 60 measures the values ​​of the read-out signals ro1 and ro2, for example, by varying the time interval from the output time of the control signal S to the output time of the read-in signals ri1 and ri2. Then, by identifying the time interval at which the values ​​of the read-out signals ro1 and ro2 match the expected values ​​described below, the delay D is indirectly identified.

[0047] The adjustment circuit 60 may adjust the read timing tr to a timing at which data d obtained by actually reading out the states of the first quantum bit 11 and the second quantum bit 21 matches an expected value that should be obtained in response to the input of the control signal S (driving pulse p1). The expected value that should be obtained in response to the input of the control signal S (driving pulse p1) is hereinafter also referred to as the "expected value X." By adjusting the read timing tr (e.g., waiting time Tw) to a first read timing (e.g., a first waiting time) at which the data d matches the expected value X, the adjustment circuit 60 further improves the readout accuracy of the states of the first quantum bit 11 and the second quantum bit 21.

[0048] The adjustment circuit 60 may vary the read timing tr within a predetermined first time range and set the read timing tr to the first read timing within the first time range at which the data d matches the expected value X. This makes it possible to extract the optimal first read timing within the first time range. For example, the adjustment circuit 60 sets the read timing tr to the median value of the period during which the data d matches the expected value X.

[0049] Adjustment circuit 60 may adjust control timing ts to the time when data d obtained by actually reading out the states of first quantum bit 11 and second quantum bit 21 matches expected value X that should be obtained in response to input of control signal S (driving pulse p1). Adjustment circuit 60 adjusts control timing ts (e.g., control interval Ts) to the first control timing (e.g., first control interval) at which data d matches expected value X, thereby further improving the accuracy of reading out the states of first quantum bit 11 and second quantum bit 21.

[0050] The adjustment circuit 60 may vary the control timing ts within a predetermined second time range and set the control timing ts to a first control timing within the second time range at which the data d matches the expected value X. This allows the optimum first control timing to be extracted within the second time range. For example, the adjustment circuit 60 sets the control timing ts to the minimum value of the period during which the data d matches the expected value X. This allows the adjustment circuit 60 to shorten the control interval Ts to the optimum shortest time at which a correct solution is obtained according to the input of the control signal S, thereby reducing the calculation time of the control device 301 and the information processing device 101 and increasing the operation speed.

[0051] 6 is a diagram showing a specific example of the configuration of the control device according to the first embodiment. The control device 301 includes a control circuit 30, a read circuit 40, and an adjustment circuit 60.

[0052] The control circuit 30 includes a generating unit 31, a generating unit 39, a writing unit 32, a memory 33, a reading unit 34, a DAC (Digital Analog Converter) 35, a local oscillator 36, a mixer 37, and a BPF (Band Pass Filter) 38.

[0053] The generation unit 31 generates a control command for controlling the states of multiple quantum bits q in accordance with a command cmd input from the computer 600. The generation unit 39 generates a test signal that causes the cross resonant gate 400 (FIG. 2) to operate as a predetermined quantum logic gate (e.g., a CNOT gate) in accordance with the command cmd input from the computer 600. The test signal is a signal for calibrating the read timing tr or the control timing ts.

[0054] The writing unit 32 temporarily writes the control command or test signal to the memory 33. The reading unit 34 reads the control command or test signal from the memory 33 in accordance with the control timing ts set by the setting unit 61 in the adjustment circuit 60, and outputs the read control command or test signal to the DAC 35. As a result, the reading unit 34 outputs the control command or test signal to the DAC 35 in accordance with the control timing ts set by the setting unit 61 in the adjustment circuit 60.

[0055] The DAC 35 is a circuit that converts a digital control command or test signal into an analog signal RF1 corresponding to the control command or test signal. The local oscillator 36 generates a local oscillation signal LOs having a higher frequency than the analog signal RF1. The mixer 37 multiplies the analog signal RF1 by the local oscillation signal LOs to upconvert the analog signal RF1 into a control signal S corresponding to the control command or test signal. The bandpass filter 38 attenuates noise in the control signal S. The control circuit 30 outputs the control signal S including a drive pulse p1 corresponding to the control command or test signal.

[0056] The readout circuit 40 includes a local oscillator 41, generators 42 and 52, mixers 43 and 53, ADCs (Analog Digital Converters) 44 and 54, write units 45 and 55, memories 46 and 56, readout units 47 and 57, and an analyzer 48.

[0057] The local oscillator 41 generates a locally oscillated signal L Or having a higher frequency than the intermediate frequency signal fr generated by the adjustment circuit 60. The generation unit 42 multiplies the intermediate frequency signal fr by the locally oscillated signal L Or to up-convert the intermediate frequency signal fr to a lead-in signal ri1. The generation unit 52 multiplies the intermediate frequency signal fr by the locally oscillated signal L Or to up-convert the intermediate frequency signal fr to a lead-in signal ri2. The readout circuit 40 outputs the lead-in signals ri1 and ri2 in accordance with the readout timing tr set by the setting unit 62 in the adjustment circuit 60.

[0058] The mixer 43 down-converts the readout signal ro1 to an analog signal aro1 by multiplying the readout signal ro1 by a locally oscillated signal LOr. The mixer 53 down-converts the readout signal ro2 to an analog signal aro2 by multiplying the readout signal ro2 by a locally oscillated signal LOr.

[0059] The ADC 44 is a circuit that converts an analog signal aro1 corresponding to the readout signal ro1 into digital read data dr1. The ADC 54 is a circuit that converts an analog signal aro2 corresponding to the readout signal ro2 into digital read data dr2.

[0060] The writing unit 45 temporarily writes the read data dr1 to the memory 46. The reading unit 47 reads the read data dr1 from the memory 46 and outputs it to the analyzing unit 48. The writing unit 55 temporarily writes the read data dr1 to the memory 56. The reading unit 57 reads the read data dr2 from the memory 56 and outputs it to the analyzing unit 48.

[0061] The analysis unit 48 analyzes the two read data dr1 and dr2. From the two read data dr1 and dr2, the analysis unit 48 generates data d, which is a solution obtained by the cross resonant gate 400. The analysis unit 48 outputs the data d to the computer 600 and the adjustment circuit 60.

[0062] The adjustment circuit 60 has a setting section 61 that sets the control timing ts and a setting section 62 that sets the read timing tr.

[0063] The setting unit 62 compares the data d obtained by the analysis unit 48 based on the readout signals ro1 and ro2 in response to the input of the control signal S corresponding to the test signal with a known expected value X obtained by the test signal. The setting unit 62 sets the read timing tr to the first read timing at which the data d matches the expected value X. For example, the setting unit 62 sets the read timing tr to the optimal first read timing at which the data d matches the expected value X within a first time range obtained by changing the read timing tr (for example, the median of the period during which the data d matches the expected value X).

[0064] The setting unit 62 may store in memory the first read timing (for example, the optimal first waiting time of the waiting time Tw) to be set as the read timing tr. The read circuit 40 may perform reading according to the first read timing stored in memory from the next time onwards. This eliminates the need to reset the first read timing based on the test signal for each read from the next time onwards. As a result, the number of times the first read timing is set is reduced, and the calibration time for the read timing tr is shortened.

[0065] The setting unit 61 compares data d obtained by the analysis unit 48 based on the readout signals ro1 and ro2 in response to input of a control signal S corresponding to a test signal with a known expected value X obtained from the test signal. The setting unit 61 sets the control timing ts to the first control timing at which the data d matches the expected value X. For example, the setting unit 61 sets the control timing ts to the optimal first control timing at which the data d matches the expected value X within a second time range obtained by changing the control timing ts (for example, the minimum value of the period during which the data d matches the expected value X).

[0066] The setting unit 61 may store in memory the first control timing (e.g., the optimal first control interval of the control interval Ts) to be set for the control timing ts. The readout circuit 40 may perform control according to the first control timing stored in memory from the next readout onward. This eliminates the need to reset the first control timing based on the test signal every time a readout is performed from the next readout onward. As a result, the number of times the first control timing is set is reduced, and the calibration time for the control timing ts is shortened.

[0067] FIG. 7 is a flowchart showing an example of a method for adjusting the control timing ts and the read timing rs.

[0068] In step S11, the control device 301 starts calibration in accordance with a command cmd (a command to start calibration) input from the computer 600.

[0069] In step S13, the adjustment circuit 60 acquires connection information for the multiple quantum bits q. In step S15, the adjustment circuit 60 determines, based on the acquired connection information, whether or not there is a connection spanning across chips between the multiple quantum bits to be cross-resonated. Step S15 is a process for determining whether the objects to be cross-resonated are multiple quantum bits located on different chips. For example, if the adjustment circuit 60 determines that the objects to be cross-resonated are multiple quantum bits located on different chips, it adjusts the control timing ts or the readout timing tr according to the result of measuring the delay D as described above.

[0070] When the adjustment circuit 60 determines that there is no connection spanning across chips among the multiple quantum bits to be cross-resonated, it refers to a first initial pattern for the initial values ​​of the waiting time Tw and the control interval Ts (step S17). The first initial pattern specifies first initial values ​​that take into account the maximum value of the delay D when there is no connection spanning across chips.

[0071] When the adjustment circuit 60 determines that there is a connection spanning across chips among the multiple quantum bits to be cross-resonated, it refers to the second initial pattern for the initial values ​​of the waiting time Tw and the control interval Ts (step S19). The second initial pattern specifies second initial values ​​that take into account the maximum value of the delay D when spanning across chips.

[0072] In step S21, the adjustment circuit 60 sets initial values ​​for the waiting time Tw and the control interval Ts based on the initial pattern referenced in accordance with the determination result of step S15. In step S21, the adjustment circuit 60 may initialize the microwave intensity of the control signal S.

[0073] In step S23, the setting unit 62 of the adjustment circuit 60 sets the read timing tr to a timing that is changed by a predetermined amount from the currently set timing.

[0074] In step S25, the control circuit 30 outputs a control signal S including a drive pulse p1 corresponding to the test signal, which causes the cross resonant gate 400 to operate as a quantum logic gate designated by the test signal (step S27).

[0075] In step S29, the read circuit 40 outputs the lead-in signals ri1 and ri2 in accordance with the read timing tr set by the setting section 62 in the adjustment circuit 60 in the immediately preceding step S23.

[0076] In step S31, the analysis unit 48 derives data d, which is a solution obtained by the cross resonance gate 400, based on the readout signals ro1 and ro2 received in response to the read-in signals ri1 and ri2 output in the immediately preceding step S29. The analysis unit 48 stores the derived data d in memory.

[0077] In step S33, the setting unit 62 determines whether the read timing tr has been changed over the entire period of the predetermined first time range. If the read timing tr has not been changed over the entire period of the predetermined first time range, the setting unit 62 repeats the processes from step S23 onwards. On the other hand, if the read timing tr has not been changed over the entire period of the predetermined first time range, the setting unit 62 executes the process of step S35.

[0078] In step S35, the setting unit 62 extracts, within the first time range, a first read timing at which the data d matches the expected value X. In step S37, the setting unit 62 sets the read timing tr to the first read timing extracted in step S35 (for example, the median value of the period during which the data d matches the expected value X).

[0079] In step S39, the setting unit 61 sets the control timing ts to the first control timing at which the data d matches the expected value X. For example, similar to the setting process of the read timing tr from step S23 to step S37 described above, the setting unit 61 changes the control timing ts within a predetermined second time range, and sets the control timing ts to the first control timing at which the data d matches the expected value X within the second time range.

[0080] In step S41, the adjustment circuit 60 determines whether the setting of the read timing tr and the control timing ts has been completed for all connections of multiple quantum bits that are to be cross-resonated across chips. If there are any connections for which the read timing tr and the control timing ts have not been set, the adjustment circuit 60 repeats the processing from step S21 onwards for the connections for which the read timing tr and the control timing ts have not been set.

[0081] 8 is a diagram showing an example of the configuration of an information processing device according to the second embodiment. In the second embodiment, the description of the configuration, actions, and effects similar to those of the first embodiment will be omitted by citing the above description. The information processing device 102 shown in FIG. 8 differs from the information processing device 101 according to the first embodiment in that the first chip 10 on which the first quantum bit 11 is arranged and the second chip 20 on which the second quantum bit 21 is arranged are cooled by a common cooling device 200.

[0082] Internal wiring 402 connects first chip 10 and second chip 20 within cooling device 200. First quantum bit 11 in first chip 10 and second quantum bit 21 in second chip 20 are coupled via internal wiring 402.

[0083] In the second embodiment as well, a transmission delay (delay D in information propagation) may occur between the first quantum bit 11 and the second quantum bit 21. Therefore, similar to the first embodiment, the adjustment circuit 60 can optimize the control timing ts or the readout timing tr by adjusting one or both of the control timing ts and the readout timing tr according to the result of measuring the delay D.

[0084] Thus, according to each of the above embodiments, in a configuration in which multiple quantum bits to be cross-resonated are arranged on different chips, the timing of controlling the cross-resonation of those quantum bits or the timing of reading from those quantum bits can be optimized.

[0085] In each embodiment, part or all of the control device 301 is an electronic circuit such as a central processing unit (CPU), a field programmable gate array (FPGA), or an application specific integrated circuit (ASIC). Part or all of the control device 301 may be a computer having a memory and a processor. Part or all of the control device 301 executes a program such as instruction code stored in a memory, or is designed as a circuit for a specific application, thereby performing the various control operations described in this specification.

[0086] 9 is an example of a hardware configuration diagram of a control device. The control device 500 corresponds to part or all of the control device 301. The control device 500 has a drive device 508, an auxiliary storage device 502, a memory device 503, a CPU 504, an interface device 505, and the like, which are all connected to each other via a bus 506.

[0087] A program that realizes processing in the control device 500 is provided by a recording medium 507. When the recording medium 507 on which the program is recorded is set in the drive device 508, the program is installed from the recording medium 507 to the auxiliary storage device 502 via the drive device 508. However, the program does not necessarily have to be installed from the recording medium 507, but may be downloaded from another computer via a network. The auxiliary storage device 502 stores the installed program as well as necessary files, data, etc.

[0088] When an instruction to start a program is received, the memory device 503 reads the program from the auxiliary storage device 502 and stores it. The CPU 504 is a processor that executes functions related to the control device 500 in accordance with the program stored in the memory device 503. The interface device 505 is used as an interface for connecting to the outside.

[0089] Examples of the recording medium 507 include portable recording media such as a CD-ROM, a DVD disk, or a USB memory. Examples of the auxiliary storage device 502 include a hard disk drive (HDD) or a flash memory. Both the recording medium 507 and the auxiliary storage device 502 correspond to computer-readable recording media.

[0090] Although the embodiments have been described above, they are presented as examples and the present invention is not limited to the above embodiments. The above embodiments can be implemented in various other forms, and various combinations, omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as set forth in the claims.

[0091] The following additional notes are provided regarding the above-described embodiments.

[0092] (Appendix 1) a control circuit that outputs a control signal to any one of a plurality of quantum bits that are arranged on different chips and that causes the quantum bits to cross-resonate; a readout circuit that processes outputting a readout signal for reading from the plurality of quantum bits to each of the plurality of quantum bits; an adjustment circuit that adjusts an interval between the output of the control signal and the output of the readout signal in accordance with delays between the plurality of quantum bits. (Appendix 2) 2. The control device according to claim 1, wherein the adjustment circuit adjusts a read timing at which the read signal is output in accordance with the delay. (Appendix 3) 3. The control device according to claim 2, wherein the adjustment circuit adjusts the read timing to a timing at which data obtained by the read signal matches an expected value. (Appendix 4) The control device described in Appendix 3, wherein the adjustment circuit sets the read timing to a first read timing within a first time range in which the read timing is changed, at which the data matches the expected value. (Appendix 5) the adjustment circuit stores the first read timing; 5. The control device according to claim 4, wherein the read circuit performs the readout in accordance with the stored first readout timing from the next time onward. (Appendix 6) The control device according to any one of Supplementary notes 2 to 5, wherein the adjustment circuit adjusts an output timing of a lead-in signal for reading in accordance with the delay. (Appendix 7) 7. The control device according to claim 1, wherein the adjustment circuit adjusts a control timing for outputting the control signal in accordance with the delay. (Appendix 8) 8. The control device according to claim 7, wherein the adjustment circuit adjusts the interval of the control timing in accordance with the delay. (Appendix 9) 9. The control device according to claim 7, wherein the adjustment circuit adjusts the control timing to a timing at which the data obtained by the readout matches an expected value. (Appendix 10) 10. The control device according to claim 9, wherein the adjustment circuit sets the control timing to a first control timing at which the data matches the expected value within a second time range in which the control timing is changed. (Appendix 11) the adjustment circuit stores the first control timing; 11. The control device according to claim 10, wherein the readout circuit outputs the control signal in accordance with the stored first control timing from the next time onwards. (Appendix 12) 12. The control device according to any one of appendices 7 to 11, wherein the adjustment circuit adjusts an output timing of a control signal input to a control quantum bit included in the plurality of quantum bits in accordance with the delay. (Appendix 13) 13. The control device according to any one of appendices 1 to 12, wherein the adjustment circuit determines whether the object to be cross-resonated is the plurality of quantum bits, and if it determines that the object is the plurality of quantum bits, adjusts the interval according to the delay. (Appendix 14) Multiple qubits, each located on a different chip, a control circuit that outputs a control signal to any one of the plurality of quantum bits to cause the plurality of quantum bits to cross-resonate; a readout circuit that processes outputting a readout signal for reading from the plurality of quantum bits to each of the plurality of quantum bits; an adjustment circuit that adjusts an interval between the output of the control signal and the output of the readout signal in accordance with a delay between the plurality of quantum bits. (Appendix 15) a first refrigerator that cools a first chip on which a control quantum bit included in the plurality of quantum bits is arranged; a second refrigerator configured to cool a second chip on which a target quantum bit included in the plurality of quantum bits is disposed; an external wiring that connects the first cooling machine and the second cooling machine; 15. The information processing device of claim 14, wherein the control qubit and the target qubit are coupled via the external wiring. (Appendix 16) A method for adjusting the interval between a process of outputting a control signal to one of a plurality of quantum bits that causes the quantum bits to cross-resonate and a process of outputting a readout signal to each of the plurality of quantum bits to read from the plurality of quantum bits, in accordance with a delay between the quantum bits that are located on different chips. [Explanation of symbols]

[0093] 10 First Chip 11 First qubit 20 Second Chip 21 Second qubit 30 Control circuit 40 Readout circuit 60 Adjustment circuit 70 Cross Resonance Gate 71 control qubits 72 target qubits 73 Transmission Line 101 Information processing equipment 200 Cooler 201 1st cooling machine 202 Second cooling machine 301 Control device 400 Cross Resonance Gate 401 External wiring 402 Internal wiring 500 control device 600 computers

Claims

1. a control circuit that outputs a control signal to any one of a plurality of quantum bits that are arranged on different chips and that causes the quantum bits to cross-resonate; a readout circuit that processes outputting a readout signal for reading from the plurality of quantum bits to each of the plurality of quantum bits; an adjustment circuit that adjusts an interval between the output of the control signal and the output of the readout signal in accordance with delays between the plurality of quantum bits.

2. The control device according to claim 1 , wherein the adjustment circuit adjusts a read timing at which the read signal is output in accordance with the delay.

3. The control device according to claim 2 , wherein the adjustment circuit adjusts the read timing to a timing at which the data obtained by the readout matches an expected value.

4. The control device according to claim 3 , wherein the adjustment circuit sets the read timing to a first read timing at which the data matches the expected value within a first time range obtained by changing the read timing.

5. the adjustment circuit stores the first read timing; The control device according to claim 4 , wherein the read circuit performs the read operation in accordance with the stored first read timing from the next time onward.

6. The control device according to claim 2 , wherein the adjustment circuit adjusts an output timing of a lead-in signal for reading the data in accordance with the delay.

7. The control device according to claim 1 , wherein the adjustment circuit adjusts a control timing for outputting the control signal in accordance with the delay.

8. The control device according to claim 7 , wherein the adjustment circuit adjusts the control timing to a timing at which the data obtained by the readout matches an expected value.

9. The control device according to claim 8 , wherein the adjustment circuit sets the control timing to a first control timing at which the data matches the expected value within a second time range obtained by changing the control timing.

10. the adjustment circuit stores the first control timing; 10. The control device according to claim 9, wherein the read circuit outputs the control signal in accordance with the stored first control timing from the next time onward.

11. The control device according to claim 7 , wherein the adjustment circuit adjusts, in accordance with the delay, an output timing of a control signal input to a control quantum bit included in the plurality of quantum bits.

12. 7. The control device according to claim 1, wherein the adjustment circuit determines whether the object to be cross-resonated is the plurality of quantum bits, and if the object is determined to be the plurality of quantum bits, adjusts the interval according to the delay.

13. Multiple qubits, each located on a different chip, a control circuit that outputs a control signal to any one of the plurality of quantum bits to cause the plurality of quantum bits to cross-resonate; a readout circuit that processes outputting a readout signal for reading from the plurality of quantum bits to each of the plurality of quantum bits; an adjustment circuit that adjusts an interval between the output of the control signal and the output of the readout signal in accordance with a delay between the plurality of quantum bits.

14. a first cooling device that cools a first chip on which a control quantum bit included in the plurality of quantum bits is arranged; a second refrigerator configured to cool a second chip on which a target quantum bit included in the plurality of quantum bits is disposed; an external wiring that connects the first cooling machine and the second cooling machine; The information processing device according to claim 13 , wherein the control qubit and the target qubit are coupled via the external wiring.

15. A method for adjusting the interval between a process of outputting a control signal to one of a plurality of quantum bits that causes the quantum bits to cross-resonate and a process of outputting a readout signal to each of the plurality of quantum bits to read from the plurality of quantum bits, in accordance with a delay between the quantum bits that are located on different chips.

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