Image sensor and method of manufacturing the same

Abstract

To provide an image sensor including a light shield pattern inserted into a light transmission film, and to provide a method of manufacturing the same.SOLUTION: The image sensor includes a substrate having a first surface and a second surface opposite to the first surface and including pixel regions spaced apart from each other, a light transmission film covering the second surface and including an anti-reflection film having a recess region, a light shield pattern provided in the light transmission film and filling the recess region to cover a portion of a first pixel region among the pixel regions, a grid disposed on the light transmission film, a color filter filling an opening of the grid, and a microlens disposed on the color filter.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to an image sensor and a method for manufacturing the same. [Background technology]

[0002] An image sensor is a semiconductor device that converts optical images into electrical signals. Recently, with the development of the computer and communications industries, there has been an increasing demand for image sensors with improved performance in various fields, such as digital cameras, video cameras, personal communication systems (PCS), game consoles, security cameras, and medical micro cameras. Image sensors are classified into charge coupled device (CCD) and complementary metal oxide semiconductor (CMOS) types. CMOS image sensors have multiple pixels arranged two-dimensionally. Each pixel contains a photodiode (PD). The photodiode converts incident light into an electrical signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 1,121,1410 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above-mentioned conventional technology, and an object of the present invention is to provide an image sensor including a light shielding pattern inserted in a light-transmitting film, and a manufacturing method thereof. [Means for solving the problem]

[0005] In order to achieve the above object, an image sensor according to one aspect of the present invention includes a substrate having a first surface and a second surface opposite to the first surface and including pixel regions spaced apart from each other; a light-transmitting film covering the second surface and including an anti-reflection portion having a recessed region; a light-shielding pattern provided in the light-transmitting film, filling the recessed region and covering a portion of a first pixel region in the pixel region; a grid disposed on the light-transmitting film; a color filter filling openings in the grid; and a microlens disposed on the color filter.

[0006] In order to achieve the above object, another aspect of the present invention provides an image sensor comprising: a substrate having a first surface and a second surface opposite to the first surface; a first deep element isolation pattern disposed within the substrate and defining pixel regions, each pixel region including a pair of subpixel regions; a second deep element isolation pattern disposed between each of the pair of subpixel regions; an anti-reflection film covering the second surface and having a recess region; a light shielding pattern filling the recess region; a grid disposed on the anti-reflection film; a color filter filling an opening in the grid; and a microlens disposed on the color filter, wherein at least a first pixel region within the pixel regions is part of an autofocus pixel; and the light shielding pattern covers at least a portion of one of the pair of subpixel regions of the first pixel region.

[0007] In order to achieve the above object, according to one aspect of the present invention, a method for manufacturing an image sensor includes the steps of forming a surface insulating film on one surface of a substrate, forming an anti-reflection film on the surface insulating film, etching the anti-reflection film to form a recess area in the anti-reflection film, forming a light shielding pattern in the recess area, forming a capping film on the light shielding pattern and the anti-reflection film, and forming a grid and a color filter on the capping film. [Effects of the Invention]

[0008] According to the present invention, quantum efficiency (QE) can be improved by selectively forming a light shielding pattern. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram of an image sensor according to an embodiment of the present invention; [Figure 2] FIG. 2 is a circuit diagram of a pixel array included in the pixel array of the image sensor of the present invention. [Figure 3A] 2 is a circuit diagram of an example of a pixel group of an image sensor according to an embodiment of the present invention; [Figure 3B] 10 is a circuit diagram of another example of a pixel group of an image sensor according to an embodiment of the present invention. [Figure 4] 1 is a cross-sectional view of an image sensor according to an embodiment of the present invention; [Figure 5] FIG. 5 is an enlarged cross-sectional view of a first example of part 'A' in FIG. [Figure 6] 5 is an enlarged cross-sectional view of a second example of an image sensor according to an embodiment of the present invention, corresponding to part 'A' of FIG. 4. [Figure 7] 5 is an enlarged cross-sectional view of a third example of an image sensor according to an embodiment of the present invention, corresponding to part 'A' of FIG. 4. [Figure 8] 5 is an enlarged cross-sectional view of a fourth example of an image sensor according to an embodiment of the present invention, corresponding to part 'A' of FIG. 4. [Figure 9] 5 is an enlarged cross-sectional view of a fifth example of an image sensor according to an embodiment of the present invention, corresponding to part 'A' of FIG. 4. [Figure 10] 5 is an enlarged cross-sectional view of a sixth example of an image sensor according to an embodiment of the present invention, corresponding to part 'A' of FIG. 4. [Figure 11] 7 is an enlarged cross-sectional view of a seventh example of an image sensor according to an embodiment of the present invention, corresponding to part 'A' of FIG. 4. [Figure 12]5 is an enlarged cross-sectional view of an eighth example of an image sensor according to an embodiment of the present invention, corresponding to part 'A' of FIG. 4. [Figure 13] 5 is an enlarged cross-sectional view of a ninth example of an image sensor according to an embodiment of the present invention, corresponding to part 'A' of FIG. 4. [Figure 14] 10 is an enlarged cross-sectional view of a tenth example of an image sensor according to an embodiment of the present invention, corresponding to part 'A' of FIG. 4. [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 16] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 17] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 18] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 20] 5 is an enlarged cross-sectional view of an eleventh example of an image sensor according to an embodiment of the present invention, corresponding to part 'A' of FIG. 4. [Figure 21] 1 is a cross-sectional view of an image sensor having a stacked structure according to an embodiment of the present invention; [Figure 22] 1 is a cross-sectional view of an image sensor having a multi-layer structure according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, specific examples of embodiments of the present invention will be described in detail with reference to the drawings.

[0011] Throughout the specification, when a component is described as "comprising" a particular element or group of elements, unless the context clearly indicates otherwise, it should be understood that the component consists solely of that element or group of elements, or that that element or group of elements is combined with additional elements to form the component. Conversely, the term "consisting of" indicates that the component consists solely of the listed elements.

[0012] Ordinal numbers such as "first," "second," "third," etc., are used simply to label particular elements, steps, etc., to distinguish them from one another. Terms not described in the specification as "first," "second," etc., may also be referred to as "first" or "second" in the claims. Also, terms referred to by a particular ordinal number (e.g., "first" in a particular claim) may be described elsewhere by another ordinal number (e.g., "second" in the specification or another claim).

[0013] Spatial and relative terms such as "below," "below," "lower," "above," "upper," "bottom," etc. are used herein for ease of description to describe the relationship of one element or feature to other elements or features as shown in the drawings. Spatial and relative terms should be understood to include various orientations of the device in use or operation other than the orientation shown in the drawings. For example, if the device were turned over in the drawings, elements described as "below" or "below" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation of above and below. The device could be placed in other orientations (rotated 90 degrees or at other orientations) and the spatial and relative descriptions used herein interpreted accordingly.

[0014] Items described in the singular herein may be provided in plural, as can be seen, for example, in the drawings, and therefore, a description of a singular item provided in plural should be understood to apply to the remaining plural items as well, unless the context clearly indicates otherwise.

[0015] FIG. 1 is a block diagram of an image sensor according to one embodiment of the present invention.

[0016] Referring to FIG. 1 , the image sensor according to this embodiment includes a pixel array 1, a row decoder 2, a row driver 3, a column decoder 4, a timing generator 5, a correlated double sampler (CDS) 6, an analog to digital converter (ADC) 7, and an input / output buffer 8.

[0017] The pixel array 1 includes a plurality of pixels arranged two-dimensionally, and the pixels convert optical signals into electrical signals. As used herein, pixel or unit pixel refers to a sensor element (e.g., a single pixel sensor) of the image sensor of the present invention and / or the smallest addressable light-sensing element of the image sensor. In some cases, a pixel is included as part of a pixel array or pixel group and / or within a pixel region, as described herein. In some cases, a pixel includes one or more subpixels, as described herein, and is therefore not limited to a single unit pixel. The pixel array 1 is driven by a plurality of drive signals (e.g., pixel select signals, reset signals, and / or charge transfer signals) transmitted from a row driver 3. The converted electrical signals are provided to a correlated double sampler (CDS) 6.

[0018] The row driver 3 provides a plurality of driving signals to the pixel array 1 for driving a plurality of pixels according to the result of decoding by the row decoder 2. When the pixels are arranged in a matrix, the driving signals are provided row by row.

[0019] A timing generator 5 provides timing and control signals to the row decoder 2 and the column decoder 4 .

[0020] The correlated double sampler 6 receives the electrical signal generated by the pixel array 11 and holds and samples the received signal. The correlated double sampler 6 double samples a specific noise level and a signal level based on the electrical signal, and outputs a difference level corresponding to the difference between the noise level and the signal level.

[0021] An analog-to-digital converter (ADC) 7 converts the analog signal corresponding to the difference level output from the correlated double sampler 6 into a digital signal, and outputs the digital signal.

[0022] The input / output buffer 8 latches the digital signals and sequentially outputs the latched signals to an image signal processor (not shown) according to the decoding result of the column decoder 4 .

[0023] FIG. 2 is a circuit diagram of a pixel included in a pixel array of an image sensor according to an embodiment of the present invention.

[0024] 2, the pixel array includes a plurality of pixels PXL, which are arranged in a matrix. Each pixel PXL includes a transfer transistor TX and logic transistors (RX, SX, SFX). The logic transistors (RX, SX, SFX) include a reset transistor RX, a selection transistor SX, and a source follower transistor SFX. Each pixel PXL also includes a photoelectric conversion element PD and a floating diffusion region FD.

[0025] The photoelectric conversion element PD generates and accumulates photocharges in proportion to the amount of externally incident light. The photoelectric conversion element PD may include a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof. The transfer transistor TX transfers the photocharges generated in the photoelectric conversion element PD to the floating diffusion region FD. The transfer gate of the transfer transistor TX is connected to a transfer gate line TGL. The floating diffusion region FD receives and cumulatively stores the photocharges generated in the photoelectric conversion element PD.

[0026] The gate of the source follower transistor SFX is connected to the floating diffusion region FD. The drain terminal of the source follower transistor SFX is connected to a power supply terminal V DD The source follower transistor SFX is controlled in response to the amount of photocharge accumulated in the floating diffusion region FD.

[0027] The reset transistor RX periodically resets the charge stored in the floating diffusion region FD. The gate of the reset transistor RX is connected to a reset gate line RGL. The source terminal of the reset transistor RX is connected to the floating diffusion region FD, and the drain terminal of the reset transistor RX is connected to a power supply terminal V. DD When the reset transistor RX is turned on, the power supply terminal V DD The power supply voltage is applied to the floating diffusion region FD through the reset transistor RX. For example, when the reset transistor RX is turned on, the charge stored in the floating diffusion region FD is discharged by the power supply voltage, and the floating diffusion region FD is reset.

[0028] The source follower transistor SFX acts as a source follower buffer amplifier. The source follower transistor SFX amplifies the potential change in the floating diffusion region FD and outputs the amplified potential change to the output line V OUT Output to.

[0029] The gate of the select transistor SX is connected to a select gate line SGL, the drain terminal of the select transistor SX is connected to the source terminal of the source follower transistor SFX, and the source terminal of the select transistor SX is connected to the output line V OUT The selection transistor SX of the pixel PXL to be read out row by row is selected by a selection signal applied through the corresponding selection gate line SGL. When the selection transistor SX is turned on, the potential change amplified by the source follower transistor SFX is transmitted to the output line V OUT will be output.

[0030] Although each pixel PXL includes a photoelectric conversion element PD, a transfer transistor TX, and logic transistors (RX, SX, SFX) in FIG. 2, embodiments of the present invention are not limited thereto. In one embodiment, some pixels adjacent to each other may form a pixel group, and the pixels of the pixel group may share at least one of the logic transistors (RX, SX, SFX). A related example will be described with reference to FIGS. 3A and 3B.

[0031] 3A and 3B are circuit diagrams of an example pixel group and another example pixel group of an image sensor according to an embodiment of the present invention.

[0032] 3A and 3B, the pixel array includes pixel groups PXLG, each of which includes a plurality of pixels. A circuit diagram of a single pixel group PXLG is shown in each of FIGS. 3A and 3B. Unlike individual pixels (e.g., FIG. 2), in this example, the pixels of a pixel group share the reset transistor RX, source follower transistor SFX, and select transistor SX described above.

[0033] Referring to FIG. 3A, in this embodiment, pixel group PXLG includes four pixels (e.g., first to fourth pixels). The first pixel includes a first transfer transistor TX1 and a first photoelectric conversion element PD1, the second pixel includes a second transfer transistor TX2 and a second photoelectric conversion element PD2, the third pixel includes a third transfer transistor TX3 and a third photoelectric conversion element PD3, and the fourth pixel includes a fourth transfer transistor TX4 and a fourth photoelectric conversion element PD4. The gates of the first to fourth transfer transistors TX1 to TX4 are connected to first to fourth transmission gate lines TGL1 to TGL4, respectively. In this embodiment, the first to fourth pixels of pixel group PXLG share the reset transistor RX, source follower SFX, and selection transistor SX described above.

[0034] Referring to FIG. 3B, in this embodiment, pixel group PXLG includes four pixels, each of which includes two sub-pixels. Therefore, in this embodiment, pixel group PXLG includes first to eighth sub-pixels. The first to eighth sub-pixels include first to eighth transfer transistors TX1 to TX8 and first to eighth photoelectric conversion elements PD1 to PD8, respectively. The gates of the first to eighth transfer transistors TX1 to TX8 are connected to first to eighth transfer gate lines TGL1 to TGL8, respectively. In this embodiment, the first to eighth sub-pixels share the reset transistor RX, source follower SFX, and selection transistor SX described above.

[0035] 3A and 3B, each pixel group PXLG includes four pixels or eight sub-pixels, but embodiments of the present invention are not limited thereto, and the number of pixels and / or the number of sub-pixels in a pixel group PXLG may vary.

[0036] 4 is a cross-sectional view of an image sensor according to an embodiment of the present invention, and FIG 5 is an enlarged cross-sectional view of a first example of part 'A' in FIG 4.

[0037] 4, the image sensor according to this embodiment includes a photoelectric conversion structure 100 (also referred to herein as a photoelectric conversion array, a photoelectric converter, or a first structure). The photoelectric conversion structure 100 includes a first substrate 110, a photodiode 120, a first deep isolation pattern DTI1, a second deep isolation pattern DTI2, a first shallow isolation pattern STI1, a floating diffusion region FD, a transfer gate TG, a first gate insulating film 130, a grid 140, a light-transmitting film 150, a light-shielding pattern 160, a color filter CF, and a microlens ML.

[0038] The first substrate 110 has a first surface 111 and a second surface 113 facing the first surface 111. The first surface 111 is the front surface of the first substrate 110, and the second surface 113 is the back surface of the first substrate 110. Light is incident on the second surface 113 of the first substrate 110. For example, the second surface 113 of the first substrate 110 is a light incident surface.

[0039] The first substrate 110 is a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (Si-Ge) substrate, a II-VI compound semiconductor substrate, a III-V compound semiconductor substrate, or an SOI (Silicon On Insulator) substrate. The first substrate 110 contains impurities of a first conductivity type, and therefore has a first conductivity type. For example, the impurities of the first conductivity type are Group 3 elements. For example, the impurities of the first conductivity type include P-type impurities such as aluminum (Al), boron (B), indium (In), and / or gallium (Ga).

[0040] The photodiode 120 is provided in the first substrate 110. The photodiode 120 includes impurities having a second conductivity type different from the first conductivity type, and thus the photodiode 120 has the second conductivity type. For example, the impurities of the second conductivity type are Group 5 elements. For example, the impurities of the second conductivity type include n-type impurities such as phosphorus, arsenic, bismuth, and / or antimony.

[0041] The first substrate 110 and the photodiode 120 are PN junctioned with each other.

[0042] In this embodiment, first deep isolation patterns DTI1 are provided in the first substrate 110 to define pixel regions within the first substrate 110, and at least one photodiode 120 is provided within each of the pixel regions.

[0043] The first deep isolation pattern DTI1 penetrates the first substrate 110. For example, the first deep isolation pattern DTI1 penetrates the substrate body between the first and second surfaces (111, 113) of the first substrate 110 and the first and second surfaces (111, 113) of the first substrate 110.

[0044] The first deep isolation patterns DTI1 are formed in the first substrate 110 to surround each pixel region in a plan view. For example, the first deep isolation patterns DTI1 are formed by a technique of filling deep trenches formed by patterning the first substrate 110 with an insulating material (e.g., a deep trench isolation (DTI) technique). In this embodiment, the pixel region is a portion of the first substrate 110 surrounded by the first deep isolation patterns DTI1.

[0045] In one embodiment, the first deep device isolation pattern DTI1 includes a conductive isolation layer provided in the deep trench and an insulating liner provided between the first substrate 110 and the conductive isolation layer. The conductive isolation layer includes a conductive material such as a doped semiconductor material (e.g., doped polysilicon). The conductive isolation layer is separated from the first substrate 110 by the insulating liner, and therefore, is electrically isolated from the first substrate 110 during operation of the image sensor.

[0046] In this embodiment, each pixel region includes a pair of sub-pixel regions. In this case, a photodiode 120 is disposed within each of the pair of sub-pixel regions. For example, a pair of photodiodes 120 is disposed within each of the pair of sub-pixel regions. When each pixel region includes a pair of sub-pixel regions, each pixel region corresponds to one of the pixels in pixel group PXLG of FIG. 3B, and the corresponding pixel again includes two sub-pixels. For example, each sub-pixel of the pixels in pixel group PXLG of FIG. 3B is formed on and within each of the pixel regions.

[0047] The pair of subpixel regions may be separated by at least one of various isolation techniques. For example, the pair of subpixel regions may be separated from each other by a doping isolation technique. For example, a doped isolation region may be provided between the pair of subpixel regions. Alternatively, the pair of subpixel regions may be separated from each other by a doped isolation region and at least one deep isolation pattern. For example, a doped isolation region and at least one deep isolation pattern may be provided between the pair of subpixel regions. Alternatively, only at least one deep isolation pattern may be provided between the pair of subpixel regions (for example, without a doped isolation region).

[0048] In this embodiment, each pixel region includes a pair of sub-pixel regions, and a second deep isolation pattern DTI2 is provided between the pair of sub-pixel regions.

[0049] Although the above-described embodiment discloses a pixel region including a pair of sub-pixel regions, embodiments of the present invention are not limited thereto. In one embodiment, each pixel region may not include a sub-pixel region. In this case, each pixel PXL of FIG. 2 is formed on and within each pixel region of FIG. 4. For example, one photodiode 120 is formed within each pixel region. In one embodiment, pixels formed in four adjacent pixel regions share the logic transistors (RX, SFX, SX) described above. In this case, the pixel group PXLG of FIG. 3A is formed on and within four adjacent pixel regions. For ease of explanation, the following description will be given using a pixel region including a pair of sub-pixel regions as an example.

[0050] The first shallow isolation patterns STI1 are provided in the first substrate 110 to define active regions. The first shallow isolation patterns STI1 are adjacent to a first surface 111 of the first substrate 110. The first shallow isolation patterns STI1 are provided between the active regions to electrically isolate the active regions from each other. In one embodiment, the first shallow isolation patterns STI1 define at least one active region in each of the subpixel regions. If the pixel region does not include a subpixel region, the first shallow isolation patterns STI1 define at least one active region in each of the pixel regions.

[0051] In one embodiment, the first deep isolation pattern DTI1 partially overlaps the first shallow isolation pattern STI1. For example, the first deep isolation pattern DTI1 penetrates a portion of the first shallow isolation pattern STI1. The overlapping portion of the first deep isolation pattern DTI1 and the first shallow isolation pattern STI1 corresponds to a portion of the first shallow isolation pattern STI1 or a portion of the first deep isolation pattern DTI1.

[0052] The transfer gate TG is disposed on a first surface 111 of the first substrate 110. The transfer gate TG is disposed on a corresponding active region (hereinafter referred to as a first active region) of each sub-pixel region. A first gate insulating film 130 is disposed between the transfer gate TG and the first active region.

[0053] A floating diffusion region FD is provided in the first active region on one side of the transmission gate TG, and in one embodiment, the floating diffusion region FD is a region doped with impurities having the second conductivity type.

[0054] In one embodiment, gate spacers (not shown) are provided on the sides of the transfer gate TG. The gate spacers comprise a different insulating material than the first shallow isolation pattern STI1. For example, if the first shallow isolation pattern STI1 comprises silicon oxide, the gate spacers comprise silicon nitride and / or silicon oxynitride.

[0055] In one embodiment, a capping liner film (not shown) is disposed on the first surface 111 of the first substrate 110 to conformally cover the first surface 111, the first gate insulating film 130, the gate spacer, and the transfer gate TG.

[0056] The light-transmitting film 150 (also referred to as a light-transmitting layer) is provided on the second surface 113 of the first substrate 110. The light-transmitting film 150 covers the second surface 113 of the first substrate 110 and the top surfaces of the first and second deep device isolation patterns (DTI1, DTI2). The light-transmitting film 150 includes a transparent insulating material. For example, the light-transmitting film 150 transmits 80% or more, 90% or more, or 95% or more of incident light.

[0057] In this embodiment, the light-transmitting film 150 functions as a film that prevents light reflection (e.g., by including an anti-reflection film 151) and / or a film having a fixed charge. For example, when the light-transmitting film 150 is used as a film that prevents light reflection, the light-transmitting film 150 prevents light reflection so that light incident on the second surface 113 of the first substrate 110 can smoothly reach the photodiode 120, thereby improving the efficiency of light capture and conversion in the photoelectric conversion structure 100 of the present invention. For example, when the light-transmitting film 150 is used as a film having a fixed charge, the light-transmitting film 150 has a negative fixed charge. For example, the light-transmitting film 150 includes a film having a fixed charge and a film that prevents light reflection, which are stacked in this order.

[0058] In this embodiment, the light-transmitting film 150 has a single-layer or multi-layer structure. For example, the light-transmitting film 150 includes at least one of an anti-reflection film 151, a surface insulating film 153, and a capping film 155. However, the structure of the light-transmitting film 150 is not limited thereto, and in one embodiment, the light-transmitting film 150 may include other films in addition to the anti-reflection film 151, the surface insulating film 153, and the capping film 155.

[0059] Referring to FIG. 5 , the light-transmitting film 150 according to this embodiment includes an anti-reflective film 151, a surface insulating film 153, and a capping film 155. A portion of the anti-reflective film 151 is recessed to define a recess region RR, and thus the anti-reflective film 151 includes a recess region RR (also referred to as an opening). A portion of the anti-reflective film 151 has a recessed opening or a hole penetrating therethrough, which defines an opening region, which is the recess region RR. Thus, the anti-reflective film 151 includes a recess region RR. In the drawing, the opening region indicated by the recess region RR is shown as a hole penetrating the anti-reflective film 151 completely, but it is actually a recess that does not completely penetrate the anti-reflective film 151, and the recess region RR is described as an example of the embodiment discussed herein. A plurality of holes or recesses forms an opening pattern including a plurality of openings (e.g., a plurality of recesses or a plurality of holes).

[0060] The anti-reflection coating 151 (also referred to as an anti-reflection portion or anti-reflection film) is disposed on the second surface 113 of the first substrate 110, and the surface insulating film 153 is disposed between the anti-reflection coating 151 and the second surface 113 of the first substrate 110. The capping film 155 covers the upper surface of the anti-reflection coating 151 and the upper surface of the light shielding pattern 160. In one embodiment, the anti-reflection coating 151 prevents light reflection, and in another embodiment, the anti-reflection coating 151 prevents light reflection to improve light capture and conversion efficiency. The anti-reflection coating 151 reduces reflection (e.g., through refractive index adjustment, thickness adjustment, or textured surface treatment), or the anti-reflection coating 151 includes one or more materials with low reflectivity. In one embodiment, the anti-reflection coating 151 includes an oxide or nitride including at least one of silicon or hafnium. For example, the anti-reflection coating 151 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, or hafnium nitride. In one embodiment, a light shielding pattern 160 is provided in the anti-reflection coating 151 .

[0061] The light shielding pattern 160 (also referred to as a light-shielding portion) is formed in the light-transmitting film 150. According to an embodiment, the light shielding pattern 160 fills the recess region RR of the anti-reflection film 151. In an embodiment, the light shielding pattern 160 has at least one of a light absorbing function, a light reflecting function, and a light blocking function. In an embodiment, the light shielding pattern 160 is disposed on a specific pixel region among the pixel regions. For example, the light shielding pattern 160 is selectively disposed on a pixel region included in an autofocus pixel (hereinafter also referred to as an autofocus pixel region). For example, the light shielding pattern 160 covers at least a portion of one of a pair of subpixel regions of the autofocus pixel region. For example, the light shielding pattern 160 vertically overlaps at least a portion of one of a pair of subpixel regions of the autofocus pixel region.

[0062] The light shielding pattern 160 (light-shielding pattern) is configured to reduce the amount of light (e.g., by absorbing, reflecting, and / or blocking light). In various examples, the light shielding pattern 160 absorbs, reflects, and / or blocks 50% or more, 80% or more, 90% or more, or 95% or more of incident light. In one embodiment, the light shielding pattern 160 includes a metal-containing material, a metal nitride, a low-refractive material, or an organic material. For example, the light shielding pattern 160 includes at least one of aluminum, titanium, titanium nitride, tungsten, tantalum, tantalum nitride, aluminum oxide, tantalum oxide, copper, molybdenum, nickel, a red organic material, a green organic material, a blue organic material, a cyan organic material, a magenta organic material, a yellow organic material, a black organic material, or a gray organic material.

[0063] In one embodiment, when the light shielding pattern 160 includes an organic material, the light shielding pattern 160 is formed of an organic material that absorbs light that passes through the color filter CF. For example, when the color filter CF passes red wavelength light, the light shielding pattern 160 includes at least one of a green organic material, a blue organic material, a cyan organic material, a black organic material, or a gray organic material. For example, when the color filter CF passes blue wavelength light, the light shielding pattern 160 includes at least one of a green organic material, a red organic material, a yellow organic material, a black organic material, or a gray organic material. Furthermore, when the color filter CF passes green wavelength light, the light shielding pattern 160 includes at least one of a blue organic material, a red organic material, a magenta organic material, a black organic material, or a gray organic material.

[0064] 5 , the recess region RR penetrates the anti-reflection film 151, and the light shielding pattern 160 contacts the surface insulating film 153 and the capping film 155. However, embodiments of the present invention are not limited thereto. In one embodiment, the light shielding pattern 160 may be spaced apart from the surface insulating film 153 and contact the capping film 155. In one embodiment, the light shielding pattern 160 may contact the surface insulating film 153 and be spaced apart from the capping film 155. In one embodiment, the light shielding pattern 160 may be spaced apart from both the surface insulating film 153 and the capping film 155.

[0065] In one embodiment, the surface insulating film 153 has at least one of the functions of a film that prevents light reflection, a film that has a negative fixed charge, and a film that prevents etching. In one embodiment, the surface insulating film 153 includes a metal oxide or a metal fluoride including at least one of aluminum, hafnium, zirconium, lanthanum, titanium, tantalum, and yttrium. For example, the surface insulating film 153 includes at least one of an aluminum oxide film, a hafnium oxide film, a zirconium oxide film, a lanthanum oxide film, a hafnium silicon oxide film, a hafnium aluminum oxide film, a titanium oxide film, and a tantalum oxide film.

[0066] As described above, the capping film 155 is provided on the anti-reflection film 151 to cover the anti-reflection film 151 and the light-shielding pattern 160. For example, the surface insulating film 153, the anti-reflection film 151, and the light-shielding pattern 160 are disposed between the second surface 113 of the first substrate 110 and the capping film 155. In one embodiment, the capping film 155 has at least one of a function of preventing light reflection and a function of preventing etching. For example, the capping film 155 includes at least one of a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, a hafnium oxide film, a zirconium oxide film, a lanthanum oxide film, a hafnium silicon oxide film, a hafnium aluminum oxide film, a titanium oxide film, or a tantalum oxide film.

[0067] The grid 140 is provided on the second surface 113 of the first substrate 110 via a light-transmitting film 150. For example, the grid 140 is provided on the light-transmitting film 150. The grid 140 defines openings. A color filter array including two-dimensionally arranged color filters CF is provided on the second surface 113 of the first substrate 110. The color filter array is provided on the light-transmitting film 150, and each of the color filters CF fills a corresponding opening in the grid 140. A lens array including two-dimensionally arranged microlenses ML is provided on the second surface 113 of the first substrate 110 via the color filter array. For example, the color filter array is disposed between the lens array and the light-transmitting film 150.

[0068] In this embodiment, each color filter CF covers a corresponding pixel region among the pixel regions. For example, each color filter CF is disposed over four pixel regions arranged in a 2x2 matrix in plan view. For example, each color filter CF covers a pair of adjacent pixel region groups. However, the embodiment of the present invention is not limited thereto. For example, each color filter CF is disposed over nine pixel regions arranged in a 3x3 matrix in plan view, and over 16 pixel regions arranged in a 4x4 matrix in plan view.

[0069] In one embodiment, the color filters CF include a first color filter having a first color, a second color filter having a second color, and a third color filter having a third color. For example, each of the color filters CF may have one of red, green, or blue. Alternatively, each of the color filters CF may have one of cyan, magenta, or yellow. The color filters CF may have colors other than the above-mentioned red, green, blue, cyan, magenta, or yellow.

[0070] The grid 140 guides incident light into the photodiode 120. The grid 140 may have a single-layer structure or a multi-layer structure. The grid 140 may include a metal-containing material (e.g., titanium, tungsten, aluminum, tantalum, etc.), a metal nitride (e.g., titanium nitride, tantalum nitride, etc.), and / or a low refractive index material. A low refractive index material refers to a material with a low refractive index lower than that of silicon (Si). In one embodiment, the low refractive index material includes a metal oxide, or a polymer and silica nanoparticles within the polymer. For example, the low refractive index material may include at least one of silicon oxide, aluminum oxide, tantalum oxide, or silicon hydrogen oxycarbide. In one embodiment, the low refractive index material has insulating properties.

[0071] In one embodiment, the grid 140 vertically overlaps at least the first deep isolation pattern DTI1. In one embodiment, although not shown, the grid 140 also vertically overlaps the second deep isolation pattern DTI2. However, embodiments of the present invention are not limited thereto. In one embodiment, when the grid 140 is shifted laterally, at least a portion of the grid 140 does not vertically overlap the first and second deep isolation patterns DTI1 and DTI2. For example, the grid 140 has a structure that is laterally offset from the first and second deep isolation patterns DTI1 and DTI2. The offset structure may be intentionally selected to optimize the optical path in consideration of the manufacturing process margin and / or the angle of propagation of the incident light.

[0072] The microlenses ML are disposed on the light-transmitting film 150 via the color filters CF. At least a portion of the microlenses ML vertically overlaps the photodiodes 120. The microlenses ML focus incident light toward the first substrate 110. In one embodiment, the microlenses ML include an organic material such as a polymer. For example, the microlenses ML include a light-transmitting resin, a photoresist material, or a thermosetting resin.

[0073] In this embodiment, the microlens ML includes a lens pattern and a planarizing portion. The planarizing portion is provided on the color filter CF, and the lens pattern is provided on the planarizing portion. The lens pattern may include the same material as the planarizing portion. The lens pattern and the planarizing portion may form a single body without an interface therebetween. In one embodiment, the planarizing portion may be omitted, and the lens pattern may be disposed directly on the color filter CF.

[0074] In this embodiment, the microlenses ML cover each pixel region. For example, each microlens ML vertically overlaps a corresponding one of the pixel regions. Therefore, each microlens ML covers a pair of subpixel regions included in the corresponding pixel region. Each microlens ML vertically overlaps a pair of photodiodes 120 formed in the pair of subpixel regions. In one embodiment, all of the microlenses ML in the lens array vertically overlap a corresponding one of the pixel regions. Each microlens ML is provided to focus incident light and includes a spherical lens, an aspherical lens, or a combination thereof. For example, each microlens ML has a convex shape in a cross-sectional view.

[0075] As described above, a pair of subpixels is formed within and on a pair of subpixel regions of a pixel region covered by each of the microlenses ML. For example, the pair of subpixels is covered by the same color filter CF. In one embodiment, the pair of subpixels can perform not only a photoelectric conversion function of converting an optical signal into an electrical signal but also an autofocus function. For example, the pair of subpixels detects a phase difference between light incident through the corresponding microlenses ML, and the autofocus function is performed using the detected phase difference data.

[0076] According to the image sensor of the above-described embodiment, a recess region RR is formed in the light-transmitting film 150 or the anti-reflective film 151, and the light-shielding pattern 160 fills the recess region RR. In this case, the light-shielding pattern 160 is selectively disposed over an autofocus pixel region within a pixel region to cover at least a portion of one of a pair of subpixel regions of the autofocus pixel region. Therefore, the light-absorbing or light-blocking light-shielding pattern 160 can be selectively provided to the autofocus pixel (AF pixel), and the light-absorbing or light-blocking structure can be minimized in the non-AF pixels. For example, the amount of light incident on the autofocus pixel is partially restricted to detect the phase difference of the incident light for autofocus. At the same time, the light-shielding pattern 160 is not provided over non-autofocus (e.g., standard) pixels, or the light-transmitting film 150 or the anti-reflective film 151 is provided over the non-autofocus (e.g., standard) pixels. Therefore, the amount of light incident on the non-autofocus pixels can be increased and the loss of light incident on the non-autofocus pixels can be minimized. As a result, the quantum efficiency (QE) of the image sensor can be improved.

[0077] For example, external light can interfere with the function of autofocus pixels (AF pixels), while additional incident light can improve the efficiency and / or performance of non-autofocus pixels (non-AF pixels). For example, if there is too much incident light, it may be difficult for the AF pixels to accurately sense the phase difference of the light. Therefore, as described above, the light shielding pattern 160 may be selectively provided on the AF pixels to minimize the structure that absorbs or blocks light in the non-AF pixels.

[0078] 6 and 7 are enlarged cross-sectional views of a second and third example of an image sensor according to an embodiment of the present invention, corresponding to part 'A' in FIG. 4. For ease of explanation, differences from the above-described embodiments will be mainly described below.

[0079] 6 and 7, the light shielding pattern 160 and the anti-reflection film 151 are disposed on the surface insulating film 153, and the capping film 155 is disposed on the anti-reflection film 151 and the light shielding pattern 160. In the present embodiment, the thickness of the light shielding pattern 160 is different from the thickness of the anti-reflection film 151. The thicknesses of the light shielding pattern 160 and the anti-reflection film 151 according to an embodiment are adjusted by varying the selectivity in the process of planarizing the light shielding pattern 160 and the anti-reflection film 151, and the thicknesses of the light shielding pattern 160 and / or the anti-reflection film 151 are not limited as they may be appropriately adjusted as needed.

[0080] 6, the thickness of the light shielding pattern 160 is thicker than the thickness of the anti-reflection film 151. For example, the thickness of the anti-reflection film 151 is thinner than the thickness of the light shielding pattern 160. In this case, the capping film 155 is formed after the light shielding pattern 160 is formed. Therefore, a portion of the capping film 155 has a step, and the level (vertical height) of the upper surface of the capping film 155 on the light shielding pattern 160 is higher than the level of the upper surface of the capping film 155 on the anti-reflection film 151. Therefore, although a portion of the grid 140 has a step as shown in FIG. 6, the present invention is not limited thereto.

[0081] 7, the thickness of the light shielding pattern 160 is thinner than the thickness of the anti-reflection film 151. For example, the thickness of the anti-reflection film 151 is thicker than the thickness of the light shielding pattern 160. In this case, the capping film 155 is formed after the light shielding pattern 160 is formed. Therefore, a portion of the capping film 155 has a step, and the level of the upper surface of the capping film 155 on the light shielding pattern 160 is lower than the level of the upper surface of the capping film 155 on the anti-reflection film 151. Therefore, although a portion of the grid 140 has a step as shown in FIG. 7, the present invention is not limited thereto.

[0082] 8 to 10 are enlarged cross-sectional views of fourth to sixth examples of an image sensor according to an embodiment of the present invention, which correspond to part 'A' in FIG.

[0083] 8 , the recess region RR extends into the surface insulating film 153. For example, the recess region RR penetrates at least a portion of the anti-reflection film 151 and the surface insulating film 153, and the anti-reflection film 151 and the surface insulating film 153 include the recess region RR. Therefore, the light shielding pattern 160 is provided in the anti-reflection film 151 and the surface insulating film 153. In this embodiment, the recess region RR also penetrates the surface insulating film 153. Therefore, the lower portion of the light shielding pattern 160 filling the recess region RR protrudes below the lower surface of the anti-reflection film 151, the surface insulating film 153 surrounds the side of the lower portion of the light shielding pattern 160, and the lower surface of the light shielding pattern 160 is substantially coplanar with the lower surface of the surface insulating film 153.

[0084] 8 is illustrated as being in contact with the second surface 113 of the first substrate 110 and the capping film 155, this is not limiting. In one embodiment, the light shielding pattern 160 may be in contact with one of the second surface 113 of the first substrate 110 and the capping film 155 and spaced apart from the other. In another embodiment, the light shielding pattern 160 may be spaced apart from the second surface 113 of the first substrate 110 and the capping film 155.

[0085] 9, the recess region RR extends into the capping film 155. For example, the recess region RR penetrates the anti-reflection film 151 and the capping film 155, and the light shielding pattern 160 fills the recess region RR. Thus, the light shielding pattern 160 is provided within the anti-reflection film 151 and the capping film 155. The upper portion of the light shielding pattern 160 protrudes above the upper surface of the anti-reflection film 151, the capping film 155 surrounds the side of the upper portion of the light shielding pattern 160, and the upper surface of the light shielding pattern 160 is substantially coplanar with the upper surface of the capping film 155.

[0086] 9 is illustrated as being in contact with the grid 140, the color filter CF, and the surface insulating film 153, this is not limiting. In one embodiment, the light shielding pattern 160 may be in contact with one of the color filter CF and the surface insulating film 153 and spaced apart from the other. In another embodiment, the light shielding pattern 160 may be spaced apart from the grid 140, the color filter CF, and the surface insulating film 153.

[0087] 10, the recess region RR extends into the surface insulating film 153 and the capping film 155. For example, the recess region RR penetrates at least a portion of the capping film 155, the anti-reflection film 151, and the surface insulating film 153. Therefore, the light shielding pattern 160 is provided in the anti-reflection film 151, the surface insulating film 153, and the capping film 155. In this case, the lower portion of the light shielding pattern 160 protrudes below the lower surface of the anti-reflection film 151, like the lower portion of the light shielding pattern 160 in FIG. 8, and the upper portion of the light shielding pattern 160 protrudes above the upper surface of the anti-reflection film 151, like the upper portion of the light shielding pattern 160 in FIG. 9.

[0088] 10 is illustrated as being in contact with the grid 140, the color filters CF, and the second surface 113 of the first substrate 110, but is not limited thereto. In one embodiment, the light shielding pattern 160 may be in contact with one of the color filters CF and the second surface 113 and spaced apart from the other one. In another embodiment, the light shielding pattern 160 may be spaced apart from the grid 140, the color filters CF, and the second surface 113.

[0089] 11 to 13 are enlarged cross-sectional views of seventh to ninth examples of an image sensor according to an embodiment of the present invention, which correspond to part 'A' in FIG.

[0090] 11 to 13, the position and / or width of the light shielding pattern 160 may be appropriately changed as needed. As described above, when the grid 140 is shifted laterally along the path of the incident light, the position of the light shielding pattern 160 is changed. For example, the horizontal position of the light shielding pattern 160 is changed in proportion to the distance by which the grid 140 is shifted laterally from the first deep isolation pattern DTI1.

[0091] The light shielding pattern 160 of FIG. 5 covers one of a pair of subpixel regions and the first and second deep isolation patterns (DTI1, DTI2) on both sides of the one subpixel region, whereas the shifted light shielding pattern 160 of FIG. 11 does not vertically overlap the first deep isolation pattern DTI1, but vertically overlaps one of the pair of subpixel regions and a portion of the other of the pair of subpixel regions.

[0092] The shifted light shielding pattern 160 in Figure 12 covers one of a pair of subpixel regions but not the other of the pair of subpixel regions. The horizontal width of the light shielding pattern 160 in Figure 12 is narrower than the horizontal width of the light shielding pattern 160 in Figure 11. The shifted light shielding pattern 160 in Figure 13 covers at least a portion of the first deep device isolation pattern DTI1, one of the pair of subpixel regions, and a portion of the other of the pair of subpixel regions. The width of the light shielding pattern 160 in Figure 13 is wider than the width of the light shielding pattern 160 in Figure 11. As a result, the horizontal position of the light shielding pattern 160 is changed according to the degree to which the grid 140 is shifted, and the width of the light shielding pattern 160 is appropriately adjusted as needed.

[0093] FIG. 14 is an enlarged cross-sectional view of a tenth example of an image sensor according to an embodiment of the present invention, corresponding to part 'A' in FIG.

[0094] FIG. 14 shows adjacent autofocus pixel regions. Referring to FIG. 14, in this embodiment, one photodiode 120 is provided in each pixel region. For example, unlike the above-described embodiment, the pixel region does not include a pair of subpixel regions and a second deep isolation pattern between them. Here, the light shielding pattern 160 covers a portion of at least one of the pixel regions. For example, the light shielding pattern 160 covers a portion of the autofocus pixel region. As described above, one photodiode 120 is provided in the autofocus pixel region, and the light shielding pattern 160 covers a portion of the photodiode 120 in the autofocus pixel region. The light shielding pattern 160 is one of the light shielding patterns 160 in FIGS. 5 to 13.

[0095] The autofocus pixel area is divided into a left side and a right side based on an imaginary center line CL that passes through the center of the photodiode 120 and is perpendicular to the second surface 113. In this embodiment, as shown in FIG. 14 , the light shield pattern 160 covers the left side of the autofocus pixel area. However, this embodiment is not limited to this. In one embodiment, the light shield pattern 160 can also cover the right side of the autofocus pixel area. In one embodiment, the pixel area includes multiple autofocus pixel areas, and one light shield pattern 160 can cover the left side of at least one of the autofocus pixel areas, and another light shield pattern 160 can cover the right side of at least another of the autofocus pixel areas.

[0096] 15 to 19 are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment of the present invention, and are enlarged cross-sectional views corresponding to part 'A' in FIG.

[0097] Referring to FIG. 15, a first substrate 110 having first and second surfaces (111, 113) is prepared, and first and second deep isolation patterns (DTI1, DTI2) are formed in the first substrate 110. The first deep isolation pattern DTI1 defines a pixel region, and the second deep isolation pattern DTI2 is formed between a pair of subpixel regions in the pixel region. A photodiode 120 is formed in each of the subpixel regions using an ion implantation process. In one embodiment, the photodiode 120 is formed before or after the formation of the first and second deep isolation patterns (DTI1, DTI2). Various components (e.g., transfer gates TG, floating diffusion regions FD, interlayer insulating films, wiring, etc.) are then formed on the first surface 111 of the first substrate 110. The first substrate 110 is then bonded to another substrate, and the second surface 113 of the first substrate 110 is then planarized. In one embodiment, a surface insulating film 153 is formed on the planarized second surface 113 of the first substrate 110 , and an anti-reflection film 151 is formed on the surface insulating film 153 .

[0098] 16, a mask pattern (not shown) is formed on the anti-reflective coating 151. The mask pattern has openings that define recess regions RR (or openings). The openings expose portions of the anti-reflective coating 151. The anti-reflective coating 151 is etched using the mask pattern as an etching mask to form recess regions RR in the anti-reflective coating 151.

[0099] In this embodiment, the etching process for forming the recess region RR is performed until the surface insulating film 153 is exposed. In this case, the exposed surface of the surface insulating film 153 corresponds to the bottom surface of the recess region RR. In this embodiment, the level of the bottom surface of the recess region RR (e.g., the vertical height) is substantially the same as the level of the upper surface of the surface insulating film 153 or the lower surface of the anti-reflective film 151. However, embodiments of the present invention are not limited thereto. In one embodiment, if the etching process is stopped before the surface insulating film 153 is exposed or includes over-etching, the level of the bottom surface of the recess region RR will be different from the level of the upper surface of the surface insulating film 153 or the lower surface of the anti-reflective film 151.

[0100] The mask pattern is removed after the recess region RR is formed. As described above, the level of the bottom surface of the recess region RR is substantially the same as the level of the upper surface of the surface insulating film 153 or the lower surface of the anti-reflection film 151.

[0101] 17, a light shielding film 161 is formed on the anti-reflection film 151 having a recess region RR. The light shielding film 161 fills the recess region RR. For example, the light shielding film 161 is formed using a deposition process. In one embodiment, the light shielding film 161 includes a metal-containing material, a metal nitride, a low refractive index material, or an organic material. For example, the light shielding film 161 is formed of at least one of aluminum, titanium, titanium nitride, tungsten, tantalum, tantalum nitride, aluminum oxide, tantalum oxide, copper, molybdenum, nickel, a red organic material, a green organic material, a blue organic material, a cyan organic material, a magenta organic material, a yellow organic material, a black organic material, or a gray organic material.

[0102] Referring to FIG. 18, a planarization process is performed on the light shielding film 161 to form a light shielding pattern 160. As shown in FIG.

[0103] In this embodiment, the top surface of the light shielding pattern 160 is substantially coplanar with the top surface of the anti-reflection film 151. In this case, the planarization process is performed until the anti-reflection film 151 is exposed. Thus, the image sensor shown in FIG. 5 is manufactured.

[0104] Alternatively or additionally, the process may be appropriately modified to manufacture an image sensor shown in one of the embodiments of Figures 6 to 14. For example, in one embodiment, the thickness of the light shielding pattern 160 is formed to be thicker than the thickness of the anti-reflection film 151. In this case, the planarization process is performed until the anti-reflection film 151 is exposed, and an additional etching process is performed on the exposed anti-reflection film 151. Therefore, the top surface of the etched anti-reflection film 151 is lower than the top surface of the light shielding pattern 160, and the image sensor shown in Figure 6 is manufactured.

[0105] In one embodiment, the thickness of the light shielding pattern 160 is formed thinner than the thickness of the anti-reflection film 151. In this case, the planarization process includes a process of over-etching the light shielding film 161 after exposing the anti-reflection film 151. Therefore, the top surface of the light shielding pattern 160 is lower than the top surface of the anti-reflection film 151, and the image sensor shown in FIG. 7 is manufactured.

[0106] 19, a capping film 155 is formed on the anti-reflection film 151 and the light shielding pattern 160. Then, the grid 140, color filters CF, and microlenses ML shown in FIG.

[0107] In one embodiment, the image sensors of FIGS. 8 to 10 are manufactured by modifying the patterning process for forming the recess region RR (i.e., the process for forming a mask pattern and the etching process using the mask pattern as an etching mask). In one embodiment, the anti-reflective film 151 and the surface insulating film 153 are etched during the etching process described with reference to FIG. 16 . Thus, the image sensor of FIG. 8 is manufactured. In one embodiment, the patterning process for forming the recess region RR is performed after the formation of the capping film 155, and the capping film 155 and the anti-reflective film 151 are etched by the etching process of the patterning process. Thus, the image sensor of FIG. 9 is manufactured. In one embodiment, the patterning process is performed after the formation of the capping film 155, and the capping film 155, the anti-reflective film 151, and the surface insulating film 153 are etched by the etching process of the patterning process. Thus, the image sensor of FIG. 10 is manufactured.

[0108] FIG. 20 is an enlarged cross-sectional view of an eleventh example of an image sensor according to an embodiment of the present invention, corresponding to part 'A' in FIG.

[0109] Referring to FIG. 20 , a light shielding pattern 160 is formed on the autofocus pixel AF PXL but not on the general pixel PXL. The light shielding pattern 160 absorbs or blocks a portion of the light incident through the microlens ML, thereby reducing the amount of light incident on a certain region. As described above, external light interferes with the function of the autofocus pixel. For example, it interferes with sensing the phase difference of light, but the additional incident light improves the efficiency and / or performance of non-autofocus pixels. Therefore, the autofocus pixel AF PXL detects the phase difference of the incident light, and the autofocus function is performed using the detected phase difference data. As a result, because the light shielding pattern 160 is not formed on the general pixel PXL, the loss of the amount of light incident on the general pixel PXL can be minimized. This can improve the quantum efficiency (QE) of the image sensor.

[0110] FIG. 21 is a cross-sectional view of an image sensor having a stacked structure according to an embodiment of the present invention.

[0111] Referring to FIG. 21, the image sensor according to this embodiment includes first and second structures (100, 200). The first structure 100 is stacked on the second structure 200. That is, the image sensor according to this embodiment has a stacked structure. The first structure 100 is also referred to as a photoelectric conversion structure. The second structure 200 is also referred to as a peripheral circuit structure. For example, the second structure 200 includes a circuit for processing pixel data as an image. The first structure 100 and the second structure 200 are bonded to each other by at least one of various bonding methods and electrically connected to each other by at least one of various connection methods.

[0112] The first structural body 100 includes a light control layer 20, a photoelectric conversion layer 10, and a first wiring layer 30a. The photoelectric conversion layer 10 is disposed between the light control layer 20 and the first wiring layer 30a.

[0113] The light control layer 20 includes the microlenses ML, color filters CF, grids 140, light-transmitting films 150, and light shielding patterns 160 shown in Fig. 5. The photoelectric conversion layer 10 includes the first substrate 110, photodiodes 120, first deep element isolation patterns DTI1, second deep element isolation patterns DTI2, first shallow element isolation patterns STI1, floating diffusion regions FD, first gate insulating films 130, and transfer gates TG shown in Fig. 4. The first wiring layer 30a includes a first interlayer insulating film 170, first contact plugs 180, first wiring 190, and first bonding pads 410.

[0114] The first interlayer insulating film 170 is provided on the first surface 111 of the first substrate 110. The first interlayer insulating film 170 covers the first surface 111, the floating diffusion region FD, and the transfer gate. For example, each of the first interlayer insulating films 170 includes at least one of silicon oxide, silicon oxynitride, or silicon nitride. In this embodiment, the first interlayer insulating film 170 is sequentially stacked on the first surface 111 of the first substrate 110. The first contact plug 180 and the first wiring 190 are provided in the first interlayer insulating film 170.

[0115] The first bonding pad 410 is disposed in the first interlayer insulating film 175 , which is the lowest layer in the first interlayer insulating film 170 .

[0116] The second structure 200 includes a peripheral circuit layer 40 and a second wiring layer 30b.

[0117] The peripheral circuit layer 40 includes a second substrate 210, a second shallow element isolation pattern STI2, a second gate insulating film 230, and a peripheral circuit gate MxG, and the second wiring layer 30b includes a second interlayer insulating film 270, a second contact plug 280, a second wiring 290, and a second bonding pad 420.

[0118] The second substrate 210 has a third surface 211 and a fourth surface 213 facing the third surface 211. The third surface 211 is the front surface of the second substrate 210, and the fourth surface 213 is the back surface of the second substrate 210. The second shallow isolation pattern STI2 is disposed in a shallow trench recessed to a specific depth from the third surface 211 of the second substrate 210.

[0119] The second shallow isolation patterns STI2 define active regions in the second substrate 210. The second shallow isolation patterns STI2 are adjacent to a third surface 211 of the second substrate 210.

[0120] The peripheral circuit gates MxG are disposed on corresponding active regions of the second substrate 210. In this embodiment, the peripheral circuit gates MxG are disposed on the third surface 211 of the second substrate 210. A second gate insulating film 230 is disposed between the peripheral circuit gates MxG and the corresponding active regions. Peripheral circuit source / drain regions are disposed in the corresponding active regions on both sides of each of the peripheral circuit gates MxG.

[0121] The second interlayer insulating film 270 is disposed on the third surface 211 of the second substrate 210 and covers the third surface 211, the second gate insulating film 230, and the peripheral circuit gate MxG. The second interlayer insulating film 270 is stacked in order on the third surface 211 of the second substrate 210. A second contact plug 280 and a second wiring 290 are provided in the second interlayer insulating film 270. The second bonding pad 420 is disposed in a second interlayer insulating film 275, which is the uppermost layer of the second interlayer insulating film 270.

[0122] The first and second bonding pads 410 and 420 electrically connect the first and second structures 100 and 200. In this embodiment, the first and second bonding pads 410 and 420 are bonded to each other to electrically connect the first structure 100 and the second structure 200. In one embodiment, the first and second bonding pads 410 and 420 include copper. The first and second bonding pads 410 and 420 are bonded to each other using a copper-copper bonding technique. The bonded bonding pads 410 and 420 may be integral with each other without an interface therebetween. In one embodiment, the bottom first interlayer insulating film 175 is bonded to the top second interlayer insulating film 275 through a covalent bond.

[0123] FIG. 22 is a cross-sectional view of an image sensor having a multi-layer structure according to an embodiment of the present invention.

[0124] 22, the image sensor according to this embodiment includes first to third structures (100, 200, 300). The first structure 100 is stacked on the third structure 300, which is stacked on the second structure 200. For example, the third structure 300 is disposed between the first structure 100 and the second structure 200. The third structure 300 is referred to as an intermediate structure. The first structure 100 and the second structure 200 are bonded to each other by at least one of various bonding methods and are electrically connected to each other by at least one of various connecting methods. The second structure 200 and the third structure 300 are bonded to each other by at least one of various bonding methods and are electrically connected to each other by at least one of various connecting methods.

[0125] The third structural body 300 includes an intermediate layer 50, a third wiring layer 30c, and a fourth wiring layer 30d. The intermediate layer 50 is disposed between the third wiring layer 30c and the fourth wiring layer 30d.

[0126] The intermediate layer 50 includes a third substrate 310, a third shallow isolation pattern STI3, a third gate insulating film 330, and a gate. The third wiring layer 30c includes at least one of the third interlayer insulating films 370, a third contact plug 380, a third wiring 390, and a third bonding pad 430. The fourth wiring layer 30d includes at least another of the third interlayer insulating films 370 and a fourth bonding pad 440.

[0127] The third substrate 310 has a fifth surface 311 and a sixth surface 313 opposite to the fifth surface 311. The fifth surface 311 is the front surface of the third substrate 310, and the sixth surface 313 is the back surface of the third substrate 310. Conversely, the fifth surface 311 may be the back surface of the third substrate 310, and the sixth surface 313 may be the front surface of the third substrate 310.

[0128] The third shallow isolation pattern STI3 is disposed in a shallow trench recessed to a specific depth from the fifth surface 311 of the third substrate 310. The third shallow isolation pattern STI3 defines an active region within the third substrate 310. In this embodiment, the third shallow isolation pattern STI3 is adjacent to the fifth surface 311 of the third substrate 310.

[0129] Gates (e.g., reset gate, select gate, source follower gate SFG, etc.) are disposed on corresponding active regions of the third substrate 310. In this embodiment, the reset gate, select gate, and source follower gate SFG are disposed on a fifth surface 311 of the third substrate 310. A third gate insulating film 330 is disposed between the active regions corresponding to each of the reset gate, select gate, and source follower gate SFG. Source / drain regions are disposed in the corresponding active regions on both sides of each of the gates.

[0130] At least one of the third interlayer insulating films 370 is disposed on the fifth surface 311 of the third substrate 310 and covers the fifth surface 311, the third gate insulating film 330, the reset gate, the select gate, and the source follower gate SFG. In this embodiment, a plurality of third interlayer insulating films 370 are stacked in order on the fifth surface 311 of the third substrate 310. At least another of the third interlayer insulating films 370 is disposed on the sixth surface 313 of the third substrate 310. For example, the lowest third interlayer insulating film 377 among the third interlayer insulating films 370 is disposed on the sixth surface 313 of the third substrate 310. A third contact plug 380 and a third wiring 390 are provided in the third interlayer insulating film 370.

[0131] The third bonding pad 430 is disposed in the third interlayer insulating film 375, which is the top layer of the third interlayer insulating film 370, and the fourth bonding pad 440 is disposed in the third interlayer insulating film 377, which is the bottom layer of the third interlayer insulating film 370.

[0132] The first to fourth bonding pads (410, 420, 430, 440) electrically connect the first to third structures (100, 200, 300). In this embodiment, the first bonding pad 410 and the third bonding pad 430 are bonded to each other to electrically connect the first structure 100 and the third structure 300. In this embodiment, the second bonding pad 420 and the fourth bonding pad 440 are bonded to each other to electrically connect the second structure 200 and the third structure 300.

[0133] In one embodiment, the third structure 300 may be bonded differently than that shown in FIG. 22 . For example, the third structure 300 may be inverted (e.g., mirrored), inverted (e.g., mirrored), or rotated 180°. For example, the first bonding pad 410 and the fourth bonding pad 440 may be bonded to each other to electrically connect the first structure 100 and the third structure 300. For example, the second bonding pad 420 and the third bonding pad 430 may be bonded to each other to electrically connect the second structure 200 and the third structure 300.

[0134] In one embodiment, the third and fourth bonding pads 430 and 440 include copper, like the first and second bonding pads 410 and 420. Pads bonded to each other among the first through fourth bonding pads 410, 420, 430, and 440 are bonded using copper-to-copper bonding technology, and for example, the bonded pads can be integrally formed without an interface between them.

[0135] In this embodiment, the bonded insulating films among the first to third interlayer insulating films (170, 270, 370) are bonded to each other by covalent bonds. For example, the first interlayer insulating film 175, which is the lowest layer in the first interlayer insulating film 170, is bonded to the third interlayer insulating film 375, which is the highest layer in the third interlayer insulating film 370. For example, the second interlayer insulating film 275, which is the highest layer in the second interlayer insulating film 270, is bonded to the third interlayer insulating film 377, which is the lowest layer in the third interlayer insulating film 370.

[0136] In one embodiment, when the third structure 300 is bonded by being vertically inverted (e.g., reflected) (not shown, upside down, upside down, left and right, rotated 180 degrees, etc.), the first interlayer insulating film 175 at the bottom of the first interlayer insulating film 170 is bonded to the third interlayer insulating film 377 at the top of the third interlayer insulating film 370, and the second interlayer insulating film 275 at the top of the second interlayer insulating film 270 is bonded to the third interlayer insulating film 375 at the bottom of the third interlayer insulating film 370.

[0137] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0138] 1 pixel array Two-line decoder 3-row driver 4-row decoder 5 Timing Generator 6. Correlated Double Sampler (CDS) 7 Analog-to-Digital Converter (ADC) 8 Input / Output Buffers 10 Photoelectric conversion layer 20 Light control layer 30a, 30b, 30c, 30d 1st to 4th wiring layer 40 Peripheral Circuit Layer 50 Middle Class 100 First structure (photoelectric conversion structure) (photoelectric conversion array or photoelectric converter) 110, 210, 310 1st to 3rd boards 111, 113, 211, 213, 311, 313 1st to 6th sides 120 photodiode 130, 230, 330 First to third gate insulating films 140 Grid (grid pattern) 150 Light transmitting film (light transmitting layer) 151 Anti-reflection coating (anti-reflection part) (anti-reflection film) 153 Surface insulating film 155 Capping membrane 160 Light shield pattern (light shielding part) (light shielding pattern) 161 Light shielding film 170, 270, 370 1st to 3rd interlayer insulating films 175 Bottom layer first interlayer insulating film 180, 280, 380 1st to 3rd contact plugs 190, 290, 390 1st to 3rd wiring 200 Second structure (peripheral circuit structure) 275 Second interlayer insulating film on the top layer 300 Third structure (intermediate structure) 375 Top layer, third interlayer insulating film 377 Bottom layer, third interlayer insulating film 410, 420, 430, 440 1st to 4th bonding pads AF PXL Autofocus Pixel (Pixel Area) CF color filter DT11, DT12 First and second deep isolation patterns FD Floating diffusion region ML Micro Lens MxG peripheral circuit gate PD photoelectric conversion element PD1 to PD8 1st to 8th photoelectric conversion elements PXL Pixel (pixel area) PXLG Pixel Group RGL Reset gate line RR Recess area (opening) RX reset transistor SGL Select Gate Line SFX Source Follower Transistor ST11, ST12, ST13 1st to 3rd shallow element isolation patterns SX select transistor TG Transmission Gate TGL Transmission Gate Line TGL1~TGL8 1st~8th transmission gate lines TX Transistor TX1~TX8 1st to 8th transmission transistors V DD power terminal V OUT Output Line

Claims

1. a substrate having a first surface and a second surface opposite to the first surface, the substrate including pixel regions spaced apart from one another; a light-transmitting film covering the second surface and including an anti-reflection film having a recessed region; a light shielding pattern provided in the light-transmitting film, filling the recessed region and covering a portion of a first pixel region among the pixel regions; a grid disposed on the light-transmitting film; a color filter filling the openings of the grid; and a microlens disposed on the color filter.

2. The image sensor of claim 1 , wherein the first pixel area covered by the light shielding pattern includes at least one autofocus pixel.

3. Each of the pixel regions includes a pair of sub-pixel regions spaced apart from each other, and a pair of photodiodes provided in each of the pair of sub-pixel regions, The image sensor of claim 1 , wherein the light shielding pattern covers one of the pair of sub-pixel regions of the pixel region.

4. a single photodiode provided within each of the pixel regions; The image sensor of claim 1 , wherein the light shielding pattern covers a portion of the single photodiode in the first pixel region.

5. 2. The image sensor of claim 1, wherein the light-transmitting film further comprises a surface insulating film disposed between the second surface and the light-shielding pattern and between the second surface and the anti-reflection film.

6. the light-transmitting film is disposed on the second surface, the light shielding pattern is provided at the same height as the light-transmitting film; the light shielding pattern is disposed on a portion of the first pixel region; the grid is disposed on the light-transmitting film; The image sensor of claim 1 , wherein the microlenses are disposed on the color filters.

7. the light shielding pattern has a lower portion that protrudes below a lower surface of the anti-reflection film, the light-transmitting film further includes a surface insulating film disposed between the antireflection film and the second surface, The image sensor of claim 6 , wherein the surface insulating film surrounds at least a side surface of the lower portion of the light shielding pattern.

8. a substrate having a first surface and a second surface opposite to the first surface; a first deep isolation pattern disposed in the substrate, the first deep isolation pattern defining pixel regions each including a pair of subpixel regions; a second deep isolation pattern disposed between each of the pair of subpixel regions; an anti-reflective coating covering the second surface and having a recessed region; a light shielding pattern filling the recessed area; a grid disposed on the anti-reflection coating; a color filter filling the openings of the grid; a microlens disposed on the color filter; At least a first pixel area among the pixel areas is a portion of an autofocus pixel; The image sensor, wherein the light shielding pattern covers at least a portion of one of the pair of sub-pixel regions of the first pixel region.

9. The image sensor of claim 8 , wherein the thickness of the light shielding pattern is different from the thickness of the anti-reflection film.

10. forming a surface insulating film on one surface of a substrate; forming an anti-reflective film on the surface insulating film; etching the anti-reflective coating to form a recessed region in the anti-reflective coating; forming a light shielding pattern within the recessed region; and forming a capping layer on the light shielding pattern and the anti-reflection layer.

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