Processor and pipeline processing method

Abstract

To provide an InO processor capable of improving processing performance.SOLUTION: According to one aspect of the present invention, there is provided a processor that executes sequentially issued instructions in a pipeline manner, the processor including a fetch unit that fetches an instruction from a memory set in a program counter, a decode unit that decodes the instruction fetched by the fetch unit, a speculative issuance prediction unit that predicts whether the load instruction fetched by the fetch unit can be speculatively issued based on reference information including a correlation between information specifying the load instruction and speculative issuance possibility, and an instruction queue that holds the instruction decoded by the decode unit in the instruction queue. A processor is provided that includes a queue control unit that issues instructions in order held in an instruction queue while issuing speculatively issuable load instructions predicted to be speculatively issuable by a speculative issuance prediction unit ahead of instructions held ahead of the speculatively issuable load instructions in the instruction queue, and an arithmetic execution unit that executes the instructions issued by the queue control unit and writes execution results in a register.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a processor and a pipeline processing method. [Background technology]

[0002] In-Order (InO) processors, which execute programs according to program order, have the advantage of simple hardware, such as small power consumption and circuit area. However, InO processors have limitations in their instruction processing performance.

[0003] In contrast to this, an Out-of-Order (OoO) processor such as that disclosed in Patent Document 1 can execute instructions that can be processed sequentially. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2024-77885 Summary of the Invention [Problem to be solved by the invention]

[0005] While OoO processors make it easier to improve processing performance, their hardware becomes more complex, resulting in significant increases in power consumption, circuit area, etc.

[0006] In view of the above circumstances, the present invention provides an InO processor that can improve processing performance. [Means for solving the problem]

[0007] According to one aspect of the present invention, there is provided a processor that executes sequentially issued instructions in a pipeline manner, comprising: a fetch unit that fetches instructions from a memory set in a program counter; a decode unit that decodes the instructions fetched by the fetch unit; a speculative issuance prediction unit that predicts whether a load instruction fetched by the fetch unit can be speculatively issued based on reference information including a correlation between information identifying the load instruction and the possibility of speculative issuance; a queue control unit that holds the instructions decoded by the decode unit in an instruction queue and issues the instructions in the order held in the instruction queue, while performing pre-issuance to issue a speculative load instruction that the speculative issuance prediction unit predicts can be speculatively issued prior to an instruction held in the instruction queue earlier than the speculative load instruction; and an execution unit that executes the instructions issued by the queue control unit and writes the execution results to a register.

[0008] According to this aspect, by speculatively issuing a load instruction ahead of time, it is possible to suppress stalls of consumer instructions that use the results of the load instruction. As a result, it is possible to improve processing performance while maintaining the advantages of the InO processor, such as low power consumption and circuit area. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram showing an example of a basic configuration of a processor 1. FIG. [Figure 2] 2 is a schematic diagram showing an example of the state of instructions in the instruction queue 11 and the speculative instruction queue 12. FIG. [Figure 3] 2 is a pipeline chart showing an example of pipeline processing that can be performed by the processor 1. [Figure 4] 2 is a flow diagram showing an example of a pipeline processing method executed by the processor 1. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. Various features shown in the following embodiments can be combined with each other.

[0011] Incidentally, the program for realizing the software appearing in one embodiment may be provided as a non-transitory computer-readable medium, or may be provided so that it can be downloaded from an external server, or may be provided so that the program is started on an external computer and its functions are realized on a client terminal (so-called cloud computing).

[0012] Furthermore, various information processing according to an embodiment may realize input and output corresponding to the input. Here, the form of information referenced in such information processing (hereinafter referred to as reference information) is not limited as long as an output is obtained as a result of the input. The reference information may be, for example, rule-based information such as a database, a lookup table, or a predetermined function (including a decision formula such as a regression formula constructed using a statistical method), a trained model that has previously trained the correlation between input and output, or a large-scale language model that can output a desired result by inputting a prompt.

[0013] In one embodiment, a "unit" may include, for example, a combination of hardware resources implemented by a circuit in the broad sense and software information processing that can be specifically realized by these hardware resources. In one embodiment, various information is handled, and this information is represented, for example, by physical values ​​of signal values ​​representing voltage and current, high and low signal values ​​as a binary bit set consisting of 0 or 1, or quantum superposition (so-called quantum bits), and communication and calculations can be performed on a circuit in the broad sense.

[0014] Furthermore, a circuit in the broad sense is a circuit realized by at least an appropriate combination of a circuit, circuitry, processor, memory, etc. The processor may be a general-purpose processor or a dedicated circuit. That is, it includes an application specific integrated circuit (ASIC), a programmable logic device (e.g., a simple programmable logic device (SPLD), a complex programmable logic device (CPLD), and a field programmable gate array (FPGA)), etc.

[0015] 1. Hardware Configuration This section explains the hardware configuration.

[0016] <Processor 1> 1 is a block diagram showing an example of the basic configuration of a processor 1. The processor 1 includes a fetch unit 2, a decode unit 3, a speculative issue prediction unit 4, a queue control unit 5, an execution unit 6, a verification unit 7, and a memory unit (a storage device that stores an instruction queue 11, a speculative instruction queue 12, a scoreboard 14, a register file 16, a speculative buffer 18, etc.). The processor 1 is an InO processor that executes pipeline processing using the InO method.

[0017] <Fetch section 2> The fetch unit 2 is configured to fetch, from a memory set in a program counter (PL), instructions (machine language instructions) that constitute a program executed by the processor 1. The program counter is a register stored in the storage unit.

[0018] The instructions fetched by the fetch unit 2 include, for example, transfer instructions, arithmetic operation instructions, logical operation instructions, branch instructions, etc. Transfer instructions are instructions for copying data, and include load instructions, store instructions, etc. Load instructions are instructions for reading data from a specified memory into a register. Store instructions are instructions for writing data from a specified register to memory. Arithmetic operation instructions are instructions for performing arithmetic operations, etc. Logical operation instructions are instructions for performing logical operations such as logical AND, logical OR, exclusive OR, and negation. Branch instructions are instructions for switching the order of instructions.

[0019] <Decoder 3> The decode unit 3 is configured to decode the instruction fetched by the fetch unit 2. Specifically, the decode unit 3 analyzes the instruction and decodes it into control information.

[0020] <Speculative Issuance Prediction Department 4> The speculative issuance prediction unit 4 is configured to predict whether a load instruction fetched by the fetch unit 2 can be speculatively issued, based on reference information including a correlation between information identifying the load instruction and the possibility of speculative issuance. Specifically, the speculative issuance prediction unit 4 determines whether the instruction fetched by the fetch unit 2 is a load instruction, and if it determines that the instruction is a load instruction, predicts the possibility of speculative issuance of the instruction. "Speculative issuance" means issuing a specific instruction to the execution unit 6 before a previous instruction without waiting for an accurate determination of whether the instruction can be executed before the previous instruction in the execution order. Furthermore, "issuing" an instruction means causing the execution unit 6 to start executing the instruction.

[0021] The reference information is an estimator configured to receive information identifying a load instruction as input and output speculative issuance possibility information for the load instruction. The reference information is, for example, a table that returns speculative issuance possibility information by accessing the program counter of the load instruction (an example of information identifying a load instruction) as an index. This makes it possible to predict the speculative issuance possibility of the instruction in parallel with the decoding of the instruction by the decoding unit 3.

[0022] The reference information is constructed, for example, by learning according to the following procedure. First, among the load instructions included in the program, those load instructions that are predicted to improve the processing performance of the processor 1 if issued in advance are stored (entered) in the reference information as "speculatively issueable." This prediction and storage in the reference information is performed, for example, when a load instruction that has not been entered in the reference information and has not yet been entered is fetched, when a load instruction that has not yet been entered is inserted into the instruction queue 11, etc.

[0023] When a load instruction not entered in the reference information is fetched by the fetch unit 2, the speculative issuance prediction unit 4 predicts that the load instruction is "not speculatively issuable." On the other hand, when a load instruction entered in the reference information as "speculatively issuable" is fetched by the fetch unit 2, the speculative issuance prediction unit 4 predicts that the load instruction is "speculatively issuable load instruction." If an error occurs in the pre-issuance of the load instruction (described later), the speculative issuance prediction unit 4 records the number of errors (cumulative number of misses) of the load instruction in the reference information. Furthermore, the speculative issuance prediction unit 4 rewrites the entry of a load instruction whose number of errors has reached a predetermined threshold to "speculative issuance not possible." When a load instruction entered as "speculative issuance not possible" in this way is fetched by the fetch unit 2, the speculative issuance prediction unit 4 predicts that the load instruction is "not speculatively issuable."

[0024] Alternatively, the reference information may be constructed by learning using the following procedure. First, in the initial state, no load instructions are described (entered) in the reference information. When a load instruction that is not entered in the reference information is fetched by the fetch unit 2, the speculative issuance prediction unit 4 predicts that the load instruction is "speculatively issuable." That is, it predicts that the load instruction is a "speculatively issuable load instruction." Thereafter, if no error occurs in the pre-issuance of the load instruction (described later), the speculative issuance prediction unit 4 associates information identifying the load instruction with information indicating "speculative issuance possible" and records them in the reference information. For example, the speculative issuance prediction unit 4 reserves an entry in a table corresponding to the program counter of the load instruction, and writes information indicating "speculative issuance possible" into the entry.

[0025] On the other hand, if an error occurs in the pre-issuance of a load instruction that is not entered in the reference information, the speculative issuance prediction unit 4 associates information that identifies the load instruction with information indicating "speculative issuance not possible" and records them in the reference information. For example, the speculative issuance prediction unit 4 reserves an entry in the table that corresponds to the program counter of the load instruction, and writes information indicating "speculative issuance not possible" into the entry.

[0026] Furthermore, if an error occurs in the pre-issuance of a load instruction (speculatively issuable load instruction) that is entered in the reference information as "speculatively issuable," the speculative issuance prediction unit 4 rewrites the entry of the load instruction to "speculatively issuable not possible." On the other hand, if no error occurs in the pre-issuance of a load instruction that is entered in the reference information as "speculatively issuable," the entry of the load instruction is not updated.

[0027] In this way, the speculative issuance prediction unit 4 can update the reference information in response to the occurrence of an error due to the pre-issuance of a speculative load instruction. This can suppress the occurrence of errors due to the pre-issuance of a load instruction. Furthermore, the reference information can be automatically constructed even when a new load instruction is fetched.

[0028] The speculative issuance prediction unit 4 may predict the speculative issuance possible timing for a load instruction in addition to predicting whether the load instruction is "speculative issuance possible" or "speculative issuance impossible." For example, in the reference information, timing possibility information including the speculative issuance possible timing may be linked to information specifying the load instruction. The timing possibility information is composed of three levels of information, for example, "issuance possible at dispatch" (LV3), "issuance possible at a predetermined position" (LV2), and "speculative issuance impossible" (LV1).

[0029] A load instruction that is "issueable at dispatch" is inserted into the instruction queue 11, which will be described later, and is immediately inserted (copied) into the speculative instruction queue 12. A load instruction that is "issueable at a predetermined position" is inserted (copied) into the speculative instruction queue 12 when the order of the instruction from the top of the instruction queue 11 reaches a predetermined range (for example, the central area of ​​the instruction queue 11).

[0030] The reference information handling timing possibility information is constructed, for example, by learning according to the following procedure. First, when a load instruction not entered in the reference information is fetched by the fetch unit 2, the speculative issuance prediction unit 4 predicts that the load instruction is "issueable at dispatch time." If no error occurs during the pre-issuance of the load instruction (described later), the speculative issuance prediction unit 4 associates information identifying the load instruction with information indicating "issueable at dispatch time" and records the association in the reference information. On the other hand, if an error occurs during the pre-issuance of the load instruction at the time the load instruction is inserted into the instruction queue 11, the speculative issuance prediction unit 4 associates information identifying the load instruction with information indicating "issueable at a predetermined position" and records the association in the reference information. In other words, the speculative issuance prediction unit 4 lowers the issuance possibility level of the load instruction by one level from LV3. Furthermore, if an error occurs in the pre-issuance of a load instruction within a predetermined range of the instruction's rank from the top of the instruction queue 11, the speculative issuance prediction unit 4 associates information identifying the load instruction with information indicating "speculative issuance not permitted" and records them in the reference information. In other words, the speculative issuance prediction unit 4 lowers the level of the issuance possibility of the load instruction by one level from LV2.

[0031] <Queue control unit 5> The queue control unit 5 is configured to manage the issuance of instructions by controlling a queue that holds instructions. Specifically, the queue control unit 5 holds the instructions decoded by the decode unit 3 in the instruction queue 11, and issues the instructions in the order held in the instruction queue 11, while performing preemptive issuance in which a speculative load instruction that the speculative issuance prediction unit 4 predicts as speculatively issuable is issued prior to an instruction that was held in the instruction queue 11 earlier than the speculative load instruction.

[0032] The instruction queue 11 holds instructions (control information) fetched by the fetch unit 2 and decoded by the decode unit 3 in a first-in-first-out (FIFO) manner. That is, the queue control unit 5 inserts multiple instructions into the instruction queue 11 in the order in which they were decoded by the decode unit 3. The queue control unit 5 also takes out instructions from the instruction queue 11 in the order in which they were inserted into the instruction queue 11 and issues them to the execution unit 6. The queue control unit 5 simultaneously issues a number of instructions corresponding to the issue width (the number of instructions that can be executed simultaneously) of the execution unit 6.

[0033] The queue control unit 5 may pre-issue a speculative load instruction when there is free space in the issue width of the execution unit 6. Specifically, the queue control unit 5 pre-issues the speculative load instruction in a cycle in which the issue width of the execution unit 6 has not been fully used. This allows pre-issuance without hindering (delaying) the issuance of normal instructions, thereby enhancing the effect of improving the processing performance of the processor 1.

[0034] The queue control unit 5 may preemptively issue (specifically, insert into the speculative instruction queue 12, which will be described later) a speculative load instruction that has reached a speculative issue point in the instruction queue 11. The speculative issue point is a position where the instruction's rank from the top of the instruction queue 11 is within a predetermined range. This allows adjustment of the balance between the effect of suppressing errors and the effect of improving processing performance depending on the configuration, usage environment, and application of the hardware (processor 1) or software (program). In other words, if the speculative issue point is located closer to the front end where instructions are inserted into the instruction queue 11, speculative errors are more likely to occur. Conversely, if the speculative issue point is located closer to the top of the instruction queue 11, the effect of improving processing performance due to preemptive issuance is reduced. Therefore, by appropriately adjusting the speculative issue point, a design that focuses on the desired effect can be achieved.

[0035] 2 is a schematic diagram showing an example of the state of instructions in the instruction queue 11 and the speculative instruction queue 12. Instructions OD are sequentially inserted into the instruction queue 11 from the front end FE. The instruction at the head of the instruction queue 11 is issued to the execution unit 6 when the issue width of the execution unit 6 is available, and is then deleted from the instruction queue 11. Each time an instruction is issued from the head of the instruction queue 11, the instruction held in the instruction queue 11 moves up in rank toward the head (approaching the head). Note that when multiple instructions are issued simultaneously, the instructions in the instruction queue 11 move up in rank in accordance with the number of issued instructions.

[0036] 2, the fourth to sixth positions from the head of the instruction queue 11 are set as speculative issue points SP. In other words, the speculative issue point SP is a position where the instruction is fourth to sixth in rank from the head of the instruction queue 11. When a speculative load instruction SL reaches the speculative issue point SP (any of the fourth to sixth positions), the queue control unit 5 pre-issues the speculative load instruction SL (specifically, inserts it into the speculative instruction queue 12, which will be described later).

[0037] The number of instructions included in the range in which the speculative issue point is set should be equal to or less than the issue width of the execution unit 6. This prevents a speculative load instruction that has been pre-issued once from reaching the speculative issue point again (i.e., the speculative issue point moving from one position within the speculative issue point to another position within the speculative issue point), thereby preventing double pre-issue. In the example of Figure 2, the number of instructions in which the speculative issue point is set (the width of the speculative issue point) is three.

[0038] Furthermore, the number of instructions included in the range in which the speculative issue point is set should be the same as the issue width of the execution unit 6. For example, if the issue width of the execution unit 6 is 3, the width of the speculative issue point should also be 3. This prevents a speculative load instruction from passing through the speculative issue point due to the instruction order being moved up when multiple instructions are issued simultaneously. As a result, the processing performance of the processor 1 can be improved.

[0039] Note that, when the speculative issue prediction unit 4 is configured to also predict the speculative issue timing as described above, the queue control unit 5 may preemptively issue a speculative load instruction at the speculative issue timing (the timing at which the specified position is reached) predicted by the speculative issue prediction unit 4. For example, for a speculative load instruction predicted as "issueable at dispatch", the queue control unit 5 preemptively issues (inserts into the speculative instruction queue 12) the instruction at the same time as inserting it into the instruction queue 11. Also, for a speculative load instruction predicted as "issueable at a specified position", the queue control unit 5 preemptively issues (inserts into the speculative instruction queue 12) the speculative load instruction when the instruction reaches a specified position in the instruction queue 11.

[0040] The queue control unit 5 preferably holds the speculative load instruction as an original load instruction in the instruction queue 11, holds a copy load instruction obtained by copying the speculative load instruction in the speculative instruction queue 12, and pre-issues the copy load instructions in the order in which they are held in the speculative instruction queue 12. This makes it possible to control the verification, processing, etc. of the execution result (pre-issuance result) of the copy load instruction based on the position of the original load instruction in the instruction queue 11.

[0041] As shown in FIG. 2, the speculative instruction queue 12 holds the copy load instructions CL copied by the queue control unit 5 in a FIFO manner, similar to the instruction queue 11. That is, the queue control unit 5 inserts multiple copy load instructions CL into the speculative instruction queue 12 in the order in which the speculative load instructions SL (original load instructions) that are the copy sources reach the speculative issue points SP. The queue control unit 5 also retrieves the copy load instructions CL from the speculative instruction queue 12 in the order in which they were inserted into the speculative instruction queue 12 and issues them to the execution unit 6 (specifically, the LSU 62). The queue control unit 5 issues the copy load instructions CL without referring to the scoreboard 14 when there is a vacancy in the issue width of the execution unit 6 (a vacancy after the instruction in the instruction queue 11 has been preferentially issued). The queue control unit 5 may also simultaneously issue to the execution unit 6 a number of copy load instructions corresponding to the number of vacancies in the issue width of the execution unit 6.

[0042] The scoreboard 14 is a table that describes the value state (ready or not ready) of each logical register. The scoreboard 14 also has a field in which a speculation buffer number (described later) is written for forwarding the execution result of a pre-issued instruction. The queue control unit 5 reads entries in the scoreboard 14 that correspond to each source register of the instruction to be issued and determines whether the values ​​of these registers are ready. The queue control unit 5 issues the instruction to the execution unit 6 when the values ​​of all source registers are ready and the execution unit (e.g., ALU 61, LSU 62, etc.) that executes the instruction in the execution unit 6 is available. When the execution unit 6 starts executing an instruction, it writes "not ready" to the entry in the scoreboard 14 that corresponds to the destination register. When the execution unit 6 finishes executing the instruction and writes the execution result to the destination register, it writes "ready" to the entry in the scoreboard 14 that corresponds to that register.

[0043] The queue control unit 5 secures an area for storing the execution result of the copy load instruction in the speculation buffer 18 in conjunction with inserting the copy load instruction into the speculation instruction queue 12. The speculation buffer 18 has a 1-bit field (ready bit) indicating whether the instruction to be written to each area (entry) of the speculation buffer 18 has been completed, a field in which the execution result of the pre-issuance of the speculative load instruction is written, and a field in which the exception code when an exception occurs in the pre-issuance, data required to handle the exception, etc. are written.

[0044] Specifically, the queue control unit 5 obtains from the free list the address (speculation buffer number) of the speculation buffer 18 that is available at the time of inserting the copy load command, and associates the speculation buffer number with the corresponding load command (original load command or copy load command) in the command queue 11 and the speculation command queue 12. If the speculation buffer number cannot be obtained (i.e., there is no available space in the speculation buffer 18), the queue control unit 5 temporarily stops inserting the copy load command into the speculation command queue 12, and inserts the copy load command into the speculation command queue 12 when there is available space in the speculation buffer 18. The capacity of the speculation buffer 18 (the number of speculation buffer numbers) is set according to, for example, the position of the speculation issue point (the expected value of the number of commands held in the speculation command queue 12).

[0045] If a copy load instruction has not been pre-issued when the original load instruction reaches the head of the instruction queue 11, the queue control unit 5 may suspend issuance of instructions from the instruction queue 11 until the copy load instruction is pre-issued. This ensures that the copy load instruction held in the speculative instruction queue 12 is pre-issued.

[0046] The queue control unit 5 checks whether a copy load instruction has been issued in advance, for example, by reading the ready bit of the speculative buffer 18 in each cycle, into which the execution result of the copy load instruction is written by the later-described operation execution unit 6. As described above, the speculative buffer number into which the execution result of the copy load instruction is stored is linked to the original load instruction in the instruction queue 11, and therefore the queue control unit 5 refers to this to read the ready bit from the speculative buffer 18.

[0047] When the original load instruction reaches the head of the instruction queue 11 and a corresponding copy load instruction is issued in advance, the queue control unit 5 preferably transfers the execution result of the copy load instruction to the instruction in the instruction queue 11. This prevents the execution result of the copy load instruction from being transferred to an instruction that should be executed before the original load instruction (an instruction inserted before the original load instruction in the instruction queue 11).

[0048] "Transfer of execution results" includes forwarding to a normal instruction that is not issued in advance. For example, the queue control unit 5 performs forwarding using the speculation buffer 18 in which the execution result of the copy load instruction is stored. Specifically, after the copy load instruction is issued, the queue control unit 5 writes the speculation buffer number indicating the storage location of the execution result of the copy load instruction to be forwarded to the scoreboard 14 instead of "not ready." The execution unit 6 obtains information that "ready and speculation buffer number is N" from the scoreboard 14 (i.e., references the speculation buffer number written to the scoreboard 14), reads the execution result from the speculation buffer 18, and executes the subsequent instruction. In this way, the execution unit 6 references the speculation buffer 18 instead of a register when forwarding.

[0049] After the forwarding is completed, the queue control unit 5 erases the speculative buffer number from the scoreboard 14 and returns the speculative buffer number to the free list (writes it in the free list as an available speculative buffer number). Forwarding ends, for example, when the execution result of the copy load instruction stored in the speculative buffer 18 is written (copied) to a register. In this case, the queue control unit 5 releases the area for the speculative buffer number. Forwarding also ends, for example, when an error is detected in verifying the execution result of the copy load instruction.

[0050] Furthermore, when the original load instruction reaches the head of the instruction queue 11 and a copy load instruction is pre-issued, the queue control unit 5 deletes the original load instruction from the instruction queue 11. In other words, the original load instruction is not deleted from the instruction queue 11 until a copy load instruction is pre-issued.

[0051] <Calculation execution unit 6> The execution unit 6 is configured to execute instructions issued by the queue control unit 5 and write the execution results to a register. The instructions executed by the execution unit 6 include normal instructions (non-speculative instructions) issued from the instruction queue 11 and preceding instructions (speculative instructions) issued from the speculative instruction queue 12. The execution unit 6 executes the instructions in the order in which they were issued.

[0052] 1, the execution unit 6 includes an ALU 61 (Arithmetic and Logic Unit) and an LSU 62 (Load Store Unit). The ALU 61 executes arithmetic operation instructions, logical operation instructions, etc. The LSU 62 executes load instructions and store instructions.

[0053] A normal instruction normally issued from the instruction queue 11 is executed by the ALU 61 or the LSU 62. A speculative load instruction (copy load instruction) pre-issued from the speculative instruction queue 12 is executed by the LSU 62.

[0054] The execution unit 6 writes the execution result of a normal instruction directly to a register in the register file 16. On the other hand, the execution unit 6 writes the execution result of a speculative load instruction to the speculation buffer 18, and if the verification unit 7, which will be described later, detects no error from the execution result of the copy load instruction, copies the execution result written to the speculation buffer 18 to the register. This makes it possible to avoid storing an execution result containing an error in a register when the execution result of the speculative load instruction contains an error.

[0055] Furthermore, when executing a speculative load instruction, the execution unit 6 sets the ready bit of the area of ​​the speculative buffer 18 (area indicated by the speculative buffer number) reserved by the queue control unit 5 to 0 (not ready). The execution unit 6 sets the ready bit to 1 (ready) when the execution result of the speculative load instruction is obtained and writing to the speculative buffer 18 is completed.

[0056] <Verification Section 7> The verification unit 7 is configured to verify the execution result of the copy load instruction. Specifically, the verification unit 7 detects an error (speculation error) when the copy load instruction overtakes an instruction that should not be overtaken. The speculation error includes a register order violation and a memory order violation.

[0057] A register order violation occurs when a load instruction is executed before the instruction that generates the value of the source register to be loaded by the load instruction is executed. In other words, a register order violation occurs when the register read during execution of a copy load instruction has been rewritten by the time the original load instruction is issued (normal issuance timing).

[0058] A register order violation is detected, for example, by a register correspondence table having entries that correspond one-to-one to each logical register. First, when the execution unit 6 writes to a register by executing a pre-issued load instruction (copy load instruction), the execution unit 6 marks (flags) the entry in the register correspondence table that corresponds to the destination register of the load instruction. After executing all pre-issued load instructions, the verification unit 7 checks whether or not the entries corresponding to the source registers of all pre-issued load instructions in the register correspondence table are marked. If the entry is marked, the verification unit 7 determines that a register order violation has occurred.

[0059] Verification unit 7 may also detect register order violations using a Store Vulnerability Window (SVW). The SVW is a mechanism that determines whether a store instruction that writes to the same address exists between the issuance of a load instruction and the verification of the execution result.

[0060] The specific procedure for detecting register order violations using the SVW concept is as follows. First, when an instruction is executed normally, the execution unit 6 or the verification unit 7 writes an instruction sequence number (ISN), which is a number indicating the order of the instruction in the program, to an entry in the detection table corresponding to the destination register number (specifically, an entry indicated by a hash value obtained by converting the destination register number). If there are multiple destination registers, this is performed for each destination register. Furthermore, if the ISN of the executed instruction is greater than ISN retire (a variable that holds the maximum value of ISN, with an initial value of 0), ISN retire is updated with the ISN of this instruction. Next, when executing a pre-issued load instruction, the execution unit 6 or the verification unit 7 reads and records ISN retire at the timing of register read, forwarding reception, etc. When verifying the execution result of the pre-issued load instruction, the verification unit 7 reads the ISN written in the entry in the detection table corresponding to the source register number (specifically, an entry indicated by a hash value obtained by converting the source register number) for each source register of the load instruction. If at least one of the read isn's is greater than the value of ISN retire recorded when the load instruction is executed, the verification unit 7 determines that a violation of the register read order has occurred.

[0061] A memory order violation is an error that occurs when a store instruction on which a load instruction depends has not been executed at the time the load instruction is pre-issued. In other words, a memory order violation is an error that occurs when the memory at the address read when a copy load instruction is executed has been rewritten by the time the original load instruction is issued (normal issuance timing).

[0062] A memory order violation is detected, for example, by a memory correspondence table having entries that correspond one-to-one to each memory address. First, when the execution unit 6 executes a pre-issued load instruction (copy load instruction) to write to memory, the execution unit 6 marks (flags) the entry in the memory correspondence table that corresponds to the memory address. After executing all pre-issued load instructions, the verification unit 7 checks whether or not the entry corresponding to the memory address to be loaded for all pre-issued load instructions is marked in the memory correspondence table. If the entry is marked, the verification unit 7 determines that a memory order violation has occurred.

[0063] Furthermore, the verification unit 7 may detect memory order violations using SVW. For example, the verification unit 7 can detect memory order violations using Bloom-like SVW. Bloom-like SVW is a method in which multiple SVWs using different hash functions are run in parallel, and only when all SVWs detect an order violation is it determined that an order violation has occurred overall. When the total table capacity is fixed, Bloom-like SVW can reduce the probability of false positives compared to methods that use a single hash function.

[0064] The verification unit 7 may perform a first verification to detect a register order violation, and after the first verification, may perform a second verification to detect a memory order violation. The verification unit 7 may read the scoreboard 14 in parallel with the first verification. This allows the verification unit 7 to immediately switch to issuing instructions in the correct order if a register order violation is detected by the first verification, thereby suppressing pipeline flushing. Furthermore, the queue control unit 5 may perform forwarding (writing the speculative buffer number to the scoreboard 14) when the first verification by the verification unit 7 is successful (no error is detected). Note that if the second verification by the verification unit 7 fails (an error is detected), the queue control unit 5 performs a pipeline flush and terminates forwarding. Specifically, the queue control unit 5 erases the speculative buffer number from the scoreboard 14 and releases the area of ​​the speculative buffer number in the speculative buffer 18 (returning it to the free list).

[0065] <effect> FIG. 3 is a pipeline chart showing an example of pipeline processing that can be executed by the processor 1. FIG. 3A is a conventional pipeline chart that does not apply speculative issuance (advance issuance), and FIG. 3B is a pipeline chart that applies speculative issuance to the same set of instructions (program) as in FIG. 3A. In FIG. 3, the horizontal axis indicates the instruction cycle (execution cycle) of the processor 1. The vertical axis indicates the execution order of each instruction in the program to be executed, with processing of each stage being performed in order from the top instruction. In FIG. 3, the speculative width of the execution unit 6 is set to 2.

[0066] In FIG. 3, "F" indicates the fetch stage by the fetch unit 2, "D" indicates the decode stage by the decode unit 3, "IQ" indicates the period held in the instruction queue 11, "RR" indicates the register read stage by the execution unit 6, "Ex" indicates the execution stage by the execution unit 6, "WB" indicates the register write stage by the execution unit 6, and "→" indicates the wait stage. The wait stage is a stage for performing staging to provide the same latency until an exception is detected. Also, in FIG. 3B, "SIQ" indicates the period held in the speculative instruction queue 12, and "Veri" indicates the speculative verification stage by the verification unit 7.

[0067] In the pipeline chart shown in Figure 3A, because instruction I3 depends on load instruction I2, it waits for load instruction I2 to execute at the head of instruction queue 11, preventing instruction I3 from being issued until cycle 14. The next load instruction, I4, is ready to execute before instruction I3 is issued, but load instruction I4 is not issued until instruction I3 is issued. Therefore, all instructions following load instruction I4 must wait for the completion of load instruction I2, even if they do not reference the execution result of load instruction I2 (do not depend on the execution result of load instruction I2). This stall, which prevents consumer instructions from being issued for load instructions, can become a performance bottleneck for InO processors.

[0068] On the other hand, in FIG. 3B, the load instruction I4 is pre-issued as a speculatively issueable load instruction. Specifically, after decoding is complete, the load instruction I4 is inserted into the instruction queue 11 (the lower stage after branching in FIG. 3B) and also into the speculative instruction queue 12 (the upper stage after branching in FIG. 3B). Thereafter, the load instruction I4 (copy load instruction) inserted into the speculative instruction queue 12 is pre-issued from the speculative instruction queue 12 in the 9th cycle when a vacancy occurs in the issue width of the execution unit 6, without waiting for the issuance of the load instructions I2 and I3. The execution result of the copy load instruction is written into the speculative buffer 18 ("WB" in the 14th cycle). On the other hand, when the load instruction I4 (original load instruction) held in the instruction queue 11 reaches a position where it can be issued, the execution result of the copy load instruction written into the speculative buffer 18 is verified. In addition, the execution result of the load instruction I4 is forwarded to the next instruction I5.

[0069] If the verification is successful, the execution result of the load instruction I4 written to the speculation buffer 18 is written to the register file 16 at the same time that the execution result of the original load instruction becomes available for writing. After the execution result of the load instruction I4 is written to the register file 16, the area used in the speculation buffer 18 is released. This process speeds up the completion of execution of all instructions by four cycles compared to FIG. 3A, where the load instruction I4 is not pre-issued. In other words, the critical path of program execution is shortened.

[0070] <Pipeline processing method> In the pipeline processing method disclosed herein, sequentially issued instructions are executed in a pipeline manner by a processor 1. This pipeline processing method includes a fetch step of fetching instructions from a memory set in a program counter, a decode step of decoding the instructions fetched in the fetch step, a speculative issuance prediction step of predicting whether the load instruction fetched in the fetch step can be speculatively issued based on reference information including a correlation between information identifying the load instruction and the possibility of speculative issuance, a queue control step of holding the instructions decoded in the decode step in an instruction queue and issuing the instructions in the order held in the instruction queue while pre-issuing a speculative load instruction predicted to be speculatively issueable in the speculative issuance prediction step prior to an instruction held in the instruction queue earlier than the speculative load instruction, and an operation execution step of executing the instructions issued in the queue control step in the order held and writing the execution results to a register.

[0071] Fig. 4 is a flow diagram showing an example of a pipeline processing method executed by the processor 1. The flow in Fig. 4 shows processing for one instruction included in a program. Therefore, the flow in Fig. 4 is executed for each of multiple instructions included in the program.

[0072] In the flow of Figure 4, first, the processor 1 fetches an instruction included in the program (step S110). Next, the processor 1 decodes the fetched instruction and predicts whether the instruction can be speculatively issued (step S120). Note that the prediction of speculative issuance possibility is performed only for load instructions. Next, the processor 1 inserts the decoded instruction into the instruction queue 11 (step S130).

[0073] After insertion into the instruction queue 11, the processor 1 determines whether the instruction can be speculatively issued (is a speculatively issueable load instruction) at a predetermined timing (for example, when the speculative issue point is reached) (step S140). If the instruction cannot be speculatively issued (including when the instruction is not a load instruction) (S140: NO), the processor 1 issues the instruction normally to the execution unit 6 when the instruction reaches the head of the instruction queue 11 (step S150). After normal issuance of the instruction, the processor 1 writes the execution result of the instruction to a register (step S160).

[0074] On the other hand, if the instruction can be speculatively issued (S140: YES), the processor 1 inserts the instruction into the speculation instruction queue 12 (step S170). Furthermore, when the instruction reaches the head of the speculation instruction queue 12, the processor 1 preemptively issues the instruction to the execution unit 6 (step S180). After preemptively issuing the instruction, the processor 1 writes the execution result of the instruction into the speculation buffer 18 (step S190). After writing into the speculation buffer 18, the processor 1 verifies the execution result of the instruction (step S200). If the verification of the execution result is successful and the instruction reaches the head of the instruction queue 11, the processor 1 writes the execution result written in the speculation buffer 18 into a register (step S210). If the verification fails in step S200, an exception handling procedure such as a pipe flush is executed.

[0075] 4. Effect The operation of this embodiment can be summarized as follows: By speculatively issuing a load instruction ahead of time, stalls of consumer instructions that use the results of the load instruction can be suppressed. As a result, processing performance can be improved while maintaining the advantages of the InO processor, such as low power consumption and circuit area.

[0076] Although the embodiment of the present invention has been described above, the present invention is not limited to this and can be modified as appropriate within the scope of the technical idea of ​​the invention.

[0077] 5.Other The queue control unit 5 does not necessarily have to pre-issue a speculative load instruction when there is a vacancy in the issue width of the execution unit 6. For example, the queue control unit 5 may pre-issue a speculative load instruction depending on the pipeline situation (pre-issue condition) other than the issue width of the execution unit 6.

[0078] The queue control unit 5 does not necessarily have to insert the speculative load instruction into the speculative instruction queue 12. For example, the queue control unit 5 may pre-issue the speculative load instruction from the instruction queue 11 directly to the execution unit 6.

[0079] The speculative issuance prediction of a load instruction by the speculative issuance prediction unit 4 may be performed in parallel with the fetching of the load instruction by the fetch unit 2, or may be performed prior to the fetching.

[0080] It may be provided in the following manner.

[0081] (1) A processor that executes sequentially issued instructions in a pipeline manner, comprising: a fetch unit that fetches instructions from a memory set in a program counter; a decode unit that decodes the instructions fetched by the fetch unit; a speculative issuance prediction unit that predicts whether a load instruction fetched by the fetch unit can be speculatively issued based on reference information including a correlation between information identifying the load instruction and the possibility of speculative issuance; a queue control unit that holds the instructions decoded by the decode unit in an instruction queue and issues instructions in the order held in the instruction queue, while performing pre-issuance to issue a speculatively issueable load instruction that the speculative issuance prediction unit predicts can be speculatively issued prior to an instruction held in the instruction queue earlier than the speculatively issueable load instruction; and an execution unit that executes the instructions issued by the queue control unit and writes the execution results to a register.

[0082] (2) In the processor described in (1) above, the queue control unit pre-issues the speculative load instruction that has reached a speculative issue point in the instruction queue, where the speculative issue point is a position where the instruction's rank from the head of the instruction queue is within a predetermined range.

[0083] (3) The processor according to (2) above, wherein the number of instructions included in the range in which the speculative issue point is set is equal to or less than the issue width of the execution unit.

[0084] (4) In the processor described in any one of (1) to (3) above, the queue control unit pre-issues the speculative load instruction when there is space in the issue width of the execution unit.

[0085] (5) In a processor described in any one of (1) to (4) above, the queue control unit retains the speculative load instruction as an original load instruction in the instruction queue, retains a copy load instruction that is a copy of the speculative load instruction in a speculative instruction queue, and pre-issues the copy load instructions in the order in which they are retained in the speculative instruction queue.

[0086] (6) In the processor described in (5) above, if the copy load instruction has not been pre-issued when the original load instruction reaches the head of the instruction queue, the queue control unit suspends the issuance of instructions from the instruction queue until the copy load instruction has been pre-issued.

[0087] (7) A processor according to (5) or (6) above, further comprising a verification unit that verifies the execution result of the copy load instruction, wherein the execution unit writes the execution result of the speculative load instruction to a speculative buffer, and if the verification unit does not detect an error in the execution result of the copy load instruction, copies the execution result written to the speculative buffer to the register.

[0088] (8) In a processor described in any one of (5) to (7) above, the queue control unit transfers the execution result of the copy load instruction to the instruction in the instruction queue when the original load instruction reaches the head of the instruction queue and the corresponding copy load instruction is issued in advance.

[0089] (9) In the processor according to any one of (1) to (8) above, the speculative issue prediction unit updates the reference information in response to the occurrence of an error associated with the advance issuance of the speculative load instruction.

[0090] (10) A pipeline processing method for causing a processor to execute sequentially issued instructions in a pipeline manner, the method comprising: a fetch step for fetching instructions from a memory set in a program counter; a decode step for decoding the instructions fetched in the fetch step; a speculative issuance prediction step for predicting whether the load instruction fetched in the fetch step can be speculatively issued based on reference information including a correlation between information identifying the load instruction and the possibility of speculative issuance; a queue control step for holding the instructions decoded in the decode step in an instruction queue and issuing instructions in the order held in the instruction queue, while issuing a speculative load instruction predicted to be speculatively issueable in the speculative issuance prediction step ahead of an instruction held in the instruction queue earlier than the speculative load instruction; and an operation execution step for executing the instructions issued in the queue control step and writing the execution result to a register. Of course, this is not the case.

[0091] Finally, while various embodiments of the present disclosure have been described, they are presented as examples and are not intended to limit the scope of the invention. The novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. Such embodiments and modifications are intended to be included within the scope and spirit of the invention, as well as within the scope of the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0092] 1: Processor 2: Fetch section 3: Decoder 4: Speculation issuance prediction section 5: Queue control section 6: Calculation execution unit 7: Verification section 11: Command queue 12: Speculative instruction queue 14: Scoreboard 16: Register file 18: Speculation buffer 61 :ALU 62: LSU CL: Copy load command FE: Front end OD: Instruction SL: Speculative load instruction SP: Speculation issue point

Claims

1. A processor that executes sequentially issued instructions in a pipelined manner, a fetch unit that fetches an instruction from a memory set in a program counter; a decode unit that decodes the instruction fetched by the fetch unit; a speculative issuance prediction unit that predicts whether speculative issuance is possible for the load instruction fetched by the fetch unit based on reference information including a correlation between information specifying the load instruction and the possibility of speculative issuance; a queue control unit that holds the instructions decoded by the decode unit in an instruction queue, issues the instructions in the order held in the instruction queue, and performs pre-issuance by issuing a speculative load instruction predicted by the speculative issue prediction unit as speculatively issuable prior to an instruction held in the instruction queue earlier than the speculative load instruction; an execution unit that executes the command issued by the queue control unit and writes the execution result into a register; A processor comprising:

2. 10. The processor of claim 1, the queue control unit pre-issues the speculative load instruction that has reached a speculative issue point in the instruction queue, wherein the speculative issue point is a position where the instruction's rank from the head of the instruction queue is within a predetermined range.

3. 3. The processor of claim 2, a number of instructions included in the range in which the speculative issue point is set is equal to or less than an issue width of the execution unit.

4. 10. The processor of claim 1, The queue control unit pre-issues the speculative load instruction when there is space in the issue width of the execution unit.

5. 10. The processor of claim 1, The queue control unit retains the speculative load instruction as an original load instruction in the instruction queue, retains a copy load instruction that is a copy of the speculative load instruction in a speculative instruction queue, and pre-issues the copy load instructions in the order in which they are retained in the speculative instruction queue.

6. 6. The processor of claim 5, A processor in which, if the copy load instruction has not been pre-issued when the original load instruction reaches the head of the instruction queue, the queue control unit suspends the issuance of instructions from the instruction queue until the copy load instruction has been pre-issued.

7. 6. The processor of claim 5, a verification unit that verifies the execution result of the copy load command, The execution unit writes the execution result of the speculative load instruction to a speculation buffer, and if the verification unit does not detect an error from the execution result of the copy load instruction, copies the execution result written to the speculation buffer to the register.

8. 6. The processor of claim 5, A processor in which the queue control unit transfers the execution result of the copy load instruction to the instructions in the instruction queue when the original load instruction reaches the head of the instruction queue and the corresponding copy load instruction is issued in advance.

9. 10. The processor of claim 1, The speculative issue prediction unit updates the reference information in response to an error occurring due to the pre-issuance of the speculative load instruction.

10. A pipeline processing method for causing a processor to execute sequentially issued instructions in a pipeline manner, comprising: a fetch step of fetching an instruction from memory set in a program counter; a decoding step of decoding the instruction fetched in the fetching step; a speculative issuance prediction step of predicting whether speculative issuance is possible for the load instruction fetched in the fetch step, based on reference information including a correlation between information specifying the load instruction and the possibility of speculative issuance; a queue control step of holding the instructions decoded in the decoding step in an instruction queue and issuing the instructions in the order held in the instruction queue, while issuing a speculative load instruction predicted in the speculative issue prediction step to be speculatively issueable in advance of an instruction held in the instruction queue earlier than the speculative load instruction; an operation execution step of executing the command issued in the queue control step and writing the execution result into a register; A pipeline processing method comprising:

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