MEMORY SYSTEM, MEMORY CONTROLLER AND CONTROL METHOD

Abstract

To perform error correction with higher accuracy. [Solution] A memory system includes a nonvolatile memory that stores a concatenated code formed by a first error correction code and a second error correction code, and a memory controller. The memory controller executes a second decoding process using the second error correction code on read information read from the nonvolatile memory, and if decoding by the second decoding process fails, executes a first decoding process using the first error correction code on the read information reflecting the correction result by the second decoding process. If decoding by the first decoding process fails, the memory controller identifies an intersection where an error is contained in component codes of two or more different dimensions of the second error correction code, executes a correction process to correct a symbol included in the intersection, and then executes the first decoding process again.

Description

[Technical Field]

[0001] The following embodiments relate to a memory system, a memory controller, and a control method. [Background technology]

[0002] In a memory system, in order to protect data stored in a memory such as a NAND flash memory, error correction coded data is stored in the memory. Therefore, when reading data stored in the memory, the error correction coded data (also called a received word) read from the memory is decoded to restore the data before being error correction coded. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2019 / 0089384 [Patent Document 2] US Patent Application Publication No. 2019 / 0288711 [Patent Document 3] US Patent Application Publication No. 2017 / 0093438 [Patent Document 4] US Patent Application Publication No. 2009 / 0132894 [Patent Document 5] US Patent Application Publication No. 2022 / 0278695 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the embodiments of the present invention is to provide a memory system, a memory controller, and a control method that can perform error correction (decoding) with higher accuracy. [Means for solving the problem]

[0005] A memory system according to an embodiment includes a nonvolatile memory that stores a concatenated code formed by a first error correction code and a second error correction code, and a memory controller. The memory controller executes a second decoding process using the second error correction code on read information read from the nonvolatile memory, and if the second decoding process fails, executes a first decoding process using the first error correction code on the read information reflecting the correction result of the second decoding process. If the first decoding process fails, the memory controller identifies an intersection where an error is contained in component codes of two or more different dimensions of the second error correction code, and executes a correction process to correct a symbol included in the intersection, and then executes the first decoding process again. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram of a memory system according to a first embodiment. [Figure 2] 10A and 10B are diagrams for explaining examples of outer codes and inner codes; [Figure 3] FIG. 10 is a diagram showing an example of a situation in which an error cannot be removed. [Figure 4] FIG. 2 is a block diagram of a decoder according to the first embodiment. [Figure 5] FIG. 10 is a diagram showing an example in which decoding is successful. [Figure 6] 10 is a flowchart of a decoding process according to the first embodiment. [Figure 7] FIG. 10 is a diagram showing an example of an error occurrence situation. [Figure 8] 10 is a flowchart of a decoding process according to the third embodiment. [Figure 9] FIG. 10 is a diagram for explaining an example in which all patterns can be tried. DETAILED DESCRIPTION OF THE INVENTION

[0007] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A memory system according to an embodiment will be described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments.

[0008] (First embodiment) Fig. 1 is a block diagram showing a schematic configuration example of a memory system according to the first embodiment. As shown in Fig. 1, the memory system 1 includes a memory controller 10 and a nonvolatile memory 20. The memory system 1 can be connected to a host 30, and Fig. 1 shows the memory system 1 connected to the host 30. The host 30 may be, for example, an electronic device such as a personal computer or a mobile terminal.

[0009] The nonvolatile memory 20 is a nonvolatile memory that stores data nonvolatilely, such as a NAND memory. In the following description, a case where a NAND memory is used as the nonvolatile memory 20 will be exemplified, but it is also possible to use storage devices other than a NAND memory, such as a three-dimensional structure flash memory, a ReRAM (Resistance Random Access Memory), or an FeRAM (Ferroelectric Random Access Memory), as the nonvolatile memory 20. Furthermore, it is not essential that the nonvolatile memory 20 be a semiconductor memory, and this embodiment can also be applied to various storage media other than semiconductor memories.

[0010] The memory system 1 may be a memory card or the like in which the memory controller 10 and the nonvolatile memory 20 are configured as a single package, or may be an SSD (Solid State Drive) or the like.

[0011] The memory controller 10 controls writing to the nonvolatile memory 20 in accordance with a write request from the host 30. The memory controller 10 also controls reading from the nonvolatile memory 20 in accordance with a read request from the host 30. The memory controller 10 includes a host I / F (host interface) 15, a memory I / F (memory interface) 13, a control unit 11, an encoding / decoding unit (codec) 14, and a data buffer 12. The host I / F 15, the memory I / F 13, the control unit 11, the encoding / decoding unit 14, and the data buffer 12 are interconnected by an internal bus 16. Some or all of the operations of the components of the memory controller 10 may be realized by a CPU (Central Processing Unit) executing firmware, or may be realized by hardware.

[0012] The host I / F 15 is a circuit that performs processing in accordance with the interface standard with the host 30 and outputs commands received from the host 30, user data to be written, etc. to the internal bus 16. The host I / F 15 also transmits user data that has been read and restored from the nonvolatile memory 20, responses from the control unit 11, etc. to the host 30.

[0013] The memory I / F 13 is a circuit that performs a write process to the nonvolatile memory 20 based on an instruction from the control unit 11. The memory I / F 13 also performs a read process from the nonvolatile memory 20 based on an instruction from the control unit 11.

[0014] The control unit 11 performs overall control of each component of the memory system 1. When the control unit 11 receives an instruction from the host 30 via the host I / F 15, it performs control in accordance with the instruction. For example, the control unit 11 instructs the memory I / F 13 to write user data and parity to the nonvolatile memory 20 in accordance with the instruction from the host 30. The control unit 11 also instructs the memory I / F 13 to read user data and parity from the nonvolatile memory 20 in accordance with the instruction from the host 30.

[0015] Furthermore, when the control unit 11 receives a write request for user data from the host 30, it accumulates the user data in the data buffer 12 and determines a storage area (memory area) for the user data in the nonvolatile memory 20. That is, the control unit 11 manages the write destination of the user data. The correspondence between the logical address of the user data received from the host 30 and the physical address indicating the storage area on the nonvolatile memory 20 where the user data is stored is stored as an address conversion table.

[0016] Furthermore, when the control unit 11 receives a read request from the host 30, it converts the logical address specified by the read request into a physical address using the address conversion table described above, and instructs the memory I / F 13 to read from the physical address.

[0017] In NAND memory, data is generally written and read in units of data called pages, and erased in units of data called blocks. In this embodiment, a plurality of memory cells connected to the same word line are called a memory cell group. If the memory cells are single-level cells (SLC), one memory cell group corresponds to one page. If the memory cells are multi-level cells (MLC), one memory cell group corresponds to multiple pages. Each memory cell is connected to both a word line and a bit line. Therefore, each memory cell can be identified by an address that identifies the word line and an address that identifies the bit line.

[0018] The data buffer 12 temporarily stores user data received by the memory controller 10 from the host 30 before storing the data in the nonvolatile memory 20. The data buffer 12 also temporarily stores user data read from the nonvolatile memory 20 before transmitting the data to the host 30. The data buffer 12 may be implemented using general-purpose memory such as an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory).

[0019] User data transmitted from the host 30 is transferred to the internal bus 16 and temporarily stored in the data buffer 12. The encoding / decoding unit 14 encodes the user data to generate code words. The encoding / decoding unit 14 also decodes received words, which are data read from the non-volatile memory 20, to restore the user data. Therefore, the encoding / decoding unit 14 includes an encoder 17 and a decoder 18. Note that the data encoded by the encoding / decoding unit 14 may include control data used inside the memory controller 10 in addition to the user data.

[0020] Next, the write process of this embodiment will be described. When writing user data to the nonvolatile memory 20, the control unit 11 instructs the encoder 17 to encode the user data. At that time, the control unit 11 determines a storage location (storage address) of the codeword in the nonvolatile memory 20, and also instructs the memory I / F 13 about the determined storage location.

[0021] The encoder 17 generates code words by encoding the user data in the data buffer 12 based on instructions from the control unit 11. Examples of encoding methods that can be used include encoding methods using algebraic codes such as BCH (Bose-Chaudhuri-Hocquenghem) codes and RS (Reed-Solomon) codes, as well as encoding methods (such as product codes) that use these codes as row- and column-oriented component codes. The memory I / F 13 controls the storage of code words in memory locations in the nonvolatile memory 20 instructed by the control unit 11.

[0022] Next, a description will be given of the processing performed when reading data from the nonvolatile memory 20 in this embodiment. When reading data from the nonvolatile memory 20, the control unit 11 specifies an address on the nonvolatile memory 20 and instructs the memory I / F 13 to read. The control unit 11 also instructs the decoder 18 to start decoding. In accordance with the instruction from the control unit 11, the memory I / F 13 reads data from the specified address in the nonvolatile memory 20 and inputs the read data to the decoder 18 as a received word. The decoder 18 decodes the received word, which is the data read from the nonvolatile memory 20.

[0023] Next, the error correction code (codeword) used in this embodiment will be described. In this embodiment, the encoder 17 generates a concatenated code as the error correction code. The concatenated code is, for example, a code made up of an error correction code C1 (first error correction code) generated using data (user data) stored in the nonvolatile memory 20, and an error correction code C2 (second error correction code) generated using the error correction code C1. Hereinafter, the error correction code C1 will be referred to as an outer code, and the error correction code C2 will be referred to as an inner code.

[0024] The outer code is used to remove residual errors that cannot be corrected by error correction using the inner code. The outer code can be, for example, a BCH code capable of correcting 4 bits. Since there is a possibility of miscorrection occurring during decoding using the outer code (removal of residual errors), a determination process may be performed to determine whether miscorrection has occurred. The inner code can be, for example, a multidimensional error correction code.

[0025] Here, a multidimensional error-correcting code refers to one in which at least one symbol, which is a constituent unit of the error-correcting code, is multiply protected by multiple smaller component codes. One symbol is composed of, for example, one bit (an element of a binary field) or an alphabet element of a finite field other than a binary field. For ease of explanation, the following explanation will use an example of a binary error-correcting code in which one symbol is composed of one bit. While the terms symbol and bit may be used interchangeably in some places in the explanation, they both mean the same thing.

[0026] An example of a multidimensional error correcting code is a product code. A product code has a structure in which, for example, each information symbol, which is a constituent unit of user data, is protected by a BCH code including parity symbols of a predetermined parity length in both the row and column directions. That is, in a product code, all symbols are doubly protected by component codes in the row direction (referred to as dimension 1) and the column direction (referred to as dimension 2). Note that the multidimensional error correcting code is not limited to this, and may be, for example, a generalized low density parity check code (LDPC code). In general multidimensional error correcting codes, including generalized LDPC codes, the degree of protection may differ for each symbol, and component codes cannot be grouped into dimension 1 and dimension 2, but the present technology can also be applied to such code configurations.

[0027] For simplicity, the following describes an example using a two-dimensional error-correcting code (product code) in which each symbol is protected by two component codes that can be grouped into dimension 1 and dimension 2. Each component code for each dimension includes one or more component codes determined for that dimension. Hereinafter, component codes corresponding to each dimension and including one or more component codes may be referred to as a component code group. For example, the component code group for dimension 1 includes n1 component codes, and the component code group for dimension 2 includes n2 component codes. Applicable error-correcting codes are not limited to this, and may be an N-dimensional error-correcting code in which at least one symbol constituting the code is protected by N component code groups (N is an integer equal to or greater than 2). When expressed in terms of the number of component codes included in each component code group, an N-dimensional error-correcting code is protected by M component codes (M is the sum of n i (1≦i≦N), N is an integer equal to or greater than 2, and n i is the number of component codes in the i-th dimension).

[0028] An example of an outer code and an inner code will be described using Figure 2. Note that Figure 2 shows an example in which a two-dimensional block product code including five blocks in the row direction and six blocks in the column direction is used as the inner code. Each block includes multiple symbols that make up the code. Each block corresponds to a symbol group, which is a collection of multiple symbols that make up the code. The number of blocks in each direction is not limited to the example shown in Figure 2. For example, in the following figures, a two-dimensional block product code including four blocks in each of the row and column directions may be described as the inner code.

[0029] 2, the encoder 17 first encodes the user data 210 into an outer code 220. The outer code 220 includes the user data 210 and an outer code parity 221. Next, the encoder 17 encodes the outer code 220 into an inner code 230. The inner code 230 includes the outer code 220, a row-wise parity 231 of the inner code, and a column-wise parity 232 of the inner code.

[0030] The inner code is, for example, a two-dimensional block product code whose component codes are BCH codes capable of correcting 3 bits. In the example of Figure 2, five component codes in the row direction (dimension 1) and six component codes in the column direction (dimension 2) are BCH codes capable of correcting 3 bits.

[0031] The outer code can be interpreted as having the following main roles. -Removal of errors that cannot be corrected by the inner code (residual errors) · Determine whether errors remain in the user data: If no errors remain, decryption is successful and the process ends.

[0032] Depending on the pattern of errors that occur, errors may not be eliminated even when an outer code is used, resulting in an error floor. Figure 3 shows an example of a situation in which errors cannot be eliminated even when an outer code is used.

[0033] In the example of Figure 3, as described above, the inner code is a product code whose component codes are BCH codes capable of correcting 3 bits, and the outer code is a BCH code capable of correcting 4 bits. The numbers in Figure 3 indicate the number of errors contained in the corresponding block. Note that RS codes may be used as the inner and outer codes instead of BCH codes.

[0034] For example, intersection 301, which is the block where the component code in the third row and the component code in the third column intersect (a block included in both component codes), contains six errors. Because the number of errors exceeds the number of correctable bits (3 bits) for the component codes, the syndrome for the component codes in the third row and third column is unsatisfactory. Furthermore, because the number of errors in intersection 301 exceeds the number of correctable bits (4 bits) for the outer code, the errors cannot be removed even if the outer code is used. In this situation where errors are concentrated at one intersection, the errors cannot be removed even if the outer code is used.

[0035] Such a situation may occur, for example, in a configuration that uses an outer code with reduced correction capability to improve overall decoding performance. In this embodiment, even in such a configuration, error correction (decoding) can be performed with high accuracy.

[0036] In this embodiment, the case where the number of intersections where an error is included in any of the component codes of each dimension (hereinafter referred to as error intersections) is 1 is targeted. An example where the number of error intersections is equal to or less than a threshold (number threshold) of 2 or more is targeted will be described in the second embodiment.

[0037] In this embodiment, if decoding using the outer code fails and only one error crossing is identified, the value of the bit in the error crossing is flipped and decoding using the outer code is further performed. For example, MBFD (Multi-Bit Flip Decoding) can be applied as such a technique.

[0038] By inverting the bit values, the number of errors in the error crossing can be reduced to the number of errors that can be corrected by the outer code. The more bits to be inverted (the number of inversions), the higher the chance of successful correction, but the amount of processing increases. Therefore, it is desirable to determine the number of inversions according to the correction capability of the outer code, the block size, the allowable amount of processing, etc.

[0039] Next, a configuration example of the decoder 18 will be described. Fig. 4 is a block diagram showing a schematic configuration example of the decoder 18 of the first embodiment. As shown in Fig. 4, the decoder 18 includes a read information memory 121, an outer code syndrome memory 122, an inner code syndrome memory 123, a decoder 101, an intersection identifying unit 102, a selecting unit 103, and a correcting unit 104.

[0040] The read information memory 121 is realized, for example, by an SRAM. The outer code syndrome memory 122 and the inner code syndrome memory 123 are realized, for example, by registers. The decoder 101, the intersection identifying unit 102, the selecting unit 103, and the correcting unit 104 are realized by at least one of a register, an adder, a multiplier, and other computing units. The register is realized, for example, by a logic circuit such as a flip-flop. The adder, the multiplier, the selector, and other computing units are realized, for example, by a logic circuit.

[0041] The read information memory 121 is a memory that stores read information, which is data read from the nonvolatile memory 20.

[0042] The outer code syndrome memory 122 is a memory that stores a syndrome SD1 of the outer code calculated in a decoding process DEC1 (first decoding process) using the outer code. The inner code syndrome memory 123 is a memory that stores a plurality of syndromes SD2 for a plurality of component codes calculated in a decoding process DEC2 (second decoding process) using the inner code. The syndromes are information that can be used to determine whether or not there is an error in the read information. For example, if the values ​​of all the syndromes are 0, it is determined that there is no error in the read information.

[0043] The decoder 101 executes a decoding process DEC1 using an outer code and a decoding process DEC2 using an inner code. For example, the decoder 101 first executes the decoding process DEC2 using the inner code on the read information. If the decoding process DEC2 fails, the decoder 101 executes the decoding process DEC1 using the outer code on the read information reflecting the correction result by the decoding process DEC2. The decoding process DEC1 is, for example, bounded distance decoding. The decoder 101 stores the read information after executing each decoding process in the read information memory 121.

[0044] When the decoding process DEC1 using the outer code fails, the intersection identifying unit 102 identifies an intersection (error intersection) where an error is contained in both component codes of two or more different dimensions. When a two-dimensional error correcting code (product code) is used, a block where an error is contained in both a component code included in a component code group of dimension 1 (row direction) and a component code included in a component code group of dimension 2 (column direction) corresponds to an error intersection.

[0045] The intersection identifying unit 102 identifies an error intersection using characteristic information indicating the accuracy of correction by the inner code (error correction code C2). The characteristic information is, for example, the syndrome SD2 of the inner code. In this case, the intersection identifying unit 102 identifies a block in which both the syndrome SD2 of the row-direction component code and the syndrome SD2 of the column-direction component code are unsatisfied as an error intersection.

[0046] The feature information is not limited to the syndrome SD2. For example, when reliability (probability information) indicating the degree to which the correction result for each component code of the inner code (error-correcting code C2) is correct is obtained, the intersection identifying unit 102 may use the reliability as the feature information. In this case, the intersection identifying unit 102 identifies, for example, a block in which the reliability of the component code in the row direction and the reliability of the component code in the column direction are both equal to or less than a threshold (reliability threshold) as an error intersection.

[0047] The selection unit 103 selects one or more bits to be corrected from the identified error crossing. The correction unit 104 executes a correction process to correct the selected bits. For example, the correction process is a process of inverting the selected bits. After the correction process is executed, the decoder 101 further executes a decoding process DEC1. The above processes by the selection unit 103, the correction unit 104, and the decoder 101 are repeatedly executed until the decoding process DEC1 is successful or until bits are corrected in all patterns.

[0048] The processing by the selection unit 103 will be further described. For example, the selection unit 103 determines an inversion number equal to or less than a predetermined maximum value (for example, 3 bits). The selection unit 103 determines an inversion pattern based on the determined inversion number, and selects bits to be corrected (inverted) from among bits included in the error crossing according to the determined pattern. The selection unit 103 selects bits to be corrected for all inversion numbers and all patterns corresponding to the inversion numbers until the decoding process DEC1 is successful.

[0049] For example, if the maximum value is 3 bits, the selection unit 103 determines the number of inversions in the order of 1 bit, 2 bits, and 3 bits. If the number of inversions is determined to be 1 bit, the selection unit 103 determines one of the patterns for inverting one bit among the multiple bits in the error crossing. If the determined pattern is a pattern for inverting the first bit, the selection unit 103 selects the first bit. If the decoding process DEC1 after correcting the selected first bit is not successful, the selection unit 103 further determines a pattern for inverting another bit (for example, the second bit).

[0050] If the decoding process DEC1 is unsuccessful after all patterns with one inversion bit have been tried, the selection unit 103 determines the number of inversion bits to be two, and repeats the same process for patterns that invert two bits. If the decoding process DEC1 is unsuccessful after all patterns with two inversion bits have been tried, the selection unit 103 determines the number of inversion bits to be three, and repeats the same process for patterns that invert three bits. Note that if the decoding process DEC1 is unsuccessful after all patterns with the maximum number of inversion bits have been tried, it is determined that the decoding has failed.

[0051] The process of correcting (inverting) the selected bits and re-executing the decoding process DEC1 may be realized by the following process. First, the decoder 18 generates data of the same size (number of elements) as the syndrome SD2 of the outer code, with elements corresponding to the selected bits set to 1 and other elements set to 0. The decoder 18 corrects the syndrome SD2 by calculating the exclusive OR (XOR) of the generated data and the syndrome SD2 before correction. The decoder 18 executes the decoding process DEC1 using the corrected syndrome SD2.

[0052] An example of successful decoding according to this embodiment will be described. Fig. 5 is a diagram showing an example of successful decoding. Fig. 5 corresponds to an example in which decoding is successful by inverting bits and executing decoding process DEC1 in a situation where errors cannot be removed even by using an outer code (for example, Fig. 3).

[0053] For example, in this embodiment, when the decoding process DEC1 fails and the situation shown in FIG. 3 occurs, the intersection identifying unit 102 identifies the intersection 301 as an error intersection using the syndrome SD2 of the inner code.

[0054] Assume that the size of intersection portion 301 is 9 bits. Assume also that six bits, the 1st, 3rd, 5th, 6th, 8th, and 9th bits, of intersection portion 301 are incorrect, as shown in Fig. 5. Assume also that selection portion 103 selects the 1st and 3rd bits by using a pattern that inverts the 1st and 3rd bits from among two-bit inversion patterns.

[0055] 5 shows the state after the first and third selected bits have been corrected by the correction unit 104. The intersection 301b contains four errors at the fifth, sixth, eighth, and ninth bits. Therefore, decoding is successful using the outer code that can correct four bits.

[0056] Next, a description will be given of the flow of the decryption process performed by the memory system 1 of this embodiment. Fig. 6 is a flowchart showing an example of the decryption process of the first embodiment.

[0057] The control unit 11 reads out the error correction code from the nonvolatile memory 20 to obtain read information (step S101). The control unit 11 transfers the read information to the read information memory 121 and stores it there.

[0058] Next, the decoder 18 executes a decoding process DEC2 using the inner code (step S102). When a product code such as that shown in Fig. 2 is used as the inner code, the decoder 18 executes the decoding process DEC2 by, for example, repeatedly decoding component codes in the row direction (dimension 1) and decoding component codes in the column direction (dimension 2). In this case, step S102 in Fig. 6 corresponds to decoding component codes for one dimension (dimension 1 or dimension 2).

[0059] When the decoder 18 finishes decoding one-dimensional component code, it executes a process of checking whether there is a residual error using the outer code (step S103). The checking process is, for example, a process of checking whether there is an error in the read information (there is no residual error) using the outer code. For example, the checking process is executed to check whether there is an error remaining in the user data portion using the syndrome SD1 of the outer code every time each component code of the inner code is decoded.

[0060] The decoder 18 determines whether the result of the check process (check result) indicates that there are no residual errors (step S104). If it is determined that the check result indicates that there are no residual errors (that there are residual errors) (step S104: No), the decoder 18 (decoder 101) executes bounded distance decoding (decoding process DEC1) using the outer code (step S105). The decoder 18 determines whether the decoding by the decoding process DEC1 is successful (step S106).

[0061] If it is determined that the decoding by the decoding process DEC1 has failed (step S106: No), the intersection identifying unit 102 identifies error intersections where the syndrome of the inner code is unsatisfied, and counts the number of identified intersections (step S107).

[0062] The decoder 18 determines whether the number of intersections is 1 (step S108). If the number of intersections is 1 (step S108: Yes), the selection unit 103 selects one or more bits to be corrected from the error intersections (step S109). The correction unit 104 executes a correction process to correct the selected bits (step S110). After the correction process is executed, the decoder 101 further executes a decoding process DEC1 (step S111). The decoder 18 determines whether the decoding by the decoding process DEC1 is successful (step S112).

[0063] If it is determined that the decoding by the decoding process DEC1 is successful (step S112: Yes), if the inspection result in step S104 is determined to be no residual error (step S104: Yes), or if it is determined that the decoding by the decoding process DEC1 is successful in step S106 (step S106: Yes), the decoder 18 notifies an external control unit or the like of the success of the decoding and the decoded word (step S115), and terminates the decoding process.

[0064] If it is determined that the decoding by the decoding process DEC1 has failed (step S112: No), the decoder 18 determines whether all the inversion patterns have been tried (step S113). If all the patterns have not been tried (step S113: No), the process returns to step S109, and the process is repeated for the unprocessed patterns.

[0065] When all patterns have been tried (step S113: Yes), or when it is determined in step S108 that the number of intersections is not 1 (step S108: No), the decoder 18 notifies an external control unit or the like of a decoding failure (step S114), and terminates the decoding process.

[0066] (Second embodiment) In the first embodiment, when the number of error crossings is one, the value of the bit in the error crossing is inverted, and decoding using the outer code is further performed. In the second embodiment, an example in which the number of error crossings is four or less will be described. This embodiment can be interpreted as an example in which the threshold value compared with the number of error crossings is four. The value of the threshold is not limited to four, and may be any other value. Note that the first embodiment can be interpreted as an example in which the threshold value is one.

[0067] In this embodiment, the selector 103 selects one or more bits to be corrected from one or more and four or less error crossings. When one error crossing is identified, the processing is the same as in the first embodiment. When multiple (two to four) error crossings are identified, the selector 103 selects one error crossing from the multiple error crossings and selects a bit from the selected error crossing.

[0068] For example, when the reliability of correction for each bit is obtained, the selection unit 103 may use one of the following methods to select an error crossing point based on the comparison result of the reliability. The minimum values ​​of the reliability of multiple bits included in the error crossing are compared, and the error crossing with the smallest minimum value is selected. The sum of a predetermined number of reliabilities of the bits included in the error crossing is compared in ascending order of reliabilities, and the error crossing with the smallest sum is selected. The predetermined number may be determined, for example, according to the maximum number of inversions or the correction capability of the outer code. ·Compare the sum of the reliability of all bits included in the error crossing and select the error crossing with the smaller sum.

[0069] The selection condition is not limited to reliability, and may be any other condition. If the condition of multiple error intersections is the same, the selection unit 103 may select any of the error intersections. If the condition of multiple error intersections is the same, the selection unit 103 may select bits from the multiple error intersections so as to be as even as possible. Furthermore, the selection unit 103 may select a number of bits from each of the multiple error intersections weighted by the reliability of each error intersection calculated as described above (such as the minimum reliability, the sum of a specified number of reliability, or the sum of the reliability of all bits).

[0070] The decryption process of this embodiment can be realized by, for example, modifying the decryption process of the first embodiment (FIG. 6) as follows. In step S108, the decoder 18 determines whether the number is equal to or less than a threshold (four or less in the above example). If multiple error crossings are identified, in step S109, the selector 103 selects one error crossing from the multiple error crossings, and selects a bit from the selected error crossing.

[0071] 7 is a diagram showing an example of an error occurrence situation to which this embodiment is applied. In the example of FIG. 7, the syndromes of the component codes in the second row, fourth row, first column, and third column are unsatisfied. Therefore, the number of error crossings is four. Because the number of error crossings is below the threshold (four or less), the procedure of this embodiment inverts the values ​​of the bits in the error crossings, and further performs decoding using the outer code.

[0072] (Third embodiment) The number of all inversion patterns varies depending on the maximum size of the error crossing (block) and the correction capability of the outer code. For example, suppose the size of the error crossing is 15 bits and the correction capability of the outer code is 4 bits. In order to correct a maximum of 15 bits, it is necessary to try a maximum of 11 bit (= 15 bits - 4 bits of the correction capability of the outer code) inversion patterns. The total number of inversion patterns from 1 bit to 11 bits is as follows for k = 1 to 11: 15 C k This is the sum of (the number of combinations of selecting k items from 15), which is 32191.

[0073] When the number of patterns is large like this, trying all patterns can place an excessive load on the decoding process, which can cause delays. If the system is configured to try only some of the patterns in order to reduce the load, the decoding process is more likely to fail.

[0074] In this embodiment, a method for reducing the total number of patterns to be tried is described. This allows for more efficient decoding and improved decoding accuracy. Specifically, in this embodiment, after inverting all bits at the error crossing (hereinafter referred to as "all bit inversion"), a process for inverting selected bits is added.

[0075] For example, the decoder 18 executes the decoding process DEC1 for all patterns in the same procedure as in the above embodiment (which may be either the first embodiment or the second embodiment). If the decoding process DEC1 is unsuccessful, the decoder 18 performs all bit inversion at the error crossings and then executes the same procedure as in the above embodiment.

[0076] Fig. 8 is a flowchart showing an example of the decoding process of the third embodiment. This embodiment differs from Fig. 6 showing the decoding process of the first embodiment in that steps S214 to S221 are added. Note that Fig. 8 corresponds to an example in which the first embodiment is modified, but a similar modification may be applied to the second embodiment.

[0077] Steps S201 to S213 are the same as steps S101 to S113 in FIG.

[0078] In this embodiment, if all patterns have been tried (step S213: Yes), the decoder 18 performs all bit inversion at the error crossing (step S214) and further performs the decoding process DEC1 (step S215). The decoder 18 determines whether the decoding by the decoding process DEC1 is successful (step S216).

[0079] If it is determined that the decoding by the decoding process DEC1 has failed (step S216: No), the decoder 18 executes the same procedures as steps S209 to S213 in steps S217 to S221 using the error crossing after all bit inversion has been performed.

[0080] If it is determined in step S221 that all patterns have been tried (step S221: Yes), the decoder 18 notifies an external control unit or the like of a failure in decoding (step S222), and ends the decoding process.

[0081] If it is determined that the decoding by the decoding process DEC1 is successful (step S216: Yes, step S220: Yes), the decoder 18 notifies an external control unit or the like of the successful decoding and the decoded word (step S223), and ends the decoding process.

[0082] In FIG. 8, the process without all bit inversion (steps S209 to S213) is followed by the process with all bit inversion (steps S214 to S221), but the order in which these processes are performed may be reversed.

[0083] Thus, in this embodiment, the correction process for correcting the selected bit includes a correction process for correcting the bit without inverting the bit included in the error intersection (first process, step S210, etc.), and a correction process for inverting the bit included in the error intersection and then correcting the bit (second process, step S218, etc.).

[0084] By including full bit inversion, the total number of patterns to be tried can be reduced. For example, if the size of the error crossing is I and the correction capability of the outer code is t bits, the maximum number of bits to be inverted, J, can be an integer that satisfies J ≥ max(floor(I / 2)-t,0).

[0085] For example, if the size of the error crossing is 15 bits and the correction capability of the outer code is 4 bits, floor(I / 2)-t=floor(15 / 2)-4=3, so J can be set to 3 (bits). Therefore, in this embodiment, in order to correct a maximum of 15 bits, it is sufficient to try two inversion patterns of up to 3 bits, one without all bit inversion and one with all bit inversion. In this case, the total number of inversion patterns is 15 C k This is twice the total (twice), which is 1150.

[0086] In this way, if the size of the error crossing is 15 bits and the correction capability of the outer code is 4 bits, all patterns can be tried by setting the maximum value of inversion to 3 (bits). In other words, all errors up to 15 bits can be corrected. Figure 9 is a diagram for explaining an example in which all patterns can be tried.

[0087] The numbers 0 to 15 represent the number of errors that can occur in a 15-bit block. If the number of errors is between 0 bits (no errors) and 4 bits, it is within the 4-bit correction capacity of the outer code, so it can be corrected without inverting any of the bits and without inverting (correcting) any of the bits. If the number of errors is between 5 bits and 7 bits, it can be corrected without inverting any of the bits, with inversion of up to 3 bits, and with 4-bit correction by the outer code. If the number of errors is between 8 bits and 10 bits, it can be corrected with inversion of all of the bits, with inversion of up to 3 bits, and with 4-bit correction by the outer code. If the number of errors is between 11 bits and 15 bits, it can be corrected with inversion of all of the bits, with no inversion of any of the bits, and with 4-bit correction by the outer code.

[0088] In this way, in this embodiment, by appropriately determining the maximum value of bit inversion depending on the size of the error crossing and the correction capability of the outer code, it becomes possible to correct all errors up to the maximum size that can occur at the error crossing.

[0089] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0090] 1. Memory System 10 Memory Controller 11 Control section 12 Data Buffers 13 Memory I / F 14 Encoding / Decoding Unit 15 Host I / F 16 Internal Bus 17 Encoder 18 Decoder 20 Non-volatile memory 30 hosts 101 Decoder 102 Intersection specific section 103 Selection section 104 Correction section 121 Readout information memory 122 Outer code syndrome memory 123 Inner code syndrome memory

Claims

1. a non-volatile memory for storing a concatenated code obtained by: a first error-correcting code generated using data to be stored; and a second error-correcting code, which is an N-dimensional error-correcting code in which at least one symbol among symbols constituting the code is protected by N component code groups (N is an integer of 2 or more), and which is generated using the first error-correcting code; reading read information from the nonvolatile memory; performing a second decoding process on the read information using the second error correction code; If the decoding by the second decoding process fails, a first decoding process is performed using the first error correction code on the read information reflecting the correction result by the second decoding process; If the decoding by the first decoding process fails, an intersection where an error is included in both of the component codes of two or more different dimensions is identified; performing a correction process for correcting the symbol included in the intersection, and then further performing the first decoding process; A memory controller; A memory system comprising:

2. The memory controller If the number of the intersections is equal to or less than a threshold, the symbols included in the intersections are corrected and the first decoding process is further performed.

10. The memory system of claim 1.

3. the symbols are bits, the modification process includes a first process of modifying the bit included in the intersection without inverting the bit, and a second process of modifying the bit after inverting the bit included in the intersection.

10. The memory system of claim 1.

4. When the size of the intersection is I and the correction capability of the first error-correcting code is t bits, the maximum value J of the number of bits to be inverted satisfies J≧max(floor(I / 2)−t, 0).

4. The memory system of claim 3.

5. The memory controller identifying the intersection using feature information indicating the correctness of the correction by the second error-correcting code; 10. The memory system of claim 1.

6. the characteristic information is a syndrome of a component code included in the component code group; 6. The memory system of claim 5.

7. the characteristic information is a reliability indicating a degree to which a correction result of a component code included in the component code group is a correct correction; 6. The memory system of claim 5.

8. the first error-correcting code and each of the N component code sets are Bose-Chaudhuri-Hocquenghem (BCH) codes; 10. The memory system of claim 1.

9. the first error-correcting code and each of the N component code groups are Reed-Solomon (RS) codes; 10. The memory system of claim 1.

10. reading out information from a nonvolatile memory that stores a concatenated code obtained by: a first error-correcting code generated using data to be stored; and a second error-correcting code, which is an N-dimensional error-correcting code in which at least one symbol among symbols constituting the code is protected by N component code groups (N is an integer of 2 or more), and which is generated using the first error-correcting code; performing a second decoding process on the read information using the second error correction code; If the decoding by the second decoding process fails, a first decoding process is performed using the first error correction code on the read information reflecting the correction result by the second decoding process; If the decoding by the first decoding process fails, an intersection where an error is included in both of the component codes of two or more different dimensions is identified; performing a correction process for correcting the symbol included in the intersection, and then further performing the first decoding process; Memory controller.

11. A control method using a memory controller that controls a nonvolatile memory that stores a concatenated code obtained by: a first error-correcting code generated using data to be stored; and a second error-correcting code that is an N-dimensional error-correcting code in which at least one symbol among symbols constituting the code is protected by N (N is an integer of 2 or more) component code groups, and that is generated using the first error-correcting code, reading read information from the nonvolatile memory; performing a second decoding process on the read information using the second error correction code; If the decoding by the second decoding process fails, a first decoding process is performed using the first error correction code on the read information reflecting the correction result by the second decoding process; If the decoding by the first decoding process fails, an intersection where an error is included in both of the component codes of two or more different dimensions is identified; performing a correction process for correcting the symbol included in the intersection, and then further performing the first decoding process; A control method comprising:

Images