Semiconductor Devices

Abstract

The present disclosure provides a low noise, low switching loss, and emitter-collector saturation voltage V CE An object of the present invention is to provide a semiconductor device capable of suppressing an increase in (sat). [Solution] A semiconductor device according to the present disclosure comprises a two-stage active dummy trench having a first upper electrode and a first lower electrode, and a two-stage active trench having a second upper electrode and a second lower electrode, the first upper electrode, the second upper electrode, and the second lower electrode being connected to the same gate pad, the two-stage active dummy trench and the two-stage active trench extending horizontally in a plan view, and within the overall horizontal length of the two-stage active dummy trench and the two-stage active trench, the length of the region where the two-stage active dummy trench and the two-stage active trench are adjacent is longer than the length of the region where the two-stage active dummy trench and the two-stage active trench are not adjacent.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device whose conduction is controlled by a gate signal. [Background technology]

[0002] Conventionally, semiconductor devices have been disclosed that include a two-stage active dummy trench having an upper electrode at the upper stage where the gate potential is at a gate potential and a lower electrode at the lower stage where the potential is not the gate potential (see, for example, Patent Documents 1 to 5). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-12813 [Patent Document 2] Japanese Patent Publication No. 2022-145318 [Patent Document 3] Japanese Patent Publication No. 2021-184443 [Patent Document 4] Japanese Patent Publication No. 2021-150538 [Patent Document 5] Japanese Patent Publication No. 2023-37881 Summary of the Invention [Problem to be solved by the invention]

[0004] When the semiconductor device is an IGBT (Insulated Gate Bipolar Transistor), the gate capacitance ratio Cgc / Cge is significantly reduced, realizing low noise and low switching loss. However, an N+ layer cannot be formed around the lower electrode in the two-stage active dummy trench. Therefore, an N+ layer barrier that accumulates holes injected from the backside of the semiconductor on the front side cannot be formed, and conductivity modulation cannot be promoted, resulting in a low emitter-collector saturation voltage V CEThere is a problem specific to IGBTs in that (sat) increases, where Cgc is the capacitance between the gate electrode and collector electrode, and Cge is the capacitance between the gate electrode and emitter electrode.

[0005] The present disclosure has been made to solve such problems, and provides a diode with low noise, low switching loss, and a low emitter-collector saturation voltage V CE An object of the present invention is to provide a semiconductor device capable of suppressing an increase in (sat). [Means for solving the problem]

[0006] In order to solve the above problems, a semiconductor device according to the present disclosure includes a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface, at least one two-stage active dummy trench provided inside the trench on the first main surface side of the semiconductor substrate, the two-stage active dummy trench having a first upper electrode at a gate potential on the upper stage and a first lower electrode at an emitter potential on the lower stage, and at least one two-stage active trench provided inside the trench on the first main surface side of the semiconductor substrate, the two-stage active trench having a second upper electrode at a gate potential on the upper stage and a second lower electrode at a gate potential on the lower stage. and a semiconductor layer of a second conductivity type provided on the second main surface side of the semiconductor substrate, the first upper electrode, the second upper electrode, and the second lower electrode are connected to the same gate pad, the two-stage active dummy trench and the two-stage active trench extend in the horizontal direction in plan view, and within the overall horizontal length of the two-stage active dummy trench and the two-stage active trench, the length of a region where the two-stage active dummy trench and the two-stage active trench are adjacent is longer than the length of a region where the two-stage active dummy trench and the two-stage active trench are not adjacent. [Effects of the Invention]

[0007] According to the present disclosure, a low noise, low switching loss, and emitter-collector saturation voltage V CE It is possible to suppress the increase in (sat). [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 3] FIG. 3 is an enlarged view of a portion of FIG. 2. [Figure 4] FIG. 10 is a cross-sectional view of a semiconductor device according to a first modification. [Figure 5] FIG. 10 is a cross-sectional view of a semiconductor device according to a second modification. [Figure 6] FIG. 13 is a cross-sectional view of a semiconductor device according to a sixth modification. [Figure 7] FIG. 13 is a cross-sectional view of a semiconductor device according to a seventh modification. [Figure 8] FIG. 13 is a cross-sectional view of a semiconductor device according to Modification 8. [Figure 9] FIG. 13 is a cross-sectional view of a semiconductor device according to a ninth modification. [Figure 10] FIG. 20 is a cross-sectional view of a semiconductor device according to a tenth modification. [Figure 11] FIG. 20 is a cross-sectional view of a semiconductor device according to an eleventh modification. [Figure 12] FIG. 20 is a cross-sectional view of a semiconductor device according to a twelfth modification. [Figure 13] FIG. 22 is a cross-sectional view of a semiconductor device according to a thirteenth modification. [Figure 14] FIG. 20 is a cross-sectional view of a semiconductor device according to a fourteenth modification. [Figure 15] FIG. 20 is a cross-sectional view of a semiconductor device according to a fifteenth modification. [Figure 16] FIG. 20 is a cross-sectional view of a semiconductor device according to Modification 18. [Figure 17] FIG. 20 is a cross-sectional view of a semiconductor device according to a nineteenth modification. DETAILED DESCRIPTION OF THE INVENTION

[0009] <First Embodiment> A semiconductor device according to a first embodiment will be described below with reference to the drawings. The semiconductor device is an IGBT. Note that identical or corresponding components are denoted by the same reference numerals, and repeated description may be omitted. In the following description, N and P indicate the conductivity type of a semiconductor. In this disclosure, the first conductivity type will be described as N-type, and the second conductivity type will be described as P-type. These conductivity types may be reversed.

[0010] Fig. 1 is a cross-sectional view of a semiconductor device according to a first embodiment. In Fig. 1, the semiconductor substrate extends from the emitter layer 3 and contact layer 4 to the collector layer 6. In Fig. 1, the upper ends of the emitter layer 3 and contact layer 4 are referred to as the first main surface of the semiconductor substrate, and the lower end of the collector layer 6 is referred to as the second main surface of the semiconductor substrate. The first main surface and the second main surface face each other.

[0011] 1, a P-type base layer 2 is provided on the first main surface side of an N- type drift layer 1. An N+ type emitter layer 3 and a P+ type contact layer 4 are provided on the first main surface side of the base layer 2.

[0012] The semiconductor substrate is provided with at least one two-stage active dummy trench 7 that penetrates the emitter layer 3 and the base layer 2 and reaches the drift layer 1. Inside the trench provided on the first main surface side of the semiconductor substrate, the two-stage active dummy trench 7 has a first upper-stage electrode 8 that is at gate potential in the upper stage and a first lower-stage electrode 9 that is at emitter potential in the lower stage.

[0013] The semiconductor substrate is provided with at least one two-stage active trench 11 that penetrates the emitter layer 3 and the base layer 2 and reaches the drift layer 1. Inside the trench provided on the first main surface side of the semiconductor substrate, the two-stage active trench 11 has a second upper-stage electrode 12 that is at a gate potential in the upper stage and a second lower-stage electrode 13 that is also at a gate potential in the lower stage.

[0014] An N-type buffer layer 5 having a higher N-type impurity concentration than the drift layer 1 is provided on the second main surface side of the drift layer 1. A P-type collector layer 6 (semiconductor layer) is provided on the second main surface side of the buffer layer 5.

[0015] Fig. 2 is a plan view of the semiconductor device according to the first embodiment, and Fig. 3 is an enlarged view of a region A in Fig. 2.

[0016] As shown in Fig. 2, the two-stage active dummy trenches 7 and the two-stage active trenches 11 extend in the horizontal direction in the element region 15. Fig. 2 shows an example in which the two-stage active trenches 11, the two-stage active dummy trenches 7, and the two-stage active dummy trenches 7 are arranged in this order perpendicular to the horizontal direction, but this is not limitative. The two-stage active dummy trenches 7 and the two-stage active trenches 11 may be arranged appropriately as needed.

[0017] As shown in FIG. 3, in the total horizontal length of the two-stage active dummy trench 7 and the two-stage active trench 11 (the length between both ends of the two-stage active dummy trench 7 and the two-stage active trench 11), the length of a region 19 where the two-stage active dummy trench 7 and the two-stage active trench 11 are adjacent (the total horizontal length of the two adjacent regions 19) is longer than the length of a region 20 where the two-stage active dummy trench 7 and the two-stage active trench 11 are not adjacent (the horizontal length of the non-adjacent region 20).

[0018] A gate pad 16 is provided in the element region 15. The first upper electrode 8 of the two-stage active dummy trench 7 and the second upper electrode 12 and second lower electrode 13 of the two-stage active trench 11 are connected to the gate pad 16.

[0019] The gate wiring region 17 is provided so as to surround the element region 15, and is connected to the gate pad 16. The termination region 18 is provided so as to surround the gate wiring region 17.

[0020] According to the first embodiment, an N+ layer is formed around the second lower electrode 13 in the two-stage active trench 11. Therefore, in addition to the effects of low noise and low switching loss obtained by providing the two-stage active dummy trench 7, the emitter-collector saturation voltage V CE It is possible to suppress the increase in (sat).

[0021] Furthermore, by arranging the two-stage active dummy trenches 7 and the two-stage active trenches 11 in the horizontal direction, it is possible to provide a high density region 19 where the two-stage active dummy trenches 7 and the two-stage active trenches 11 are adjacent to each other. Therefore, it is possible to make up for the weakness of the two-stage active dummy trenches 7 in terms of reduced carrier accumulation to the greatest extent possible.

[0022] <Variation 1> 4 is a cross-sectional view of a semiconductor device according to Modification 1. As shown in FIG. 4, in two-step active dummy trench 7, first oxide film 10 has a first boundary oxide film located between first upper electrode 8 and first lower electrode 9. In addition, in two-step active trench 11, second oxide film 14 has a second boundary oxide film located between second upper electrode 12 and second lower electrode 13.

[0023] The overhang width T1 is the width between the end face on the second major surface side of the base layer 2 and the end face on the second major surface side of the second upper electrode 12. The overhang width T1 is longer than the film thickness T2 of the second boundary oxide film.

[0024] 4 shows the relationship between the overhang width T1 in the two-step active trench 11 and the film thickness T2 of the second boundary oxide film, but the same applies to the two-step active dummy trench 7. That is, the overhang width, which is the width between the end face on the second main surface side of the base layer 2 and the end face on the second main surface side of the first upper-stage electrode 8, is longer than the film thickness of the first boundary oxide film.

[0025] According to the first modification, the carrier accumulation effect can be improved by increasing the protruding width of each of the two-step active dummy trench 7 and the two-step active trench 11. In particular, the carrier accumulation effect can be improved by increasing the protruding width of the two-step active dummy trench 7.

[0026] In addition, as in the two-stage active trench 11 shown in FIG. 4, when the thickness of the second lower oxide film covering the second lower electrode 13 of the second oxide film 14 is thicker than the thickness of the second upper oxide film covering the second upper electrode 12, the emitter-collector saturation voltage V CE This is because the area where the second upper oxide film, which is thinner, protrudes increases, making it easier for an N+ layer to form.

[0027] <Variation 2> Fig. 5 is a cross-sectional view of a semiconductor device according to Modification 2. As shown in Fig. 5, in the semiconductor device according to Modification 2, a length T3 between the two-step active dummy trench 7 and the two-step active trench 11 is shorter than a length T4 between the end face on the second main surface side of the base layer 2 and the end face on the second main surface side of the two-step active trench 11.

[0028] 5 shows the relationship between the length T3 between the two-step active dummy trench 7 and the two-step active trench 11 and the length T4 between the end face on the second main surface side of the base layer 2 and the end face on the second main surface side of the two-step active trench 11, but the same applies to the two-step active dummy trench 7. In other words, the length T3 between the two-step active dummy trench 7 and the two-step active trench 11 is shorter than the length between the end face on the second main surface side of the base layer 2 and the end face on the second main surface side of the two-step active dummy trench 7.

[0029] According to the second modification, electrons diffused in a 45° direction from the channel of the two-step active dummy trench 7 reach the two-step active trench 11, thereby improving the carrier accumulation effect of the two-step active trench 11.

[0030] <Variation 3> In the semiconductor device according to the third modification, the number of two-stage active trenches 11 is the same as the number of two-stage active dummy trenches 7.

[0031] According to the third modification, the carrier accumulation effect can be improved.

[0032] <Variation 4> In the semiconductor device according to the fourth modification, the number of two-step active trenches 11 is greater than the number of two-step active dummy trenches 7. For example, the ratio of the number of two-step active trenches 11 to the number of two-step active dummy trenches 7 is 6:4 or more, and preferably 10:1 or less.

[0033] According to the fourth modification, the carrier accumulation effect can be improved.

[0034] <Variation 5> In the semiconductor device according to the fifth modification, the number of two-step active trenches 11 is smaller than the number of two-step active dummy trenches 7. For example, the ratio between the number of two-step active trenches 11 and the number of two-step active dummy trenches 7 is 1:10 or more and 4:6 or less.

[0035] According to the fifth modification, it is possible to reduce both the switching loss and the DC (Direct Current Loss) loss by increasing the number of two-stage active dummy trenches 7. Here, the DC loss refers to the loss that occurs due to the resistance of a device when a current passes through the device.

[0036] <Variation 6> Fig. 6 is a cross-sectional view of a semiconductor device according to Modification 6. As shown in Fig. 6, the semiconductor device according to Modification 6 further includes a carrier accumulation layer 21. The carrier accumulation layer 21 is provided on the first main surface side of the drift layer 1.

[0037] According to the sixth modification, the carrier accumulation layer 21 is provided, thereby improving the carrier accumulation effect. CE The increase in (sat) can be suppressed more effectively than in the first embodiment and the first to fifth modifications.

[0038] The carrier accumulation layer 21 in the sixth modification is also applicable to the first embodiment and other modifications.

[0039] <Variation 7> 7 is a cross-sectional view of a semiconductor device according to Modification 7. As shown in FIG. 7, in the two-stage active dummy trench 7, the first oxide film 10 has a first upper oxide film covering the first upper electrode 8 and a first lower oxide film covering the first lower electrode 9. In the two-stage active trench 11, the second oxide film 14 has a second upper oxide film covering the second upper electrode 12 and a second lower oxide film covering the second lower electrode 13.

[0040] In the two-stage active trench 11, the film thickness T5 of the second lower stage oxide film is thicker than the film thickness T6 of the second upper stage oxide film.

[0041] 7 shows the relationship between the thickness T5 of the second lower oxide film and the thickness T6 of the second upper oxide film, but the same applies to the two-stage active dummy trench 7. That is, the thickness of the first lower oxide film is thicker than the thickness of the first upper oxide film.

[0042] According to the seventh modification, by increasing the thickness of the second lower oxide film of the two-stage active trench 11, it is possible to suppress an increase in switching loss due to an increase in Cgc.

[0043] Furthermore, by making the first lower oxide film thicker than the first upper oxide film, the insulation between the first upper electrode 8 and the first lower electrode 9 is improved, and gate reliability such as TDDB (Time Dependent Dielectric Breakdown) is improved. The same effect can be obtained by making the second lower oxide film thicker than the second upper oxide film.

[0044] <Variation 8> 8 is a cross-sectional view of a semiconductor device according to Modification 8. As shown in Fig. 8, in two-stage active trench 11, second lower electrode 13 has a depth length T7 longer than second upper electrode 12 has a depth length T8 longer than second upper electrode 12. This narrows the area of ​​second upper electrode 12 that is covered with the thin second upper oxide film.

[0045] In the two-stage active dummy trench 7, the length in the depth direction of the first lower-stage electrode 9 is longer than the length in the depth direction of the first upper-stage electrode 8. This narrows the Cgc connection region of the first upper-stage electrode 8.

[0046] According to the eighth modification, an increase in switching loss due to an increase in Cgc can be suppressed.

[0047] <Variation 9> 9 is a cross-sectional view of a semiconductor device according to Modification 9. As shown in Fig. 9, in the two-stage active trench 11, the length T7 of the second lower electrode 13 in the depth direction is shorter than the length T8 of the second upper electrode 12 in the depth direction. Furthermore, in the two-stage active dummy trench 7, the length of the first lower electrode 9 in the depth direction is shorter than the length of the first upper electrode 8 in the depth direction.

[0048] According to the ninth modification, the N+ layer is deepened by increasing the depth direction length of the first upper-stage electrode 8 of the two-stage active dummy trench 7. In addition, when the second upper-stage oxide film is thin as shown in FIG. 9, the region in the two-stage active trench 11 where the second upper-stage oxide film is thin (the region where the N+ layer is likely to be formed) also becomes deeper. Therefore, the emitter-collector saturation voltage V CEThe increase in (sat) can be suppressed more effectively than in the first embodiment and the first to eighth modifications.

[0049] <Modification 10> 10 is a cross-sectional view of a semiconductor device according to Modification 10. As shown in FIG. 10, in a two-stage active trench 11, a second upper-stage electrode 12 has a first portion 22 and a second portion 23 that form a concave shape toward the first main surface. The second portion 23 is formed to protrude from the surface of the first portion that faces the second main surface. The second lower-stage electrode 13 has a convex portion that forms a convex shape toward the first main surface.

[0050] Similarly, in the two-stage active dummy trench 7, the first upper-stage electrode 8 has a first portion and a second portion that form a concave shape toward the first principal surface, and the first lower-stage electrode 9 has a convex portion that forms a convex shape toward the first principal surface.

[0051] According to the modification 10, an N+ layer is formed around the second portion in addition to the first portion. Therefore, the N+ layer formed in the two-stage active dummy trench 7 becomes deeper. Furthermore, when the second upper-stage oxide film is thin as shown in FIG. 10, the region in the two-stage active trench 11 where the second upper-stage oxide film is thin (the region where the N+ layer is likely to be formed) also becomes deeper. Therefore, the emitter-collector saturation voltage V CE The increase in (sat) can be suppressed more effectively than in the first embodiment and the first to ninth modifications.

[0052] <Variation 11> Fig. 11 is a cross-sectional view of a semiconductor device according to Modification 11. As shown in Fig. 11, in the semiconductor device according to Modification 11, two or more two-step active dummy trenches 7 are provided adjacent to each other, and two or more two-step active trenches 11 are provided adjacent to each other. Note that, although the example of Fig. 11 shows two each of the two-step active dummy trenches 7 and two-step active trenches 11, there may be three or more each.

[0053] In the two-stage active trench 11, an N+ layer is formed around the second lower electrode 13. Therefore, by providing the two-stage active trenches 11 adjacent to each other, the carrier accumulation effect can be improved, and the emitter-collector saturation voltage V CE The increase in (sat) can be suppressed more effectively than in the first embodiment and the first to fifth modifications.

[0054] <Variation 12> Fig. 12 is a cross-sectional view of a semiconductor device according to Modification 12. As shown in Fig. 12, the semiconductor device according to Modification 12 includes a first trench group 24 and a second trench group 25, each including a two-stage active dummy trench 7 and a two-stage active trench 11.

[0055] The first trench group 24 includes two two-stage active dummy trenches 7 and two two-stage active trenches 11, with the ratio of the two-stage active trenches 11 being 0.5. The second trench group 25 includes one two-stage active dummy trench 7 and three two-stage active trenches 11, with the ratio of the two-stage active trenches 11 being 0.75. In this way, the first trench group 24 and the second trench group 25 differ in the ratio of the two-stage active trenches 11 being included.

[0056] 12 shows a case where each of the first trench group 24 and the second trench group 25 includes four trenches, but this is not limited to this. Furthermore, the ratio of the two-stage active trenches 11 included in each of the first trench group 24 and the second trench group 25 is not limited to the example of FIG.

[0057] According to the twelfth modification, the emitter-collector saturation voltage V CEIt is possible to provide regions with different values ​​of (sat), thereby optimizing the number of two-stage active trenches 11. For example, the ratio of two-stage active trenches 11 included is increased in a group of trenches provided in the center of the chip (the center of the semiconductor device in a plan view) where heat is likely to be trapped, and the ratio of two-stage active trenches 11 included is decreased in a group of trenches provided in the periphery of the chip (the periphery of the semiconductor device in a plan view) where heat is likely to escape. This improves the effect of reducing switching loss by the two-stage active dummy trenches 7 and the emitter-collector saturation voltage V CE This can achieve both the effect of reducing (sat).

[0058] <Variation 13> 13 is a cross-sectional view of a semiconductor device according to Modification 13. As shown in Fig. 13, the semiconductor device according to Modification 13 has second trench groups 25 provided in the central portion and first trench groups 24 provided in the peripheral portion. The proportion of two-step active trenches 11 included in the second trench groups 25 is 0.75, and the proportion of two-step active trenches 11 included in the first trench groups 24 is 0.5. In other words, the proportion of two-step active trenches 11 included in the second trench groups 25 provided in the central portion is higher than the proportion of two-step active trenches 11 included in the first trench groups 24 provided in the peripheral portion.

[0059] When a semiconductor device operates at a low frequency, the number of times the semiconductor device is switched is small, and therefore the switching loss is small. In such a semiconductor device, it is effective to prioritize DC loss over switching loss. According to Modification 13, the ratio of two-stage active trenches 11 included in the second trench group 25 provided in the central portion is made higher than the ratio of two-stage active trenches 11 included in the first trench group 24 provided in the outer periphery, thereby reducing DC loss.

[0060] <Variation 14> 14 is a cross-sectional view of a semiconductor device according to Modification 14. As shown in FIG. 14, the semiconductor device according to Modification 14 has a first trench group 24 provided in the central portion and a second trench group 25 provided in the peripheral portion. The ratio of the two-stage active dummy trenches 7 included in the first trench group 24 is 0.5, and the ratio of the two-stage active dummy trenches 7 included in the second trench group 25 is 0.25. In other words, the ratio of the two-stage active dummy trenches 7 included in the first trench group 24 provided in the central portion is higher than the ratio of the two-stage active dummy trenches 7 included in the second trench group 25 provided in the peripheral portion.

[0061] When a semiconductor device operates at a high frequency, the number of switching operations of the semiconductor device increases, resulting in increased switching loss. For such a semiconductor device, it is effective to prioritize switching loss. According to Modification 14, the ratio of two-stage active dummy trenches 7 included in the first trench group 24 provided in the central portion is set higher than the ratio of two-stage active dummy trenches 7 included in the second trench group 25 provided in the outer periphery, thereby reducing switching loss.

[0062] <Variation 15> 15 is a cross-sectional view of a semiconductor device according to Modification 15. As shown in FIG.

[0063] Specifically, the semiconductor substrate is provided with a one-step dummy trench 26 that penetrates the emitter layer 3 and the base layer 2 and reaches the drift layer 1. The one-step dummy trench 26 has, inside the trench provided on the first main surface side of the semiconductor substrate, a dummy electrode 27 and a dummy oxide film 28 that covers the dummy electrode 27. The dummy electrode 27 is at an emitter potential.

[0064] According to the fifteenth modification, holes are attracted to the dummy electrode 27, which is at the emitter potential, thereby increasing the hole density at the interface of the one-stage dummy trench 26. This makes it easier to discharge holes to the emitter electrode, thereby reducing turn-off loss.

[0065] <Variation 16> In the semiconductor device according to the sixteenth modification, the number of the one-stage dummy trenches 26 is smaller than the number of the two-stage active dummy trenches 7.

[0066] According to the sixteenth modification, by reducing the number of one-stage dummy trenches 26, the emitter-collector saturation voltage V CE The increase in (sat) can be suppressed.

[0067] <Variation 17> In the semiconductor device according to the seventeenth modification, the number of the one-stage dummy trenches 26 is smaller than the number of the two-stage active trenches 11.

[0068] According to the seventeenth modification, by reducing the number of one-stage dummy trenches 26, the emitter-collector saturation voltage V CE The increase in (sat) can be suppressed.

[0069] <Variation 18> Fig. 16 is a cross-sectional view of a semiconductor device according to Modification 18. As shown in Fig. 16, in the two-stage active trench 11, the thickness T5 of the second lower oxide film is thinner than the thickness T6 of the second upper oxide film.

[0070] 16 shows the relationship between the thickness T5 of the second lower oxide film and the thickness T6 of the second upper oxide film, but the same applies to the two-stage active dummy trench 7. That is, the thickness of the first lower oxide film is thinner than the thickness of the first upper oxide film.

[0071] According to the modification 18, by reducing the thickness of the second lower oxide film in the two-step active trench 11, the N+ layer formed around the second lower electrode 13 in the two-step active trench 11 can be made thicker and the impurity concentration of the N+ layer can be increased. Therefore, the emitter-collector saturation voltage V CEThe increase in (sat) can be suppressed more effectively than in the first embodiment and the first to seventeenth modifications.

[0072] <Variation 19> Fig. 17 is a cross-sectional view of a semiconductor device according to Modification 19. As shown in Fig. 17, the semiconductor device according to Modification 19 includes a first resistor Rg1 and a second resistor Rg2.

[0073] The first resistor Rg1 is connected between the first upper electrode 8 and the second upper electrode 12 and a gate electrode (not shown). The second resistor Rg2 is connected between the second lower electrode 13 and the gate electrode. The resistance value of the first resistor Rg1 is greater than the resistance value of the second resistor Rg2.

[0074] According to the modification 19, by making the resistance value of the first resistor Rg1 larger than the resistance value of the second resistor Rg2, the charging speed to the second lower electrode 13 increases, the N+ layer formed around the second lower electrode 13 becomes thicker, and the impurity concentration of the N+ layer becomes higher. Therefore, the emitter-collector saturation voltage V CE The increase in (sat) can be suppressed more effectively than in the first embodiment and the first to seventeenth modifications.

[0075] <Variation 20> The semiconductor device according to the 20th modification is a reverse conducting-insulated gate bipolar transistor (RC-IGBT).

[0076] Specifically, the semiconductor device according to Modification 20 has an IGBT region and a diode region. For example, a two-stage active trench 11 may be provided in the IGBT region, and a two-stage active dummy trench 7 may be provided in the diode region.

[0077] Furthermore, within the scope of the present disclosure, the embodiments may be modified or omitted as appropriate.

[0078] <Additional Notes> Various aspects of the present disclosure are summarized below as appendices.

[0079] (Appendix 1) a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface; At least one two-stage active dummy trench having a first upper stage electrode at a gate potential in an upper stage and a first lower stage electrode at an emitter potential in a lower stage inside a trench provided on the first main surface side of the semiconductor substrate; Inside a trench provided on the first main surface side of the semiconductor substrate, at least one two-stage active trench has a second upper stage electrode at an upper stage that is at the gate potential and a second lower stage electrode at a lower stage that is at the gate potential; a second conductivity type semiconductor layer provided on the second main surface side of the semiconductor substrate; Equipped with the first upper electrode, the second upper electrode, and the second lower electrode are connected to a same gate pad; In a plan view, the two-stage active dummy trench and the two-stage active trench extend in a horizontal direction, a length of a region where the two-step active dummy trench and the two-step active trench are adjacent to each other is longer than a length of a region where the two-step active dummy trench and the two-step active trench are not adjacent to each other, in the entire horizontal length of the two-step active dummy trench and the two-step active trench. (Appendix 2) a second conductivity type base layer provided on the first main surface side of the semiconductor substrate; the two-stage active dummy trench has a first boundary oxide film located between the first upper stage electrode and the first lower stage electrode; the two-stage active trench has a second boundary oxide film located between the second upper stage electrode and the second lower stage electrode; The semiconductor device described in Appendix 1, wherein an overhang width, which is the width between the end face of the base layer on the second main surface side and the end faces of the first upper electrode and the second upper electrode on the second main surface side, is longer than the film thickness of the first boundary oxide film and the film thickness of the second boundary oxide film. (Appendix 3) a second conductivity type base layer provided on the first main surface side of the semiconductor substrate; 3. The semiconductor device according to claim 1, wherein a length between the two-step active dummy trench and the two-step active trench is shorter than a length between an end face of the base layer on the second main surface side and an end face of the two-step active dummy trench on the second main surface side and an end face of the two-step active trench on the second main surface side. (Appendix 4) 4. The semiconductor device according to claim 1, wherein the number of the two-stage active trenches is the same as the number of the two-stage active dummy trenches. (Appendix 5) 4. The semiconductor device according to claim 1, wherein the number of the two-stage active trenches is greater than the number of the two-stage active dummy trenches. (Appendix 6) 4. The semiconductor device according to claim 1, wherein the number of the two-stage active trenches is smaller than the number of the two-stage active dummy trenches. (Appendix 7) 7. The semiconductor device according to claim 1, further comprising a carrier accumulation layer provided on the first main surface side of the drift layer. (Appendix 8) the two-stage active dummy trench has a first upper stage oxide film covering the first upper stage electrode and a first lower stage oxide film covering the first lower stage electrode; the two-stage active trench has a second upper stage oxide film covering the second upper stage electrode and a second lower stage oxide film covering the second lower stage electrode; The first lower oxide film has a thickness greater than the thickness of the first upper oxide film, 8. The semiconductor device according to claim 1, wherein the second lower oxide film has a thickness greater than that of the second upper oxide film. (Appendix 9) The length of the first lower electrode in the depth direction is longer than the length of the first upper electrode in the depth direction, 9. The semiconductor device according to claim 1, wherein the second lower electrode has a length in the depth direction that is longer than the length in the depth direction of the second upper electrode. (Appendix 10) the length of the first lower electrode in the depth direction is shorter than the length of the first upper electrode in the depth direction; 9. The semiconductor device according to claim 1, wherein the second lower electrode has a length in the depth direction that is shorter than the length in the depth direction of the second upper electrode. (Appendix 11) 11. The semiconductor device according to claim 1, wherein the first upper electrode and the second upper electrode each have a first portion and a second portion that form a concave shape toward the first main surface. (Appendix 12) Two or more of the two-stage active dummy trenches are provided adjacent to each other, 12. The semiconductor device according to any one of claims 1 to 11, wherein two or more of the two-stage active trenches are provided adjacent to each other. (Appendix 13) a plurality of trench groups including the two-stage active dummy trench and the two-stage active trench; 13. The semiconductor device according to claim 1, wherein each of the trench groups has a different ratio of the two-stage active trenches. (Appendix 14) 14. The semiconductor device according to claim 13, wherein, in plan view, the group of trenches located on the inside includes a higher proportion of the two-stage active trenches than the group of trenches located on the outside. (Appendix 15) 14. The semiconductor device according to claim 13, wherein, in plan view, the group of trenches located on the inside includes a higher proportion of the two-stage active dummy trenches than the group of trenches located on the outside. (Appendix 16) 16. The semiconductor device according to any one of claims 1 to 15, further comprising at least one single-stage dummy trench having a dummy electrode inside a trench provided on the first main surface side of the semiconductor substrate. (Appendix 17) 17. The semiconductor device according to claim 16, wherein the number of the one-stage dummy trenches is smaller than the number of the two-stage active dummy trenches. (Appendix 18) 17. The semiconductor device according to claim 16, wherein the number of the one-stage dummy trenches is smaller than the number of the two-stage active trenches. (Appendix 19) the two-stage active dummy trench has a first upper stage oxide film covering the first upper stage electrode and a first lower stage oxide film covering the first lower stage electrode; the two-stage active trench has a second upper stage oxide film covering the second upper stage electrode and a second lower stage oxide film covering the second lower stage electrode; the first lower oxide film has a thickness smaller than the thickness of the first upper oxide film; 19. The semiconductor device according to any one of claims 1 to 7 or 9 to 18, wherein the second lower oxide film has a thickness smaller than that of the second upper oxide film. (Appendix 20) a first resistor connected between the first upper electrode and the second upper electrode and a gate electrode; a second resistor connected between the second lower electrode and the gate electrode; Furthermore, 20. The semiconductor device according to claim 1, wherein the resistance value of the first resistor is greater than the resistance value of the second resistor. (Appendix 21) 21. The semiconductor device according to any one of appendices 1 to 20, wherein the semiconductor device is a reverse conducting-insulated gate bipolar transistor (RC-IGBT). [Explanation of symbols]

[0080] 1 drift layer, 2 base layer, 3 emitter layer, 4 contact layer, 5 buffer layer, 6 collector layer, 7 two-stage active dummy trench, 8 first upper electrode, 9 first lower electrode, 10 first oxide film, 11 two-stage active trench, 12 second upper electrode, 13 second lower electrode, 14 second oxide film, 15 element region, 16 gate pad, 17 gate wiring region, 18 termination region, 19 adjacent region, 20 non-adjacent region, 21 carrier accumulation layer, 22 first portion, 23 second portion, 24 first trench group, 25 second trench group, 26 one-stage dummy trench, 27 dummy electrode, 28 dummy oxide film.

Claims

1. a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface; at least one two-stage active dummy trench having a first upper stage electrode at a gate potential in an upper stage and a first lower stage electrode at an emitter potential in a lower stage inside a trench provided on the first main surface side of the semiconductor substrate; at least one two-stage active trench having, inside the trench provided on the first main surface side of the semiconductor substrate, a second upper stage electrode at an upper stage which is at the gate potential and a second lower stage electrode at a lower stage which is at the gate potential; a second conductivity type semiconductor layer provided on the second main surface side of the semiconductor substrate; Equipped with the first upper electrode, the second upper electrode, and the second lower electrode are connected to a same gate pad; In a plan view, the two-stage active dummy trench and the two-stage active trench extend in a horizontal direction, a length of a region where the two-step active dummy trench and the two-step active trench are adjacent to each other is longer than a length of a region where the two-step active dummy trench and the two-step active trench are not adjacent to each other, in the entire length of the two-step active dummy trench and the two-step active trench in the horizontal direction.

2. a second conductivity type base layer provided on the first main surface side of the semiconductor substrate; the two-stage active dummy trench has a first boundary oxide film located between the first upper stage electrode and the first lower stage electrode; the two-stage active trench has a second boundary oxide film located between the second upper stage electrode and the second lower stage electrode; 2. The semiconductor device according to claim 1, wherein an overhang width, which is a width between an end face of the base layer on the second main surface side and end faces of the first upper electrode and the second upper electrode on the second main surface side, is longer than a film thickness of the first boundary oxide film and a film thickness of the second boundary oxide film.

3. a second conductivity type base layer provided on the first main surface side of the semiconductor substrate; 2. The semiconductor device according to claim 1, wherein a length between the two-step active dummy trench and the two-step active trench is shorter than a length between an end face of the base layer on the second main surface side and an end face of the two-step active dummy trench on the second main surface side and an end face of the two-step active trench on the second main surface side.

4. The semiconductor device according to claim 1 , wherein the number of said two-stage active trenches is the same as the number of said two-stage active dummy trenches.

5. The semiconductor device according to claim 1 , wherein the number of said two-stage active trenches is greater than the number of said two-stage active dummy trenches.

6. The semiconductor device according to claim 1 , wherein the number of said two-stage active trenches is smaller than the number of said two-stage active dummy trenches.

7. The semiconductor device according to claim 1 , further comprising a carrier accumulation layer provided on the first main surface side of the drift layer.

8. the two-stage active dummy trench has a first upper stage oxide film covering the first upper stage electrode and a first lower stage oxide film covering the first lower stage electrode; the two-stage active trench has a second upper stage oxide film covering the second upper stage electrode and a second lower stage oxide film covering the second lower stage electrode; the first lower oxide film has a thickness greater than the thickness of the first upper oxide film; 2. The semiconductor device according to claim 1, wherein said second lower oxide film has a thickness greater than that of said second upper oxide film.

9. the length of the first lower electrode in the depth direction is longer than the length of the first upper electrode in the depth direction; 2. The semiconductor device according to claim 1, wherein the length of said second lower electrode in the depth direction is longer than the length of said second upper electrode in the depth direction.

10. a length of the first lower electrode in a depth direction is shorter than a length of the first upper electrode in a depth direction; 2. The semiconductor device according to claim 1, wherein the length of said second lower electrode in the depth direction is shorter than the length of said second upper electrode in the depth direction.

11. 2. The semiconductor device according to claim 1, wherein said first upper electrode and said second upper electrode each have a first portion and a second portion that form a recessed shape toward said first main surface.

12. Two or more of the two-stage active dummy trenches are provided adjacent to each other, The semiconductor device according to claim 1 , wherein two or more of the two-stage active trenches are provided adjacent to each other.

13. a plurality of trench groups including the two-stage active dummy trench and the two-stage active trench; The semiconductor device according to claim 1 , wherein each of the trench groups has a different ratio of the two-stage active trenches included therein.

14. The semiconductor device according to claim 13 , wherein, in plan view, the group of trenches located on the inner side includes a higher proportion of the two-stage active trenches than the group of trenches located on the outer side.

15. The semiconductor device according to claim 13 , wherein, in plan view, the group of trenches located on the inner side includes a higher proportion of the two-stage active dummy trenches than the group of trenches located on the outer side.

16. 2. The semiconductor device according to claim 1, further comprising at least one single-stage dummy trench having a dummy electrode inside the trench provided on said first main surface side of said semiconductor substrate.

17. The semiconductor device according to claim 16 , wherein the number of the one-stage dummy trenches is smaller than the number of the two-stage active dummy trenches.

18. The semiconductor device according to claim 16 , wherein the number of the one-stage dummy trenches is smaller than the number of the two-stage active trenches.

19. the two-stage active dummy trench has a first upper stage oxide film covering the first upper stage electrode and a first lower stage oxide film covering the first lower stage electrode; the two-stage active trench has a second upper stage oxide film covering the second upper stage electrode and a second lower stage oxide film covering the second lower stage electrode; the first lower oxide film has a thickness smaller than the thickness of the first upper oxide film; 2. The semiconductor device according to claim 1, wherein said second lower oxide film has a thickness smaller than that of said second upper oxide film.

20. a first resistor connected between the first upper electrode and the second upper electrode and a gate electrode; a second resistor connected between the second lower electrode and the gate electrode; Furthermore, The semiconductor device according to claim 1 , wherein the resistance value of said first resistor is greater than the resistance value of said second resistor.

21. 2. The semiconductor device according to claim 1, wherein the semiconductor device is a reverse conducting-insulated gate bipolar transistor (RC-IGBT).

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