Eye pattern evaluation device

Abstract

To provide a device that evaluates eye patterns through autonomous control without requiring configuration by the host. [Solution] The eye pattern evaluation device comprises a first interface circuit configured to acquire an eye pattern, and a controller configured to control the first interface circuit and a non-volatile memory, and is capable of communicating with a host, wherein the controller determines whether the number of received counts at a predetermined point included in the acquired eye pattern has reached a threshold, and if the number of received counts at the predetermined point has reached the threshold, it records log information indicating the communication quality at the predetermined point in the non-volatile memory.

Description

Technical Field

[0001] One embodiment of the present disclosure relates to an eye pattern evaluation device.

Background Art

[0002] In recent years, the development of high-performance memory systems such as Universal Flash Storage (UFS) has been progressing. In such a memory system, in order to evaluate the communication quality of received data signals and analyze when communication errors occur, it has a function of monitoring an eye pattern generated based on a data waveform.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] An object of the present disclosure is to provide a device that evaluates an eye pattern by autonomous control without requiring setting by the host side.

Means for Solving the Problems

[0005] A An eye pattern evaluation device according to one embodiment comprises a first interface circuit configured to acquire an eye pattern, and a controller configured to control the first interface circuit and a non-volatile memory, and is an eye pattern evaluation device that can communicate with a host, wherein the controller determines whether the number of received counts at a predetermined point included in the acquired eye pattern has reached a threshold, and if the number of received counts at the predetermined point has reached the threshold, it records log information indicating the communication quality at the predetermined point in the non-volatile memory. [Brief explanation of the drawing]

[0006] [Figure 1] This block diagram shows the configuration of a memory system according to one embodiment. [Figure 2] This figure shows the circuit configuration of the host interface unit according to one embodiment. [Figure 3] This flowchart shows the operation of an eye pattern evaluation device according to one embodiment. [Figure 4] This is a sequence diagram showing the operation of an eye pattern evaluation device according to one embodiment. [Figure 5] This figure shows log information recorded by an eye pattern evaluation device according to one embodiment. [Figure 6] This flowchart shows the operation of an eye pattern evaluation device according to one embodiment. [Figure 7] This figure shows log information recorded by an eye pattern evaluation device according to one embodiment. [Figure 8] This flowchart shows the operation of an eye pattern evaluation device according to one embodiment. [Figure 9] This figure illustrates the operation of an eye pattern evaluation device using logs recorded by an eye pattern evaluation device according to one embodiment. [Figure 10] This figure shows an example of a log recorded by an eye pattern evaluation device according to one embodiment. [Figure 11]This block diagram shows the configuration of a system according to one embodiment. [Modes for carrying out the invention]

[0007] The eye pattern evaluation apparatus according to the embodiment will be described in detail below with reference to the drawings. In the following description, components having substantially the same function and configuration are denoted by the same reference numerals, and redundant explanations may be omitted. The embodiments shown below illustrate devices and methods for realizing the technical concept of this embodiment. The technical concept of the embodiment is not limited to the materials, shapes, structures, arrangements, etc., of the components described below. The technical concept of the embodiment may be modified in various ways from the claims.

[0008] An "eye pattern" is a graph created by sampling the transitions of many signal waveforms of communication data and superimposing them. The graph, with its superimposed waveforms, resembles an eye, hence the name "eye pattern." For example, if a signal waveform that transitions from Low level to High level to Low level is superimposed with a signal waveform that transitions from High level to Low level to High level, an eye pattern with a large opening (large aperture ratio) will be obtained if the transition to the set voltage is abrupt at the same timing. On the other hand, if the transition timing is delayed, the set voltage is not reached, or the transition speed is slow, the aperture ratio in the eye pattern will be small. Therefore, the size and shape of the eye in the eye pattern can be used to evaluate the communication quality of the data and analyze when communication errors occur. "Eye pattern evaluation" is an evaluation that confirms the opening of the eye pattern by comparing the values ​​obtained by the deserializer 117 and deserializer 118, which will be described later.

[0009] [1. First Embodiment] A memory system 1 according to the first embodiment will now be described. The memory system 1 according to the first embodiment is a system in which the memory controller 10 autonomously controls the operation of the memory system 1 without receiving commands from the host 2, and enables the evaluation of the eye pattern.

[0010] [1-1. Overall configuration of the memory system] Figure 1 shows an example of the configuration of a memory system according to an embodiment. The memory system 1 is configured to be connectable to a host 2. While connected to the host 2, the memory system 1 performs data transmission and reception with the host 2 in response to requests from the host 2.

[0011] Host 2 is, for example, an electronic device such as a personal computer, a portable information device, or a server. Host 2 may be a processor provided in the electronic device or a circuit that has the function of communicating with memory system 1. Any interface standard can be adopted as the communication interface standard between memory system 1 and host 2. Two or more hosts 2 may be connected to memory system 1. Host 2 and memory system 1 may be connected via a network.

[0012] The memory system 1 includes a memory controller 10 and NAND-type flash memory (hereinafter referred to as NAND memory 12). The memory system 1 is, for example, a storage device such as a UFS device or an SSD (Solid State Drive). For example, if the memory system 1 is a UFS device, then the host 2 is a UFS host. The NAND memory 12 is a non-volatile storage medium that functions as storage. The NAND memory 12 is composed of one or more chips. The memory controller 10 includes a host interface unit 11 (Host I / F), a NAND controller 13 (NAND Controller), a RAM (Random Access Memory) 14, and a control unit 15 (Control Unit).

[0013] The control unit 15 is configured to include, for example, one or more processors. The control unit 15 executes various functions of the memory system 1 by executing firmware stored in advance in the memory system 1. The storage location of the program is arbitrarily designed. For example, the firmware is stored in the NAND memory 12 in advance and loaded into the RAM 14 at startup. The control unit 15 is configured to control the host interface unit 11, the NAND controller 13, and the RAM 14 by executing the firmware loaded into the RAM 14. That is, the memory system 1 includes a processor (control unit 15) and a memory (NAND memory 12), and the processor is configured to execute various functions by executing a program read from the memory. The memory system 1 is controlled by, for example, a plurality of processes based on firmware. Some or all of the plurality of processes executed by the control unit 15 may be realized by a hardware circuit. Also, the control unit 15 may be constituted by a control circuit which is a hardware circuit.

[0014] The control unit 15 controls the enabling or disabling of the eye pattern acquisition function (hereinafter referred to as the "eye monitor function") by the host interface unit 11 described later. Further, in the eye pattern evaluation, the control unit 15 sets parameters such as the voltage offset and timing offset described later to acquire the eye pattern. Although details will be described later, the control unit 15 determines whether or not the reception count at a predetermined point (for example, a point specified by a combination of voltage offset and timing offset) included in the eye pattern has reached a threshold value. When the reception count has reached the threshold value, the control unit 15 records log information indicating the communication quality at the predetermined point in the NAND memory 12.

[0015] The control unit 15 evaluates the eye pattern by performing the above determination and recording log information for each point included in the eye pattern. Note that the recording of log information means recording information related to the error count or the presence or absence of an error at the point where the above determination is made in association with information identifying the point. That is, communication quality is a concept including information related to the error count or the presence or absence of an error.

[0016] The host interface unit 11 is an interface device for the memory system 1 to communicate with the host 2. The host interface unit 11 executes the transfer of user data between the host 2 and the RAM 14 under the control of the control unit 15. The host interface unit 11 is configured to obtain an eye pattern on a two-axis coordinate by sequentially changing the combination of the voltage offset and the timing offset.

[0017] When a standby request command for putting the memory system 1 into the standby state or a transfer speed change command for changing the data transfer speed in the memory system 1 to a predetermined speed is issued from the host 2 to the memory system 1, the host interface unit 11 notifies these commands to the control unit 15. Here, putting the memory system 1 into the standby state means stopping or restricting the operations of at least a part of the NAND controller 13, the RAM 14, and the control unit 15 of the memory system 1. The above standby request command and transfer speed change command may be referred to as "specific commands". In the present embodiment, the standby request command and the transfer speed change command are exemplified as specific commands, but are not limited to these commands. For example, a command that requests a process for clearing the reception count or the error count in the eye monitor function is included in the specific commands.

[0018] If the host interface unit 11 receives a specific command from the host 2 while the eye pattern is being acquired as described above, the control unit 15 records the following log information before the eye monitor function stops. When the control unit 15 receives a specific command, it determines whether the number of received signals at the predetermined point has reached a threshold. If the number of received signals has reached the threshold, the control unit 15 records the log information in the NAND memory 12, and then the host interface unit 11 changes the operating mode based on the specific command (control to a standby state based on a standby request command, or control to a transfer speed change state based on a transfer speed change command).

[0019] On the other hand, if the result of the above determination is that the number of received signals has not reached the threshold, the control unit 15 notifies the host interface unit 11 of the result, and the host interface unit 11 then changes the operating mode based on a specific command. After that, if the operating mode returns from the standby state or the transfer speed change state, the host interface unit 11 resumes acquiring the eye pattern.

[0020] The control unit 15 records log information at a predetermined point in the NAND memory 12, and then sets a voltage offset and timing offset to identify the next point (next point) where communication quality evaluation will be performed. Next, the control unit 15 determines whether the number of received signals at the next point has reached a threshold. If the number of received signals has reached the threshold, the control unit 15 records log information indicating the communication quality at the next point in the NAND memory 12.

[0021] As will be explained in detail later, in this embodiment, the next best point is a point adjacent to a predetermined point where evaluation was performed previously (an adjacent point). In other words, an adjacent point is a point identified by changing either the voltage offset or the timing offset value at the predetermined point by one. However, the next best point is not limited to an adjacent point. In other words, the next best point may be a point that is not adjacent to the point where evaluation was performed.

[0022] The NAND controller 13 is an interface device for accessing the NAND memory 12. Under the control of the control unit 15, the NAND controller 13 performs the transfer of user data or management information between the RAM 14 and the NAND memory 12. Although details are omitted, the NAND controller 13 can perform processing such as error correction.

[0023] RAM 14 is a storage medium for temporarily storing data. RAM 14 may be built into the memory controller 10 or mounted outside the memory controller 10. As RAM 14, for example, a storage medium capable of sending and receiving data at a higher speed than NAND memory 12 can be used. As RAM 14, for example, a volatile or non-volatile storage medium can be used. As RAM 14, for example, DRAM (Dynamic RAM), SRAM (Static RAM), FeRAM (Ferroelectric RAM), MRAM (Magnetoresistive RAM), PRAM (Phase change RAM), etc. can be used.

[0024] [1-2. Circuit configuration of the host interface section] Figure 2 shows the circuit configuration provided in the host interface unit 11 according to the first embodiment. The RX input pin 111 receives the received signal. This received signal is, for example, a signal that operates differentially between two lines in the physical layer of the serial interface. The received signal is compensated, such as by amplifying the high-frequency components by the EQ (Equalizer) 112, and then sent to the data sampler 114 and the eye monitor sampler 116.

[0025] The data sampler 114, synchronized with the clock from the clock data recovery (CDR) circuit 113, extracts binary data contained in the received signal based on the reference voltage and outputs it to the deserializer 117 and the CDR circuit 113 (Main Data / Edge (Serial)). The process by which the data sampler 114 extracts binary data from the received signal is hereafter referred to as "sampling" or "acquisition".

[0026] The CDR circuit 113 separates the clock from the received data (Data / Edge) and outputs the separated clock to the data sampler 114, the eye monitor sampler 116, and the PI circuit 115. The CDR circuit 113 reconstructs a multiphase clock. The multiphase clock reconstructed by the CDR circuit 113 includes multiple clocks with different phases from each other.

[0027] The PI circuit 115 generates a clock timing signal with a phase shifted based on the clock from the CDR circuit 113, and supplies the generated clock timing signal to the eye monitor sampler 116. The PI circuit 115 also receives a control signal from the eye monitor controller 120 indicating the timing within the sampling period for the signal to be sampled. The PI circuit 115 supplies the clock timing signal generated according to the control signal to the eye monitor sampler 116.

[0028] The eye monitor sampler 116 is a sampling circuit that samples the signal waveform, including the aperture portion of the eye pattern in the received signal. The eye monitor sampler 116 is installed alongside the data sampler 114. The eye monitor sampler 116 receives the received signal processed by the EQ 112. The eye monitor sampler 116 receives the clock timing signal from the PI circuit 115 and the clock from the CDR circuit 113. For the received signal processed by the EQ 112, the eye monitor sampler 116 determines the voltage amplitude level of the received signal using the reference voltage (Voltage Threshold Setting) from the DAC 119, synchronized with the clock timing signal from the PI circuit 115, and extracts the determination result as binary data synchronized with the clock from the CDR circuit 113. The eye monitor sampler 116 outputs the extracted received signal (Eye Mon. Data (Serial)) to the deserializer 118.

[0029] The deserializer 117 converts the received signal input to the deserializer 117 into parallel data and outputs it (Data (Parallel)). The deserializer 118 converts the received signal input to the deserializer 118 into parallel data and outputs it (Eye Mon. Data (Parallel)). The DAC 119 receives a control signal indicating a reference voltage from the eye monitor controller 120 and outputs the reference voltage corresponding to the control signal to the eye monitor sampler 116.

[0030] The eye monitor controller 120 is an example of a control circuit and output circuit. The eye monitor controller 120 sets the phase and voltage when sampling the signal to be processed by the eye monitor sampler 116, and outputs a control signal indicating the set content. Based on the data output by the data sampler 114 and the data output by the eye monitor sampler 116, the eye monitor controller 120 generates eye monitor data (eye pattern data) of the entire signal, including the eye pattern aperture of the received signal. The eye monitor controller 120 generates eye pattern data, which is data in which many waveform data are superimposed on a coordinate plane unfolded with voltage on the vertical axis and phase (timing) on ​​the horizontal axis. In order to generate eye pattern data, the eye monitor controller 120 outputs a control signal (Phase Offset Setting) indicating the phase or voltage related to the signal to be extracted to the PI circuit 115 or DAC 119. The eye monitor controller 120 also outputs a signal (Phase Offset Region Bit) indicating the setting range by the phase control signal related to the signal to be extracted to the eye monitor sampler 116.

[0031] The control signal output by the eye monitor controller 120 to the PI circuit 115 indicates the timing within the sampling period for the signal to be sampled. This signal determines the value of the timing offset for the sampled signal. The control signal output by the eye monitor controller 120 to the DAC 119 is a reference voltage threshold, which is the voltage value corresponding to the signal to be sampled. This signal determines the value of the voltage offset for the sampled signal. The values ​​of the timing offset and voltage offset are set by the control unit 15 or the eye monitor controller 120. By performing sampling while sequentially changing these offset values, an eye pattern can be generated.

[0032] The data sampler 114 and the eye monitor sampler 116 perform sampling based on multiple clocks input to each. The eye monitor controller 120 counts the number of times an error occurs when comparing the signal acquired from the data sampler 114 with the signal acquired from the eye monitor sampler 116 (Error Count) and the number of samples taken (Sampling Count). An error in the comparison indicates that the comparison results do not match. The eye monitor controller 120 calculates the bit error rate (BER) based on the error count and the number of samples taken. This BER is expressed as the number of bits in error divided by the total number of bits transmitted.

[0033] [1-3. Memory System Operation] The operation of the memory system 1 will be explained using Figure 3. Figure 3 is a flowchart showing the operation of the memory system according to one embodiment. The flowchart shown in Figure 3 is realized through the cooperation of the host interface unit 11 and the control unit 15. Note that the flowchart shown in Figure 3 shows the operation when a specific command is issued while eye pattern acquisition is in progress.

[0034] As shown in Figure 3, when the memory system 1 starts operating, the control unit 15 first sets up the eye pattern evaluation. Specifically, when power is supplied from the host 2 and the BOOT process is performed, the memory system 1 rewrites a register or attribute so that the firmware implemented in the control unit 15 enables the eye monitor function, and the control unit 15 sets the voltage offset and timing offset (step S301) and identifies a predetermined point for determining the number of received counts. Next, the control unit 15 enables the eye monitor function by the host interface unit 11 (step S302).

[0035] When the eye monitor function is enabled, the host interface unit 11 starts acquiring the eye pattern (step S303). In S303, for example, eye pattern acquisition may start when the transfer speed meets a predetermined condition. For example, eye pattern acquisition may start when the transfer speed becomes "HS-GEAR5 mode" in the "MIPI M-PHY v5.0" standard. Note that in the eye pattern setting in S301, the transfer speed at which eye pattern acquisition starts may be set. Once eye pattern acquisition starts, the host interface unit 11 acquires the eye pattern while receiving write / read requests from the host 2, attribute write / read operations, or filler symbol transmission operations.

[0036] When the host interface unit 11 receives a specific command from the host 2 while acquiring the eye pattern (step S304), the control unit 15 determines whether the number of received counts has reached a threshold for a set point (a predetermined point included in the eye pattern) identified by the currently set voltage offset and timing offset (step S305).

[0037] In step S305, if the control unit 15 determines that the number of received signals has reached a threshold (YES in S305), the control unit 15 records log information for the setting point in the NAND memory 12 (step S306). As described above, the log information is, for example, information related to the number of errors or whether or not an error occurred at the setting point. On the other hand, in step S305, if the control unit 15 determines that the number of received signals has not reached a threshold (NO in S305), the control unit 15 notifies the host interface unit 11 of the result, and the host interface unit 11 changes the operating mode based on a specific command (step S309).

[0038] In S306, once log information is recorded, the control unit 15 determines whether the eye pattern acquisition operation has finished (step S307). In S307, if the control unit 15 determines that the eye pattern acquisition operation has finished (YES in S307), the control unit 15 terminates the flow shown in Figure 3. On the other hand, in S307, if the control unit 15 determines that the eye pattern acquisition operation has not finished (NO in S307), the control unit 15 sets the next point where the communication quality evaluation will be performed after the current setpoint (step S308). For example, the control unit 15 increments or decrements the voltage offset or timing offset to identify an adjacent point adjacent to the current setpoint.

[0039] Then, the host interface unit 11 changes the operating mode based on a specific command (step S309). For example, the host interface unit 11 controls the memory system 1 to a standby state based on a standby request command. After that, when the memory system 1 recovers from the standby state, the host interface unit 11 resumes the eye pattern acquisition operation (S303).

[0040] The processing flow between the host interface unit 11, the NAND controller 13, and the control unit 15 will be explained using Figure 4. Figure 4 is a sequence diagram showing the operation of an eye pattern evaluation device according to one embodiment. In Figure 4, an example is shown in which a standby request command is issued from the host 2 as a specific command, and the error count is recorded as log information indicating communication quality.

[0041] When a standby request command is issued from host 2 to memory system 1, as shown in Figure 4, the host interface unit 11 notifies the control unit 15 of the standby request (step S401). In response to this standby request, the control unit 15 notifies the host interface unit 11 of a request to confirm the received count and the error count (step S402). In response to this confirmation request, the host interface unit 11 notifies the received count and the error count (step S403). In response to the above single confirmation request, the host interface unit 11 may notify the received count and the error count at once, or the host interface unit 11 may initially notify only the received count and only notify the error count if the received count reaches a threshold.

[0042] The control unit 15 instructs the NAND controller 13 to record the error count received from the host interface unit 11 as log information in the NAND memory 12, associating it with information that identifies the currently set setting point (e.g., voltage offset and timing offset) (step S404). Once the NAND controller 13 has finished recording the log information in the NAND memory 12, the NAND controller 13 notifies the control unit 15 that the recording of the log information is complete (step S405). The control unit 15 then sets the voltage offset and timing offset corresponding to the next point, and the host interface unit 11 controls the memory system 1 to a standby state (step S406).

[0043] [1-4. Log Information] Figure 5 shows a visualization of the log information recorded in the NAND memory 12. In Figure 5, the horizontal axis represents the timing offset value, and the vertical axis represents the voltage offset value. In Figure 5, integers from "-13" to "+13" are displayed as the timing offset value and the voltage offset value, respectively. Figure 5 has cells corresponding to each combination of timing offset and voltage offset, and each cell displays the error count. As shown in Figure 5, when the error count is "0", the cell is displayed in white. When the error count is "10", the cell is displayed in gray. When the error count is "99", the cell is displayed in black.

[0044] In Figure 5, the maximum error count is "99," but the maximum value can be 100 or more. Also, for the sake of explanation, the cells are colored, but coloring the cells is not mandatory.

[0045] In Figure 5, the region where the error count is "0" corresponds to the area in Figure 2 where the signal acquired from the data sampler 114 and the signal acquired from the eye monitor sampler 116 coincide, and thus corresponds to the eye portion of the eye pattern displayed as a graph. In other words, in the log information shown in Figure 5, the communication quality of the data can be evaluated by the area or shape of the region where the error count is "0" or the region where the error count is relatively small (for example, the region where the error count is "3" or less).

[0046] For example, if host 2 has implemented a command to read the above log information, the control unit 15 reads the log information recorded in the NAND memory 12 based on the command requesting the log information and notifies host 2 of the log information via the host interface unit 11.

[0047] In conventional memory systems, enabling the eye monitor function required configuration on the host. Therefore, if the host did not implement a program to enable the memory system's eye monitor function, it was impossible to check the signal waveforms and eye patterns within the circuit using the memory system. Furthermore, to conserve power in the memory system, if a specific command like the one described above was input, and the necessary number of received counts for BER calculation had not been obtained at that time, the received counts and error counts up to that point would be cleared. Consequently, if configuration was required on host 2, evaluation using the eye monitor function became difficult.

[0048] On the other hand, even in such cases, the memory system 1 according to this embodiment can avoid the problems described above. Specifically, even if a specific command is issued from a host 2 that does not have a program implemented to enable the eye monitor function of the memory system 1, log information is recorded in the NAND memory 12 by the functions of the host interface unit 11 and the control unit 15. Therefore, even if the reception count and error count are cleared when the operating mode is changed based on a specific command, the reception count and error count up to that point can be used. Thus, the eye pattern can be evaluated by autonomous control without requiring settings by the host 2.

[0049] [2. Second Embodiment] The memory system according to the second embodiment will be described with reference to Figures 6 and 7. The memory system 1 according to the second embodiment is similar to the memory system 1 according to the first embodiment. In the following description, the explanation of the same configuration as the memory system 1 according to the first embodiment will be omitted, and the differences between the two will be mainly described. Regarding the memory system 1 according to the second embodiment, the overall configuration of the memory system 1 and the configuration of each functional unit (for example, the host interface unit 11 and the control unit 15) are the same as in the first embodiment.

[0050] In the first embodiment, the error count was recorded as log information, whereas in the second embodiment, information regarding whether or not an error occurred is recorded as log information.

[0051] [2-1. Memory System Operation] The operation of the memory system 1 will be explained using Figure 6. Figure 6 is a flowchart showing the operation of the memory system according to one embodiment. The flowchart shown in Figure 6 is realized through the cooperation of the host interface unit 11 and the control unit 15. Note that the flowchart shown in Figure 6 shows the operation when a specific command is issued while eye pattern acquisition is in progress.

[0052] The flowchart shown in Figure 6 is similar to the flowchart shown in Figure 3, but steps S601 to S604 in Figure 6 are the same as steps S301 to S304 in Figure 3, so their explanation is omitted.

[0053] As shown in Figure 6, when the host interface unit 11 receives a specific command from the host 2 while acquiring the eye pattern (step S604), the control unit 15 determines whether an error has occurred at the set point (a predetermined point included in the eye pattern) identified by the currently set voltage offset and timing offset (step S605). If the error count at the set point is 1 or more, the control unit 15 determines that an error has occurred at the set point ("YES" in S605) and records "FAIL" as log information for the set point in the NAND memory 12 (step S606). On the other hand, if the error count at the set point is 0, the control unit 15 determines that no error has occurred at the set point ("NO" in S605) and determines whether the reception count at the set point has reached a threshold (step S607).

[0054] In step S607, if the control unit 15 determines that the number of received signals has reached a threshold (YES in S607), the control unit 15 records "PASS" in the NAND memory 12 as log information for the above setting point (step S608). On the other hand, in step S607, if the control unit 15 determines that the number of received signals has not reached a threshold (NO in S607), the control unit 15 notifies the host interface unit 11 of the result, and the host interface unit 11 changes the operating mode based on a specific command (step S611).

[0055] In S606 or S608, when log information is recorded, the control unit 15 determines whether the eye pattern acquisition operation has finished (step S609). In S609, if the control unit 15 determines that the eye pattern acquisition operation has finished (YES in S609), the control unit 15 terminates the flow shown in Figure 6. On the other hand, in S609, if the control unit 15 determines that the eye pattern acquisition operation has not finished (NO in S609), the control unit 15 sets the next point where the communication quality evaluation will be performed after the current setpoint (step S610). For example, the control unit 15 increments or decrements the voltage offset or timing offset to identify an adjacent point adjacent to the current setpoint.

[0056] Then, the host interface unit 11 changes the operating mode based on a specific command (step S611). For example, the host interface unit 11 controls the memory system 1 to a standby state based on a standby request command. After that, when the memory system 1 recovers from the standby state, the host interface unit 11 resumes the eye pattern acquisition operation (S603).

[0057] [2-2. Log Information] Figure 7 illustrates a visualization of the log information recorded in the NAND memory 12. Figure 7 is similar to Figure 5, but the information recorded in each cell differs. Specifically, in Figure 7, each cell records whether or not an error occurred. The "F" recorded in a cell indicates that an error was detected at the corresponding setting point. The "P" recorded in a cell indicates that no error occurred at the corresponding setting point. If an error occurred, the cell is displayed in black. If no error occurred, the cell is displayed in white.

[0058] In the log information shown in Figure 7, the data communication quality can be evaluated by the area or shape of the region where the cell record is "P".

[0059] As described above, the memory system 1 according to this embodiment can simplify log information. Furthermore, if even one error exists, the operation for the currently evaluated setting point can be terminated and the next point can be evaluated, thus enabling faster operation.

[0060] [3. Third Embodiment] The memory system according to the third embodiment will be described with reference to Figure 8. The memory system 1 according to the third embodiment is similar to the memory system 1 according to the second embodiment. In the following description, the explanation of the same configuration as the memory system 1 according to the second embodiment will be omitted, and the differences between the two will be mainly described. Regarding the memory system 1 according to the third embodiment, the overall configuration of the memory system 1 and the configuration of each functional unit (for example, the host interface unit 11 and the control unit 15) are the same as in the first embodiment.

[0061] The third embodiment differs from the second embodiment in that, when a specific command is issued and the number of received counts has not reached a threshold, the number of received counts up to that point is recorded, and when the system returns from the operation mode based on the specific command, the recorded count is read out.

[0062] [3-1. Memory System Operation] The operation of the memory system 1 will be explained using Figure 8. Figure 8 is a flowchart showing the operation of the memory system according to one embodiment. The flowchart shown in Figure 8 is realized through the cooperation of the host interface unit 11 and the control unit 15. Note that the flowchart shown in Figure 8 shows the operation when a specific command is issued while eye pattern acquisition is in progress.

[0063] The flowchart shown in Figure 8 is similar to the flowchart shown in Figure 6. Steps S801 to S811 in Figure 8 are the same as steps S601 to S611 in Figure 6, so their explanation is omitted.

[0064] As shown in Figure 8, in step S807, if the control unit 15 determines that the number of received signals has not reached the threshold ("NO" in S807), the control unit 15 records the number of received signals at the current set point in the NAND memory 12 (step S882). Once the process in S882 is complete, the control unit 15 notifies the host interface unit 11 that the process is complete, and the host interface unit 11 changes the operating mode based on a specific command (step S811). Subsequently, when the memory system 1 returns from the operating mode based on the specific command, the host interface unit 11 resumes the eye pattern acquisition operation (S803).

[0065] When the eye pattern acquisition operation resumes in S803, the control unit 15 reads the reception count recorded in the NAND memory 12 (step S881). Then, it restarts the reception count based on the read reception count.

[0066] If the received count has not reached a threshold when a specific command is issued, the received count up to that point is cleared. However, according to the memory system 1 of this embodiment, in such a case, the received count is recorded in the NAND memory 12, and when eye pattern acquisition resumes, the received count recorded in the NAND memory 12 is read out. Therefore, even in cases where a specific command is issued in a short period of time, the received count up to the time the specific command is issued can be effectively utilized.

[0067] [4. Fourth Embodiment] The memory system according to the fourth embodiment will be described using Figures 9 and 10. The memory system 1 according to the fourth embodiment is similar to the memory system 1 according to the second embodiment. In the following description, the description of the same configuration as the memory system 1 according to the second embodiment will be omitted, and the differences between the two will be mainly described. Regarding the memory system 1 according to the fourth embodiment, the overall configuration of the memory system 1 and the configuration of each functional unit (for example, the host interface unit 11 and the control unit 15) are the same as in the first embodiment.

[0068] In the second embodiment, the eye pattern is acquired and log information is recorded for all cells arranged in a matrix by sequentially changing the voltage offset and timing offset. In contrast, in the fourth embodiment, the eye pattern is acquired and log information is recorded for only a portion of the cells arranged in a matrix, and the eye pattern is not acquired for the other cells, with the log information being determined by estimation.

[0069] [4-1. Scanning Method for Voltage Offset and Timing Offset] The scanning method for voltage offset and timing offset will be explained using Figure 9. In this embodiment, when the eye pattern acquisition operation starts, as shown by arrow (1) in Figure 9, the reception count and error count are measured while incrementing (+1) the value of the timing offset from [voltage offset:timing offset]=[+13:-13]. If the log information in each cell is "F", the above operation is repeated, and when the value of the timing offset reaches [+13], the value of the voltage offset is decremented (-1).

[0070] Next, as shown by arrow (2) in Figure 9, the receive count and error count are measured while incrementing the timing offset (+1) from [voltage offset:timing offset] = [+12:-13] (i.e., from the minimum value of the timing offset). Here, if the log information in a certain cell is "P" (in Figure 9, the timing offset is [0]), the measurement shown by arrow (2) is interrupted, and as shown by arrow (3) in Figure 9, the receive count and error count are measured while decrementing the timing offset (-1) from [voltage offset:timing offset] = [+12:+13] (i.e., from the maximum value of the timing offset). When the voltage offset is [+12], there is only one cell with log information "P", so the measurement shown by arrow (3) is performed for all timing offset values ​​until the timing offset value becomes [+1], and the voltage offset value is decremented (-1).

[0071] Next, as shown by arrow (4) in Figure 9, the receive count and error count are measured while incrementing the timing offset (+1) from [voltage offset:timing offset]=[+11:-13]. If the log information in a certain cell is "P" (in Figure 9, the timing offset is [-1]), the measurement shown by arrow (4) is interrupted, and as shown by arrow (5) in Figure 9, the receive count and error count are measured while decrementing the timing offset (-1) from [voltage offset:timing offset]=[+11:+13]. If the log information in a certain cell is "P" (in Figure 9, the timing offset is [+1]), the voltage offset value is decremented (-1), and as shown by arrow (6) in Figure 9, the receive count and error count are measured while incrementing the timing offset (+1) from [voltage offset:timing offset]=[+10:-13].

[0072] It is presumed that in the eye pattern, "P" is recorded in almost all cells in the area inside the eye's outline. Therefore, once the eye's outline is identified, the measurement of the receive count and error count in the area inside it can be omitted.

[0073] To rephrase the above configuration, the control unit 15 records log information "F" at a predetermined point (for example, [voltage offset:timing offset]=[+11:-3]) in the NAND memory 12, and then changes (increments) the value of the timing offset to set it to an adjacent point next to the predetermined point (for example, [voltage offset:timing offset]=[+11:-2]). Because an error occurred at the adjacent point [+11:-2], the control unit 15 changes (increments) the value of the timing offset to set it to an adjacent point next to the adjacent point [+11:-2] (for example, [voltage offset:timing offset]=[+11:-1]). On the other hand, because no error occurred at the adjacent point [+11:-1], the control unit 15 changes (decrements) the value of the voltage offset to set it to a point where the voltage offset value is different from both the predetermined point [+11:-3] and the adjacent point [+11:-2] (for example, [voltage offset:timing offset]=[+10:-13]).

[0074] In the above configuration, instead of determining whether an error has occurred, it is also possible to determine whether the error count has reached a threshold. In that case, the control unit 15 increments the timing offset value when the error count has reached the threshold, and decrements the voltage offset value when the error count has not reached the threshold.

[0075] In addition, in the above configuration, the timing offset and voltage offset may be swapped. That is, the control unit 15 may measure the receive count and error count while decrementing the voltage offset (-1) from [voltage offset:timing offset]=[+13:-13].

[0076] Figure 10 shows an example of a log in the case shown in Figure 9. In the log shown in Figure 10, the value of the timing offset when "P" is recorded as log information is recorded for each voltage offset. For example, when the timing offset is [+13], "P" is not recorded, so [F] is recorded as log information. When the timing offset is [+12], whether the timing offset is incremented from [-13] or decremented from [+13], "P" is recorded as log information when the timing offset is [0], so "0 0" is recorded as log information. When the timing offset is [+11], if the timing offset is incremented from [-13], "P" is recorded as log information when the timing offset is [-1], and if it is decremented from [+13], "P" is recorded as log information when the timing offset is [+1]. Therefore, in this case, "-1 +1" is recorded as log information. Note that the log shown in Figure 10 is just an example and is not limited to this log format.

[0077] In the example above, a configuration was illustrated in which the voltage offset is decremented and the timing offset is incremented from [-13] when "P" is recorded as log information, but the configuration is not limited to this. For example, when "P" is recorded as log information, the voltage offset may be decremented while maintaining the timing offset, and the timing offset may be decremented from that cell. In this case, the voltage offset may be decremented while maintaining the timing offset when the log information changes from "P" to "F". In other words, the boundary between "P" and "F" may be identified by scanning in a stepwise manner.

[0078] As described above, the memory system 1 according to this embodiment makes it possible to omit the acquisition of predictable log information, thereby enabling further speed improvements in operation.

[0079] [5. Fifth Embodiment] The memory system according to the fifth embodiment will be described using Figure 11. The memory system 1 according to the fifth embodiment is similar to the memory system 1 according to the first embodiment. In the following description, the explanation of the same configuration as the memory system 1 according to the first embodiment will be omitted, and the differences between the two will be mainly described.

[0080] Figure 11 is a block diagram showing the configuration of a system according to one embodiment. The block diagram shown in Figure 11 is similar to the block diagram shown in Figure 1, but in addition to the first host interface unit 11 corresponding to the host interface unit 11 in Figure 1, it includes a second host interface unit 19 that communicates with a dedicated logger 3. The second host interface unit 19 is configured to acquire log information recorded in the NAND memory 12. For example, a low-speed interface such as an SPI communication interface may be used as the second host interface unit 19.

[0081] As shown in Figure 11, the memory system 1 is equipped with a second host interface unit 19, which allows log information recorded in the NAND memory 12 to be read by a method other than via the host 2. Therefore, log information can be read even if the host 2 does not implement a command for reading log information.

[0082] Although embodiments of the present invention have been described above with reference to the drawings, the present invention is not limited to the above embodiments, and can be modified as appropriate without departing from the spirit of the invention. For example, a memory system based on this embodiment, with additions, deletions, or design changes made by a person skilled in the art, is also included in the scope of the present invention as long as it retains the gist of the invention. Furthermore, the above embodiments can be combined as appropriate as long as they do not contradict each other, and technical matters common to each embodiment are included in each embodiment even without explicit description.

[0083] Any effects or benefits other than those brought about by the embodiments described above, if they are clear from the description herein or easily predictable to a person skilled in the art, are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0084] 1: Memory system, 2: Host, 3: Logger, 10: Memory controller, 11: Host interface section, 12: NAND memory, 13: NAND controller, 14: RAM, 15: Control section, 19: Second host interface section, 111: RX input pin, 112: EQ, 113: Clock data recovery (CDR) circuit, 114: Data sampler, 115: PI circuit, 116: Eye monitor sampler, 117: Deserializer, 118: Deserializer, 120: Eye monitor controller

Claims

1. A first interface circuit configured to acquire an eye pattern, An eye pattern evaluation device comprising a controller configured to control the first interface circuit and non-volatile memory, and capable of communicating with a host, The aforementioned controller, Determine whether the number of received signals at a predetermined point included in the acquired eye pattern has reached a threshold. An eye pattern evaluation device that, when the number of received counts at the predetermined point reaches the threshold, records log information indicating the communication quality at the predetermined point in the non-volatile memory.

2. The eye pattern evaluation device according to claim 1, wherein the controller determines whether the number of received counts at predetermined points included in the acquired eye pattern has reached a threshold value when the first interface circuit receives a specific command from the host while acquiring the eye pattern.

3. The eye pattern evaluation apparatus according to claim 2, wherein the specified command includes a standby request command to stop the operation of the controller, or a transfer speed change command to change the data transfer speed of the controller to a predetermined speed or less.

4. The predetermined point is identified by one combination of voltage offset and timing offset set when acquiring the eye pattern. The aforementioned controller, After recording the log information at the predetermined point in the non-volatile memory, a combination of the voltage offset and timing offset indicating an adjacent point adjacent to the predetermined point is set. Determine whether the number of received counts at the adjacent point has reached a threshold. The eye pattern evaluation device according to claim 3, wherein if the number of received counts at the adjacent point reaches the threshold, the log information at the adjacent point is recorded in the non-volatile memory.

5. The first interface circuit is, After recording the log information in the non-volatile memory, the system is controlled to a standby state based on the standby request command or a transfer speed change state based on the transfer speed change command. The eye pattern evaluation device according to claim 3, wherein when the device returns from the standby state or the transfer speed change state, it resumes acquiring the eye pattern.

6. The eye pattern evaluation device according to claim 1, wherein the communication quality includes information relating to the number of errors or whether or not an error occurred at the predetermined point.

7. The eye pattern evaluation apparatus according to claim 4, wherein the controller records the number of error counts at a point identified by a combination of any of the plurality of voltage offsets and any of the plurality of timing offsets, including the predetermined point and the adjacent point, as log information in the non-volatile memory.

8. The eye pattern evaluation apparatus according to claim 4, wherein the controller records different information in the non-volatile memory as log information at a point identified by a combination of any of the plurality of voltage offsets and any of the plurality of timing offsets, including the predetermined point and the adjacent point, depending on whether an error occurs or not.

9. The eye pattern evaluation device according to claim 2, wherein when the controller receives the specific command, if the number of received counts at the predetermined point has not reached the threshold, the controller records the number of received counts in the non-volatile memory.

10. The aforementioned specific command includes a standby request command that stops the operation of the controller, or a transfer speed change command that changes the data transfer speed of the controller to a predetermined speed or lower. The aforementioned controller, After recording the reception count in the non-volatile memory, the system is controlled to a standby state based on the standby request command or a transfer speed change state based on the transfer speed change command. When recovering from the aforementioned standby state or the aforementioned transfer speed change state, the acquisition of the eye pattern is resumed. The eye pattern evaluation device according to claim 9, which reads the number of received counts recorded in the non-volatile memory.

11. The predetermined point is identified by one combination of voltage offset and timing offset set when acquiring the eye pattern. The aforementioned controller, After recording the log information at the predetermined point in the non-volatile memory, the combination of the voltage offset and the timing offset indicating a first adjacent point adjacent to the predetermined point is set by changing the value of the timing offset. Determine whether the error count at the first adjacent point has reached a threshold or whether an error has occurred. If the error count at the first adjacent point reaches a threshold or an error occurs, the value of the timing offset is changed to set the combination of the voltage offset and the timing offset that indicates the second adjacent point adjacent to the first adjacent point. The eye pattern evaluation device according to claim 1, wherein if the error count at the first adjacent point does not reach a threshold or no errors occur, the value of the voltage offset is changed to set a combination of the voltage offset and the timing offset that indicates a third point whose voltage offset value is different from that of the predetermined point and the first adjacent point.

12. The predetermined point is identified by one combination of voltage offset and timing offset set when acquiring the eye pattern. The aforementioned controller, After recording the log information at the predetermined point in the non-volatile memory, the voltage offset value is changed to set a combination of the voltage offset and the timing offset that indicates a first adjacent point adjacent to the predetermined point. Determine whether the error count at the first adjacent point has reached a threshold or whether an error has occurred. If the error count at the first adjacent point reaches a threshold or an error occurs, the voltage offset value is changed to set a combination of the voltage offset and timing offset that indicates the second adjacent point adjacent to the first adjacent point. The eye pattern evaluation device according to claim 1, wherein if the error count at the first adjacent point does not reach a threshold or no errors occur, the value of the timing offset is changed to set a combination of the voltage offset and the timing offset that indicates a third point whose timing offset value is different from that of the predetermined point and the first adjacent point.

13. The eye pattern evaluation apparatus according to claim 1, further comprising a second interface circuit different from the first interface circuit, configured to acquire the log information recorded in the non-volatile memory.

14. The eye pattern evaluation device according to claim 1, wherein the controller notifies the host of the log information based on a command received from the host.

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