Indication device

Abstract

One of our challenges is to provide highly reliable semiconductor display devices. We also aim to reduce power consumption. One of the objectives is to provide a semiconductor display device that can perform the following functions. [Solution] A decoder is provided in the scan line drive circuit, and according to the signal input to the scan line drive circuit This means that pulses are sequentially input only to the scan lines that the pixels of the lines being displayed possess, and the other lines are not displayed. The system is configured to not input pulses to the scan lines of pixels in lines that are not being displayed. And, all pixels of the line selected by the pulse, or some of the pixels of the selected line By supplying video signals to the pixels from the signal line drive circuit, the pixels are positioned in a specific area of ​​the pixel. The image will only be displayed for the pixels that are marked.

Description

[Technical Field]

[0001] The present invention relates to an active-matrix semiconductor display device using thin-film transistors and the Regarding the drive method. [Background technology]

[0002] Thin-film transistors using semiconductor films formed on insulating surfaces are active-matrix type. It is an essential semiconductor element for the drive circuit or pixel section of the semiconductor display device. Thin-film transistors are subject to the constraint of the substrate's heat resistance temperature, so they are manufactured at relatively low temperatures. Amorphous silicon capable of forming thin films, obtained by crystallization using laser light or catalytic elements. Thin-film transistors, which have polysilicon or similar materials in their active layer, are used in semiconductor display devices. It has become the mainstream transistor.

[0003] In recent years, the high mobility obtained from polysilicon and amorphous silicon have been used. These new semiconductor materials, which possess both uniform device characteristics and other desirable properties, are called oxide semiconductors. Attention is being drawn to metal oxides that exhibit semiconductor properties. Metal oxides are used in a variety of applications. For example, indium oxide, a well-known metal oxide, is used in liquid crystal display devices. It is used as a transparent electrode material. Examples of metal oxides that exhibit semiconductor properties include, for example, Examples of semiconductors include tungsten oxide, tin oxide, indium oxide, and zinc oxide. Thin-film transistors that use metal oxides exhibiting specific properties in the channel formation region are already known. (Patent Documents 1 to 4, Non-Patent Document 1).

[0004] Metal oxides are known to include not only monocrystalline oxides but also multicrystalline oxides. For example, homologous oxides. InGaO3(ZnO) having a phase m (m: natural number) is a polymorphic It is known as a primary oxide semiconductor (Non-Patent Documents 2 to 4). And, as described above, Oxide semiconductors composed of n-Ga-Zn oxides are used in the channel layer of thin-film transistors. It has been confirmed to be applicable (Patent Document 5, Non-Patent Documents 5 and 6). [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 1988-1986 [Patent Document 2] Japanese Patent Application Publication No. 8-264794 [Patent Document 3] Special Publication No. 11-505377 [Patent Document 4] Japanese Patent Publication No. 2000-150900 [Patent Document 5] Japanese Patent Publication No. 2004-103957 [Non-patent literature]

[0006] [Non-Patent Document 1] MW Prins, KO Grosse-Holz, G. Muller, JFM Cillessen, JB Giesbers, RP Weening, and RM Wolf, "A ferroelectric transparent thin-film transistor", Appl. Phys. Lett., 17 June 1996, Vol.68 p.3652 [Non-Patent Document 2] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, p.298-315 [Non-licensed Document 3] N. Kimizuka, M. Isobe, and M. Nakamura, "Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m(m=3,4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m(m=7,8,9, and 16) in the In2O3-ZnGa2O4-ZnO System", J. Solid State Chem., 1995, Vol.116, p.170-178 [Non-licensed Document 4] Masaki Nakamura, Noboru Kimizuka, Naohiko Mori, Mitsumasa Isobe, "The crystal structure of the ホモロガス phase, InFeO3(ZnO)m(m: natural number) and the same type of compound", Solid State Physics, 1993, Vol.28, No.5, p.317-327 [Non-licensed Document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, "Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor", SCIENCE, 2003, Vol.300, p.1269-1272 [Non-licensed Document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors", NATURE, 2004, Vol.432 p.488-492

Summary of the Invention

Problems to be Solved by the Invention

[0007] By the way, in an active matrix type semiconductor display device, the number of pixels tends to increase in order to display higher-definition and higher-resolution images. Therefore, high-speed driving is required for the scanning line drive circuit and the signal line drive circuit, and the problem of high power consumption due to the high driving frequency has emerged. In addition, the semiconductor display device is also required to have high reliability so that it can withstand continuous use for a long time. For example, when the video displayed on the semiconductor display device is fixed, a phenomenon called image sticking occurs, in which deterioration of the semiconductor element or the display element progresses in a specific pixel. Image sticking is a phenomenon observed in the entire semiconductor display device, but it is particularly likely to occur significantly in semiconductor display devices such as liquid crystal display devices, light-emitting devices using organic light-emitting elements, and surface conduction electron emission element displays (SED). In order to achieve the high reliability and low power consumption driving required for these semiconductor display devices, it is necessary not only to improve the characteristics of the semiconductor element or the display element, but also to devise the driving method. Due to the continuous use of the semiconductor display device for a long time, the semiconductor element or

[0008] ​​​​​​​​​​This is one of the driving methods to prevent the display elements from degrading and to prevent excessive power consumption. One example is partial drive. Partial drive is a method where the image displayed on the screen is partially... When there is no change over a period of time, the image is displayed only in a limited area of ​​the pixel, and This is a driving method that stops the display of images in other areas.

[0009] However, even when using partial drive, the drive circuit continues to operate, and its power consumption The power consumption was not significantly reduced compared to normal operation.

[0010] In light of the above-mentioned challenges, one of our objectives is to provide highly reliable semiconductor display devices. Alternatively, One of our goals is to provide semiconductor display devices that can reduce power consumption.

[0011] Alternatively, one of the objectives is to provide a driving method for semiconductor display devices that can improve reliability. Alternatively, one of the objectives is to provide a driving method for semiconductor display devices that can reduce power consumption. do. [Means for solving the problem]

[0012] To solve the above problem, a scan line driving circuit sequentially selects only the pixels of the lines to be displayed. This is provided in the semiconductor display device. Specifically, a decoder is provided in the scan line driving circuit, and the scan line According to the signal input to the drive circuit, sequentially scans only the scan lines of the pixels of the line to be displayed. The scan lines of pixels in lines that receive a pulse and do not display anything else receive a pulse. It operates without applying force. Then, all pixels of the line selected by the pulse, Alternatively, by supplying a video signal from the signal line drive circuit to some of the pixels of a selected line. The image is displayed only for pixels located in a specific area of ​​the pixel region.

[0013] Note that the display of the image across the entire pixel area and the display of the image in a part of the pixel area are different. It can be controlled by a signal input to the controller. The image is displayed in a portion of the pixel area. When displaying, the signal input to the decoder determines which of the multiple pixels in the pixel section is a specific pixel. It is sufficient to sequentially input pulses only to the scan lines that each pixel of the line possesses. Furthermore, the entire pixel area is used to create the image. When displaying an image, the signal input to the decoder determines the scan lines of all the pixels in each line. Simply input pulses in sequence.

[0014] Furthermore, the pixels are controlled to switch according to the pulses of the signal input to the scan line, At a minimum, one thin-film transistor is required, and when that thin-film transistor is turned on, a signal line driving circuit is generated. It has a display element whose operation is controlled according to a video signal provided from there. The thin-film transistor described above uses an oxide semiconductor in the channel formation region. Furthermore, scanning line drive In some or all of the dynamic circuits and signal line drive circuits, oxide semiconductors are used. Conductor elements, such as thin-film transistors in which oxide semiconductors are used in the channel formation region It is acceptable for such a provision to be made.

[0015] Furthermore, oxide semiconductors are quaternary metal oxides, specifically In-Sn-Ga-Zn-O system oxide semiconductors. Conductors, and ternary metal oxides such as In-Ga-Zn-O oxide semiconductors and In-Sn-Z nO-based oxide semiconductors, In-Al-Zn-O-based oxide semiconductors, Sn-Ga-Zn-O-based Oxide semiconductors, Al-Ga-Zn-O based oxide semiconductors, Sn-Al-Zn-O based oxide semiconductors Conductors, and binary metal oxides such as In-Zn-O oxide semiconductors and Sn-Zn-O oxide semiconductors. Monocrystalline semiconductors, Al-Zn-O oxide semiconductors, Zn-Mg-O oxide semiconductors, Sn-Mg -O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, In-Ga-O-based oxide semiconductors and Using In-O-based oxide semiconductors, Sn-O-based oxide semiconductors, Zn-O-based oxide semiconductors, etc. It is possible to be. In this specification, for example, In-Sn-Ga-Zn-O system Oxide semiconductors include indium (In), tin (Sn), gallium (Ga), and zinc (Zn). This means a metal oxide containing [a certain compound], and its stoichiometric composition ratio is not particularly specified. The oxide semiconductor may contain silicon.

[0016] Alternatively, oxide semiconductors have the chemical formula InMO3(ZnO). m It can be expressed as (m>0) Here, M is one or more metallic elements selected from Ga, Al, Mn, and Co. This indicates.

[0017] Furthermore, after forming the oxide semiconductor film, the process is carried out under a reduced pressure atmosphere or an inert gas atmosphere. Heat treatment removes moisture and hydroxyl groups adsorbed on the surface and inside the oxide semiconductor film. or remove hydrogen, etc. The temperature range for the heat treatment is preferably 400°C to 700°C. Alternatively, the temperature should be between 450°C and 650°C. By performing the above heat treatment, the oxide semiconductor film will be heated. , water present within the gate insulating film, or at and near the interface between the oxide semiconductor film and other insulating films. Impurities such as hydroxyl groups or hydrogen are removed. Therefore, the above impurities are removed. This can prevent the degradation of the ZISTA's properties.

[0018] Furthermore, thin-film transistors may be bottom-gate type or top-gate type. Both bottom-contact and bottom-gate transistors are good. A gate electrode on a surface, a gate insulating film on the gate electrode, and a gate electric field on the gate insulating film. An oxide semiconductor film overlapping the electrode, a source electrode and a drain electrode on the oxide semiconductor film, and an oxide A semiconductor film, an oxide insulating film on the source electrode and drain electrode, and oxidation on the oxide insulating film It has a conductive film that overlaps with a semiconductor film. The top gate type transistor has an acid on the insulating surface. A semiconductor film, a gate insulating film which is an oxide insulating film on the oxide semiconductor film, and a gate insulating film It has a gate electrode that overlaps with an oxide semiconductor film and functions as a conductive film. A bottom-contact transistor has a gate electrode on an insulating surface and a gate electrode on the gate electrode. A gate insulating film, a source electrode on the gate insulating film, a drain electrode, and a source electrode, drain electrode An oxide semiconductor film that is in the finest position and overlaps with the gate electrode on the gate insulating film, and an acid An oxide insulating film on an oxide semiconductor film, and a conductive layer on the oxide insulating film that overlaps with the oxide semiconductor film. It has a membrane. [Effects of the Invention]

[0019] The scan line drive circuit is operated to input pulses only to the pixels of the specified line. This prevents power from being consumed on scan lines other than the designated line, and oxide It is possible to reduce the power consumption of semiconductor display devices using semiconductors. Also, specified By operating the scan line drive circuit to input pulses only to the pixels of the semiconductor surface, the semiconductor surface To prevent prolonged continuous use of the display device, semiconductor elements or display elements using oxide semiconductors This can prevent deterioration. [Brief explanation of the drawing]

[0020] [Figure 1] A block diagram of a semiconductor display device and a diagram showing the configuration of the pixel section. [Figure 2] Pixel timing chart. [Figure 3] Pixel timing chart. [Figure 4] A diagram showing the arrangement of areas within the pixel region where an image is displayed. [Figure 5] A diagram showing the decoder configuration. [Figure 6] Cross-sectional and top views of a transistor. [Figure 7] Cross-sectional and top views of a transistor. [Figure 8] Cross-sectional and top views of a transistor. [Figure 9] A circuit diagram showing the configuration of a NOR gate. [Figure 10] A circuit diagram showing the configuration of a NOR gate. [Figure 11] Block diagram of a semiconductor display device. [Figure 12] Circuit diagram of the pixel section. [Figure 13] Circuit diagram of the pixel section. [Figure 14] Top view and cross-sectional view of the electronic paper. [Figure 15] A diagram showing an example of an image displayed in certain areas. [Figure 16] A schematic diagram showing the order of initialization period, write period, and retention period. [Figure 17] A timing chart showing the voltage applied to the pixel electrodes and the voltage of the selection signal input to each scan line. [Figure 18] A diagram illustrating the configuration of a signal line drive circuit. [Figure 19] A circuit diagram showing the configuration of a shift register. [Figure 20] A timing chart illustrating the configuration of the pulse output circuit and the operation of the shift register. [Figure 21]A diagram illustrating the method for fabricating a semiconductor device. [Figure 22] A diagram illustrating the method for fabricating a semiconductor device. [Figure 23] A diagram illustrating the method for fabricating a semiconductor device. [Figure 24] A diagram illustrating the method for fabricating a semiconductor device. [Figure 25] A diagram illustrating the method for fabricating a semiconductor device. [Figure 26] A diagram illustrating the method for fabricating a semiconductor device. [Figure 27] Cross-sectional view of a liquid crystal display device. [Figure 28] Cross-sectional view of the light-emitting device. [Figure 29] A diagram showing the configuration of a liquid crystal display module. [Figure 30] A diagram of an electronic device using a semiconductor display device. [Modes for carrying out the invention]

[0021] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... Not limited to the following description, the present invention may have forms and characteristics that do not depart from the spirit and scope of the invention. Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention This shall not be interpreted as being limited to the contents of the embodiments described below.

[0022] The semiconductor display devices of the present invention include liquid crystal display devices and organic light-emitting devices (OLEDs). A light-emitting device equipped with a light-emitting element in each pixel, electronic paper, DMD (Digital Microwave Oscillator) romirror device), PDP (Plasma Display Pane) l), SED (Surface-conduction Electron-emitter) Field Emission Display (FED) ) and other semiconductor display devices that have circuit elements using semiconductor films in their drive circuits, It falls into that category.

[0023] (Embodiment 1) Figure 1(A) shows, as an example, a block diagram of a semiconductor display device according to one aspect of the present invention.

[0024] The semiconductor display device shown in Figure 1(A) comprises multiple pixels, each containing a display element and a thin-film transistor. A pixel section 100, a scan line driving circuit 101 that selects each pixel line by line, and selected It also has a signal line driving circuit 102 that controls the input of video signals to the pixels of the line. Furthermore, as shown in Figure 1(B), the pixel section 100 is extended from the scan line driving circuit 101 Multiple scan lines G1 to Gy and multiple signal lines extended from the signal line drive circuit 102 S1 to Sx are arranged to intersect. Each pixel 105 has multiple scan lines At least one and at least one of multiple signal lines are provided, which are input to the scan line. The signal and the signal input to the signal line control each pixel 105 display element and thin film transistor The operation of the device is controlled.

[0025] The scan line drive circuit 101 has a decoder 103, and input to the scan line drive circuit 101 Its operation is controlled by n-bit control signals D1 to Dn. Specifically, the control Depending on the combination of the values ​​of each bit in signals D1 to Dn, the decoder 103 outputs to scan line G1 ~Gy can be sequentially input with selection signals having pulses. Also, control signal D1~ The combination of the values ​​of each bit in Dn determines the scan lines that the pixels of the lines to be displayed have. Only pulses are input in order, and the scan lines of pixels on lines that do not display other pulses are not used. The scan line drive circuit 101 can be operated in a way that does not input a RUSS signal.

[0026] For example, in the pixel area 100 shown in Figure 1(B), the image is displayed only in area 104. This shall be done. In this case, the scan lines G1 to Gt-1 of the pixels in area 104 The pulses are input in order, and the scan lines Gt~G of the pixels of the lines that do not display anything else are input. To prevent pulse input to y, the combination of values ​​for each bit of the control signals D1 to Dn is used. This activates the scan line drive circuit 101.

[0027] The signal line drive circuit 102 receives the video signal and controls the drive of the signal line drive circuit 102. A drive signal is input. All pixels of the line selected by the pulse, or selected A video signal is supplied from the signal line drive circuit 102 to some of the pixels in the line. The image is displayed only in pixels located in a specific area 104 of the pixel section 100. This can be done. Specifically, in Figure 1(B), the signal line S1 is driven from the signal line drive circuit 102. A video signal that contains image information only in ~Sq-1 (a natural number greater than 2 and less than x). By inputting this signal, and inputting video signals that do not contribute to image display to the signal lines Sq~Sx, The image is displayed only for pixels located in area 104.

[0028] Furthermore, video signals that do not contribute to image display refer to the current or electrical signals that the pixel has to the display element. This is a video signal that interferes with the provision of pressure. A video signal that does not contribute to image display is input to a pixel. When this occurs, the supply of current or voltage to the display elements within the pixel is hindered, or multiple consecutive pixels are affected. Because the gradation displayed by the display element is maintained throughout the frame period, the pixel The image will not be displayed.

[0029] Furthermore, a video signal containing image information is transmitted from the signal line drive circuit 102 to the selected line. If the input is only to some of the pixels, specifically the video signal is in a particular area 104 It is supplied only to the signal lines S1~Sq-1 of the pixels within it. The frame frequency is constant. If so, input a video signal that has image information in all pixels of the selected line. Rather than the case where a video signal containing image information is input to some pixels of the selected line, In this case, the driving frequency of the signal line driving circuit 102 can be kept low, thus reducing consumption It can reduce electricity consumption.

[0030] Note that in Figure 1(B), a portion of area 104 where the image is displayed is connected to signal lines S1~Sq-1 This is a group of pixels having scan lines G1 to Gt-1, located in the upper left of the pixel section 100. This is an example of a combination. However, the present invention is not limited to this configuration, and for example, as shown in Figure 4(A) Furthermore, it is acceptable if a part of the area 104 that displays the image is located in the upper right corner of the pixel area 100. Alternatively, it may be located in the center of the pixel portion 100 as shown in Figure 4(B), or as shown in Figure 4(C). As shown, it may be located in the lower left of the pixel portion 100. The position and range of A104 are determined by the position of the line selected by the scan line drive circuit 101. Depending on the position of the signal line to which a video signal containing image information is input from the signal line drive circuit 102 That can be decided as needed.

[0031] Next, an example of the specific configuration of decoder 103 is shown in the circuit diagram in Figure 5. D is a multiple NOR gate 106-1~106-2 nhas, and each NOR circuit has an n-bit control signal input. Note that the number of NOR circuits shown in FIG. 5 is merely an example , and it is not necessarily n 2, and the number of NOR circuits is not restricted by the number of bits of the control signal .

[0032] The n-bit control signal is selected from the control signals D1 to Dn or the control signals Db1 to Dbn obtained by inverting the polarities of the control signals D1 to Dn, and the NOR circuits 106-1 to 106-2 n have different control signals input to each other. For example, the NOR circuit 106- 1 has the control signals D1 to Dn input. The NOR circuit 106-2 has the control signals D2 to Dn and the control signal Db1 input. The NOR circuit 106-3 has the control signals D1, D3 to Dn and the control signal Db2 input. Thus, by having different control signals input to the NOR circuits 106-1 to 106 n -2 n to each other, only the signal output from any one of the NOR circuits 106-1 to 106 -2 n can have a voltage at a different height from the signals output from the others. Specifically, only the signal output from any one of the NOR circuits 106-1 to 106-2 can be at a high level (Hi) voltage and the others at a low level (L n o) voltage. And by changing the values of the control signals D1 to Dn and the control signals Db1 to Dbn at predetermined intervals, a signal with a pulse of a high level voltage shifting can be output from the NOR circuits 106-1 to 106-2 . n from a high

[0033] The NOR circuits 106-1 to 106-2 nThe signal output from is used as a selection signal for scan line G1 It is input to ~Gy. Among the scan lines G1~Gy, the voltage corresponding to the pulse of the selected signal is input. The scan lines that are being scanned correspond to the so-called selected scan lines.

[0034] Note that the control signals Db1 to Dbn are generated within the scan line drive circuit 101 by an inverter or the like. It may also be generated by reversing the polarity of the control signals D1~Dn, or by scanning line drive cycle From outside path 101, for example from a controller, along with control signals D1~Dn, scan line drive cycle It is also acceptable if it is entered in road 101.

[0035] When displaying an image in all pixels of the pixel section 100, the scan lines G1 to Gy are selected in order. The values ​​of control signals D1~Dn and Db1~Dbn are determined so that the pulses are input. To display the image only in area 104, select scan lines G1 to Gt-1 in order. A pulse is input to the selector signal, and no pulse is input to the scan lines Gt~Gy, the control signal Determine the values ​​of signals D1 to Dn and the control signals Db1 to Dbn.

[0036] The decoder shown in Figure 5, when an n-bit control signal is input, will at least one of the following: Alternatively, a selection signal with pulses is output from one NOR gate. All scan lines are pulsed. If it is necessary to input a selection signal that does not have a scan line, then the total number of scan lines will be greater than the total number of NOR gates. Design it so that the number of NOR gates is also reduced. Alternatively, for an n-bit control signal, the total number of NOR gates 2 n -a, and the total number of NOR circuits is 2 n -a is equal to or greater than the total number of scan lines y. Alternatively, in addition to the n-bit control signal, a high-level (Hi) voltage is applied to all NO signals. The configuration applies the signal to all R circuits simultaneously, forcing the output from all NOR circuits to a low level. It is also acceptable to set the voltage to (Lo).

[0037] Figure 2 shows the inputs to scan lines G1 to Gy when displaying an image in all pixels of the pixel section 100. This shows the timing chart of the selected signal and the video signals input to signal lines S1~Sx. As shown in Figure 2, when displaying an image in all of the pixel units 100, one frame During the specified period, selection signals with sequentially shifted voltage pulses are input to scan lines G1 to Gy. Therefore, every pixel in every line becomes a display line that displays. During the one-line period in which a pulse appears in the selection signal input to the line, signal line S A video signal containing image information is input to terminals 1 through Sx.

[0038] Furthermore, Figure 3 shows the case where the image is displayed only in a part of area 104 of the pixel section 100. The selection signal input to scan lines G1~Gy and the video signal input to signal lines S1~Sx The timing chart is shown. As shown in Figure 3, the image is displayed only in area 104. When performing this operation, voltage pulses are sequentially applied to scan lines G1 to Gt-1 during one frame period. A selected signal is input, and the scan lines Gt~Gy do not have pulses, that is, A selection signal with a flat voltage profile is input. Therefore, scan lines G1 to Gt-1 The pixels of the lines that have a scan line Gt~Gy become the display lines that are displayed, and the lines that have scan lines Gt~Gy The pixels become non-display lines that are not shown. And, when a pulse appears in the selection signal 1 During the line period, when a video signal is input to signal lines S1~Sx, scan line G1 The video signal is input only to the pixels of the display line that has ~Gt-1. Also, Area 1 The video signal input to the signal lines S1~Sq-1 of the pixel 04 contains image information, The video signal input to lines Sq~Sx does not contribute to the display of the image. Therefore, as shown in Figure 3. Depending on the driving method, the image can be displayed only in the pixels of area 104.

[0039] Furthermore, after scanning up to scan line Gt-1 is completed, the video input to signal lines S1~Sq-1 Set the O signal to a constant voltage that does not contribute to image display, or do not input a video signal. The signal lines S1 to Sq-1 can also be left floating. With the above configuration, the scan line Gt- After scanning up to 1 is complete, charging and discharging of signal lines S1 to Sq-1 ceases, so the signal lines This can reduce the power consumption of the power circuit.

[0040] Furthermore, the signal line drive circuit 10 is configured to input video signals only to signal lines S1 to Sq-1. You may also operate step 2. In this case, if you want to display the image in all of the pixel units 100... Furthermore, the driving frequency of the signal line driving circuit 102 can be lowered, thereby reducing power consumption.

[0041] Note that in Figures 2 and 3, the video signals input to signal lines S1 to Sx are displayed as pulses. However, depending on the image information contained in the video signal, it is certainly possible that no pulses will appear.

[0042] Furthermore, in Figures 2 and 3, the video signal is input sequentially to each signal line from the signal line drive circuit 102. A timing chart for sequential point drive is shown as an example. However, the present invention is not limited to this configuration. The wiring sequence is not fixed, and the video signal is input in parallel to all signal lines from the signal line drive circuit 102. It can also be the next drive.

[0043] Furthermore, if the image is to be displayed in only a part of area 104, the entire pixel area 100 will not be displayed. By deliberately lowering the frame frequency compared to when performing the operation, the scan line drive circuit 101 is set to... Therefore, by reducing the number of scans required to sequentially select scan lines, the power consumption of the scan line drive circuit is reduced. You can also lower it.

[0044] Also, in the case of time-gradation drive, the number of scans is reduced by lowering the frame frequency. You can do that, or you can reduce the number of scans by lowering the number of grayscale levels, and reduce the scan line count. The power consumption of the drive circuit may be reduced. Time-based gradation driving refers to the period of one frame. This is a driving method for displaying gradations by controlling the time that pixels display white.

[0045] A semiconductor display device according to one aspect of the present invention provides pulse input only to the pixels of a specified line. The scan line drive circuit is operated in such a way that power is lost on scan lines other than the specified line. This prevents the consumption of energy, thereby reducing the power consumption of semiconductor display devices. Furthermore, the scan line drive circuit is operated to input pulses only to the pixels of the specified line. By doing so, in the pixel area 100, areas other than some areas 104 will be affected for a long period of time. Prevents continuous use and prevents degradation of semiconductor elements such as thin-film transistors or display elements. It is possible.

[0046] The semiconductor display device shown in Figure 1(A) comprises a pixel unit 100, a scan line driving circuit 101 or The system may be a system-on-panel configuration in which the signal line drive circuit 102 is formed on a single board. By using a MUON panel, the scanning line driving circuit 101 or the signal line driving circuit 102, etc. The number of pins required to connect the drive circuit and the pixel unit 100 has been reduced, and the connection between the drive circuit and the pixel unit is not Yield reduction due to poor quality, low mechanical strength at connection points using pins, etc. This makes it possible to avoid this. Furthermore, not only can the display device be miniaturized, but the assembly and inspection processes can also be improved. Cost reduction through optimization will also be possible with the implementation of system-on-panel integration. In the case of panels, connections such as FPC (Flexible Printed Circuit) are used. Through the unit, various signals such as control signals, video signals, and drive signals are transmitted from the controller, and electricity The source voltage is supplied to the pixel unit 100, the scan line drive circuit 101, or the signal line drive circuit 102. It can be done.

[0047] Furthermore, the semiconductor display device of the present invention is not limited to a system-on-panel configuration. It is used in the output section of the scan line drive circuit 101 and the signal line drive circuit 102. Analog switches and other components are formed on a single substrate together with the pixel section 100, and the remaining drive frequency It is also possible to form a circuit with a relatively large number of components on a separate board. In this case, the drive frequency is A high-speed circuit is formed using semiconductor elements made of single-crystal semiconductors, and the pixel portion 100 and the driving frequency Low-cost circuits can be formed using semiconductor elements made of oxide semiconductors. By partially adopting a system-on-panel approach, the yield reduction caused by the aforementioned connection problems can be reduced. To avoid the low mechanical strength at connection points using pins, or in the assembly process The advantages of a system-on-panel, such as cost reduction through the elimination of inspection processes, are somewhat limited. It can be enjoyed to a certain extent. Furthermore, the pixel unit 100, the scan line driving circuit 101 and the signal line driving circuit 102 Compared to a system-on-panel where everything is formed on a single substrate, the performance of circuits with high drive frequencies is improved. It can be improved further, and it is difficult to achieve when using single-crystal semiconductors. It is possible to form pixel areas with a large surface area.

[0048] (Embodiment 2) In this embodiment, an oxide semiconductor film used in the pixels or driving circuits of a semiconductor display device. Regarding the configuration of a thin-film transistor having a channel formation region, the channel etch structure Let's explain using the Tomgate model as an example.

[0049] Figure 6(A) shows a cross-sectional view of thin-film transistor 201, and Figure 6(B) shows the thin film shown in Figure 6(A). The top views of transistor 201 are shown below. Note that the dashed line A1-A2 in Figure 6(B) The cross-sectional view shown corresponds to Figure 6(A).

[0050] The thin-film transistor 201 has a gate electrode 203 formed on the substrate 202, and a gate electrode The gate insulating film 204 formed on 203 and the gate electrode 203 are located at a position where they overlap. Island-shaped oxide semiconductor film 205 formed on the insulating film 204, and island-shaped oxide semiconductor film Source electrode 206 and drain electrode 207 formed on 205, and oxide semiconductor film 20 5. Having an oxide insulating film 208 formed on the source electrode 206 and the drain electrode 207. They are doing it.

[0051] An insulating film, which serves as an underlay, may be provided between the gate electrode 203 and the substrate 202. The underlayer is an insulating film that prevents the diffusion of impurity elements from the substrate 202, specifically silicon nitride. A film, silicon oxide film, silicon nitride film, or silicon oxide nitride film may be used as a single layer, or Multiple selected films can be stacked and used. The material of the gate electrode 203 is molybdenum. Metal materials such as butene, titanium, chromium, tantalum, tungsten, neodymium, and scandium Materials, conductive films using alloy materials mainly composed of these metal materials, or nitrides of these metals It can be used in a single layer or in a laminated form. If they can withstand the temperature, aluminum and copper can also be used as the above-mentioned metal materials. .

[0052] For example, the two-layer stacked structure of the gate electrode 203 consists of a titanium nitride film and a molybdenum film. A stacked two-layer structure is preferable. As for a three-layer stacked structure, a tungsten film or This consists of a tungsten nitride film and an alloy film of aluminum and silicon or an alloy of aluminum and titanium. It is preferable to have a three-layer structure consisting of a gold film and a titanium nitride film or a titanium film.

[0053] In this specification, an oxidized nitride is defined as a compound in which the oxygen content is higher than the nitrogen content. It is a substance, and nitride oxides have a higher nitrogen content than oxygen in their composition. It refers to a substance.

[0054] The film thickness of tectonic acid 203 is 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, a sputtering method using a tungsten target is used to produce 150n After forming a conductive film for the gate electrode of m, the conductive film is processed into the desired shape by etching. The gate electrode 203 is formed by (patterning).

[0055] The gate insulating film 204 is formed by a silicon oxide film using plasma CVD or sputtering. , forming a silicon nitride film, a silicon oxide nitride film, or a silicon nitride oxide film as a single layer or in multiple layers. This can be done. For example, by using silane (e.g., monosilane), oxygen, and nitrogen as film-forming gases. Then, a silicon oxide nitride film can be formed by plasma CVD. In this embodiment, An insulating film with a thickness of 200 nm, formed by the CVD method, is used as the gate insulating film 204. The film deposition conditions were a silane gas flow rate of 4 sccm and a nitrous oxide (N2O) flow rate of 80 The pressure is set to 0 sccm, and the substrate temperature is set to 400°C.

[0056] The island-shaped oxide semiconductor film 205 is formed by using an oxide semiconductor as a target and by sputtering. After forming an oxide semiconductor film, the film is processed into a desired shape by etching or other methods. It is formed. In addition, oxide semiconductor films are formed in a noble gas (e.g., argon) atmosphere, or in an oxygen atmosphere. It can be formed by sputtering in a mixed atmosphere of noble gas and oxygen.

[0057] Furthermore, before depositing the oxide semiconductor film by sputtering, argon gas is introduced to form plasma Reverse sputtering is performed to generate sputtering, and dust adhering to the surface of the gate insulating film 204 is removed. It is preferable to do so. Reverse sputtering is a method in which voltage is not applied to the target side, and an argon atmosphere is used. Under atmospheric pressure, a voltage is applied to the substrate side using an RF power supply to form plasma near the substrate and modify the surface. This is a testing method. Note that nitrogen, helium, or other elements may be used instead of an argon atmosphere. Alternatively, the procedure may be carried out in an atmosphere where oxygen, nitrous oxide, etc., are added to an argon atmosphere. The procedure may also be carried out in an atmosphere containing chlorine, carbon tetrafluoride, etc., in addition to a argon atmosphere.

[0058] The oxide semiconductor film used to form the channel formation region has the semiconductor properties described above. You can use an oxide material that does not have an oxide.

[0059] In this embodiment, the oxide semiconductor film is made of In (indium), Ga (gallium), and Oxide semiconductor target containing Zn (zinc) (In2O3:Ga2O3:ZnO=1:1 Using :1) a sputtering method, an In-Ga-Zn-O non-single crystal film is used. In this embodiment, the DC sputtering method is used, the argon flow rate is set to 30 sccm, and the oxygen is The flow rate is set to 15 sccm, and the substrate temperature is set to room temperature.

[0060] Even if the gate insulating film 204 and the oxide semiconductor film are formed continuously without exposure to the atmosphere, Good. By continuously depositing the film without exposure to the atmosphere, the interface becomes less susceptible to water and hydrocarbons. Each layer interface is formed without being contaminated by atmospheric components or impurity elements suspended in the atmosphere. This allows for a reduction in variations in the characteristics of thin-film transistors.

[0061] Furthermore, to remove water, hydrogen, and hydroxyl groups contained in the oxide semiconductor film 205, Under reduced pressure, under an inert gas atmosphere such as nitrogen or a rare gas, under an oxygen gas atmosphere, or in an ultra-dry atmosphere Dry air (measured using a CRDS (Cavity Ring-Down Laser Spectroscopy) type dew point meter) In that case, the moisture content is 20 ppm or less (dew point equivalent to -55°C), preferably 1 ppm or less. Preferably in an atmosphere of 10 ppb or less (air), at a temperature of 400°C to 700°C, preferably Alternatively, heat treatment of the island-shaped oxide semiconductor film 205 in a temperature range of 450°C to 650°C. It is desirable to perform the following steps, and then slowly cool the mixture in an inert atmosphere to a temperature range of room temperature or above 100°C. It is possible to heat-treat the oxide semiconductor film 205 in the above atmosphere, In membrane 205, water, hydrogen, and hydroxyl groups contained within the membrane are removed.

[0062] Heat treatment can be performed using an electric furnace or GRTA (Gas Rap) which uses heated gas. id Thermal Anneal (Lamp) method or LRTA (Lamp) method using lamp light Using instantaneous heating methods such as the Rapid Thermal Annealing method Yes, it is possible. For example, when performing heat treatment using an electric furnace, the temperature rise characteristic must be 0.1°C / min or higher. The temperature reduction characteristics should be 20°C / min or less, and between 0.1°C / min and 15°C / min. preferable.

[0063] In addition, during the heat treatment, water is added to nitrogen or a noble gas such as helium, neon, or argon. It is preferable that it does not contain hydrogen, etc. Alternatively, nitrogen introduced into the heat treatment device, The purity of noble gases such as helium, neon, and argon is 6N (99.9999%) or higher. Preferably 7N (99.99999%) or higher (i.e., impurity concentration of 1 ppm or less, preferably) It is preferable that the concentration be 0.1 ppm or less.

[0064] After heat treatment, the island-shaped oxide semiconductor film 205 may be partially or entirely crystallized. stomach.

[0065] Furthermore, after the oxide semiconductor film 205 is subjected to heat treatment, the oxide semiconductor film is subjected to an oxygen atmosphere. The 205 may be subjected to heat treatment. As a result of the above heat treatment, the oxide semiconductor film 205 contains This allows for the removal of impurities such as moisture. Then, by heat treatment under an oxygen atmosphere... By creating an oxygen-rich environment in the oxide semiconductor film 205, its resistance can be increased. The heat treatment temperature below is such that the low-melting-point metals such as Zn that make up the oxide semiconductor vaporize. Temperatures that are difficult to achieve, for example, 100°C to less than 350°C, preferably 150°C to less than 250°C. This is done. The oxygen gas used in the above heat treatment under an oxygen atmosphere contains water, hydrogen, etc. It is preferable that this does not occur. Alternatively, the purity of the oxygen gas introduced into the heat treatment device should be 6N (99 0.9999% or higher, preferably 7N (99.99999% or higher), (i.e., impurities in oxygen) It is preferable to set the substance concentration to 1 ppm or less, preferably 0.1 ppm or less.

[0066] Furthermore, the source electrode 206 and drain electrode 207 are located on the island-shaped oxide semiconductor film 205. After forming a conductive film for the drain electrode, the film is patterned by etching or the like. The above patterning forms the source electrode 206 and the drain electrode 207. During this process, a portion of the exposed parts of the island-shaped oxide semiconductor film 205 is etched.

[0067] For example, conductive films for source and drain electrodes include aluminum, chromium, tantalum, Titanium, manganese, magnesium, molybdenum, tungsten, zirconium, beryllium Elements selected from yttrium, or compounds containing one or more of the above elements as components. Gold and other materials can be used. Furthermore, if heat treatment is performed after the formation of the conductive film, this heating... It is preferable to give the conductive film heat resistance to processing. Aluminum alone does not have heat resistance. Because it is inferior and prone to corrosion, if heat treatment is performed after the formation of the conductive film... Combined with heat-resistant conductive materials, it forms a conductive film. Heat-resistant when combined with aluminum. Examples of conductive materials include titanium, tantalum, tungsten, molybdenum, chromium, and neodymium. Elements selected from um and scandium, or compounds containing one or more of the above elements as components. Gold, or nitrides containing the above elements as components, are preferred.

[0068] The film thickness of the source electrode 206 and drain electrode 207 is 10 nm to 400 nm, preferably 1 The wavelength is set to 00nm to 200nm. In this embodiment, a sputtering process using a molybdenum target is performed. After forming a conductive film for the source electrode and drain electrode by the T method, the conductive film is etched by By processing (patterning) them into the desired shape, the source electrode 206 and drain electrode 20 Form 7.

[0069] Furthermore, the oxide insulating film 208 is an island-shaped oxide semiconductor film 205, a source electrode 206 and a drain The low-resistance island-shaped oxide semiconductor is formed by sputtering so as to be in contact with the in electrode 207. The oxide insulating film 208 formed in contact with the conductive film 205 is resistant to moisture, hydrogen, oxygen, and hydroxyl Silicon oxide, which contains as few impurities as possible and blocks their intrusion from the outside. Inorganic insulating films, such as films or silicon nitride films, are used.

[0070] In this embodiment, a silicon oxide film with a thickness of 300 nm is formed as the oxide insulating film 208. The substrate temperature during film formation should be between room temperature and 300°C, and in this embodiment, it is 100°C. The deposition of silicon oxide films by sputtering is carried out under a noble gas (e.g., argon) atmosphere, and oxygen This can be carried out under a specific atmosphere, or under a noble gas (e.g., argon) and oxygen atmosphere. Furthermore, either a silicon oxide target or a silicon target may be used as the target. For example, using a silicon target, silicon oxide can be formed by sputtering in an oxygen atmosphere. It is possible.

[0071] The low-resistance oxide semiconductor film 205 is oxidized by sputtering or PCVD in contact with it. When the insulating film 208 is formed, at least acid is present in the low-resistance oxide semiconductor film 205. The region in contact with the dielectric insulating film 208 preferably has a carrier concentration of 1 × 10⁻⁶. 18 / cm 3 less than As the resistance decreases, it becomes high, resulting in a high-resistivity oxide semiconductor region. Oxide insulating film 2 Due to the formation of 08, the oxide semiconductor film 205 has high resistance near the interface with the oxide insulating film 208. It has an oxide semiconductor region.

[0072] After forming the source electrode 206 and drain electrode 207, the oxide insulating film 208 is formed. Before or after formation, under a reduced pressure atmosphere, under an inert gas atmosphere such as nitrogen or a noble gas, acid Under a gas atmosphere or in ultra-dry air (CRDS (cavity ring-down laser spectroscopy) The moisture content measured using a dew point meter of the ) type is 20 ppm or less (equivalent to a dew point of -55°C). In an atmosphere (preferably 1 ppm or less, preferably 10 ppb or less of air), oxidation The material semiconductor film 205 is subjected to heat treatment again, and the water and hydrogen contained in the oxide semiconductor film 205 The hydroxyl group may be removed. Source electrode 206, drain electrode 207 The heat treatment after formation is carried out considering the heat resistance of the source electrode 206 and drain electrode 207. This is performed at a lower temperature than the heat treatment performed before forming the - electrode 206 and drain electrode 207. This is desirable. Specifically, 350°C to 650°C, preferably 400°C to 60°C. It is best to perform this process in a temperature range below 0°C.

[0073] Furthermore, as shown in Figure 6(C), the thin-film transistor 201 is mounted on the oxide insulating film 208, Furthermore, it may have a conductive film 209. The conductive film 209 is located on the source electrode 206 or Dray The same material or layered structure as that used for the in electrode 207 can be used. Conductive film 209 The film thickness shall be 10 nm to 400 nm, preferably 100 nm to 200 nm. A resist mask is formed using photolithography, and then processed into the desired shape (patterning). The conductive film 209 is formed so as to overlap with the channel formation region of the oxide semiconductor film 205. The conductive film 209 may be in an electrically insulating floating state. It is also acceptable for an electric potential to be applied. In the latter case, the conductive film 209 has a gate electrode 20 It is also acceptable for the same potential as 3 to be applied, or for a fixed potential such as ground to be applied. It is acceptable to have it. By controlling the height of the potential applied to the conductive film 209, the thin-film transistor 20 It is possible to control the threshold voltage of 1.

[0074] Furthermore, when forming the conductive film 209, the insulating film 210 is formed to cover the conductive film 209. It is desirable to do so. The insulating film 210 contains as few impurities as possible, such as water, hydrogen, oxygen, and hydroxyl groups. It does not contain these, and blocks their intrusion from the outside, such as silicon oxide film and silicon nitride film. Which inorganic insulating film should be used?

[0075] Thin-film transistors using oxide semiconductors are similar to thin-film transistors using amorphous silicon. Thin-film transistors using amorphous silicon have higher mobility than standard transistors. It has similarly uniform element characteristics. Therefore, not only the pixel portion, but also the driving frequency is higher than the pixel portion. Oxide semiconductors can be used as semiconductor elements that make up high-wavenumber drive circuits, and lasers - System-on-panel implementation is possible without using processes such as crystallization.

[0076] Furthermore, the gate electrode, source electrode, drain electrode, and Even when a highly resistive metal material is used as the conductive film on the oxide insulating film, the display can be made Pulses are sequentially input only to the scan lines of the pixels, and in a specific area of ​​the pixel, By displaying only the image, the overall power consumption of the semiconductor display device can be reduced, and reliability can be improved. It can improve.

[0077] This embodiment can be implemented in combination with the above embodiment.

[0078] (Embodiment 3) In this embodiment, the structure of the thin-film transistor 201 is different from that of the thin-film transistor 201 shown in Embodiment 2. The configuration of a non-contact thin-film transistor will be described. Note that this is the same as in Embodiment 2. The parts or parts having similar functions, and the processes can be carried out in the same manner as in Embodiment 2. Therefore, repeated explanations will be omitted.

[0079] Figure 7(A) shows a cross-sectional view of the thin-film transistor 211, and Figure 7(B) shows the thin film shown in Figure 7(A). The top views of transistor 211 are shown below. Note that the dashed line B1-B2 in Figure 7(B) The cross-sectional view shown corresponds to Figure 7(A).

[0080] The thin-film transistor 211 has a gate electrode 213 formed on the substrate 212, and a gate electrode A gate insulating film 214 formed on 213, and a source formed on the gate insulating film 214. The electrode 216 and the drain electrode 217 are located at a position overlapping with the gate electrode 213, and the gate is isolated. Island-shaped structures formed on the source electrode 216 and drain electrode 217 so as to be in contact with the edge film 214. The oxide semiconductor film 215 and the oxide insulating film 218 formed on the oxide semiconductor film 215 It has.

[0081] An insulating film, which serves as an underlay, may be provided between the gate electrode 213 and the substrate 212. The undercoat can employ the same materials and layered structure as in Embodiment 2. The material of electrode 213 can be the same as that of Embodiment 2, and a laminated structure can be adopted. .

[0082] The film thickness of gate 213 is 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, a sputtering method using a tungsten target is used to produce 150n After forming a conductive film for the gate electrode of m, the conductive film is processed into the desired shape by etching. The gate electrode 213 is formed by (patterning).

[0083] The gate insulating film 214 employs the same material and layered structure as in Embodiment 2. It can be formed using the manufacturing method shown. In this embodiment, plasma CVD method A 200 nm thick insulating film formed by this process is used as the gate insulating film 214. The test involved a silane gas flow rate of 4 sccm and a nitrous oxide (N2O) flow rate of 800 sccm. The substrate temperature will be set to 400°C.

[0084] Furthermore, the source electrode 216 and drain electrode 217 are placed on the gate insulating film 214, and the source electrode After forming a conductive film for the drain electrode, it is patterned by etching or the like. The conductive film for the source electrode and drain electrode is the same material and lamination as in Embodiment 2. A structure can be adopted.

[0085] In the case of a bottom contact type, the film thickness of the source electrode 216 and the drain electrode 217 is... To prevent the oxide semiconductor film 215 formed thereon from undergoing step breaks, as shown in Embodiment 2 It is desirable to make it thinner compared to the bottom-gate type. Specifically, 10nm to 200nm. Preferably, the wavelength is 50 nm to 75 nm. In this embodiment, a molybdenum target is used. After forming a conductive film for the source electrode and drain electrode by sputtering, the conductive film is then etched. By processing (patterning) the source electrode 216 into the desired shape, the dray An electrode 217 is formed.

[0086] The island-shaped oxide semiconductor film 215 employs the same materials and stacked structure as in Embodiment 2. Using the manufacturing method shown in Embodiment 2, gate insulation is provided at a position overlapping with the gate electrode 213. It can be formed on the source electrode 216 and drain electrode 217 so as to be in contact with the film 214. Cut.

[0087] In this embodiment, the oxide semiconductor film is made of In (indium), Ga (gallium), and Oxide semiconductor target containing Zn (zinc) (In2O3:Ga2O3:ZnO=1:1 Using :1) a sputtering method, an In-Ga-Zn-O non-single crystal film is used. In this embodiment, the DC sputtering method is used, the argon flow rate is set to 30 sccm, and the oxygen is The flow rate is set to 15 sccm, and the substrate temperature is set to room temperature.

[0088] Furthermore, to remove water, hydrogen, and hydroxyl groups contained in the oxide semiconductor film 215, Heat treatment under an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.) The following steps should be taken. For the conditions of the heat treatment, refer to Embodiment 2. Oxidation By heat-treating the material semiconductor film 215, the oxide semiconductor film 215 contains Water, hydrogen, and a hydroxyl group are removed.

[0089] Furthermore, the oxide insulating film 218 is made in contact with the island-shaped oxide semiconductor film 215 by sputtering. It is formed by the same material and layered structure as in Embodiment 2. This can be formed using the manufacturing method shown in Embodiment 2.

[0090] Furthermore, after forming the oxide insulating film 218, an inert gas such as nitrogen or a rare gas is used under a reduced pressure atmosphere. Under a dry atmosphere, under an oxygen gas atmosphere, or in ultra-dry air (CRDS (cavity ring down)). When measured using a dew point meter with a laser spectroscopy method, the moisture content was 20 ppm (in terms of dew point). (air) atmosphere at -55°C or below, preferably 1 ppm or less, preferably 10 ppb or less In this process, the oxide semiconductor film 215 is subjected to heat treatment again, and the oxide semiconductor film 215 contains You may also remove water, hydrogen, and hydroxyl groups. Regarding the heat treatment conditions: You can also refer to Embodiment 2.

[0091] Furthermore, as shown in Figure 7(C), the thin-film transistor 211 is mounted on the oxide insulating film 218, Furthermore, it may have a conductive film 219. The conductive film 219 is located on the source electrode 216 or The same material or layered structure as that used for the rain electrode 217 can be used. Conductive film 21 The film thickness of 9 shall be 10 nm to 400 nm, preferably 100 nm to 200 nm. A resist mask is formed by photolithography and then processed into the desired shape (patterning). By doing so, the conductive film 219 overlaps with the channel formation region of the oxide semiconductor film 215. The conductive film 219 is formed in an electrically insulating floating state. It is also acceptable for it to be in a state where an electric potential is applied. In the latter case, the conductive film 219 has a potential The potential may be the same as that of electrode 213, or it may be a fixed potential such as ground. It may also be given. By controlling the height of the potential applied to the conductive film 219, thin film traction can be controlled. The threshold voltage of the inverter 211 can be controlled.

[0092] Then, when forming the conductive film 219, an insulating film 220 is formed so as to cover the conductive film 219. The insulating film 220 contains as few impurities as possible, such as water, hydrogen, oxygen, and hydroxyl groups. These inorganic insulating films, such as silicon oxide films and silicon nitride films, block the intrusion of these from the outside. Use a border membrane.

[0093] Thin-film transistors using oxide semiconductors are similar to thin-film transistors using amorphous silicon. Thin-film transistors using amorphous silicon have higher mobility than standard transistors. It has similarly uniform element characteristics. Therefore, not only the pixel portion, but also the driving frequency is higher than the pixel portion. Oxide semiconductors can be used as semiconductor elements that make up high-wavenumber drive circuits, and lasers System-on-panel implementation is possible without using processes such as crystallization.

[0094] Furthermore, the gate electrode, source electrode, drain electrode, and Even when a highly resistive metal material is used as the conductive film on the oxide insulating film, Embodiment 1 As explained above, pulses are sequentially input only to the scan lines that the pixels of the lines to be displayed have. By displaying an image only in a specific area of ​​the pixel, the overall consumption of the semiconductor display device is reduced. This allows for reduced power consumption and improved reliability.

[0095] This embodiment can be implemented in combination with the above embodiment.

[0096] (Embodiment 4) In this embodiment, the thin-film transistor 201 shown in Embodiment 2 or Embodiment 3 is used This bottom-gate type transistor with a channel protection structure differs in structure from the thin-film transistor 221 shown. The configuration of the thin-film transistor will be described. Note that the same parts or similar parts as in Embodiment 2 will be described. The parts and processes that have the ability can be carried out in the same manner as in Embodiment 2, so repeatability I will omit the explanation.

[0097] Figure 8(A) shows a cross-sectional view of the thin-film transistor 221, and Figure 8(B) shows the thin film shown in Figure 8(A). The top views of transistor 221 are shown below. Note that the dashed line C1-C2 in Figure 8(B) The cross-sectional view shown corresponds to Figure 8(A).

[0098] The thin-film transistor 221 has a gate electrode 223 formed on the substrate 222, and a gate electrode A gate insulating film 224 formed on 223 and a gate electrode 223 at a position overlapping with the gate electrode 223 Island-shaped oxide semiconductor film 225 formed on an insulating film 224, and island-shaped oxide semiconductor film Of the 225, the island-shaped oxide semiconductor film 22 overlaps with the channel formation region. A channel protective film 231 formed on 5 and an island-shaped oxide semiconductor film 225 formed Source electrode 226 and drain electrode 227, Channel protective film 231, Source electrode 226 The device also includes an oxide insulating film 228 formed on the drain electrode 227.

[0099] An insulating film, which serves as an underlay, may be provided between the gate electrode 223 and the substrate 222. The undercoat can employ the same materials and layered structure as in Embodiment 2. The material of electrode 223 can be the same as that of embodiment 2, and a laminated structure can be adopted. .

[0100] The film thickness of the gate electrode 223 is 10 nm to 400 nm, preferably 100 nm to 200 nm is set. In this embodiment, after forming a conductive film for the gate electrode with a thickness of 150 n m by a sputtering method using a tungsten target, the conductive film is processed (patterned) into a desired shape by etching to form the gate electrode 223.

[0101] The gate insulating film 224 employs the same material and laminated structure as in Embodiment 2 and can be formed using the manufacturing method shown in Embodiment 2 . In this embodiment, an insulating film with a thickness of 200 nm formed by plasma CVD is used as the gate insulating film 224. The film formation conditions are a flow rate of silane gas of 4 sccm, a flow rate of dinitrogen monoxide (N2O) of 800 sccm and a substrate temperature of 400 °C .

[0102] The island-shaped oxide semiconductor film 225 employs the same material and laminated structure as in Embodiment 2 and can be formed on the gate insulating film 224 at a position overlapping the gate electrode 223 using the manufacturing method shown in Embodiment 2 .

[0103] In this embodiment, an In-Ga-Zn-O-based non-monocrystalline film obtained by a sputtering method using an oxide semiconductor target containing In (indium), Ga (gallium), and Zn (zinc) (In2O3:Ga2O3:ZnO = 1:1 :1) is used . In this embodiment, the DC sputtering method is used, with an argon flow rate of 30 sccm, an oxygen flow rate of 15 sccm, and a substrate temperature of room temperature

[0104] ​Furthermore, to remove water, hydrogen, and hydroxyl groups contained in the oxide semiconductor film 225, Under reduced pressure, under an inert gas atmosphere such as nitrogen or a rare gas, under an oxygen gas atmosphere, or in an ultra-dry atmosphere Dry air (measured using a CRDS (Cavity Ring-Down Laser Spectroscopy) type dew point meter) In that case, the moisture content is 20 ppm or less (dew point equivalent to -55°C), preferably 1 ppm or less. Preferably, the product is subjected to heat treatment in an atmosphere of 10 ppb or less (air). For the conditions, refer to Embodiment 2. Heat the oxide semiconductor film 225. Through processing, the oxide semiconductor film 225 loses the water, hydrogen, and hydroxyl contained within the film. The group is removed.

[0105] The channel protection film 231 is formed from the island-shaped oxide semiconductor film 225, and later from the channel formation region. It is formed on the island-shaped oxide semiconductor film 225 so as to overlap with the channel protection film 2. By providing 31, the portion of the oxide semiconductor film 225 that will become the channel formation region Damage during subsequent processes (film thinning due to plasma or etching agent during etching) This can prevent (and so on). Therefore, the reliability of thin-film transistors can be improved. .

[0106] The channel protective film 231 contains an inorganic material containing oxygen (silicon oxide, silicon oxide nitride, silicon nitride oxide). (Such as a material) can be used. The channel protective film 231 can be processed by plasma CVD or thermal CVD. It can be formed using vapor phase growth methods such as the VA or sputtering method. Channel protective film 231 is shaped by etching after film deposition. Here, silicon oxide is shaped by sputtering. By forming a base film and etching it using a mask created by photolithography, the color is produced. A protective film 231 is formed.

[0107] Furthermore, the island-shaped oxide semiconductor film 225 is oxidized by sputtering or PCVD. When the channel protective film 231, which is a material insulating film, is formed, oxygen is supplied from the channel protective film 231. It is supplied and in the island-shaped oxide semiconductor film 225, it is in contact with at least the channel protection film 231. The region preferably has a carrier concentration of 1 × 10⁻⁶ 18 / cm 3 Less than 1 × 1 0 14 / cm 3 By lowering the resistance to a certain level, it becomes highly resistive, entering the high-resistivity oxide semiconductor region. The formation of the channel protection film 231 causes the oxide semiconductor film 225 to become the channel protection film 23 A region of highly resistive oxide semiconductor can be present near the interface with 1.

[0108] Furthermore, the source electrode 226 and drain electrode 227 are connected to an island-shaped oxide semiconductor film 225 and a channel After forming conductive films for the source and drain electrodes on the flannel protective film 231, etching and other processes are performed. It is formed by patterning. As a conductive film for source electrode and drain electrode, The same materials, laminated structure, and film thickness as in Embodiment 2 can be used.

[0109] In this embodiment, the source electrode drain is formed by sputtering using a molybdenum target. After forming a conductive film for electrodes, the conductive film is processed into a desired shape by etching (pattern By (sing), a source electrode 226 and a drain electrode 2 are placed on the island-shaped oxide semiconductor film 225. Forms 27.

[0110] Furthermore, the oxide insulating film 228 consists of island-shaped oxide semiconductor films 225, source electrodes 226, and drain electrodes. The oxide insulating film 228 is formed by sputtering so as to be in contact with the electrode 227. Adopt the same materials and laminated structure as in Form 2, and form using the manufacturing method shown in Form 2 This can be done. When forming the channel protection film 231, it is not always necessary to form the oxide insulating film 228.

[0111] In addition, after forming the source electrode 226 and the drain electrode 227, before or after forming the oxide insulating film 228, in a reduced pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, an acid gas atmosphere, or in an air atmosphere where the moisture content measured using a dew point meter of the CRDS (cavity ring-down laser spectroscopy ) method is 20 ppm or less (dew point conversion of -55 °C), preferably 1 ppm or less, preferably 10 ppb or less, the oxide semiconductor film 225 may be heat-treated again to desorb moisture, hydrogen, and hydroxy groups contained in the oxide semiconductor film 225. Regarding the conditions of the heat treatment, refer to Form 2 for reference.

[0112] In addition, as shown in FIG. 8(C), the thin film transistor 221 may further have a conductive film 229 on the oxide insulating film 228. The conductive film 229 can use the same materials or the same laminated structure as the source electrode 226 or the drain electrode 227. The film thickness of the conductive film 22 9 is 10 nm to 400 nm, preferably 100 nm to 200 nm. And a resist mask is formed by photolithography and processed (patterned ) into a desired shape, so that the conductive film 229 is formed to overlap the channel formation region of the oxide semiconductor film 225. The conductive film 229 is in a floating state where it is electrically insulated ​​​​It is also acceptable for the conductive film 229 to be in a state where an electric potential is applied. In the latter case, the conductive film 229 has a potential The potential may be the same as that of electrode 223, or it may be a fixed potential such as ground. It may also be given. By controlling the height of the potential applied to the conductive film 229, thin film traction can be controlled. The threshold voltage of the inverter 221 can be controlled.

[0113] Then, when forming the conductive film 229, an insulating film 230 is formed so as to cover the conductive film 229. The insulating film 230 contains as few impurities as possible, such as water, hydrogen, and hydroxyl groups. Inorganic insulating films such as silicon oxide films and silicon nitride films block external intrusion. Use.

[0114] Thin-film transistors using oxide semiconductors are similar to thin-film transistors using amorphous silicon. Thin-film transistors using amorphous silicon have higher mobility than standard transistors. It has similarly uniform element characteristics. Therefore, not only the pixel portion, but also the driving frequency is higher than the pixel portion. Oxide semiconductors can be used as semiconductor elements that make up high-wavenumber drive circuits, and lasers System-on-panel implementation is possible without using processes such as crystallization.

[0115] Furthermore, the gate electrode, source electrode, drain electrode, and Even when a highly resistive metal material is used as the conductive film on the oxide insulating film, the display can be made Pulses are sequentially input only to the scan lines of the pixels, and in a specific area of ​​the pixel, By displaying only the image, the overall power consumption of the semiconductor display device can be reduced, and reliability can be improved. It can improve.

[0116] This embodiment can be implemented in combination with the above embodiment.

[0117] (Embodiment 5) In this embodiment, we will describe a specific example of the configuration of the NOR circuit used in the decoder. I will explain.

[0118] Figure 9 shows an example of a NOR gate circuit diagram. All NOR gates shown in Figure 9 are of the n-channel type. It is formed using thin-film transistors.

[0119] Furthermore, the NOR circuit shown in Figure 9 has n source and drain electrodes connected to each other. It has transistors 911-1 to 911-n and transistor 912. In this specification, "connection" refers to a connection in which an electrical signal is transmitted between two electrodes. Furthermore, it is acceptable for another conductor, such as wiring, to be present between the electrodes.

[0120] The source electrodes of the n transistors 911-1 to 911-n are connected to a low-level power supply voltage VS S is given. Also, the drain electrodes of n transistors 911-1 to 911-n are It is connected to the source electrode of transistor 912, and the voltage of the source electrode is transmitted to the scan line. The voltage Vout is given. The drain electrode and gate electrode of transistor 912 are A high-level power supply voltage VDD is provided.

[0121] The NOR gate uses n bits selected from the control signals D1 to Dn and Db1 to Dbn. A control signal is input. At least one of the control signals input to the NOR gate is high. When the voltage level is high, one of the transistors 911-1 to 911-n turns on. A low-level power supply voltage VSS is applied to the scan line as voltage Vout.

[0122] Next, when all the control signals input to the NOR gate become low-level (Lo) voltages, the transistor Transistors 911-1 to 911-n are all turned off. Also, transistor 912 is turned on. Therefore, a high-level power supply voltage VDD is applied to the scan line as voltage Vout.

[0123] Next, Figure 10 shows another example of a NOR gate circuit diagram. The NOR gate shown in Figure 10 is a total It is formed using n-channel thin-film transistors.

[0124] Furthermore, the NOR circuit shown in Figure 10 has its source electrode and drain electrode connected to each other in n The transistors 901-1 to 901-n are connected to each other, with their source and drain electrodes connected to one another. n transistors 902-1 to 902-n, transistor 903, and transistor It has Ta904.

[0125] Transistors 901-1 to 901-n and transistors 902-1 to 902-n are, Each gate electrode is connected to the others. In other words, i is selected from 1 to n. If defined as any number, the gate electrodes of transistors 901-i and 902-i The following are connected. Also, the source electrodes of n transistors 901-1 to 901-n, The source electrodes of the n transistors 902-1 to 902-n are connected to a low-level power supply voltage VS S is given. Also, the drain electrodes of n transistors 901-1 to 901-n are It is connected to the source electrode of transistor 903 and the gate electrode of transistor 904. The drain electrode and gate electrode of transistor 903, and the drain electrode of transistor 904 A high-level power supply voltage VDD is applied to the electrode. The source of transistor 904 The electrodes are connected to the drain electrodes of n transistors 902-1 to 902-n. The voltages across these electrodes are then applied to the scan line as a voltage Vout.

[0126] The NOR gate uses n bits selected from the control signals D1 to Dn and Db1 to Dbn. A control signal is input. At least one of the control signals input to the NOR gate is high. When the voltage level is (Hi), one of the transistors 901-1 to 901-n, and One of the transistors 902-1 to 902-n turns on. Therefore, through the on transistor... Then, a low-level voltage VSS is applied to the scan line as voltage Vout. Also, the ON The source electrode of transistor 903 and the gate of transistor 904 are connected via the transistor. A low-level voltage VSS is also applied to the electrodes.

[0127] Next, when all the control signals input to the NOR gate become low-level (Lo) voltages, the transistor All transistors 901-1 to 901-n and transistors 902-1 to 902-n are turned off. Also, since transistor 903 is on, the power supply voltage VDD is from transistor 90 Current begins to flow through 3, and the source electrode of transistor 903 and the gate of transistor 904 The voltage across the electrode begins to rise.

[0128] And the voltage between the gate electrode and source electrode of transistor 904, that is, the gate voltage, When the power supply voltage VSS + the threshold voltage Vth of transistor 904 is exceeded, transistor 90 4 turns on. When transistor 904 turns on, the power supply voltage VDD is turned on to the transistor Current begins to flow through 904, and the voltage V is the voltage at the source electrode of transistor 904. The output also represents the voltage of the source electrode of transistor 903 and the gate electrode of transistor 904. Following suit, it begins to rise.

[0129] Next, the source electrode of transistor 903 is at the threshold of the power supply voltage VDD - transistor 903. As the voltage value approaches Vth over time, transistor 903 automatically turns off. Also, since transistors 902-1 to 902-n are all off, transistor 904 The gate electrode of transistor 904 becomes floating. Therefore, the gate electrode and source electrode of transistor 904 The voltage difference between them is maintained by the gate capacitance of transistor 904.

[0130] On the other hand, transistor 904 remains in the ON state even after transistor 903 is turned off. Therefore, the voltage Vout, which is the voltage at the source electrode of transistor 904, continues to rise. Therefore, the voltage of the gate electrode of transistor 904 increases as the voltage Vout rises. The voltage continues to rise while maintaining the voltage difference between the gate electrode and the source electrode. As the source electrode and voltage Vout of 904 approach the power supply voltage VDD, the voltage Vout increases. It stops and the voltage is maintained at VDD.

[0131] Thus, as shown in the NOR circuit in Figure 10, the gate electrode of transistor 904 is floating By setting it to this state, when the bootstrap operation is performed, transistor 903 and the transistor Regardless of the threshold voltage of the TA904, the voltage Vout can be made equal to the voltage VDD.

[0132] Furthermore, the NOR circuit shown in Figure 10 performs bootstrap operation, so as described above, The gate electrode of transistor 904 needs to be in a floating state. When the gate electrode of transistor 904 is made to float, the electricity leaking from the gate electrode of transistor 904 The larger the load, the greater the potential increase at the gate electrode due to the bootstrap action. This suppresses the potential of the gate electrode, which becomes lower. In particular, in the NOR circuit shown in Figure 10... In this configuration, transistors 901-1 to 901-n are connected to the gate electrode of transistor 904. Therefore, there are many transistors connected to the gate electrode of transistor 904. Therefore, due to charge leakage from the above transistor, the gate electrode of transistor 904 The electrical potential tends to become low.

[0133] Therefore, as the transistors that make up the NOR circuit shown in Figure 10, oxide semiconductors are channeled A transistor having a channel formation region is used. Because the transistor has a low off-current, the amount of charge leaking from the gate electrode of transistor 904 This can be kept to a minimum. As a result, when performing a bootstrap motion, the transition The potential of the gate electrode of transistor 904 can be increased. Therefore, transistor 90 Since the gate voltage of 4 can be increased, the rise time of voltage Vout can be shortened. This can be done. Also, the amplitude of the potentials of the control signals D1~Dn and Db1~Dbn can be reduced. Because it can be cut, the power consumption of the NOR circuit can be reduced.

[0134] This embodiment can be implemented in combination with the above embodiment.

[0135] (Embodiment 6) This embodiment describes an example of the overall configuration of the semiconductor display device of the present invention. Figure 11 shows a block diagram of the semiconductor display device of the present invention.

[0136] The semiconductor display device shown in Figure 11(A) has multiple pixels, each equipped with a display element and a thin-film transistor. A pixel section 300 having multiple pixels, a scan line driving circuit 301 that selects each pixel line by line, and selection It has a signal line driving circuit 302 that controls the input of a video signal to the pixels of the line.

[0137] In Figure 11(A), the scan line drive circuit 301 has a decoder 303, and the scan line drive The operation of the motor circuit 301 is controlled by n-bit control signals D1 to Dn input to it. Specifically, the combination of the values ​​of each bit in the control signals D1 to Dn determines the decoding. From the 303, a selection signal having pulses is sequentially input to the pixel section 300 via the scan line. This is possible. Also, the display can be changed depending on the combination of values ​​of each bit in the control signals D1 to Dn. Pulses are sequentially input only to the pixels of the lines to be displayed, and to the pixels of the other lines that are not to be displayed. This allows the scan line drive circuit 301 to be operated without receiving pulse input.

[0138] Furthermore, the signal line drive circuit 302 connects the shift register 304 and the sampling circuit 305. It has at least one drive that controls the operation of the shift register 304. The input signals are the clock signal S-CLK and the start pulse signal S-SP. Then, according to these drive signals, timing signals are generated in which pulses shift sequentially. The input is then passed to the sampling circuit 305. The sampling circuit 305 processes the input data. According to the ming signal, the video signal for one line period input to the signal line drive circuit 302 The sampled video signal is then transmitted via the signal line to the pixel section 30 The inputs are entered sequentially into 0.

[0139] Meanwhile, the scan line drive circuit 301 controls the decoder 30 according to the input control signals D1 to Dn. In step 3, a selection signal with pulses is generated and input to each scan line. In pixels with scan lines, the video signal is input via the signal line.

[0140] The time it takes for video signals to be written to all signal lines is called the line period. This is called the interval. In practice, the line period includes the period in which the horizontal retrace period is added to the line period. Sometimes it happens.

[0141] Furthermore, the video signal sampling may be performed sequentially for each corresponding pixel, or within one line. It is also possible to divide the pixels into several groups and perform the process in parallel for each pixel corresponding to each group. stomach.

[0142] In Figure 11(A), the pixel unit 300 is directly connected to the downstream stage of the sampling circuit 305. However, the present invention is not limited to this configuration. A sampling circuit is placed in front of the pixel unit 300. A circuit can be provided to perform signal processing on the video signal output from 305. An example of a circuit that performs this is a buffer that can shape the waveform. .

[0143] Furthermore, in Figure 11(A), the timing signal for sampling the video signal is shifted. Although the present invention is generated using a tracer 304, it is not limited to this configuration. For example, As shown in Figure 11(B), instead of the shift register 304, the decoder 306 is used. It is also possible to generate a timing signal. In this case, the operation of decoder 306 is controlled. The control signals DS1 to DSm are input to the signal line drive circuit 302 as drive signals. .

[0144] By using the decoder 306, the video signal from the signal line drive circuit 302 is transmitted to a specific area. Only the signal lines of a pixel can be sampled and input. The frame frequency is If constant, rather than inputting a video signal to all pixels of the selected line, Inputting a video signal to some pixels of the selected line is preferable to using the signal line drive circuit 302 Since the drive frequency can be kept low, power consumption can be reduced.

[0145] The semiconductor display device shown in Figure 11 consists of a pixel unit 300, a scan line driving circuit 301, or a signal The system may be a system-on-panel configuration in which the line drive circuit 302 is formed on a single substrate. By using a panel, the drive cycle of the scan line drive circuit 301 or signal line drive circuit 302, etc. The number of pins used to connect the road and the pixel unit 300 has been reduced, preventing connection failures between the drive circuit and the pixel unit. To avoid the resulting decrease in yield and the low mechanical strength at connection points using pins. This makes it possible to do so. Furthermore, it not only allows for miniaturization of the display device, but also reduces the assembly and inspection processes. Cost reductions can also be achieved through the implementation of a system-on-panel design. In the case of a flexible printed circuit (FPC), the connection part is Through this, various signals such as control signals, video signals, and drive signals are transmitted from the controller, as well as power signals. Pressure is supplied to the pixel unit 300, the scan line drive circuit 301, or the signal line drive circuit 302. .

[0146] Furthermore, the semiconductor display device shown in Figure 11 is not limited to a system-on-panel configuration. Low-sampling circuits, such as the scan line drive circuit 301 and the signal line drive circuit 302. Analog switches and other components used in the path 305 are formed on a single substrate together with the pixel section 300. Then, the remaining shift register 304 and decoder 306, which have relatively high drive frequencies, are connected to another base It may also be formed on a plate. In this case, a circuit with a high driving frequency can use a single-crystal semiconductor. It is formed from semiconductor elements, and the pixel section 300 and the circuit with a low driving frequency use oxide semiconductors. It can be formed using semiconductor elements. In this way, a system-on-panel can be partially adopted. By using this, the yield reduction caused by the aforementioned connection failures, and the connection points using pins... This avoids the low mechanical strength, reduces costs by shortening assembly and inspection processes, and This allows you to enjoy some of the benefits of a system-on-panel design. Furthermore, the pixel section has 300 pixels, and the running A system on which the signal line drive circuit 301 and the signal line drive circuit 302 are all formed on a single substrate. Compared to Nell, it can further improve the performance of circuits with high drive frequencies, and moreover, it is a single crystal It is possible to form large pixel areas, which is difficult to achieve when using semiconductors. .

[0147] This embodiment can be implemented in combination with the above embodiment.

[0148] (Embodiment 7) In this embodiment, the specific structure of the pixel portion of a semiconductor display device according to one aspect of the present invention is described. Let me explain an example of success.

[0149] Figure 12 shows a light-emitting device in which each pixel is equipped with a light-emitting element, such as an organic light-emitting element (OLED). This is a circuit diagram of the pixel section. The pixel section shown in Figure 12 consists of multiple signal lines S1 to Sx and multiple power supplies. It has lines V1 to Vx and multiple scan lines G1 to Gy. Each of the multiple pixels 310 has a signal line S At least one of the 1~Sx lines, one of the power lines V1~Vx, and one of the scan lines G1~Gy It also possesses.

[0150] Each pixel 310 has a light-emitting element 313 and a switch that controls the input of a video signal to the pixel 310. A switching transistor 311 and a driving transistor that controls the current value supplied to the light-emitting element 313. It has a transistor 312. The gate electrode of the switching transistor 311 is It is connected to one of the scan lines G1 to Gy, and the switching transistor 311 is The drain electrode and the drive electrode are connected such that one is connected to one of the signal lines S1 to Sx, and the other is connected to the drive electrode. It is connected to the gate electrode of the drive transistor 312. The drain electrode and the power electrode are connected such that one is connected to one of the power lines V1 to Vx, and the other is connected to the power line Vx. It is connected to the pixel electrode of the optical element 313. Furthermore, the pixel 310 has a holding capacitance 314. The holding capacity 314 has one electrode connected to one of the power lines V1 to Vx, and the other One electrode is connected to the gate electrode of the drive transistor 312.

[0151] The light-emitting element 313 has an anode, a cathode, and an electroluminescent layer provided between the anode and the cathode. The anode and cathode are used with one as the pixel electrode and the other as the counter electrode. The anode is driven When connected to the source or drain electrode of transistor 312, the anode is connected to the pixel The electrodes and cathode become opposing electrodes. Conversely, the cathode becomes the source electrode of the drive transistor 312 or When connected to a drain electrode, the cathode becomes the pixel electrode and the anode becomes the counter electrode.

[0152] Voltage is supplied from the power supply to the counter electrode of the light-emitting element 313 and to the power line. The voltage difference between the counter electrode and the power line causes the drive transistor 312 to light up when it is turned on. The voltage is maintained at a value such that a forward bias voltage is applied to the element.

[0153] The switching transistor 311 is turned on by the selection signal pulse input to the scan line. When this happens, the voltage of the video signal input to the signal line is the gate of the drive transistor 312. The voltage of this input video signal is applied to the electrodes. According to the voltage of this input video signal, the drive transistor 31 The gate voltage of 2 (the voltage difference between the gate electrode and the source electrode) is determined. The drain current of the drive transistor 312, which flows according to this, is supplied to the light-emitting element 313. As a result, the light-emitting element 313 emits light.

[0154] When displaying an image in a specific area, only the scan lines of the pixels in that area are palpable. Select signals with a specific value are sequentially input. Then, only to the signal lines of the pixels in that area, the image is displayed. By inputting a video signal containing image information, the image can be displayed only in a specific area. It is possible.

[0155] Furthermore, the light-emitting device controls the time during which pixels display white within a single frame. It may be a time-based grayscale drive that displays grayscale, or a video signal that has analog image information. Analog grayscale drive using [a specific method / technology] is also acceptable.

[0156] The configuration of the pixel 310 shown in Figure 12 is just one example of the pixels that the semiconductor display device of the present invention may have. Yes, and the present invention is not limited to the pixel configuration shown in Figure 12.

[0157] Figure 13 is a circuit diagram of the pixel section of a liquid crystal display device, in which each pixel is equipped with a liquid crystal element. The pixel area shown has multiple signal lines S1 to Sx and multiple scan lines G1 to Gy. Each pixel 320 has at least one of the signal lines S1 to Sx and one of the scan lines G1 to Gy. I have it.

[0158] Pixel 320 consists of a transistor 321 that functions as a switching element and a liquid crystal element 322 It has a retaining capacitance 323. The gate electrode of transistor 321 is on scan line G1~ It is connected to one of the scan lines Gy, and the source and drain electrodes of transistor 321 are One end is connected to one of the signal lines S1 to Sx, and the other end is connected to the pixel electrode of the liquid crystal element 322. They are connected. The liquid crystal element 322 has a pixel electrode, a counter electrode, and the space between the pixel electrode and the counter electrode. It has a liquid crystal sandwiched between two. The holding capacitance 323 is opposite the pixel electrode of the liquid crystal element 322. It is provided to hold the voltage applied between the poles. Specifically, it has a holding capacitance 323. Of the pair of electrodes, one is connected to the pixel electrode of the liquid crystal element 322, and the other has a constant voltage Pressure is being applied.

[0159] When scan lines G1 to Gy are selected in order, in the pixel 320 having the selected scan line, Transistor 321 turns on. Then, the video signal input to signal lines S1~Sx A voltage is applied to the pixel electrodes of the liquid crystal element 322 via the ON transistor 321. In the liquid crystal element 322, when a voltage is applied, the orientation of the liquid crystal molecules changes, and consequently the refractive index of the liquid crystal changes. The refractive index changes. Therefore, the transmittance changes according to the voltage of the video signal, so the liquid crystal element Tone gradation can be represented in sub-322.

[0160] When displaying an image in a specific area, only the scan lines of the pixels in that area are palpable. Select signals with a specific value are sequentially input. Then, only to the signal lines of the pixels in that area, the image is displayed. By inputting a video signal containing image information, the image can be displayed only in a specific area. It is possible.

[0161] The configuration of the pixel 320 shown in Figure 13 is just one example of the pixels that the semiconductor display device of the present invention may have. Yes, and the present invention is not limited to the pixel configuration shown in Figure 13.

[0162] (Embodiment 8) In this embodiment, one of the semiconductor display devices of the present invention is electronic paper or digital This section explains semiconductor display devices called "papers."

[0163] Electronic paper allows for control of grayscale levels by applying voltage and also possesses memory capabilities. The display element used is a non-aqueous electrophoretic display element. Specifically, the display element used in electronic paper is a non-aqueous electrophoretic display element. A dynamic display element, a PD with liquid crystal droplets dispersed in a polymer material between two electrodes. Table of LC (polymer dispersed liquid crystal) method Display element, display having chiral nematic liquid crystal or cholesteric liquid crystal between two electrodes. The element has charged microparticles between two electrodes, and the microparticles are moved in the powder by an electric field. A powder transfer type display element can be used. In addition, a non-aqueous electrophoretic type display element can be used. This is a display element in which a dispersion of charged fine particles is sandwiched between two electrodes, and charged A display element having a dispersion of fine particles on two electrodes with an insulating film in between, A twisting ball, having two hemispheres of different colors charged with different charges, is placed between two electrodes. A display element dispersed in a solvent, and multiple charged microparticles dispersed in a solution. This includes display elements that have a chlorocapsule between two electrodes.

[0164] Figure 14(A) shows the pixel section 700 of the electronic paper, the signal line driving circuit 701, and the scan line driving circuit. A top view of circuit 702 is shown.

[0165] The pixel section 700 has multiple pixels 703. In addition, multiple signals are transmitted from the signal line drive circuit 701. The signal line 707 is routed into the pixel section 700. Multiple signals are transmitted from the scan line drive circuit 702. The scan line 708 is routed into the pixel area 700.

[0166] Each pixel 703 has a transistor 704, a display element 705, and a holding capacitor 706. The gate electrode of transistor 704 is connected to one of the scan lines 708. The source electrode and drain electrode of the transistor 704 are connected such that one is connected to one of the signal lines 707, and the other is connected to It is connected to the pixel electrode of the display element 705.

[0167] In Figure 14(A), the voltage applied between the pixel electrode and the counter electrode of the display element 705 is maintained. In order to hold, a holding capacitor 706 is connected in parallel with the display element 705, but the display element 7 If the memory capacity of 05 is high enough to maintain the display, then the retention capacity is 70 It is not always necessary to include a 6.

[0168] Note that in Figure 14(A), each pixel has one transistor that functions as a switching element. The configuration of the provided active matrix type pixel section has been described, but this is only one aspect of the present invention. Electronic paper is not limited to this configuration. The number of transistors provided in each pixel may vary. It's fine if other elements such as resistors and coils are connected in addition to the transistor and capacitor. good.

[0169] Figure 14(B) shows an example of electrophoretic electronic paper with microcapsules, and each image A cross-sectional view of the display element 705 provided on component 703 is shown.

[0170] The display element 705 includes a pixel electrode 710, a counter electrode 711, and the pixel electrode 710 and the counter electrode It has a microcapsule 712 to which a voltage is applied by 711. Transistor 70 One of the source electrodes or drain electrodes 713 of 4 is connected to the pixel electrode 710.

[0171] Inside the microcapsule 712 are positively charged white pigments such as titanium dioxide and carbon Negatively charged black pigments such as black are sealed together with a dispersion medium such as oil. The video signal voltage applied to the pixel electrode 710 is used to determine the relationship between the pixel electrode and the counter electrode. By applying a voltage between them, the black pigment is attracted to the positive electrode and the white pigment to the negative electrode. It can display gradations.

[0172] Furthermore, in Figure 14(B), the microcapsule 712 is located between the pixel electrode 710 and the counter electrode 711. It is fixed in between by a translucent resin 714. However, the present invention is this structure Not limited to the form, the shape is formed by the microcapsule 712, the pixel electrode 710, and the counter electrode 711. The resulting space may be filled with gases such as air or inert gases. However, this In this case, the microcapsule 712 is attached to the pixel electrode 710 and the counter electrode 711 by an adhesive or the like. It is desirable to fix both, or at least one of them.

[0173] Furthermore, the number of microcapsules 712 in the display element 705 is as shown in Figure 14(B). There are not necessarily multiple microcapsules. One display element 705 has multiple microcapsules 712. Alternatively, multiple display elements 705 may have one microcapsule 712. This is also good. For example, two display elements 705 share one microcapsule 712, and one of them A positive voltage is applied to the pixel electrode 710 of the display element 705, and to the other display element 705. Assume that a negative voltage was applied to the pixel electrode 710. In this case, a positive voltage is In the region overlapping with the applied pixel electrode 710, a black color is observed within the microcapsule 712. The pigment is attracted towards the pixel electrode 710, and the white pigment is attracted towards the counter electrode 711. Conversely, in the region overlapping with the pixel electrode 710 to which a negative voltage is applied, the microcap Within cell 712, the white pigment is attracted to the pixel electrode 710, and the black pigment is attracted to the counter electrode 71 It is pulled towards side 1.

[0174] Next, regarding the specific driving method of the electronic paper, the electrophoretic type electronic paper described above... Let me explain with an example.

[0175] The operation of e-paper can be explained by dividing it into an initialization period, a writing period, and a retention period. Yes, it's possible.

[0176] Before switching the displayed image, the gradation of each pixel within the pixel area is first reset during the initialization period. By unifying, the display elements are initialized. By initializing the display elements, afterimages remain. This can be prevented. Specifically, in electrophoretic imaging, each pixel is displayed as either white or black. The gradation displayed by the microcapsules 712 of the display element 705 is adjusted.

[0177] In this embodiment, after inputting an initialization video signal that displays black to the pixels, white is displayed This section describes the initialization process when an initialization video signal, as shown, is input to a pixel. For example, an electrophoretic electronic paper that displays images toward the opposing electrode 711. In this case, first, the black pigment in the microcapsule 712 is directed toward the counter electrode 711, and the white pigment is directed toward the counter electrode 711. A voltage is applied to the display element 705 so that it faces the electrode 710 side. Next, the microcap The white pigment in cell 712 faces the opposing electrode 711, and the black pigment faces the pixel electrode 710. Next, a voltage is applied to the display element 705.

[0178] Also, if the video signal for initialization is input to the pixel only once, it will be displayed before the initialization period. Depending on the gradation, the movement of the white and black pigments within the microcapsule 712 may be incomplete. It ends up being the case that even after the initialization period has ended, the gradation displayed between pixels remains A difference may occur. Therefore, a negative voltage is applied to the common voltage Vcom. By applying Vp to the pixel electrode 710 multiple times, black is displayed, and relative to the common voltage Vcom... It is desirable to display white by applying a positive voltage Vp to the pixel electrode 710 multiple times. It seems so.

[0179] Furthermore, if the grayscale displayed by each pixel's display element is different before the initialization period, The minimum number of times a video signal needs to be input will also vary. Therefore, display before the initialization period. The number of times an initialization video signal is input between pixels is changed to match the grayscale level. This is also acceptable. In this case, pixels that no longer require an initialization video signal will have the same It's a good idea to input the voltage Vcom.

[0180] Furthermore, the voltage Vp or voltage -Vp of the initialization video signal is applied to the pixel electrode 710 multiple times. In order to do this, during the period in which the selection signal pulse is applied to each scan line, the scan line is This process involves repeatedly performing a series of operations: inputting an initialization video signal to the pixels of the lines that the system has. The voltage Vp or voltage -Vp of the initialization video signal is applied to the pixel electrode 710 multiple times. This converges the movement of the white and black pigments within the microcapsule 712, thereby inter-pixel This prevents differences in gradation from occurring and allows for the initialization of pixels in the pixel area.

[0181] During the initialization period, instead of displaying black and then white for each pixel, white is displayed. Alternatively, during the initialization period, each pixel Alternatively, you could display white first, then black, and then white again.

[0182] Furthermore, the timing at which the initialization period begins is the same for all pixels within the pixel area. It's not necessary. For example, you could do it pixel by pixel, or pixel by pixel belonging to the same line. You can also vary the timing at which the initialization period begins.

[0183] Next, during the write period, a video signal containing image information in each pixel is input.

[0184] When displaying an image across the entire pixel area, all scan lines must be powered sequentially within one frame period. A selection signal with a shifted pressure pulse is input. Then, a pulse appears in the selection signal. During the 1-line period, video signals containing image information are input to all signal lines. ru.

[0185] According to the voltage of the video signal applied to the pixel electrode 710, the white inside the microcapsule 712 As the color pigment and black pigment move towards the pixel electrode 710 side or the opposing electrode 711 side, the display element Child 705 displays grayscale.

[0186] Furthermore, during the writing period, similar to the initialization period, the video signal voltage is applied to the pixel electrode 710 multiple times. It is desirable to apply the signal. Therefore, during the period when the selection signal pulse is applied to each scan line In this process, a series of operations is performed in which a video signal is input to the pixels of the line having the scan line. Perform this multiple times.

[0187] Next, during the retention period, a common voltage Vcom is input to all pixels via the signal line, and then scanning... No selection signals are input to the lines, nor are video signals input to the signal lines. Therefore, the display element The white pigment and black pigment within the microcapsule 712 of 705 are paired with the pixel electrode 710. The arrangement is maintained unless a positive or negative voltage is applied between the forward electrodes 711. Therefore, the gradation displayed by the display element 705 is preserved. Thus, during the writing period, the data is written. The selected image will remain displayed even during the retention period.

[0188] If images are displayed only in certain areas, the above-mentioned initialization period and write period will apply. The initialization period can be omitted from the interval and retention period. Figure 16(A) shows 1f During the frame period, the initialization period Ta for the black display, the initialization period Tb for the white display, and the write period. The order in which Tc and retention period Td appear is schematically shown. Initialization period Ta and initialization period Tb The order may be reversed. Also, in Figure 16(B), the image table is shown only in some areas. When performing the operation, the occurrence of the write period Tc and the retention period Td when the initialization period is omitted. The sequence is schematically shown. By omitting the initialization period or reducing the number of initializations, scanning can be performed. This reduces the number of cycles and lowers the power consumption of the scan line drive circuit.

[0189] If you want to display an image in only a portion of the pixels in a certain area, during the writing period, that area A selection signal is input in which voltage pulses are sequentially shifted only to the scan lines of the pixels A, Other scan lines do not have pulses, i.e., the selection signal has a flat voltage profile. Input. Then, within the one-line period in which a pulse appears in the selection signal, the area A video signal containing image information is input only to the signal lines of the pixels A, and the other signal lines... This inputs a video signal that does not contribute to the display of the image.

[0190] Furthermore, even when displaying images in some areas, during the writing period, the pixel electrode 710 It is desirable to apply the voltage of the video signal multiple times. Therefore, each pulse of the selection signal During the period given to the scan line, a video signal is input to the pixels of the line having the scan line. The series of actions of applying force is performed multiple times.

[0191] Furthermore, because the display element 705 used in electronic paper has high memory capacity, initialization is not required. In cases where there is no change in gradation over a continuous frame period, a voltage is applied to the display element. It is also possible to do this without adding anything. For example, as shown in Figure 15(A), a black circle on a white background. After displaying the image with the drawing, the position of the black circle is as shown in Figure 15(B) in Figure 15(A). When displaying an image different from the image shown, the gradation displayed by the display element 705 is in area A. In area B, it remains white; in area C, it remains black; and in area D, it remains white. This is the result. Figure 17 shows the voltage applied to the pixel electrode 710 in the pixels of regions A to D. This shows the timing chart of the voltage of the selection signal input to each scan line.

[0192] In region A, there is no change in gradation even when the image is switched, so a common voltage V is applied to the pixel electrode 710. The voltage com is applied. Since the common voltage Vcom is also applied to the counter electrode 711, the region Display element A continues to display white without any change in gradation. In area B, the image switches. As the gradation changes from black to white during this process, a voltage -Vp is applied to the pixel electrode 710. In area B, the display element shows black. In area C, the gradation does not change even when the image switches. Since there is no chemical reaction, a common voltage Vcom is applied to the pixel electrode 710. The common voltage Vcom is Since it is also applied between the direct electrodes 711, the display element in region C does not change in gradation and continues Display black. In region D, the gradation changes from white to black when the image switches, so the image A voltage Vp is applied to the electrode 710. Therefore, the display element in region D displays white.

[0193] Thus, in pixels where there is no change in gradation over a continuous frame period, the display element When no voltage is applied, the power consumption of the signal line drive circuit can be reduced.

[0194] This embodiment can be implemented in combination with the above embodiment.

[0195] (Embodiment 9) This embodiment describes the configuration of a signal line driving circuit using an n-channel transistor. I will reveal it.

[0196] The signal line driving circuit shown in Figure 18(A) includes a shift register 5601 and a sampling circuit. It has 5602. The sampling circuit 5602 has multiple switching circuits 5602_1 It has ~5602_N (where N is a natural number). Switching circuits 5602_1~5602_N Each of these consists of multiple n-channel transistors 5603_1 to 5603_k (where k is a natural number). It holds.

[0197] The connection relationships of the signal line drive circuit will be explained using the switching circuit 5602_1 as an example. Furthermore, of the source electrode and drain electrode of the transistor, one of them is designated as the first The following description will refer to one terminal as the first terminal and the other as the second terminal.

[0198] The first terminals of transistors 5603_1 to 5603_k are connected to wires 5604_1 to 56, respectively. It is connected to 04_k. The video signals are connected to each of the wires 5604_1 to 5604_k. The input is received. The second terminals of transistors 5603_1 to 5603_k are connected to signal line S1, respectively. ~Sk is connected. The gate electrodes of transistors 5603_1~5603_k are It is connected to line 5605_1.

[0199] The shift register 5601 supplies voltages of increasing magnitude to the wiring 5605_1 through 5605_N. Outputs a timing signal having (H level), and switching circuits 5602_1~560 It has the function of selecting 2_N in order.

[0200] Switching circuit 5602_1 switches transistors 5603_1 to 5603_N. The continuity between wiring 5604_1~5604_k and signal lines S1~Sk (first terminal) The function of controlling the continuity between the child and the second terminal, i.e., the electrical connection of wiring 5604_1~5604_k It has a function to control whether or not to supply power to signal lines S1~Sk.

[0201] Next, regarding the operation of the signal line drive circuit in Figure 18(A), see the timing chart in Figure 18(B). Refer to the diagram for explanation. Figure 18(B) shows the wiring from shift register 5601 to 5605_ The timing signals Sout_1 to Sout_N are input to 1 to 5605_N respectively, The video signals Vdata_1 to Vd are input to wiring 5604_1 to 5604_k respectively. The timing chart for ata_k is shown as an example.

[0202] Note that one operating period of the signal line drive circuit corresponds to one line period in the display device. (Figure 1) Section 8(B) illustrates the case where one line period is divided into periods T1 to TN. T1 to TN are the periods for writing the video signal to a single pixel belonging to the selected row. That is the case.

[0203] During periods T1 to TN, the shift register 5601 receives a high-level timing signal. Outputs are sent sequentially to wiring 5605_1 to 5605_N. For example, during period T1, shift Register 5601 outputs a high-level signal to wire 5605_1. Then the switch The transistors 5603_1~5603_k in the 5602_1 circuit are turned on. Then, wiring 5604_1~5604_k and signal lines S1~Sk become conductive. The wiring 5604_1~5604_k receives input from Data(S1)~Data(Sk). Data(S1)~Data(Sk) are, respectively, transistors 5603_1~5 Through 603_k, write to the pixels in columns 1 through k of the selected row. This is done. In this way, during the period T1 to TN, the pixels belonging to the selected row are sequentially divided into k columns. The video signal is written to number [number].

[0204] As described above, the video signal is written to the pixels in multiple columns, The number of wires or connections can be reduced. Therefore, the connection with external circuits such as controllers can be reduced. The number of sequences can be reduced. Also, the video signal is written to the pixels in multiple columns. Therefore, the writing time can be extended, preventing insufficient writing of the video signal. It is possible.

[0205] Next, using Figures 19 and 20, we will discuss one form of shift register used in a signal line drive circuit. I will explain.

[0206] The shift register consists of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N( The first pulse output circuit 10_1 has a natural number N≧3 (see Figure 19(A)). The pulse output circuit 10_N up to the Nth order receives the first clock signal CK1 from the first wiring 11. The second clock signal CK2 is transmitted from the second wire 12, and the third clock signal is transmitted from the third wire 13. The fourth clock signal CK4 is supplied from the fourth wiring 14, CK3. Also, the first pulse In output circuit 10_1, the start pulse SP1 (first start pulse) from the fifth wire 15 A pulse (R) is input. Also, the nth pulse output circuit 10_n (where n is 2 ≤ n ≤ n) from the second stage onward. For N (a natural number), the signal from the pulse output circuit one stage prior (previous stage signal OUT(n-1) and A natural number (n≧2) is input. Also, in the first pulse output circuit 10_1, two stages The signal from the third pulse output circuit 10_3 in the subsequent stage is input. Similarly, the second stage and subsequent stages In the n pulse output circuit 10_n, the (n+2) pulse output circuit 10_(n The signal from +2) (called the subsequent signal OUT(n+2)) is input. Therefore, each stage From this pulse output circuit, inputs are provided to the subsequent and / or two-stage preceding pulse output circuits. The first output signal (OUT(1)(SR)~OUT(N)) is electrically connected to another wire, etc. The second output signal (OUT(1)~OUT(N)) is output. Note that Figure 19(A) As shown, the last two stages of the shift register receive the subsequent signal OUT(n+2). Because it is not powered, for example, a second start pulse SP2 and a third start pulse The configuration should involve inputting SP3 into each respective input.

[0207] The clock signal (CK) alternates between high and low levels (low voltage) at regular intervals. This is a signal that repeats the following. Here, the first clock signal (CK1) to the fourth clock signal ( CK4) is delayed by 1 / 4 period in order. In this embodiment, the first clock signal ( Using the CK1) to the fourth clock signal (CK4), control is performed to drive the pulse output circuit, etc. conduct.

[0208] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11~ It is electrically connected to one of the fourth wires 14. For example, in Figure 19(A), The first pulse output circuit 10_1 has a first input terminal 21 that is electrically connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal 23 is It is electrically connected to the third wiring 13. Also, the second pulse output circuit 10_2 is Input terminal 21 is electrically connected to the second wiring 12, and input terminal 22 is connected to the third wiring The third input terminal 23 is electrically connected to the fourth wiring 14, and the third input terminal 23 is electrically connected to the fourth wiring 14. Yes, they are.

[0209] Each of the first pulse output circuits 10_1 to the Nth pulse output circuits 10_N has a first input terminal Child 21, second input terminal 22, third input terminal 23, fourth input terminal 24, fifth input terminal Assume that it has a child 25, a first output terminal 26, and a second output terminal 27 (see Figure 19(B)). (See). In the first pulse output circuit 10_1, the first clock signal is connected to the first input terminal 21. When signal CK1 is input, the second clock signal CK2 is input to the second input terminal 22, and the third The third clock signal CK3 is input to input terminal 23, and the start signal is input to the fourth input terminal 24. A pulse is input, and the subsequent signal OUT(3) is input to the 5th input terminal 25, and the 1st output The first output signal OUT(1)(SR) is output from terminal 26, and the second output terminal 27 This indicates that the second output signal, OUT(1), is being output.

[0210] Next, an example of a specific circuit configuration for a pulse output circuit is shown in Figure 20(A).

[0211] Each pulse output circuit has a first transistor 31 to a thirteenth transistor 43. (See Figure 20(A)). Also, the first input terminal 21 to the fifth input terminal 25 mentioned above, In addition to the first output terminal 26 and the second output terminal 27, a first high power supply potential VDD is supplied. Power line 51, power line 52 supplied with a second high power potential VCC, and power line 52 supplied with a low power potential VSS. Signals are sent from the power line 53 to the first transistor 31 through the thirteenth transistor 43, The power supply potential is supplied. Here, the relationship between the power supply potential levels of each power line in Figure 20(A) is: The first power supply potential VDD > the second power supply potential VCC > the third power supply potential VSS. Clock signals 1 (CK1) through 4 (CK4) are set to high level at regular intervals. This is a signal that alternates between high and low levels, with VDD when it is high and VSS when it is low. Let's assume that the potential VDD of power line 51 is set higher than the potential VCC of power line 52. To lower the potential applied to the transistor's gate electrode without affecting its operation. This can suppress the shift in the transistor's threshold voltage and inhibit degradation. It is possible.

[0212] In Figure 20(A), the first transistor 31 has its first terminal electrically connected to the power line 51. The second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode The second transistor 32 is electrically connected to the first terminal 24. The second terminal is electrically connected to the power line 53, and the first terminal of the ninth transistor 39 is electrically connected to the first terminal. They are connected, and the gate electrode is electrically connected to the gate electrode of the fourth transistor 34. The third transistor 33 has its first terminal electrically connected to the first input terminal 21. The second terminal is electrically connected to the first output terminal 26. The fourth transistor 34 is The first terminal is electrically connected to the power line 53, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has its first terminal electrically connected to the power line 53. The second terminal is connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. The pole is electrically connected, and the gate electrode is electrically connected to the fourth input terminal 24. Transistor 36 of 6 has its first terminal electrically connected to the power line 52, and its second terminal is connected to the second The gate electrode of transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected. The gate electrode is electrically connected to the fifth input terminal 25. The seventh transistor 37 has its first terminal electrically connected to the power line 52, and its second terminal connected to the eighth transistor 38. The second terminal is electrically connected, and the gate electrode is electrically connected to the third input terminal 23. The eighth transistor 38 has its first terminal connected to the gate electrode of the second transistor 32 and It is electrically connected to the gate electrode of the fourth transistor 34, and the gate electrode is connected to the second input terminal It is electrically connected to 22. The ninth transistor 39 has its first terminal connected to the first transistor It is electrically connected to the second terminal of the sta 31 and the second terminal of the second transistor 32, and the second terminal The child is connected to the gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40. Electrically connected, the gate electrode is electrically connected to power line 52. 10th transistor The ZISTA 40 has a first terminal electrically connected to the first input terminal 21, and a second terminal connected to the second output terminal It is electrically connected to the power terminal 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39. They are connected. The 11th transistor 41 has its first terminal electrically connected to the power line 53. The second terminal is electrically connected to the second output terminal 27, and the gate electrode is connected to the second transistor The gate electrode of transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected. The 12th transistor 42 has its first terminal electrically connected to the power line 53, and its second terminal The child is electrically connected to the second output terminal 27, and the gate electrode is connected to the gate electrode of the seventh transistor 37. It is electrically connected to the electrode. The 13th transistor 43 has its first terminal connected to the power line 5 It is electrically connected to 3, and the second terminal is electrically connected to the first output terminal 26, and the gate electrode is electrically connected to 3. This is electrically connected to the gate electrode of the seventh transistor 37.

[0213] In Figure 20(A), the gate electrode of the third transistor 33 and the tenth transistor 4 The connection point between the gate electrode of transistor 0 and the second terminal of transistor 9 39 is defined as node A. Also, the gate electrode of the second transistor 32, the gate electrode of the fourth transistor 34, and The second terminal of transistor 35 (number 5), the second terminal of transistor 36 (number 6), and the eighth transistor The connection point between the first terminal of transistor 38 and the gate electrode of transistor 41 (number 11) is at node B. (See Figure 20(A)).

[0214] Timing of a shift register equipped with multiple pulse output circuits as shown in Figure 20(A) Regarding point T, see Figure 20(B).

[0215] As shown in Figure 20(A), the 9th gate electrode is subjected to a second power supply potential VCC. By providing transistor 39, before and after the bootstrap operation, It has the following advantages:

[0216] If there is no 9th transistor 39 to which a second potential VCC is applied to the gate electrode, boot When the potential of node A rises due to the strapping action, the second terminal of the first transistor 31 The potential of the source electrode increases and becomes higher than the first power supply potential VDD. The source electrode of the first transistor 31 switches to the first terminal side, i.e., the power line 51 side. Therefore, in the first transistor 31, between the gate electrode and the source electrode, the gate electrode A large bias voltage is applied between the and drain electrodes, causing significant stress. This can potentially cause transistor degradation. Therefore, a second power supply potential VC is applied to the gate electrode. By providing a ninth transistor 39 to which C is applied, bootstrap operation Although the potential of node A rises as a result, the potential of the second terminal of the first transistor 31 remains above This makes it possible to prevent a rise in voltage. In other words, by providing a ninth transistor 39 Therefore, a negative bias is applied between the gate electrode and source electrode of the first transistor 31. The voltage value can be reduced. Therefore, by using the circuit configuration of this embodiment, a negative bias voltage is applied between the gate electrode and source electrode of the first transistor 31. Because it can also be made smaller, it is possible to suppress the degradation of the first transistor 31 due to stress. Cut.

[0217] Furthermore, the location where the ninth transistor 39 is installed is the second transistor 31 The terminal and the gate electrode of the third transistor 33 are connected via the first and second terminals. Any configuration that allows for this is acceptable. Note that the pulse output circuit in this embodiment may be provided with multiple pulse output circuits. In the case of a shift register, the signal line drive circuit has more stages than the scan line drive circuit, and the 9th stage The transistor 39 can be omitted, which has the advantage of reducing the number of transistors.

[0218] Furthermore, the semiconductor layers of the first transistor 31 to the thirteenth transistor 43 are made of oxide semiconductor material. By using a conductor, the off-current of the transistor is reduced, as well as the on-current and electric field. The effect mobility can be increased, and the degree of degradation can be reduced, so the circuit It can reduce malfunctions within the device. Also, transistors using oxide semiconductors are aluminum Compared to transistors using fast silicon, a high potential is applied to the gate electrode. The degree of transistor degradation is small. Therefore, the power supply that provides the second power potential VCC The same operation can be obtained by supplying the first power supply potential VDD to the line, and the power running between circuits This allows for a reduction in the number of power lines, thus enabling the miniaturization of the circuit.

[0219] Furthermore, the gate electrode of the seventh transistor 37 is supplied with power from the third input terminal 23. A lock signal is supplied to the gate electrode of the eighth transistor 38 by the second input terminal 22. The clock signal is transmitted to the gate electrode of the seventh transistor 37 via the second input terminal 22. The clock signal supplied is sent to the gate electrode of the eighth transistor 38 and to the third input terminal 23. The same effect can be achieved by reversing the wiring so that the clock signal is supplied by [the specified component]. In this case, in the shift register shown in Figure 20(A), the seventh transistor 37 From a state where both transistors 38 and 8 are ON, the 7th transistor 37 turns OFF, Transistor 8 38 is ON, then transistor 7 37 is OFF, and the 8th transistor By turning off the inverter 38, the second input terminal 22 and the third input terminal The decrease in potential at node B, caused by the decrease in potential at 23, is due to the decrease in potential at the 7th transistor 37. This is due to a decrease in the potential of the gate electrode, and a decrease in the potential of the gate electrode of transistor 38 of the eighth transistor. This will occur twice. On the other hand, the shift register shown in Figure 20(A) is shown in Figure 20(B) During the specified period, both the seventh transistor 37 and the eighth transistor 38 are ON. Then, the seventh transistor 37 is ON, the eighth transistor 38 is OFF, and then, By turning off transistor 37 (number 7) and transistor 38 (number 8), , Node B is affected by a decrease in the potential of the second input terminal 22 and the third input terminal 23. The potential drop is reduced to a single instance caused by the potential drop at the gate electrode of the eighth transistor 38. Therefore, the gate electrode of the seventh transistor 37 is connected to the third input terminal 23. Then a clock signal is supplied to the gate electrode of the eighth transistor 38 and the second input terminal 22 It is preferable to have a wiring configuration in which the clock signal is supplied from node B. This is because the number of potential fluctuations is reduced, and noise can also be reduced.

[0220] In this way, the period during which the potential of the first output terminal 26 and the second output terminal 27 is maintained at the L level In between, a configuration is set in which a high-level signal is periodically supplied to node B, and the pulse output This can suppress malfunctions in the force circuit.

[0221] This embodiment can be implemented in combination with the above embodiment.

[0222] (Embodiment 10) In this embodiment, a method for manufacturing a semiconductor display device according to one aspect of the present invention is shown in Figure 21. This will be explained using Figure 26.

[0223] In Figure 21(A), the translucent substrate 400 is made of aluminosilicate glass, Various types of glass used in the electronics industry, such as aluminoborosilicate glass and aluminoborosilicate glass. Lath substrates can be used. Also, flexible synthetic resins such as plastics can be used. While substrates generally tend to have a low heat resistance temperature, they can withstand the processing temperatures in subsequent manufacturing processes. If obtained, it can be used as substrate 400. As a plastic substrate, Polyesters such as polyethylene terephthalate (PET), and polyether sulfonate. Polyethylene (PES), polyethylene naphthalate (PEN), polycarbonate (PC), poly Ether ether ketone (PEEK), polysulfone (PSF), polyetherimide ( PEI), polyarylate (PAR), polybutylene terephthalate (PBT), poly Mid, acrylonitrile butadiene styrene resin, polyvinyl chloride, polypropylene, Examples include polyvinyl acetate and acrylic resin.

[0224] Next, after forming a conductive film over the entire surface of the substrate 400, a first photolithography process is performed. A resist mask is formed, and unwanted parts are removed by etching to create wiring and electrodes (gates). This forms a gate wiring including electrode 401, a capacitive wiring 408, and a first terminal 421. When etching is performed, at least the end of the gate electrode 401 will be etched to form a tapered shape. do.

[0225] The materials used for the above conductive film include molybdenum, titanium, chromium, tantalum, tungsten, and neodymium. Metallic materials such as zinc and scandium, alloy materials mainly composed of these metallic materials, or The metal nitride can be used in a single layer or in a multilayer structure. If it can withstand the heat treatment temperature, aluminum and copper can be used as the above metal material. It is also possible to do so.

[0226] For example, as a conductive film having a two-layer laminated structure, a titanium nitride film and a molybdenum film are laminated. A two-layer structure is preferred. As a three-layer laminated structure, a tungsten film or nitride film is preferred. A tungsten film and an aluminum-silicon alloy film or an aluminum-titanium alloy film. It is preferable to have a three-layer structure in which a titanium nitride film or a titanium film is laminated.

[0227] Next, as shown in Figure 21(B), gate electrode 401, capacitive wiring 408, first terminal 4 A gate insulating film 402 is formed on 21. The gate insulating film 402 is formed by sputtering, PCVD, etc. Using methods such as those described above, the film thickness is set to 50-250 nm.

[0228] For example, a silicon oxide film is used as the gate insulating film 402 by sputtering, with a thickness of 100 nm. It is formed by this. Of course, the gate insulating film 402 is not limited to such a silicon oxide film. Other insulating films such as silicon oxide nitride film, silicon nitride film, aluminum oxide, and tantalum oxide film. These materials may be used to form a single-layer or laminated structure.

[0229] Next, an oxide semiconductor film 403 (In-Ga-Zn-O non-single-layer film) is placed on the gate insulating film 402. A crystal film is formed. After plasma treatment, an In-Ga-Zn-O non-single crystalline film is deposited without exposure to the atmosphere. Deposition of the crystal film is necessary to remove dust and moisture from the interface between the gate insulating film 402 and the oxide semiconductor film 403. It is useful in that it does not cause adhesion. Here, a diameter of 8 inches contains In, Ga, and Zn. Oxide semiconductor target (In-Ga-Zn-O system oxide semiconductor target (In2O3 Using :Ga2O3:ZnO=1:1:1, the distance between the substrate 400 and the target is 170mm, pressure 0.4Pa, DC power supply 0.5kW, oxygen only, argon only. Alternatively, the film is deposited under an argon and oxygen atmosphere. Note that if a pulsed DC power supply is used, This is preferable because it reduces dust generated during film formation and ensures a uniform film thickness distribution. -The thickness of the Zn-O non-single crystal film shall be 5 nm to 200 nm. In this embodiment, the film thickness A 50nm In-Ga-Zn-O non-single crystal film is deposited.

[0230] The oxide semiconductor film 403 for forming the channel formation region has the semiconductor characteristics described above. A suitable oxide material can be used.

[0231] Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. RF sputtering The method is mainly used when depositing insulating films, while the DC sputtering method is mainly used when depositing metal films. It is used for this purpose.

[0232] There are also multi-point sputtering systems that can set up multiple targets made of different materials. The apparatus can deposit multiple layers of different material films in the same chamber, or multiple types of materials in the same chamber. It is also possible to deposit films by simultaneously discharging electrical currents from similar materials.

[0233] Furthermore, a sputtering apparatus that uses the magnetron sputtering method, which has a magnetic mechanism inside the chamber. Alternatively, ECR sputtering uses plasma generated with microwaves instead of glow discharge. There are sputtering machines that use this method.

[0234] Furthermore, as a film deposition method using the sputtering method, the target material and sputtering gas components are deposited during film deposition. Reactive sputtering is a method that uses chemical reactions to form thin films of these compounds, and during film formation... There is also a bias sputtering method that applies voltage to the circuit board.

[0235] Next, as shown in Figure 21(C), a second photolithography process is performed to create a resist mass. A ripple is formed and the oxide semiconductor film 403 is etched. For example, a mixture of phosphoric acid, acetic acid and nitric acid Unwanted portions are removed by wet etching using a solution to form island-shaped oxide semiconductor films 4 Form 04 so that it overlaps with gate electrode 401. Note that etching here is done by wetting It is not limited to etching; dry etching may also be used.

[0236] Etching gases used in dry etching include chlorine-containing gases (chlorine-based gases, for example) Chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC) l4) etc.) are preferable.

[0237] Also, fluorine-containing gases (fluorinated gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (SF4)) 6) Nitrogen fluoride (NF3), trifluoromethane (CHF3), etc., hydrogen bromide (HBr ), oxygen (O2), and noble gases such as helium (He) and argon (Ar) are added to these gases. Added gases, etc., can be used.

[0238] As for dry etching methods, parallel plate type RIE (Reactive Ion Etching) Methods such as the ing method and ICP (Inductively Coupled Plasma: induction) A coupled plasma etching method can be used. The desired processing shape can be etched. To that end, etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side) Adjust the amount of power used, the electrode temperature on the substrate, etc., as appropriate.

[0239] The etching solution used for wet etching is a solution of phosphoric acid, acetic acid, and nitric acid, I TO07N (manufactured by Kanto Chemical Co., Ltd.) may also be used.

[0240] Furthermore, the etching solution after wet etching is washed away along with the etched material. The material is removed. The waste etching solution containing the removed material is purified, and the material contained in it is removed. It may be reused. Indium and other elements contained in the oxide semiconductor film can be extracted from the waste liquid after etching. By recovering and reusing materials, resources can be used effectively and costs can be reduced. .

[0241] To process the material into the desired shape, etching conditions (etching solution, etching) are adjusted according to the material. Adjust the cooking time, temperature, etc. as appropriate.

[0242] Next, as shown in Figure 22(A), under a reduced pressure atmosphere, an inert gas atmosphere such as nitrogen or a noble gas is used. Below, under an oxygen gas atmosphere, or in ultra-dry air (CRDS (cavity ring down laser) When measured using a spectroscopic dew point meter, the moisture content was 20 ppm (equivalent to a dew point of -55°C). ) Preferably in an air atmosphere of 1 ppm or less, preferably 10 ppb or less. By applying heat treatment to the oxide semiconductor film 404, an oxide semiconductor film 405 is formed. Specifically, under an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.), odor And, in a temperature range of 400°C to 700°C, preferably 450°C to 650°C, Island A crystalline oxide semiconductor film 404 is subjected to heat treatment, and then heated in an inert atmosphere at room temperature or above 100°C. Slow cooling is performed to a temperature below °C. The oxide semiconductor film 404 is then heat-treated in the above atmosphere. As a result, water, hydrogen, and hydroxyl groups contained within the oxide semiconductor film 404 are removed. Therefore, a thin film transient in which a channel formation region is formed using the oxide semiconductor film 405 The sta provides a high on-current.

[0243] Heat treatment can be performed using an electric furnace or GRTA (Gas Rap) which uses heated gas. id Thermal Anneal (Lamp) method or LRTA (Lamp) method using lamp light Using instantaneous heating methods such as the Rapid Thermal Annealing method Yes, it is possible. For example, when performing heat treatment using an electric furnace, the temperature rise characteristic must be 0.1°C / min or higher. The temperature reduction characteristics should be 20°C / min or less, and between 0.1°C / min and 15°C / min. preferable.

[0244] In addition, during the heat treatment, water is added to nitrogen or a noble gas such as helium, neon, or argon. It is preferable that it does not contain hydrogen, etc. Alternatively, nitrogen introduced into the heat treatment device, The purity of noble gases such as helium, neon, and argon is 6N (99.9999%) or higher. Preferably 7N (99.99999%) or higher (i.e., impurity concentration of 1 ppm or less, preferably) It is preferable that the concentration be 0.1 ppm or less.

[0245] After heat treatment, the island-shaped oxide semiconductor film 405 may be partially or entirely crystallized. stomach.

[0246] Furthermore, after the oxide semiconductor film 405 is subjected to heat treatment, the oxide semiconductor film is subjected to an oxygen atmosphere. By heat-treating 405, impurities such as moisture contained in the oxide semiconductor film 405 are removed. It can be removed. Then, by heat treatment in an oxygen atmosphere, the oxide semiconductor film 405 Resistance can be increased by creating an oxygen-rich environment. The temperature for heat treatment in an oxygen atmosphere is , a temperature at which metals with low melting points, such as Zn, which make up oxide semiconductors, are less likely to vaporize, for example, 1 The process is carried out at a temperature between 0°C and 350°C, preferably between 150°C and 250°C. The above oxygen atmosphere is used. It is preferable that the oxygen gas used in the heat treatment described below does not contain moisture, hydrogen, etc. Alternatively, the purity of the oxygen gas introduced into the heating apparatus should be 6N (99.9999%) or higher. More specifically, 7N (99.99999%) or higher (i.e., the impurity concentration in oxygen should be 1 ppm or less). Preferably, the concentration is 0.1 ppm or less.

[0247] Note that the cross-sectional view within the area of ​​dashed lines C1-C2 in Figure 22(A) and the cross-sectional view within the area of ​​dashed lines D1-D2 are shown separately. The plan view shown in Figure 24 is a cross-sectional view along the dashed line C1-C2, and the plan view is along the dashed line D1-D2. This corresponds to a cross-sectional view.

[0248] Next, as shown in Figure 22(B), a conductive film 4 made of a metallic material is placed on the oxide semiconductor film 405. 06 is formed by sputtering or vacuum deposition. The material for the conductive film 406 is aluminum. chromium, tantalum, titanium, manganese, magnesium, molybdenum, tungsten, An element selected from ttrium, beryllium, and yttrium, or one of the above elements or Alloys containing multiple components can be used. Furthermore, after the formation of the conductive film 406, heat treatment... When performing this process, it is preferable to give the conductive film 406 heat resistance to this heat treatment. Aluminum alone has problems such as poor heat resistance and susceptibility to corrosion, so conductive If heat treatment is performed after the formation of the film 406, the conductive film 40 is combined with a heat-resistant conductive material. Forms 6. Heat-resistant conductive materials to be combined with aluminum include titanium and tantalum. Elements selected from tungsten, molybdenum, chromium, neodymium, and scandium, or an alloy containing one or more of the above elements as components, or nitrogen containing the above elements as a component. Monsters and the like are preferred.

[0249] Next, as shown in Figure 22(C), a third photolithography process is performed to create a resist mass. A groove is formed, and unnecessary parts are removed by etching to form the source electrode 407a or drain electrode. The pole 407b and the second terminal 420 are formed. The etching method used in this process is wet Etching or dry etching is used. For example, an aluminum film is used as the conductive film 406. Alternatively, if using an aluminum alloy film, a solution of phosphoric acid, acetic acid, and nitric acid is used. Wet etching can be performed. Additionally, wet etching using ammonia hydrogen water is possible. This etches the conductive film 406 to the source electrode 407a or the drain electrode 407b. It may be formed.

[0250] In this etching process, a portion of the exposed area of ​​the oxide semiconductor film 405 is also etched. This can happen. In this case, the oxide semiconductor between the source electrode 407a or the drain electrode 407b may be The body membrane 409 is a region with a thin film thickness.

[0251] In this third photolithography step, the source electrode 407a or the drain electrode 40 The second terminal 420, made of the same material as 7b, is left at the terminal. Note that the second terminal 420 is saw Electrically connected to the source wiring (source wiring including source electrode 407a or drain electrode 407b) It continues.

[0252] Furthermore, a resist having regions of multiple (e.g., two) thicknesses formed by a multi-gradation mask. Using masks reduces the number of resist masks required, thus simplifying the process and lowering costs. This can be streamlined.

[0253] Next, remove the resist mask and, under reduced pressure, under an inert gas atmosphere such as nitrogen or a rare gas. , under an oxygen gas atmosphere, or in ultra-dry air (CRDS (cavity ring down laser component) The moisture content measured using a light-based dew point meter was 20 ppm (equivalent to a dew point of -55°C). In the following conditions, preferably in an air atmosphere of 1 ppm or less, preferably 10 ppb or less, The oxide semiconductor film 409 is subjected to heat treatment again, and the water contained in the oxide semiconductor film 409 is removed. Alternatively, the hydroxyl group may be removed. Source electrode 407a or drain electrode The heat treatment after forming 407b is necessary for the resistance of the source electrode 407a or the drain electrode 407b. Considering thermal properties, a heating treatment is performed before forming the source electrode 407a or drain electrode 407b. It is preferable to perform the procedure at a lower temperature than the theoretical limit. Specifically, a temperature between 350°C and 650°C is preferred. Alternatively, it is best to perform the process in a temperature range of 400°C to 600°C.

[0254] Note that the cross-sectional view within the area of ​​dashed lines C1-C2 in Figure 22(C) and the cross-sectional view within the area of ​​dashed lines D1-D2 are shown separately. The plan view shown in Figure 25 is a cross-sectional view along the dashed line C1-C2, and the plan view is along the dashed line D1-D2. This corresponds to a cross-sectional view.

[0255] Next, as shown in Figure 23(A), the gate insulating film 402, oxide semiconductor film 409, and source An oxide insulating film 411 is formed to cover electrode 407a or drain electrode 407b. The edge film 411 uses a silicon oxide nitride film formed by the PCVD method. Source electrode 407a or The exposed region of the oxide semiconductor film 409 provided between the drain electrodes 407b and the oxide insulating By providing the silicon oxide nitride film 411 in contact with the surface, oxygen is supplied and oxidation occurs. The region of the oxide semiconductor film 409 in contact with the insulating film 411 becomes highly resistive (carrier concentration decreases). Preferably 1 × 10 18 / cm 3 Acids having a channel-forming region with high resistance (less than) A ionized semiconductor film 412 can be formed.

[0256] Next, after forming the oxide insulating film 411, a heat treatment may be performed. The heat treatment may be performed in an atmospheric atmosphere. In an open atmosphere or under a nitrogen atmosphere, at a temperature of 350°C to 650°C, preferably 400°C or lower. It is preferable to perform this process in a temperature range of 600°C or less. When this heat treatment is performed, the oxide semiconductor film 412 The oxide insulating film 411 is heated in contact with the oxide semiconductor film 412. By increasing the resistance, the electrical characteristics of the transistor are improved and variations in electrical characteristics are reduced. This can be done. This heat treatment is not particularly limited as long as it is performed after the formation of the oxide insulating film 411. Other processes, such as heat treatment during resin film formation or heat treatment to reduce the resistance of transparent conductive films. By combining it with the rationale, it can be done without increasing the number of steps.

[0257] Thin-film transistor 413 can be fabricated using the above process.

[0258] Next, a fourth photolithography step is performed to form a resist mask, and an oxide insulating film 4 Contact holes are formed by etching 11 and the gate insulating film 402, and drain electricity Part of pole 407b, part of the first terminal 421, and part of the second terminal 420 are exposed. Next, after removing the resist mask, a transparent conductive film is deposited. The material for the transparent conductive film is indium oxide (In2O3) and indium tin oxide (In2O3-SnO2, ITO These materials (abbreviated as) are formed using sputtering or vacuum deposition methods. The etching process is carried out using a hydrochloric acid-based solution. However, etching ITO in particular generates residue. Because it is easy to etch, indium oxide zinc oxide (In2 O3-ZnO may also be used. In addition, a heat treatment is performed to reduce the resistance of the transparent conductive film. In this case, the oxide semiconductor film 412 is made highly resistive to improve the electrical characteristics of the transistor, This can be combined with heat treatment to reduce variations in electrical properties.

[0259] Next, a fifth photolithography step is performed to form a resist mask, and etching is performed. After removing the unnecessary parts, the pixel electrode 414 connected to the drain electrode 407b and the first end A transparent conductive film 415 connected to the child 421 and a transparent conductive film 4 connected to the second terminal 420 It forms 16.

[0260] The transparent conductive films 415 and 416 become electrodes or wiring used for connection to the FPC. The transparent conductive film 415 formed on terminal 421 functions as an input terminal for gate wiring. It serves as a terminal electrode for continued use. The transparent conductive film 416 formed on the second terminal 420 is source-distributed These are terminal electrodes for connection that function as input terminals for wires.

[0261] In this fifth photolithography step, the gate insulating film 402 and the oxide insulating film 41 With material 1 as the dielectric, a retained capacitance is formed by the capacitive wiring 408 and the pixel electrode 414.

[0262] Figure 23(C) shows a cross-sectional view after the resist mask has been removed. The cross-sectional views within the area of ​​dashed lines C1-C2 and D1-D2 are shown in Figure 26. This corresponds to the cross-sectional view along the dashed lines C1-C2 and D1-D2 in the plan view. .

[0263] Thus, through five photolithography processes, five photomasks are used to create the bottom The gate-type staggered thin-film transistor 413 can achieve its desired retention capacitance. Then, these are arranged in a matrix corresponding to individual pixels to form the pixel area. This can be used as one of the substrates for fabricating more active-matrix type display devices. For convenience, in this specification, such substrates are referred to as active matrix substrates.

[0264] When manufacturing an active-matrix liquid crystal display device, an active-matrix substrate is used. A liquid crystal layer is provided between the opposing substrate on which the opposing electrode is located, and the active matrix substrate and Secure it to the opposing substrate.

[0265] Furthermore, without providing capacitive wiring, the pixel electrodes are connected to the gate wiring of adjacent pixels and the oxide insulating film and gate The retention capacity may be formed by stacking the insulating films in between.

[0266] In an active-matrix liquid crystal display device, pixel electrodes are arranged in a matrix. By driving the pixels, a display pattern is formed on the screen. For details, see the selected pixels. A voltage is applied between the electrode and the counter electrode corresponding to the pixel electrode, Optical modulation is performed on the liquid crystal layer placed between the electrode and the counter electrode, and this optical modulation is used to create a display pattern. It is perceived by the observer as such.

[0267] When manufacturing a light-emitting device, a partition made of an organic resin film is provided between each organic light-emitting element. In some cases, the organic resin film is heat-treated. The principle is to increase the resistance of the oxide semiconductor film 412 to improve the electrical characteristics of the transistor, and This process can also serve as a heat treatment to reduce variations in gas properties.

[0268] By forming it with a thin-film transistor using an oxide semiconductor, manufacturing costs can be reduced. This can be achieved. In particular, by reducing impurities such as water, hydrogen, and OH through heat treatment, oxides can be produced. To improve the purity of semiconductor films, a thin-film transistor with good electrical characteristics and high reliability is used. It is possible to manufacture semiconductor display devices.

[0269] Since the semiconductor film in the channel formation region is a high-resistivity region, the electrical characteristics of the thin-film transistor are It stabilizes the system and prevents increases in off-current, etc. Therefore, it has good electrical characteristics and is reliable. This makes it possible to create a semiconductor display device with high-performance thin-film transistors.

[0270] This embodiment can be implemented in combination with the above embodiment.

[0271] (Embodiment 11) This embodiment describes the configuration of a liquid crystal display device according to one aspect of the present invention.

[0272] Figure 27 shows an example cross-sectional view of a liquid crystal display device according to one aspect of the present invention. The thin-film transistor 1401 has a gate electrode 1402 formed on an insulating surface, and a gate electrode A gate insulating film 1403 formed to cover pole 1402, and the gate insulating film 1403 between An oxide semiconductor film 1404 is formed sandwiched between the gate electrode 1402 and overlapping it, and an acid A pair of source or drain regions formed on the ionized semiconductor film 1404 A semiconductor film 1405 and a source electrode or drain formed on a pair of semiconductor films 1405 It has a pair of conductive films 1406 and an oxide insulating film 1407 that function as electrodes. The oxide insulating film 1407 is in contact with at least the oxide semiconductor film 1404, and the gate electrode 1 402, gate insulating film 1403, oxide semiconductor film 1404, and a pair of semiconductor films 140 It is formed to cover 5 and a pair of conductive films 1406.

[0273] An insulating film 1408 is formed on the oxide insulating film 1407. Oxide insulating film 1407, An opening is provided in a part of the insulating film 1408, and in this opening, the conductive film 1406 A pixel electrode 1410 is formed so as to be in contact with one of the pixels.

[0274] Furthermore, spacers 141 for controlling the cell gap of the liquid crystal element are placed on the insulating film 1408. 7 is formed. Spacer 1417 is shaped by etching the insulating film into the desired shape. Although it is possible to do so, by dispersing the filler on the insulating film 1408, cell gaps You can also control the program.

[0275] Furthermore, an alignment film 1411 is formed on the pixel electrode 1410. The alignment film 1411 is For example, it can be formed by applying a rubbing treatment to an insulating film. Also, the pixel electrode 14 Opposite to 10, a counter electrode 1413 is provided, and the pixels of the counter electrode 1413 An alignment film 1414 is formed on the side closer to the electrode 1410. And the pixel electrode 1410 And, in the region surrounded by the sealing material 1416 between the opposing electrodes 1413, there is liquid crystal 1415 A sealant is provided. The sealant 1416 may also contain a filler.

[0276] The pixel electrode 1410 and the counter electrode 1413 are made of, for example, indium tin oxide containing silicon oxide (I TSO), indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide ( Transparent conductive materials such as IZO (zinc oxide) and gallium-doped zinc oxide (GZO) can be used. In this embodiment, light is transmitted to the pixel electrode 1410 and the counter electrode 1413. An example of fabricating a transparent liquid crystal element using a conductive film is shown, but the present invention is not limited to this configuration. i. A liquid crystal display device according to one aspect of the present invention may be semi-transmissive or reflective.

[0277] Color filters and shielding films (black matrices) to prevent discrepancies. These may be provided in the liquid crystal display device shown in Figure 27.

[0278] In this embodiment, the liquid crystal display device is TN (Twisted Nematics). ) type was shown, but VA (Vertical Alignment) type, OCB (opti cally compensated Birefringence) type, IPS(In The thin film of the present invention can also be used in other liquid crystal display devices such as the Plane Switching type. A transistor can be used.

[0279] A liquid crystal display device according to one aspect of the present invention is highly reliable.

[0280] This embodiment can be freely combined with other embodiments.

[0281] (Embodiment 12) In this embodiment, a light-emitting device is used in which a thin-film transistor according to one aspect of the present invention is used as a pixel. The configuration will be described. In this embodiment, the transistor for driving the light-emitting element is The cross-sectional structure of pixels in the n-type case will be explained using Figure 28. This section will explain the case where the first electrode is the cathode and the second electrode is the anode, but the first electrode is the anode The second electrode may also be the cathode.

[0282] Figure 28(A) shows that transistor 6031 is n-type and the light emitted from light-emitting element 6033 A cross-sectional view of the pixel is shown when the signal is extracted from the first electrode 6034 side. Transistor 6031 It is covered with an insulating film 6037, and on the insulating film 6037 there is a partition wall 6038 having an opening. It is formed. The first electrode 6034 is partially exposed at the opening of the partition wall 6038. In the opening, the first electrode 6034, the electroluminescent layer 6035, and the second electrode 6036 are in sequence. It is stacked on top of each other.

[0283] The first electrode 6034 is formed of a light-transmitting material or film thickness, and has a small work function. It can be formed from metals, alloys, electrically conductive compounds, and mixtures thereof. Specifically, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, and Sr. The group, alloys containing these (Mg:Ag, Al:Li, Mg:In, etc.), and their chemical compounds. In addition to composites (calcium fluoride, calcium nitride), rare earth metals such as Yb and Er are also used. This can be done. Also, when an electron injection layer is provided, other conductive layers such as aluminum can be used. This is also possible. The first electrode 6034 is then coated with a film thickness (preferably 5) that allows light to pass through. It is formed with a thickness of approximately nm to 30 nm. Furthermore, the conductive layer has a thickness sufficient to transmit light. A transparent conductive layer is formed using a translucent oxide conductive material so as to be in contact with the top or bottom of the material. Furthermore, the sheet resistance of the first electrode 6034 may be suppressed. Adding oxides (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), and gallium Using only the conductive layer made of other translucent oxide conductive materials such as added zinc oxide (GZO) It is also possible to add ITO and silicon dioxide to the first electrode 6034. Indium oxide containing tin oxide (hereinafter referred to as ITSO) and silicon oxide, further 2 A mixture containing approximately 20% zinc oxide (ZnO) may also be used. Translucent oxide conductive material When used, it is desirable to provide an electron injection layer in the electroluminescent layer 6035.

[0284] Furthermore, the second electrode 6036 is formed of a material and film thickness that reflects or shields light, and It is formed from a material suitable for use as an anode. For example, titanium nitride, zirconium nitride, One or more of the following materials: titanium, tungsten, nickel, platinum, chromium, silver, aluminum, etc. In addition to single-layer films consisting of the above, lamination of films mainly composed of titanium nitride and aluminum, titanium nitride A three-layer structure consisting of a film, a film mainly composed of aluminum, and a titanium nitride film is used as the second electrode 6036. It can be used for this purpose.

[0285] The electroluminescent layer 6035 is composed of one or more layers. In that case, these layers are considered to be a hole injection layer, a hole transport layer, and an emissive layer from the viewpoint of carrier transport characteristics. They can be classified into electron transport layers, electron injection layers, etc. The electroluminescent layer 6035 is in addition to being an emissive layer. If it has one of the following: a hole injection layer, a hole transport layer, an electron transport layer, or an electron injection layer, then Starting from electrode 6034, the layers are arranged in the following order: electron injection layer, electron transport layer, light emission layer, hole transport layer, and hole injection layer. The layers are stacked on top of each other. Note that the boundaries between each layer do not necessarily need to be clear, and the layers that make up each other are still distinct. In some cases, the materials are partially mixed, and the interface is unclear. Each layer contains organic materials, and It is possible to use mechanical materials. As organic materials, polymers, medium molecular weights, and low molecular weights are available. Any of the sub-system materials can be used. Note that medium-molecular-weight materials refer to materials with a variety of structural units. The number of returns (degree of polymerization) corresponds to a low polymer of about 2 to 20. Hole injection layer and hole transport layer The distinction between them is not always strict, and these are particularly important in terms of hole transportability (hole mobility). They are the same in the sense that they are characteristics. For convenience, the hole injection layer is the layer on the side in contact with the anode, and The layer in contact with the hole injection layer is called the hole transport layer to distinguish it. Similarly, the layer in contact with the cathode is called the electron injection layer, and the layer in contact with the electron injection layer is called the electron transport layer. It is called a luminescent electron transport layer. The luminescent layer may also function as an electron transport layer and is therefore also called a luminescent electron transport layer.

[0286] In the case of the pixel shown in Figure 28(A), the light emitted from the light-emitting element 6033 is indicated by the white arrow. As shown, it can be extracted from the first electrode 6034 side.

[0287] Next, in Figure 28(B), the transistor 6041 is of type n, and is emitted from the light-emitting element 6043. This shows a cross-sectional view of the pixel when light is extracted from the second electrode 6046 side. Transistor 60 41 is covered with an insulating film 6047, and a partition wall 604 having an opening is located on the insulating film 6047. 8 is formed. The first electrode 6044 is partially exposed at the opening of the partition wall 6048. In the opening, the first electrode 6044, the electroluminescent layer 6045, and the second electrode 6046 They are stacked in order.

[0288] The first electrode 6044 is formed of a material and film thickness that reflects or shields light, and also works Formation using metals, alloys, electrically conductive compounds, and mixtures thereof with low function This is possible. Specifically, alkali metals such as Li and Cs, and alkali metals such as Mg, Ca, and Sr. Potassium earth metals, alloys containing them (Mg:Ag, Al:Li, Mg:In, etc.), and In addition to these compounds (calcium fluoride, calcium nitride), rare earth metals such as Yb and Er are also included. It can be used. Also, when an electron injection layer is provided, other conductive layers such as aluminum can be used. It is also possible to use it.

[0289] Furthermore, the second electrode 6046 is formed of a light-transmitting material or film thickness, and as an anode Formed from a material suitable for use. For example, indium tin oxide (ITO), zinc oxide ( Examples include zinc oxide (ZnO), indium zinc oxide (IZO), and zinc oxide with added gallium (GZO). Other translucent oxide conductive materials can be used for the second electrode 6046. Indium tin oxide containing TO and silicon oxide (hereinafter referred to as ITSO), and silicon oxide containing The indium oxide is then mixed with 2-20% zinc oxide (ZnO) to create the second... It may also be used for electrode 6046. In addition to the above-mentioned translucent oxide conductive materials, for example, titanium nitride can also be used. Zirconium nitride, titanium, tungsten, nickel, platinum, chromium, silver, aluminum In addition to single-layer films consisting of one or more of the above, films mainly composed of titanium nitride and aluminum. Lamination, a three-layer structure of titanium nitride film, aluminum-based film, and titanium nitride film, etc. The second electrode 6046 can also be used. However, materials other than translucent oxide conductive materials may be used. When used, the second electric field should be made with a film thickness (preferably about 5 nm to 30 nm) that allows light to pass through. Forms pole 6046.

[0290] The electroluminescent layer 6045 can be formed in the same manner as the electroluminescent layer 6035 in Figure 28(A). ru.

[0291] In the case of the pixel shown in Figure 28(B), the light emitted from the light-emitting element 6043 is indicated by the white arrow. As shown, it can be extracted from the second electrode 6046 side.

[0292] Next, in Figure 28(C), the transistor 6051 is of type n, and is emitted from the light-emitting element 6053. Cross-sectional view of a pixel when light is extracted from the first electrode 6054 side and the second electrode 6056 side. This shows that transistor 6051 is covered with an insulating film 6057, and on the insulating film 6057 A partition wall 6058 having an opening is formed. The electrode 6054 is partially exposed, and in the opening, the first electrode 6054 and the electroluminescent layer 60 55, and the second electrode 6056 are stacked in order.

[0293] The first electrode 6054 can be formed in the same manner as the first electrode 6034 in Figure 28(A). Furthermore, the second electrode 6056 is formed in the same manner as the second electrode 6046 in Figure 28(B). This can be done. The electroluminescent layer 6055 is formed in the same manner as the electroluminescent layer 6035 in Figure 28(A). It is possible.

[0294] In the case of the pixel shown in Figure 28(C), the light emitted from the light-emitting element 6053 is indicated by the white arrow. As shown, it can be extracted from the first electrode 6054 side and the second electrode 6056 side. .

[0295] This embodiment can be implemented in appropriate combination with other embodiments.

[0296] (Embodiment 13) This embodiment describes the configuration of a liquid crystal display device according to one aspect of the present invention.

[0297] Figure 29 is an example of a perspective view showing the structure of the liquid crystal display device of the present invention. The display device includes a liquid crystal panel 1601 in which liquid crystal elements are formed between a pair of substrates, and a first diffuser plate 1 602, prism sheet 1603, second diffuser plate 1604, light guide plate 1605, It comprises a ray plate 1606, a light source 1607, and a circuit board 1608.

[0298] A liquid crystal panel 1601, a first diffuser plate 1602, a prism sheet 1603, and a second diffuser The diffuser plate 1604, the light guide plate 1605, and the reflector plate 1606 are stacked in that order. Light source 1 607 is provided at the end of the light guide plate 1605, and the light source diffused inside the light guide plate 1605 Light from 1607 passes through the first diffuser 1602, the prism sheet 1603, and the second diffuser. The liquid crystal panel 1601 is uniformly illuminated by 1604.

[0299] In this embodiment, a first diffuser plate 1602 and a second diffuser plate 1604 are used. However, the number of diffusers is not limited to this; it can be one or three or more. The light guide plate only needs to be placed between the light guide plate 1605 and the liquid crystal panel 1601. Therefore, Even if the diffuser plate is provided only on the side closer to the liquid crystal panel 1601 than the zoom sheet 1603, That's good, and the diffuser is provided only on the side closer to the light guide plate 1605 than the prism sheet 1603. It's okay to be there.

[0300] Furthermore, the prism sheet 1603 is not limited to having a sawtooth cross-section as shown in Figure 29, and the light guide It is sufficient if the board 1605 has a shape that can concentrate the light from it towards the liquid crystal panel 1601.

[0301] The circuit board 1608 includes circuits for generating various signals that are input to the liquid crystal panel 1601, and The circuit board 16 is equipped with circuits for processing these signals. And in Figure 29, the circuit board 16 08 and LCD panel 1601 are FPC (Flexible Printed Circular Printer) It is connected via uit)1609. Note that the above circuit is COG (Chip On It may also be connected to the liquid crystal panel 1601 using the Glass method, or one of the above circuits Even if the part is connected to the FPC1609 using the COF (Chip On Film) method good.

[0302] In Figure 29, a control system circuit for controlling the drive of the light source 1607 is provided on the circuit board 1608. In this example, the control system circuit and the light source 1607 are connected via the FPC 1610. This indicates that the above control system circuit may also be formed on the liquid crystal panel 1601. In this case, the LCD panel 1601 and the light source 1607 are connected by an FPC or the like. ru.

[0303] Figure 29 shows an edge-lit type light source 1607 positioned at the edge of the liquid crystal panel 1601. Although the source is illustrated, in the liquid crystal display device of the present invention, the light source 1607 is located directly below the liquid crystal panel 1601. It may also be a direct-hit type positioned directly beneath the surface.

[0304] This embodiment can be implemented in appropriate combination with the above embodiment. [Examples]

[0305] By using a semiconductor display device according to one aspect of the present invention, a highly reliable and low-power electronic display device can be obtained. We can provide equipment, especially portable power supplies, which are difficult to obtain at a constant power supply. In the case of a sub-device, by adding a semiconductor display device according to one aspect of the present invention to its components... This also offers advantages such as longer continuous usage time.

[0306] Furthermore, the semiconductor display device of the present invention allows for suppressing the temperature of the heat treatment in the manufacturing process. Therefore, it is made from flexible synthetic resins such as plastics, which have lower heat resistance than glass. To fabricate thin-film transistors with excellent characteristics and high reliability, even on substrates. This is possible. Therefore, by using the manufacturing method according to one aspect of the present invention, high reliability can be achieved. It is possible to provide a semiconductor display device that is low power consumption, lightweight, and flexible. Polyester, such as polyethylene terephthalate (PET), is used as a plastic substrate. Polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate Bonate (PC), polyetheretherketone (PEEK), polysulfone (PSF) Polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate Polyurethane (PBT), polyimide, acrylonitrile butadiene styrene resin, polyvinyl chloride Examples include polypropylene, polyvinyl acetate, and acrylic resin.

[0307] A semiconductor display device according to one aspect of the present invention is a display device, a notebook personal computer, Image playback device equipped with a recording medium (typically DVD: Digital Versatile) (A device having a display capable of playing recording media such as eDiscs and displaying the images thereof.) It can be used for the following purposes. In addition, a semiconductor display device according to one aspect of the present invention can be used. Examples of electronic devices that can be used include mobile phones, portable game consoles, personal digital assistants, e-books, and video cameras. Cameras, digital still cameras, goggle-type displays (head-mounted displays) Navigation systems, sound playback devices (car audio, digital audio players) (e.g., photocopiers, fax machines, printers, multifunction printers, ATMs) Examples include ATMs and vending machines. Specific examples of these electronic devices are shown in Figure 30. .

[0308] Figure 30(A) is an e-book, which has a housing 7001, a display unit 7002, etc. One of the present inventions The semiconductor display device according to this embodiment can be used in the display unit 7002. By using a semiconductor display device according to one aspect of the present invention, a highly reliable and low-power electronic display device can be obtained. Books can be provided. Also, by using a flexible substrate, the display unit 700 Since the semiconductor display device used in 2 can be made flexible, it has high reliability and low By minimizing power consumption, we can provide flexible, lightweight, and user-friendly e-books.

[0309] Figure 30(B) shows a display device, which includes a housing 7011, a display unit 7012, a support base 7013, etc. A semiconductor display device according to one aspect of the present invention can be used in the display unit 7012. By using a semiconductor display device according to one aspect of the present invention in the display unit 7012, high reliability is achieved. A low-power display device can be provided. The display device includes a personal computer. This includes all information display devices, such as those for viewers, TV broadcast reception, and advertising.

[0310] Figure 30(C) shows a display device, which includes a housing 7021, a display unit 7022, etc. One of the present inventions The semiconductor display device according to this embodiment can be used in the display unit 7022. By using a semiconductor display device according to one aspect of the present invention, a highly reliable and low-power display can be obtained. The device can be provided. Furthermore, by using a flexible substrate, the display unit 702 The semiconductor display device used in 2, and other signal processing circuits, can be made flexible. Therefore, it is possible to realize a highly reliable, low-power, flexible, and lightweight display device. This is possible. Therefore, as shown in Figure 30(C), the display device can be used by fixing it to a cloth or the like. This will significantly broaden the range of applications for semiconductor display devices.

[0311] Figure 30(D) shows a portable game console, comprising a casing 7031, casing 7032, display unit 7033, Display unit 7034, microphone 7035, speaker 7036, operation key 7037, stand It has illustration 7038, etc. A semiconductor display device according to one aspect of the present invention has a display unit 7033, It can be used in the display unit 7034. One aspect of the present invention can be used in the display unit 7033 and the display unit 7034. By using semiconductor display devices related to this, a highly reliable, low-power portable game console can be created. It can be provided. Note that the portable game console shown in Figure 30(D) has two display units 7 It has 033 and a display unit 7034, but the number of display units that a portable game console has is this Not limited to this.

[0312] Figure 30(E) is a mobile phone, comprising a housing 7041, a display unit 7042, an audio input unit 7043, It has an audio output unit 7044, an operation key 7045, a light receiving unit 7046, etc. By converting the light received into an electrical signal, external images can be captured. A semiconductor display device according to one aspect of the invention can be used in the display unit 7042. By using a semiconductor display device according to one aspect of the present invention in 042, a highly reliable and low-power consumption device can be obtained. We can provide you with a mobile phone.

[0313] This embodiment can be implemented in appropriate combination with the above embodiment. [Explanation of symbols]

[0314] 10. Pulse output circuit 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 21 Input terminals 22 Input terminals 23 Input terminals 24 input terminals 25 Input terminals 26 output terminals 27 Output terminals 31 transistors 32 transistors 33 transistors 34 transistors 35 transistors 36 transistors 37 transistors 38 transistors 39 Transistors 40 transistors 41 Transistors 42 transistors 43 transistors 51 Power line 52 Power line 53 Power line 100 pixel section 101 Scan line drive circuit 102 Signal line drive circuit 103 Decoder 104 Area 105 each pixel 106 NOR circuit 201 Thin-film transistors 202 circuit boards 203 Terminal 204 Gate Insulator 205 oxide semiconductor film 206 Source Electrode 207 Drain electrode 208 Oxide Insulating Film 209 Conductive film 210 insulating film 211 Thin-film transistors 212 circuit boards 213 Terminal 214 Gate insulating film 215 Oxide semiconductor film 216 Source electrodes 217 Drain electrode 218 Oxide Insulating Film 219 Conductive film 220 insulating film 221 Thin-film transistors 222 circuit boards 223 Terminal 224 Gate insulating film 225 oxide semiconductor film 226 Source Electrode 227 Drain electrode 228 Oxide insulating film 229 Conductive film 230 insulating film 231 Channel Protective Film 300 pixel section 301 Scan line drive circuit 302 Signal Line Drive Circuit 303 Decoder 304 Shift Register 305 Sampling Circuit 306 Decoder 310 pixels 311 Switching Transistors 312 Drive Transistors 313 Light-emitting element 314 holding capacity 320 pixels 321 Transistors 322 liquid crystal elements 323 holding capacity 400 circuit boards 401 Gate Shutdown 402 Gate Insulator 403 Oxide semiconductor film 404 oxide semiconductor film 405 oxide semiconductor film 406 Conductive film 408 Capacitance wiring 409 Oxide semiconductor film 411 Oxide Insulating Film 412 Oxide semiconductor film 413 Thin-film transistors 414 pixel electrodes 415 Transparent conductive film 416 Transparent conductive film 420 terminals 421 terminals 700 pixel section 701 Signal Line Drive Circuit 702 Scan Line Drive Circuit 702 Line drive circuit 703 pixels 704 Transistors 705 display elements 706 Holding capacity 707 Signal Line 708 scan lines 710 Pixel Electrodes 711 Counter electrode 712 microcapsules 713 Drain electrode 714 Resin 901 Transistor 902 Transistors 903 Transistor 904 Transistor 911 Transistor 912 transistors 1401 Thin-film transistor 1402 Shutdown 1403 Gate Insulator 1404 Oxide semiconductor film 1405 Semiconductor film 1406 Conductive film 1407 Oxide insulating film 1408 Insulating film 1410 Pixel Electrodes 1411 Alignment film 1413 Counter electrode 1414 Alignment film 1415 LCD 1416 Sealant 1417 Spacer 1601 LCD panel 1602 Diffuser 1603 Prism Sheet 1604 Diffuser 1605 Light guide plate 1606 Reflector 1607 Light source 1608 Circuit board 1609 FPC 1610 FPC 407a Source electrode 407b Drain electrode 5601 Shift Register 5602 Sampling Circuit 5602 Switching Circuit 5603 n-channel transistor 5603 Transistor 5604 Wiring 5605 Wiring 6031 transistor 6033 Light-emitting element 6034 Electrode 6035 Electroluminescent Layer 6036 Electrode 6037 Insulating film 6038 Bulkhead 6041 transistor 6043 Light-emitting element 6044 Electrode 6045 Electroluminescent layer 6046 Electrode 6047 Insulating film 6048 Bulkhead 6051 Transistor 6053 Light-emitting element 6054 Electrode 6055 Electroluminescent Layer 6056 Electrode 6057 Insulating film 6058 Bulkhead 7001 enclosure 7002 Display section 7011 enclosure 7012 Display section 7013 Support stand 7021 enclosure 7022 Display section 7031 enclosure 7032 enclosure 7033 Display section 7034 Display section 7035 Microphone 7036 Speaker 7037 Operation Keys 7038 Stylus 7041 enclosure 7042 Display section 7043 Voice Input Section 7044 Audio output section 7045 Operation Keys 7046 Light receiving section

Claims

1. It comprises a pixel section and a scanning line driving circuit that inputs a signal to the pixel section, The scan line driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The aforementioned pixel section has a seventh transistor, The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor each have a channel formation region in the oxide semiconductor layer. The oxide semiconductor layer has an In-Ga-Zn-O based oxide semiconductor, The oxide semiconductor layer has crystals in at least a portion of it. The source and drain of the first transistor are always in electrical contact with the source and drain of the second transistor. The source and drain of the first transistor are always in electrical contact with the source and drain of the third transistor. One of the sources and drains of the first transistor is always in electrical contact with the first wiring. The source and drain of the first transistor are always in electrical contact with the second wiring. The source and drain of the sixth transistor are always in electrical contact with the source and drain of the fifth transistor. The source and drain of the sixth transistor are always in electrical contact with the source and drain of the fourth transistor. One of the sources and drains of the sixth transistor is electrically connected to the gate of the first transistor. The source and drain of the sixth transistor are always in electrical contact with the third wiring. The source and drain of the fifth transistor are always in electrical contact with the source and drain of the fourth transistor. The source and drain of the fifth transistor are always in electrical contact with the source and drain of the third transistor. The source and drain of the fifth transistor are always in electrical contact with the source and drain of the second transistor. The gate of the fifth transistor is always in electrical contact with the gate of the third transistor. The gate of the fourth transistor is always in electrical contact with the gate of the second transistor. When the first transistor is ON, the potential of the second wiring is input to the first wiring via the channel formation region of the first transistor. A display device in which the gate potential of the first transistor can be controlled independently of the gate potential of the sixth transistor.

2. It comprises a pixel section and a scanning line driving circuit that inputs a signal to the pixel section, The scan line driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The aforementioned pixel section has a seventh transistor, The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor each have a channel formation region in the oxide semiconductor layer. The oxide semiconductor layer has an In-O-based oxide semiconductor, The oxide semiconductor layer has crystals in at least a portion of it. The source and drain of the first transistor are always in electrical contact with the source and drain of the second transistor. The source and drain of the first transistor are always in electrical contact with the source and drain of the third transistor. One of the sources and drains of the first transistor is always in electrical contact with the first wiring. The source and drain of the first transistor are always in electrical contact with the second wiring. The source and drain of the sixth transistor are always in electrical contact with the source and drain of the fifth transistor. The source and drain of the sixth transistor are always in electrical contact with the source and drain of the fourth transistor. One of the sources and drains of the sixth transistor is electrically connected to the gate of the first transistor. The source and drain of the sixth transistor are always in electrical contact with the third wiring. The source and drain of the fifth transistor are always in electrical contact with the source and drain of the fourth transistor. The source and drain of the fifth transistor are always in electrical contact with the source and drain of the third transistor. The source and drain of the fifth transistor are always in electrical contact with the source and drain of the second transistor. The gate of the fifth transistor is always in electrical contact with the gate of the third transistor. The gate of the fourth transistor is always in electrical contact with the gate of the second transistor. When the first transistor is ON, the potential of the second wiring is input to the first wiring via the channel formation region of the first transistor. A display device in which the gate potential of the first transistor can be controlled independently of the gate potential of the sixth transistor.

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