Data compression device and data compression / decompression system

Abstract

This provides a data compression device that can expand dictionary size using existing resources. [Solution] According to the embodiment, the data compression device comprises N data compression circuits, a dictionary buffer linking control circuit, and a longest match selection circuit. The dictionary buffer linking control circuit controls the switching between a first mode in which the N data compression circuits operate independently and a second mode in which the N data compression circuits cooperate. In the second mode, the longest match selection circuit selects the dictionary compression result with the longest match length from among the N. The data compression circuits have dictionary buffers. In the first mode, the dictionary buffer linking control circuit inputs different uncompressed data to the N data compression circuits, and in the second mode, it links the N dictionary buffers by saving the oldest dictionary data from the i-th dictionary buffer to the (i+1)-th dictionary buffer, and inputs the same uncompressed data to the N data compression circuits.

Description

Technical Field

[0004] , , , , , , , , ,

[0001] Embodiments of the present invention relate to a data compression device and a data compression / decompression system.

Background Art

[0002] For example, in a data compressor having a dictionary compression circuit of the LZ77 method, data input in the past is buffered in a dictionary buffer, and data that matches the input data is searched for from the past data on the dictionary buffer. When the matching data is stored in the dictionary buffer, compression is performed by replacing it with a match distance that is the address of the dictionary buffer and a match length that indicates the length of the matching data, and outputting it as a dictionary compression result. One way to improve the compression efficiency of a dictionary compression circuit is to increase the dictionary size (a parameter indicating whether it is possible to refer to the past several bytes for matching). However, increasing the dictionary size increases the circuit scale of the dictionary buffer and the dictionary search logic for searching for a match from the dictionary buffer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment of the present invention provides a data compression device and a data compression / decompression system that can expand the dictionary size by diverting existing resources.

Means for Solving the Problems

[0005] According to one embodiment, the data compression device comprises N (where N is an integer greater than or equal to 2) data compression circuits, a dictionary buffer linking control circuit, and a longest match selection circuit. The data compression circuit has a first dictionary compression circuit. The dictionary buffer linking control circuit controls the switching between a first mode in which the N data compression circuits operate independently and a second mode in which the N data compression circuits cooperate. In the second mode, the longest match selection circuit selects the dictionary compression result with the longest match length from among the dictionary compression results of the N first dictionary compression circuits, each of which has a different match length. The first dictionary compression circuit has a dictionary buffer for buffering the uncompressed data to be compressed as dictionary data. In the first mode, the dictionary buffer linking control circuit inputs different uncompressed data to the N data compression circuits. In the second mode, the dictionary buffer concatenation control circuit concatenates N dictionary buffers by saving the oldest dictionary data stored in the i-th dictionary buffer to the (i+1)th dictionary buffer, thereby inputting the same uncompressed data to N data compression circuits. [Brief explanation of the drawing]

[0006] [Figure 1] A diagram showing an example configuration of the memory system of the first embodiment. [Figure 2] This figure shows a comparative example to illustrate how the circuit size of the dictionary compression unit increases with the enlargement of the dictionary size to improve the compression efficiency of the dictionary compression unit. [Figure 3] A diagram showing an example configuration of a data compression device in a memory system according to the first embodiment. [Figure 4] This figure shows how the compressed IP appears in the memory system of the first embodiment depending on whether or not the dictionary buffer of the data compression device is concatenated, and the configuration of the dictionary buffer when the dictionary buffer is concatenated. [Figure 5] A diagram showing an example configuration of a data compression device in a memory system according to the second embodiment. [Figure 6] This figure shows the configuration of the dictionary buffer in the memory system of the second embodiment when dictionary buffer concatenation is enabled for the data compression device. [Figure 7] A diagram showing an example configuration of a data compression device and a data decompression device in a memory system of the third embodiment. [Figure 8] This figure shows the configuration of the dictionary buffer in the memory system of the third embodiment when dictionary buffer concatenation is enabled for the data compression device. [Figure 9] A diagram showing an example configuration of a data compression device and a data decompression device in a memory system of the fourth embodiment. [Figure 10] This figure shows the configuration of the dictionary buffer in the memory system of the fourth embodiment when dictionary buffer concatenation is enabled for the data compression device. [Figure 11] A diagram showing an example configuration of a data compression device in a memory system according to the fifth embodiment. [Figure 12] This figure shows the configuration of the dictionary buffer in the memory system of the fourth embodiment when dictionary buffer concatenation is enabled for the data compression device. [Modes for carrying out the invention]

[0007] The embodiments will be described below with reference to the drawings.

[0008] (First Embodiment) First, the first embodiment will be described.

[0009] Figure 1 shows an example configuration of the memory system 1 according to the first embodiment. Figure 1 also shows an example configuration of an information processing system that includes the memory system 1 and a host 2 to which the memory system 1 is connected as storage. The host 2 is an information processing device such as a server or a personal computer.

[0010] Memory system 1 has a memory controller 11 and a flash memory 12. Here, an example where the memory system 1 is realized as an SSD (solid state drive) is shown. The memory system 1 can be realized not only as an SSD but also as various types of data storage devices. That is, the memory system 1 can be equipped with various types of storage media, not limited to the flash memory 12.

[0011] The memory controller 11 is a device that controls the overall operation of the memory system 1. The memory controller 11 has a processor 111, a host interface circuit 112, a memory interface circuit 113, a data compression device 114, a data decompression device 115, and an ECC (error check and correct) circuit 116.

[0012] The processor 111 realizes various processes to be executed by the memory controller 11 by executing a program called firmware or the like. Various processes to be executed by the memory controller 11 include a write process of writing data to the flash memory 12 in response to a write command from the host 2, a read process of reading data stored in the flash memory 12 in response to a read command from the host 2, and the like. Here, an example where various processes to be executed by the memory controller 11 are realized by the processor 111 executing firmware is shown, but it may also be realized by dedicated hardware built into the memory controller 11, such as an electric circuit.

[0013] The host interface circuit 112 controls communication compliant with a predetermined communication standard with the host 2. The memory interface circuit 113 controls writing of data to the flash memory 12 and reading of data from the flash memory 12.

[0014] The data compression device 114 compresses the write data requested to be written to the flash memory 12 by a write command to generate compressed data. The data decompression device 115 decompresses the compressed data corresponding to the read data requested to be read from the flash memory 12 by a read command to obtain the read data. In other words, the memory system 1 of the first embodiment has a data compression and decompression system that compresses and decompresses data.

[0015] The ECC circuit 116 performs error correction processing on the compressed data generated by the data compression device 114. Specifically, upon receiving a write command, the ECC circuit 116 generates an error correction code to detect and correct any errors that may occur in the compressed data to be written to the flash memory 12 in the future. The processor 111 is configured to write the error correction code to the flash memory 12 via the memory interface circuit 113. In other words, the processor 111 is configured to write data based on the compressed data generated by the data compression device 114 to the flash memory 12 via the memory interface circuit 113. Furthermore, when the processor 111 receives a read command from the host 2, it reads data based on the received read command from the flash memory 12 via the memory interface circuit 113. The ECC circuit 116 performs error correction processing on the read data. That is, the ECC circuit 116 uses the error correction code to check whether there are any errors in the compressed data read from the flash memory 12, and corrects any errors detected. The read data, after error correction processing has been performed, is input as compressed data to the data decompression device 115 by the processor 111, and the data decompression device 115 decompresses the input compressed data. The processor 111 sends the decompressed data to the host 2 in response to a read command from the host 2. In other words, the processor 111 is configured to decompress data based on the data read from the flash memory 12 in response to a read command from the host 2, and to send the decompressed data to the host 2.

[0016] FIG. 2 is a diagram showing a comparative example for explaining that as the dictionary size is increased to improve the compression efficiency of the dictionary compression unit, the circuit scale of the dictionary compression unit increases.

[0017] FIG. 2(A) shows a configuration example of a compression IP (Intellectual Property) 80 having a dictionary compression unit 81 with a dictionary size of 2 KiB.

[0018] The dictionary compression unit 81 has a dictionary buffer 811 for buffering past input data, and a dictionary search Logic 812 for searching for data that matches the current input data from the dictionary buffer 811. The dictionary buffer 811 has a capacity capable of buffering the past 2 KiB of input data. Also, the dictionary search Logic 812 has an ability to search for data that matches the current input data from the past 2 KiB of input data buffered in the dictionary buffer 811.

[0019] The compression IP 80 further has an entropy encoding unit 82 for entropy encoding the dictionary compression result output from the dictionary compression unit 81.

[0020] On the other hand, FIG. 2(B) shows a configuration example of a compression IP 90 having a dictionary compression unit 91 with a dictionary size of 4 KiB. The dictionary buffer 911 of the compression IP 90 has a capacity capable of buffering the past 4 KiB of input data. Also, the dictionary search Logic 912 has an ability to search for data that matches the current input data from the past 4 KiB of input data buffered in the dictionary buffer 811.

[0021] The compression IP 90 also further has an entropy encoding unit 92 for entropy encoding the dictionary compression result output from the dictionary compression unit 91.

[0022] As is clear from the comparison between the dictionary buffer 811 and dictionary search logic 812 of the dictionary compression unit 81 in the compressed IP 80 in Figure 2(A) and the dictionary buffer 911 and dictionary search logic 912 of the dictionary compression unit 91 in the compressed IP 90 in Figure 2(B), increasing the dictionary size of the dictionary compression unit from, for example, 2KiB to 4KiB in order to improve the compression efficiency of the dictionary compression unit leads to an increase in the circuit size of the dictionary compression unit.

[0023] In contrast, the data compression device 114 in the memory system 1 of the first embodiment expands the dictionary size by reusing existing resources without increasing the circuit size of the dictionary compression unit. This point will be described in detail below.

[0024] Figure 3 shows an example configuration of the data compression device 114 in the memory system 1 of the first embodiment.

[0025] The data compression device 114 of the first embodiment includes two compression IPs (Core0, Core1) 21 internally. In the following description of the compression IPs 21, when it is necessary to distinguish between them, a sub-number (-1, -2) will be used in the reference numeral; otherwise, the sub-number will be omitted. Sub-numbers may also be used similarly for other components that exist in multiples.

[0026] The compressed IP21 entropy encodes the dictionary compression result output by the LZ77 dictionary compression unit using the entropy encoding unit 32. The entropy encoding method is, for example, Huffman coding.

[0027] The dictionary compression unit 31 is, for example, a dictionary compression hardware with a dictionary size of 2 KiB and an input throughput of 4 Bytes / cycle, and includes a 2 KiB shift register 41, a byte-to-byte comparison unit 42, a match length calculation unit 43, and a longest match determination unit 44. The shift register 41 is a dictionary buffer where data previously input to the dictionary compression unit 31 is buffered (stored) as dictionary data, such as the dictionary buffer 811 in Figure 2(A) and the dictionary buffer 911 in Figure 2(B). The shift register 41 is then used when the byte-to-byte comparison unit 42 searches for data that matches the input data when data is subsequently input to the dictionary compression unit 31.

[0028] In each cycle, when 4 bytes of uncompressed data are input to the dictionary compression unit 31, the dictionary compression unit 31 writes the input uncompressed data to the shift register 41. The uncompressed data written to the shift register 41 is treated as dictionary data. The byte-to-all comparison unit 42 compares the uncompressed data stored in the shift register 41 (up to 2 KiB) with the input 4 bytes of uncompressed data. Next, the match length calculation unit 43 calculates the match length for the total match distance, which is the distance from one uncompressed data in the input uncompressed data to another uncompressed data in the uncompressed data held in the shift register 41, based on the comparison result of the byte-to-all comparison unit 42. Finally, the longest match determination unit 44 selects the longest match length from among the match lengths calculated for the total match distance. The shift register 41 is shifted 4 bytes per cycle in the direction of evicting previously input data, and the input uncompressed data is written to the 4 bytes that become available.

[0029] The dictionary buffer linking control unit 22 controls the connection relationship between the shift register 41 of the dictionary compression unit 31 of compressed IP (Core0) 21-1 and the shift register 41 of the dictionary compression unit 31 of compressed IP (Core1) 21-2, based on the Compression Level input to the data compression device 114, and also controls the input of uncompressed data to compressed IP (Core1) 21-2. The Compression Level is a value that indicates which of a predetermined number of stages the compression efficiency requested by the host 2 to the memory controller 11 is at.

[0030] If the Compression Level is below a predetermined threshold, the dictionary buffer concatenation control unit 22 controls compressed IP(Core0)21-1 and compressed IP(Core1)21-2 to operate independently. That is, the shift register 41 of the dictionary compression unit 31 of compressed IP(Core0)21-1 and the shift register of the dictionary compression unit 31 of compressed IP(Core1)21-2 are not connected, and separate uncompressed data is input to compressed IP(Core0)21-1 and compressed IP(Core1)21-2, respectively.

[0031] As a result, the compressed IP (Core0) 21-1 and compressed IP (Core1) 21-2 can operate in parallel, and the data compression device 114 provides two compressed IPs with 4 bytes / cycle and a dictionary size of 2 KiB in the first mode, resulting in an overall input throughput of 8 bytes / cycle for the data compression device 114.

[0032] On the other hand, if the Compression Level is above a predetermined threshold, the dictionary buffer concatenation control unit 22 concatenates the shift register 41 of compressed IP (Core0) 21-1 and the shift register 41 of compressed IP (Core1) 21-2 to operate as a single dictionary buffer. The dictionary buffer concatenation control unit 22 kept the input to the shift register 41 of the dictionary compression unit 31 of compressed IP (Core1) 21-2 as the input uncompressed data until the shift register 41 of compressed IP (Core0) 21-1 and the shift register 41 of compressed IP (Core1) 21-2 were concatenated. If the Compression Level is above a predetermined threshold, the dictionary buffer concatenation control unit 22 concatenates the shift register 41 of compressed IP (Core0) 21-1 with the shift register 41 of compressed IP (Core1) 21-2, and switches the input to the shift register 41 of the dictionary compression unit 31 of compressed IP (Core1) 21-2 to the oldest dictionary data evicted in the shift register 41 of the dictionary compression unit 31 of compressed IP (Core0) 21-1. Specifically, it controls switch 51.

[0033] Furthermore, the dictionary buffer concatenation control unit 22 switches the input to the byte-total comparison unit 42 of the dictionary compression unit 31 of compressed IP (Core1) 21-2 from uncompressed data, which is the input to compressed IP (Core1) 21-2, to uncompressed data, which is the input to compressed IP (Core0) 21-1. Specifically, it controls switch 52.

[0034] The match length of the match output by the longest match determination unit 44 of the dictionary compression unit 31 of compressed IP (Core0) 21-1 and the match length of the match output by the longest match determination unit 44 of the dictionary compression unit 31 of compressed IP (Core1) 21-2 are compared by the longest match selection unit 23. The longest match selection unit 23 selects the match with the longer match length, and the switch 53 controlled by the dictionary buffer linking control unit 22 controls it, which is then input to the entropy encoding unit 32 of compressed IP (Core0) 21-1. In this case, the switch 54 controlled by the dictionary buffer linking control unit 22 switches the output of the longest match determination unit 44 of compressed IP (Core1) 21-2 to be supplied to the read-and-discard control unit 33, and the entropy encoding unit 32 of compressed IP (Core1) 21-2 does not operate. In other words, the dictionary buffer concatenation control unit 22 controls the switch 54 to switch the output of the longest match determination unit 44 of the compressed IP (Core1) 21-2 to be supplied to the discard control unit 33, thereby controlling the entropy encoding unit 32 of the compressed IP (Core1) 21-2 to not operate. That is, the dictionary buffer concatenation control unit 22 deactivates the entropy encoding unit 32 of the compressed IP (Core1) 21-2, which is in an operational state due to the supply of the output of the longest match determination unit 44 of the compressed IP (Core1) 21-2, by blocking the input to the entropy encoding unit 32 of the compressed IP (Core1) 21-2.

[0035] As a result, the shift register 41 of compressed IP (Core0) 21-1 and the shift register 41 of compressed IP (Core1) 21-2 are linked to form a 4KiB dictionary. Consequently, the byte-to-total comparison unit 42, the match length calculation unit 43, and the longest match determination unit 44 are also linked to obtain the match search result for the 4KiB dictionary.

[0036] As a result, the data compression device 114 provides one compression IP with a second mode of 4 bytes / cycle and a dictionary size of 4 KiB, and the overall input throughput of the data compression device 114 becomes 4 bytes / cycle. The input throughput when the dictionary buffer is concatenated is halved compared to when the dictionary buffer is not concatenated, but in return, the dictionary size is doubled, so an improvement in the compression ratio can be expected. Furthermore, since this method can be implemented by reusing almost all existing components, the increase in circuit size due to the expansion of the dictionary size can also be suppressed.

[0037] Figure 4 shows how the compressed IP21 appears in the memory system 1 of the first embodiment depending on whether or not the dictionary buffer is linked, and the configuration of the dictionary buffer when the dictionary buffer is linked.

[0038] Figure 4(A) shows how the compressed IP21 appears with and without dictionary buffer concatenation, which is determined by the Compression Level.

[0039] If the Compression Level is below a predetermined threshold, dictionary buffer concatenation is disabled (OFF). In this case, the two compression IP21s operate independently with a 4Byte / cycle and a dictionary size of 2KiB. In this case, the total input throughput of the data compression device 114 is 8Byte / cycle.

[0040] On the other hand, if the Compression Level is above a predetermined threshold, dictionary buffer concatenation is enabled (ON). In this case, the two compression IP21s cooperate with a 4Byte / cycle and a dictionary size of 4KiB. In this case, the total input throughput of the data compression device 114 is 4Byte / cycle.

[0041] Figure 4(B) shows an example of a dictionary buffer configuration when dictionary buffer linking is enabled (ON). When dictionary buffer linking is enabled (ON), uncompressed data is first input to the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core0) 21-1. The uncompressed data is shifted by 4 bytes per cycle, and once it is evicted from the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core0) 21-1, it is input to the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core1) 21-2.

[0042] As described above, the data compression device 114 in the memory system 1 of the first embodiment can expand the dictionary size by reusing an existing resource, the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core1) 21-2.

[0043] (Second Embodiment) Next, a second embodiment will be described.

[0044] The second embodiment, like the first embodiment, uses a memory system implemented as an SSD as an example. The same reference numerals are used for components identical to those in the first embodiment, and their descriptions are omitted.

[0045] Figure 5 shows an example configuration of the data compression device 114 in the memory system 1 of the second embodiment.

[0046] In the data compression device 114 of the second embodiment, the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core0) 21-1 and the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core1) 21-2 are linked. Furthermore, when the dictionary buffers are linked, the delay buffer 34 of the compressed IP (Core1) 21-2, in which the entropy encoding unit 32 does not operate, is reused (used) as the dictionary buffer. As a result, the second embodiment can increase the dictionary size compared to the first embodiment.

[0047] The entropy coding unit 32 uses dynamic Huffman coding (a Huffman coding scheme that generates a code table based on the frequency of occurrence of input symbols) as the entropy coding method, and each of the compressed IP (Core0) 21-1 and compressed IP (Core0) 21-2 has a delay buffer 34, for example, composed of 10KiB-SRAM, for the purpose of buffering input symbols during the cycle period of code table generation.

[0048] The symbols of the dictionary compression result are buffered in the delay buffer 34. The entropy coding unit 32 counts the frequency of occurrence of each symbol contained in a block of a predetermined size, constructs a Huffman tree based on the obtained frequency of occurrence, and generates an encoding table. The dictionary compression unit 31 of the compressed IP (Core0) 21-1 has the same configuration as the dictionary compression unit 31 of the first embodiment.

[0049] The dictionary compression unit 31 of the compressed IP (Core0) 21-2 has a hash-based dictionary search unit 45 in addition to the configuration of the dictionary compression unit 31 of the first embodiment. The operation of the dictionary buffer concatenation control unit 22 in the second embodiment is as follows.

[0050] If the Compression Level is below a predetermined threshold, the dictionary buffer concatenation control unit 22 controls the compressed IP(Core0)21-1 and compressed IP(Core1)21-2 to operate independently. That is, the shift register 41 of the dictionary compression unit 31 of compressed IP(Core0)21-1 and the shift register of the dictionary compression unit 31 of compressed IP(Core1)21-2 are not connected, and separate uncompressed data is input to compressed IP(Core0)21-1 and compressed IP(Core1)21-2. In addition, the hash-based dictionary search unit 45 does not operate.

[0051] The inputs to the delay buffer 34 of compressed IP (Core0) 21-1 and the delay buffer 34 of compressed IP (Core0) 21-2 become the outputs of the longest match determination units 44 of compressed IP (Core0) 21-1 and compressed IP (Core1) 21-2, respectively.

[0052] As a result, similar to the first embodiment, the compressed IP (Core0) 21-1 and compressed IP (Core0) 21-2 can operate in parallel, and the data compression device 114 provides two compressed IPs with 4 bytes / cycle and a dictionary size of 2 KiB in first mode, resulting in an overall input throughput of 8 bytes / cycle for the data compression device 114.

[0053] On the other hand, if the Compression Level is above a predetermined threshold, the dictionary buffer concatenation control unit 22 concatenates the shift register 41 of compressed IP (Core0) 21-1, the shift register 41 of compressed IP (Core1) 21-2, and the delay buffer 34 of compressed IP (Core1) 21-2 to operate as a single dictionary buffer. The dictionary buffer concatenation control unit 22 switches the input to the shift register 41 of the dictionary compression unit 31 of compressed IP (Core1) 21-2 from uncompressed data input to the oldest dictionary data evicted in the shift register 41 of the dictionary compression unit 31 of compressed IP (Core0) 21-1. Specifically, it controls switch 51.

[0054] Furthermore, the dictionary buffer concatenation control unit 22 switches the input to the byte-total comparison unit 42 of the dictionary compression section of compressed IP (Core1) 21-2 from uncompressed data, which is the input to compressed IP (Core1) 21-2, to uncompressed data, which is the input to compressed IP (Core0) 21-1. Specifically, it controls switch 52.

[0055] Furthermore, the dictionary buffer linking control unit 22 switches the input to the delay buffer 34 of the compressed IP (Core1) 21-2 from the output result of the longest match determination unit 44 of the compressed IP (Core1) 21-2 to the oldest dictionary data evicted in the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core1) 21-2. Specifically, it controls switches 54 and 55.

[0056] The write policy for the delayed buffer 34 of the compressed IP (Core1) 21-2 is a ring buffer. The hash-based dictionary lookup unit 45 performs hash-based dictionary lookup processing on the dictionary data written to the delayed buffer 34.

[0057] The longest match selection unit 23 compares the output of the longest match determination unit 44 of compressed IP (Core0) 21-1, the output of the longest match determination unit 44 of compressed IP (Core1) 21-2, and the output of the match length calculation unit 455 of the hash-based dictionary search unit 45, and outputs the match with the longest match length to the delay buffer 34 and entropy coding unit 32 of compressed IP (Core0) 21-1. In addition, the uncompressed data that is input to compressed IP (Core0) 21-1 is input to the hash-based dictionary search unit 45 of compressed IP (Core1) 21-2.

[0058] The hash-based dictionary lookup unit 45 includes a hash calculation unit 451-1, a hash calculation unit 451-2, a hash registration unit 452, a hash lookup unit 453, a hash table unit 454, and a match length calculation unit 455. The hash table unit 454 has an array with number of elements = H, and each entry in the array stores a 14-bit (≒ceil(1024×10)) delayed buffer address and D 1-bit flags indicating whether the delayed buffer address is valid or invalid. For example, H=512 and D=4. When a dictionary buffer concatenation operation is performed and a write operation is made to the delayed buffer 34 of the compressed IP (Core1) 21-2, the hash calculation unit 451-1 calculates a hash value based on at least a portion of the data written to the delayed buffer 34. The hash value is calculated, for example, based on the first 3 bytes of the data written to the delayed buffer 34. The hash registration unit 452 determines the array index (0 to H-1) of the hash table unit based on the hash value and writes the delayed buffer address of the data written to the delayed buffer 34 to the entry corresponding to the determined index. The D delayed buffer addresses included in the array entry are updated according to the FIFO policy. When uncompressed data is input to the hash-based dictionary lookup unit 45, the hash calculation unit 451-2 calculates a hash value based on at least a portion of the uncompressed data input. The method for calculating the hash value is the same as the method for calculating the hash value used for the hash registration unit 452. The hash lookup unit 453 determines the array index (0 to H-1) of the hash table unit 454 based on the hash value and reads the entry corresponding to the determined index from the array. Of the D delayed buffer addresses included in the entry read from the array, at least a portion of the D' (D'≦D) that are indicated as valid by a flag are selected and dictionary data is read from the delayed buffer 34. The selection criteria are, for example, in order of smallest match distance (= in order of latest timing of push to FIFO), but are not limited to this method.In addition to the delayed buffer address and the enable / disable flag, a portion of the hash value may be stored as an entry in the array, and selection may be made by comparing this value with the hash value input to the hash search unit 453. The read dictionary data and the uncompressed data input to the hash-based dictionary search unit 455 are compared by the match length calculation unit 455, and the match length is calculated.

[0059] The output of the longest match determination unit 44 of compressed IP (Core0) 21-1, the output of the longest match determination unit 44 of compressed IP (Core1) 21-2, and the output of the match length calculation unit 455 of the hash-based dictionary search unit 45 are compared by the longest match selection unit 23, and the match with the longer match length is selected and input to the entropy coding unit 32 of compressed IP (Core0) 21-1. The entropy coding unit 32 of compressed IP (Core1) 21-2 does not perform any operations.

[0060] As a result, the shift register 41 of compressed IP (Core0) 21-1, the shift register 41 of compressed IP (Core1) 21-2, and the delay buffer 34 of compressed IP (Core1) 21-2 are linked together to form a 14KiB dictionary, and the match search results for the 14KiB dictionary are obtained. Consequently, the data compression device 114 provides one compressed IP 21 with a second mode of 4 bytes / cycle and a dictionary size of 14KiB, and the overall input throughput of the data compression device 114 becomes 4 bytes / cycle. Compared to the first embodiment, the input throughput is the same, the dictionary size is increased by 10KiB, and an improvement in the compression ratio can be expected.

[0061] Figure 6 shows the configuration of the dictionary buffer in the memory system of the second embodiment when dictionary buffer concatenation of the data compression device is enabled.

[0062] When dictionary buffer concatenation is enabled, uncompressed data is first input to the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core0) 21-1. The uncompressed data is shifted 4 bytes per cycle, and once it is evicted from the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core0) 21-1, it is input to the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core1) 21-2. Furthermore, once the uncompressed data is evicted from the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core1) 21-2, it is input to the delay buffer 34 of the compressed IP (Core1) 21-2.

[0063] As described above, the data compression device 114 in the memory system 1 of the second embodiment can expand the dictionary size by reusing existing resources such as the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core1) 21-2 and the delay buffer 34 of the compressed IP (Core1) 21-2.

[0064] (Third embodiment) Next, a third embodiment will be described.

[0065] The second embodiment, like the first and second embodiments, uses a memory system implemented as an SSD as an example. The same reference numerals are used for components identical to those in the first and second embodiments, and their descriptions are omitted.

[0066] Figure 7 shows an example configuration of the data compression device 114 and data decompression device 115 in the memory system 1 of the third embodiment.

[0067] In the data compression device 114 of the third embodiment, a data decompression device 115 is applied as an existing resource to be repurposed in order to expand the dictionary size. The data decompression device 115 has two decompression IPs 61 with a decompression throughput of 4 bytes / cycle. More specifically, the data decompression device 115 has a decompression IP (Core0) 61-1 and a decompression IP (Core1) 61-2.

[0068] The extended IP61 includes an entropy decoding unit 71, a dictionary extension unit 72, and a dictionary buffer 73 of 32KiB-SRAM. The extended IP(Core1)61-2 also includes a hash-based dictionary search unit 74 similar to the hash-based dictionary search unit 45 of the second embodiment.

[0069] In the third embodiment, the dictionary buffer 73 for dictionary decompression included in the decompression IP (Core1) 61-2 is reused as the dictionary buffer for the compression IP 21, thereby increasing the dictionary size during compression.

[0070] If the Compression Level is below a predetermined threshold, the dictionary buffer linking control unit 22 controls the compressed IP(Core0)21-1 and compressed IP(Core1)21-2 of the data compression device 114 and the decompressed IP(Core0)61-1 and decompressed IP(Core1)61-2 of the data decompression device 115 to operate independently. That is, the shift register 41 of the dictionary compression unit 31 of the compressed IP(Core0)21-1 of the data compression device 114 and the shift register 41 of the dictionary compression unit 31 of the compressed IP(Core1)21-2 of the data compression device 114 are not connected, and separate uncompressed data is input to the compressed IP(Core0)21-1 and compressed IP(Core1)21-2, respectively, while separate compressed data is input to the decompressed IP(Core0)61-1 and decompressed IP(Core1)61-2 of the data decompression device 115. Furthermore, the hash-based dictionary search unit 74 of the data decompression IP (Core1) 61-2 of the data decompression device 115 does not operate.

[0071] As a result, the compression IP (Core0) 21-1 and compression IP (Core1) 21-2 of the data compression device 114 can operate in parallel, and the decompression IP (Core0) 61-1 and decompression IP (Core1) 61-2 of the data decompression device 115 can also operate in parallel. In its first mode, the data compression device 114 provides two compression IPs 21 with a rate of 4 bytes / cycle and a dictionary size of 2 KiB, resulting in an overall input throughput of 8 bytes / cycle for the data compression device 114. The data decompression device 115 provides two decompression IPs 61 with a rate of 4 bytes / cycle and a dictionary size of 32 KiB, resulting in an overall output throughput of 8 bytes / cycle for the data decompression device 115.

[0072] On the other hand, if the Compression Level is above a predetermined threshold, the dictionary buffer linking control unit 22 links the shift register 41 of the compressed IP (Core0) 21-1 of the data compression device 114, the shift register 41 of the compressed IP (Core1) 21-2, and the dictionary buffer 73 of the decompression IP (Core1) 61-2 of the data decompression device 115, and controls them to operate as a single dictionary buffer. The dictionary buffer linking control unit 22 switches the input to the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core0) 21-1 of the data compression device 114 from uncompressed data input to the oldest dictionary data evicted in the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core0) 21-1 of the data compression device 114. Specifically, it controls switch 51.

[0073] Furthermore, the dictionary buffer linking control unit 22 switches the input to the byte-total comparison unit 42 of the dictionary compression unit 31 of the compressed IP (Core1) 21-2 of the data compression device 114 from uncompressed data input, which is the input to the compressed IP (Core1) 21-2 of the data compression device 114, to uncompressed data, which is the input to the compressed IP (Core0) 21-1 of the data compression device 114. Specifically, it controls switch 52.

[0074] Furthermore, the dictionary buffer linking control unit 22 switches the input to the dictionary buffer 73 of the decompression IP (Core1) 61-2 of the data decompression device 115 from the output result of the dictionary decompression unit 72 of the decompression IP (Core1) 61-2 of the data decompression device 115 to the oldest dictionary data evicted in the shift register 41 of the dictionary compression unit 31 of the compression IP (Core1) 21-2 of the data compression device 114. Specifically, it controls switch 56.

[0075] In this case, the entropy decoding unit 71 and the dictionary decompression unit 72 of the decompression IP (Core1) 61-2 of the data decompression device 115 do not operate.

[0076] The write policy for the dictionary buffer 73 of the decompression IP (Core1) 61-2 of the data decompression device 115 is a ring buffer. The hash-based dictionary lookup unit 74 performs hash-based dictionary lookup processing on the dictionary data written to the dictionary buffer 73 of the decompression IP (Core1) 61-2 of the data decompression device 115.

[0077] The longest match selection unit 23 compares the output of the longest match determination unit 44 of the dictionary compression unit 31 of the compressed IP (Core0) 21-1 of the data compression device 114, the output of the longest match determination unit 44 of the dictionary compression unit 31 of the compressed IP (Core1) 21-2 of the data compression device 114, and the output of the match length calculation unit 745 of the hash-based dictionary search unit 74 of the decompressed IP (Core1) 61-2 of the data decompression device 115, and outputs the match with the longest match length to the delay buffer 34 and entropy coding unit of the compressed IP (Core0) 21-1 of the data compression device 114. In addition, the uncompressed data that is input to the compressed IP (Core0) 21-1 is input to the hash-based dictionary search unit 74 of the data decompression device 115.

[0078] As a result, the shift register 41 of the compressed IP (Core0) 21-1 of the data compression device 114, the shift register 41 of the compressed IP (Core1) 21-2 of the data compression device 114, and the dictionary buffer 73 of the decompression IP (Core1) 61-2 of the data decompression device 115 are linked together to form a 36KiB dictionary, and the match search results for the 36KiB dictionary are obtained.

[0079] As a result, the data compression device 114 provides one compressed IP21 with a second mode of 4 bytes / cycle and a dictionary size of 36 KiB, resulting in an overall input throughput of 4 bytes / cycle for the data compression device 114. The overall output throughput of the data decompression device 115 is 8 bytes / cycle when the dictionary buffer is not connected in the data compression device 114, and 4 bytes / cycle when the dictionary buffer is connected. Compared to the first embodiment, the input throughput of the data compression device 114 is the same, the output throughput of the data decompression device 115 is halved, the dictionary size is increased by 32 KiB, and an improvement in the compression ratio can be expected.

[0080] Figure 8 shows the configuration of the dictionary buffer in the memory system 1 of the third embodiment when dictionary buffer concatenation is enabled for the data compression device 114.

[0081] When dictionary buffer concatenation is enabled, uncompressed data is first input to the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core0) 21-1 of the data compression device 114. The uncompressed data is shifted 4 bytes per cycle, and once it is evicted from the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core0) 21-1 of the data compression device 114, it is input to the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core1) 21-2 of the data compression device 114. Furthermore, once the uncompressed data is evicted from the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core1) 21-2 of the data compression device 114, it is input to the dictionary buffer 73 of the decompression IP (Core1) 61-2 of the data decompression device 115.

[0082] As described above, the data compression device 114 in the memory system 1 of the third embodiment can expand the dictionary size by reusing existing resources, namely the shift register 41 of the dictionary compression unit 31 of the compression IP (Core 1) 21-2 of the data compression device 114 and the dictionary buffer 73 of the decompression IP (Core 1) 61-2 of the data decompression device 115.

[0083] (Fourth Embodiment) Next, a fourth embodiment will be described.

[0084] The fourth embodiment, like the first to third embodiments, uses a memory system implemented as an SSD as an example. The same reference numerals are used for components identical to those in the first to third embodiments, and their descriptions are omitted.

[0085] Figure 9 shows an example configuration of the data compression device 114 and data decompression device 115 in the memory system 1 of the fourth embodiment.

[0086] As shown in Figure 9, in the fourth embodiment, the data compression device 114 has one compression IP (Core0) 21. The data decompression device 115 also has one decompression IP (Core0) 61. The decompression IP (Core0) 61 has a hash-based dictionary lookup unit 74.

[0087] In the fourth embodiment, the dictionary buffer linking control unit 22 of the compressed IP (Core0) 21 of the data compression device 114, in second mode, links the shift register 41 of the compressed IP (Core0) 21 of the data compression device 114 and the dictionary buffer 73 of the decompressed IP (Core0) 61 of the data decompression device 115 to form a 34 KiB dictionary buffer.

[0088] Figure 10 shows the configuration of the dictionary buffer in the memory system 1 of the fourth embodiment when dictionary buffer concatenation is enabled for the data compression device 114.

[0089] When dictionary buffer concatenation is enabled, uncompressed data is first input to the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core0) 21 of the data compression device 114. The uncompressed data is shifted 4 bytes per cycle, and once it is evicted from the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core0) 21 of the data compression device 114, it is input to the dictionary buffer 73 of the decompression IP (Core0) 61 of the data decompression device 115.

[0090] As described above, even if the data compression device 114 has only one compression IP (Core0) 21 and the data decompression device 115 has only one decompression IP (Core0) 61, the data compression device 114 in the memory system 1 of the fourth embodiment can expand the dictionary size by reusing an existing resource, the dictionary buffer 73 of the decompression IP (Core0) 61 of the data decompression device 115.

[0091] (Fifth embodiment) Next, a fifth embodiment will be described.

[0092] The fifth embodiment, like the first to fourth embodiments, uses a memory system implemented as an SSD as an example. The same reference numerals are used for components identical to those in the first to fourth embodiments, and their descriptions are omitted.

[0093] Figure 11 shows an example configuration of the data compression device 114 in the memory system 1 of the fifth embodiment.

[0094] As shown in Figure 11, in the fifth embodiment, the data compression device 114 has three compression IPs (Core0, Core1, Core2) 21 (-1 to 3). The entropy coding unit 32 of each compression IP 21 is a dynamic Huffman code, similar to the second embodiment, and uses a delay buffer 34 composed of 10 KiB-SRAM. In the fifth embodiment, the dictionary buffer concatenation control unit 22 of the data compression device 114, in second mode, concatenates the shift register 41 of compression IP (Core0) 21-1, the shift register 41 of compression IP (Core1) 21-2, the shift register 41 of compression IP (Core2) 21-3, the delay buffer 34 of compression IP (Core1) 21-2, and the delay buffer 34 of compression IP (Core2) 21-3 to form a 26 KiB dictionary buffer.

[0095] If the Compression Level is above a predetermined threshold, the dictionary buffer concatenation control unit 22 switches the input to the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core1) 21-2 from the uncompressed data input to the oldest dictionary data evicted in the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core0) 21-1. Specifically, it controls the switch 51 of the compressed IP (Core1) 21-2.

[0096] Furthermore, the dictionary buffer linking control unit 22 switches the input to the byte comparison unit 42 of the dictionary compression unit 31 of the compressed IP (Core1) 21-2 from uncompressed data, which is the input to the compressed IP (Core1) 21-2, to uncompressed data, which is the input to the compressed IP (Core0) 21-1. Specifically, it controls the switch 52 of the compressed IP (Core1) 21-2.

[0097] Furthermore, the dictionary buffer linking control unit 22 switches the input to the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core2) 21-3 from uncompressed data input to the oldest dictionary data evicted by the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core1) 21-2. Specifically, it controls the switch 51 of the compressed IP (Core2) 21-3.

[0098] Furthermore, the dictionary buffer linking control unit 22 switches the input to the byte-total comparison unit 42 of the dictionary compression unit 31 of the compressed IP (Core2) 21-3 from the uncompressed data input which is the input to the compressed IP (Core2) 21-3 to the uncompressed data input which is the input to the compressed IP (Core0) 21-1. Specifically, it controls the switch 52 of the compressed IP (Core2) 21-3.

[0099] Furthermore, the dictionary buffer concatenation control unit 22 switches the input to the delay buffer 34 of the compressed IP (Core1) 21-2 from the output of the longest match determination unit 44 of the compressed IP (Core1) 21-2 to the oldest dictionary data evicted by the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core2) 21-3. Specifically, it controls switches 54 and 55 of the compressed IP (Core1) 21-2.

[0100] Furthermore, the dictionary buffer concatenation control unit 22 switches the input to the delay buffer 34 of the compressed IP (Core2) 21-3 from the output of the longest match determination unit 44 of the compressed IP (Core2) 21-3 to the oldest dictionary data that is overwritten in the delay buffer 34 of the compressed IP (Core1) 21-2.

[0101] The longest match selection unit 23 compares the output of the longest match determination unit 44 of compressed IP (Core0) 21-1 with the output of the longest match determination unit 44 of compressed IP (Core1) 21-2 with the output of the longest match determination unit 44 of compressed IP (Core2) 21-3 with the output of the match length calculation unit 455 of the hash-based dictionary search unit 45 of compressed IP (Core1) 21-2 with the output of the match length calculation unit 455 of the hash-based dictionary search unit 45 of compressed IP (Core2) 21-3, and outputs the match with the longest match length to the delay buffer 34 of compressed IP (Core0) 21-1 and the entropy coding unit 32 of compressed IP (Core0) 21-1. Furthermore, the uncompressed data, which is the input to the compressed IP (Core0) 21-1, is input to the hash-based dictionary search unit 45 of the compressed IP (Core1) 21-2 and the hash-based dictionary search unit 45 of the compressed IP (Core2) 21-3.

[0102] As a result, the shift register 41 of compressed IP (Core0) 21-1, the shift register 41 of compressed IP (Core1) 21-2, the shift register 41 of compressed IP (Core2) 21-3, and the delay buffer 34 of compressed IP (Core1) 21-2 are linked together to form a 26KiB dictionary, and the match search results for the 26KiB dictionary are obtained.

[0103] As a result, the data compression device provides one compressed IP21 with a second mode of 4 bytes / cycle and a dictionary size of 26 KiB, and the input throughput of the entire data compression device 114 becomes 4 bytes / cycle. Compared to the first embodiment, the input throughput of the entire data compression device 114 remains the same, but the dictionary size increases by 24 KiB, and an improvement in the compression ratio can be expected.

[0104] Figure 12 shows the configuration of the dictionary buffer in the memory system 1 of the fifth embodiment when dictionary buffer concatenation is enabled for the data compression device 114.

[0105] When dictionary buffer concatenation is enabled, uncompressed data is first input to the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core0) 21-1. The uncompressed data is shifted 4 bytes per cycle, and once it is evicted from the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core0) 21-1, it is input to the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core1) 21-2. Similarly, once the uncompressed data is evicted from the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core1) 21-2, it is input to the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core2) 21-3.

[0106] Furthermore, once the uncompressed data is evicted from the shift register 41 of the dictionary compression unit 31 of the compressed IP (Core2) 21-3, it is input to the delay buffer 34 of the compressed IP (Core1) 21-2. Additionally, once the uncompressed data is evicted from the delay buffer 34 of the compressed IP (Core1) 21-2, it is input to the delay buffer 34 of the compressed IP (Core2) 21-3.

[0107] As described above, the data compression device 114 in the memory system 1 of the fifth embodiment can further expand the dictionary size by reusing existing resources such as the shift register 41 of the dictionary compression unit 31 of the compression IP (Core1) 21-2, the shift register 41 of the dictionary compression unit 31 of the compression IP (Core2) 21-3, the delay buffer 34 of the compression IP (Core1) 21-2, and the delay buffer 34 of the compression IP (Core2) 21-3.

[0108] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0109] 1...Memory system, 2...Host, 11...Controller, 12...Flash memory, 21...Compressed IP, 22...Dictionary buffer concatenation control unit, 23...Longest match selection unit, 31...Dictionary compression unit, 32...Entropy encoding unit, 33...Read-and-discard control unit, 34...Delay buffer, 41...Shift register, 42...Byte total comparison unit, 43...Match length calculation unit, 44...Longest match determination unit, 45...Hash-based dictionary search unit, 51-56...Switch, 71...Entropy decoding unit 72...Dictionary decompression unit, 73...Dictionary buffer, 74...Hash-based dictionary search unit, 111...Processor, 112...Host interface circuit, 113...Memory interface circuit, 114...Data compression device, 115...Data decompression device, 116...ECC circuit, 451...Hash calculation unit, 452...Hash registration unit, 453...Hash search unit, 454...Hash table unit, 455...Match length calculation unit, 456...Match length calculation unit, 745...Match length calculation unit.

Claims

1. N (where N is an integer greater than or equal to 2) data compression circuits, each having a first dictionary compression circuit, A dictionary buffer linking control circuit controls the switching between a first mode in which the N data compression circuits operate independently and a second mode in which the N data compression circuits cooperate. In the second mode described above, the longest match selection circuit selects the dictionary compression result with the longest match length from among the dictionary compression results of the N first dictionary compression circuits, each of the N data compression circuits, It is equipped with, The first dictionary compression circuit has a dictionary buffer for buffering the uncompressed data to be compressed as dictionary data, The aforementioned dictionary buffer concatenation control circuit is In the first mode, N different uncompressed data are input to the N data compression circuits. In the second mode, When registering the dictionary data in the i-th dictionary buffer (where i is an integer between 1 and N-1), the oldest dictionary data stored in the i-th dictionary buffer is saved to the (i+1)-th dictionary buffer, thereby concatenating the N dictionary buffers. The same uncompressed data is input to the N data compression circuits. Data compression device.

2. The data compression circuit has an entropy coding circuit, The aforementioned dictionary buffer concatenation control circuit is In the first mode, the dictionary compression results of the N first dictionary compression circuits are input to the N entropy coding circuits, each of the N data compression circuits, In the case of the second mode described above, The dictionary compression result selected by the longest match selection circuit is input to the entropy coding circuit of the first data compression circuit. The (N-1) entropy coding circuits of the second to the Nth data compression circuits are deactivated. The data compression device according to claim 1.

3. The data compression device according to claim 2, wherein each of the N first dictionary compression circuits compares the uncompressed data previously input and stored in the dictionary buffer with the uncompressed data input thereafter to calculate the dictionary compression result.

4. The data compression device according to claim 3, wherein the dictionary compression result includes a match length, which is the length of data that matches between the subsequently input uncompressed data and the previously input uncompressed data stored in the dictionary buffer, and a match distance, which is the distance from the matching data in the subsequently input uncompressed data to the matching data in the previously input uncompressed data stored in the dictionary buffer.

5. The data compression apparatus according to claim 2, wherein the dictionary buffer linking control circuit blocks the input of the dictionary compression result, thereby deactivating (N-1) of the entropy coding circuits of the second to Nth data compression circuits.

6. The entropy coding circuit has a delay buffer for buffering the symbols of the dictionary compression result of the first dictionary compression circuit, The second to Nth data compression circuits each have a second dictionary compression circuit that performs dictionary compression using the delay buffer of the entropy coding circuit. In the second mode, the dictionary buffer concatenation control circuit is configured as follows: The oldest dictionary data in the dictionary buffer of the Nth data compression circuit is shifted to the delay buffer of the second data compression circuit. The oldest dictionary data in the delay buffer of the j-th data compression circuit (where j is an integer greater than or equal to 2 and less than or equal to N-1) is shifted to the delay buffer of the (j+1)-th data compression circuit. The dictionary buffer and the delay buffer are further concatenated in this manner. The dictionary compression results of the second dictionary compression circuit of the data compression circuits from the second to the Nth are input to the longest match selection circuit. The data compression device according to claim 2.

7. The data compression device according to claim 6, wherein the second dictionary compression circuit performs hash-based dictionary compression.

8. A data compression device according to claim 1, A data decompression device having N data decompression circuits, It is equipped with, The aforementioned data decompression circuit is A dictionary decompression buffer for buffering uncompressed data obtained by decompressing the compressed data to be decompressed as dictionary data, A third dictionary compression circuit that performs dictionary compression using the aforementioned dictionary decompression buffer, It has, In the second mode, the dictionary buffer concatenation control circuit is configured as follows: The oldest dictionary data in the dictionary buffer of the Nth data compression circuit is shifted to the dictionary decompression buffer of the second data decompression circuit. The oldest dictionary data in the dictionary expansion buffer of the j-th data expansion circuit is shifted to the dictionary expansion buffer of the (j+1)-th data expansion circuit. The dictionary buffer and the dictionary decompression buffer are further concatenated in this manner. The dictionary compression results of the third dictionary compression circuit of the data decompression circuit from the second to the Nth data are input to the longest match selection circuit. Data compression and decompression system.

9. Each of the aforementioned data compression circuits has an entropy coding circuit, The aforementioned dictionary buffer concatenation control circuit is In the first mode, the dictionary compression results of the N first dictionary compression circuits are input to the N entropy coding circuits, each of the N data compression circuits, In the case of the second mode described above, The dictionary compression result selected by the longest match selection circuit is input to the entropy coding circuit of the first data compression circuit. The (N-1) entropy coding circuits of the second to the Nth data compression circuits are deactivated. The data compression / decompression system according to claim 8.

10. A data compression device having a data compression circuit including a first dictionary compression circuit, A data decompression device having a data decompression circuit including a third dictionary compression circuit, It is equipped with, The aforementioned data compression device is A dictionary buffer coupling control circuit controls the switching between a first mode in which the data compression circuit operates independently and a second mode in which the data compression circuit and the data decompression circuit cooperate. In the second mode described above, a longest match selection circuit selects the dictionary compression result with the longest match length from among the dictionary compression results of the first dictionary compression circuit and the dictionary compression results of the third dictionary compression circuit, It has, The data decompression circuit has a dictionary decompression buffer for buffering the uncompressed data obtained by decompressing the compressed data to be decompressed as dictionary data. The third dictionary compression circuit performs dictionary compression using the dictionary decompression buffer. In the second mode, the dictionary buffer concatenation control circuit is configured as follows: The dictionary buffer and the dictionary decompression buffer are linked such that the oldest dictionary data in the dictionary buffer of the data compression circuit is shifted to the dictionary decompression buffer of the data decompression circuit. Data compression and decompression system.

11. The data compression circuit has an entropy coding circuit, The aforementioned dictionary buffer concatenation control circuit is When the first mode is selected, the dictionary compression result of the first dictionary compression circuit is input to the entropy coding circuit. In the second mode described above, the dictionary compression result selected by the longest match selection circuit is input to the entropy coding circuit. The data compression / decompression system according to claim 10.

12. The data compression / decompression system according to claim 8 or 10, wherein the third dictionary compression circuit performs hash-based dictionary compression.

Images