Phased array transmitter, transmission method, and program

Abstract

This invention provides a phased array transmitter, a transmission method, and a program that suppress the increase in bandwidth required for DPD. [Solution] The phased array transmitter comprises a plurality of power amplifiers, a plurality of antennas that form N beams based on a plurality of amplified signals, each amplified by the plurality of power amplifiers from N (N is an integer of 2 or more) transmission signals, an interference suppression unit that applies gain and phase shift to the N feedback signals or a plurality of amplified signals so that the bandwidth of the kth feedback signal (k=1~N) after interference suppression, which is represented by a linear sum of N feedback signals or a linear sum of the plurality of amplified signals based on the actual received signals or estimated received signals of the N beams, is narrowed, and a distortion compensation unit that uses the kth feedback signal after interference suppression to determine a distortion compensation coefficient for compensating for nonlinear distortion occurring in the plurality of power amplifiers.

Description

Technical Field

[0001] The present disclosure relates to a phased array transmitter, a transmission method, and a program.

Background Art

[0002] Patent Document 1 discloses a wireless communication system that suppresses interference between beams with different frequencies. The related wireless communication system generates a cancellation signal corresponding to beam interference, adds the frequency-shifted cancellation signal to a transmission signal, and outputs the transmission signal with the cancellation signal added to a DPD (Digital Pre-Distortion) processing unit.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Since the bandwidth of the signal with the cancellation signal added increases, the related wireless communication system has a problem that the bandwidth required for DPD is wide.

[0005] The present disclosure has been made to solve such problems, and an object thereof is to provide a phased array transmitter, a transmission method, and a program that suppress an increase in the bandwidth required for DPD.

Means for Solving the Problems

[0006] The phased array transmitter according to the present disclosure is a plurality of antennas that form N beams (N is an integer of 2 or more) based on a plurality of amplified signals respectively amplified by the plurality of power amplifiers from N transmission signals (N is an integer of 2 or more), An interference suppression unit that applies gain and phase shift to the N feedback signals or the multiple amplification signals such that the bandwidth of the kth feedback signal (k=1~N) after interference suppression, which is represented by a linear sum of N feedback signals based on the actual received signals or estimated received signals of the N beams, or a linear sum of the multiple amplification signals, is narrowed. A strain compensation unit that uses the kth feedback signal after interference suppression to determine a strain compensation coefficient for compensating for the nonlinear strain generated in the plurality of power amplifiers. It is equipped with.

[0007] The method of transmission related to this disclosure is: Gain and phase shift are applied to the N feedback signals or the multiple amplified signals such that the bandwidth of the kth feedback signal after interference suppression is narrowed, which is represented by a linear sum of multiple amplified signals each amplified by multiple power amplifiers provided in a phased array transmitter that forms N beams from N (where N is an integer greater than or equal to 2) transmit signals, or a linear sum of N feedback signals based on the actual received signals or estimated received signals of the N beams. Using the kth feedback signal after interference suppression, a distortion compensation coefficient is determined to compensate for the nonlinear distortion generated in the multiple power amplifiers.

[0008] The program related to this disclosure is A process of applying gain and phase shift to the N feedback signals or the multiple amplified signals such that the bandwidth of the kth feedback signal after interference suppression is narrowed, which is represented by a linear sum of multiple amplified signals each amplified by multiple power amplifiers provided in a phased array transmitter that forms N beams from N (N is an integer greater than or equal to 2) transmit signals, or a linear sum of N feedback signals based on the actual received signals or estimated received signals of the N beams. A process to determine a distortion compensation coefficient for compensating for the nonlinear distortion generated in the multiple power amplifiers using the feedback signal k after interference suppression. Have the computer execute it. [Effects of the Invention]

[0009] This disclosure provides a phased array transmitter, a transmission method, and a program that can suppress the increase in bandwidth required for DPD. [Brief explanation of the drawing]

[0010] [Figure 1] This is a diagram illustrating an example configuration of a phased array transmitter according to this disclosure. [Figure 2] This is a diagram illustrating an example of the operation of the phased array transmitter described herein. [Figure 3] This is a diagram illustrating an example configuration of a phased array transmitter according to this disclosure. [Figure 4] This is a diagram illustrating an example configuration of a phased array transmitter according to this disclosure. [Figure 5] This is a diagram illustrating an example configuration of a phased array transmitter according to this disclosure. [Figure 6] This is a diagram illustrating an example configuration of a phased array transmitter according to this disclosure. [Figure 7] This is a diagram illustrating an example configuration of a phased array transmitter according to this disclosure. [Figure 8] This is a diagram illustrating an example configuration of a phased array transmitter according to this disclosure. [Figure 9] This is a diagram illustrating an example configuration of a phased array transmitter according to this disclosure. [Figure 10] This is a diagram illustrating an example of the operation of the phased array transmitter described herein. [Figure 11] This is a diagram illustrating an example of the hardware configuration of a phased array transmitter according to this disclosure. [Modes for carrying out the invention]

[0011] The specific configuration of this embodiment will be described below with reference to the drawings. The following description illustrates preferred embodiments of the present invention, and the scope of the present invention is not limited to these embodiments. In the following description, the same reference numerals indicate substantially the same function.

[0012] Embodiment 1 Referring to Figure 1, the phased array transmitter 1000 includes DPD (Digital Pre-Distortion) 11-14, DAC (Digital To Analog Converter) 21-24, upconverters 31-34, array banks 41-4M, adders 51-5M, power amplifiers 61-6M, antennas 71-7M, array banks 81-8M, adders 91-94, downconverters 101-104, ADC (Analog To Digital Converter) 111-114, interference suppression circuit 120, downconverters 131-134, and a learning unit 140. Note that the filters after upconverters 31-34 and downconverters 101-104 and 131-134 are not shown. In Figure 1, the unidirectional arrows simply indicate the direction of a signal (data) flow and do not exclude bidirectionality. The same applies to Figures 3-8, which will be described later.

[0013] In the following, array banks 41-4M may be simply referred to as array bank 4 when they are not distinguished from each other. Adding units 51-5M may be simply referred to as adding unit 5 when they are not distinguished from each other. Power amplifiers 61-6M may be simply referred to as power amplifier 6 when they are not distinguished from each other. Antennas 71-7M may be simply referred to as antenna 7 when they are not distinguished from each other. Array banks 81-8M may be simply referred to as array bank 8 when they are not distinguished from each other.

[0014] The phased array transmitter 1000 forms N beams from N transmission signals. The N beams may be formed using N types of bands, or each beam may be formed using multiple types of bands. N is an arbitrary integer of 2 or more. Although the case of N = 4 will be specifically described, N may be 3 or less, or may be 5 or more. Transmission signals x1 to x4 are input to the phased array transmitter 1000. When the transmission signals x1 to x4 are not distinguished from each other, they may simply be referred to as the transmission signal x. The phased array transmitter 1000 includes M antennas 71 to 7M. M is an arbitrary integer of 2 or more, and M may be larger than N.

[0015] Each component of the phased array transmitter 1000 may be software or a module in which processing is executed by a processor executing a program stored in a memory. Alternatively, each component may be hardware such as a circuit or a chip.

[0016] DPD11 applies the distortion compensation coefficient determined by the learning unit 140 to the transmission signals x1 to x4 to generate a distortion-compensated signal x1 ’ . Similarly, DPD12 to DPD14 each generate a distortion-compensated signal x2 ’ to x4 ’ respectively. DAC21 to 24 each perform DA conversion on the distortion-compensated signals x1 ’ to x4 ’ respectively.

[0017] The upconverter 31 shifts the frequency of the DA-converted signal x1 ’ by f1 and outputs the frequency-shifted signal x1 ’ to each of the array banks 41 to 4M. The upconverter 32 shifts the frequency of the DA-converted signal x2 ’ by f2 and outputs the frequency-shifted signal x2 ’ to each of the array banks 41 to 4M. The upconverter 33 shifts the frequency of the DA-converted signal x3 ’ by f3 and outputs the frequency-shifted signal x3 ’The output is sent to each of the array banks 41-4M. The upconverter 34 outputs four DA-converted signals. ’ The frequency is shifted by f4, and the frequency-shifted signal x4 ’ Output to each of array banks 41-4M.

[0018] Array Bank 4 has signal x1 ’ ~x4 ’ Gain and phase shift are applied to each of them. In other words, array bank 4 is for signal x1 ’ ~x4 ’ The amplitude of each element is varied, and the phase is also varied. Array bank 4 is composed of analog circuits such as a VGA (Variable Gain Amplifier) ​​and a phase shifter. Array bank 8 and array banks 1211-1214 and 1231-123M, which will be described later, are similar.

[0019] The gain and phase shift amounts provided by array bank 4 are represented by the array matrix F. For example, if the spatial channel matrix is ​​H, then the array matrix F is matrix H H The channel matrix H may also be, for example, a matrix composed of the amplitude and phase variations in the transmission path (channel) between each transmitting antenna (antenna 7) and receiving antenna. The superscript H represents the adjoint matrix.

[0020] The summing unit 5 adds gain and phase shift to the signal x1, which has been given gain and phase shift by the corresponding array bank 4. ’ ~x4 ’ The signals are added together. Power amplifier 6 amplifies the output signal of the corresponding adder 5. Antenna 7 transmits the signal amplified by the corresponding power amplifier 6. Four beams B1 to B4 are formed by the transmission of signals from M antennas 7. Receivers 201 to 204 each receive beams B1 to B4. Beams B1 to B4 correspond to transmitted signals x1 to x4, respectively. When receivers 201 to 204 are not distinguished from each other, they may simply be referred to as receiver 200.

[0021] The array bank 8 imparts gain and phase shift amounts to the output signal of the corresponding power amplifier 6, determined according to the spatial channel matrix H. The phased array transmitter 1000 may estimate the spatial channel matrix H using a known signal (e.g., a pilot signal) between the phased array transmitter 1000 and the receiver 200. Alternatively, the phased array transmitter 1000 may estimate the spatial channel matrix H by estimating the radio wave propagation characteristics from the positional relationship between the phased array transmitter 1000 and the receiver 200 and the antenna arrangement.

[0022] The summing unit 91 adds the output signals of array banks 81 to 8M to generate a feedback signal FB1 that estimates the received signal of beam B1. The summing unit 92 adds the output signals of array banks 81 to 8M to generate a feedback signal FB2 that estimates the received signal of beam B2. The summing unit 93 adds the output signals of array banks 81 to 8M to generate a feedback signal FB3 that estimates the received signal of beam B3. The summing unit 94 adds the output signals of array banks 81 to 8M to generate a feedback signal FB4 that estimates the received signal of beam B4.

[0023] Downconverters 101-104 shift the frequency of feedback signals FB1-FB4 by f. ADCs 111-114 each perform AD conversion on the frequency-shifted feedback signals FB1-FB4.

[0024] The interference suppression circuit 120 outputs the feedback signal FB after interference suppression, which is represented by a linear sum of frequency-shifted feedback signals FB1 to FB4. k ’ Gain and phase shift are applied to each of the feedback signals FB1 to FB4 so that the bandwidth of (k=1 to 4) is narrowed. The diagram placed below the interference suppression circuit 120 schematically shows the processing performed by the interference suppression circuit 120. The dashed arrows represent the process of applying complex weights w, i.e., complex multiplication. If the information of array bank 4 is known, that is, if the array matrix F is known, the weights w in the interference suppression circuit 120 are the matrix (HF) -1It can be calculated exactly according to the matrix (HF). -1 By using this method, the effects of interference are removed, and the feedback signal FB1 after interference suppression is obtained. ’ ~FB4 ’ The bandwidth of each of these can be narrowed.

[0025] Referring to Figure 2, the graph located above the downward arrow illustrates the spectrum of the feedback signal input to the interference suppression circuit 120. The horizontal axis represents frequency, and the vertical axis represents signal level. The hatched low-frequency band contains interference from the adjacent channel, increasing the bandwidth of the feedback signal. Referring to the graph located below the downward arrow, the signal from the adjacent channel has been removed, narrowing the bandwidth of the feedback signal after interference suppression.

[0026] Referring again to Figure 1, the downconverter 131 receives the feedback signal FB1 after interference suppression. ’ The frequency is shifted by (f1-f). The downconverter 132 receives the feedback signal FB2 after interference suppression. ’ The frequency is shifted by (f2-f). The downconverter 133 receives the feedback signal FB3 after interference suppression. ’ The frequency is shifted by (f3-f). The downconverter 134 receives the feedback signal FB4 after interference suppression. ’ Shift the frequency by (f4-f).

[0027] The learning unit 140 receives the frequency-shifted, interference-suppressed feedback signal FB1 ’ ~FB4 ’ Using signals x1 to x4, the distortion compensation coefficient for DPD processing is determined.

[0028] The learning unit 140 may, for example, determine the distortion compensation coefficient according to the Volterra series. Figure 1 shows the distortion-compensated signal x1. ’ ~x4 ’ Let z1, z2, z4 be the respective signals. Then, DPD11 is given by z1 = f1(x1, x2, x3, x4, α1) from the signals x1, x2, x3, x4. (n)) Outputs. α1 (n) This represents the distortion compensation coefficient used in the nth compensation. Similarly, for DPD12~14, z² = f²(x1, x2, x3, x4, α² (n) )~z4=f4(x1,x2,x3,x4,α4 (n) Outputs ).

[0029] Then, the learning unit 140 calculates α1 according to the following equations (1) and (2). (n) The learning unit 140 optimizes Δα1 according to equation (2), and uses Δα1 to update α1. (n) Update α2 (n) ~α4 (n) Also, α1 (n) It will be updated in the same way.

number

number

[0030] The learning unit 140 may use series other than Volterra series. Furthermore, the learning unit 140 may perform calculations equivalent to those using series by using a LUT (Look Up Table).

[0031] The phased array transmitter 1000 may be used, for example, in Beyond 5G to transmit high-quality data to a large number of user terminals simultaneously without interference. Alternatively, the phased array transmitter 1000 may be used, for example, in satellite communications to transmit high-quality data to a large number of ground stations simultaneously without interference.

[0032] The inventors have discovered that, with regard to the relevant phased array transmitter, the distortion of the own channel is not affected even if the distortion of the signal in the adjacent channel is not canceled. This is because signals in frequency bands other than the desired band can be filtered out from the received signal. However, if the distortion of the signal in the adjacent channel is not canceled, it is necessary to effectively suppress interference in the feedback signal.

[0033] Embodiment 1 calculates the distortion compensation coefficient for DPD processing using a bandwidth-limited feedback signal, thereby suppressing the increase in bandwidth required for DPD and reducing costs.

[0034] Modification 1 of Embodiment 1 Comparing Figure 1 and Figure 3, Figure 3 includes additional upconverters 151-154 and an interference control unit 160. The interference control unit 160 may be software or a module whose processing is performed by the processor executing a program stored in memory. Alternatively, the interference control unit 160 may be hardware such as a circuit or chip.

[0035] The upconverter 151 generates a reference signal x1 by shifting the frequency of the transmitted signal x1 by (f1-f). f The signal is output to the interference control unit 160. The upconverter 152 outputs a reference signal x2 obtained by frequency shifting the transmitted signal x2 by (f2-f). f The signal is output to the interference control unit 160. The upconverter 153 outputs a reference signal x3 obtained by frequency shifting the transmitted signal x3 by (f3-f). f The signal is output to the interference control unit 160. The upconverter 154 outputs a reference signal x4 obtained by frequency shifting the transmitted signal x4 by (f4-f). f This is output to the interference control unit 160.

[0036] The interference control unit 160 denotes the AD-converted feedback signals FB1 to FB4 as z1 to z4, respectively, and calculates the interference rejection matrix G according to the following equation (3).

number

[0037] The interference suppression circuit 120 applies gain and phase shift to the feedback signals FB1 to FB4 according to the interference removal matrix G calculated by the interference control unit 160. Then, the interference suppression circuit 120 applies the feedback signal FB1 after interference suppression.’ ~FB4 ’ This is output to the learning unit 140. In other words, the interference control unit 160 controls the interference suppression circuit 120 so that the error between each output signal of the interference suppression circuit 120 and the corresponding reference signal is minimized.

[0038] Even when the array matrix F is unknown or when the error in the array matrix F is significant, the modification 1 of Embodiment 1 can suppress the increase in the bandwidth required for the DPD.

[0039] Modification 2 of Embodiment 1 Figure 4 is a diagram illustrating an example configuration of the phased array transmitter 1000 according to this disclosure. The upconverters 31-34 described above may be placed between the DACs 21-24 and the array banks 41-4M. Alternatively, the downconverters 131-134 described above may be placed after the interference suppression circuit 120.

[0040] Receivers 201 to 204 each receive beams B1 to B4 at different azimuth angles φ and elevation angles θ. When the received signals y1 to y4 from receivers 201 to 204 are not distinguished from each other, they are sometimes simply referred to as received signal y. If P is the matrix representing the signal amplification by power amplifier 6, then y = HPFx holds. Receiver 201 transmits received signal y1 as feedback signal FB1 to the phased array transmitter 1000. Receiver 202 transmits received signal y2 as feedback signal FB2 to the phased array transmitter 1000. Receiver 203 transmits received signal y3 as feedback signal FB3 to the phased array transmitter 1000. Receiver 204 transmits received signal y4 as feedback signal FB4 to the phased array transmitter 1000.

[0041] The interference suppression circuit 120 is an interference-suppressed kth feedback signal FB, which is represented by a linear sum of feedback signals FB1 to FB4 based on the actual received signal. kGain and phase shift are applied to the feedback signals FB1 to FB4 so that the bandwidth of (k=1 to 4) is narrowed. As in the modified example 1 of Embodiment 1, the phased array transmitter 1000 may suppress interference using the interference control unit 160.

[0042] By modifying Embodiment 1 in Modification 2, it is possible to suppress the increase in bandwidth required for the DPD even when using an actual received signal.

[0043] Embodiment 2 Referring to Figure 5, the interference suppression circuit 120 is composed of analog circuits, and the ADCs 111 to 114 are located downstream of the interference suppression circuit 120.

[0044] The interference suppression circuit 120 comprises array banks 1211 to 1214 and adders 1221 to 1224. Each of the array banks 1211 to 1214 is an interference suppression matrix (HF) -1 Gain and phase shift are applied to the feedback signals FB1 to FB4 accordingly. The summing unit 1221 adds the output signals of array banks 1211 to 1214 to obtain the feedback signal FB1 after interference suppression. ’ The summing unit 1222 adds the output signals of array banks 1211 to 1214 to generate the feedback signal FB2 after interference suppression. ’ The summing unit 1223 adds the output signals of array banks 1211 to 1214 to generate the feedback signal FB3 after interference suppression. ’ The summing unit 1222 adds the output signals of array banks 1211 to 1214 to generate the feedback signal FB4 after interference suppression. ’ Generates.

[0045] The downconverter 131 receives the feedback signal FB1 after interference suppression. ’ The frequency is shifted by f1. The downconverter 132 receives the feedback signal FB2 after interference suppression. ’ The frequency is shifted by f2. The downconverter 133 receives the feedback signal FB3 after interference suppression. ’The frequency is shifted by f3. The downconverter 134 receives the feedback signal FB4 after interference suppression. ’ The frequency is shifted by f4. ADC111~114 each transmit the frequency-shifted, interference-suppressed feedback signal FB1. ’ ~FB4 ’ Convert the data to AD.

[0046] In Embodiment 2, before sampling with ADC111-114, the feedback signal FB1 after interference suppression is processed. ’ ~FB4 ’ Because the bandwidth is limited, the required speed for ADC111-114 is relaxed, allowing for lower-cost implementation. By matching the frequency shift amount of downconverters 131-134 to the frequency of the corresponding channel, the signal bandwidth required for ADC111-114 can be reduced to its limit.

[0047] Modification 1 of Embodiment 2 Comparing Figure 5 and Figure 6, Figure 6 shows the addition of an interference control unit 160. The interference control unit 160 takes the output signals of ADCs 111 to 114 as z1 to z4, respectively, and calculates the interference removal matrix G according to equation (3) above. If it is difficult to obtain the interference removal matrix G precisely in a single calculation, the interference removal matrix G may be obtained, for example, by sweeping the parameters that define the interference removal matrix G.

[0048] Even when the array matrix F is unknown or when the error in the array matrix F is significant, the required speed of ADCs 111 to 114 can be reduced by the modification 1 of Embodiment 2.

[0049] Embodiment 3 Embodiment 3 is a specific example of Embodiment 2. Comparing Figure 5 and Figure 7, the M array banks 81-8M and 4 array banks 1211-1214 in Figure 5 are integrated into the M array banks 1231-123M in Figure 7. In other words, array banks 81-8M are not provided in the path between the interference suppression circuit 120 and the power amplifier 6. When array banks 1231-123M are not distinguished from each other, they may simply be referred to as array bank 123.

[0050] The interference suppression circuit 120 comprises array banks 1231-123M and adders 1221-1224. Array bank 123 is a matrix (HF) -1 H=F -1 H -1 H=F -1 In other words, gain and phase shift are applied to the amplified signal from the corresponding power amplifier 6 according to the inverse matrix of the array matrix F. The summing unit 1221 adds the output signals of array banks 1231 to 123M to produce the feedback signal FB1 after interference suppression. ’ The summing unit 1222 adds the output signals of array banks 1231 to 123M to generate the feedback signal FB2 after interference suppression. ’ The summing unit 1223 adds the output signals of array banks 1231 to 123M to generate the feedback signal FB3 after interference suppression. ’ The summing unit 1224 adds the output signals of array banks 1231 to 123M to generate the feedback signal FB4 after interference suppression. ’ Generates.

[0051] According to Embodiment 3, the array bank placed before the interference suppression circuit 120 is unnecessary, thereby reducing circuit area and cost.

[0052] Modification 1 of Embodiment 3 Comparing Figure 7 and Figure 8, Figure 8 shows that an interference control unit 160 has been added. The interference control unit 160 calculates the interference rejection matrix G according to equation (3) above, using the output signals of ADC111 to 114 as z1 to z4, respectively.

[0053] By modifying Embodiment 3, even when the array matrix F is unknown or when the error in the array matrix F has a large impact, the array bank placed before the interference suppression circuit 120 is not required, thereby reducing circuit area and cost.

[0054] Embodiment 4 Figure 9 is a diagram illustrating an example configuration of a phased array transmitter 1000 according to this disclosure. The phased array transmitter 1000 includes a power amplifier 6, an antenna 7, an interference suppression unit 120, and a distortion compensation unit 140. The interference suppression unit 120 and the distortion compensation unit 140 may be software or modules whose processing is performed by a processor executing a program stored in memory. Alternatively, the interference suppression unit 120 and the distortion compensation unit 140 may be hardware such as a circuit or chip. The interference suppression circuit 120 described above is a specific example of the interference suppression unit 120, and the learning unit 140 described above is a specific example of the distortion compensation unit 140.

[0055] Multiple antennas 7 form N beams based on multiple amplified signals, each amplified by multiple power amplifiers 6, from N (where N is an integer greater than or equal to 2) transmitted signals.

[0056] The interference suppression unit 120 applies gain and phase shift to the N feedback signals or the multiple amplified signals such that the bandwidth of the kth feedback signal (k=1~N) after interference suppression, which is represented by a linear sum of N feedback signals based on the actual received signals or estimated received signals of the N beams, or a linear sum of the multiple amplified signals, is narrowed.

[0057] The distortion compensation unit 140 uses the kth feedback signal after interference suppression to determine a distortion compensation coefficient for compensating for the nonlinear distortion generated in the multiple power amplifiers 6.

[0058] Figure 10 is a flowchart illustrating the transmission method according to the present disclosure. First, the interference suppression unit 120 applies gain and phase shift to N feedback signals or a plurality of amplified signals so that the bandwidth of the kth feedback signal after interference suppression is narrowed (step S101). Next, the distortion compensation unit 140 determines a distortion compensation coefficient using the kth feedback signal after interference suppression (step S102). Steps S101 to S102 may be repeated.

[0059] Figure 11 is a diagram illustrating an example of the hardware configuration of the phased array transmitter 1000. The power amplifier 6 and antenna 7 are not shown. Referring to Figure 11, the phased array transmitter 1000 includes a network interface 1001, a processor 1002, and memory 1003. The network interface 1001 is used to communicate with other network node devices that constitute the communication system. The network interface 1001 may also be used for wireless communication. For example, the network interface 1001 may be used for wireless LAN communication as defined in the IEEE 802.11 series, or for mobile communication as defined in 3GPP® (3rd Generation Partnership Project). Alternatively, the network interface 1001 may include, for example, a network interface card (NIC) compliant with the IEEE 802.3 series.

[0060] The processor 1002 reads and executes software (computer programs) from memory 1003, thereby performing the processes shown in steps S101 to S102 of Figure 10. The processor 1002 may be, for example, a microprocessor, an MPU, or a CPU. The processor 1002 may include multiple processors.

[0061] Memory 1003 is composed of a combination of volatile and non-volatile memory. Memory 1003 may also include storage located away from the processor 1002. In this case, the processor 1002 may access memory 1003 via an I / O (Input / Output) interface, which is not shown.

[0062] In the example shown in Figure 11, memory 1003 is used to store a group of software modules. The processor 1002 can perform the processing in steps S101 to S102 by reading these software modules from memory 1003 and executing them.

[0063] As explained with reference to Figure 11, each of the processors in the phased array transmitter 1000 in the above embodiment executes one or more programs that include a set of instructions for causing a computer to perform the algorithm described with reference to the drawings.

[0064] In the examples described above, the program includes a set of instructions (or software code) that, when loaded into a computer, cause the computer to perform one or more of the functions described in the embodiments. The program may be stored on a non-temporary computer-readable medium or a physical storage medium. Examples, but not limited to, include random-access memory (RAM), read-only memory (ROM), flash memory, solid-state drive (SSD) or other memory technologies, CD-ROM, digital versatile disc (DVD), Blu-ray® disc or other optical disc storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices. The program may be transmitted over a temporary computer-readable medium or a communication medium. Examples, but not limited to, include temporary computer-readable medium or a communication medium that includes electrically, optically, acoustically or otherwise propagating signals.

[0065] Furthermore, the technical concepts described in this disclosure are not limited to the embodiments described above, and may be modified as appropriate without departing from the spirit of the invention.

[0066] Although the present disclosure has been described above with reference to embodiments, the present disclosure is not limited to the embodiments described above. Various modifications to the structure and details of the present disclosure can be made as can be understood by those skilled in the art within the scope of the present disclosure. Furthermore, each embodiment can be combined with other embodiments as appropriate.

[0067] Each drawing is merely illustrative to illustrate one or more embodiments. Each drawing may be associated with one or more other embodiments rather than with only one specific embodiment. As those skilled in the art will understand, various features or steps described with reference to any one drawing can be combined with features or steps shown in one or more other drawings, for example, to create embodiments not explicitly shown or described. Not all features or steps shown in any one drawing to illustrate an exemplary embodiment are necessarily required, and some features or steps may be omitted. The order of steps shown in any of the drawings may be changed as appropriate.

[0068] Some or all of the embodiments described above may also be described as follows, but are not limited to the following: Some or all of the elements (e.g., configurations and functions) described in Appendices 2 to 8 that are dependent on Appendice 1 may also be dependent on Appendices 9 and 10 in the same way as in Appendices 2 to 8. Some or all of the elements described in any appendice may be applied to various hardware, software, recording means, systems, and methods for recording software.

[0069] (Note 1) Multiple power amplifiers, Multiple antennas that form N beams based on multiple amplified signals, each amplified by the multiple power amplifiers, from N (where N is an integer greater than or equal to 2) transmission signals, An interference suppression unit that applies gain and phase shift to the N feedback signals or the multiple amplification signals such that the bandwidth of the kth feedback signal (k=1~N) after interference suppression, which is represented by a linear sum of N feedback signals based on the actual received signals or estimated received signals of the N beams, or a linear sum of the multiple amplification signals, is narrowed. A strain compensation unit that uses the kth feedback signal after interference suppression to determine a strain compensation coefficient for compensating for the nonlinear strain generated in the plurality of power amplifiers. A phased array transmitter equipped with a phased array transmitter. (Note 2) The gain and phase shift amounts are based on the inverse matrix of the product of the array matrix and spatial channel matrix of the phased array. Phased array transmitter as described in Appendix 1. (Note 3) An interference control unit calculates the gain and phase shift amount such that the difference between the k-th feedback signal and the k-th reference signal corresponding to the k-th feedback signal is minimized. A phased array transmitter as described in Appendix 1, comprising the following features. (Note 4) Of the N receivers that receive the N beams, the kth receiver receives the kth beam and transmits the received signal of the kth beam to the phased array transmitter as the kth feedback signal. A phased array transmitter as described in any one of the items 1 to 3 of the appendix. (Note 5) The interference suppression unit is composed of an analog circuit, A downconverter that downconverts the kth feedback signal after interference suppression according to the frequency at which the kth transmission signal among the N transmission signals is transmitted, An AD converter that performs AD conversion on the kth feedback signal after the interference suppression has been downconverted. A phased array transmitter as described in Appendix 2 or 3, comprising: (Note 6) The gain and phase shift are calculated based on the kth feedback signal after the interference suppression has been converted using AD conversion. Phased array transmitter as described in Appendix 5. (Note 7) The k-th feedback signal after interference suppression is represented by a linear sum of the plurality of amplified signals. Phased array transmitter as described in Appendix 5. (Note 8) The aforementioned distortion compensation coefficient is updated according to the Volterra series. Phased array transmitter as described in Appendix 1 or 2. (Note 9) Gain and phase shift are applied to the N feedback signals or the multiple amplified signals such that the bandwidth of the kth feedback signal after interference suppression is narrowed, which is represented by a linear sum of multiple amplified signals each amplified by multiple power amplifiers provided in a phased array transmitter that forms N beams from N (where N is an integer greater than or equal to 2) transmitted signals, or a linear sum of N feedback signals based on the actual received signals or estimated received signals of the N beams. Using the kth feedback signal after interference suppression, a distortion compensation coefficient is determined to compensate for the nonlinear distortion occurring in the multiple power amplifiers. Sending method. (Note 10) A process of applying gain and phase shift to the N feedback signals or the multiple amplified signals such that the bandwidth of the kth feedback signal after interference suppression is narrowed, which is represented by a linear sum of multiple amplified signals each amplified by multiple power amplifiers provided in a phased array transmitter that forms N beams from N (N is an integer greater than or equal to 2) transmit signals, or a linear sum of N feedback signals based on the actual received signals or estimated received signals of the N beams. A process to determine a distortion compensation coefficient for compensating for the nonlinear distortion generated in the multiple power amplifiers using the feedback signal k after interference suppression. A program that causes a computer to execute something. [Explanation of Symbols]

[0070] 1000 Phased Array Transmitter 11-14 DPD 21-24 DAC 31-34, 151-154 Upconverter 41-4M, 4, 81-8M, 8, 1211-1214, 1231-123M, 123 Array Bank 51~5M, 5, 91~94, 1221~1224 Addition section 61~6M, 6 Power Amplifier 71~7M, 7 antennas 101-104, 131-134 Downconverter 111-114 ADC 120 Interference suppression unit 140 Learning Department 160 Interference Control Unit 201-204, 200 Receiver 1001 Network Interface 1002 Processor 1003 memory

Claims

1. Multiple power amplifiers, Multiple antennas that form N beams based on multiple amplified signals, each amplified by the multiple power amplifiers, from N (where N is an integer of 2 or more) transmission signals, An interference suppression unit that applies gain and phase shift to the N feedback signals or the plurality of amplified signals such that the bandwidth of the kth feedback signal (k=1 to N) after interference suppression, which is represented by a linear sum of N feedback signals based on the actual received signals or estimated received signals of the N beams, or a linear sum of the plurality of amplified signals, is narrowed. A strain compensation unit that uses the kth feedback signal after interference suppression to determine a strain compensation coefficient for compensating for the nonlinear strain generated in the plurality of power amplifiers. A phased array transmitter equipped with a phased array transmitter.

2. The gain and phase shift amounts are based on the inverse matrix of the product of the array matrix and spatial channel matrix of the phased array. The phased array transmitter according to claim 1.

3. The interference control unit calculates the gain and phase shift amount such that the difference between the k feedback signal and the k reference signal corresponding to the k feedback signal is minimized. A phased array transmitter according to claim 1, comprising:

4. Of the N receivers that receive the N beams, the kth receiver receives the kth beam and transmits the received signal of the kth receiver to the phased array transmitter as the kth feedback signal. A phased array transmitter according to any one of claims 1 to 3.

5. The interference suppression unit is composed of an analog circuit, A downconverter that downconverts the kth feedback signal after interference suppression according to the frequency at which the kth transmission signal among the N transmission signals is transmitted, An AD converter that performs AD conversion on the kth feedback signal, which has been down-converted and has had interference suppressed. A phased array transmitter according to claim 2 or 3, comprising:

6. The gain and phase shift are calculated based on the kth feedback signal after AD conversion and interference suppression. The phased array transmitter according to claim 5.

7. The k-th feedback signal after interference suppression is represented by a linear sum of the plurality of amplified signals. The phased array transmitter according to claim 5.

8. The aforementioned distortion compensation coefficient is updated according to the Volterra series. A phased array transmitter according to claim 1 or 2.

9. Gain and phase shift are applied to the N feedback signals or the multiple amplified signals such that the bandwidth of the kth feedback signal after interference suppression is narrowed, which is represented by a linear sum of multiple amplified signals each amplified by multiple power amplifiers provided in a phased array transmitter that forms N beams from N (where N is an integer of 2 or more) transmit signals, or a linear sum of N feedback signals based on the actual received signals or estimated received signals of the N beams. Using the kth feedback signal after interference suppression, a distortion compensation coefficient is determined to compensate for the nonlinear distortion occurring in the multiple power amplifiers. Sending method.

10. A process of applying gain and phase shift to the N feedback signals or the multiple amplified signals such that the bandwidth of the kth feedback signal after interference suppression is narrowed, which is represented by a linear sum of multiple amplified signals each amplified by multiple power amplifiers provided in a phased array transmitter that forms N beams from N (where N is an integer of 2 or more) transmit signals, or a linear sum of N feedback signals based on the actual received signals or estimated received signals of the N beams. A process to determine a distortion compensation coefficient for compensating for the nonlinear distortion generated in the plurality of power amplifiers using the feedback signal k after interference suppression. A program that causes a computer to execute something.

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