Isolator

Abstract

To provide an isolator that can reduce signal transmission delay while simultaneously reducing power consumption. [Solution] The isolator according to the embodiment includes a ΔΣ modulated analog-to-digital converter that converts an input analog signal into a pulse train digital data signal corresponding to the amplitude and outputs it; an attribute signal detection circuit that outputs input attribute information relating to the attributes of the input analog signal; a high-speed feedback encoder that encodes the digital data signal based on the input attribute information and outputs a first encoded signal; an edge encoder that edge encodes the first encoded signal and outputs a second encoded signal; an isolated transmission circuit that outputs a transmission signal transmitted through an isolation section according to the second encoded signal; and a demodulation circuit that outputs a demodulated digital data signal obtained by demodulating the digital data signal based on the transmission signal, and / or outputs demodulated attribute information obtained by demodulating the input attribute information.

Description

[Technical Field]

[0001] This embodiment relates to an isolator. [Background technology]

[0002] Generally, an isolator is distinguished, for example, by an insulating layer, into a primary circuit on the input side and a secondary circuit on the output side. In this case, the primary circuit digitizes the analog signal input from the target device, modulates it, and then transmits it to the insulating layer. The secondary circuit demodulates the data transmitted through the insulating layer and outputs it.

[0003] An example of such an isolator is the isolation amplifier, and in its primary circuit, a ΔΣ modulated analog-to-digital converter (ΔΣADC) is used to digitize the analog input signal. A ΔΣADC is a circuit that oversamples the analog signal, modulates it using ΔΣ modulation, and quantizes it, thereby converting it into a digital signal or pulse train corresponding to the amplitude of the analog signal and outputting it. Because the quantization noise in the output signal of this ΔΣADC is biased towards the high-frequency side due to ΔΣ modulation, the quantization noise can be effectively removed by, for example, incorporating a low-pass filter in the secondary circuit. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Application No. 2022-148872 [Overview of the project] [Problems that the invention aims to solve]

[0005] One embodiment aims to provide an isolator that can reduce signal transmission delay while simultaneously reducing power consumption. [Means for solving the problem]

[0006] An isolator according to one embodiment is: A ΔΣ modulated analog-to-digital converter receives an input analog signal and converts it into a digital data signal of a pulse train corresponding to the amplitude of the input analog signal, and outputs it. An attribute signal detection circuit detects the attributes of the input analog signal and outputs input attribute information relating to the attributes of the input analog signal. A high-speed feedback encoder that encodes the digital data signal based on the input attribute information and outputs a first encoded signal, An edge encoder that receives the first encoded signal as input, edge encodes the first encoded signal, and outputs a second encoded signal, An isolated transmission circuit having an insulating section where the input and output are electrically isolated, receiving the second encoded signal and outputting a transmission signal transmitted through the insulating section in accordance with the second encoded signal, The system includes a demodulation circuit that receives the transmission signal and outputs a demodulated digital data signal obtained by demodulating a second encoded signal based on the transmission signal, and / or the input attribute information. It is characterized by the following: [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows an example of the configuration of an isolator according to the first embodiment. [Figure 2] Figure 2 shows an example of a signal waveform in the isolator shown in Figure 1. [Figure 3] Figure 3 shows another example of the signal waveform in the isolator shown in Figure 1. [Figure 4] Figure 4 shows an example of how a demodulation circuit determines the type of data sequence of the second encoded signal and the attributes of the input analog signal corresponding to that data sequence. [Figure 5] Figure 5 shows an example of the configuration of an isolator according to the second embodiment. [Figure 6]Figure 6 shows an example of a signal waveform in the isolator shown in Figure 5. [Figure 7] Figure 7 shows an example of a specific configuration of the data rewriting circuit R for the isolator shown in Figure 5. [Figure 8] Figure 8 shows an example of a specific configuration of the demodulation circuit of the isolator shown in Figure 5. [Modes for carrying out the invention]

[0008] The isolators according to the embodiments will be described in detail below with reference to the attached drawings. However, the present invention is not limited to these embodiments.

[0009] (First Embodiment) [Isolator] Figure 1 shows an example of the configuration of an isolator according to the first embodiment.

[0010] As shown in Figure 1, the isolator 100 according to the first embodiment is an isolation amplifier comprising a primary circuit 101 located on the input side and a secondary circuit 102 located on the output side, with an isolation transmission circuit S in between.

[0011] For example, as shown in Figure 1, the specific circuit configuration of this isolator 100 includes a ΔΣ modulated analog-to-digital converter C1, an attribute signal detection circuit DX, a high-speed feedback encoder FFB, an edge encoder EN, an isolated transmission circuit S, a demodulation circuit DM, a control circuit CON, a low-pass filter LPF, a digital-to-analog converter C2, a clock signal generation circuit W, a second pulse transmission circuit QX, a second pulse reception circuit QY, and a transformer QT.

[0012] For example, as shown in FIG. 1, the Σ-modulation analog-digital converter C1, the attribute detection circuit DX, the high-speed feedback encoder FFB, the edge encoder EN, and the first pulse transmission circuit SX of the insulation transmission circuit S and the inductor IX of the transformer T, and the second pulse reception circuit QY and the inductor QIY of the transformer QT are arranged in the primary circuit 101.

[0013] For another example, as shown in FIG. 1, the demodulation circuit DM, the control circuit CON, the low-pass filter LPF, the digital-analog converter C2, and the first pulse reception circuit SY of the insulation transmission circuit S and the inductor IY of the transformer T, and the second pulse transmission circuit QX and the inductor QIX of the transformer QT are arranged in the secondary circuit 102.

[0014] These configurations of the isolator 100 will be described in detail below.

[0015] [ΔΣ-Modulation Analog-Digital Converter] The ΔΣ-modulation analog-digital converter C1 is configured such that, for example, as shown in FIG. 1, an input analog signal VIN is input thereto. Then, this ΔΣ-modulation analog-digital converter C1 oversamples, ΔΣ-modulates, and quantizes the input analog signal VIN in synchronization with the first clock signal CK1, and converts it into a digital data signal ΔΣ of a pulse train corresponding to the amplitude of the input analog signal VIN and outputs the same.

[0016] [Attribute Signal Detection Circuit] The excessive input signal detection circuit DX is configured such that, for example, as shown in FIG. 1, an input analog signal VIN is input thereto. Then, this attribute signal detection circuit DX detects the attribute of the input analog signal VIN and outputs input attribute information ZIN regarding the attribute of the input analog signal VIN to the high-speed feedback encoder shown below.

[0017] For example, the attribute signal detection circuit DX outputs input attribute information ZIN (second polarity "L" in the example of Figures 2 and 3 described later) indicating that the input analog signal VIN is the first attribute which is normally the input of a data signal, if the amplitude of the input analog signal VIN is below an over-threshold set based on the input range of the ΔΣ modulated analog-to-digital converter C1.

[0018] On the other hand, the attribute signal detection circuit DX outputs input attribute information ZIN (first polarity "H" in the example of Figures 2 and 3 described later) indicating that the input analog signal VIN is an over-input signal if the amplitude of the input analog signal VIN is greater than the over-threshold.

[0019] [High-speed feedback encoder] The high-speed feedback encoder (FFB), as shown in Figure 1, for example, receives a digital data signal ΔΣ and input attribute information ZIN as inputs. This high-speed feedback encoder (FFB) is synchronized with a first clock signal CK1 to encode the digital data signal ΔΣ based on the input attribute information ZIN and outputs a 2-bit first encoded signal FOUT.

[0020] For example, a high-speed feedback encoder (FFB) outputs a first encoded signal FOUT, which is encoded according to the polarity of the data sequence of the digital data signal ΔΣ, when the input attribute information ZIN indicates a first attribute.

[0021] On the other hand, the high-speed feedback encoder FFB outputs a first encoded signal FOUT that, when the input attribute information ZIN indicates a second attribute, forcibly rewrites some of the data in the data sequence of the digital data signal ΔΣ (for example, data every other clock cycle of the first clock signal CK1) with a predetermined value (for example, 2-bit data "LL") that has been encoded.

[0022] Therefore, the first encoded signal FOUT, which includes a data sequence containing this predetermined value of rewritten data, contains information about the second attribute related to the overloaded input signal. Although overloaded input is used as an example of input attribute information, it is not limited to this.

[0023] [Edge Encoder] The edge encoder EN receives the first encoded signal FOUT as input. This edge encoder EN performs edge encoding on the first encoded signal FOUT and outputs a 2-bit second encoded signal EOUT (it generates a pulse for the second encoded signal EOUT when it detects an edge of the pulse of the first encoded signal FOUT).

[0024] Furthermore, as shown in Figure 2 described later, this edge encoder EN is configured to perform a refresh operation every refresh cycle (number of cycles) M, generating a refresh pulse in the second encoded signal EOUT.

[0025] [Isolated transmission circuit] The isolated transmission circuit S has insulating sections SX, SY, and T, which electrically isolate the input and output, as shown in Figure 1, for example. This isolated transmission circuit S receives a second encoded signal EOUT as input and outputs a transmission signal DMIN transmitted through the insulating sections SX, SY, and T in response to the second encoded signal EOUT.

[0026] This insulating section SX, SY, and T includes, for example, a first pulse transmitting circuit SX, a transformer T, a first pulse receiving circuit SY, and another transformer T, as shown in Figure 1.

[0027] The first pulse transmitting circuit SX is then configured to receive the second encoded signal EOUT as input. The first pulse transmitting circuit SX then supplies a current corresponding to this second encoded signal EOUT to the inductor IX at one end of the transformer T. In other words, the first pulse transmitting circuit SX generates a pulse signal by supplying current between the P terminal and the N terminal to which the inductor IX is connected. The current flowing through the inductor IX at one end of the transformer T is then transmitted via a magnetic field to the inductor IY at the other end of the transformer T.

[0028] Then, the first pulse receiving circuit SY reconstructs the second encoded signal EOUT based on the signal transmitted to the inductor IY and outputs it as the transmission signal DMIN.

[0029] In particular, this isolated transmission circuit S transmits a transmission signal DMIN of a data sequence of data with first polarity "H" or second polarity "L" synchronized with the first clock signal CK1, in response to the second encoded signal EOUT.

[0030] Furthermore, the isolated transmission circuit S transmits a transmission signal DMIN that does not contain pulses within a predetermined clock period defined by the first clock signal CK1, in response to the second encoded signal EOUT.

[0031] In the example shown in Figure 1, a magnetic coupling method is used in the configuration of the isolated transmission circuit S, but it is not limited to this, and optical coupling or capacitive coupling methods may also be used.

[0032] [Demodulation circuit] The demodulation circuit DM receives the transmission signal DMIN as input, for example, as shown in Figure 1. The demodulation circuit DM then outputs a demodulated digital data signal DOUT, obtained by demodulating the second encoded signal based on the transmission signal DMIN, and / or input attribute information, in synchronization with the second clock signal CK2.

[0033] For example, as shown in Figure 2 described later, the demodulation circuit DM, in the second encoded signal EOUT (i.e., the transmission signal DMIN), if the two bits of data before and after the two bits of rewritten data "LL" of a predetermined value rewritten by the aforementioned high-speed feedback encoder FFB are considered the first data and the second data, respectively, then if the polarity (value) of the first data and the polarity (value) of the second data are equal, the input attribute information ZIN determines that the input analog signal VIN exhibits the second attribute of being an over-input signal, and outputs demodulation attribute information ZOUT according to this determination result.

[0034] Furthermore, as shown in Figure 3 described later, in this first embodiment, the first data sequence of the second encoded signal EOUT, which is encoded by the edge encoder EN from the digital data signal ΔΣ corresponding to the input attribute information ZIN indicating the first attribute, and the second data sequence of the second encoded signal EOUT, which is encoded by the edge encoder EN from the digital data signal ΔΣ corresponding to the input attribute information ZIN indicating the second attribute, may be the same.

[0035] In this case, the demodulation circuit DM outputs a demodulated digital data signal DOUT, which is demodulated as the data sequence of the input analog signal VIN of the normal data signal, based on the data sequence of the transmission signal corresponding to the second encoded signal EOUT of the second data sequence (i.e., it outputs the data corresponding to the excessive input signal as the data of the normal data signal).

[0036] Furthermore, as shown in Figure 4 described later, in this embodiment, the demodulation circuit DM outputs an error signal DMS if it determines that a transmission error has occurred due to a malfunction of the isolator 100 or the like, based on the transmission signal DMIN corresponding to the second encoding signal EOUT.

[0037] As described later, the first clock signal CK1, which defines the operation of the ΔΣ modulated analog-to-digital converter C1 and the high-speed feedback encoder FFB, is synchronized with the second clock signal CK2, which defines the operation of the demodulation circuit DM.

[0038] As a result, the operation of the ΔΣ modulated analog-to-digital converter C1 and the high-speed feedback encoder FFB is synchronized with the operation of the demodulation circuit DM.

[0039] [control circuit] The control circuit CON receives the error signal DMS output by the demodulation circuit DM. In response to this error signal DMS, the control circuit CON performs control operations such as cutting the power supply to the secondary circuit 102 to stop the output of the isolator 100.

[0040] [Digital-to-analog converter] The digital-to-analog converter C2 receives the demodulated digital data signal DOUT as input. The digital-to-analog converter C2 then converts the demodulated digital data signal DOUT into a demodulated analog signal AOUT and outputs it.

[0041] [Low-pass filter] The low-pass filter (LPF) receives the demodulated analog signal AOUT as input. The LPF then removes harmonics from the demodulated analog signal AOUT, reconstructs the input analog signal VIN that was input to the primary circuit 101, and outputs it as the differential output of the secondary circuit 102.

[0042] Furthermore, the low-pass filter (LPF) receives the demodulation attribute information ZOUT signal output by the demodulation circuit (DM) as input.

[0043] For example, in the case of a low-pass filter (LPF), if the demodulation attribute information ZOUT indicates the first polarity "H" which is the second attribute, the common-mode potential of the differential output signal VOUT of the low-pass filter (LPF) is raised higher than usual to transmit information about the excessive input signal to a subsequent CPU or other device.

[0044] On the other hand, when the demodulation attribute information ZOUT of the low-pass filter (LPF) is the second polarity "L" indicating the first attribute, the LPF sets the common-mode potential of the differential output signal VOUT of the low-pass filter to the normal potential and transmits information to the subsequent CPU or other device indicating that it is a normal data signal.

[0045] [Clock signal generation circuit] The clock signal generation circuit W generates and outputs a second clock signal CK2. This second clock signal CK2 generated by the clock signal generation circuit W is supplied to the demodulation circuit DM.

[0046] This second clock signal CK2 is then transmitted from the secondary circuit 102 to the primary circuit 101 as the first clock signal CK1 via the second pulse transmitting circuit QX, the transformer QT (inductors QIX, QIY), and the second pulse receiving circuit QY.

[0047] Therefore, as previously described, the first clock signal CK1, which defines the operation of the ΔΣ modulated analog-to-digital converter C1 and the high-speed feedback encoder FFB, is synchronized with the second clock signal CK2, which defines the operation of the demodulation circuit DM.

[0048] In other words, the operation of the ΔΣ modulated analog-to-digital converter C1 and the high-speed feedback encoder FFB is synchronized with the operation of the demodulation circuit DM.

[0049] [Isolator behavior] Next, an example of the operation of the isolator 100 having the above configuration will be described. Here, Figure 2 is a diagram showing an example of a signal waveform in the isolator shown in Figure 1.

[0050] For example, as shown in Figure 2, when the input attribute information ZIN indicates the first attribute "L", the input analog signal VIN is not an excessive input signal, but rather a normal data signal within the input range of the ΔΣ modulated analog-to-digital converter C1.

[0051] In a high-speed feedback encoder (FFB), the digital data signal ΔΣ is converted to 2 bits, and a first encoded signal FOUT, where P and N are represented here, is output.

[0052] In this case, if the digital data signal ΔΣ is of the first polarity "H", then the 2 bits of data PN in the first encoded signal FOUT are converted to the first polarity "HL". On the other hand, if the digital data signal ΔΣ is of the second polarity "L", then the 2 bits of data in the first encoded signal FOUT are converted to the second polarity "LH".

[0053] As mentioned above, the first encoded signal FOUT output by the high-speed feedback encoder FFB consists of two bits, PN, and is listed in a specific order.

[0054] The edge encoder EN then edge-encodes this first encoded signal FOUT and outputs a 2-bit second encoded signal EOUT of PN.

[0055] Then, the first pulse transmitting circuit SX flows currents with different polarities between the P terminal and N terminal of inductor IX, depending on the polarity of the 2-bit second encoded signal EOUT. Then, the first pulse receiving circuit SY outputs a 2-bit transmission signal DMIN based on the change in the polarity of the current flowing through inductor IY, which corresponds to the difference in the polarity of the current in inductor IX.

[0056] On the other hand, as shown in Figure 2, when the input attribute information ZIN indicates the second attribute, i.e., the first polarity "H", that is, when the input analog signal VIN is outside the input range of the ΔΣ modulated analog-to-digital converter C1, and is a so-called over-input signal, the high-speed feedback encoder FFB performs a special encoding.

[0057] For example, at time 13CK in Figure 2, when the input attribute information ZIN becomes the first polarity "H" indicating the second attribute, the high-speed feedback encoder FFB outputs data converted to, for example, "HL" (or "LH") as described above. Thereafter, every other clock cycle of the first clock signal CK1, the data of the digital data signal ΔΣ is rewritten to the rewritten data "LL" and output (times 14CK, 16CK, 18CK, and 20CK in Figure 2).

[0058] The high-speed feedback encoder (FFB) then converts the data of the non-rewritable digital data signal ΔΣ, which is every other clock cycle of the clock signal CK1, into "HL" (or "LH") and outputs it (at times 15CK, 17CK, and 19CK in Figure 2).

[0059] To identify the rewritten data "LL" as described above, the first encoded signal FOUT requires 2 bits.

[0060] For example, when the data of the second encoded signal EOUT becomes "LL" in accordance with the data of the first encoded signal FOUT becoming "LL", the first pulse transmission circuit SX of the isolated transmission circuit S does not output current for one cycle of the first clock signal CK1.

[0061] Then, the demodulation circuit DM of the secondary circuit 102 receives a second clock signal CK2 with the same period as the first clock signal CK1. Therefore, the demodulation circuit DM determines that the data "LL" has been input if no pulse signal is input for one period of the second clock signal CK2.

[0062] Here, for example, as shown in Figure 2, from the beginning until time 12CK, the data of the digital data signal ΔΣ is converted according to the above rule and output to the first encoded signal FOUT. From time 13CK onwards, when the input attribute information ZIN becomes the first polarity "H" indicating the second attribute, the output becomes a repetition of the data of the digital data signal ΔΣ and the rewritten data "LL".

[0063] JPEG2026057440000002.jpg27163

[0064] JPEG2026057440000003.jpg43163

[0065] Here, the first pulse transmission circuit SX outputs a current signal to the transformer T in accordance with the P and N terminal signals of the second encoded signal EOUT, which is edge-encoded from the first encoded signal FOUT, when the input attribute information ZIN is data "L" indicating the first attribute.

[0066] On the other hand, the first pulse transmission circuit SX outputs a current signal to transformer T with a one-data interval when the input attribute information ZIN is the data "H" indicating the second attribute, but does not output current to transformer T for the remaining half, i.e., when the P and N terminals of the output of the first pulse transmission circuit SX are "LL".

[0067] Assuming that transmission from the first pulse transmitting circuit SX to the first pulse receiving circuit SY takes one clock cycle, in addition to this one clock cycle period for transmission, the demodulation circuit DM outputs the demodulated digital data signal DOUT and demodulated attribute information ZOUT with a delay of three clock cycles of the second clock signal CK2. This is because the demodulation circuit DM requires data from a continuous period of three clock cycles to determine the demodulated attribute information ZOUT.

[0068] JPEG2026057440000004.jpg21163

[0069] As previously described, when the input attribute information ZIN is the data "L" indicating the first attribute, current is output to the transformer T for each pulse of the first clock signal CK1, according to the data of the digital data signal ΔΣ, for each clock cycle of the clock signal CK1. To reduce power consumption, it is effective to reduce the number of times current is output to the transformer T.

[0070] As previously described, the isolator 100 has a transmission system that includes an edge encoder EN between the high-speed feedback encoder FFB and the isolated transmission circuit S.

[0071] The ΔΣ digital data signal output by the ΔΣ modulated analog-to-digital converter C1 consists of "L" data up to the second data from the left (time 2CK), followed by eight consecutive "H" data from the third data from the left (time 3CK), and then "L" for the 11th and 12th data (times 11CK and 12CK). At this time, the data of the input attribute information ZIN is "L" of the second polarity.

[0072] Next, the digital data signal ΔΣ will be "H" for eight consecutive periods, from the 13th (time 13CK) to the 20th (time 20CK). At this time, the data of the input attribute information ZIN is the first polarity "H". When the data of the input attribute information ZIN is the first polarity "H", the high-speed feedback encoder FFB converts the digital data signal ΔΣ into a first encoded signal FOUT, in which the 2-bit data and the rewritten data "LL" signal appear alternately. Therefore, the data is not converted by the edge encoder EN (i.e., the edge encoder EN outputs the data of the first encoded signal FOUT as the second encoded signal EOUT without converting it).

[0073] On the other hand, when the input attribute information ZIN is the data "L" which indicates the first attribute, the high-speed feedback encoder FFB simply converts the digital data signal ΔΣ into 2-bit data, and the continuous data sequence is maintained. The edge encoder EN sends data only when there is a data transition.

[0074] Here, we will detail the data transformation from the second data point (time CK2) to the fourth data point (time CK4) in Figure 2.

[0075] As shown in Figure 2, the second (CK2) to fourth (CK4) data points of the first encoded signal FOUT output by the ΔΣ modulated analog-to-digital converter C1 are consecutive at the P and N terminals, with data "LH" followed by data "HL" and "HL".

[0076] Then, the second data (time CK2) to the fourth data (time CK4) of the second encoded signal EOUT output by the edge encoder EN will have consecutive data of "LL," so at the P and N terminals, the data will be "LL" followed by "HL" and then "LL."

[0077] The second data (CK2) of the second encoded signal EOUT becomes "LL" because the second data (time CK2) of the digital data signal ΔΣ is the same data as the first data.

[0078] The fact that the eighth data point from the left (time CL8) of the second encoded signal EOUT output by the edge encoder EN is "HL" is due to considerations of the refresh operation.

[0079] In the example shown in Figure 2, the refresh period M is set to 6 cycles of the first clock signal CK1 for illustrative purposes. The refresh period M represents the number of cycles of each data signal, i.e., the number of clock cycles of the first clock signal CK1.

[0080] The edge encoder EN refresh operation is performed when the same data is processed consecutively, and the second encoding signal EOUT during the refresh is the same signal as the first encoding signal FOUT at that time.

[0081] On the other hand, when the excessive input signal shown in Figure 2 is input (time 13CK~20CK), if the data of the digital data signal ΔΣ remains "H", the second encoded signal EOUT will alternately output the same data, in this case the data "HL", and the rewritten data "LL".

[0082] Then, in the second encoded signal EOUT (i.e., the transmission signal DMIN), if the two bits of data before and after the two bits of rewritten data "LL" of a predetermined value rewritten by the aforementioned high-speed feedback encoder FFB are considered the first data and the second data, respectively, the demodulation circuit DM determines that the input analog signal VIN exhibits the second attribute of being an over-input signal, based on the polarity (value) of the first data and the polarity (value) of the second data, and outputs demodulation attribute information ZOUT according to this determination result.

[0083] Thus, unless the refresh operation cycle M is set to 2 clocks, the refresh operation will not be performed, and therefore, the data "L" of the input attribute information ZIN, i.e., the data when a normal data signal is input, and the data "H" of the input attribute information ZIN, i.e., the data when an excessive input signal is input, will not be confused.

[0084] JPEG2026057440000005.jpg42163

[0085] JPEG2026057440000006.jpg15161

[0086] First, in the case of a normal data signal where the input attribute information ZIN is the data "L" indicating the first attribute, the digital data signal ΔΣ is simply converted to 2 bits by the high-speed feedback encoder FFB, so the data sequence of the first encoded signal FOUT becomes "HL", "HL", "LH".

[0087] The edge encoder EN converts consecutive identical data into "LL," so the data sequence of the second encoded signal EOUT output by the edge encoder EN becomes "HL," "LL," and "LH."

[0088] On the other hand, even in the case of an excessive input signal where the input attribute information ZIN data is of the first polarity "H", the digital data signal ΔΣ is converted to 2 bits by the high-speed feedback encoder FFB. However, in this case, the high-speed feedback encoder FFB forcibly inserts the data "LL" at intervals of one clock cycle of the first clock signal CK1. Therefore, the data sequence of the first encoded signal FOUT becomes "HL", "LL", "LH".

[0089] Then, in the edge encoder EN, since there are no consecutive identical data points, they are output as is, and the data sequence of the second encoded signal EOUT becomes "HL", "LL", and "LH".

[0090] Thus, these two data sequences of the second encoded signal EOUT contain the same data. However, one data sequence is the data sequence when the input attribute information ZIN is in the second polarity "L" indicating the first attribute, while the other data sequence is the data when the input attribute information ZIN is in the first polarity "H" indicating the second attribute. It is not possible to determine the attribute of the input analog signal VIN from these data sequences.

[0091] As previously mentioned, the attribute of the input analog signal VIN indicates the presence or absence of an overloaded input signal. However, if it is not possible to determine whether the input analog signal VIN is an overloaded input signal, it becomes difficult to promptly transmit the attribute indicating an overloaded input signal to the CPU or other devices connected downstream of the isolator 100.

[0092] Thus, when FFB encoding, which transmits information about the attributes of excessive input signals at high speed, and edge encoding, which enables low power consumption, are connected in series, it becomes impossible to determine whether or not excessive input signal information is present for certain input data.

[0093] Therefore, in this first embodiment, as described later, if there is excessive input information, i.e., attribute information that cannot be identified, the system is set in advance to prioritize specific attribute information.

[0094] In this first embodiment, if attribute information is defined as the presence or absence of an overload input, the preferred attribute information is set to the absence of an overload input signal (first attribute). As a result, a difference occurs between the digital data signal ΔΣ output by the ΔΣ modulated analog-to-digital converter C1 and the demodulated digital data signal DOUT demodulated by the demodulation circuit DM only when the analog signal VIN is an overload input signal (second attribute). In that case, since the input analog signal VIN is an overload input signal, it is considered that there is little need to correctly transmit the information of the digital data signal ΔΣ.

[0095] Here, Figure 4 shows an example of how the demodulation circuit determines the type of data sequence of the second encoded signal (transmission signal) and the attributes of the input analog signal corresponding to that data sequence.

[0096] JPEG2026057440000007.jpg20161

[0097] Under these conditions, the demodulation circuit DM can determine, based on the transmission signal DMIN, that the input analog signal VIN is a normal data signal within the range of the ΔΣ modulated analog-to-digital converter C1 and is not an over-input signal.

[0098] JPEG2026057440000008.jpg27161

[0099] JPEG2026057440000009.jpg21161

[0100] JPEG2026057440000010.jpg39161

[0101] The data sequence of the digital data signal ΔΣ under these conditions is, for example, "LLHHLLHH...". However, this data sequence occurs when the input analog signal VIN is 0. Therefore, this digital data signal ΔΣ data sequence occurs frequently.

[0102] If this data sequence is identified as an overloaded input signal, the system will frequently shut down, making it impractical. Furthermore, when an overloaded input signal is present, the data of the digital data signal ΔΣ is likely to be stuck on one of the polarities. Therefore, when an overloaded input signal is present, the likelihood of the polarity of the data in the digital data signal ΔΣ reversing is low.

[0103] In an ideal ΔΣ modulated analog-to-digital converter C1 with a stable response, the data polarity will not be reversed when an excessive input signal is input. However, if the input of an excessive input signal temporarily causes a polarity reversal of the data (at time 15CK in Figure 3), this reversal will delay the detection of the excessive input. On the other hand, as shown in Figure 3, the delay until the detection of the excessive input signal is limited to a few clock cycles, so it can be argued that there will be no major problems due to the delay in detecting the excessive input signal.

[0104] Next, in the case where the data sequence type shown in Figure 4 is "Inter-data LL transmission (2)", the number of consecutive LL transmissions N is less than the number of refresh cycles M which is 2 or more. In this case, since there are 2 or more LL transmissions, there is no judgment of an excessive input signal.

[0105] JPEG2026057440000011.jpg19160

[0106] Next, in the case where the data sequence type shown in Figure 4 is "inter-data LL transmission (3)", this is when the number of consecutive LL transmissions N is equal to the refresh period M which is 2 or more. In this case, since there are 2 or more LL transmissions, there is no judgment of an excessive input signal. However, the demodulation circuit DM may be either polarity inversion or refresh of a normal data signal, but both are within the category of a normal data signal and are therefore judged as a normal data signal.

[0107] Next, in the case where the data sequence type shown in Figure 4 is "Inter-data LL transmission (4)", this occurs when the number of consecutive LL transmissions N is greater than the refresh cycle M, which is set to 2 or more. In this case, since there are two or more LL transmissions, there is no judgment of an excessive input signal, and the refresh cycle M has also passed. Therefore, the demodulation circuit DM determines that there is an abnormality on the data transmission side. Here, the demodulation circuit DM determines that the power is off because no data is being transmitted.

[0108] JPEG2026057440000012.jpg26160

[0109] As described above, the isolator 100 according to this first embodiment performs pulse transmission with encoding of an over-input signal, which is advantageous for low power consumption. Furthermore, the isolator 100 reduces the delay of signal transmission by making a rational judgment for data sequences in which it is not possible to distinguish between encoding and edge encoding for determining an over-input signal.

[0110] In other words, according to the isolator 100 of the first embodiment, it is possible to reduce signal transmission delay while reducing power consumption.

[0111] (Second embodiment) In the first embodiment described above, an example of an isolator configuration was explained. However, the isolator configuration is not limited to this. Therefore, in this second embodiment, an isolator configuration is described that reduces the delay in the determination of an excessive input signal (demodulation of demodulation attribute information indicating the second attribute) in the demodulation circuit when the input analog signal VIN is detected as an excessive input signal.

[0112] Figure 5 shows an example of the configuration of the isolator according to the second embodiment. Figure 6 shows an example of the signal waveform in the isolator shown in Figure 5. In the description of the isolator according to this second embodiment, components that are denoted by the same reference numerals as in the first embodiment will not be described.

[0113] As shown in Figure 5, the isolator 200 according to the second embodiment further includes a data rewriting circuit R in the primary circuit 101a, compared to the isolator 100 shown in Figure 1 described above.

[0114] The data rewriting circuit R is located between the ΔΣ modulated analog-to-digital converter C1 and the high-speed feedback encoder FFB, as shown in Figure 5, for example.

[0115] This data rewriting circuit R rewrites a portion of the data in the digital data signal ΔΣ output by the Σ-modulated analog-to-digital converter C1 according to the input attribute information ZIN, and outputs it to the high-speed feedback encoder FFB.

[0116] For example, this data rewriting circuit R outputs the input digital data signal ΔΣ directly to the high-speed feedback encoder FFB when the input attribute information ZIN indicates that the input analog signal VIN is a normal data signal (the first attribute).

[0117] On the other hand, the data rewriting circuit R is configured such that when the input attribute information ZIN indicates that the input analog signal VIN is an over-input signal, and the data sequence of the digital data signal ΔΣ contains data that has been temporarily inverted from the first polarity "H" to the second polarity "L", it rewrites the polarity of the inverted data from the second polarity "L" to the first polarity "H".

[0118] Here, the ΔΣ modulated analog-to-digital converter C1 outputs a digital data signal ΔΣ of first polarity "H" when the input attribute information ZIN indicates that the input analog signal VIN is a positive over-input signal.

[0119] However, for example, as shown in Figure 6 at time 15CK, if the input attribute information ZIN is first polarity "H" indicating the second attribute that the input analog signal VIN is an over-input signal, then due to a design problem of the ΔΣ modulated analog-to-digital converter C1, the data sequence of the digital data signal ΔΣ (D i ~D i+3 Data D, which temporarily reversed from the first polarity "H" to the second polarity "L" in the above case. i+2 It may contain

[0120] When this input attribute information ZIN is the first polarity "H" indicating the second attribute, the inversion of the polarity of the digital data signal ΔΣ is not a desired operation for the ΔΣ modulated analog-to-digital converter C1.

[0121] Furthermore, when the input analog signal VIN is an over-input signal, that is, when the data of the input attribute information ZIN is the first polarity "H" indicating the second attribute, and the data of the digital data signal ΔΣ is fixed at "H", then unless the refresh period M is set to 2, this data sequence indicates an over-input signal, that is, it is the data sequence when the data of the input attribute information ZIN is the first polarity "H" indicating the second attribute. Note that the period M is not normally set to 2.

[0122] Furthermore, when the input attribute information ZIN data is "H" (high) indicating the second attribute, and the digital data signal ΔΣ data is fixed at "L", this data sequence represents an overloaded input signal, i.e., the data sequence when the input attribute information ZIN data is "H" (high) indicating the second attribute, unless the refresh period M is set to 2. Here, "L" fixed signifies a negative overloaded input.

[0123] Here, as shown in Figure 6, depending on the design of the ΔΣ modulated analog-to-digital converter C1, the digital data signal ΔΣ may not be fixed to "H" or "L" even when the input attribute information ZIN data is of the first polarity "H". In this case, when the transmission signal DMIN is observed in the demodulation circuit DM, the input attribute information ZIN data may be of either the first polarity "H" or the second polarity "L".

[0124] To avoid this possibility, in this second embodiment, when an excessive input signal is detected, that is, when the data of the input attribute information ZIN is of the first polarity "H", the digital data signal ΔΣ is fixed for the duration that the data of the input attribute information ZIN remains "H". As a result, the demodulation circuit DM can demodulate the demodulation attribute information corresponding to the input attribute information ZIN indicating the presence or absence of an excessive input, as shown in Figure 6, based on the transmission signal DMIN, which corresponds to the second encoded signal EOUT shown in Figure 6.

[0125] As shown in Figure 6, if the data of the digital data signal ΔΣ changes from "H" to "L" on the third clock cycle (time CK15) after the detection of an excessive input signal, and the data becomes "H" from the fourth clock cycle (time CK16) onward, that is, the data rewriting of the digital data signal ΔΣ in this second embodiment is applied.

[0126] JPEG2026057440000013.jpg20160

[0127] At the P terminal of the output of the second encoded signal EOUT, both ends of the data "L" are "H", and the demodulation circuit DM can determine the excessive input signal based on the transmission signal DMIN corresponding to the second encoded signal EOUT and demodulate the demodulation attribute information ZOUT.

[0128] As described above, as shown in Figure 6, if the data on both sides of the predetermined value data "LL" of the 2-bit second encoded signal EOUT are the same value, the input attribute information ZIN is uniquely determined. Using this point, when the input attribute information is determined to be a second attribute indicating an over-input signal, the input analog signal VIN is fixed to the data of the digital data signal ΔΣ at that time until the state of being an over-input signal ends.

[0129] This allows the demodulation circuit DM to uniquely determine the input attribute information. In this case, the data of the digital data signal ΔΣ is intentionally changed, but the data of the digital data signal ΔΣ when the input signal is excessive can be set to a fixed value. Therefore, it is considered that there are no problems caused by changing the data of the digital data signal ΔΣ.

[0130] Furthermore, the other configurations and operations of the isolator 200 in this second embodiment are the same as those of the isolator 100 in the first embodiment.

[0131] In other words, according to this second embodiment of the isolator, it is possible to reduce signal transmission delay while simultaneously reducing power consumption.

[0132] (Third embodiment) Figure 7 shows an example of a specific configuration of the data rewriting circuit R of the isolator 200 shown in Figure 5. Note that the data rewriting circuit R shown in Figure 7 is an example of a configuration of the data rewriting circuit R applied to the isolator 200 according to the second embodiment described above, and is not limited to this.

[0133] For example, as shown in Figure 7, the data rewriting circuit R comprises a selector SE, two flip-flops FF1 and FF2, and a delay circuit DE.

[0134] The input attribute information ZIN output by the attribute signal detection circuit DX is input to the flip-flop FF2 of the data rewriting circuit R. The flip-flop FF2 then converts the input attribute information ZIN into attribute signal information ZFF2 synchronized with the first clock signal CK1 output from the second pulse receiving circuit QY, and outputs it.

[0135] The delay circuit DE outputs a clock signal, which is a delayed version of the first clock signal CK1, to the flip-flop FF1.

[0136] The flip-flop FF1 converts the signal selected and output by selector SE into a signal synchronized with the clock signal output from delay circuit DE, and then outputs it.

[0137] The selector SE selects and outputs either the current digital data signal ΔΣ(A) or the digital data signal (B) output by the flip-flop FF1 half a clock ago, according to the attribute signal information ZFF2.

[0138] For example, if the attribute signal information ZFF2 = "L", selector SE selects and outputs the current digital data signal ΔΣ.

[0139] On the other hand, if the attribute signal information ZFF2 = "H", the selector SE selects and outputs the digital data signal output by the flip-flop FF1 from 1 / 2 clock cycle ago.

[0140] The output signal OUT, which is output by the selector SE, the output of the data rewriting circuit R, is then input to the next stage high-speed feedback encoder FFB, as shown in Figure 5.

[0141] As previously described, the determination of the data sequence at the PN terminal of the second encoded signal EOUT is shown in Figure 4.

[0142] JPEG2026057440000014.jpg52160

[0143] (Fourth embodiment) FIG. 8 is a diagram showing an example of a specific configuration of the demodulation circuit of the isolator shown in FIG. 5. Note that the demodulation circuit DM shown in FIG. 8 is an example of the configuration of the demodulation circuit DM applied to the isolator 200 according to the above-described second embodiment, and is not limited thereto.

[0144] For example, as shown in FIG. 8, the demodulation circuit DM includes a data demodulation unit DMU and an attribute information demodulation unit ZMU.

[0145] Then, as shown in FIG. 8, the transmission signals DMIN (DMINP, DMINM) output by the first pulse reception circuit SY are separately input to the data demodulation unit DMU and the attribute information demodulation unit ZMU.

[0146] The data demodulation unit DMU uses, for example, edge encoding demodulation that makes the data the same as the previous data if the transmission signal DMIN (DMINP, DMINM) is "LL". Alternatively, the data demodulation unit DMU may use signal interpolation technology for the decimated signal as the "LL" of the transmission signal DMIN (DMINP, DMINM) to reproduce the signal.

[0147] JPEG2026057440000015.jpg20160

[0148] In FIG. 8, when the current outputs of the first pulse reception circuit SY are DMINP and DMINM, the outputs of the flip-flops FF1a and FF2a are the data z one CK before, respectively. -1 DMINP, z - represented by 1DMINM, and the outputs of the flip-flops FF3a and FF4a are the data z two CK before, respectively. -2 DMINP, z -2 represented by DMINM.

[0149] The data z one CK before -1 DMINP, z -1DMINM needs to detect cases where both are "L" and the current data and the data from 2CK before are not "LL" but have the same sign, i.e., "HL" or "LH". Therefore, the AND gate 3AND1 detects "HL-LL-HL" and outputs a signal corresponding to this detection. Furthermore, the AND gate 3AND2 detects "LH-LL-LH" and outputs a signal corresponding to this detection. Then, the OR circuit OR1 calculates the OR of the signals output by these AND circuits 3AND1 and 3AND2, thereby outputting demodulated attribute information ZOUT, which indicates attribute information related to the excessive input signal. For example, if the demodulation attribute information ZOUT=“H”, it is determined that an excessive input signal has been detected, and if the demodulation attribute information ZOUT=“L”, it is determined that a normal data signal is being input.

[0150] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0151] 100, 200 isolators C1 ΔΣ Modulated Analog-to-Digital Converter DX attribute signal detection circuit FFB High-Speed ​​Feedback Encoder EN Edge Encoder S isolated transmission circuit DM demodulation circuit CON control circuit LPF (Low-Pass Filter) C2 Digital-to-Analog Converter QX 2nd Pulse Transmitter Circuit QY 2nd pulse receiving circuit QT Transformer

Claims

1. It is an isolator, A ΔΣ modulated analog-to-digital converter receives an input analog signal and converts it into a digital data signal of a pulse train corresponding to the amplitude of the input analog signal, and outputs it. An attribute signal detection circuit detects the attributes of the input analog signal and outputs input attribute information relating to the attributes of the input analog signal. A high-speed feedback encoder that encodes the digital data signal based on the input attribute information and outputs a first encoded signal, An edge encoder that receives the first encoded signal as input, edge encodes the first encoded signal, and outputs a second encoded signal, An isolated transmission circuit having an insulating section where the input and output are electrically isolated, receiving the second encoded signal and outputting a transmission signal transmitted through the insulating section in accordance with the second encoded signal, The system includes a demodulation circuit that receives the transmission signal and outputs a demodulated digital data signal obtained by demodulating the second encoded signal based on the transmission signal, and / or the input attribute information. An isolator characterized by the following features.

2. The attribute signal detection circuit is, If the amplitude of the input analog signal is less than or equal to the over-threshold set based on the input range of the ΔΣ modulated analog-to-digital converter, input attribute information indicating that the input analog signal is normally an input to a data signal is output. On the other hand, if the amplitude of the input analog signal is greater than the over-threshold, input attribute information indicating that the input analog signal is an over-input signal (a second attribute) is output. The isolator according to feature 1.

3. If the first data sequence of the second encoded signal encoded by the edge encoder from the digital data signal corresponding to the input attribute information indicating the first attribute and the second data sequence of the second encoded signal encoded by the edge encoder from the digital data signal corresponding to the input attribute information indicating the second attribute are the same, The demodulation circuit outputs a demodulated digital data signal, which is demodulated as a data sequence of the input analog signal of the normal data signal, based on the data sequence of the transmission signal corresponding to the second encoded signal of the second data sequence. The isolator according to feature 1.

4. The first clock signal that defines the operation of the ΔΣ modulated analog-to-digital converter and the high-speed feedback encoder is synchronized with the second clock signal that defines the operation of the demodulation circuit. The isolator according to feature 1.

5. The aforementioned high-speed feedback encoder is When the input attribute information indicates the first attribute, a first encoded signal encoded according to the polarity of the data sequence of the digital data signal is output. On the other hand, if the input attribute information indicates the second attribute, a first encoded signal is output, which is encoded in such a way that a portion of the data in the data sequence of the digital data signal is forcibly rewritten with pre-set predetermined value data. The isolator according to feature 3.

6. The demodulation circuit, if the data before and after the rewritten data of the predetermined value are designated as the first data and the second data, determines that the input attribute information indicates the second attribute, which is an over-input signal, when the polarity of the first data and the polarity of the second data are the same, and outputs demodulation attribute information corresponding to this determination result. The isolator according to feature 5.

7. The system further comprises a data rewriting circuit positioned between the ΔΣ modulated analog-digital converter and the high-speed feedback encoder, which rewrites a portion of the data of the digital data signal output by the ΔΣ modulated analog-digital converter according to the input attribute information and outputs it to the high-speed feedback encoder. The aforementioned data rewriting circuit is When the input attribute information indicates a first attribute that the input analog signal is a normal data signal, the input digital data signal is output directly to the high-speed feedback encoder. On the other hand, if the input attribute information indicates a second attribute that the input analog signal is an over-input signal, and the data sequence of the digital data signal contains temporarily inverted data, the polarity of the inverted data is rewritten. The isolator according to feature 1.

8. The aforementioned isolated transmission circuit is In accordance with the second encoded signal, a transmission signal of pulses in a data sequence of data of first or second polarity synchronized with the first clock signal is transmitted, or a transmission signal that does not contain pulses is transmitted within a predetermined clock period defined by the first clock signal. The isolator according to feature 1.

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