Pseudo-synchronization detection device and digital receiver

Abstract

The present invention aims to provide a pseudo-synchronization detection device and a digital receiving device that can reduce the probability of false detection of a pseudo-synchronization state and improve the pull-in speed. [Solution] The pseudo-synchronous detection device 15 is provided in a digital receiving device 1A that receives a phase-shifted modulation signal Spsk transmitted by a digital transmitting device 2, and decodes data from the I signal Si and Q signal Sq obtained by synchronously detecting and demodulating the phase-shifted modulation signal Spsk. The pseudo-synchronous detection device 15 includes a pseudo-frequency correction unit 151 that corrects the frequency correction value fcrt2 detected based on the I signal Si and Q signal Sq to a frequency corresponding to the normal frequency when pseudo-synchronous detection occurs, and a pseudo-synchronous determination unit 152 that determines whether or not a pseudo-synchronous determination is necessary to determine whether or not a pseudo-synchronous state is in place using the decoded data.

Description

Technical Field

[0001] The present invention relates to a pseudo-synchronization detection device and a digital reception device used in a wireless communication system.

Background Art

[0002] Patent Document 1 discloses a technique for countermeasures against pseudo-synchronization in an automatic frequency control (AFC) function mounted on a receiver of a digital wireless communication system. Here, pseudo-synchronization refers to a state in which the reference oscillator of the receiver is corrected and locked at an incorrect frequency. In the technique disclosed in Patent Document 1, a pseudo-synchronization transformed synchronization word obtained by transforming a normal synchronization word into a sequence received during pseudo-synchronization is prepared, and when the correlation between the detected received data sequence and the pseudo-synchronization transformed synchronization word is detected, it is determined that the state is a pseudo-synchronization state, and countermeasures against pseudo-synchronization are taken by converting the frequency error detected by the AFC into a correct frequency correction value.

[0003] When the technique disclosed in Patent Document 1 detects a pseudo-synchronization state, it locks to the normal frequency by correcting the reference oscillator by converting the frequency correction value detected by the AFC into a correct frequency correction value. As a result, it is possible to eliminate a state in which the receiver falls into a pseudo-synchronization state during the pulling-in process at the start of communication and cannot communicate, and to improve the communication quality.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, conventional technology may, probabilistically, misdetect the correlation between the detected received data sequence and the pseudo-synchronous modified synchronization word, even when pseudo-synchronous conditions are not present, and incorrectly determine that a pseudo-synchronous state exists. If a pseudo-synchronous state is incorrectly determined when the signal is being pulled toward the normal frequency at the start of communication, the frequency correction value will deviate significantly from the normal frequency correction value. As a result, conventional technology suffers from the problem of slow pull-in speed until synchronization is detected.

[0006] The object of the present invention is to provide a pseudo-synchronization detection device and a digital receiving device that can reduce the probability of false detection of a pseudo-synchronization state and improve the pull-in speed. [Means for solving the problem]

[0007] To achieve the above objective, a pseudo-synchronous detection device according to one aspect of the present invention is a pseudo-synchronous detection device provided in a digital receiving device that receives a phase-shifted modulation signal transmitted by a digital transmitting device and decodes data from an I signal and a Q signal obtained by synchronously detecting and demodulating the phase-shifted modulation signal, and is characterized by comprising: a pseudo-frequency correction unit that corrects a frequency correction value detected based on the I signal and the Q signal to a frequency corresponding to the normal frequency at the time of pseudo-synchronous detection; and a pseudo-synchronous determination unit that determines whether or not a pseudo-synchronous determination is necessary to determine whether or not a pseudo-synchronous state is in place using the decoded data.

[0008] Furthermore, in order to achieve the above objective, a digital receiving device according to one aspect of the present invention is characterized by comprising: a receiving unit that receives a phase-shifted modulation signal transmitted by a digital transmitting device; a demodulation unit that synchronously detects the phase-shifted modulation signal and demodulates an I signal and a Q signal; a decoding unit that decodes data from the I signal and the Q signal; and a pseudo-synchronous detection device according to the above aspect. [Effects of the Invention]

[0009] According to each aspect of the present invention, the probability of falsely detecting a pseudo-synchronization state can be reduced and the pull-in speed can be improved. [Brief explanation of the drawing]

[0010] [Figure 1] This is a block diagram showing the schematic configuration of a pseudo-synchronization detection device and a digital receiving device according to a first embodiment of the present invention. [Figure 2] This diagram illustrates a pseudo-synchronization detection device and a digital receiving device according to a first embodiment of the present invention, and schematically shows the relationship between pseudo-synchronization determination and frequency correction value. [Figure 3] This is a block diagram showing the schematic configuration of a digital receiving device according to a second embodiment of the present invention. [Modes for carrying out the invention]

[0011] Each embodiment of the present invention illustrates an apparatus or method for embodying the technical concept of the present invention, and the technical concept of the present invention does not limit the materials, shapes, structures, arrangements, etc. of the components to those described below. The technical concept of the present invention can be modified in various ways within the technical scope defined by the claims described in the patent claims.

[0012] [First Embodiment] 1-1. Configuration of a digital receiving device: The schematic configuration of the pseudo-synchronous detection device and digital receiver according to the first embodiment will be described with reference to Figures 1 and 2. The digital receiver 1A according to this embodiment is a device that receives a phase-shifted modulation signal Spsk transmitted by the digital transmitter 2 and decodes data from the I signal and Q signal obtained by synchronous detection and demodulation of the phase-shifted modulation signal Spsk. The pseudo-synchronous detection device 15 according to this embodiment is a device provided in the digital receiver 1A. The digital receiver 1A transmits and receives data using a type of phase-shifted modulation called Quadrature Phase-Shift Keying (QPSK), which uses, for example, four phases.

[0013] Figure 1 is a block diagram illustrating the schematic configuration of the pseudo-synchronous detection device 15 and the digital receiver 1A according to this embodiment. In Figure 1, for ease of understanding, the digital receiver 1A and the digital transmitter 2 that transmits and receives the phase-shifted modulation signal Spsk are shown.

[0014] As shown in Figure 1, the digital receiver 1A according to this embodiment includes an antenna 11, a demodulation unit 12, a decoding unit 13, a synchronization word determination unit 14, and a pseudo-synchronization detection device 15 according to this embodiment. The antenna 11 corresponds to an example of a receiver that receives the phase-shifted modulation signal Spsk transmitted by the digital transmitter 2.

[0015] The demodulation unit 12 synchronously detects the phase-shifted modulated signal Spsk received by the antenna 11 and demodulates the I signal Si and the Q signal Sq. The demodulation unit 12 includes a local oscillator 121, a 90-degree phase shifter 122, mixers 123 and 124, and analog-to-digital converters 125 and 126. Hereinafter, "analog-to-digital" will be abbreviated as "A / D".

[0016] The local oscillator 121 oscillates a local signal at the same frequency (carrier frequency) as the carrier signal of the phase-shifted modulated signal Spsk received by the antenna 11. The output of the local oscillator 121 is connected to the input of the 90-degree phase shifter 122 and one of the inputs of the mixer 123. The local oscillator 121 outputs the oscillated local signal to the mixer 123 and the 90-degree phase shifter 122.

[0017] The 90-degree phase shifter 122 shifts the phase of the local signal oscillating from the local oscillator 121 by 90 degrees (π / 2). The output of the 90-degree phase shifter 122 is connected to one of the inputs of the mixer 124. The 90-degree phase shifter 122 outputs the local signal with a 90-degree phase shift to the mixer 124.

[0018] The other input of mixer 123 is connected to antenna 11. Mixer 123 multiplies the phase shift keying signal Spsk received by antenna 11 with the local signal input from local oscillator 121, and extracts the I signal Si. The output of mixer 123 is connected to the input of A / D converter 125. Mixer 123 outputs the extracted I signal Si to A / D converter 125.

[0019] The other input of mixer 124 is connected to antenna 11. Mixer 124 multiplies the phase shift keying signal Spsk received by antenna 11 with the signal input from 90-degree phase shifter 122 (i.e., a signal whose phase is shifted by 90 degrees with respect to the local signal), and extracts the Q signal Sq. The output of mixer 124 is connected to the input of A / D converter 126. Mixer 124 outputs the extracted Q signal Sq to A / D converter 126.

[0020] A / D converter 125 A / D-converts the I signal Si input from mixer 123 to generate I data Di1. The output of A / D converter 125 is connected to decoder section 13. A / D converter 125 outputs the generated I data Di1 to decoder section 13.

[0021] A / D converter 126 A / D-converts the Q signal Sq input from mixer 124 to generate Q data Dq1. The output of A / D converter 126 is connected to decoder section 13. A / D converter 126 outputs the generated Q data Dq1 to decoder section 13.

[0022] Decoder section 13 decodes the decoded data Dd from the I data Di1 and Q data Dq1 input from demodulation section 12. Also, decoder section 13 calculates a frequency correction value fcrt1 (details will be described later) based on the amount of change per unit time of the deviation from the normal phase of the received symbol data Xk, Yk (details will be described later). Decoder section 13 includes a phase correction section 131, a digital filter section 132, a symbol data acquisition section 133, a decoding processing section 134, and a frequency correction value detection section 135.

[0023] The phase correction unit 131 rotates and corrects the phases of I data Di1 and Q data Dq1 based on a frequency correction value fcrt2 (details to be described later) input from a pseudo-frequency correction unit 151 (details to be described later) provided in the pseudo-synchronous detection device 15. The phase correction unit 131 has an input unit (not shown) into which the frequency correction value fcrt2 is input, and two output units (not shown) that output I data Di2 and Q data Dq2 with the phases of I data Di1 and Q data Dq1 corrected. The phase correction unit 131 outputs the phase-corrected I data Di2 and Q data Dq2 to the digital filter unit 132.

[0024] The digital filter unit 132 removes unwanted frequency components from the I data Di2 and Q data Dq2 input from the phase correction unit 131 and outputs them to the symbol data acquisition unit 133.

[0025] The symbol data acquisition unit 133 includes a symbol clock regeneration unit (not shown) that regenerates a symbol clock signal indicating the sign switching timing (i.e., the zero-crossing point timing) of the I data Di3 and Q data Dq3 input from the digital filter unit 132. The symbol data acquisition unit 133 acquires received symbol data Xk based on the I data Di3 input from the digital filter unit 132 and the symbol clock signal generated by the symbol clock regeneration unit. The symbol data acquisition unit 133 acquires received symbol data Yk based on the Q data Dq3 input from the digital filter unit 132 and the symbol clock signal generated by the symbol clock regeneration unit. The symbol data acquisition unit 133 outputs the extracted received symbol data Xk and Yk to the decoding processing unit 134 and the frequency correction value detection unit 135, respectively.

[0026] The decoding processing unit (an example of a decoding unit) 134 detects the quadrant in which the received symbol data Xk,Yk input from the symbol data acquisition unit 133 are located, and determines the bit data corresponding to that quadrant. In this embodiment, when the modulation scheme is QPSK, the bit data is (0,0) when the received symbol data is in the first quadrant of the IQ coordinates, (0,1) when it is in the second quadrant, (1,1) when it is in the third quadrant, and (1,0) when it is in the fourth quadrant. The decoding processing unit 134 outputs the bit data as decoded data Dd to the synchronization word determination unit 14.

[0027] The frequency correction value detection unit 135 detects the frequency correction value fcrt1. The frequency correction value fcrt1 corresponds to the amount of frequency difference (frequency error) between the frequency of the local signal and the carrier frequency of the received signal. The frequency correction value detection unit 135 employs methods such as the Costas loop method or the inverse modulation method as AFC methods, but a method that estimates the amount of frequency difference from the change in the phase error of each symbol is easier to apply in digital signal processing. In this method, the phase that should be detected is determined from the quadrant of the detected symbol data, and the frequency error is determined from the change in the phase difference corresponding to the received symbol data with respect to the determined phase. In this embodiment, the phase correction unit 131, the frequency correction value detection unit 135, and the pseudo-frequency correction unit 151 realize AFC that automatically adjusts the deviation of the received frequency.

[0028] In this embodiment, the frequency correction value detection unit 135 detects a first frequency correction value fcrt1, which is the amount of frequency difference (frequency error) between the frequency of the local signal and the carrier frequency of the received phase-shifted modulation signal Spsk, based on the received symbol position obtained from the received symbol data Xk,Yk acquired by the symbol data acquisition unit 133 and the normal symbol position. The frequency correction value fcrt1 is detected based on the amount of change per unit time of the difference (phase shift) between the phase corresponding to the normal symbol position set in the quadrant where the received symbol data Xk,Yk exist and the phase corresponding to the received symbol position obtained from the received symbol data Xk,Yk.

[0029] The frequency correction value detection unit 135 calculates the frequency correction value fcrt1 based on the received symbol data Xk and Yk input from the symbol data acquisition unit 133. If there is a difference between the carrier frequency of the phase-shifted modulation signal Spsk transmitted from the digital transmitter 2 and the frequency of the local signal oscillated by the local oscillator 121, the phase error between the received symbol position and the normal symbol position increases or decreases with each symbol time. Therefore, if the symbol time is Ts and the phase error between the received symbol position and the normal symbol position is Δθ, the frequency correction value fcrt1 can be obtained by the following equation (1). fcrt1=Δθ / (2π×Ts) ···(1)

[0030] The synchronization word determination unit 14 performs both a normal synchronization determination and a pseudo-synchronization determination to determine whether the received signal is in a normal synchronization state. A normal synchronization state is a state in which the frequency of the received signal is correctly corrected and locked to the normal frequency (correct frequency). A pseudo-synchronization state is a state in which the frequency of the received signal is incorrectly corrected and locked to the wrong frequency. Therefore, in a normal synchronization state, the symbol data acquisition unit 133 acquires the received symbol position based on the normal phase error (i.e., the actual phase error) for the phase-shifted modulation signal Spsk received by the antenna 11. On the other hand, in a pseudo-synchronization state, the symbol data acquisition unit 133 acquires the received symbol position based on the wrong phase error for the phase-shifted modulation signal Spsk received by the antenna 11.

[0031] The synchronization word determination unit 14 performs normal synchronization determination and pseudo-synchronization determination using the decoded data Dd input from the decoded processing unit 134. In normal synchronization determination, the synchronization word determination unit 14 determines whether the decoded data Dd, which is the data decoded by the decoded processing unit 134, matches a predetermined normal synchronization word, and determines that normal synchronization is in effect if the decoded data Dd and the normal synchronization word match. In pseudo-synchronization determination, the synchronization word determination unit 14 determines whether the decoded data Dd matches a pseudo-synchronization-modified synchronization word, which is a modified version of the normal synchronization word, and determines that pseudo-synchronization is in effect if the pseudo-synchronization-modified synchronization word and the decoded data Dd match.

[0032] Incidentally, the digital transmitter 2 transmits a phase-shifted modulation signal Spsk, which includes a synchronization word, to the digital receiver 1A. Therefore, the decoded data Dd includes the decoded synchronization word (hereinafter sometimes referred to as the "decoded synchronization word"). On the other hand, the synchronization word determination unit 14 stores the regular synchronization word and a pseudo-synchronization-modified synchronization word which is a modified version of the regular synchronization word. Therefore, the synchronization word determination unit 14 can perform a synchronization determination by detecting the correlation between the regular synchronization word and the pseudo-synchronization-modified synchronization word and the decoded synchronization word. If the synchronization word determination unit 14 finds a correlation between the regular synchronization word and the decoded synchronization word, it determines that the digital receiver 1A is in a regular synchronization state. On the other hand, if the synchronization word determination unit 14 finds a correlation between the pseudo-synchronization-modified synchronization word and the decoded synchronization word, it determines that the digital receiver 1A is in a pseudo-synchronization state.

[0033] More specifically, the synchronization word, decoded synchronization word, normal synchronization word, and pseudo-synchronous modified synchronization word have a configuration in which a predetermined string is represented by multiple bits. The synchronization word determination unit 14 determines whether a correlation has been established between the bit sequence representing the normal synchronization word and the bit sequence representing the pseudo-synchronous modified synchronization word and the bit sequence representing the decoded synchronization word. If the synchronization word determination unit 14 determines that a correlation has been established between the normal synchronization word and the decoded synchronization word, it determines that the digital receiver 1A is in a normal synchronization state. On the other hand, if a correlation has been established between the pseudo-synchronous modified synchronization word and the decoded synchronization word, the synchronization word determination unit 14 determines that the digital receiver 1A is in a pseudo-synchronous state.

[0034] As described above, the synchronization word determination unit 14 is configured to perform both normal synchronization determination and pseudo-synchronization determination. However, if the pseudo-synchronization determination unit 152 (details described later) determines that pseudo-synchronization determination is unnecessary, the pseudo-synchronization determination unit 14 does not perform pseudo-synchronization determination. The synchronization word determination unit 14 does not perform pseudo-synchronization determination if it receives a pseudo-synchronization determination signal Psd (details described later) from the pseudo-synchronization determination unit 152, indicating that pseudo-synchronization determination is unnecessary. On the other hand, the synchronization word determination unit 14 performs pseudo-synchronization determination if it receives a pseudo-synchronization determination signal Psd from the pseudo-synchronization determination unit 152. As will be described in detail later, in the digital receiver 1A, pseudo-synchronization determination is deemed unnecessary if the frequency correction value fcrt2 based on the frequency correction value fcrt1 is a value that cannot result in a pseudo-synchronization state. This reduces the probability that the digital receiver 1A will be incorrectly determined to be in a pseudo-synchronization state even though it is in a normal synchronization state.

[0035] One of the two outputs of the synchronization word determination unit 14 is connected to a subsequent stage (not shown), and the other of the two outputs is connected to the pseudo-frequency correction unit 151 (details will be described later). If the synchronization word determination unit 14 determines that the system is in a normal synchronization state, it outputs the decoded data Dd as a decoded signal Ds to the subsequent stage. On the other hand, if the synchronization word determination unit 14 determines that the system is in a pseudo-synchronization state, it discards the decoded data Dd as invalid data and does not output the decoded signal Ds to the subsequent stage.

[0036] The synchronization word determination unit 14 outputs a pseudo-synchronization determination signal Ps to the pseudo-frequency correction unit 151 when it determines that a pseudo-synchronization state is present, and does not output a pseudo-synchronization determination signal Ps to the pseudo-frequency correction unit 151 when it determines that a normal synchronization state is present.

[0037] One of the two inputs of the pseudo-synchronization detection device 15 is connected to the output of the frequency correction value detection unit 135, and the other of the two inputs is connected to the other output of the synchronization word determination unit 14. The pseudo-synchronization detection device 15 includes a pseudo-frequency correction unit 151 and a pseudo-synchronization determination unit 152. One of the two inputs of the pseudo-frequency correction unit 151 is connected to the output of the frequency correction value detection unit 135, and the other of the two inputs is connected to the other output of the synchronization word determination unit 14.

[0038] 1-2. Configuration of the pseudo-synchronous detection device: The schematic configuration of the pseudo-synchronous detection device according to the first embodiment will be explained with reference to Figures 1 and 2. As shown in Figure 1, the pseudo-synchronization detection device 15 according to this embodiment includes a pseudo-frequency correction unit 151 and a pseudo-synchronization determination unit 152.

[0039] The pseudo-frequency correction unit 151 receives the frequency correction value fcrt1 from the frequency correction value detection unit 135. When pseudo-synchronization is detected in the synchronization word determination unit 14 (when pseudo-synchronization is detected), the pseudo-frequency correction unit 151 subtracts the maximum value of the frequency correction value detectable by AFC processing, Δf=1 / 4Ts, from the frequency correction value fcrt1 using a known method shown in Patent Document 1. If the frequency correction value fcrt1 is a positive value, it adds Δf=1 / 4Ts to the frequency correction value fcrt1 to generate a frequency correction value fcrt2 corresponding to the normal frequency. On the other hand, when normal synchronization is detected in the synchronization word determination unit 14 (when normal synchronization is detected), the pseudo-frequency correction unit 151 sets the frequency correction value fcrt1 to the frequency correction value fcrt2. The frequency correction value fcrt1 is detected using the received symbol data Xk and Yk. The received symbol data Xk and Yk are obtained from the I data Di3 and Q data Dq3 output from the digital filter unit 132. The I data Di3 and Q data Dq3 are generated based on the I signal Si and Q signal Sq, which are obtained by quadrature detection of the phase-shifted modulated signal Spsk transmitted by the digital transmitter 2 and received by the antenna 11, and converted into baseband signals. Therefore, the frequency correction value fcrt1 is based on the I signal Si and Q signal Sq.

[0040] Therefore, the pseudo-frequency correction unit 151 corrects the frequency correction value fcrt1 detected based on the I signal Si and Q signal Sq to a frequency equivalent to the normal frequency when pseudo-synchronous detection occurs. When pseudo-synchronous detection occurs, the pseudo-frequency correction unit 151 corrects the frequency correction value fcrt1 to generate a frequency correction value fcrt2. On the other hand, when pseudo-synchronous detection does not occur (i.e., when normal synchronous detection occurs), the pseudo-frequency correction unit 151 sets the frequency correction value fcrt1 to a frequency correction value fcrt2. When the pseudo-synchronous detection signal Ps is input from the synchronous word detection unit 14, the pseudo-frequency correction unit 151 determines that pseudo-synchronous detection has occurred and corrects the frequency correction value fcrt1 to a frequency equivalent to the normal frequency to generate a frequency correction value fcrt2.

[0041] The pseudo-synchronization determination unit 152 determines whether or not a pseudo-synchronization determination is necessary to determine whether or not a pseudo-synchronization state is in place. Specifically, the pseudo-synchronization determination unit 152 determines whether or not a pseudo-synchronization determination is necessary based on the frequency correction value fcrt2. In addition, the pseudo-synchronization determination unit 152 determines whether or not a pseudo-synchronization determination is necessary based on a threshold value based on the maximum oscillation frequency difference between a reference oscillator (not shown) provided in the digital transmitter 2 and a local oscillator 121 (an example of a reference oscillator) provided in the digital receiver 1A.

[0042] Here, we will explain the relationship between the threshold value and the frequency correction value used by the pseudo-synchronization determination unit 152 to determine whether pseudo-synchronization determination is necessary or not. Let "flim" be the maximum value of the frequency correction value detectable by the AFC processing in the digital receiver 1A. Let "fmax" be the maximum oscillation frequency difference between the local oscillator generated based on the reference oscillator provided in the digital transmitter 2 and the local oscillator (an example of a reference oscillator) 121 provided in the digital receiver 1A. Specifically, the maximum oscillation frequency difference fmax corresponds to the maximum value of the frequency deviation (frequency shift) that can occur between the local signal generated based on the reference oscillator provided in the digital transmitter 2 and the local signal oscillated by the local oscillator 121 provided in the digital receiver 1A. The maximum oscillation frequency difference fmax is determined by the specifications between the digital transmitter 2 and the digital receiver 1A (for example, the specifications of the communication system in which the digital receiver 1A is used). The relationship between the absolute value of the maximum oscillation frequency difference fmax |fmax| and the absolute value of the maximum value of the frequency correction value flim detectable by the AFC processing in the digital receiver 1A |flim| is given by equation (2) below. |fmax|<|flim| ···(2)

[0043] When digital receiver 1A is receiving a phase-shifted modulation signal Spsk transmitted from digital transmitter 2, let |fregular| be the absolute value of the actual frequency shift amount fregular (i.e., the frequency correction value detected in a normal synchronization state). Also, let |fpseudo| be the absolute value of the frequency shift amount fpseudo when a pseudo-synchronization state is detected due to a false detection despite the normal synchronization state. In this case, the relationship between the absolute value of the frequency shift amount fregular |fregular| and the absolute value of the frequency shift amount fpseudo |fpseudo| is given by equation (3) below. |fpseudo|=|flim|-|fregular| ···(3)

[0044] When digital receiver 1A is receiving a phase-shifted modulation signal Spsk transmitted from digital transmitter 2, the range of the absolute value of the frequency shift amount fregular that can be detected in a normally synchronized state is given by the following equation (4). 0≦|fregular|≦|fmax| (4)

[0045] Here, the range of the frequency deviation fpseudo that can be detected when locked to the pseudo-synchronization frequency (i.e., in a pseudo-synchronization state) is given by equation (5) below, from equations (3) and (4). |flim|-|fmax|≦fpseudo≦|flim| ···(5)

[0046] Here, equation (5) can be transformed into equation (5-1) when each absolute value is negative, and into equation (5-2) when each absolute value is positive. -flim≦fpseudo≦-(flim-fmax) ···(5-1) +(flim-fmax)≦fpseudo≦flim ···(5-2)

[0047] Frequency shifts satisfying equations (5-1) and (5-2) may be detected even in a pseudo-synchronous state. On the other hand, frequency shifts that do not satisfy equations (5-1) and (5-2) are detected only in a normal synchronous state and not in a pseudo-synchronous state. Therefore, "flim-fmax" on the right-hand side of equation (5-1) and the left-hand side of equation (5-2) become the threshold fth for determining whether or not a pseudo-synchronous determination is necessary. In other words, the threshold fth can be expressed by the following equation (6). fth = flim - fmax ... (6)

[0048] Therefore, substituting equation (6) into equations (5-1) and (5-2), we can express them as shown in equations (7-1) and (7-2) below. -flim≦fpseudo≦-fth (7-1) +fth≦fpseudo≦flim ···(7-2)

[0049] The range of frequency deviations that does not satisfy equations (5-1) and (5-2) is the range in which the frequency deviation fpseudo cannot be detected when locked to the pseudo-synchronization frequency, i.e., the undetectable range of the frequency deviation fpseudo.

[0050] The range of the frequency deviation fregular that does not satisfy equations (5-1) and (5-2) in a normally synchronized state can be expressed as shown in equation (8) below, and substituting equation (6) into equation (8) gives the following equation (9). -(flim-fmax) <fregular<+(flim-fmax)···(8) -fth <fregular<+fth ···(9)

[0051] When the digital receiver 1A is locked to the regular synchronization frequency, the frequency correction value fcrt1 output from the frequency correction value detection unit 135 corresponds to the frequency deviation amount fregular. When the digital receiver 1A is locked to the regular synchronization frequency, the frequency correction value fcrt2 output from the pseudo-frequency correction unit 151 is the same as the frequency correction value fcrt1 output from the frequency correction value detection unit 135. Therefore, when the digital receiver 1A is locked to the regular synchronization frequency, the frequency correction value fcrt2 output from the pseudo-frequency correction unit 151 corresponds to the frequency deviation amount fregular.

[0052] When the digital receiver 1A is locked to a pseudo-synchronous frequency, the frequency correction value fcrt1 output from the frequency correction value detection unit 135 corresponds to the frequency deviation amount fpseudo. When the digital receiver 1A is locked to a pseudo-synchronous frequency, the frequency correction value fcrt2 output from the pseudo-frequency correction unit 151 is the value obtained by correcting the frequency correction value fcrt1 output from the frequency correction value detection unit 135 to a frequency equivalent to the normal frequency. That is, in this case, the frequency correction value fcrt2 output from the pseudo-frequency correction unit 151 is the value obtained by correcting the frequency deviation amount fpseudo to a frequency equivalent to the normal frequency. Since there is a relationship between the frequency deviation amount fpseudo and the frequency deviation amount fregular given by equation (3), the value obtained by correcting the frequency deviation amount fpseudo to a frequency equivalent to the normal frequency corresponds to the frequency deviation amount fregular. For this reason, when the digital receiver 1A is locked to a pseudo-synchronous frequency, the frequency correction value fcrt2 output from the pseudo-frequency correction unit 151 corresponds to the frequency deviation amount fregular.

[0053] Therefore, the frequency shift amount fregular in equations (7-1) and (7-2), and the frequency shift amount fregular in equation (9) can be changed to the frequency correction value fcrt2, so equations (7-1), (7-2), and (9) can be expressed as equations (10), (11), and (12) below. -flim≦fcrt≦-fth (10) +fth≦fcrt≦flim ···(11) -fth <fcrt<+fth ···(12)

[0054] Figure 2 schematically shows the relationship between pseudo-synchronization determination and frequency correction value (i.e., frequency shift amount). The vertical axis shows the frequency correction value fcrt2 output from the pseudo-frequency correction unit 151. The value of the frequency correction value fcrt2 increases from bottom to top in Figure 2.

[0055] For example, when the oscillation frequency of the local oscillator in the digital transmitter 2 is used as the reference, the frequency deviation amounts fregular and fpseudo will be positive if the frequency of the local signal in the digital receiver 1A is lower than the oscillation frequency, and negative if the frequency of the local signal in the digital receiver 1A is higher than the oscillation frequency. Therefore, as shown in Figure 2, the maximum oscillation frequency difference fmax and the maximum value flim of the frequency correction value fcrt2 are symmetrical on the positive and negative sides, with "0" (the value when there is no frequency deviation) in between.

[0056] The range between the maximum oscillation frequency difference fmax, which is a positive value indicated as "+fmax" in Figure 2, and the maximum oscillation frequency difference fmax, which is a negative value indicated as "-fmax" in Figure 2, represents the range of possible frequency shifts between the digital transmitter 2 and the digital receiver 1A.

[0057] The range between the maximum oscillation frequency difference fmax of the frequency correction value fcrt2, which is a negative value indicated as "-fmax" in Figure 2, and the negative threshold fth, which is indicated as "-fth" in Figure 2, is the negative range that can take both the normal frequency and the pseudo-frequency. The range between the maximum oscillation frequency difference fmax of the frequency correction value fcrt2, which is a positive value indicated as "+fmax" in Figure 2, and the positive threshold fth, which is indicated as "+fth" in Figure 2, is the positive range that can take both the normal frequency and the pseudo-frequency. Range R1 is the range expressed by equation (10), and range R2 is the range expressed by equation (11). Therefore, if the frequency correction value fcrt2 output from the pseudo-frequency correction unit 151 is a value included in range R1 or range R2, pseudo-synchronization determination is required.

[0058] The range R3 between the positive threshold fth, indicated by "+fth" in Figure 2, and the negative threshold fth, indicated by "-fth" in Figure 2, is the range in which pseudo-frequency cannot be obtained. The range R3 is the range expressed by equation (12). Therefore, if the frequency correction value fcrt2 output from the pseudo-frequency correction unit 151 is a value included in the range R3, pseudo-synchronization determination becomes unnecessary.

[0059] Therefore, the pseudo-synchronization determination unit 152 compares the frequency correction value fcrt2 input from the pseudo-frequency correction unit 151 with the stored threshold value fth to determine whether pseudo-synchronization determination is necessary or not. Specifically, if the maximum value of the frequency correction value is flim, the maximum oscillation frequency difference is fmax, the frequency correction value is fcrt, and the threshold value is fth, then the threshold value is expressed by the above-mentioned equation (6), and the pseudo-synchronization determination unit 152 determines that pseudo-synchronization determination is unnecessary if the above-mentioned equation (12) is satisfied.

[0060] Furthermore, if the maximum value of the frequency correction value is flim, the maximum oscillation frequency difference is fmax, the frequency correction value is fcrt, and the threshold is fth, then the threshold is expressed by equation (6) above, and the pseudo-synchronization determination unit 152 determines that pseudo-synchronization determination is necessary if it satisfies equation (10) or equation (12) above.

[0061] The output of the pseudo-synchronization determination unit 152 is connected to the other of the two inputs of the synchronization word determination unit 14. If the pseudo-synchronization determination unit 152 determines that pseudo-synchronization determination is necessary, it outputs a pseudo-synchronization determination signal Psd to the synchronization word determination unit 14. On the other hand, if the pseudo-synchronization determination unit 152 determines that pseudo-synchronization determination is unnecessary, it does not output a pseudo-synchronization determination signal Psd to the synchronization word determination unit 14.

[0062] 1-3. Operation of the pseudo-synchronization detection device and the digital receiver: Next, an example of the operation of the pseudo-synchronous detection device and the digital receiver according to this embodiment will be explained again using Figure 1. The operation examples of the pseudo-synchronous detection device 15 and the digital receiver 1A will be explained below, using the synchronization detection of local signals and carrier signals as an example.

[0063] For example, in the i-th data decoding of the phase-shifted modulation signal Spsk which includes a synchronization word, the synchronization word determination unit 14 detects a match between the decoded synchronization word and the regular synchronization word contained in the decoded data Dd. As a result, the synchronization word determination unit 14 outputs the decoded data Dd as a decoded signal Ds to the next stage. In addition, the synchronization word determination unit 14 does not output a pseudo-synchronization determination signal Ps to the pseudo-frequency correction unit 151 in the i-th data decoding.

[0064] In the i-th data decoding, the pseudo-frequency correction unit 151 outputs the frequency correction value fcrt1 input from the frequency correction value detection unit 135 as the frequency correction value fcrt2 to the pseudo-synchronization determination unit 152 and the phase correction unit 131. In the i-th data decoding, the pseudo-synchronization determination unit 152 checks whether the frequency correction value fcrt2 input from the pseudo-frequency correction unit 151 satisfies any of equations (10), (11), or (12), and determines whether pseudo-synchronization determination is necessary or not. For example, if the pseudo-synchronization determination unit 152 determines that pseudo-synchronization determination is necessary because the frequency correction value fcrt2 satisfies equation (10), it outputs a pseudo-synchronization determination signal Psd to the synchronization word determination unit 14.

[0065] In the i-th data decoding, the pseudo-synchronization determination signal Psd is input from the pseudo-synchronization determination unit 152. Therefore, the synchronization word determination unit 14 performs both normal synchronization determination and pseudo-synchronization determination in the i+1th data decoding. The synchronization word determination unit 14 detects a match between the decoded synchronization word and the pseudo-synchronization-modified synchronization word contained in the decoded data Dd. As a result, the synchronization word determination unit 14 discards the decoded data Dd as invalid data and does not output the decoded signal Ds to the subsequent stage. In addition, the synchronization word determination unit 14 outputs the pseudo-synchronization determination signal Ps to the pseudo-frequency correction unit 151 in the i+1th data decoding.

[0066] In the (i+1)th data decoding, the pseudo-frequency correction unit 151 corrects the frequency correction value fcrt1 input from the frequency correction value detection unit 135 to a frequency corresponding to the normal frequency, and outputs the resulting frequency correction value fcrt2 to the pseudo-synchronization determination unit 152 and the phase correction unit 131. In the (i+1)th data decoding, the pseudo-synchronization determination unit 152 determines whether the frequency correction value fcrt2 input from the pseudo-frequency correction unit 151 satisfies any of equations (10), (11), or (12), and determines whether pseudo-synchronization determination is necessary or not. For example, if the pseudo-synchronization determination unit 152 determines that pseudo-synchronization determination is unnecessary because the frequency correction value fcrt2 satisfies equation (12), it does not output the pseudo-synchronization determination signal Psd to the synchronization word determination unit 14.

[0067] In the i+1th data decoding, since the pseudo-synchronization determination signal Psd is not input from the pseudo-synchronization determination unit 152, the synchronization word determination unit 14 performs a regular synchronization determination in the i+2nd data decoding and does not perform a pseudo-synchronization determination. The synchronization word determination unit 14 outputs the decoded data Dd as the decoded signal Ds to the next stage. Also, in the i+2nd data decoding, the synchronization word determination unit 14 does not output the pseudo-synchronization determination signal Ps to the pseudo-frequency correction unit 151.

[0068] Hereafter, the pseudo-synchronization detection device 15 and the digital receiver 1A operate in the same manner as the i-th data decoding, and based on the determination result of the pseudo-synchronization determination unit 152 regarding whether pseudo-synchronization determination is necessary or not, they output a pseudo-synchronization determination signal Psd to the synchronization word determination unit 14 as needed. In this way, the digital receiver 1A performs data decoding through synchronization detection of the local signal and the carrier signal each time a phase-shifted modulation signal Spsk is input.

[0069] In the data decoding operation through synchronization detection of local and carrier signals, when the pseudo-frequency correction unit 151 receives a pseudo-synchronization determination signal Ps (i.e., when the synchronization word determination unit 14 determines that a pseudo-synchronization state has been detected), it outputs a frequency correction value fcrt2 to the phase correction unit 131, which is obtained by correcting the frequency correction value fcrt1 to a frequency corresponding to the normal frequency, so that a normal synchronization word is detected in the next data decoding. The phase correction unit 131 corrects the phase of the I data Di1 and Q data Dq1 based on the frequency correction value fcrt2 in the next data decoding. As a result, the synchronization word determination unit 14 is more likely to determine that a normal synchronization state has been detected in the next data decoding. In other words, the digital receiver 1A is more likely to be locked to the normal synchronization frequency in the next data decoding.

[0070] Furthermore, if the pseudo-synchronization determination signal Psd is not input from the pseudo-synchronization determination unit 152, the synchronization word determination unit 14 will not perform a pseudo-synchronization determination in the next data decoding. As a result, the synchronization word determination unit 14 will no longer have the possibility of determining a pseudo-synchronization state, and will therefore have an even higher probability of determining a normal synchronization state in the next data decoding. In other words, the digital receiver 1A will have an even higher probability of being locked to the normal synchronization frequency in the next data decoding.

[0071] 1-4. Examples: Next, the pseudo-synchronization detection device and digital receiver according to the embodiment of this example will be described again using Figure 1. This embodiment will be described using the frequency stability standard of the Association of Radio Industries and Businesses (ARIB) standard number: ARIB STD-T61.

[0072] Table 1 shows the frequency stability specifications in the ARIB STD-T61 Common Specification for Fire and Emergency Digital Radio Systems. Thus, in the ARIB STD-T61 Fire and Emergency Digital Radio System, the frequency stability of each radio station is specified as a common specification.

[0073] [Table 1]

[0074] As shown in Table 1, when the base station acts as a receiving device, the frequency stability of the local signal emitted from the local oscillator installed at the base station is ±1.5 [ppm]. Furthermore, when the base station acts as the frequency reference for a mobile station, i.e., when the base station acts as a transmitting device, the frequency stability of the signal emitted from the local oscillator installed at the base station is ±0.2 [ppm].

[0075] As shown in Table 1, the frequency stability of a mobile station varies depending on the average power. When the average power of a mobile station is 1[W] or less and the mobile station acts as a receiver, the frequency stability of the local signal emitted from the local oscillator installed in the mobile station is ±2.5[ppm]. Furthermore, when the mobile station's frequency reference is set to follow that of a reference base station (a base station acting as a transmitting device), i.e., when the mobile station is a transmitting device and its average power is 1[W] or less, the frequency stability of the signal emitted from the local oscillator installed in the mobile station is ±2.3+A[ppm], where A is the frequency deviation of the reference base station.

[0076] When a mobile station with an average power exceeding 1[W] acts as a receiving device, the frequency stability of the local signal emitted from the local oscillator installed in the mobile station is ±1.5[ppm]. Furthermore, when a mobile station is used with its frequency reference following that of a reference base station (a base station acting as a transmitting device), i.e., when the mobile station is a transmitting device and its average power exceeds 1[W], the frequency stability of the signal emitted from the local oscillator installed in the mobile station is ±1.3+A[ppm], where A is the frequency deviation of the reference base station.

[0077] Thus, the frequencies of signals transmitted by base stations and mobile stations will vary within the range that satisfies the frequency stability requirements shown in Table 1. Therefore, depending on the combination of base stations and mobile stations used as transmitters and receivers, different frequency shifts may occur between the carrier signal of the transmitter and the local signal of the receiver.

[0078] Tables 2 and 3 show the range of frequency shift (range of maximum oscillation frequency difference fmax) that occurs between the carrier signal of a transmitting device and the local signal of a receiving device when the frequency stability of a base station and a mobile station is defined as shown in Table 1, and the base station and mobile station are used as either a transmitting device or a receiving device. In Table 2, the amount of frequency shift is expressed by frequency stability. In Table 3, the amount of frequency shift is expressed by frequency. In Tables 2 and 3, "Target device" refers to a transmitting device. In Tables 2 and 3, "Opponent device" refers to a receiving device. "Base station" in Tables 2 and 3 corresponds to "Base station" in Table 1. "Mobile station" in Tables 2 and 3 corresponds to a mobile station with an average power of 1W or less as shown in Table 1.

[0079] [Table 2]

[0080] [Table 3]

[0081] When the target device (transmitter) is a base station, the frequency stability is ±0.2 [ppm] (see Table 1), and when the opposing device (receiver) is a base station, the frequency stability is ±1.5 (see Table 1). Therefore, as shown in Table 2, when both the target device and the opposing device are base stations, the range of frequency drift between the two base stations is -1.7 [ppm] to +1.7 [ppm].

[0082] When the receiving device is a base station, the frequency stability is ±2.5 (see Table 1). Therefore, as shown in Table 2, when the target device is a base station and the receiving device is a mobile station, the range of frequency drift between the base station and the mobile station is -2.7 [ppm] to +2.7 [ppm].

[0083] When the target device (transmitter) is a mobile station, the frequency stability is ±1.3 + A [ppm] (see Table 1). The reference base station that the mobile station's frequency reference follows corresponds to the base station applied to the transmitter. Therefore, when the target device is a mobile station, "A" in the frequency stability is ±0.2 [ppm] (see Table 1). Thus, as shown in Table 2, when the target device is a mobile station and the opposing device is a base station, the range of frequency drift between the mobile station and the base station is -3.0 [ppm] to +3.0 [ppm].

[0084] As shown in Table 2, when both the target device and the opposing device are mobile stations, the range of frequency difference between the two mobile stations is from -4.0 [ppm] to +4.0 [ppm].

[0085] If the opposing device is a base station, the set frequencies for the carrier signal of the target device and the local signal of the opposing device should be, for example, 275 MHz. If the opposing device is a mobile station, the set frequencies for the carrier signal of the target device and the local signal of the opposing device should be, for example, 266 MHz.

[0086] In this case, as shown in Table 3, if both the target device and the opposing device are base stations, the range of frequency difference between the two base stations is -467[Hz] to +467[Hz] (=275[MHz] × ±1.7[ppm]). If the target device is a base station and the opposing device is a mobile station, the range of frequency difference between the base station and the mobile station is -718[Hz] to +718[Hz] (=266[MHz] × ±2.7[ppm]). If the target device is a mobile station and the opposing device is a base station, the range of frequency difference between the mobile station and the base station is -825[Hz] to +825[Hz] (=275[MHz] × ±3.0[ppm]). If both the target device and the opposing device are mobile stations, the range of frequency difference between the two mobile stations is -1064[Hz] to +1064[Hz] (=266[MHz] × ±4.0[ppm]). Each value shown in Table 3 represents the maximum amount of frequency deviation, and therefore corresponds to an example of the maximum oscillation frequency difference fmax.

[0087] For communication between radio stations such as base stations and mobile stations, it is sufficient to detect and correct the frequency deviation (frequency error) within the range shown in Table 3. In reality, it is necessary to detect the frequency deviation over a wider range than that shown in Table 3, taking into account factors such as the aging of the reference oscillator installed at each radio station. However, in this embodiment, for the sake of explanation, other factors such as aging are not considered.

[0088] Incidentally, the range of frequency shift detectable by AFC processing corresponds to 1 / 4 of the symbol rate. For example, if the symbol rate is 4.8 [ksp], the range of frequency shift detectable by AFC is ±1200 [Hz]. This ±1200 [Hz] corresponds to an example of the maximum value flim of the frequency correction value fcrt2.

[0089] As shown in equation (6) above, the threshold fth used in the synchronization word determination unit 14 to determine whether or not pseudo-synchronization determination is necessary is the value obtained by subtracting the maximum value of the frequency shift that can occur between the carrier signal oscillated in the digital transmitter and the local signal in the digital receiver from the maximum value of the frequency shift that can be detected by AFC processing. Therefore, the threshold fth in this embodiment is the value obtained by subtracting each of the values ​​shown in Table 3 from ±1200 Hz. Table 4 shows the threshold fth in this embodiment.

[0090] [Table 4]

[0091] As shown in Table 4, when both the target device and the opposing device are base stations, the threshold fth is ±733[Hz] (=±1200[Hz]-±467[Hz]). That is, the positive threshold fth is +733[Hz] and the negative threshold fth is -733[Hz]. When the target device is a base station and the opposing device is a mobile station, the threshold fth is ±482[Hz] (=±1200[Hz]-±718[Hz]). That is, the positive threshold fth is +482[Hz] and the negative threshold fth is -482[Hz]. When the target device is a mobile station and the opposing device is a base station, the threshold fth is ±375[Hz] (=±1200[Hz]-±825[Hz]). That is, the positive threshold fth is +375[Hz] and the negative threshold fth is -375[Hz]. If both the target device and the opposing device are mobile stations, the threshold fth will be ±136[Hz] (=±1200[Hz]-±1064[Hz]). That is, the positive threshold fth will be +136[Hz] and the negative threshold fth will be -136[Hz].

[0092] If the frequency correction value fcrt1 detected by the frequency correction value detection unit 135 (see Figure 1) or the frequency correction value fcrt2 obtained by correcting the frequency correction value fcrt1 in the pseudo-frequency correction unit 151 (see Figure 1) is within the range of the threshold fth shown in Table 4 (excluding the values ​​at both ends of the range), the synchronization word determination unit 14 (see Figure 1) does not need to perform pseudo-synchronization determination.

[0093] In ARIB-STD T61, the frequency of the phase-shifted modulation signal differs depending on whether it is transmitted from a base station or a mobile station. Therefore, the digital receiver 1A in this embodiment may switch the threshold values ​​shown in Table 4 depending on what kind of radio station (i.e., base station or mobile station) it is waiting for signals from (at what frequency it is waiting). In other words, the threshold value fth may be set to different values ​​according to the specifications of the digital transmitter 2 and the digital receiver 1A, respectively. Here, these specifications include the specifications of the wireless communication system in which the digital transmitter 2 and the digital receiver 1A are installed (in this embodiment, ARIB-STD T61), and the type of radio station, such as a mobile station or a base station. In this way, by setting the threshold value fth in the range in which the pseudo-synchronization determination is performed, the digital receiver 1A can limit the frequency range in which the pseudo-synchronization determination is performed on the detected frequency correction value fcrt2 to a predetermined frequency range instead of the entire frequency range. This makes it possible for the digital receiver 1A to reduce false detections of pseudo-synchronization determination.

[0094] As described above, the pseudo-synchronous detection device 15 according to this embodiment is provided in a digital receiver 1A that receives a phase-shifted modulation signal Spsk transmitted by a digital transmitter 2, and decodes data from the I signal Si and Q signal Sq obtained by synchronously detecting and demodulating the phase-shifted modulation signal Spsk. The pseudo-synchronous detection device 15 includes a pseudo-frequency correction unit 151 that corrects the frequency correction value fcrt2 detected based on the I signal Si and Q signal Sq to a frequency corresponding to the normal frequency when pseudo-synchronous detection occurs, and a pseudo-synchronous determination unit 152 that determines whether or not a pseudo-synchronous determination is necessary to determine whether or not a pseudo-synchronous state is in place using the decoded data.

[0095] Furthermore, the digital receiving device 1A according to this embodiment includes an antenna 11 that receives a phase-shifted modulation signal Spsk transmitted by the digital transmitting device 2, a demodulation unit 12 that synchronously detects the phase-shifted modulation signal Spsk and demodulates the I signal Si and the Q signal Sq, a decoding unit 13 that decodes data from the I signal Si and the Q signal Sq, and a pseudo-synchronous detection device 15 according to this embodiment.

[0096] A pseudo-synchronization detection device 15 and a digital receiver 1A having such a configuration can reduce the probability of falsely detecting a pseudo-synchronization state and improve the pull-in speed.

[0097] [Second Embodiment] 2-1. Configuration of the pseudo-synchronization detection device and the digital receiver: A pseudo-synchronous detection device and a digital receiver according to a second embodiment of the present invention will be described with reference to Figure 3. Figure 3 is a block diagram illustrating the schematic configuration of the pseudo-synchronous detection device 15 and the digital receiver 1B according to this embodiment. In Figure 3, for ease of understanding, the digital receiver 1B and the digital transmitter 2 that transmits and receives the phase-shifted modulation signal Spsk are shown. With regard to the respective components of the pseudo-synchronous detection device 15 and the digital receiver 1B according to this embodiment, components that perform the same operation and function as the respective components of the pseudo-synchronous detection device 15 and the digital receiver 1A according to the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0098] The pseudo-synchronization detection device 15 according to this embodiment has the same configuration as the pseudo-synchronization detection device 15 according to the first embodiment and performs the same functions. The digital receiver 1B according to this embodiment is characterized in that it is equipped with a pseudo-synchronization detection unit 16 instead of the synchronization word determination unit 14 provided in the digital receiver 1A according to the first embodiment.

[0099] As shown in Figure 3, the digital receiver 1B includes a pseudo-synchronous detection unit 16. One of the two inputs of the pseudo-synchronous detection unit 16 is connected to the output of the decoding processing unit 134. The other of the two inputs of the pseudo-synchronous detection unit 16 is connected to the output of the pseudo-synchronous determination unit 152. One of the two outputs of the pseudo-synchronous detection unit 16 is connected to a subsequent stage (not shown). The other of the two outputs of the pseudo-synchronous detection unit 16 is connected to the other input of the pseudo-frequency correction unit 151.

[0100] The pseudo-synchronization detection unit 16 performs a pseudo-synchronization determination to determine whether the decoded data Dd, which is the data decoded by the decoding unit, matches a pseudo-synchronization-modified synchronization word, which is a modified version of a predetermined regular synchronization word. Specifically, the pseudo-synchronization detection unit 16 detects that a pseudo-synchronization state exists if the degree of agreement between the decoded synchronization word contained in the decoded data Dd and the pseudo-synchronization-modified synchronization word is greater than or equal to a predetermined value. On the other hand, the pseudo-synchronization detection unit 16 does not detect that a pseudo-synchronization state exists if the degree of agreement between the decoded synchronization word and the pseudo-synchronization-modified synchronization word is lower than the predetermined value.

[0101] The pseudo-synchronous detection unit 16 outputs a pseudo-synchronous determination signal Ps to the pseudo-frequency correction unit 151 when it detects that the digital receiver 1B is in a pseudo-synchronous state. On the other hand, the pseudo-synchronous detection unit 16 does not output a pseudo-synchronous determination signal Ps to the pseudo-frequency correction unit 151 when it does not detect that the digital receiver 1B is in a pseudo-synchronous state. As a result, the pseudo-frequency correction unit 151 in this embodiment can operate in the same way as the pseudo-frequency correction unit 151 in the first embodiment, depending on whether or not a pseudo-synchronous determination signal Ps is input.

[0102] The pseudo-synchronization detection unit 16 does not perform pseudo-synchronization determination if the pseudo-synchronization determination unit 152 has determined that pseudo-synchronization determination is unnecessary. Specifically, if the pseudo-synchronization detection unit 16 receives a pseudo-synchronization determination signal Psd from the pseudo-synchronization determination unit 152, it does not perform pseudo-synchronization determination even if decoded data Dd is input in the synchronization detection of the next symbol. As a result, the pseudo-synchronization detection unit 16 does not perform pseudo-synchronization determination in frequency ranges where a pseudo-synchronization state does not occur, so the digital receiver 1B can reduce the probability of falsely detecting a pseudo-synchronization state, similar to the digital receiver 1A according to the first embodiment.

[0103] If the pseudo-synchronization detection unit 16 determines that a pseudo-synchronization state is present, it discards the decoded data Dd as invalid data and does not output a decoded signal Ds to the subsequent stage. On the other hand, if the pseudo-synchronization detection unit 16 does not determine that a pseudo-synchronization state is present, it outputs the decoded data Dd input from the decoded processing unit 134 as a decoded signal Ds to the subsequent stage.

[0104] In this embodiment, the frequency correction value fcrt2 input to the phase correction unit 131 is generated by correcting the frequency correction value fcrt1 when pseudo-synchronous detection occurs, and therefore reflects the pseudo-synchronous detection from one symbol prior. Based on the frequency correction value fcrt2, which reflects the pseudo-synchronous detection from one symbol prior, the phase correction unit 131 corrects the phase of the I data Di1 and Q data Dq1 input from the A / D converters 125 and 126. Therefore, when the pseudo-synchronous detection unit 16 detects that a pseudo-synchronous state exists in the pseudo-synchronous determination, the phase correction unit 131 executes automatic frequency control (AFC) according to the pseudo-synchronous modified synchronous word and corrects the phases of the I data Di1 based on the I signal Si and the Q data Dq1 based on the Q signal Sq, respectively.

[0105] 2-2. Operation of the pseudo-synchronization detection device and the digital receiver: The pseudo-synchronous detection device 15 according to this embodiment has the same configuration as the pseudo-synchronous detection device 15 according to the first embodiment and performs the same functions, and therefore operates in the same manner as the pseudo-synchronous detection device 15 according to the first embodiment. The digital receiver 1B in this embodiment operates in the same manner as the digital receiver 1A according to the first embodiment, except that the pseudo-synchronous detection unit 16 does not perform a normal synchronization determination. For this reason, a description of the operation of the pseudo-synchronous detection device 15 and the digital receiver 1B according to this embodiment will be omitted.

[0106] As described above, the pseudo-synchronous detection device 15 according to this embodiment is provided in a digital receiver 1A that receives a phase-shifted modulation signal Spsk transmitted by a digital transmitter 2, and decodes data from the I signal Si and Q signal Sq obtained by synchronously detecting and demodulating the phase-shifted modulation signal Spsk. The pseudo-synchronous detection device 15 includes a pseudo-frequency correction unit 151 that corrects the frequency correction value fcrt2 detected based on the I signal Si and Q signal Sq to a frequency corresponding to the normal frequency when pseudo-synchronous detection occurs, and a pseudo-synchronous determination unit 152 that determines whether or not a pseudo-synchronous determination is necessary to determine whether or not a pseudo-synchronous state is in place using the decoded data.

[0107] Furthermore, the digital receiving device 1B according to this embodiment includes an antenna 11 that receives a phase-shifted modulation signal Spsk transmitted by the digital transmitting device 2, a demodulation unit 12 that synchronously detects the phase-shifted modulation signal Spsk and demodulates the I signal Si and the Q signal Sq, a decoding unit 13 that decodes data from the I signal Si and the Q signal Sq, and a pseudo-synchronous detection device 15 according to this embodiment.

[0108] A pseudo-synchronization detection device 15 and a digital receiver 1B having such a configuration can reduce the probability of falsely detecting a pseudo-synchronization state and improve the pull-in speed.

[0109] The present invention is not limited to the embodiments described above, and various modifications are possible. In the first embodiment described above, the synchronization word determination unit 14 and the phase correction unit 131 may be configured to have a first period set as the period after the synchronization word determination unit 14 determines that a pseudo-synchronization state is in place in the pseudo-synchronization determination and the phase correction unit 131 corrects the phases of the I data Di1 and Q data Dq1, respectively. During this first period, the synchronization word determination unit 14 does not perform the pseudo-synchronization determination until it determines that a normal synchronization state is in place in the normal synchronization determination, and the phase correction unit 131 does not need to correct the phases of the I data Di1 and Q data Dq1, respectively. As a result, the digital receiver 1A can reduce the continuous false detection of a pseudo-synchronization state during the normal frequency pull-in process for a predetermined period after the start of reception of the phase-shifted modulation signal Spsk.

[0110] In the first embodiment described above, the frequency correction value detection unit 135 may have a second period set as the elapsed time since the digital receiver 1A started receiving the phase shift modulation signal Spsk. If the synchronization word determination unit 14 does not determine that the system is in a normal synchronization state in the normal synchronization determination even after the second period has elapsed, the frequency correction value detection unit 135 may reset the frequency correction value fcrt1 (for example, set the frequency correction value fcrt1 to 0). This allows the digital receiver 1A to periodically reset the AFC processing, thereby reducing the likelihood of continuous false detection of a pseudo-synchronization state within the range of frequency correction values ​​for which pseudo-synchronization determination is not performed. [Explanation of Symbols]

[0111] 1A, 1B Digital Receiver 2. Digital Transmitter 11 Antennas 12 Demodulation section 13 Decoding section 14 Synchronized word determination unit 15. Pseudo-Synchronization Detection Device 16. Pseudo-Synchronization Detection Unit 121 Local Oscillator 122 90-degree phase shifter 123,124 Mixer 125,126 A / D converters 131 Phase correction section 132 Digital filter section 133 Symbol data acquisition unit 134 Decoding Processing Unit 135 Frequency Correction Value Detection Unit 151 Pseudo-frequency correction unit 152 Pseudo synchronization judgment decision unit Dd decoded data Di1, Di2, Di3 I data Dq1, Dq2, Dq3 Q data Ds decoded signal fcrt1, fcrt2 frequency correction values flim maximum fmax Maximum oscillation frequency difference fth threshold Ps Pseudo synchronization judgment signal Psd Pseudo synchronization judgment decision signal Si I signal SPSK Phase-Shift Modulated Signal Sq Q signal Xk,Yk Received Symbol Data

Claims

1. A pseudo-synchronous detection device provided in a digital receiving device that receives a phase-shifted modulation signal transmitted by a digital transmitting device and decodes data from the I signal and Q signal obtained by synchronously detecting and demodulating the phase-shifted modulation signal, A pseudo-frequency correction unit corrects the frequency correction value detected based on the I signal and the Q signal to a frequency equivalent to the normal frequency when pseudo-synchronization is detected. A pseudo-synchronization determination unit determines whether or not a pseudo-synchronization determination is necessary to determine whether or not a pseudo-synchronization state is in place using the decoded data. A pseudo-synchronous detection device characterized by comprising the following:

2. The pseudo-synchronization determination unit determines whether the pseudo-synchronization determination is necessary or unnecessary based on the frequency correction value. The pseudo-synchronous detection device according to claim 1, characterized by the following:

3. The pseudo-synchronization determination unit determines whether the pseudo-synchronization determination is necessary or unnecessary based on a threshold value derived from the maximum oscillation frequency difference between the reference oscillator provided in the digital transmitting device and the reference oscillator provided in the digital receiving device. The pseudo-synchronous detection device according to claim 1, characterized by the following:

4. If the maximum value of the frequency correction value is flim, the maximum oscillation frequency difference is fmax, the frequency correction value is fcrt, and the threshold is fth, then the threshold is expressed by the following equation (1), and the pseudo-synchronization determination unit determines that the pseudo-synchronization determination is unnecessary if the following equation (2) is satisfied. The pseudo-synchronous detection device according to claim 3, characterized by the following: fth=flim-fmax...(1) -fth<fcrt<fth...(2)

5. If the maximum value of the frequency correction value is flim, the maximum oscillation frequency difference is fmax, the frequency correction value is fcrt, and the threshold value is fth, then the threshold value is expressed by the following equation (3), and the pseudo-synchronization determination unit determines that the pseudo-synchronization determination is necessary if the following equation (4) or equation (5) is satisfied. The pseudo-synchronous detection device according to claim 3, characterized by the following: fth=flim-fmax...(3) -flim≦fcrt≦-fth...(4) fth ≤ fcrt ≤ flim ... (5)

6. The threshold value is set to a different value depending on the specifications of the digital transmitting device and the digital receiving device, respectively. The pseudo-synchronous detection device according to claim 3, characterized by the following:

7. A receiving unit that receives a phase-shifted modulation signal transmitted by a digital transmission device, A demodulation unit that synchronously detects the phase-shifted modulation signal and demodulates the I signal and the Q signal, A decoding unit that decodes data from the I signal and the Q signal, A pseudo-synchronous detection device according to any one of claims 1 to 6 and A digital receiving device characterized by having the following features.

8. The system includes a synchronization word determination unit that performs a normal synchronization determination to determine whether or not the system is in a normal synchronization state, and the pseudo-synchronization determination. The aforementioned synchronization word determination unit, In the normal synchronization determination, it is determined whether the decoded data, which is the data decoded by the decoding unit, matches a predetermined normal synchronization word, and if the decoded data and the normal synchronization word match, it is determined that the normal synchronization state is achieved. In the pseudo-synchronization determination, it is determined whether the pseudo-synchronization-modified synchronization word, which is a modified version of the regular synchronization word, matches the decoded data, and if the pseudo-synchronization-modified synchronization word matches the decoded data, it is determined that the pseudo-synchronization state exists. If the pseudo-synchronization determination unit determines that the pseudo-synchronization determination is unnecessary, the pseudo-synchronization determination is not performed. A digital receiving device according to claim 7, characterized by the following:

9. The decoding unit includes a phase correction unit that corrects the phases of the I data based on the I signal and the Q data based on the Q signal, respectively, based on the frequency correction value input from the pseudo-frequency correction unit. A digital receiving device according to claim 8, characterized by the following:

10. In the first period after the synchronization word determination unit determines in the pseudo-synchronization determination that the pseudo-synchronization state is in place, and the phase correction unit corrects the phases of the I data and the Q data respectively, The synchronization word determination unit does not perform the pseudo-synchronization determination until it determines in the normal synchronization determination that the normal synchronization state is achieved. The phase correction unit does not correct the phases of the I data and the Q data. A digital receiving device according to claim 9, characterized by the following:

11. The system includes a frequency correction value detection unit that detects the aforementioned frequency correction value, If the frequency correction value detection unit does not determine that the synchronization word determination unit is in the normal synchronization state in the normal synchronization determination even after the second period has elapsed, the frequency correction value detection unit resets the frequency correction value. A digital receiving device according to claim 8, characterized by the following:

12. The system includes a pseudo-synchronization detection unit that performs a pseudo-synchronization determination to determine whether the decoded data, which is the data decoded by the decoding unit, matches a pseudo-synchronization modified synchronization word, which is a modified version of a predetermined regular synchronization word, and detects that the system is in a pseudo-synchronization state when the decoded data and the pseudo-synchronization modified synchronization word match. The pseudo-synchronization detection unit shall not perform the pseudo-synchronization determination if the pseudo-synchronization determination unit determines that the pseudo-synchronization determination is unnecessary. A digital receiving device according to claim 7, characterized by the following:

13. The decoding unit, when the pseudo-synchronization detection unit detects that the pseudo-synchronization state is in the pseudo-synchronization determination, has a phase correction unit that performs automatic frequency control according to the pseudo-synchronization modified synchronization word and corrects the phases of the I data based on the I signal and the Q data based on the Q signal. A digital receiving device according to claim 12, characterized by the following:

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